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-- NEED RESULT: ARCH00071.P1: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P2: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P3: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P4: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P5: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P6: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P7: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P8: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P9: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P10: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P11: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P12: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P13: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P14: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P15: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P16: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071.P17: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00071: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: P17: Transport transactions entirely completed passed -- NEED RESULT: P16: Transport transactions entirely completed passed -- NEED RESULT: P15: Transport transactions entirely completed passed -- NEED RESULT: P14: Transport transactions entirely completed passed -- NEED RESULT: P13: Transport transactions entirely completed passed -- NEED RESULT: P12: Transport transactions entirely completed passed -- NEED RESULT: P11: Transport transactions entirely completed passed -- NEED RESULT: P10: Transport transactions entirely completed passed -- NEED RESULT: P9: Transport transactions entirely completed passed -- NEED RESULT: P8: Transport transactions entirely completed passed -- NEED RESULT: P7: Transport transactions entirely completed passed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00071 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00071) -- ENT00071_Test_Bench(ARCH00071_Test_Bench) -- -- REVISION HISTORY: -- -- 06-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00071 of E00000 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_boolean : chk_sig_type := -1 ; signal chk_bit : chk_sig_type := -1 ; signal chk_severity_level : chk_sig_type := -1 ; signal chk_character : chk_sig_type := -1 ; signal chk_st_enum1 : chk_sig_type := -1 ; signal chk_integer : chk_sig_type := -1 ; signal chk_st_int1 : chk_sig_type := -1 ; signal chk_time : chk_sig_type := -1 ; signal chk_st_phys1 : chk_sig_type := -1 ; signal chk_real : chk_sig_type := -1 ; signal chk_st_real1 : chk_sig_type := -1 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- signal s_boolean : boolean := c_boolean_1 ; signal s_bit : bit := c_bit_1 ; signal s_severity_level : severity_level := c_severity_level_1 ; signal s_character : character := c_character_1 ; signal s_st_enum1 : st_enum1 := c_st_enum1_1 ; signal s_integer : integer := c_integer_1 ; signal s_st_int1 : st_int1 := c_st_int1_1 ; signal s_time : time := c_time_1 ; signal s_st_phys1 : st_phys1 := c_st_phys1_1 ; signal s_real : real := c_real_1 ; signal s_st_real1 : st_real1 := c_st_real1_1 ; signal s_st_rec1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3 : st_arr3 := c_st_arr3_1 ; -- begin PGEN_CHKP_1 : process ( chk_boolean ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_boolean = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_boolean ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_boolean <= transport c_boolean_2 after 10 ns, c_boolean_1 after 20 ns ; -- when 1 => correct := s_boolean = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_boolean = c_boolean_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P1" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_boolean <= transport c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns ; -- when 3 => correct := s_boolean = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; s_boolean <= transport c_boolean_1 after 5 ns ; -- when 4 => correct := correct and s_boolean = c_boolean_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_boolean <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P1 ; -- PGEN_CHKP_2 : process ( chk_bit ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_bit = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_bit ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_bit <= transport c_bit_2 after 10 ns, c_bit_1 after 20 ns ; -- when 1 => correct := s_bit = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_bit = c_bit_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P2" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_bit <= transport c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns ; -- when 3 => correct := s_bit = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; s_bit <= transport c_bit_1 after 5 ns ; -- when 4 => correct := correct and s_bit = c_bit_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_bit <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P2 ; -- PGEN_CHKP_3 : process ( chk_severity_level ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_severity_level = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_severity_level ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_severity_level <= transport c_severity_level_2 after 10 ns, c_severity_level_1 after 20 ns ; -- when 1 => correct := s_severity_level = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_severity_level = c_severity_level_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P3" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_severity_level <= transport c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns ; -- when 3 => correct := s_severity_level = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; s_severity_level <= transport c_severity_level_1 after 5 ns ; -- when 4 => correct := correct and s_severity_level = c_severity_level_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_severity_level <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P3 ; -- PGEN_CHKP_4 : process ( chk_character ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_character = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process ( s_character ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_character <= transport c_character_2 after 10 ns, c_character_1 after 20 ns ; -- when 1 => correct := s_character = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_character = c_character_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P4" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_character <= transport c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns ; -- when 3 => correct := s_character = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; s_character <= transport c_character_1 after 5 ns ; -- when 4 => correct := correct and s_character = c_character_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_character <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P4 ; -- PGEN_CHKP_5 : process ( chk_st_enum1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_st_enum1 = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process ( s_st_enum1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_enum1 <= transport c_st_enum1_2 after 10 ns, c_st_enum1_1 after 20 ns ; -- when 1 => correct := s_st_enum1 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1 = c_st_enum1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P5" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_enum1 <= transport c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns ; -- when 3 => correct := s_st_enum1 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_enum1 <= transport c_st_enum1_1 after 5 ns ; -- when 4 => correct := correct and s_st_enum1 = c_st_enum1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_enum1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P5 ; -- PGEN_CHKP_6 : process ( chk_integer ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_integer = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process ( s_integer ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_integer <= transport c_integer_2 after 10 ns, c_integer_1 after 20 ns ; -- when 1 => correct := s_integer = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_integer = c_integer_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P6" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_integer <= transport c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns ; -- when 3 => correct := s_integer = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; s_integer <= transport c_integer_1 after 5 ns ; -- when 4 => correct := correct and s_integer = c_integer_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_integer <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P6 ; -- PGEN_CHKP_7 : process ( chk_st_int1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions entirely completed", chk_st_int1 = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- P7 : process ( s_st_int1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_int1 <= transport c_st_int1_2 after 10 ns, c_st_int1_1 after 20 ns ; -- when 1 => correct := s_st_int1 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1 = c_st_int1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P7" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_int1 <= transport c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns ; -- when 3 => correct := s_st_int1 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_int1 <= transport c_st_int1_1 after 5 ns ; -- when 4 => correct := correct and s_st_int1 = c_st_int1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_int1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P7 ; -- PGEN_CHKP_8 : process ( chk_time ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions entirely completed", chk_time = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- P8 : process ( s_time ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_time <= transport c_time_2 after 10 ns, c_time_1 after 20 ns ; -- when 1 => correct := s_time = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_time = c_time_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P8" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_time <= transport c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns ; -- when 3 => correct := s_time = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; s_time <= transport c_time_1 after 5 ns ; -- when 4 => correct := correct and s_time = c_time_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_time <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P8 ; -- PGEN_CHKP_9 : process ( chk_st_phys1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions entirely completed", chk_st_phys1 = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- P9 : process ( s_st_phys1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_phys1 <= transport c_st_phys1_2 after 10 ns, c_st_phys1_1 after 20 ns ; -- when 1 => correct := s_st_phys1 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1 = c_st_phys1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P9" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_phys1 <= transport c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns ; -- when 3 => correct := s_st_phys1 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_phys1 <= transport c_st_phys1_1 after 5 ns ; -- when 4 => correct := correct and s_st_phys1 = c_st_phys1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_phys1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P9 ; -- PGEN_CHKP_10 : process ( chk_real ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Transport transactions entirely completed", chk_real = 4 ) ; end if ; end process PGEN_CHKP_10 ; -- P10 : process ( s_real ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_real <= transport c_real_2 after 10 ns, c_real_1 after 20 ns ; -- when 1 => correct := s_real = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_real = c_real_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P10" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_real <= transport c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns ; -- when 3 => correct := s_real = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; s_real <= transport c_real_1 after 5 ns ; -- when 4 => correct := correct and s_real = c_real_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_real <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P10 ; -- PGEN_CHKP_11 : process ( chk_st_real1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Transport transactions entirely completed", chk_st_real1 = 4 ) ; end if ; end process PGEN_CHKP_11 ; -- P11 : process ( s_st_real1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_real1 <= transport c_st_real1_2 after 10 ns, c_st_real1_1 after 20 ns ; -- when 1 => correct := s_st_real1 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1 = c_st_real1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P11" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_real1 <= transport c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns ; -- when 3 => correct := s_st_real1 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_real1 <= transport c_st_real1_1 after 5 ns ; -- when 4 => correct := correct and s_st_real1 = c_st_real1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_real1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P11 ; -- PGEN_CHKP_12 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Transport transactions entirely completed", chk_st_rec1 = 4 ) ; end if ; end process PGEN_CHKP_12 ; -- P12 : process ( s_st_rec1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec1 <= transport c_st_rec1_2 after 10 ns, c_st_rec1_1 after 20 ns ; -- when 1 => correct := s_st_rec1 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1 = c_st_rec1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P12" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec1 <= transport c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns ; -- when 3 => correct := s_st_rec1 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec1 <= transport c_st_rec1_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec1 = c_st_rec1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P12 ; -- PGEN_CHKP_13 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Transport transactions entirely completed", chk_st_rec2 = 4 ) ; end if ; end process PGEN_CHKP_13 ; -- P13 : process ( s_st_rec2 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec2 <= transport c_st_rec2_2 after 10 ns, c_st_rec2_1 after 20 ns ; -- when 1 => correct := s_st_rec2 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2 = c_st_rec2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P13" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec2 <= transport c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns ; -- when 3 => correct := s_st_rec2 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec2 <= transport c_st_rec2_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec2 = c_st_rec2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P13 ; -- PGEN_CHKP_14 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Transport transactions entirely completed", chk_st_rec3 = 4 ) ; end if ; end process PGEN_CHKP_14 ; -- P14 : process ( s_st_rec3 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec3 <= transport c_st_rec3_2 after 10 ns, c_st_rec3_1 after 20 ns ; -- when 1 => correct := s_st_rec3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3 = c_st_rec3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P14" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec3 <= transport c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns ; -- when 3 => correct := s_st_rec3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec3 <= transport c_st_rec3_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec3 = c_st_rec3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P14 ; -- PGEN_CHKP_15 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Transport transactions entirely completed", chk_st_arr1 = 4 ) ; end if ; end process PGEN_CHKP_15 ; -- P15 : process ( s_st_arr1 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr1 <= transport c_st_arr1_2 after 10 ns, c_st_arr1_1 after 20 ns ; -- when 1 => correct := s_st_arr1 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1 = c_st_arr1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P15" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr1 <= transport c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns ; -- when 3 => correct := s_st_arr1 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1 <= transport c_st_arr1_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr1 = c_st_arr1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P15 ; -- PGEN_CHKP_16 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Transport transactions entirely completed", chk_st_arr2 = 4 ) ; end if ; end process PGEN_CHKP_16 ; -- P16 : process ( s_st_arr2 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr2 <= transport c_st_arr2_2 after 10 ns, c_st_arr2_1 after 20 ns ; -- when 1 => correct := s_st_arr2 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2 = c_st_arr2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P16" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr2 <= transport c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns ; -- when 3 => correct := s_st_arr2 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2 <= transport c_st_arr2_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr2 = c_st_arr2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P16 ; -- PGEN_CHKP_17 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Transport transactions entirely completed", chk_st_arr3 = 4 ) ; end if ; end process PGEN_CHKP_17 ; -- P17 : process ( s_st_arr3 ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_arr3 <= transport c_st_arr3_2 after 10 ns, c_st_arr3_1 after 20 ns ; -- when 1 => correct := s_st_arr3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3 = c_st_arr3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00071.P17" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr3 <= transport c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns ; -- when 3 => correct := s_st_arr3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3 <= transport c_st_arr3_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr3 = c_st_arr3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00071" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00071" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P17 ; -- -- end ARCH00071 ; -- entity ENT00071_Test_Bench is end ENT00071_Test_Bench ; -- architecture ARCH00071_Test_Bench of ENT00071_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00071 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00071_Test_Bench ;
-- $Id: rb_sres_or_3.vhd 1181 2019-07-08 17:00:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> -- ------------------------------------------------------------------------------ -- Module Name: rb_sres_or_3 - syn -- Description: rbus result or, 3 input -- -- Dependencies: rb_sres_or_mon [sim only] -- Test bench: - -- Target Devices: generic -- Tool versions: ise 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- -- Revision History: -- Date Rev Version Comment -- 2010-12-04 343 1.1.1 use now rb_sres_or_mon -- 2010-06-26 309 1.1 add rritb_sres_or_mon -- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_ -- 2008-01-20 113 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use work.slvtypes.all; use work.rblib.all; -- ---------------------------------------------------------------------------- entity rb_sres_or_3 is -- rbus result or, 3 input port ( RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output ); end rb_sres_or_3; architecture syn of rb_sres_or_3 is begin proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3) begin RB_SRES_OR.ack <= RB_SRES_1.ack or RB_SRES_2.ack or RB_SRES_3.ack; RB_SRES_OR.busy <= RB_SRES_1.busy or RB_SRES_2.busy or RB_SRES_3.busy; RB_SRES_OR.err <= RB_SRES_1.err or RB_SRES_2.err or RB_SRES_3.err; RB_SRES_OR.dout <= RB_SRES_1.dout or RB_SRES_2.dout or RB_SRES_3.dout; end process proc_comb; -- synthesis translate_off ORMON : rb_sres_or_mon port map ( RB_SRES_1 => RB_SRES_1, RB_SRES_2 => RB_SRES_2, RB_SRES_3 => RB_SRES_3, RB_SRES_4 => rb_sres_init ); -- synthesis translate_on end syn;
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3e/icvyHXeRZz9uKyU0fpBVGCNenLsayC3J/1y4AM/Nnr8t+3A== `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block IVdhbAqIZuXqh+/r/SQDX1SlfzXrQo1kAZUmc7CyFUL+WtfySYG3i7tLm5C4yLs7O1nAFCG/ySRD KQZ6P+9oIg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block f3Vm6A7nFUJ3AkFKQuW4QZOMfCwFkGp7LLnxhDZa5phMGUPMMjlhgYjJxI7ZGnau2knjvOyPgOTr p+opUCLjAs2H2pO2YzoLpaj0g7g9VHOOMOkf+zq42eOnNjScOHY3zhHDQ14KKfho17iZkE0dDZVd GRqhEaAyw5OtaZC92gM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block IVdhbAqIZuXqh+/r/SQDX1SlfzXrQo1kAZUmc7CyFUL+WtfySYG3i7tLm5C4yLs7O1nAFCG/ySRD KQZ6P+9oIg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block f3Vm6A7nFUJ3AkFKQuW4QZOMfCwFkGp7LLnxhDZa5phMGUPMMjlhgYjJxI7ZGnau2knjvOyPgOTr p+opUCLjAs2H2pO2YzoLpaj0g7g9VHOOMOkf+zq42eOnNjScOHY3zhHDQ14KKfho17iZkE0dDZVd GRqhEaAyw5OtaZC92gM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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3e/icvyHXeRZz9uKyU0fpBVGCNenLsayC3J/1y4AM/Nnr8t+3A== `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c Y2O4fk1xOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV FIedseAJGSJjdgeT43M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c Y2O4fk1xOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV FIedseAJGSJjdgeT43M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0 dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc mYqTUQDFFlehrx6Wh0E= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c Y2O4fk1xOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV FIedseAJGSJjdgeT43M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c Y2O4fk1xOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV FIedseAJGSJjdgeT43M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c Y2O4fk1xOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV FIedseAJGSJjdgeT43M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c Y2O4fk1xOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV FIedseAJGSJjdgeT43M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE ieee.std_logic_unsigned.all; ENTITY GreenDroidADDMPCore IS PORT ( i00 : IN std_logic_vector(31 DOWNTO 0); i01 : IN std_logic_vector(31 DOWNTO 0); r00 : OUT std_logic_vector(31 DOWNTO 0); r01 : OUT std_logic_vector(31 DOWNTO 0); FP : IN std_logic_vector(31 DOWNTO 0); FPout : OUT std_logic_vector(31 DOWNTO 0); M_ADDR : OUT std_logic_vector(31 DOWNTO 0); M_DATA : INOUT std_logic_vector(31 DOWNTO 0); M_RD : INOUT std_logic; M_WR : INOUT std_logic; M_RDY : IN std_logic; reset : IN std_logic; CLK : IN std_logic ); END ENTITY; ARCHITECTURE Behavioural OF GreenDroidADDMPCore IS TYPE States IS (ST_INIT,WS_INIT,ST_RESET,ST00,WS00,ST_END); SIGNAL Mstate : States; BEGIN -- CONTROL PROCESS -------- PROCESS(clk,reset) BEGIN IF reset='1' THEN Mstate <= ST_RESET; ELSIF(rising_edge(clk)) THEN CASE Mstate IS WHEN ST_RESET => Mstate <= ST_INIT; WHEN ST_INIT => IF M_RDY='1' THEN Mstate <= ST00; ELSE Mstate <= WS_INIT; END IF; WHEN WS_INIT => IF M_RDY='1' THEN Mstate <= ST00; END IF; WHEN ST00 | WS00| ST_END => WHEN OTHERS => END CASE; END IF; END PROCESS; -- EXECUTE PROCESS -------- PROCESS(clk,reset) VARIABLE T,s0,s1,s2,s3,s4,s5,s6,s7,fpi :std_logic_vector(31 DOWNTO 0); BEGIN IF(reset='1') THEN -- reset any internal states -- s0 := (OTHERS=>'0'); s1 := (OTHERS=>'0'); s2 := (OTHERS=>'0'); s3 := (OTHERS=>'0'); s4 := (OTHERS=>'0'); s5 := (OTHERS=>'0'); s6 := (OTHERS=>'0'); s7 := (OTHERS=>'0'); fpi:=(OTHERS=>'0'); M_ADDR <= (OTHERS=>'Z'); M_DATA <= (OTHERS=>'Z'); M_RD <= 'Z'; M_WR <= 'Z'; ELSIF(rising_edge(clk)) THEN M_DATA <="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; CASE Mstate IS WHEN ST_INIT => -- connect 2 input params here -- s0 := i00; s1 := i01; fpi := FP; --add ; s0:=s0+s1 ; s1 := s2; s2 := s3; s3 := s4; s4 := s5; s5 := s6; s6 := s7; --copy1 ; s7 := s6; s6 := s5; s5 := s4; s4 := s3; s3 := s2; s2 := s1; s1 := s0; -- recover 2 results here -- r00 <= s0; r01 <= s1; FPout <= fpi; WHEN OTHERS => END CASE; END IF; END PROCESS; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 08:42:38 12/26/2015 -- Design Name: -- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_clockedround2.vhd -- Project Name: idea_rcs2 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: clockedround -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; ENTITY tb_clockedround2 IS END tb_clockedround2; ARCHITECTURE behavior OF tb_clockedround2 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT clockedround PORT( Clock : IN std_logic; Init : IN std_logic; Result : OUT std_logic; Trafo : IN std_logic; X1 : IN std_logic_vector(15 downto 0); X2 : IN std_logic_vector(15 downto 0); X3 : IN std_logic_vector(15 downto 0); X4 : IN std_logic_vector(15 downto 0); Z1 : IN std_logic_vector(15 downto 0); Z2 : IN std_logic_vector(15 downto 0); Z3 : IN std_logic_vector(15 downto 0); Z4 : IN std_logic_vector(15 downto 0); Z5 : IN std_logic_vector(15 downto 0); Z6 : IN std_logic_vector(15 downto 0); Y1 : OUT std_logic_vector(15 downto 0); Y2 : OUT std_logic_vector(15 downto 0); Y3 : OUT std_logic_vector(15 downto 0); Y4 : OUT std_logic_vector(15 downto 0); Y1_trafo : OUT std_logic_vector(15 downto 0); Y2_trafo : OUT std_logic_vector(15 downto 0); Y3_trafo : OUT std_logic_vector(15 downto 0); Y4_trafo : OUT std_logic_vector(15 downto 0) ); END COMPONENT; --Inputs signal Clock : std_logic := '0'; signal Init : std_logic := '0'; signal Trafo : std_logic := '0'; signal X1 : std_logic_vector(15 downto 0) := (others => '0'); signal X2 : std_logic_vector(15 downto 0) := (others => '0'); signal X3 : std_logic_vector(15 downto 0) := (others => '0'); signal X4 : std_logic_vector(15 downto 0) := (others => '0'); signal Z1 : std_logic_vector(15 downto 0) := (others => '0'); signal Z2 : std_logic_vector(15 downto 0) := (others => '0'); signal Z3 : std_logic_vector(15 downto 0) := (others => '0'); signal Z4 : std_logic_vector(15 downto 0) := (others => '0'); signal Z5 : std_logic_vector(15 downto 0) := (others => '0'); signal Z6 : std_logic_vector(15 downto 0) := (others => '0'); --Outputs signal Result : std_logic; signal Y1 : std_logic_vector(15 downto 0); signal Y2 : std_logic_vector(15 downto 0); signal Y3 : std_logic_vector(15 downto 0); signal Y4 : std_logic_vector(15 downto 0); signal Y1_trafo : std_logic_vector(15 downto 0); signal Y2_trafo : std_logic_vector(15 downto 0); signal Y3_trafo : std_logic_vector(15 downto 0); signal Y4_trafo : std_logic_vector(15 downto 0); -- Clock period definitions constant Clock_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: clockedround PORT MAP ( Clock => Clock, Init => Init, Result => Result, Trafo => Trafo, X1 => X1, X2 => X2, X3 => X3, X4 => X4, Z1 => Z1, Z2 => Z2, Z3 => Z3, Z4 => Z4, Z5 => Z5, Z6 => Z6, Y1 => Y1, Y2 => Y2, Y3 => Y3, Y4 => Y4, Y1_trafo => Y1_trafo, Y2_trafo => Y2_trafo, Y3_trafo => Y3_trafo, Y4_trafo => Y4_trafo ); -- Clock process definitions Clock_process :process begin Clock <= '0'; wait for Clock_period/2; Clock <= '1'; wait for Clock_period/2; end process; Z1 <= std_logic_vector(to_unsigned(1,16)); Z2 <= std_logic_vector(to_unsigned(2,16)); Z3 <= std_logic_vector(to_unsigned(3,16)); Z4 <= std_logic_vector(to_unsigned(4,16)); Z5 <= std_logic_vector(to_unsigned(5,16)); Z6 <= std_logic_vector(to_unsigned(6,16)); X1 <= std_logic_vector(to_unsigned(0,16)); X2 <= std_logic_vector(to_unsigned(1,16)); X3 <= std_logic_vector(to_unsigned(2,16)); X4 <= std_logic_vector(to_unsigned(3,16)); Trafo <= '0'; Init <= '0', '1' after 50 ns, '0' after 70 ns; END;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 08:42:38 12/26/2015 -- Design Name: -- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_clockedround2.vhd -- Project Name: idea_rcs2 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: clockedround -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; ENTITY tb_clockedround2 IS END tb_clockedround2; ARCHITECTURE behavior OF tb_clockedround2 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT clockedround PORT( Clock : IN std_logic; Init : IN std_logic; Result : OUT std_logic; Trafo : IN std_logic; X1 : IN std_logic_vector(15 downto 0); X2 : IN std_logic_vector(15 downto 0); X3 : IN std_logic_vector(15 downto 0); X4 : IN std_logic_vector(15 downto 0); Z1 : IN std_logic_vector(15 downto 0); Z2 : IN std_logic_vector(15 downto 0); Z3 : IN std_logic_vector(15 downto 0); Z4 : IN std_logic_vector(15 downto 0); Z5 : IN std_logic_vector(15 downto 0); Z6 : IN std_logic_vector(15 downto 0); Y1 : OUT std_logic_vector(15 downto 0); Y2 : OUT std_logic_vector(15 downto 0); Y3 : OUT std_logic_vector(15 downto 0); Y4 : OUT std_logic_vector(15 downto 0); Y1_trafo : OUT std_logic_vector(15 downto 0); Y2_trafo : OUT std_logic_vector(15 downto 0); Y3_trafo : OUT std_logic_vector(15 downto 0); Y4_trafo : OUT std_logic_vector(15 downto 0) ); END COMPONENT; --Inputs signal Clock : std_logic := '0'; signal Init : std_logic := '0'; signal Trafo : std_logic := '0'; signal X1 : std_logic_vector(15 downto 0) := (others => '0'); signal X2 : std_logic_vector(15 downto 0) := (others => '0'); signal X3 : std_logic_vector(15 downto 0) := (others => '0'); signal X4 : std_logic_vector(15 downto 0) := (others => '0'); signal Z1 : std_logic_vector(15 downto 0) := (others => '0'); signal Z2 : std_logic_vector(15 downto 0) := (others => '0'); signal Z3 : std_logic_vector(15 downto 0) := (others => '0'); signal Z4 : std_logic_vector(15 downto 0) := (others => '0'); signal Z5 : std_logic_vector(15 downto 0) := (others => '0'); signal Z6 : std_logic_vector(15 downto 0) := (others => '0'); --Outputs signal Result : std_logic; signal Y1 : std_logic_vector(15 downto 0); signal Y2 : std_logic_vector(15 downto 0); signal Y3 : std_logic_vector(15 downto 0); signal Y4 : std_logic_vector(15 downto 0); signal Y1_trafo : std_logic_vector(15 downto 0); signal Y2_trafo : std_logic_vector(15 downto 0); signal Y3_trafo : std_logic_vector(15 downto 0); signal Y4_trafo : std_logic_vector(15 downto 0); -- Clock period definitions constant Clock_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: clockedround PORT MAP ( Clock => Clock, Init => Init, Result => Result, Trafo => Trafo, X1 => X1, X2 => X2, X3 => X3, X4 => X4, Z1 => Z1, Z2 => Z2, Z3 => Z3, Z4 => Z4, Z5 => Z5, Z6 => Z6, Y1 => Y1, Y2 => Y2, Y3 => Y3, Y4 => Y4, Y1_trafo => Y1_trafo, Y2_trafo => Y2_trafo, Y3_trafo => Y3_trafo, Y4_trafo => Y4_trafo ); -- Clock process definitions Clock_process :process begin Clock <= '0'; wait for Clock_period/2; Clock <= '1'; wait for Clock_period/2; end process; Z1 <= std_logic_vector(to_unsigned(1,16)); Z2 <= std_logic_vector(to_unsigned(2,16)); Z3 <= std_logic_vector(to_unsigned(3,16)); Z4 <= std_logic_vector(to_unsigned(4,16)); Z5 <= std_logic_vector(to_unsigned(5,16)); Z6 <= std_logic_vector(to_unsigned(6,16)); X1 <= std_logic_vector(to_unsigned(0,16)); X2 <= std_logic_vector(to_unsigned(1,16)); X3 <= std_logic_vector(to_unsigned(2,16)); X4 <= std_logic_vector(to_unsigned(3,16)); Trafo <= '0'; Init <= '0', '1' after 50 ns, '0' after 70 ns; END;
-- ------------------------------------------------------------- -- -- Entity Declaration for inst_1_e -- -- Generated -- by: wig -- on: Fri Jul 15 13:54:30 2005 -- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_1_e-e.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $ -- $Date: 2005/07/15 16:20:01 $ -- $Log: inst_1_e-e.vhd,v $ -- Revision 1.2 2005/07/15 16:20:01 wig -- Update all testcases; still problems though -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_1_e -- entity inst_1_e is -- Generics: -- No Generated Generics for Entity inst_1_e -- Generated Port Declaration: -- No Generated Port for Entity inst_1_e end inst_1_e; -- -- End of Generated Entity inst_1_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
-------------------------------------------------------------------------------- -- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: P.49d -- \ \ Application: netgen -- / / Filename: sfifo_15x128.vhd -- /___/ /\ Timestamp: Thu Feb 21 12:25:57 2013 -- \ \ / \ -- \___\/\___\ -- -- Command : -w -sim -ofmt vhdl /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/sfifo_15x128.ngc /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/sfifo_15x128.vhd -- Device : 7a200tffg1156-2 -- Input file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/sfifo_15x128.ngc -- Output file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/sfifo_15x128.vhd -- # of Entities : 1 -- Design Name : sfifo_15x128 -- Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/ -- -- Purpose: -- This VHDL netlist is a verification model and uses simulation -- primitives which may not represent the true implementation of the -- device, however the netlist is functionally correct and should not -- be modified. This file cannot be synthesized and should only be used -- with supported simulation tools. -- -- Reference: -- Command Line Tools User Guide, Chapter 23 -- Synthesis and Simulation Design Guide, Chapter 6 -- -------------------------------------------------------------------------------- -- synthesis translate_off library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; use UNISIM.VPKG.ALL; entity sfifo_15x128 is port ( clk : in STD_LOGIC := 'X'; rst : in STD_LOGIC := 'X'; wr_en : in STD_LOGIC := 'X'; rd_en : in STD_LOGIC := 'X'; full : out STD_LOGIC; empty : out STD_LOGIC; prog_full : out STD_LOGIC; prog_empty : out STD_LOGIC; din : in STD_LOGIC_VECTOR ( 127 downto 0 ); dout : out STD_LOGIC_VECTOR ( 127 downto 0 ) ); end sfifo_15x128; architecture STRUCTURE of sfifo_15x128 is signal N1 : STD_LOGIC; signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_275 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC; signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i_279 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_408 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_409 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_GND_12_o_MUX_2_o : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_GND_12_o_MUX_1_o : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_567 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_568 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_569 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_570 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_571 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_572 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3_573 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1_574 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_1_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_2_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_3_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_4_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_wr_en_i_584 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_rd_en_i_585 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_1_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_2_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_3_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_lut_2_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_3_PWR_41_o_equal_7_o : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_1_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_2_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_3_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_4_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i_600 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i_601 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_1_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_2_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_3_Q : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o3_605 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o4_606 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o5_607 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o6_608 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb3_609 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb5_610 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i_rstpot_611 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot_612 : STD_LOGIC; signal N2 : STD_LOGIC; signal N5 : STD_LOGIC; signal N6 : STD_LOGIC; signal N8 : STD_LOGIC; signal N9 : STD_LOGIC; signal N10 : STD_LOGIC; signal N12 : STD_LOGIC; signal N14 : STD_LOGIC; signal N16 : STD_LOGIC; signal N17 : STD_LOGIC; signal N19 : STD_LOGIC; signal N21 : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_N0 : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_7_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_7_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC; signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC; signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 ); signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 ); signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 ); signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1 : STD_LOGIC_VECTOR ( 0 downto 0 ); signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count : STD_LOGIC_VECTOR ( 3 downto 1 ); signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1 : STD_LOGIC_VECTOR ( 0 downto 0 ); signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count : STD_LOGIC_VECTOR ( 3 downto 1 ); signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad : STD_LOGIC_VECTOR ( 4 downto 1 ); signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad : STD_LOGIC_VECTOR ( 4 downto 1 ); begin full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_275; empty <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i_279; prog_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i; prog_empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i; XST_GND : GND port map ( G => N1 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => rst, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3_573, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_409 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDP port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_GND_12_o_MUX_2_o, PRE => rst, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_569 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDP port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_GND_12_o_MUX_1_o, PRE => rst, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_572 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3 : FDP generic map( INIT => '1' ) port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_408, PRE => rst, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3_573 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD generic map( INIT => '0' ) port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_568, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_567 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD generic map( INIT => '0' ) port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_571, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_570 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2 : FDP generic map( INIT => '1' ) port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1_574, PRE => rst, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_408 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2 : FDP generic map( INIT => '1' ) port map ( C => clk, D => N1, PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0 : FDP generic map( INIT => '1' ) port map ( C => clk, D => N1, PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD generic map( INIT => '0' ) port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_569, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_568 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg_1 : FDP generic map( INIT => '1' ) port map ( C => clk, D => N1, PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD generic map( INIT => '0' ) port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_572, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_571 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1 : FDP generic map( INIT => '1' ) port map ( C => clk, D => N1, PRE => rst, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1_574 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP generic map( INIT => '1' ) port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o, PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i_279 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP generic map( INIT => '1' ) port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o, PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad_4 : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_4_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(4) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad_3 : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_3_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(3) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad_2 : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_2_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(2) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad_1 : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_1_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(1) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_wr_en_i : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_wr_en_i_584 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_rd_en_i : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_rd_en_i_585 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_3 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3), Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_2 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2), Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_1 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1), Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_0 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1(0), Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_3_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_2 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_2_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_1 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_1_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP generic map( INIT => '1' ) port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb, PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_408, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_275 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP generic map( INIT => '1' ) port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb, PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_408, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_4 : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_4_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(4) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_3 : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_3_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(3) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_2 : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_2_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(2) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_1 : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_1_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(1) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i_600 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i : FDC generic map( INIT => '0' ) port map ( C => clk, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i_601 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_3 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3), Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_2 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2), Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_1 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1), Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_0 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1(0), Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_3_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_2 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_2_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_1 : FDCE generic map( INIT => '0' ) port map ( C => clk, CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1), D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_1_Q, Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2 generic map( INIT => X"2" ) port map ( I0 => rd_en, I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2 generic map( INIT => X"2" ) port map ( I0 => wr_en, I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en1 : LUT3 generic map( INIT => X"F4" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278, I1 => rd_en, I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 : LUT2 generic map( INIT => X"2" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_569, I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_568, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_GND_12_o_MUX_2_o ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 : LUT2 generic map( INIT => X"2" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_572, I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_571, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_GND_12_o_MUX_1_o ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2 generic map( INIT => X"2" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_569, I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_567, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2 generic map( INIT => X"2" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_572, I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_570, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_3_PWR_41_o_equal_7_o_3_1 : LUT4 generic map( INIT => X"0080" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(4), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(3), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(2), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(1), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_3_PWR_41_o_equal_7_o ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_lut_2_1 : LUT2 generic map( INIT => X"9" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_lut_2_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o4 : LUT6 generic map( INIT => X"0A0ACECEFF0AFFCE" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o4_606 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o5 : LUT6 generic map( INIT => X"22F222F2FFFF22F2" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o5_607 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o6 : LUT4 generic map( INIT => X"4F44" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o6_608 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o7 : LUT6 generic map( INIT => X"FFFFFFFFAAAAA8AA" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278, I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o5_607, I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o6_608, I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o4_606, I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o3_605, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb5 : LUT6 generic map( INIT => X"FFFFFFFF4F44FFFF" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o5_607, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb5_610 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb7 : LUT5 generic map( INIT => X"FF44FF40" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_409, I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562, I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o4_606, I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb3_609, I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb5_610, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i : FDP generic map( INIT => '1' ) port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i_rstpot_611, PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q, Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i : FDP generic map( INIT => '1' ) port map ( C => clk, D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot_612, PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_408, Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot : LUT5 generic map( INIT => X"45440444" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_409, I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i, I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i_600, I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_3_PWR_41_o_equal_7_o, I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i_601, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot_612 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_xor_2_11 : LUT6 generic map( INIT => X"6696669696996696" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_2_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_2_11 : LUT6 generic map( INIT => X"9996966699969996" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_2_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_xor_3_11_SW0 : LUT4 generic map( INIT => X"7510" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), O => N2 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_3_11_SW0 : LUT4 generic map( INIT => X"693C" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), O => N5 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_3_11_SW1 : LUT4 generic map( INIT => X"D22D" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), O => N6 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_3_11 : LUT6 generic map( INIT => X"FFFFE8EE17110000" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, I4 => N5, I5 => N6, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_3_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_4_11_SW0 : LUT5 generic map( INIT => X"69669969" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2), O => N8 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_4_11_SW1 : LUT6 generic map( INIT => X"9969996999696966" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), O => N9 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_4_11_SW2 : LUT6 generic map( INIT => X"9969696669666966" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), O => N10 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_4_11 : LUT6 generic map( INIT => X"FFCCBF8C73403300" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_lut_2_Q, I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, I3 => N8, I4 => N10, I5 => N9, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_4_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o3_SW0 : LUT6 generic map( INIT => X"FFFF2FF22FF2FFFF" ) port map ( I0 => wr_en, I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562, I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), O => N12 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o3 : LUT6 generic map( INIT => X"0000000084210000" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, I5 => N12, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o3_605 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb3_SW0 : LUT6 generic map( INIT => X"D0000D0000D0000D" ) port map ( I0 => rd_en, I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278, I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), O => N14 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb3 : LUT6 generic map( INIT => X"0990000000000000" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, I5 => N14, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb3_609 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_cy_3_11_SW0 : LUT6 generic map( INIT => X"75F7757510511010" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), O => N16 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_cy_3_11_SW1 : LUT6 generic map( INIT => X"75F7757510511010" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2), O => N17 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_xor_4_11 : LUT6 generic map( INIT => X"9969666699996696" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, I4 => N16, I5 => N17, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_4_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i_rstpot_SW0 : LUT2 generic map( INIT => X"E" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(3), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(4), O => N19 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i_rstpot : LUT6 generic map( INIT => X"AAAABAAA8AAAAAAA" ) port map ( I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i, I1 => N19, I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(1), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(2), I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_wr_en_i_584, I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_rd_en_i_585, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i_rstpot_611 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_xor_3_11_SW2 : LUT4 generic map( INIT => X"7510" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1), O => N21 ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_xor_3_11 : LUT6 generic map( INIT => X"9969666699996696" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en, I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, I4 => N2, I5 => N21, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_3_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_xor_1_11 : LUT6 generic map( INIT => X"5A965A5A5AA55A5A" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562, I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278, I4 => rd_en, I5 => wr_en, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_1_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_1_11 : LUT6 generic map( INIT => X"5A965A5A5AA55A5A" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278, I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562, I4 => wr_en, I5 => rd_en, O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_1_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Madd_gc0_count_3_GND_427_o_add_0_OUT_xor_2_11 : LUT3 generic map( INIT => X"9A" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_2_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Madd_gc0_count_3_GND_427_o_add_0_OUT_xor_3_11 : LUT4 generic map( INIT => X"AA6A" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_3_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Madd_gc0_count_3_GND_427_o_add_0_OUT_xor_1_11 : LUT2 generic map( INIT => X"9" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_1_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Madd_gcc0_gc0_count_3_GND_435_o_add_0_OUT_xor_2_11 : LUT3 generic map( INIT => X"9A" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_2_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Madd_gcc0_gc0_count_3_GND_435_o_add_0_OUT_xor_3_11 : LUT4 generic map( INIT => X"AA6A" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2), I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1), I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_3_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Madd_gcc0_gc0_count_3_GND_435_o_add_0_OUT_xor_1_11 : LUT2 generic map( INIT => X"9" ) port map ( I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1), I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_1_Q ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_wr_pntr_0_inv1_INV_0 : INV port map ( I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1(0) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rd_pntr_0_inv1_INV_0 : INV port map ( I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1(0) ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram : RAMB36E1 generic map( DOA_REG => 0, DOB_REG => 0, EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "SDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 72, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "READ_FIRST", WRITE_MODE_B => "READ_FIRST", WRITE_WIDTH_A => 0, WRITE_WIDTH_B => 72 ) port map ( CASCADEINA => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, CASCADEINB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, CASCADEOUTA => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTA_UNCONNECTED , CASCADEOUTB => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTB_UNCONNECTED , CLKARDCLK => clk, CLKBWRCLK => clk, DBITERR => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DBITERR_UNCONNECTED , ENARDEN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en, ENBWREN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, INJECTDBITERR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, INJECTSBITERR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, REGCEAREGCE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, REGCEB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, RSTRAMARSTRAM => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q, RSTRAMB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, RSTREGARSTREG => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, RSTREGB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, SBITERR => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_SBITERR_UNCONNECTED , ADDRARDADDR(15) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_N0, ADDRARDADDR(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3), ADDRARDADDR(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), ADDRARDADDR(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), ADDRARDADDR(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), ADDRARDADDR(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(15) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_N0, ADDRBWRADDR(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3), ADDRBWRADDR(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2), ADDRBWRADDR(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1), ADDRBWRADDR(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), ADDRBWRADDR(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIADI(31) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIADI(30) => din(99), DIADI(29) => din(98), DIADI(28) => din(97), DIADI(27) => din(96), DIADI(26) => din(95), DIADI(25) => din(94), DIADI(24) => din(93), DIADI(23) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIADI(22) => din(92), DIADI(21) => din(91), DIADI(20) => din(90), DIADI(19) => din(89), DIADI(18) => din(88), DIADI(17) => din(87), DIADI(16) => din(86), DIADI(15) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIADI(14) => din(85), DIADI(13) => din(84), DIADI(12) => din(83), DIADI(11) => din(82), DIADI(10) => din(81), DIADI(9) => din(80), DIADI(8) => din(79), DIADI(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIADI(6) => din(78), DIADI(5) => din(77), DIADI(4) => din(76), DIADI(3) => din(75), DIADI(2) => din(74), DIADI(1) => din(73), DIADI(0) => din(72), DIBDI(31) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIBDI(30) => din(127), DIBDI(29) => din(126), DIBDI(28) => din(125), DIBDI(27) => din(124), DIBDI(26) => din(123), DIBDI(25) => din(122), DIBDI(24) => din(121), DIBDI(23) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIBDI(22) => din(120), DIBDI(21) => din(119), DIBDI(20) => din(118), DIBDI(19) => din(117), DIBDI(18) => din(116), DIBDI(17) => din(115), DIBDI(16) => din(114), DIBDI(15) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIBDI(14) => din(113), DIBDI(13) => din(112), DIBDI(12) => din(111), DIBDI(11) => din(110), DIBDI(10) => din(109), DIBDI(9) => din(108), DIBDI(8) => din(107), DIBDI(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIBDI(6) => din(106), DIBDI(5) => din(105), DIBDI(4) => din(104), DIBDI(3) => din(103), DIBDI(2) => din(102), DIBDI(1) => din(101), DIBDI(0) => din(100), DIPADIP(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIPADIP(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIPADIP(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIPADIP(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIPBDIP(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIPBDIP(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIPBDIP(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIPBDIP(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DOADO(31) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_31_UNCONNECTED , DOADO(30) => dout(99), DOADO(29) => dout(98), DOADO(28) => dout(97), DOADO(27) => dout(96), DOADO(26) => dout(95), DOADO(25) => dout(94), DOADO(24) => dout(93), DOADO(23) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_23_UNCONNECTED , DOADO(22) => dout(92), DOADO(21) => dout(91), DOADO(20) => dout(90), DOADO(19) => dout(89), DOADO(18) => dout(88), DOADO(17) => dout(87), DOADO(16) => dout(86), DOADO(15) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_15_UNCONNECTED , DOADO(14) => dout(85), DOADO(13) => dout(84), DOADO(12) => dout(83), DOADO(11) => dout(82), DOADO(10) => dout(81), DOADO(9) => dout(80), DOADO(8) => dout(79), DOADO(7) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_7_UNCONNECTED , DOADO(6) => dout(78), DOADO(5) => dout(77), DOADO(4) => dout(76), DOADO(3) => dout(75), DOADO(2) => dout(74), DOADO(1) => dout(73), DOADO(0) => dout(72), DOBDO(31) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_31_UNCONNECTED , DOBDO(30) => dout(127), DOBDO(29) => dout(126), DOBDO(28) => dout(125), DOBDO(27) => dout(124), DOBDO(26) => dout(123), DOBDO(25) => dout(122), DOBDO(24) => dout(121), DOBDO(23) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_23_UNCONNECTED , DOBDO(22) => dout(120), DOBDO(21) => dout(119), DOBDO(20) => dout(118), DOBDO(19) => dout(117), DOBDO(18) => dout(116), DOBDO(17) => dout(115), DOBDO(16) => dout(114), DOBDO(15) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_15_UNCONNECTED , DOBDO(14) => dout(113), DOBDO(13) => dout(112), DOBDO(12) => dout(111), DOBDO(11) => dout(110), DOBDO(10) => dout(109), DOBDO(9) => dout(108), DOBDO(8) => dout(107), DOBDO(7) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_7_UNCONNECTED , DOBDO(6) => dout(106), DOBDO(5) => dout(105), DOBDO(4) => dout(104), DOBDO(3) => dout(103), DOBDO(2) => dout(102), DOBDO(1) => dout(101), DOBDO(0) => dout(100), DOPADOP(3) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_3_UNCONNECTED , DOPADOP(2) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_2_UNCONNECTED , DOPADOP(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_1_UNCONNECTED , DOPADOP(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_0_UNCONNECTED , DOPBDOP(3) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_3_UNCONNECTED , DOPBDOP(2) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_2_UNCONNECTED , DOPBDOP(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_1_UNCONNECTED , DOPBDOP(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_0_UNCONNECTED , ECCPARITY(7) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_7_UNCONNECTED , ECCPARITY(6) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_6_UNCONNECTED , ECCPARITY(5) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_5_UNCONNECTED , ECCPARITY(4) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_4_UNCONNECTED , ECCPARITY(3) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_3_UNCONNECTED , ECCPARITY(2) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_2_UNCONNECTED , ECCPARITY(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_1_UNCONNECTED , ECCPARITY(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_0_UNCONNECTED , RDADDRECC(8) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_8_UNCONNECTED , RDADDRECC(7) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_7_UNCONNECTED , RDADDRECC(6) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_6_UNCONNECTED , RDADDRECC(5) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_5_UNCONNECTED , RDADDRECC(4) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_4_UNCONNECTED , RDADDRECC(3) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_3_UNCONNECTED , RDADDRECC(2) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_2_UNCONNECTED , RDADDRECC(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_1_UNCONNECTED , RDADDRECC(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_0_UNCONNECTED , WEA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, WEA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, WEA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, WEA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, WEBWE(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram : RAMB36E1 generic map( DOA_REG => 0, DOB_REG => 0, EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "SDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 72, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "READ_FIRST", WRITE_MODE_B => "READ_FIRST", WRITE_WIDTH_A => 0, WRITE_WIDTH_B => 72 ) port map ( CASCADEINA => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, CASCADEINB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, CASCADEOUTA => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTA_UNCONNECTED , CASCADEOUTB => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTB_UNCONNECTED , CLKARDCLK => clk, CLKBWRCLK => clk, DBITERR => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DBITERR_UNCONNECTED , ENARDEN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en, ENBWREN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, INJECTDBITERR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, INJECTSBITERR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, REGCEAREGCE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, REGCEB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, RSTRAMARSTRAM => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q, RSTRAMB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, RSTREGARSTREG => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, RSTREGB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, SBITERR => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_SBITERR_UNCONNECTED , ADDRARDADDR(15) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_N0, ADDRARDADDR(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3), ADDRARDADDR(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2), ADDRARDADDR(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1), ADDRARDADDR(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0), ADDRARDADDR(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRARDADDR(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(15) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_N0, ADDRBWRADDR(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3), ADDRBWRADDR(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2), ADDRBWRADDR(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1), ADDRBWRADDR(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0), ADDRBWRADDR(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, ADDRBWRADDR(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, DIADI(31) => din(34), DIADI(30) => din(33), DIADI(29) => din(32), DIADI(28) => din(31), DIADI(27) => din(30), DIADI(26) => din(29), DIADI(25) => din(28), DIADI(24) => din(27), DIADI(23) => din(25), DIADI(22) => din(24), DIADI(21) => din(23), DIADI(20) => din(22), DIADI(19) => din(21), DIADI(18) => din(20), DIADI(17) => din(19), DIADI(16) => din(18), DIADI(15) => din(16), DIADI(14) => din(15), DIADI(13) => din(14), DIADI(12) => din(13), DIADI(11) => din(12), DIADI(10) => din(11), DIADI(9) => din(10), DIADI(8) => din(9), DIADI(7) => din(7), DIADI(6) => din(6), DIADI(5) => din(5), DIADI(4) => din(4), DIADI(3) => din(3), DIADI(2) => din(2), DIADI(1) => din(1), DIADI(0) => din(0), DIBDI(31) => din(70), DIBDI(30) => din(69), DIBDI(29) => din(68), DIBDI(28) => din(67), DIBDI(27) => din(66), DIBDI(26) => din(65), DIBDI(25) => din(64), DIBDI(24) => din(63), DIBDI(23) => din(61), DIBDI(22) => din(60), DIBDI(21) => din(59), DIBDI(20) => din(58), DIBDI(19) => din(57), DIBDI(18) => din(56), DIBDI(17) => din(55), DIBDI(16) => din(54), DIBDI(15) => din(52), DIBDI(14) => din(51), DIBDI(13) => din(50), DIBDI(12) => din(49), DIBDI(11) => din(48), DIBDI(10) => din(47), DIBDI(9) => din(46), DIBDI(8) => din(45), DIBDI(7) => din(43), DIBDI(6) => din(42), DIBDI(5) => din(41), DIBDI(4) => din(40), DIBDI(3) => din(39), DIBDI(2) => din(38), DIBDI(1) => din(37), DIBDI(0) => din(36), DIPADIP(3) => din(35), DIPADIP(2) => din(26), DIPADIP(1) => din(17), DIPADIP(0) => din(8), DIPBDIP(3) => din(71), DIPBDIP(2) => din(62), DIPBDIP(1) => din(53), DIPBDIP(0) => din(44), DOADO(31) => dout(34), DOADO(30) => dout(33), DOADO(29) => dout(32), DOADO(28) => dout(31), DOADO(27) => dout(30), DOADO(26) => dout(29), DOADO(25) => dout(28), DOADO(24) => dout(27), DOADO(23) => dout(25), DOADO(22) => dout(24), DOADO(21) => dout(23), DOADO(20) => dout(22), DOADO(19) => dout(21), DOADO(18) => dout(20), DOADO(17) => dout(19), DOADO(16) => dout(18), DOADO(15) => dout(16), DOADO(14) => dout(15), DOADO(13) => dout(14), DOADO(12) => dout(13), DOADO(11) => dout(12), DOADO(10) => dout(11), DOADO(9) => dout(10), DOADO(8) => dout(9), DOADO(7) => dout(7), DOADO(6) => dout(6), DOADO(5) => dout(5), DOADO(4) => dout(4), DOADO(3) => dout(3), DOADO(2) => dout(2), DOADO(1) => dout(1), DOADO(0) => dout(0), DOBDO(31) => dout(70), DOBDO(30) => dout(69), DOBDO(29) => dout(68), DOBDO(28) => dout(67), DOBDO(27) => dout(66), DOBDO(26) => dout(65), DOBDO(25) => dout(64), DOBDO(24) => dout(63), DOBDO(23) => dout(61), DOBDO(22) => dout(60), DOBDO(21) => dout(59), DOBDO(20) => dout(58), DOBDO(19) => dout(57), DOBDO(18) => dout(56), DOBDO(17) => dout(55), DOBDO(16) => dout(54), DOBDO(15) => dout(52), DOBDO(14) => dout(51), DOBDO(13) => dout(50), DOBDO(12) => dout(49), DOBDO(11) => dout(48), DOBDO(10) => dout(47), DOBDO(9) => dout(46), DOBDO(8) => dout(45), DOBDO(7) => dout(43), DOBDO(6) => dout(42), DOBDO(5) => dout(41), DOBDO(4) => dout(40), DOBDO(3) => dout(39), DOBDO(2) => dout(38), DOBDO(1) => dout(37), DOBDO(0) => dout(36), DOPADOP(3) => dout(35), DOPADOP(2) => dout(26), DOPADOP(1) => dout(17), DOPADOP(0) => dout(8), DOPBDOP(3) => dout(71), DOPBDOP(2) => dout(62), DOPBDOP(1) => dout(53), DOPBDOP(0) => dout(44), ECCPARITY(7) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_7_UNCONNECTED , ECCPARITY(6) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_6_UNCONNECTED , ECCPARITY(5) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_5_UNCONNECTED , ECCPARITY(4) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_4_UNCONNECTED , ECCPARITY(3) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_3_UNCONNECTED , ECCPARITY(2) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_2_UNCONNECTED , ECCPARITY(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_1_UNCONNECTED , ECCPARITY(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_0_UNCONNECTED , RDADDRECC(8) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_8_UNCONNECTED , RDADDRECC(7) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_7_UNCONNECTED , RDADDRECC(6) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_6_UNCONNECTED , RDADDRECC(5) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_5_UNCONNECTED , RDADDRECC(4) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_4_UNCONNECTED , RDADDRECC(3) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_3_UNCONNECTED , RDADDRECC(2) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_2_UNCONNECTED , RDADDRECC(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_1_UNCONNECTED , RDADDRECC(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_0_UNCONNECTED , WEA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, WEA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, WEA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, WEA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR, WEBWE(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en, WEBWE(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_XST_GND : GND port map ( G => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR ); U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_XST_VCC : VCC port map ( P => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_N0 ); end STRUCTURE; -- synthesis translate_on
------------------------------------------------------------------------------- -- axi_vdma_sts_mngr ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_vdma_sts_mngr.vhd -- Description: This entity mangages 'halt' and 'idle' status -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_vdma.vhd -- |- axi_vdma_pkg.vhd -- |- axi_vdma_intrpt.vhd -- |- axi_vdma_rst_module.vhd -- | |- axi_vdma_reset.vhd (mm2s) -- | | |- axi_vdma_cdc.vhd -- | |- axi_vdma_reset.vhd (s2mm) -- | | |- axi_vdma_cdc.vhd -- | -- |- axi_vdma_reg_if.vhd -- | |- axi_vdma_lite_if.vhd -- | |- axi_vdma_cdc.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_vdma_sg_cdc.vhd (mm2s) -- |- axi_vdma_vid_cdc.vhd (mm2s) -- |- axi_vdma_fsync_gen.vhd (mm2s) -- |- axi_vdma_sof_gen.vhd (mm2s) -- |- axi_vdma_reg_module.vhd (mm2s) -- | |- axi_vdma_register.vhd (mm2s) -- | |- axi_vdma_regdirect.vhd (mm2s) -- |- axi_vdma_mngr.vhd (mm2s) -- | |- axi_vdma_sg_if.vhd (mm2s) -- | |- axi_vdma_sm.vhd (mm2s) -- | |- axi_vdma_cmdsts_if.vhd (mm2s) -- | |- axi_vdma_vidreg_module.vhd (mm2s) -- | | |- axi_vdma_sgregister.vhd (mm2s) -- | | |- axi_vdma_vregister.vhd (mm2s) -- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s) -- | | |- axi_vdma_blkmem.vhd (mm2s) -- | |- axi_vdma_genlock_mngr.vhd (mm2s) -- | |- axi_vdma_genlock_mux.vhd (mm2s) -- | |- axi_vdma_greycoder.vhd (mm2s) -- |- axi_vdma_mm2s_linebuf.vhd (mm2s) -- | |- axi_vdma_sfifo_autord.vhd (mm2s) -- | |- axi_vdma_afifo_autord.vhd (mm2s) -- | |- axi_vdma_skid_buf.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (mm2s) -- | -- |- axi_vdma_sg_cdc.vhd (s2mm) -- |- axi_vdma_vid_cdc.vhd (s2mm) -- |- axi_vdma_fsync_gen.vhd (s2mm) -- |- axi_vdma_sof_gen.vhd (s2mm) -- |- axi_vdma_reg_module.vhd (s2mm) -- | |- axi_vdma_register.vhd (s2mm) -- | |- axi_vdma_regdirect.vhd (s2mm) -- |- axi_vdma_mngr.vhd (s2mm) -- | |- axi_vdma_sg_if.vhd (s2mm) -- | |- axi_vdma_sm.vhd (s2mm) -- | |- axi_vdma_cmdsts_if.vhd (s2mm) -- | |- axi_vdma_vidreg_module.vhd (s2mm) -- | | |- axi_vdma_sgregister.vhd (s2mm) -- | | |- axi_vdma_vregister.vhd (s2mm) -- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm) -- | | |- axi_vdma_blkmem.vhd (s2mm) -- | |- axi_vdma_genlock_mngr.vhd (s2mm) -- | |- axi_vdma_genlock_mux.vhd (s2mm) -- | |- axi_vdma_greycoder.vhd (s2mm) -- |- axi_vdma_s2mm_linebuf.vhd (s2mm) -- | |- axi_vdma_sfifo_autord.vhd (s2mm) -- | |- axi_vdma_afifo_autord.vhd (s2mm) -- | |- axi_vdma_skid_buf.vhd (s2mm) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL) -- |- axi_sg_v3_00_a.axi_sg.vhd -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_vdma_v6_2_8; use axi_vdma_v6_2_8.axi_vdma_pkg.all; ------------------------------------------------------------------------------- entity axi_vdma_sts_mngr is port ( -- system signals prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- -- -- dma control and sg engine status signals -- run_stop : in std_logic ; -- regdir_idle : in std_logic ; -- ftch_idle : in std_logic ; -- cmnd_idle : in std_logic ; -- sts_idle : in std_logic ; -- line_buffer_empty : in std_logic ; -- dwidth_fifo_pipe_empty : in std_logic ; -- video_prmtrs_valid : in std_logic ; -- prmtr_update_complete : in std_logic ; --CR605424 -- -- stop and halt control/status -- stop : in std_logic ; -- halt : in std_logic ; -- CR 625278 halt_cmplt : in std_logic ; -- -- -- system state and control -- all_idle : out std_logic ; -- ftchcmdsts_idle : out std_logic ; -- cmdsts_idle : out std_logic ; -- halted_clr : out std_logic ; -- halted_set : out std_logic ; -- idle_set : out std_logic ; -- idle_clr : out std_logic -- ); end axi_vdma_sts_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_vdma_sts_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal all_is_idle : std_logic := '0'; signal ftch_idle_d1 : std_logic := '0'; signal ftch_idle_re : std_logic := '0'; signal ftch_idle_fe : std_logic := '0'; signal datamover_idle : std_logic := '0'; --signal cmdstsfifo_idle : std_logic := '0'; signal halted_set_i : std_logic := '0'; --signal datamover_idle_i : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- CR573389 - modified all_idle output to look at sg engine ftch idle only -- if video parameters are NOT valid, else ignore ftchidle. this fixes -- issue of xfer pausing while descriptors are being fetched. -- all_idle only used for frame sync determination ALL_IDLE_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then all_idle <= '1'; -- Qualify all idle with sg engine fetch idle when -- no video parameters are valid elsif(video_prmtrs_valid = '0')then all_idle <= ftch_idle and cmnd_idle and sts_idle and line_buffer_empty and dwidth_fifo_pipe_empty and regdir_idle -- Reg Direct idle (for fsync only) and prmtr_update_complete; -- CR605424 idle needs to account for lutram copy -- Otherwise if we have valid video parameters then do -- not stall transfers in free-run mode due to sg engine fetches else all_idle <= cmnd_idle and sts_idle and dwidth_fifo_pipe_empty and line_buffer_empty; end if; end if; end process ALL_IDLE_PROCESS; -- Idle for soft_reset determination -- Note Line buffer is not looked at because do not want to stall soft reset if external -- stream target does not accept data from line buffer. ftchcmdsts_idle <= ftch_idle and cmnd_idle and sts_idle; -- Command/Status Idle (Used for s2mm linebuffer reset qualification on shut down) cmdsts_idle <= cmnd_idle and sts_idle; ------------------------------------------------------------------------------- -- For data mover halting look at halt complete to determine when halt -- is done and datamover has completly halted. If datamover not being -- halted then can ignore flag thus simply flag as idle. ------------------------------------------------------------------------------- -- CR 625278 --datamover_idle <= '1' when (stop = '1' and halt_cmplt = '1') -- or (stop = '0') -- else '0'; -- -- Need to sample and hold for cases when user clears run/stop starting -- a shutdown phase, then an error occurs (stop=1) causing a second -- shutdown phase to start. previous the halt complete was missed by datamove_idle -- because stop asserted after the halt complete asserted due to the first -- shutdown phase. DATAMOVER_IDLE_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then datamover_idle <= '0'; -- if dm being halted and halt is completed then -- set and hold datamover idle. elsif(halt = '1' and halt_cmplt = '1')then datamover_idle <= '1'; -- clear datamove_idle if running and dm not -- being halted. elsif(halt = '0' and run_stop = '1')then datamover_idle <= '0'; end if; end if; end process DATAMOVER_IDLE_PROCESS; ------------------------------------------------------------------------------- -- Set halt bit if run/stop cleared and all processes are idle ------------------------------------------------------------------------------- -- Everything is idle when everything is idle used for setting halt flag. all_is_idle <= ftch_idle and cmnd_idle and sts_idle and dwidth_fifo_pipe_empty and line_buffer_empty; HALT_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then halted_set_i <= '0'; -- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted elsif(run_stop = '0' and all_is_idle = '1' and datamover_idle = '1')then halted_set_i <= '1'; else halted_set_i <= '0'; end if; end if; end process HALT_PROCESS; halted_set <= halted_set_i; ------------------------------------------------------------------------------- -- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors ------------------------------------------------------------------------------- NOT_HALTED_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then halted_clr <= '0'; elsif(run_stop = '1')then halted_clr <= '1'; else halted_clr <= '0'; end if; end if; end process NOT_HALTED_PROCESS; ------------------------------------------------------------------------------- -- Register ALL is Idle to create rising and falling edges on idle flag ------------------------------------------------------------------------------- IDLE_REG_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then ftch_idle_d1 <= '0'; else ftch_idle_d1 <= ftch_idle; end if; end if; end process IDLE_REG_PROCESS; ftch_idle_re <= ftch_idle and not ftch_idle_d1; ftch_idle_fe <= not ftch_idle and ftch_idle_d1; -- Set or Clear IDLE bit in DMASR idle_set <= ftch_idle_re and run_stop; idle_clr <= ftch_idle_fe; end implementation;
------------------------------------------------------------------------------- -- axi_vdma_sts_mngr ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_vdma_sts_mngr.vhd -- Description: This entity mangages 'halt' and 'idle' status -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_vdma.vhd -- |- axi_vdma_pkg.vhd -- |- axi_vdma_intrpt.vhd -- |- axi_vdma_rst_module.vhd -- | |- axi_vdma_reset.vhd (mm2s) -- | | |- axi_vdma_cdc.vhd -- | |- axi_vdma_reset.vhd (s2mm) -- | | |- axi_vdma_cdc.vhd -- | -- |- axi_vdma_reg_if.vhd -- | |- axi_vdma_lite_if.vhd -- | |- axi_vdma_cdc.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_vdma_sg_cdc.vhd (mm2s) -- |- axi_vdma_vid_cdc.vhd (mm2s) -- |- axi_vdma_fsync_gen.vhd (mm2s) -- |- axi_vdma_sof_gen.vhd (mm2s) -- |- axi_vdma_reg_module.vhd (mm2s) -- | |- axi_vdma_register.vhd (mm2s) -- | |- axi_vdma_regdirect.vhd (mm2s) -- |- axi_vdma_mngr.vhd (mm2s) -- | |- axi_vdma_sg_if.vhd (mm2s) -- | |- axi_vdma_sm.vhd (mm2s) -- | |- axi_vdma_cmdsts_if.vhd (mm2s) -- | |- axi_vdma_vidreg_module.vhd (mm2s) -- | | |- axi_vdma_sgregister.vhd (mm2s) -- | | |- axi_vdma_vregister.vhd (mm2s) -- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s) -- | | |- axi_vdma_blkmem.vhd (mm2s) -- | |- axi_vdma_genlock_mngr.vhd (mm2s) -- | |- axi_vdma_genlock_mux.vhd (mm2s) -- | |- axi_vdma_greycoder.vhd (mm2s) -- |- axi_vdma_mm2s_linebuf.vhd (mm2s) -- | |- axi_vdma_sfifo_autord.vhd (mm2s) -- | |- axi_vdma_afifo_autord.vhd (mm2s) -- | |- axi_vdma_skid_buf.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (mm2s) -- | -- |- axi_vdma_sg_cdc.vhd (s2mm) -- |- axi_vdma_vid_cdc.vhd (s2mm) -- |- axi_vdma_fsync_gen.vhd (s2mm) -- |- axi_vdma_sof_gen.vhd (s2mm) -- |- axi_vdma_reg_module.vhd (s2mm) -- | |- axi_vdma_register.vhd (s2mm) -- | |- axi_vdma_regdirect.vhd (s2mm) -- |- axi_vdma_mngr.vhd (s2mm) -- | |- axi_vdma_sg_if.vhd (s2mm) -- | |- axi_vdma_sm.vhd (s2mm) -- | |- axi_vdma_cmdsts_if.vhd (s2mm) -- | |- axi_vdma_vidreg_module.vhd (s2mm) -- | | |- axi_vdma_sgregister.vhd (s2mm) -- | | |- axi_vdma_vregister.vhd (s2mm) -- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm) -- | | |- axi_vdma_blkmem.vhd (s2mm) -- | |- axi_vdma_genlock_mngr.vhd (s2mm) -- | |- axi_vdma_genlock_mux.vhd (s2mm) -- | |- axi_vdma_greycoder.vhd (s2mm) -- |- axi_vdma_s2mm_linebuf.vhd (s2mm) -- | |- axi_vdma_sfifo_autord.vhd (s2mm) -- | |- axi_vdma_afifo_autord.vhd (s2mm) -- | |- axi_vdma_skid_buf.vhd (s2mm) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL) -- |- axi_sg_v3_00_a.axi_sg.vhd -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_vdma_v6_2_8; use axi_vdma_v6_2_8.axi_vdma_pkg.all; ------------------------------------------------------------------------------- entity axi_vdma_sts_mngr is port ( -- system signals prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- -- -- dma control and sg engine status signals -- run_stop : in std_logic ; -- regdir_idle : in std_logic ; -- ftch_idle : in std_logic ; -- cmnd_idle : in std_logic ; -- sts_idle : in std_logic ; -- line_buffer_empty : in std_logic ; -- dwidth_fifo_pipe_empty : in std_logic ; -- video_prmtrs_valid : in std_logic ; -- prmtr_update_complete : in std_logic ; --CR605424 -- -- stop and halt control/status -- stop : in std_logic ; -- halt : in std_logic ; -- CR 625278 halt_cmplt : in std_logic ; -- -- -- system state and control -- all_idle : out std_logic ; -- ftchcmdsts_idle : out std_logic ; -- cmdsts_idle : out std_logic ; -- halted_clr : out std_logic ; -- halted_set : out std_logic ; -- idle_set : out std_logic ; -- idle_clr : out std_logic -- ); end axi_vdma_sts_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_vdma_sts_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal all_is_idle : std_logic := '0'; signal ftch_idle_d1 : std_logic := '0'; signal ftch_idle_re : std_logic := '0'; signal ftch_idle_fe : std_logic := '0'; signal datamover_idle : std_logic := '0'; --signal cmdstsfifo_idle : std_logic := '0'; signal halted_set_i : std_logic := '0'; --signal datamover_idle_i : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- CR573389 - modified all_idle output to look at sg engine ftch idle only -- if video parameters are NOT valid, else ignore ftchidle. this fixes -- issue of xfer pausing while descriptors are being fetched. -- all_idle only used for frame sync determination ALL_IDLE_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then all_idle <= '1'; -- Qualify all idle with sg engine fetch idle when -- no video parameters are valid elsif(video_prmtrs_valid = '0')then all_idle <= ftch_idle and cmnd_idle and sts_idle and line_buffer_empty and dwidth_fifo_pipe_empty and regdir_idle -- Reg Direct idle (for fsync only) and prmtr_update_complete; -- CR605424 idle needs to account for lutram copy -- Otherwise if we have valid video parameters then do -- not stall transfers in free-run mode due to sg engine fetches else all_idle <= cmnd_idle and sts_idle and dwidth_fifo_pipe_empty and line_buffer_empty; end if; end if; end process ALL_IDLE_PROCESS; -- Idle for soft_reset determination -- Note Line buffer is not looked at because do not want to stall soft reset if external -- stream target does not accept data from line buffer. ftchcmdsts_idle <= ftch_idle and cmnd_idle and sts_idle; -- Command/Status Idle (Used for s2mm linebuffer reset qualification on shut down) cmdsts_idle <= cmnd_idle and sts_idle; ------------------------------------------------------------------------------- -- For data mover halting look at halt complete to determine when halt -- is done and datamover has completly halted. If datamover not being -- halted then can ignore flag thus simply flag as idle. ------------------------------------------------------------------------------- -- CR 625278 --datamover_idle <= '1' when (stop = '1' and halt_cmplt = '1') -- or (stop = '0') -- else '0'; -- -- Need to sample and hold for cases when user clears run/stop starting -- a shutdown phase, then an error occurs (stop=1) causing a second -- shutdown phase to start. previous the halt complete was missed by datamove_idle -- because stop asserted after the halt complete asserted due to the first -- shutdown phase. DATAMOVER_IDLE_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then datamover_idle <= '0'; -- if dm being halted and halt is completed then -- set and hold datamover idle. elsif(halt = '1' and halt_cmplt = '1')then datamover_idle <= '1'; -- clear datamove_idle if running and dm not -- being halted. elsif(halt = '0' and run_stop = '1')then datamover_idle <= '0'; end if; end if; end process DATAMOVER_IDLE_PROCESS; ------------------------------------------------------------------------------- -- Set halt bit if run/stop cleared and all processes are idle ------------------------------------------------------------------------------- -- Everything is idle when everything is idle used for setting halt flag. all_is_idle <= ftch_idle and cmnd_idle and sts_idle and dwidth_fifo_pipe_empty and line_buffer_empty; HALT_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then halted_set_i <= '0'; -- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted elsif(run_stop = '0' and all_is_idle = '1' and datamover_idle = '1')then halted_set_i <= '1'; else halted_set_i <= '0'; end if; end if; end process HALT_PROCESS; halted_set <= halted_set_i; ------------------------------------------------------------------------------- -- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors ------------------------------------------------------------------------------- NOT_HALTED_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then halted_clr <= '0'; elsif(run_stop = '1')then halted_clr <= '1'; else halted_clr <= '0'; end if; end if; end process NOT_HALTED_PROCESS; ------------------------------------------------------------------------------- -- Register ALL is Idle to create rising and falling edges on idle flag ------------------------------------------------------------------------------- IDLE_REG_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then ftch_idle_d1 <= '0'; else ftch_idle_d1 <= ftch_idle; end if; end if; end process IDLE_REG_PROCESS; ftch_idle_re <= ftch_idle and not ftch_idle_d1; ftch_idle_fe <= not ftch_idle and ftch_idle_d1; -- Set or Clear IDLE bit in DMASR idle_set <= ftch_idle_re and run_stop; idle_clr <= ftch_idle_fe; end implementation;
------------------------------------------------------------------------------- -- axi_vdma_sts_mngr ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_vdma_sts_mngr.vhd -- Description: This entity mangages 'halt' and 'idle' status -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_vdma.vhd -- |- axi_vdma_pkg.vhd -- |- axi_vdma_intrpt.vhd -- |- axi_vdma_rst_module.vhd -- | |- axi_vdma_reset.vhd (mm2s) -- | | |- axi_vdma_cdc.vhd -- | |- axi_vdma_reset.vhd (s2mm) -- | | |- axi_vdma_cdc.vhd -- | -- |- axi_vdma_reg_if.vhd -- | |- axi_vdma_lite_if.vhd -- | |- axi_vdma_cdc.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_vdma_sg_cdc.vhd (mm2s) -- |- axi_vdma_vid_cdc.vhd (mm2s) -- |- axi_vdma_fsync_gen.vhd (mm2s) -- |- axi_vdma_sof_gen.vhd (mm2s) -- |- axi_vdma_reg_module.vhd (mm2s) -- | |- axi_vdma_register.vhd (mm2s) -- | |- axi_vdma_regdirect.vhd (mm2s) -- |- axi_vdma_mngr.vhd (mm2s) -- | |- axi_vdma_sg_if.vhd (mm2s) -- | |- axi_vdma_sm.vhd (mm2s) -- | |- axi_vdma_cmdsts_if.vhd (mm2s) -- | |- axi_vdma_vidreg_module.vhd (mm2s) -- | | |- axi_vdma_sgregister.vhd (mm2s) -- | | |- axi_vdma_vregister.vhd (mm2s) -- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s) -- | | |- axi_vdma_blkmem.vhd (mm2s) -- | |- axi_vdma_genlock_mngr.vhd (mm2s) -- | |- axi_vdma_genlock_mux.vhd (mm2s) -- | |- axi_vdma_greycoder.vhd (mm2s) -- |- axi_vdma_mm2s_linebuf.vhd (mm2s) -- | |- axi_vdma_sfifo_autord.vhd (mm2s) -- | |- axi_vdma_afifo_autord.vhd (mm2s) -- | |- axi_vdma_skid_buf.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (mm2s) -- | -- |- axi_vdma_sg_cdc.vhd (s2mm) -- |- axi_vdma_vid_cdc.vhd (s2mm) -- |- axi_vdma_fsync_gen.vhd (s2mm) -- |- axi_vdma_sof_gen.vhd (s2mm) -- |- axi_vdma_reg_module.vhd (s2mm) -- | |- axi_vdma_register.vhd (s2mm) -- | |- axi_vdma_regdirect.vhd (s2mm) -- |- axi_vdma_mngr.vhd (s2mm) -- | |- axi_vdma_sg_if.vhd (s2mm) -- | |- axi_vdma_sm.vhd (s2mm) -- | |- axi_vdma_cmdsts_if.vhd (s2mm) -- | |- axi_vdma_vidreg_module.vhd (s2mm) -- | | |- axi_vdma_sgregister.vhd (s2mm) -- | | |- axi_vdma_vregister.vhd (s2mm) -- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm) -- | | |- axi_vdma_blkmem.vhd (s2mm) -- | |- axi_vdma_genlock_mngr.vhd (s2mm) -- | |- axi_vdma_genlock_mux.vhd (s2mm) -- | |- axi_vdma_greycoder.vhd (s2mm) -- |- axi_vdma_s2mm_linebuf.vhd (s2mm) -- | |- axi_vdma_sfifo_autord.vhd (s2mm) -- | |- axi_vdma_afifo_autord.vhd (s2mm) -- | |- axi_vdma_skid_buf.vhd (s2mm) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL) -- |- axi_sg_v3_00_a.axi_sg.vhd -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_vdma_v6_2_8; use axi_vdma_v6_2_8.axi_vdma_pkg.all; ------------------------------------------------------------------------------- entity axi_vdma_sts_mngr is port ( -- system signals prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- -- -- dma control and sg engine status signals -- run_stop : in std_logic ; -- regdir_idle : in std_logic ; -- ftch_idle : in std_logic ; -- cmnd_idle : in std_logic ; -- sts_idle : in std_logic ; -- line_buffer_empty : in std_logic ; -- dwidth_fifo_pipe_empty : in std_logic ; -- video_prmtrs_valid : in std_logic ; -- prmtr_update_complete : in std_logic ; --CR605424 -- -- stop and halt control/status -- stop : in std_logic ; -- halt : in std_logic ; -- CR 625278 halt_cmplt : in std_logic ; -- -- -- system state and control -- all_idle : out std_logic ; -- ftchcmdsts_idle : out std_logic ; -- cmdsts_idle : out std_logic ; -- halted_clr : out std_logic ; -- halted_set : out std_logic ; -- idle_set : out std_logic ; -- idle_clr : out std_logic -- ); end axi_vdma_sts_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_vdma_sts_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal all_is_idle : std_logic := '0'; signal ftch_idle_d1 : std_logic := '0'; signal ftch_idle_re : std_logic := '0'; signal ftch_idle_fe : std_logic := '0'; signal datamover_idle : std_logic := '0'; --signal cmdstsfifo_idle : std_logic := '0'; signal halted_set_i : std_logic := '0'; --signal datamover_idle_i : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- CR573389 - modified all_idle output to look at sg engine ftch idle only -- if video parameters are NOT valid, else ignore ftchidle. this fixes -- issue of xfer pausing while descriptors are being fetched. -- all_idle only used for frame sync determination ALL_IDLE_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then all_idle <= '1'; -- Qualify all idle with sg engine fetch idle when -- no video parameters are valid elsif(video_prmtrs_valid = '0')then all_idle <= ftch_idle and cmnd_idle and sts_idle and line_buffer_empty and dwidth_fifo_pipe_empty and regdir_idle -- Reg Direct idle (for fsync only) and prmtr_update_complete; -- CR605424 idle needs to account for lutram copy -- Otherwise if we have valid video parameters then do -- not stall transfers in free-run mode due to sg engine fetches else all_idle <= cmnd_idle and sts_idle and dwidth_fifo_pipe_empty and line_buffer_empty; end if; end if; end process ALL_IDLE_PROCESS; -- Idle for soft_reset determination -- Note Line buffer is not looked at because do not want to stall soft reset if external -- stream target does not accept data from line buffer. ftchcmdsts_idle <= ftch_idle and cmnd_idle and sts_idle; -- Command/Status Idle (Used for s2mm linebuffer reset qualification on shut down) cmdsts_idle <= cmnd_idle and sts_idle; ------------------------------------------------------------------------------- -- For data mover halting look at halt complete to determine when halt -- is done and datamover has completly halted. If datamover not being -- halted then can ignore flag thus simply flag as idle. ------------------------------------------------------------------------------- -- CR 625278 --datamover_idle <= '1' when (stop = '1' and halt_cmplt = '1') -- or (stop = '0') -- else '0'; -- -- Need to sample and hold for cases when user clears run/stop starting -- a shutdown phase, then an error occurs (stop=1) causing a second -- shutdown phase to start. previous the halt complete was missed by datamove_idle -- because stop asserted after the halt complete asserted due to the first -- shutdown phase. DATAMOVER_IDLE_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then datamover_idle <= '0'; -- if dm being halted and halt is completed then -- set and hold datamover idle. elsif(halt = '1' and halt_cmplt = '1')then datamover_idle <= '1'; -- clear datamove_idle if running and dm not -- being halted. elsif(halt = '0' and run_stop = '1')then datamover_idle <= '0'; end if; end if; end process DATAMOVER_IDLE_PROCESS; ------------------------------------------------------------------------------- -- Set halt bit if run/stop cleared and all processes are idle ------------------------------------------------------------------------------- -- Everything is idle when everything is idle used for setting halt flag. all_is_idle <= ftch_idle and cmnd_idle and sts_idle and dwidth_fifo_pipe_empty and line_buffer_empty; HALT_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then halted_set_i <= '0'; -- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted elsif(run_stop = '0' and all_is_idle = '1' and datamover_idle = '1')then halted_set_i <= '1'; else halted_set_i <= '0'; end if; end if; end process HALT_PROCESS; halted_set <= halted_set_i; ------------------------------------------------------------------------------- -- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors ------------------------------------------------------------------------------- NOT_HALTED_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then halted_clr <= '0'; elsif(run_stop = '1')then halted_clr <= '1'; else halted_clr <= '0'; end if; end if; end process NOT_HALTED_PROCESS; ------------------------------------------------------------------------------- -- Register ALL is Idle to create rising and falling edges on idle flag ------------------------------------------------------------------------------- IDLE_REG_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then ftch_idle_d1 <= '0'; else ftch_idle_d1 <= ftch_idle; end if; end if; end process IDLE_REG_PROCESS; ftch_idle_re <= ftch_idle and not ftch_idle_d1; ftch_idle_fe <= not ftch_idle and ftch_idle_d1; -- Set or Clear IDLE bit in DMASR idle_set <= ftch_idle_re and run_stop; idle_clr <= ftch_idle_fe; end implementation;
------------------------------------------------------------------------------- -- axi_vdma_sts_mngr ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_vdma_sts_mngr.vhd -- Description: This entity mangages 'halt' and 'idle' status -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_vdma.vhd -- |- axi_vdma_pkg.vhd -- |- axi_vdma_intrpt.vhd -- |- axi_vdma_rst_module.vhd -- | |- axi_vdma_reset.vhd (mm2s) -- | | |- axi_vdma_cdc.vhd -- | |- axi_vdma_reset.vhd (s2mm) -- | | |- axi_vdma_cdc.vhd -- | -- |- axi_vdma_reg_if.vhd -- | |- axi_vdma_lite_if.vhd -- | |- axi_vdma_cdc.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_vdma_sg_cdc.vhd (mm2s) -- |- axi_vdma_vid_cdc.vhd (mm2s) -- |- axi_vdma_fsync_gen.vhd (mm2s) -- |- axi_vdma_sof_gen.vhd (mm2s) -- |- axi_vdma_reg_module.vhd (mm2s) -- | |- axi_vdma_register.vhd (mm2s) -- | |- axi_vdma_regdirect.vhd (mm2s) -- |- axi_vdma_mngr.vhd (mm2s) -- | |- axi_vdma_sg_if.vhd (mm2s) -- | |- axi_vdma_sm.vhd (mm2s) -- | |- axi_vdma_cmdsts_if.vhd (mm2s) -- | |- axi_vdma_vidreg_module.vhd (mm2s) -- | | |- axi_vdma_sgregister.vhd (mm2s) -- | | |- axi_vdma_vregister.vhd (mm2s) -- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s) -- | | |- axi_vdma_blkmem.vhd (mm2s) -- | |- axi_vdma_genlock_mngr.vhd (mm2s) -- | |- axi_vdma_genlock_mux.vhd (mm2s) -- | |- axi_vdma_greycoder.vhd (mm2s) -- |- axi_vdma_mm2s_linebuf.vhd (mm2s) -- | |- axi_vdma_sfifo_autord.vhd (mm2s) -- | |- axi_vdma_afifo_autord.vhd (mm2s) -- | |- axi_vdma_skid_buf.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (mm2s) -- | -- |- axi_vdma_sg_cdc.vhd (s2mm) -- |- axi_vdma_vid_cdc.vhd (s2mm) -- |- axi_vdma_fsync_gen.vhd (s2mm) -- |- axi_vdma_sof_gen.vhd (s2mm) -- |- axi_vdma_reg_module.vhd (s2mm) -- | |- axi_vdma_register.vhd (s2mm) -- | |- axi_vdma_regdirect.vhd (s2mm) -- |- axi_vdma_mngr.vhd (s2mm) -- | |- axi_vdma_sg_if.vhd (s2mm) -- | |- axi_vdma_sm.vhd (s2mm) -- | |- axi_vdma_cmdsts_if.vhd (s2mm) -- | |- axi_vdma_vidreg_module.vhd (s2mm) -- | | |- axi_vdma_sgregister.vhd (s2mm) -- | | |- axi_vdma_vregister.vhd (s2mm) -- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm) -- | | |- axi_vdma_blkmem.vhd (s2mm) -- | |- axi_vdma_genlock_mngr.vhd (s2mm) -- | |- axi_vdma_genlock_mux.vhd (s2mm) -- | |- axi_vdma_greycoder.vhd (s2mm) -- |- axi_vdma_s2mm_linebuf.vhd (s2mm) -- | |- axi_vdma_sfifo_autord.vhd (s2mm) -- | |- axi_vdma_afifo_autord.vhd (s2mm) -- | |- axi_vdma_skid_buf.vhd (s2mm) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL) -- |- axi_sg_v3_00_a.axi_sg.vhd -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_vdma_v6_2_8; use axi_vdma_v6_2_8.axi_vdma_pkg.all; ------------------------------------------------------------------------------- entity axi_vdma_sts_mngr is port ( -- system signals prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- -- -- dma control and sg engine status signals -- run_stop : in std_logic ; -- regdir_idle : in std_logic ; -- ftch_idle : in std_logic ; -- cmnd_idle : in std_logic ; -- sts_idle : in std_logic ; -- line_buffer_empty : in std_logic ; -- dwidth_fifo_pipe_empty : in std_logic ; -- video_prmtrs_valid : in std_logic ; -- prmtr_update_complete : in std_logic ; --CR605424 -- -- stop and halt control/status -- stop : in std_logic ; -- halt : in std_logic ; -- CR 625278 halt_cmplt : in std_logic ; -- -- -- system state and control -- all_idle : out std_logic ; -- ftchcmdsts_idle : out std_logic ; -- cmdsts_idle : out std_logic ; -- halted_clr : out std_logic ; -- halted_set : out std_logic ; -- idle_set : out std_logic ; -- idle_clr : out std_logic -- ); end axi_vdma_sts_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_vdma_sts_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal all_is_idle : std_logic := '0'; signal ftch_idle_d1 : std_logic := '0'; signal ftch_idle_re : std_logic := '0'; signal ftch_idle_fe : std_logic := '0'; signal datamover_idle : std_logic := '0'; --signal cmdstsfifo_idle : std_logic := '0'; signal halted_set_i : std_logic := '0'; --signal datamover_idle_i : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- CR573389 - modified all_idle output to look at sg engine ftch idle only -- if video parameters are NOT valid, else ignore ftchidle. this fixes -- issue of xfer pausing while descriptors are being fetched. -- all_idle only used for frame sync determination ALL_IDLE_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then all_idle <= '1'; -- Qualify all idle with sg engine fetch idle when -- no video parameters are valid elsif(video_prmtrs_valid = '0')then all_idle <= ftch_idle and cmnd_idle and sts_idle and line_buffer_empty and dwidth_fifo_pipe_empty and regdir_idle -- Reg Direct idle (for fsync only) and prmtr_update_complete; -- CR605424 idle needs to account for lutram copy -- Otherwise if we have valid video parameters then do -- not stall transfers in free-run mode due to sg engine fetches else all_idle <= cmnd_idle and sts_idle and dwidth_fifo_pipe_empty and line_buffer_empty; end if; end if; end process ALL_IDLE_PROCESS; -- Idle for soft_reset determination -- Note Line buffer is not looked at because do not want to stall soft reset if external -- stream target does not accept data from line buffer. ftchcmdsts_idle <= ftch_idle and cmnd_idle and sts_idle; -- Command/Status Idle (Used for s2mm linebuffer reset qualification on shut down) cmdsts_idle <= cmnd_idle and sts_idle; ------------------------------------------------------------------------------- -- For data mover halting look at halt complete to determine when halt -- is done and datamover has completly halted. If datamover not being -- halted then can ignore flag thus simply flag as idle. ------------------------------------------------------------------------------- -- CR 625278 --datamover_idle <= '1' when (stop = '1' and halt_cmplt = '1') -- or (stop = '0') -- else '0'; -- -- Need to sample and hold for cases when user clears run/stop starting -- a shutdown phase, then an error occurs (stop=1) causing a second -- shutdown phase to start. previous the halt complete was missed by datamove_idle -- because stop asserted after the halt complete asserted due to the first -- shutdown phase. DATAMOVER_IDLE_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then datamover_idle <= '0'; -- if dm being halted and halt is completed then -- set and hold datamover idle. elsif(halt = '1' and halt_cmplt = '1')then datamover_idle <= '1'; -- clear datamove_idle if running and dm not -- being halted. elsif(halt = '0' and run_stop = '1')then datamover_idle <= '0'; end if; end if; end process DATAMOVER_IDLE_PROCESS; ------------------------------------------------------------------------------- -- Set halt bit if run/stop cleared and all processes are idle ------------------------------------------------------------------------------- -- Everything is idle when everything is idle used for setting halt flag. all_is_idle <= ftch_idle and cmnd_idle and sts_idle and dwidth_fifo_pipe_empty and line_buffer_empty; HALT_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then halted_set_i <= '0'; -- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted elsif(run_stop = '0' and all_is_idle = '1' and datamover_idle = '1')then halted_set_i <= '1'; else halted_set_i <= '0'; end if; end if; end process HALT_PROCESS; halted_set <= halted_set_i; ------------------------------------------------------------------------------- -- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors ------------------------------------------------------------------------------- NOT_HALTED_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then halted_clr <= '0'; elsif(run_stop = '1')then halted_clr <= '1'; else halted_clr <= '0'; end if; end if; end process NOT_HALTED_PROCESS; ------------------------------------------------------------------------------- -- Register ALL is Idle to create rising and falling edges on idle flag ------------------------------------------------------------------------------- IDLE_REG_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then ftch_idle_d1 <= '0'; else ftch_idle_d1 <= ftch_idle; end if; end if; end process IDLE_REG_PROCESS; ftch_idle_re <= ftch_idle and not ftch_idle_d1; ftch_idle_fe <= not ftch_idle and ftch_idle_d1; -- Set or Clear IDLE bit in DMASR idle_set <= ftch_idle_re and run_stop; idle_clr <= ftch_idle_fe; end implementation;
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Tue Sep 17 15:49:29 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_gcd_0_0_stub.vhdl -- Design : gcd_block_design_gcd_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is Port ( s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_gcd_bus_AWVALID : in STD_LOGIC; s_axi_gcd_bus_AWREADY : out STD_LOGIC; s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_gcd_bus_WVALID : in STD_LOGIC; s_axi_gcd_bus_WREADY : out STD_LOGIC; s_axi_gcd_bus_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_gcd_bus_BVALID : out STD_LOGIC; s_axi_gcd_bus_BREADY : in STD_LOGIC; s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_gcd_bus_ARVALID : in STD_LOGIC; s_axi_gcd_bus_ARREADY : out STD_LOGIC; s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_gcd_bus_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_gcd_bus_RVALID : out STD_LOGIC; s_axi_gcd_bus_RREADY : in STD_LOGIC; ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC; interrupt : out STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "s_axi_gcd_bus_AWADDR[5:0],s_axi_gcd_bus_AWVALID,s_axi_gcd_bus_AWREADY,s_axi_gcd_bus_WDATA[31:0],s_axi_gcd_bus_WSTRB[3:0],s_axi_gcd_bus_WVALID,s_axi_gcd_bus_WREADY,s_axi_gcd_bus_BRESP[1:0],s_axi_gcd_bus_BVALID,s_axi_gcd_bus_BREADY,s_axi_gcd_bus_ARADDR[5:0],s_axi_gcd_bus_ARVALID,s_axi_gcd_bus_ARREADY,s_axi_gcd_bus_RDATA[31:0],s_axi_gcd_bus_RRESP[1:0],s_axi_gcd_bus_RVALID,s_axi_gcd_bus_RREADY,ap_clk,ap_rst_n,interrupt"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "gcd,Vivado 2018.2"; begin end;
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_2; USE blk_mem_gen_v8_2.blk_mem_gen_v8_2; ENTITY centipede_ROM IS PORT ( clka : IN STD_LOGIC; addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END centipede_ROM; ARCHITECTURE centipede_ROM_arch OF centipede_ROM IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF centipede_ROM_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_2 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_2; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF centipede_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF centipede_ROM_arch : ARCHITECTURE IS "centipede_ROM,blk_mem_gen_v8_2,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF centipede_ROM_arch: ARCHITECTURE IS "centipede_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=centipede_ROM.mif,C_INIT_FILE=centipede_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; BEGIN U0 : blk_mem_gen_v8_2 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 3, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 1, C_INIT_FILE_NAME => "centipede_ROM.mif", C_INIT_FILE => "centipede_ROM.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 0, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 8, C_READ_WIDTH_A => 8, C_WRITE_DEPTH_A => 16384, C_READ_DEPTH_A => 16384, C_ADDRA_WIDTH => 14, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 8, C_READ_WIDTH_B => 8, C_WRITE_DEPTH_B => 16384, C_READ_DEPTH_B => 16384, C_ADDRB_WIDTH => 14, C_HAS_MEM_OUTPUT_REGS_A => 0, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "4", C_COUNT_18K_BRAM => "0", C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => '0', regcea => '0', wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addra => addra, dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), douta => douta, clkb => '0', rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)), dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END centipede_ROM_arch;
------------------------------------------------------------------------------- -- system_tb.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- START USER CODE (Do not remove this line) -- User: Put your libraries here. Code in this -- section will not be overwritten. -- END USER CODE (Do not remove this line) entity system_tb is end system_tb; architecture STRUCTURE of system_tb is constant fpga_0_clk_1_sys_clk_pin_PERIOD : time := 10000.000000 ps; constant fpga_0_rst_1_sys_rst_pin_LENGTH : time := 160000 ps; component system is port ( fpga_0_clk_1_sys_clk_pin : in std_logic; fpga_0_rst_1_sys_rst_pin : in std_logic ); end component; -- Internal signals signal fpga_0_clk_1_sys_clk_pin : std_logic; signal fpga_0_rst_1_sys_rst_pin : std_logic; -- START USER CODE (Do not remove this line) -- User: Put your signals here. Code in this -- section will not be overwritten. -- END USER CODE (Do not remove this line) begin dut : system port map ( fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin, fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin ); -- Clock generator for fpga_0_clk_1_sys_clk_pin process begin fpga_0_clk_1_sys_clk_pin <= '0'; loop wait for (fpga_0_clk_1_sys_clk_pin_PERIOD/2); fpga_0_clk_1_sys_clk_pin <= not fpga_0_clk_1_sys_clk_pin; end loop; end process; -- Reset Generator for fpga_0_rst_1_sys_rst_pin process begin fpga_0_rst_1_sys_rst_pin <= '0'; wait for (fpga_0_rst_1_sys_rst_pin_LENGTH); fpga_0_rst_1_sys_rst_pin <= not fpga_0_rst_1_sys_rst_pin; wait; end process; -- START USER CODE (Do not remove this line) -- User: Put your stimulus here. Code in this -- section will not be overwritten. -- END USER CODE (Do not remove this line) end architecture STRUCTURE;
--This should pass context c1 is end context c1; --This should fail context c1 is end context c1; context c1 is end context c1; context c2 is end context c2; context c1 is end context c1;
----------------------------------------------------------------------------------------------------------- -- -- NONRESTORING INTEGER OPERANDS DIVIDER -- -- Created by Claudio Brunelli, 2004 -- ----------------------------------------------------------------------------------------------------------- --Copyright (c) 2004, Tampere University of Technology. --All rights reserved. --Redistribution and use in source and binary forms, with or without modification, --are permitted provided that the following conditions are met: --* Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. --* Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. --* Neither the name of Tampere University of Technology nor the names of its -- contributors may be used to endorse or promote products derived from this -- software without specific prior written permission. --THIS HARDWARE DESCRIPTION OR SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND --CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT --LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND NONINFRINGEMENT AND --FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT --OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, --EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, --PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --ARISING IN ANY WAY OUT OF THE USE OF THIS HARDWARE DESCRIPTION OR SOFTWARE, EVEN --IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.cop_definitions.all; use work.cop_components.all; entity integer_divider is port( clk : in std_logic; reset : in std_logic; dvd : in std_logic_vector(dividend_width-1 downto 0); dvs : in std_logic_vector(divisor_width-1 downto 0); quot : out std_logic_vector(quotient_width-1 downto 0); rest : out std_logic_vector(division_rem_width-1 downto 0) ); end integer_divider ; ------------------------------------------------------------------------------- architecture rtl of integer_divider is type vector_bus is array (div_k_max downto 0) of std_logic_vector(26 downto 0); signal positive_q, turned_positive_q, temp_q, q : std_logic_vector(div_k_max downto 0); signal r : vector_bus; signal pipelined_r1, pipelined_r4, pipelined_r7, pipelined_r10, pipelined_r13, pipelined_r16, pipelined_r19, pipelined_r22 : std_logic_vector(26 downto 0); signal temp_remainder : std_logic_vector(26 downto 0); signal x, d, pipelined_d1, pipelined_d2, pipelined_d3, pipelined_d4, pipelined_d5, pipelined_d6, pipelined_d7, pipelined_d8 : std_logic_vector(26 downto 0); signal vector_q : std_logic_vector(quotient_width-1 downto 0); signal fixed_enable : std_logic; signal d_is_greater : std_logic; signal delayed_d_is_greater : std_logic; signal delayed_positive_q1, delayed_positive_q2, delayed_positive_q3, delayed_positive_q4, delayed_positive_q5, delayed_positive_q6, delayed_positive_q7, delayed_positive_q8, delayed_positive_q9, delayed_positive_q10, delayed_positive_q11, delayed_positive_q12, delayed_positive_q13, delayed_positive_q14, delayed_positive_q15, delayed_positive_q16, delayed_positive_q17, delayed_positive_q18, delayed_positive_q19, delayed_positive_q20, delayed_positive_q21 : std_logic; signal triple_y : integer; signal r24_case_a, r24_case_b, r24_case_c, r24_case_d : std_logic_vector(26 downto 0); signal r25_case_a, r25_case_b, r25_case_c, r25_case_d, r25_case_e, r25_case_f, r25_case_g, r25_case_h : std_logic_vector(26 downto 0); signal simple_x : std_logic_vector(27 downto 0); signal double_x : std_logic_vector(28 downto 0); signal double_y : std_logic_vector(27 downto 0); signal quad_y : std_logic_vector(28 downto 0); begin ----------------------------------------------------------------------------------------------------------------- fixed_enable <= '1'; -- d_is_greater delay chain D_IS_GREATER_PIPELINE: ff_chain generic map (length => 8) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => d_is_greater, ff_chain_out => delayed_d_is_greater); -- positive_q delay chain --------------------------------------------- POSITIVE_Q1_PIPELINE: ff_chain generic map (length => 7) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(1), ff_chain_out => delayed_positive_q1); POSITIVE_Q2_PIPELINE: ff_chain generic map (length => 7) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(2), ff_chain_out => delayed_positive_q2); POSITIVE_Q3_PIPELINE: ff_chain generic map (length => 7) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(3), ff_chain_out => delayed_positive_q3); --------------------------------------------- POSITIVE_Q4_PIPELINE: ff_chain generic map (length => 6) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(4), ff_chain_out => delayed_positive_q4); POSITIVE_Q5_PIPELINE: ff_chain generic map (length => 6) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(5), ff_chain_out => delayed_positive_q5); POSITIVE_Q6_PIPELINE: ff_chain generic map (length => 6) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(6), ff_chain_out => delayed_positive_q6); --------------------------------------------- POSITIVE_Q7_PIPELINE: ff_chain generic map (length => 5) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(7), ff_chain_out => delayed_positive_q7); POSITIVE_Q8_PIPELINE: ff_chain generic map (length => 5) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(8), ff_chain_out => delayed_positive_q8); POSITIVE_Q9_PIPELINE: ff_chain generic map (length => 5) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(9), ff_chain_out => delayed_positive_q9); --------------------------------------------- POSITIVE_Q10_PIPELINE: ff_chain generic map (length => 4) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(10), ff_chain_out => delayed_positive_q10); POSITIVE_Q11_PIPELINE: ff_chain generic map (length => 4) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(11), ff_chain_out => delayed_positive_q11); POSITIVE_Q12_PIPELINE: ff_chain generic map (length => 4) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(12), ff_chain_out => delayed_positive_q12); --------------------------------------------- POSITIVE_Q13_PIPELINE: ff_chain generic map (length => 3) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(13), ff_chain_out => delayed_positive_q13); POSITIVE_Q14_PIPELINE: ff_chain generic map (length => 3) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(14), ff_chain_out => delayed_positive_q14); POSITIVE_Q15_PIPELINE: ff_chain generic map (length => 3) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(15), ff_chain_out => delayed_positive_q15); --------------------------------------------- POSITIVE_Q16_PIPELINE: ff_chain generic map (length => 2) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(16), ff_chain_out => delayed_positive_q16); POSITIVE_Q17_PIPELINE: ff_chain generic map (length => 2) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(17), ff_chain_out => delayed_positive_q17); POSITIVE_Q18_PIPELINE: ff_chain generic map (length => 2) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(18), ff_chain_out => delayed_positive_q18); --------------------------------------------- POSITIVE_Q19_PIPELINE: ff_chain generic map (length => 1) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(19), ff_chain_out => delayed_positive_q19); POSITIVE_Q20_PIPELINE: ff_chain generic map (length => 1) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(20), ff_chain_out => delayed_positive_q20); POSITIVE_Q21_PIPELINE: ff_chain generic map (length => 1) port map ( clk => clk, reset => reset, enable => fixed_enable, ff_chain_in => positive_q(21), ff_chain_out => delayed_positive_q21); --------------------------------------------- -- d delay chain D_PIPELINE_REG1: data_register generic map (reg_width => divisor_width+3) port map (clk => clk, reset => reset, data_in => d, data_out => pipelined_d1); D_PIPELINE_REG2: data_register generic map (reg_width => divisor_width+3) port map (clk => clk, reset => reset, data_in => pipelined_d1, data_out => pipelined_d2); D_PIPELINE_REG3: data_register generic map (reg_width => divisor_width+3) port map (clk => clk, reset => reset, data_in => pipelined_d2, data_out => pipelined_d3); D_PIPELINE_REG4: data_register generic map (reg_width => divisor_width+3) port map (clk => clk, reset => reset, data_in => pipelined_d3, data_out => pipelined_d4); D_PIPELINE_REG5: data_register generic map (reg_width => divisor_width+3) port map (clk => clk, reset => reset, data_in => pipelined_d4, data_out => pipelined_d5); D_PIPELINE_REG6: data_register generic map (reg_width => divisor_width+3) port map (clk => clk, reset => reset, data_in => pipelined_d5, data_out => pipelined_d6); D_PIPELINE_REG7: data_register generic map (reg_width => divisor_width+3) port map (clk => clk, reset => reset, data_in => pipelined_d6, data_out => pipelined_d7); D_PIPELINE_REG8: data_register generic map (reg_width => divisor_width+3) port map (clk => clk, reset => reset, data_in => pipelined_d7, data_out => pipelined_d8); process(dvd, dvs, r, x, d, d_is_greater) begin -- normalized operands are added with a "sign bit" and a "buffer bit"; a new -- null LSB is added to avoid data loss in case of dividend pre-scaling: r(0) <-- x/2 x <= ("00" & dvd & '0'); d <= ("00" & dvs & '0'); positive_q(0) <= '0'; if (x < d) then d_is_greater <= '1'; else d_is_greater <= '0'; end if; if (d_is_greater = '1') then -- dividend pre-scaling: r(0) determination r(0) <= x; else r(0) <= ( '0' & x(26 downto 1) ); end if; end process; -------------------------------------------------- -- since r(0) is always positive, there's no need to select between 2 possibilities process(r, d) begin --positive_q(1) <= '1'; r(1) <= conv_std_logic_vector( (conv_integer(signed(r(0)&'0')) - conv_integer(signed(d))), 27 ); end process; -------------------------------------------------- ------------------------------------ -- INTERNAL PIPELINE: register 1 ------------------------------------ PIPELINE_REG1_R: data_register generic map (reg_width => division_rem_width+2) port map (clk => clk, reset => reset, data_in => r(1), data_out => pipelined_r1); -- k=2 process(pipelined_r1, pipelined_d1) begin if ( (pipelined_r1(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(1) <= '0'; r(2) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r1&'0')) + conv_integer(signed(pipelined_d1))), 27 ); else positive_q(1) <= '1'; r(2) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r1&'0')) - conv_integer(signed(pipelined_d1))), 27 ); end if; end process; -------------------------------------------------- -- k=3 process(r, pipelined_d1) begin if ( (r(2)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(2) <= '0'; r(3) <= conv_std_logic_vector( (conv_integer(signed(r(2)&'0')) + conv_integer(signed(pipelined_d1))), 27 ); else positive_q(2) <= '1'; r(3) <= conv_std_logic_vector( (conv_integer(signed(r(2)&'0')) - conv_integer(signed(pipelined_d1))), 27 ); end if; end process; -------------------------------------------------- -- k=4 process(r, pipelined_d1) begin if ( (r(3)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(3) <= '0'; r(4) <= conv_std_logic_vector( (conv_integer(signed(r(3)&'0')) + conv_integer(signed(pipelined_d1))), 27 ); else positive_q(3) <= '1'; r(4) <= conv_std_logic_vector( (conv_integer(signed(r(3)&'0')) - conv_integer(signed(pipelined_d1))), 27 ); end if; end process; -------------------------------------------------- ------------------------------------ -- INTERNAL PIPELINE: register 2 ------------------------------------ PIPELINE_REG2_R: data_register generic map (reg_width => division_rem_width+2) port map (clk => clk, reset => reset, data_in => r(4), data_out => pipelined_r4); -- k=5 process(pipelined_r4, pipelined_d2) begin if ( (pipelined_r4(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(4) <= '0'; r(5) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r4&'0')) + conv_integer(signed(pipelined_d2))), 27 ); else positive_q(4) <= '1'; r(5) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r4&'0')) - conv_integer(signed(pipelined_d2))), 27 ); end if; end process; -------------------------------------------------- -- k=6 process(r, pipelined_d2) begin if ( (r(5)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(5) <= '0'; r(6) <= conv_std_logic_vector( (conv_integer(signed(r(5)&'0')) + conv_integer(signed(pipelined_d2))), 27 ); else positive_q(5) <= '1'; r(6) <= conv_std_logic_vector( (conv_integer(signed(r(5)&'0')) - conv_integer(signed(pipelined_d2))), 27 ); end if; end process; -------------------------------------------------- -- k=7 process(r, pipelined_d2) begin if ( (r(6)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(6) <= '0'; r(7) <= conv_std_logic_vector( (conv_integer(signed(r(6)&'0')) + conv_integer(signed(pipelined_d2))), 27 ); else positive_q(6) <= '1'; r(7) <= conv_std_logic_vector( (conv_integer(signed(r(6)&'0')) - conv_integer(signed(pipelined_d2))), 27 ); end if; end process; -------------------------------------------------- ------------------------------------ -- INTERNAL PIPELINE: register 3 ------------------------------------ PIPELINE_REG3_R: data_register generic map (reg_width => division_rem_width+2) port map (clk => clk, reset => reset, data_in => r(7), data_out => pipelined_r7); -- k=8 process(pipelined_r7, pipelined_d3) begin if ( (pipelined_r7(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(7) <= '0'; r(8) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r7&'0')) + conv_integer(signed(pipelined_d3))), 27 ); else positive_q(7) <= '1'; r(8) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r7&'0')) - conv_integer(signed(pipelined_d3))), 27 ); end if; end process; -------------------------------------------------- -- k=9 process(r, pipelined_d3) begin if ( (r(8)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(8) <= '0'; r(9) <= conv_std_logic_vector( (conv_integer(signed(r(8)&'0')) + conv_integer(signed(pipelined_d3))), 27 ); else positive_q(8) <= '1'; r(9) <= conv_std_logic_vector( (conv_integer(signed(r(8)&'0')) - conv_integer(signed(pipelined_d3))), 27 ); end if; end process; -------------------------------------------------- -- k=10 process(r, pipelined_d3) begin if ( (r(9)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(9) <= '0'; r(10) <= conv_std_logic_vector( (conv_integer(signed(r(9)&'0')) + conv_integer(signed(pipelined_d3))), 27 ); else positive_q(9) <= '1'; r(10) <= conv_std_logic_vector( (conv_integer(signed(r(9)&'0')) - conv_integer(signed(pipelined_d3))), 27 ); end if; end process; -------------------------------------------------- ------------------------------------ -- INTERNAL PIPELINE: register 4 ------------------------------------ PIPELINE_REG4_R: data_register generic map (reg_width => division_rem_width+2) port map (clk => clk, reset => reset, data_in => r(10), data_out => pipelined_r10); -- k=11 process(pipelined_r10, pipelined_d4) begin if ( (pipelined_r10(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(10) <= '0'; r(11) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r10&'0')) + conv_integer(signed(pipelined_d4))), 27 ); else positive_q(10) <= '1'; r(11) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r10&'0')) - conv_integer(signed(pipelined_d4))), 27 ); end if; end process; -------------------------------------------------- -- k=12 process(r, pipelined_d4) begin if ( (r(11)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(11) <= '0'; r(12) <= conv_std_logic_vector( (conv_integer(signed(r(11)&'0')) + conv_integer(signed(pipelined_d4))), 27 ); else positive_q(11) <= '1'; r(12) <= conv_std_logic_vector( (conv_integer(signed(r(11)&'0')) - conv_integer(signed(pipelined_d4))), 27 ); end if; end process; -------------------------------------------------- -- k=13 process(r, pipelined_d4) begin if ( (r(12)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(12) <= '0'; r(13) <= conv_std_logic_vector( (conv_integer(signed(r(12)&'0')) + conv_integer(signed(pipelined_d4))), 27 ); else positive_q(12) <= '1'; r(13) <= conv_std_logic_vector( (conv_integer(signed(r(12)&'0')) - conv_integer(signed(pipelined_d4))), 27 ); end if; end process; -------------------------------------------------- ------------------------------------ -- INTERNAL PIPELINE: register 5 ------------------------------------ PIPELINE_REG5_R: data_register generic map (reg_width => division_rem_width+2) port map (clk => clk, reset => reset, data_in => r(13), data_out => pipelined_r13); -- k=14 process(pipelined_r13, pipelined_d5) begin if ( (pipelined_r13(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(13) <= '0'; r(14) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r13&'0')) + conv_integer(signed(pipelined_d5))), 27 ); else positive_q(13) <= '1'; r(14) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r13&'0')) - conv_integer(signed(pipelined_d5))), 27 ); end if; end process; -------------------------------------------------- -- k=15 process(r, pipelined_d5) begin if ( (r(14)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(14) <= '0'; r(15) <= conv_std_logic_vector( (conv_integer(signed(r(14)&'0')) + conv_integer(signed(pipelined_d5))), 27 ); else positive_q(14) <= '1'; r(15) <= conv_std_logic_vector( (conv_integer(signed(r(14)&'0')) - conv_integer(signed(pipelined_d5))), 27 ); end if; end process; -------------------------------------------------- -- k=16 process(r, pipelined_d5) begin if ( (r(15)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(15) <= '0'; r(16) <= conv_std_logic_vector( (conv_integer(signed(r(15)&'0')) + conv_integer(signed(pipelined_d5))), 27 ); else positive_q(15) <= '1'; r(16) <= conv_std_logic_vector( (conv_integer(signed(r(15)&'0')) - conv_integer(signed(pipelined_d5))), 27 ); end if; end process; -------------------------------------------------- ------------------------------------ -- INTERNAL PIPELINE: register 6 ------------------------------------ PIPELINE_REG6_R: data_register generic map (reg_width => division_rem_width+2) port map (clk => clk, reset => reset, data_in => r(16), data_out => pipelined_r16); -- k=17 process(pipelined_r16, pipelined_d6) begin if ( (pipelined_r16(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(16) <= '0'; r(17) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r16&'0')) + conv_integer(signed(pipelined_d6))), 27 ); else positive_q(16) <= '1'; r(17) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r16&'0')) - conv_integer(signed(pipelined_d6))), 27 ); end if; end process; -------------------------------------------------- -- k=18 process(r, pipelined_d6) begin if ( (r(17)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(17) <= '0'; r(18) <= conv_std_logic_vector( (conv_integer(signed(r(17)&'0')) + conv_integer(signed(pipelined_d6))), 27 ); else positive_q(17) <= '1'; r(18) <= conv_std_logic_vector( (conv_integer(signed(r(17)&'0')) - conv_integer(signed(pipelined_d6))), 27 ); end if; end process; -------------------------------------------------- -- k=19 process(r, pipelined_d6) begin if ( (r(18)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(18) <= '0'; r(19) <= conv_std_logic_vector( (conv_integer(signed(r(18)&'0')) + conv_integer(signed(pipelined_d6))), 27 ); else positive_q(18) <= '1'; r(19) <= conv_std_logic_vector( (conv_integer(signed(r(18)&'0')) - conv_integer(signed(pipelined_d6))), 27 ); end if; end process; -------------------------------------------------- ------------------------------------ -- INTERNAL PIPELINE: register 7 ------------------------------------ PIPELINE_REG7_R: data_register generic map (reg_width => division_rem_width+2) port map (clk => clk, reset => reset, data_in => r(19), data_out => pipelined_r19); -- k=20 process(pipelined_r19, pipelined_d7) begin if ( (pipelined_r19(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(19) <= '0'; r(20) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r19&'0')) + conv_integer(signed(pipelined_d7))), 27 ); else positive_q(19) <= '1'; r(20) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r19&'0')) - conv_integer(signed(pipelined_d7))), 27 ); end if; end process; -------------------------------------------------- -- k=21 process(r, pipelined_d7) begin if ( (r(20)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(20) <= '0'; r(21) <= conv_std_logic_vector( (conv_integer(signed(r(20)&'0')) + conv_integer(signed(pipelined_d7))), 27 ); else positive_q(20) <= '1'; r(21) <= conv_std_logic_vector( (conv_integer(signed(r(20)&'0')) - conv_integer(signed(pipelined_d7))), 27 ); end if; end process; -------------------------------------------------- -- k=22 process(r, pipelined_d7) begin if ( (r(21)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(21) <= '0'; r(22) <= conv_std_logic_vector( (conv_integer(signed(r(21)&'0')) + conv_integer(signed(pipelined_d7))), 27 ); else positive_q(21) <= '1'; r(22) <= conv_std_logic_vector( (conv_integer(signed(r(21)&'0')) - conv_integer(signed(pipelined_d7))), 27 ); end if; end process; -------------------------------------------------- ------------------------------------ -- INTERNAL PIPELINE: register 8 ------------------------------------ PIPELINE_REG8_R: data_register generic map (reg_width => division_rem_width+2) port map (clk => clk, reset => reset, data_in => r(22), data_out => pipelined_r22); triple_y <= ( conv_integer(signed(pipelined_d8&'0')) + conv_integer(signed(pipelined_d8)) ); -- k=23 process(pipelined_r22, pipelined_d8) begin if ( (pipelined_r22(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(22) <= '0'; r(23) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r22&'0')) + conv_integer(signed(pipelined_d8))), 27 ); else positive_q(22) <= '1'; r(23) <= conv_std_logic_vector( (conv_integer(signed(pipelined_r22&'0')) - conv_integer(signed(pipelined_d8))), 27 ); end if; end process; -------------------------------------------------- -- r(23), has been calculated; now special quantities are calculated to allow early r(25) determination double_x <= (r(23)&"00"); simple_x <= (r(23)&'0'); double_y <= (pipelined_d8&'0'); quad_y <= (pipelined_d8&"00"); r24_case_a <= conv_std_logic_vector( (conv_integer(signed(simple_x)) + conv_integer(signed(double_y))), 27 ); r24_case_b <= conv_std_logic_vector( (conv_integer(signed(simple_x)) + conv_integer(signed(pipelined_d8))), 27 ); r24_case_c <= conv_std_logic_vector( (conv_integer(signed(simple_x)) ), 27 ); r24_case_d <= conv_std_logic_vector( (conv_integer(signed(simple_x)) - conv_integer(signed(pipelined_d8))), 27 ); r25_case_a <= conv_std_logic_vector( (conv_integer(signed(double_x)) + triple_y), 27 ); r25_case_b <= conv_std_logic_vector( (conv_integer(signed(double_x)) + conv_integer(signed(pipelined_d8))), 27 ); r25_case_c <= conv_std_logic_vector( (conv_integer(signed(double_x)) - conv_integer(signed(pipelined_d8))), 27 ); r25_case_d <= conv_std_logic_vector( (conv_integer(signed(double_x)) - triple_y), 27 ); r25_case_e <= conv_std_logic_vector( (conv_integer(signed(double_x)) + conv_integer(signed(quad_y))), 27 ); r25_case_f <= conv_std_logic_vector( (conv_integer(signed(double_x)) + conv_integer(signed(double_y))), 27 ); r25_case_g <= conv_std_logic_vector( (conv_integer(signed(double_x))), 27 ); r25_case_h <= conv_std_logic_vector( (conv_integer(signed(double_x)) - conv_integer(signed(double_y))), 27 ); -- k=24 process(r) begin if ( (r(23)(26)) = '1' ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(23) <= '0'; else positive_q(23) <= '1'; end if; end process; -------------------------------------------------- -- k=25 process(r, r24_case_b, r24_case_d) begin if ( ((r(23)(26)) = '1') and (r24_case_b(26) = '1') ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) positive_q(24) <= '0'; elsif ( ((r(23)(26)) = '1') and (r24_case_b(26) = '0') ) then positive_q(24) <= '1'; elsif ( ((r(23)(26)) = '0') and (r24_case_d(26) = '1') ) then positive_q(24) <= '0'; else positive_q(24) <= '1'; end if; end process; -------------------------------------------------- positive_q(25) <= '1'; -- Signed Digit (SD) to binary form result conversion turned_positive_q(div_k_max) <= '0'; turned_positive_q(div_k_max-1) <= delayed_positive_q1; turned_positive_q(div_k_max-2) <= delayed_positive_q2; turned_positive_q(div_k_max-3) <= delayed_positive_q3; turned_positive_q(div_k_max-4) <= delayed_positive_q4; turned_positive_q(div_k_max-5) <= delayed_positive_q5; turned_positive_q(div_k_max-6) <= delayed_positive_q6; turned_positive_q(div_k_max-7) <= delayed_positive_q7; turned_positive_q(div_k_max-8) <= delayed_positive_q8; turned_positive_q(div_k_max-9) <= delayed_positive_q9; turned_positive_q(div_k_max-10) <= delayed_positive_q10; turned_positive_q(div_k_max-11) <= delayed_positive_q11; turned_positive_q(div_k_max-12) <= delayed_positive_q12; turned_positive_q(div_k_max-13) <= delayed_positive_q13; turned_positive_q(div_k_max-14) <= delayed_positive_q14; turned_positive_q(div_k_max-15) <= delayed_positive_q15; turned_positive_q(div_k_max-16) <= delayed_positive_q16; turned_positive_q(div_k_max-17) <= delayed_positive_q17; turned_positive_q(div_k_max-18) <= delayed_positive_q18; turned_positive_q(div_k_max-19) <= delayed_positive_q19; turned_positive_q(div_k_max-20) <= delayed_positive_q20; turned_positive_q(div_k_max-21) <= delayed_positive_q21; turned_positive_q(div_k_max-22) <= positive_q(22); turned_positive_q(div_k_max-23) <= positive_q(23); turned_positive_q(div_k_max-24) <= positive_q(24); turned_positive_q(div_k_max-25) <= positive_q(25); q <= (turned_positive_q); -------------------------------------------------- -- remainder and quotient selection -- note that bits 26 and 25 in the last remainder can be discarded, since remainder is surely less than divider, which has MSB in position 24 process(q, delayed_d_is_greater, temp_q, r, r24_case_a, r24_case_b, r24_case_c, r24_case_d, r25_case_a, r25_case_b, r25_case_c, r25_case_d, r25_case_e, r25_case_f, r25_case_g, r25_case_h) begin if (delayed_d_is_greater = '1') then -- remainder is r(24) if ( ((r(23)(26)) = '1') and (r24_case_b(26) = '1') ) then -- r(i-1) < 0 => 2r(i-1) < 0 (this way only sign bit check is needed) temp_q <= (q(div_k_max downto 1) & '0'); temp_remainder <= r24_case_a; elsif ( ((r(23)(26)) = '1') and (r24_case_b(26) = '0') ) then temp_q <= q; temp_remainder <= r24_case_b; elsif ( ((r(23)(26)) = '0') and (r24_case_d(26) = '1') ) then temp_q <= (q(div_k_max downto 1) & '0'); temp_remainder <= r24_case_c; else temp_remainder <= r24_case_d; temp_q <= q; end if; vector_q <= temp_q(25 downto 1) ; -- 0.1xxx else -- remainder is r(25) if ( (r(23)(26) = '1') and (r24_case_b(26) = '1') and (r25_case_a(26) = '1') ) then temp_q <= (q(div_k_max downto 1) & '0'); temp_remainder <= r25_case_e; elsif ( (r(23)(26) = '1') and (r24_case_b(26) = '0') and (r25_case_b(26) = '1') ) then temp_q <= (q(div_k_max downto 1) & '0'); temp_remainder <= r25_case_f; elsif ( (r(23)(26) = '0') and (r24_case_d(26) = '1') and (r25_case_c(26) = '1') ) then temp_q <= (q(div_k_max downto 1) & '0'); temp_remainder <= r25_case_g; elsif ( (r(23)(26) = '0') and (r24_case_d(26) = '0') and (r25_case_d(26) = '1') ) then temp_q <= (q(div_k_max downto 1) & '0'); temp_remainder <= r25_case_h; elsif ( (r(23)(26) = '1') and (r24_case_b(26) = '1') and (r25_case_a(26) = '0') ) then temp_q <= q; temp_remainder <= r25_case_a; elsif ( (r(23)(26) = '1') and (r24_case_b(26) = '0') and (r25_case_b(26) = '0') ) then temp_q <= q; temp_remainder <= r25_case_b; elsif ( (r(23)(26) = '0') and (r24_case_d(26) = '1') and (r25_case_c(26) = '0') ) then temp_q <= q; temp_remainder <= r25_case_c; else temp_q <= q; temp_remainder <= r25_case_d; end if; vector_q <= temp_q(24 downto 0) ; -- 1.xxxx end if; end process; ------------------------------------------------------------------------ quot <= vector_q; rest <= temp_remainder(24 downto 0); ----------------------------------------------------------------------------------------------------------------- end rtl;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; package debounce_pkg is component debounce is generic( counter_size : INTEGER := 19 --counter size (19 bits gives 10.5ms with 50MHz clock) ); port( clk : IN STD_LOGIC; --input clock button : IN STD_LOGIC; --input signal to be debounced result : OUT STD_LOGIC --debounced signal ); end component; end package;
-- file: pll_exdes.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ -- Clocking wizard example design ------------------------------------------------------------------------------ -- This example design instantiates the created clocking network, where each -- output clock drives a counter. The high bit of each counter is ported. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity pll_exdes is generic ( TCQ : in time := 100 ps); port (-- Clock in ports CLK_IN1 : in std_logic; -- Reset that only drives logic in example design COUNTER_RESET : in std_logic; CLK_OUT : out std_logic_vector(1 downto 1) ; -- High bits of counters driven by clocks COUNT : out std_logic; -- Status and control signals RESET : in std_logic; LOCKED : out std_logic ); end pll_exdes; architecture xilinx of pll_exdes is -- Parameters for the counters --------------------------------- -- Counter width constant C_W : integer := 16; -- When the clock goes out of lock, reset the counters signal locked_int : std_logic; signal reset_int : std_logic := '0'; -- Declare the clocks and counter signal clk : std_logic; signal clk_int : std_logic; signal clk_n : std_logic; signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0'); signal rst_sync : std_logic; signal rst_sync_int : std_logic; signal rst_sync_int1 : std_logic; signal rst_sync_int2 : std_logic; component pll is port (-- Clock in ports CLK_IN1 : in std_logic; -- Clock out ports CLK_OUT1 : out std_logic; -- Status and control signals RESET : in std_logic; LOCKED : out std_logic ); end component; begin -- Alias output to internally used signal LOCKED <= locked_int; -- When the clock goes out of lock, reset the counters reset_int <= (not locked_int) or RESET or COUNTER_RESET; process (clk, reset_int) begin if (reset_int = '1') then rst_sync <= '1'; rst_sync_int <= '1'; rst_sync_int1 <= '1'; rst_sync_int2 <= '1'; elsif (clk 'event and clk='1') then rst_sync <= '0'; rst_sync_int <= rst_sync; rst_sync_int1 <= rst_sync_int; rst_sync_int2 <= rst_sync_int1; end if; end process; -- Instantiation of the clocking network ---------------------------------------- clknetwork : pll port map (-- Clock in ports CLK_IN1 => CLK_IN1, -- Clock out ports CLK_OUT1 => clk_int, -- Status and control signals RESET => RESET, LOCKED => locked_int); clk_n <= not clk; clkout_oddr : ODDR2 port map (Q => CLK_OUT(1), C0 => clk, C1 => clk_n, CE => '1', D0 => '1', D1 => '0', R => '0', S => '0'); -- Connect the output clocks to the design ------------------------------------------- clk <= clk_int; -- Output clock sampling ------------------------------------- process (clk, rst_sync_int2) begin if (rst_sync_int2 = '1') then counter <= (others => '0') after TCQ; elsif (rising_edge(clk)) then counter <= counter + 1 after TCQ; end if; end process; -- alias the high bit to the output COUNT <= counter(C_W-1); end xilinx;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: - -- Engineer: Jochem Govers -- -- Create Date: 13:00:21 05/13/2010 -- Design Name: -- Module Name: bscan_spi - Behavioral -- Project Name: -- Target Devices: Spartan 3e 100/250/500 VQ100 -- Tool versions: ISE 11.4 -- Description: a simple implementation of the BSCAN_SPARTAN3E module to access -- external SPI Flash via JTAG. -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added header recognation of header and TDO alignment (requires -- 4 bytes of preamble and 1 byte post). Based on design -- of xc3sprog (changes made to CS handling and header length). -- Additional Comments: tested on Butterfly One with xc3s250e -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity bscan_spi is Port ( SPI_MISO : in STD_LOGIC; SPI_MOSI : inout STD_LOGIC; SPI_CS : inout STD_LOGIC; SPI_SCK : inout STD_LOGIC); end bscan_spi; architecture Behavioral of bscan_spi is --component BSCAN_SPARTAN6 -- port (CAPTURE : out STD_ULOGIC; -- DRCK1 : out STD_ULOGIC; -- DRCK2 : out STD_ULOGIC; -- RESET : out STD_ULOGIC; -- SEL1 : out STD_ULOGIC; -- SEL2 : out STD_ULOGIC; -- SHIFT : out STD_ULOGIC; -- TDI : out STD_ULOGIC; -- UPDATE : out STD_ULOGIC; -- TDO1 : in STD_ULOGIC; -- TDO2 : in STD_ULOGIC); -- end component; signal user_CAPTURE : std_ulogic; signal user_DRCK1 : std_ulogic; signal user_DRCK2 : std_ulogic; signal user_RESET : std_ulogic; signal user_SEL1 : std_ulogic; signal user_SEL2 : std_ulogic; signal user_SHIFT : std_ulogic; signal user_TDI : std_ulogic; signal user_UPDATE : std_ulogic; signal user_TDO1 : std_ulogic; signal user_TDO2 : std_ulogic; signal tdi_mem : std_logic_vector(31 downto 0); signal tdo_mem : std_logic_vector(7 downto 0); signal len : std_logic_vector(15 downto 0); signal CS_GO_PREP : std_logic; signal CS_GO : std_logic; signal CS_STOP_PREP : std_logic; signal CS_STOP : std_logic; signal reset : std_logic; signal have_header : std_logic; begin reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1); BS : BSCAN_SPARTAN6 port map ( CAPTURE => user_CAPTURE, DRCK => user_DRCK1, --DRCK2 => user_DRCK2, RESET => user_RESET, SEL => user_SEL1, --SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TDO => user_TDO1 --TDO2 => user_TDO2 ); process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1) begin -- default assignments (put outputs in High-Z state if not in USER1) --user_TDO1<=SPI_MISO; user_TDO1<=tdo_mem(tdo_mem'high); SPI_MOSI<='Z'; SPI_SCK<='Z'; SPI_CS<='Z'; if (user_SEL1='1') then SPI_MOSI<='0'; SPI_SCK<='1'; --SPI_CS<='1'; SPI_CS<=not(CS_GO and not(CS_STOP)); if(user_SHIFT='1') then SPI_SCK<=user_DRCK1; --SPI_CS<='0'; SPI_MOSI<=user_TDI; end if; end if; end process; process(user_DRCK1) variable i : integer; begin if(reset = '1')then have_header<='0'; CS_GO<='0'; elsif(falling_edge(user_DRCK1))then if ( have_header='0') then if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then len <= tdi_mem(15 downto 0); have_header <= '1'; if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then CS_GO <= '1'; end if; end if; elsif (len /= 0) then len <= len - 1; end if; end if; end process; process(user_DRCK1) variable i : integer; variable j : integer; begin if(reset ='1') then tdo_mem<=(others => '0'); tdi_mem<=(others => '0'); CS_STOP<='0'; elsif(rising_edge(user_DRCK1))then tdi_mem(0)<=user_TDI; for j in 1 to tdi_mem'high loop tdi_mem(j)<=tdi_mem(j-1); end loop; tdo_mem(0)<=SPI_MISO; for i in 1 to tdo_mem'high loop tdo_mem(i)<=tdo_mem(i-1); end loop; if(CS_GO='1' and len=0)then CS_STOP<='1'; end if; end if; end process; end Behavioral;
library ieee; use ieee.std_logic_1164.all; entity writeback is port( AluOutW, ReadDataW: in std_logic_vector(31 downto 0); MemToReg: in std_logic; ResultW: out std_logic_vector(31 downto 0)); end entity; architecture wb_arq of writeback is component mux2 generic (MAX : integer := 32); port ( d0, d1: in std_logic_vector((MAX-1) downto 0); s: in std_logic; y: out std_logic_vector((MAX-1) downto 0)); end component; begin mux2_1: mux2 port map ( d0 => AluOutW, d1 => ReadDataW, s => MemToReg, y => ResultW); --salida end architecture;
library ieee; use ieee.std_logic_1164.all; entity writeback is port( AluOutW, ReadDataW: in std_logic_vector(31 downto 0); MemToReg: in std_logic; ResultW: out std_logic_vector(31 downto 0)); end entity; architecture wb_arq of writeback is component mux2 generic (MAX : integer := 32); port ( d0, d1: in std_logic_vector((MAX-1) downto 0); s: in std_logic; y: out std_logic_vector((MAX-1) downto 0)); end component; begin mux2_1: mux2 port map ( d0 => AluOutW, d1 => ReadDataW, s => MemToReg, y => ResultW); --salida end architecture;
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY control IS PORT ( instruction : IN std_logic_vector(5 downto 0); RegDst : OUT std_logic; Branch : OUT std_logic_vector(1 downto 0); MemtoReg : OUT std_logic; ALUOp : OUT std_logic_vector(3 downto 0); MemWrite : OUT std_logic; ALUSrc : OUT std_logic; RegWrite : OUT std_logic ); END control; ARCHITECTURE behavior OF control IS BEGIN WITH instruction SELECT -- 00 = Branch Branch <= "10" WHEN "000000", -- 3 downto 0 = equal zero or not equal zero "11" WHEN "001111", "00" WHEN OTHERS; WITH instruction SELECT -- 01 = ALU ALUOp <= "0000" WHEN "010000", -- 3 downto 0 = ALU-Code "0001" WHEN "010001", "0010" WHEN "010010", "0110" WHEN "010110", "0111" WHEN "010111", "1100" WHEN "011100", "1111" WHEN "100000", "1111" WHEN OTHERS; WITH instruction SELECT MemWrite <= '1' WHEN "100000", '0' WHEN OTHERS; WITH instruction SELECT MemtoReg <= '1' WHEN "100001", '0' WHEN OTHERS; WITH instruction SELECT ALUSrc <= '1' WHEN "100000", '1' WHEN "100001", '0' WHEN OTHERS; WITH instruction SELECT RegWrite <= '1' WHEN "010000", '1' WHEN "010001", '1' WHEN "010010", '1' WHEN "010110", '1' WHEN "010111", '1' WHEN "011100", '0' WHEN OTHERS; WITH instruction SELECT RegDst <= '1' WHEN "010000", '1' WHEN "010001", '1' WHEN "010010", '1' WHEN "010110", '1' WHEN "010111", '1' WHEN "011100", '0' WHEN OTHERS; END behavior;
-- $Id: serport_1clock.vhd 438 2011-12-11 23:40:52Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation, either version 2, or at your option any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for complete details. -- ------------------------------------------------------------------------------ -- Module Name: serport_1clock - syn -- Description: serial port: serial port module, 1 clock domain -- -- Dependencies: serport_uart_rxtx_ab -- serport_xonrx -- serport_xontx -- memlib/fifo_1c_dram -- Test bench: - -- Target Devices: generic -- Tool versions: xst 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri -- 2011-11-13 424 13.1 O40d xc3s1000-4 157 337 64 232 s 9.9 -- -- Revision History: -- Date Rev Version Comment -- 2011-12-10 438 1.0.2 internal reset on abact -- 2011-12-09 437 1.0.1 rename stat->moni port -- 2011-11-13 424 1.0 Initial version -- 2011-10-23 419 0.5 First draft ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.serport.all; use work.memlib.all; entity serport_1clock is -- serial port module, 1 clock domain generic ( CDWIDTH : positive := 13; -- clk divider width CDINIT : natural := 15; -- clk divider initial/reset setting RXFAWIDTH : natural := 5; -- rx fifo address width TXFAWIDTH : natural := 5); -- tx fifo address width port ( CLK : in slbit; -- clock CE_MSEC : in slbit; -- 1 msec clock enable RESET : in slbit; -- reset ENAXON : in slbit; -- enable xon/xoff handling ENAESC : in slbit; -- enable xon/xoff escaping RXDATA : out slv8; -- receiver data out RXVAL : out slbit; -- receiver data valid RXHOLD : in slbit; -- receiver data hold TXDATA : in slv8; -- transmit data in TXENA : in slbit; -- transmit data enable TXBUSY : out slbit; -- transmit busy MONI : out serport_moni_type; -- serport monitor port RXSD : in slbit; -- receive serial data (uart view) TXSD : out slbit; -- transmit serial data (uart view) RXRTS_N : out slbit; -- receive rts (uart view, act.low) TXCTS_N : in slbit -- transmit cts (uart view, act.low) ); end serport_1clock; architecture syn of serport_1clock is signal R_RXOK : slbit := '1'; signal RESET_INT : slbit := '0'; signal UART_RXDATA : slv8 := (others=>'0'); signal UART_RXVAL : slbit := '0'; signal UART_TXDATA : slv8 := (others=>'0'); signal UART_TXENA : slbit := '0'; signal UART_TXBUSY : slbit := '0'; signal XONTX_TXENA : slbit := '0'; signal XONTX_TXBUSY : slbit := '0'; signal RXFIFO_DI : slv8 := (others=>'0'); signal RXFIFO_ENA : slbit := '0'; signal RXFIFO_BUSY : slbit := '0'; signal RXFIFO_SIZE : slv(RXFAWIDTH downto 0) := (others=>'0'); signal TXFIFO_DO : slv8 := (others=>'0'); signal TXFIFO_VAL : slbit := '0'; signal TXFIFO_HOLD : slbit := '0'; signal RXERR : slbit := '0'; signal RXOVR : slbit := '0'; signal RXACT : slbit := '0'; signal ABACT : slbit := '0'; signal ABDONE : slbit := '0'; signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0'); signal TXOK : slbit := '0'; signal RXOK : slbit := '0'; begin assert CDWIDTH<=16 report "assert(CDWIDTH<=16): max width of UART clock divider" severity failure; UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo generic map ( CDWIDTH => CDWIDTH, CDINIT => CDINIT) port map ( CLK => CLK, CE_MSEC => CE_MSEC, RESET => RESET, RXSD => RXSD, RXDATA => UART_RXDATA, RXVAL => UART_RXVAL, RXERR => RXERR, RXACT => RXACT, TXSD => TXSD, TXDATA => UART_TXDATA, TXENA => UART_TXENA, TXBUSY => UART_TXBUSY, ABACT => ABACT, ABDONE => ABDONE, ABCLKDIV => ABCLKDIV ); RESET_INT <= RESET or ABACT; XONRX : serport_xonrx -- xon/xoff logic rx path port map ( CLK => CLK, RESET => RESET_INT, ENAXON => ENAXON, ENAESC => ENAESC, UART_RXDATA => UART_RXDATA, UART_RXVAL => UART_RXVAL, RXDATA => RXFIFO_DI, RXVAL => RXFIFO_ENA, RXHOLD => RXFIFO_BUSY, RXOVR => RXOVR, TXOK => TXOK ); XONTX : serport_xontx -- xon/xoff logic tx path port map ( CLK => CLK, RESET => RESET_INT, ENAXON => ENAXON, ENAESC => ENAESC, UART_TXDATA => UART_TXDATA, UART_TXENA => XONTX_TXENA, UART_TXBUSY => XONTX_TXBUSY, TXDATA => TXFIFO_DO, TXENA => TXFIFO_VAL, TXBUSY => TXFIFO_HOLD, RXOK => RXOK, TXOK => TXOK ); RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based generic map ( AWIDTH => RXFAWIDTH, DWIDTH => 8) port map ( CLK => CLK, RESET => RESET_INT, DI => RXFIFO_DI, ENA => RXFIFO_ENA, BUSY => RXFIFO_BUSY, DO => RXDATA, VAL => RXVAL, HOLD => RXHOLD, SIZE => RXFIFO_SIZE ); TXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based generic map ( AWIDTH => TXFAWIDTH, DWIDTH => 8) port map ( CLK => CLK, RESET => RESET_INT, DI => TXDATA, ENA => TXENA, BUSY => TXBUSY, DO => TXFIFO_DO, VAL => TXFIFO_VAL, HOLD => TXFIFO_HOLD, SIZE => open ); -- receive back preasure -- on if fifo more than 3/4 full -- off if fifo less than 1/2 full proc_rxok: process (CLK) constant rxsize_rxok_off : slv3 := "011"; constant rxsize_rxok_on : slv3 := "010"; variable rxsize_msb : slv3 := "000"; begin if rising_edge(CLK) then if RESET_INT = '1' then R_RXOK <= '1'; else rxsize_msb := RXFIFO_SIZE(RXFAWIDTH downto RXFAWIDTH-2); if unsigned(rxsize_msb) >= unsigned(rxsize_rxok_off) then R_RXOK <= '0'; elsif unsigned(rxsize_msb) <= unsigned(rxsize_rxok_on) then R_RXOK <= '1'; end if; end if; end if; end process proc_rxok; RXOK <= R_RXOK; RXRTS_N <= not R_RXOK; proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY) begin if TXCTS_N = '0' then -- transmit cts asserted UART_TXENA <= XONTX_TXENA; XONTX_TXBUSY <= UART_TXBUSY; else -- transmit cts not asserted UART_TXENA <= '0'; XONTX_TXBUSY <= '1'; end if; end process proc_cts; MONI.rxerr <= RXERR; MONI.rxovr <= RXOVR; MONI.rxact <= RXACT; MONI.txact <= UART_TXBUSY; MONI.abact <= ABACT; MONI.abdone <= ABDONE; MONI.rxok <= RXOK; MONI.txok <= TXOK; proc_abclkdiv: process (ABCLKDIV) begin MONI.abclkdiv <= (others=>'0'); MONI.abclkdiv(ABCLKDIV'range) <= ABCLKDIV; end process proc_abclkdiv; end syn;
------------------------------------------------------------------------------- -- axi_vdma_mngr ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_vdma_mngr.vhd -- Description: This entity is the top level entity for the AXI VDMA Controller -- manager. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_vdma.vhd -- |- axi_vdma_pkg.vhd -- |- axi_vdma_intrpt.vhd -- |- axi_vdma_rst_module.vhd -- | |- axi_vdma_reset.vhd (mm2s) -- | | |- axi_vdma_cdc.vhd -- | |- axi_vdma_reset.vhd (s2mm) -- | | |- axi_vdma_cdc.vhd -- | -- |- axi_vdma_reg_if.vhd -- | |- axi_vdma_lite_if.vhd -- | |- axi_vdma_cdc.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_vdma_sg_cdc.vhd (mm2s) -- |- axi_vdma_vid_cdc.vhd (mm2s) -- |- axi_vdma_fsync_gen.vhd (mm2s) -- |- axi_vdma_sof_gen.vhd (mm2s) -- |- axi_vdma_reg_module.vhd (mm2s) -- | |- axi_vdma_register.vhd (mm2s) -- | |- axi_vdma_regdirect.vhd (mm2s) -- |- axi_vdma_mngr.vhd (mm2s) -- | |- axi_vdma_sg_if.vhd (mm2s) -- | |- axi_vdma_sm.vhd (mm2s) -- | |- axi_vdma_cmdsts_if.vhd (mm2s) -- | |- axi_vdma_vidreg_module.vhd (mm2s) -- | | |- axi_vdma_sgregister.vhd (mm2s) -- | | |- axi_vdma_vregister.vhd (mm2s) -- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s) -- | | |- axi_vdma_blkmem.vhd (mm2s) -- | |- axi_vdma_genlock_mngr.vhd (mm2s) -- | |- axi_vdma_genlock_mux.vhd (mm2s) -- | |- axi_vdma_greycoder.vhd (mm2s) -- |- axi_vdma_mm2s_linebuf.vhd (mm2s) -- | |- axi_vdma_sfifo_autord.vhd (mm2s) -- | |- axi_vdma_afifo_autord.vhd (mm2s) -- | |- axi_vdma_skid_buf.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (mm2s) -- | -- |- axi_vdma_sg_cdc.vhd (s2mm) -- |- axi_vdma_vid_cdc.vhd (s2mm) -- |- axi_vdma_fsync_gen.vhd (s2mm) -- |- axi_vdma_sof_gen.vhd (s2mm) -- |- axi_vdma_reg_module.vhd (s2mm) -- | |- axi_vdma_register.vhd (s2mm) -- | |- axi_vdma_regdirect.vhd (s2mm) -- |- axi_vdma_mngr.vhd (s2mm) -- | |- axi_vdma_sg_if.vhd (s2mm) -- | |- axi_vdma_sm.vhd (s2mm) -- | |- axi_vdma_cmdsts_if.vhd (s2mm) -- | |- axi_vdma_vidreg_module.vhd (s2mm) -- | | |- axi_vdma_sgregister.vhd (s2mm) -- | | |- axi_vdma_vregister.vhd (s2mm) -- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm) -- | | |- axi_vdma_blkmem.vhd (s2mm) -- | |- axi_vdma_genlock_mngr.vhd (s2mm) -- | |- axi_vdma_genlock_mux.vhd (s2mm) -- | |- axi_vdma_greycoder.vhd (s2mm) -- |- axi_vdma_s2mm_linebuf.vhd (s2mm) -- | |- axi_vdma_sfifo_autord.vhd (s2mm) -- | |- axi_vdma_afifo_autord.vhd (s2mm) -- | |- axi_vdma_skid_buf.vhd (s2mm) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL) -- |- axi_sg_v3_00_a.axi_sg.vhd -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_vdma_v6_2; use axi_vdma_v6_2.axi_vdma_pkg.all; ------------------------------------------------------------------------------- entity axi_vdma_mngr is generic( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1; -- Depth of DataMover command FIFO C_INCLUDE_SF : integer range 0 to 1 := 0; -- Include or exclude store and forward module -- 0 = excluded -- 1 = included C_USE_FSYNC : integer range 0 to 1 := 0; -- Specifies DMA oeration synchronized to frame sync input -- 0 = Free running -- 1 = Fsync synchronous --C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 -- --C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 -- C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1; -- Setting this make core backward compatible to 2012.4 version in terms of ports and registers C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1; -- Enable debug information bit 0 C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1; -- Enable debug information bit 1 C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1; -- Enable debug information bit 2 C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1; -- Enable debug information bit 3 C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1; -- Enable debug information bit 4 C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1; -- Enable debug information bit 5 C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1; -- Enable debug information bit 6 C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1; -- Enable debug information bit 7 C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1; -- Enable debug information bit 8 C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1; -- Enable debug information bit 9 C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1; -- Enable debug information bit 10 C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1; -- Enable debug information bit 11 C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1; -- Enable debug information bit 12 C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1; -- Enable debug information bit 13 C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1; -- Enable debug information bit 14 C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1; -- Enable debug information bit 15 C_ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0; -- CR591965 -- Specifies VDMA Flush on Frame sync enabled -- 0 = Disabled -- 1 = Enabled C_NUM_FSTORES : integer range 1 to 32 := 1; -- Number of Frame Stores C_GENLOCK_MODE : integer range 0 to 3 := 0; -- Specifies Gen-Lock Mode of operation -- 0 = Master - Channel configured to be Gen-Lock Master -- 1 = Slave - Channel configured to be Gen-Lock Slave C_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1; -- Number of Gen-Lock masters capable of controlling Gen-Lock Slave --C_GENLOCK_REPEAT_EN : integer range 0 to 1 := 0; -- CR591965 -- In flush on frame sync mode specifies whether frame number -- will increment on error'ed frame or repeat error'ed frame -- 0 = increment frame -- 1 = repeat frame ----------------------------------------------------------------------- C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1; -- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE -- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE -- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE. ----------------------------------------------------------------------- C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0; -- Enable internal genlock bus -- 0 = disable internal genlock bus -- 1 = enable internal genlock bus C_EXTEND_DM_COMMAND : integer range 0 to 1 := 0; -- Extend datamover command by padding BTT with 1's for -- indeterminate BTT mode ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_INCLUDE_SG : integer range 0 to 1 := 1 ; -- Include or Exclude Scatter Gather Engine -- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode) -- 1 = Include Scatter Gather Engine C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- AXI Master Stream in for descriptor fetch ----------------------------------------------------------------------- -- Memory Map Parameters ----------------------------------------------------------------------- C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Read Port C_DM_STATUS_WIDTH : integer := 8 ; -- CR608521 -- DataMover status width - is based on mode of operation C_S2MM_SOF_ENABLE : integer range 0 to 1 := 0; C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0; C_INCLUDE_MM2S : integer range 0 to 1 := 1; -- Include or exclude MM2S primary data path -- 0 = Exclude MM2S primary data path -- 1 = Include MM2S primary data path C_INCLUDE_S2MM : integer range 0 to 1 := 1; -- Include or exclude S2MM primary data path -- 0 = Exclude S2MM primary data path -- 1 = Include S2MM primary data path C_FAMILY : string := "virtex7" -- Target FPGA Device Family ); port ( -- Secondary Clock and Reset prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- soft_reset : in std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- -- Control and Status -- run_stop : in std_logic ; -- dmasr_halt : in std_logic ; -- dmacr_repeat_en : in std_logic ; -- sync_enable : in std_logic ; -- regdir_idle : in std_logic ; -- ftch_idle : in std_logic ; -- halt : in std_logic ; -- halt_cmplt : in std_logic ; -- halted_clr : out std_logic ; -- halted_set : out std_logic ; -- idle_set : out std_logic ; -- idle_clr : out std_logic ; -- chnl_current_frame : out std_logic_vector (FRAME_NUMBER_WIDTH-1 downto 0) ; -- genlock_pair_frame : out std_logic_vector (FRAME_NUMBER_WIDTH-1 downto 0) ; -- frame_number : out std_logic_vector (FRAME_NUMBER_WIDTH-1 downto 0) ; -- new_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0); -- new_curdesc_wren : out std_logic ; -- stop : out std_logic ; -- all_idle : out std_logic ; -- cmdsts_idle : out std_logic ; -- ftchcmdsts_idle : out std_logic ; -- fsize_mismatch_err_flag : out std_logic ; -- CR591965 fsize_mismatch_err : out std_logic ; -- CR591965 lsize_mismatch_err : out std_logic ; -- CR591965 lsize_more_mismatch_err : out std_logic ; -- CR591965 s2mm_fsize_mismatch_err_s : out std_logic ; -- CR591965 mm2s_fsize_mismatch_err_s : in std_logic ; -- CR591965 mm2s_fsize_mismatch_err_m : in std_logic ; -- CR591965 -- -- Register direct support -- prmtr_updt_complete : in std_logic ; -- reg_module_vsize : in std_logic_vector -- (VSIZE_DWIDTH-1 downto 0) ; -- reg_module_hsize : in std_logic_vector -- (HSIZE_DWIDTH-1 downto 0) ; -- reg_module_stride : in std_logic_vector -- (STRIDE_DWIDTH-1 downto 0) ; -- reg_module_frmdly : in std_logic_vector -- (FRMDLY_DWIDTH-1 downto 0) ; -- reg_module_strt_addr : in STARTADDR_ARRAY_TYPE -- (0 to C_NUM_FSTORES - 1) ; -- -- mstr_pntr_ref : in std_logic_vector(3 downto 0) ; -- (master in control) genlock_select : in std_logic ; -- frame_ptr_ref : in std_logic_vector -- (FRAME_NUMBER_WIDTH-1 downto 0) ; -- frame_ptr_in : in std_logic_vector -- ((C_GENLOCK_NUM_MASTERS -- *NUM_FRM_STORE_WIDTH)-1 downto 0) ; -- frame_ptr_out : out std_logic_vector -- (NUM_FRM_STORE_WIDTH-1 downto 0) ; -- internal_frame_ptr_in : in std_logic_vector -- (NUM_FRM_STORE_WIDTH-1 downto 0) ; -- -- update_frmstore : out std_logic ; -- CR582182 frmstr_err_addr : out std_logic_vector -- (FRAME_NUMBER_WIDTH-1 downto 0) ; -- CR582182 valid_frame_sync : out std_logic ; -- valid_frame_sync_cmb : out std_logic ; -- valid_video_prmtrs : out std_logic ; -- parameter_update : out std_logic ; -- tailpntr_updated : in std_logic ; -- frame_sync : in std_logic ; -- circular_prk_mode : in std_logic ; -- line_buffer_empty : in std_logic ; -- dwidth_fifo_pipe_empty : in std_logic ; -- crnt_vsize : out std_logic_vector -- (VSIZE_DWIDTH-1 downto 0) ; -- CR575884 num_frame_store : in std_logic_vector -- (NUM_FRM_STORE_WIDTH-1 downto 0) ; -- all_lines_xfred : in std_logic ; -- CR616211 all_lasts_rcvd : in std_logic ; -- s2mm_strm_all_lines_rcvd : in std_logic ; -- drop_fsync_d_pulse_gen_fsize_less_err : in std_logic ; -- s2mm_fsize_more_or_sof_late : in std_logic ; -- s2mm_dmasr_lsize_less_err : in std_logic ; -- s2mm_fsync_core : in std_logic ; s2mm_fsync_out_m : in std_logic ; mm2s_fsync_out_m : in std_logic ; capture_hsize_at_uf_err : out std_logic_vector(15 downto 0) ; -- Test Vector signals -- tstvect_err : out std_logic ; -- tstvect_fsync : out std_logic ; -- tstvect_frame : out std_logic_vector -- (FRAME_NUMBER_WIDTH-1 downto 0) ; -- tstvect_frm_ptr_out : out std_logic_vector -- (FRAME_NUMBER_WIDTH-1 downto 0) ; -- mstrfrm_tstsync_out : out std_logic ; -- -- -- AXI Stream Signals -- packet_sof : in std_logic ; -- -- -- Primary DMA Errors -- dma_interr_set_minus_frame_errors : out std_logic ; -- dma_interr_set : out std_logic ; -- dma_slverr_set : out std_logic ; -- dma_decerr_set : out std_logic ; -- -- -- SG Descriptor Fetch AXI Stream In -- m_axis_ftch_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_ftch_tvalid : in std_logic ; -- m_axis_ftch_tready : out std_logic ; -- m_axis_ftch_tlast : in std_logic ; -- -- -- User Command Interface Ports (AXI Stream) -- s_axis_cmd_tvalid : out std_logic ; -- s_axis_cmd_tready : in std_logic ; -- s_axis_cmd_tdata : out std_logic_vector -- ((C_M_AXI_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- User Status Interface Ports (AXI Stream) -- m_axis_sts_tvalid : in std_logic ; -- m_axis_sts_tready : out std_logic ; -- m_axis_sts_tdata : in std_logic_vector -- (C_DM_STATUS_WIDTH-1 downto 0); -- CR608521 m_axis_sts_tkeep : in std_logic_vector -- ((C_DM_STATUS_WIDTH/8)-1 downto 0) ; -- CR608521 err : in std_logic ; -- -- ftch_err : in std_logic -- ); end axi_vdma_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_vdma_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Zero vector for tying off unused inputs constant ZERO_VALUE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Primary DataMover Command signals signal cmnd_wr : std_logic := '0'; signal cmnd_data : std_logic_vector ((C_M_AXI_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0'); signal cmnd_pending : std_logic := '0'; signal sts_received : std_logic := '0'; -- Primary DataMover Status signals signal done : std_logic := '0'; signal stop_i : std_logic := '0'; signal interr : std_logic := '0'; signal interr_minus_frame_errors : std_logic := '0'; signal slverr : std_logic := '0'; signal decerr : std_logic := '0'; signal tag : std_logic_vector(3 downto 0) := (others => '0'); signal dma_err : std_logic := '0'; --signal error : std_logic := '0'; signal zero_size_err : std_logic := '0'; signal fsize_mismatch_err_i : std_logic := '0'; -- CR591965 signal lsize_mismatch_err_i : std_logic := '0'; -- CR591965 signal lsize_more_mismatch_err_i : std_logic := '0'; -- CR591965 signal cmnd_idle : std_logic := '0'; signal sts_idle : std_logic := '0'; signal ftch_complete : std_logic := '0'; signal ftch_complete_clr : std_logic := '0'; signal video_prmtrs_valid : std_logic := '0'; signal prmtr_update_complete : std_logic := '0'; -- CR605424 --Descriptor video xfer parameters signal desc_data_wren : std_logic := '0'; signal desc_strtaddress : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal desc_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); signal desc_hsize : std_logic_vector(HSIZE_DWIDTH-1 downto 0) := (others => '0'); signal desc_stride : std_logic_vector(STRIDE_DWIDTH-1 downto 0) := (others => '0'); signal desc_frmdly : std_logic_vector(FRMDLY_DWIDTH-1 downto 0) := (others => '0'); -- Scatter Gather register Bank signal crnt_vsize_i : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884 signal crnt_hsize : std_logic_vector(HSIZE_DWIDTH-1 downto 0) := (others => '0'); signal crnt_stride : std_logic_vector(STRIDE_DWIDTH-1 downto 0) := (others => '0'); signal crnt_frmdly : std_logic_vector(FRMDLY_DWIDTH-1 downto 0) := (others => '0'); signal crnt_start_address : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0'); signal frame_number_i : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal mstr_frame_ref_in : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal slv_frame_ref_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal valid_frame_sync_i : std_logic := '0'; signal valid_frame_sync_d2 : std_logic := '0'; signal initial_frame : std_logic := '0'; signal tstvect_fsync_d1 : std_logic := '0'; signal tstvect_fsync_d2 : std_logic := '0'; signal repeat_frame : std_logic := '0'; -- CR591965 signal repeat_frame_nmbr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); -- CR591965 signal s_h_frame_number : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); -- CR582182 signal dm_prev_frame_number : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); -- CR582182 signal all_idle_d1 : std_logic := '0'; -- CR582182 signal all_idle_re : std_logic := '0'; -- CR582182 signal all_idle_i : std_logic := '0'; -- CR582182 signal late_idle : std_logic := '0'; -- CR582182 signal frame_sync_d1 : std_logic := '0'; signal frame_sync_d2 : std_logic := '0'; signal err_d1 : std_logic := '0'; -- Dynamic frame store support signal num_fstore_minus1_cmb : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0'); signal num_fstore_minus1 : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal num_fstore_equal_one : std_logic := '0'; signal fsize_mismatch_err_flag_i : std_logic := '0'; signal flag_to_repeat_after_fsize_less_err : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin fsize_mismatch_err_flag <= fsize_mismatch_err_flag_i ; -- Number of fstore value set in register is 0x01. num_fstore_equal_one <= '1' when num_fstore_minus1 = ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) else '0'; -- Pass errors to register module dma_interr_set <= interr ; dma_interr_set_minus_frame_errors <= interr_minus_frame_errors ; dma_slverr_set <= slverr ; dma_decerr_set <= decerr ; -- Route out to map to reset module for halt/recover of datamover fsize_mismatch_err <= fsize_mismatch_err_i; -- CR591965 lsize_mismatch_err <= lsize_mismatch_err_i; -- CR591965 lsize_more_mismatch_err <= lsize_more_mismatch_err_i; -- CR591965 -- Pass current vertical size out for line tracking in linebuffers crnt_vsize <= crnt_vsize_i; -- CR575884 -- Pass out to allow masking of fsync_out when parameters are not valid. valid_video_prmtrs <= video_prmtrs_valid; all_idle <= all_idle_i; -- CR582182 --***************************************************************************** -- Frame sync for incrementing frame_number. This sync is qualified with -- video parameter valid to prevent incrementing frame_number on first frame. -- So valid_frame_sync will assert after first frame and then every frame -- after that. --***************************************************************************** -- Qualify frame sync with valid parameters to allow for -- clean video startup valid_frame_sync_i <= frame_sync and video_prmtrs_valid; --***************************************************************************** -- Frame Sync For Masking FSync OUT when shutting down channel for -- FrmCntEn Mode and frame count reached. (cannot move in time) --***************************************************************************** -- Pass combinatorial version for frame_count enable masking in axi_vdma_fsync_gen. valid_frame_sync_cmb <= valid_frame_sync_i; --***************************************************************************** -- INTIAL Frame Flag -- Used to keep frame_number at Zero for intial frame --***************************************************************************** -- Flag used for intializing frame number to 0. Will -- hold frame number at 0 until a valid frame sync -- occurs. REG_INITIAL_FRAME_FLAG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0' or dmasr_halt = '1')then initial_frame <= '0'; elsif(frame_sync = '1')then initial_frame <= '1'; end if; end if; end process REG_INITIAL_FRAME_FLAG; --***************************************************************************** -- Frame Store Error Address (CR582182) -- Frame number currently being operated on from a memory map perspective. -- Needed because axi stream can complete significanly prior to memory map -- completion on S2MM writes allowing for an external fsync to be seen before -- all status is returned from datamover. This memory mapped based frame -- number allows the correct frame store pointer to be updated to the -- PARK_PTR_REF register during error events. --***************************************************************************** GEN_FRMSTORE_EXTFSYNC : if C_USE_FSYNC = 1 generate begin -- Register all idle to generate re pulse for error frame store process REG_IDLE_RE : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0' )then all_idle_d1 <= '0'; else all_idle_d1 <= all_idle_i; end if; end if; end process REG_IDLE_RE; all_idle_re <= all_idle_i and not all_idle_d1; -- Case 2: Fsync asserts before Idle -- If this case and not case 3 (below) then do not sample -- frame_number but use s_h_frame_number. LATE_IDLE_CASE : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0' or all_idle_re = '1' or video_prmtrs_valid = '0')then late_idle <= '0'; elsif(frame_sync = '1' and all_idle_i = '0')then late_idle <= '1'; end if; end if; end process LATE_IDLE_CASE; -- Sample and hold frame number for special "late idle" case -- i.e. when memory map write does not complete before external -- fsync in asserts S_H_FRAME : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then s_h_frame_number <= (others => '0'); elsif(frame_sync = '1')then s_h_frame_number <= frame_number_i; end if; end if; end process S_H_FRAME; -- Sample current frame. If normal fsync to idle relationship -- then pass frame_number. If idle occurs after fsync then -- pass sample-n-held frame number. ---- REG_FRMSTORE_FRAME : process(prmry_aclk) ---- begin ---- if(prmry_aclk'EVENT and prmry_aclk = '1')then ---- -- Reset on reset and also on error delayed 1 to prevent re-assertion on transient ---- -- conditions causing wrong error frame to be logged. ---- --if(prmry_resetn = '0' or zero_size_err_d1 = '1')then ---- if(prmry_resetn = '0')then ---- frmstr_err_addr <= (others => '0'); ---- update_frmstore <= '0'; ---- ---- -- On frame size mismatch, late idle will be asserted and need ---- -- to latch in last frame (i.e. sample and held frame) into ---- -- the frame store register. ---- elsif(late_idle = '1' and fsize_mismatch_err_i = '1')then ---- frmstr_err_addr <= s_h_frame_number; ---- update_frmstore <= '1'; ---- ---- -- CR591965 capture error frame for zero size and frm mismatch ---- -- needed because these two errors are detected at the completion ---- -- of a frame ---- --elsif(zero_size_err_re = '1')then ---- elsif(zero_size_err = '1' or fsize_mismatch_err_i = '1')then ---- frmstr_err_addr <= frame_number_i; ---- update_frmstore <= '1'; ---- ---- -- Not in Park mode and Idle occurs after fsync therefore ---- -- pass sample-n-held frm number ---- -- CR583667 ---- --elsif(late_idle = '1' and all_idle_re = '1')then ---- elsif(late_idle = '1' and all_idle_re = '1' and circular_prk_mode = '1')then ---- frmstr_err_addr <= s_h_frame_number; ---- update_frmstore <= '1'; ---- ---- -- On idle assertion latch current frame number ---- -- CR583667 ---- --elsif(all_idle_re = '1')then ---- elsif(all_idle_re = '1' or circular_prk_mode = '0')then ---- frmstr_err_addr <= frame_number_i; ---- update_frmstore <= '1'; ---- --else ---- -- update_frmstore <= '0'; ---- end if; ---- end if; ---- end process REG_FRMSTORE_FRAME; frmstr_err_addr <= frame_number_i; update_frmstore <= '1'; end generate GEN_FRMSTORE_EXTFSYNC; -- If configured for internal fsync then can simply pass -- frame number to framestore value. GEN_FRMSTORE_INTFSYNC : if C_USE_FSYNC = 0 generate begin frmstr_err_addr <= frame_number_i; update_frmstore <= '1'; end generate GEN_FRMSTORE_INTFSYNC; --***************************************************************************** -- Dynamic Frame Store Support --***************************************************************************** -- One less than setting of number of frame stores. Use for reverse -- flag toggle num_fstore_minus1_cmb <= std_logic_vector(unsigned(num_frame_store) - 1); REG_NUM_FSTR_MINUS1 : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then num_fstore_minus1 <= (others =>'0'); else num_fstore_minus1 <= num_fstore_minus1_cmb(FRAME_NUMBER_WIDTH-1 downto 0); end if; end if; end process REG_NUM_FSTR_MINUS1; --***************************************************************************** -- Dynamic GenLock Slave Mode --***************************************************************************** -- Frame counter for Dynamic GenLock Slave Mode DYNAMIC_SLAVE_MODE_FRAME_CNT : if C_GENLOCK_MODE = 3 generate signal reg_frame_number_ds : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal rst_to_frame_zero : std_logic := '0'; signal valid_frame_sync_d1 : std_logic := '0'; --signal valid_frame_sync_d2 : std_logic := '0'; begin -- Register qualified frame sync (i.e. valid parameters and frame_sync) -- for use in IOC Threshold count wr to hold counter at intial -- value until after first frame. This is done in axi_vdma_reg_module.vhd DS_REG_VALID_FSYNC_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then valid_frame_sync <= '0'; valid_frame_sync_d1 <= '0'; valid_frame_sync_d2 <= '0'; else valid_frame_sync_d1 <= valid_frame_sync_i; valid_frame_sync_d2 <= valid_frame_sync_d1; valid_frame_sync <= valid_frame_sync_d2; end if; end if; end process DS_REG_VALID_FSYNC_OUT; -- Frame sync for test vector, delay counter, and threshold counter -- Register test vector signals out. Also used for -- delay timer and threshold counter. -- Mask with valid video parameters to prevent delay counter -- from counting at start up for external fsyncs that can -- be coming in long before starting. -- Note: tstvect_fsync output needs to be aligned exactly -- with valid_frame_sync output for use in register module to -- reset threshold counter on first frame but not on subsequent -- frames. -- coverage off DS_PROCESS_TSTVECTOR_REG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_fsync_d1 <= '0'; tstvect_fsync_d2 <= '0'; tstvect_fsync <= '0'; else tstvect_fsync_d1 <= frame_sync; tstvect_fsync_d2 <= tstvect_fsync_d1; tstvect_fsync <= tstvect_fsync_d2 and video_prmtrs_valid; end if; end if; end process DS_PROCESS_TSTVECTOR_REG; -- coverage on -- Pass frame number out for test vector -- used in verification only --tstvect_frame <= frame_number_i; -- coverage off DS_TSTVECT_FRM_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frame <= (others => '0'); elsif (dmasr_halt = '0') then tstvect_frame <= frame_number_i; --else -- tstvect_frame <= tstvect_frame; end if; end if; end process DS_TSTVECT_FRM_OUT; -- coverage on -- Calculate frame to work on based on frame delay DS_GEN_FSTORE_GRTR_ONE : if C_NUM_FSTORES > 1 generate begin -- Register to break long timing paths DS_REG_EXT_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then reg_frame_number_ds <= (others => '0'); else reg_frame_number_ds <= slv_frame_ref_out; end if; end if; end process DS_REG_EXT_FRM_NUMBER; end generate DS_GEN_FSTORE_GRTR_ONE; DS_GEN_FSTORE_EQL_ONE : if C_NUM_FSTORES = 1 generate begin reg_frame_number_ds <= slv_frame_ref_out; end generate DS_GEN_FSTORE_EQL_ONE; --************************************************************************* --** VERIFICATION ONLY RTL --************************************************************************* -- coverage off -- TSTVECT_FTPTR_OUT : process(reg_frame_number_ds) DS_TSTVECT_FTPTR_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frm_ptr_out <= (others => '0'); elsif (dmasr_halt = '0') then tstvect_frm_ptr_out <= reg_frame_number_ds(FRAME_NUMBER_WIDTH-1 downto 0); --else --tstvect_frm_ptr_out <= tstvect_frm_ptr_out; end if; end if; end process DS_TSTVECT_FTPTR_OUT; -- coverage on --************************************************************************* --** END VERIFICATION ONLY RTL --************************************************************************* ------------------------------------------------------------------------------- -- Include State Machine and support logic ------------------------------------------------------------------------------- rst_to_frame_zero <= '1' when (dmasr_halt = '1') or (initial_frame = '0' and sync_enable = '0' and circular_prk_mode = '1') else '0'; -- CR582183 incorrect frame delay on first frame -- Delay fsync 2 pipeline stages to allow crnt_frmdly to propogate to -- the correct value for frame_number_i sampling for genlock slave mode DS_REG_DELAY_FSYNC : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then frame_sync_d1 <= '0'; frame_sync_d2 <= '0'; else frame_sync_d1 <= frame_sync; frame_sync_d2 <= frame_sync_d1; end if; end if; end process DS_REG_DELAY_FSYNC; -- Frame Number generation DS_REG_FRAME_COUNT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then -- Clear at reset or stopped or first valid fsync not occured if(prmry_resetn = '0' or rst_to_frame_zero = '1')then frame_number_i <= (others => '0'); -- GenLock Mode and Not in Park Mode (i.e. in tail ptr mode) -- elsif(valid_frame_sync_i = '1' and sync_enable = '1' and circular_prk_mode = '1')then -- latch with frame_sync when doing gen lock to proper capture initial frame ptr in. -- CR582183 incorrect frame delay on first frame --elsif(frame_sync = '1' and sync_enable = '1' and circular_prk_mode = '1')then --elsif(frame_sync_d2 = '1' and sync_enable = '1' and circular_prk_mode = '1')then --elsif(fsize_mismatch_err_flag_i= '1')then elsif(flag_to_repeat_after_fsize_less_err= '1')then frame_number_i <= frame_number_i; elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and circular_prk_mode = '1')then frame_number_i <= reg_frame_number_ds(FRAME_NUMBER_WIDTH-1 downto 0); -- Otherwise all other changes are on frame sync boudnary. elsif(valid_frame_sync_d2 = '1')then -- If Park is enabled if(circular_prk_mode = '0')then frame_number_i <= frame_ptr_ref; -- Frame count reached terminal count therefore roll count over --elsif(frame_number_i = FRAME_NUMBER_TC)then elsif(frame_number_i = num_fstore_minus1)then frame_number_i <= (others => '0'); -- Increment frame count with each sync if valid prmtr values -- stored. else frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 1); end if; end if; end if; end process DS_REG_FRAME_COUNT; frame_number <= frame_number_i; --pass Dynamic Genlock Slave's current working frame number for grey encoding and then output mstr_frame_ref_in <= frame_number_i; REG_CURR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then chnl_current_frame <= (others => '0'); else chnl_current_frame <= frame_number_i; end if; end if; end process REG_CURR_FRM_NUMBER; ----chnl_current_frame <= frame_number_i; ----genlock_pair_frame <= slv_frame_ref_out; REG_PAIR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then genlock_pair_frame <= (others => '0'); else genlock_pair_frame <= slv_frame_ref_out; end if; end if; end process REG_PAIR_FRM_NUMBER; end generate DYNAMIC_SLAVE_MODE_FRAME_CNT; --***************************************************************************** -- GEN-LOCK Slave Mode --***************************************************************************** -- Frame counter for Gen-Lock Slave Mode SLAVE_MODE_FRAME_CNT : if C_GENLOCK_MODE = 1 generate constant ONE_FSTORE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(1,NUM_FRM_STORE_WIDTH)); signal ext_frame_number_grtr : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal ext_frame_number_lesr : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal reg_frame_number_grtr : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal reg_frame_number_lesr : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal ext_slv_frmref : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal ext_crnt_frmdly : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal ext_num_fstore : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal rst_to_frame_zero : std_logic := '0'; signal valid_frame_sync_d1 : std_logic := '0'; --signal valid_frame_sync_d2 : std_logic := '0'; begin -- Register qualified frame sync (i.e. valid parameters and frame_sync) -- for use in IOC Threshold count wr to hold counter at intial -- value until after first frame. This is done in axi_vdma_reg_module.vhd S_REG_VALID_FSYNC_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then valid_frame_sync <= '0'; valid_frame_sync_d1 <= '0'; valid_frame_sync_d2 <= '0'; else valid_frame_sync_d1 <= valid_frame_sync_i; valid_frame_sync_d2 <= valid_frame_sync_d1; valid_frame_sync <= valid_frame_sync_d2; end if; end if; end process S_REG_VALID_FSYNC_OUT; -- Frame sync for test vector, delay counter, and threshold counter -- Register test vector signals out. Also used for -- delay timer and threshold counter. -- Mask with valid video parameters to prevent delay counter -- from counting at start up for external fsyncs that can -- be coming in long before starting. -- Note: tstvect_fsync output needs to be aligned exactly -- with valid_frame_sync output for use in register module to -- reset threshold counter on first frame but not on subsequent -- frames. S_PROCESS_TSTVECTOR_REG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_fsync_d1 <= '0'; tstvect_fsync_d2 <= '0'; tstvect_fsync <= '0'; else tstvect_fsync_d1 <= frame_sync; tstvect_fsync_d2 <= tstvect_fsync_d1; tstvect_fsync <= tstvect_fsync_d2 and video_prmtrs_valid; end if; end if; end process S_PROCESS_TSTVECTOR_REG; -- Pass frame number out for test vector -- used in verification only --tstvect_frame <= frame_number_i; -- coverage off S_TSTVECT_FRM_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frame <= (others => '0'); elsif (dmasr_halt = '0') then tstvect_frame <= frame_number_i; --else -- tstvect_frame <= tstvect_frame; end if; end if; end process S_TSTVECT_FRM_OUT; -- coverage on -- Calculate frame to work on based on frame delay GEN_FSTORE_GRTR_ONE : if C_NUM_FSTORES > 1 generate begin -- Extend unsigned vectors by 1 bit to allow for -- carry out during addition. --ext_slv_frmref <= '0' & slv_frame_ref_out; --ext_crnt_frmdly <= '0' & crnt_frmdly; ext_slv_frmref <= "00" & slv_frame_ref_out; ext_crnt_frmdly <= "00" & crnt_frmdly; ext_num_fstore <= '0' & num_frame_store; -- Calculate for when frame delay less than or equal to slave frame ref. This is -- normal operation where a simple subtraction of frame delay from slave frame ref -- will work. ext_frame_number_lesr <= std_logic_vector(unsigned(ext_slv_frmref) - unsigned(ext_crnt_frmdly)); -- Calculate for when frame delay greater than slave frame ref. This is roll-over -- point, i.e. if slave frame ref = 0 then you want frame number to be C_NUM_FSTORES-1 -- This can be calculated with (C_NUM_FSTORES + Slave Frame Ref) - Frame Delay --ext_frame_number_grtr <= std_logic_vector( (C_NUM_FSTORES + unsigned(ext_slv_frmref)) -- - unsigned(ext_crnt_frmdly)); ext_frame_number_grtr <= std_logic_vector( (unsigned(ext_num_fstore) + unsigned(ext_slv_frmref)) - unsigned(ext_crnt_frmdly)); -- Register to break long timing paths REG_EXT_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then reg_frame_number_grtr <= (others => '0'); reg_frame_number_lesr <= (others => '0'); -- If frame stores set to 1 then simply pass unmodified version -- through elsif(num_frame_store = ONE_FSTORE)then reg_frame_number_grtr <= ext_slv_frmref; reg_frame_number_lesr <= ext_slv_frmref; else reg_frame_number_grtr <= ext_frame_number_grtr; reg_frame_number_lesr <= ext_frame_number_lesr; end if; end if; end process REG_EXT_FRM_NUMBER; end generate GEN_FSTORE_GRTR_ONE; -- For frame stores = 1 then frame delay has no meaning. GEN_FSTORE_EQL_ONE : if C_NUM_FSTORES = 1 generate begin reg_frame_number_grtr <= ext_slv_frmref; reg_frame_number_lesr <= ext_slv_frmref; end generate GEN_FSTORE_EQL_ONE; --************************************************************************* --** VERIFICATION ONLY RTL --************************************************************************* -- coverage off ---- TSTVECT_FTPTR_OUT : process(crnt_frmdly, ---- slv_frame_ref_out, ---- reg_frame_number_lesr, ---- reg_frame_number_grtr) ---- begin ---- if(crnt_frmdly <= slv_frame_ref_out)then ---- tstvect_frm_ptr_out <= reg_frame_number_lesr(FRAME_NUMBER_WIDTH-1 downto 0); ---- else ---- tstvect_frm_ptr_out <= reg_frame_number_grtr(FRAME_NUMBER_WIDTH-1 downto 0); ---- end if; ---- end process TSTVECT_FTPTR_OUT; S_TSTVECT_FTPTR_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frm_ptr_out <= (others => '0'); elsif (dmasr_halt = '0') then if(crnt_frmdly <= slv_frame_ref_out)then tstvect_frm_ptr_out <= reg_frame_number_lesr(FRAME_NUMBER_WIDTH-1 downto 0); else tstvect_frm_ptr_out <= reg_frame_number_grtr(FRAME_NUMBER_WIDTH-1 downto 0); end if; --else --tstvect_frm_ptr_out <= tstvect_frm_ptr_out; end if; end if; end process S_TSTVECT_FTPTR_OUT; -- coverage on --************************************************************************* --** END VERIFICATION ONLY RTL --************************************************************************* ------------------------------------------------------------------------------- -- Include State Machine and support logic ------------------------------------------------------------------------------- rst_to_frame_zero <= '1' when (dmasr_halt = '1') or (initial_frame = '0' and sync_enable = '0' and circular_prk_mode = '1') else '0'; -- CR582183 incorrect frame delay on first frame -- Delay fsync 2 pipeline stages to allow crnt_frmdly to propogate to -- the correct value for frame_number_i sampling for genlock slave mode REG_DELAY_FSYNC : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then frame_sync_d1 <= '0'; frame_sync_d2 <= '0'; else frame_sync_d1 <= frame_sync; frame_sync_d2 <= frame_sync_d1; end if; end if; end process REG_DELAY_FSYNC; -- Frame Number generation REG_FRAME_COUNT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then -- Clear at reset or stopped or first valid fsync not occured if(prmry_resetn = '0' or rst_to_frame_zero = '1')then frame_number_i <= (others => '0'); -- GenLock Mode and Not in Park Mode (i.e. in tail ptr mode) -- elsif(valid_frame_sync_i = '1' and sync_enable = '1' and circular_prk_mode = '1')then -- latch with frame_sync when doing gen lock to proper capture initial frame ptr in. -- CR582183 incorrect frame delay on first frame --elsif(frame_sync = '1' and sync_enable = '1' and circular_prk_mode = '1')then --elsif(fsize_mismatch_err_flag_i= '1')then elsif(flag_to_repeat_after_fsize_less_err= '1')then frame_number_i <= frame_number_i; elsif(frame_sync_d2 = '1' and sync_enable = '1' and circular_prk_mode = '1')then -- If frame delay less than or equal slave frame reference -- then simply subtract if(crnt_frmdly <= slv_frame_ref_out)then frame_number_i <= reg_frame_number_lesr(FRAME_NUMBER_WIDTH-1 downto 0); else frame_number_i <= reg_frame_number_grtr(FRAME_NUMBER_WIDTH-1 downto 0); end if; -- Otherwise all other changes are on frame sync boudnary. elsif(valid_frame_sync_d2 = '1')then -- If Park is enabled if(circular_prk_mode = '0')then frame_number_i <= frame_ptr_ref; -- Frame count reached terminal count therefore roll count over --elsif(frame_number_i = FRAME_NUMBER_TC)then elsif(frame_number_i = num_fstore_minus1)then frame_number_i <= (others => '0'); -- Increment frame count with each sync if valid prmtr values -- stored. else frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 1); end if; end if; end if; end process REG_FRAME_COUNT; frame_number <= frame_number_i; --pass Genlock Slave's current working frame number for grey encoding and then output -- CR 703788 --mstr_frame_ref_in <= (others => '0'); -- Not Used in Slave Mode mstr_frame_ref_in <= frame_number_i; -- CR 703788 REG_CURR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then chnl_current_frame <= (others => '0'); else chnl_current_frame <= frame_number_i; end if; end if; end process REG_CURR_FRM_NUMBER; ----chnl_current_frame <= frame_number_i; ----genlock_pair_frame <= slv_frame_ref_out; REG_PAIR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then genlock_pair_frame <= (others => '0'); else genlock_pair_frame <= slv_frame_ref_out; end if; end if; end process REG_PAIR_FRM_NUMBER; end generate SLAVE_MODE_FRAME_CNT; --***************************************************************************** -- Dynamic GenLock Master Mode --***************************************************************************** -- Frame counter for Gen-Lock Master Mode DYNAMIC_MASTER_MODE_FRAME_CNT : if C_GENLOCK_MODE = 2 generate signal valid_frame_sync_d1 : std_logic := '0'; --signal flag_to_repeat_after_fsize_less_err : std_logic := '0'; --signal valid_frame_sync_d2 : std_logic := '0'; begin -- Register qualified frame sync (i.e. valid parameters and frame_sync) -- for use in IOC Threshold count wr to hold counter at intial -- value until after first frame. This is done in axi_vdma_reg_module.vhd DM_REG_VALID_FSYNC_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then valid_frame_sync <= '0'; valid_frame_sync_d1 <= '0'; valid_frame_sync_d2 <= '0'; else valid_frame_sync_d1 <= valid_frame_sync_i; valid_frame_sync_d2 <= valid_frame_sync_d1; valid_frame_sync <= valid_frame_sync_d2; end if; end if; end process DM_REG_VALID_FSYNC_OUT; -- Frame sync for test vector, delay counter, and threshold counter -- Register test vector signals out. Also used for -- delay timer and threshold counter. ---- DM_PROCESS_TSTVECTOR_REG : process(prmry_aclk) ---- begin ---- if(prmry_aclk'EVENT and prmry_aclk = '1')then ---- if(prmry_resetn = '0')then ---- tstvect_fsync_d1<= '0'; ---- tstvect_fsync_d2<= '0'; ---- tstvect_frame <= (others => '0'); ---- else ---- tstvect_fsync_d1<= frame_sync; ---- tstvect_fsync_d2<= tstvect_fsync_d1; ---- tstvect_frame <= frame_number_i; ---- end if; ---- end if; ---- end process DM_PROCESS_TSTVECTOR_REG; -- coverage off DM_PROCESS_TSTVECTOR_REG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_fsync_d1 <= '0'; tstvect_fsync_d2 <= '0'; tstvect_fsync <= '0'; else tstvect_fsync_d1 <= frame_sync; tstvect_fsync_d2 <= tstvect_fsync_d1; tstvect_fsync <= tstvect_fsync_d2 and video_prmtrs_valid; end if; end if; end process DM_PROCESS_TSTVECTOR_REG; DM_TSTVECT_FRM_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frame <= (others => '0'); elsif (dmasr_halt = '0') then tstvect_frame <= frame_number_i; --else -- tstvect_frame <= tstvect_frame; end if; end if; end process DM_TSTVECT_FRM_OUT; -- coverage on -- Mask with valid video parameters to prevent delay counter -- from counting at start up for external fsyncs that can -- be coming in long before starting. -- video_prmtrs_valid asserts on clock cycle following assertion -- of frame_sync, thus pipeline delay to create tstvect_fsync_d1 -- is required to assert first fsync for first valid frame -- Note: tstvect_fsync output needs to be aligned exactly -- with valid_frame_sync output for use in register module to -- reset threshold counter on first frame but not on subsequent -- frames. --tstvect_fsync <= tstvect_fsync_d1 and video_prmtrs_valid; --tstvect_fsync <= tstvect_fsync_d2 and video_prmtrs_valid; DM_GEN_FSTORE_GRTR_TWO : if C_NUM_FSTORES > 2 generate begin ------------------------------------------------------------------------------- -- Include State Machine and support logic ------------------------------------------------------------------------------- -- Frame Number generation DM_REG_FRAME_COUNT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then -- Clear at reset or stopped or first valid fsync not occured if(prmry_resetn = '0' or dmasr_halt = '1' or (circular_prk_mode = '1' and initial_frame = '0') or num_fstore_equal_one = '1')then frame_number_i <= (others => '0'); -- If Park is enabled then on frame sync transision to -- frame pointer reference. --elsif(fsize_mismatch_err_flag_i= '1')then elsif(flag_to_repeat_after_fsize_less_err= '1')then frame_number_i <= frame_number_i; elsif(valid_frame_sync_d2 = '1' and circular_prk_mode = '0')then frame_number_i <= frame_ptr_ref; ------------------------------------------------------------------------------------------------------------ -- On Repeat Frame simply hold current frame number (CR591965) --elsif(repeat_frame = '1')then elsif(repeat_frame = '1' and dmacr_repeat_en = '1')then frame_number_i <= repeat_frame_nmbr; ------------------------------------------------------------------------------------------------------------ -- Frame count reached terminal count therefore roll count over --elsif(valid_frame_sync_i = '1' and frame_number_i = FRAME_NUMBER_TC)then elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and frame_number_i = num_fstore_minus1 and (slv_frame_ref_out /= "00000"))then frame_number_i <= (others => '0'); elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and frame_number_i = num_fstore_minus1 and (slv_frame_ref_out = "00000"))then frame_number_i <= "00001"; elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and slv_frame_ref_out = num_fstore_minus1 and (frame_number_i = std_logic_vector(unsigned(slv_frame_ref_out) - 1)))then frame_number_i <= (others => '0'); elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (slv_frame_ref_out /= num_fstore_minus1) and (slv_frame_ref_out /= "00000") and (frame_number_i = std_logic_vector(unsigned(slv_frame_ref_out) - 1)))then frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 2); -- Increment frame count with each sync if valid prmtr values -- stored. elsif(valid_frame_sync_d2 = '1' and frame_number_i = num_fstore_minus1)then frame_number_i <= (others => '0'); elsif(valid_frame_sync_d2 = '1')then frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 1); end if; end if; end process DM_REG_FRAME_COUNT; end generate DM_GEN_FSTORE_GRTR_TWO; DM_GEN_FSTORES_EQL_TWO : if C_NUM_FSTORES = 2 generate begin ------------------------------------------------------------------------------- -- Include State Machine and support logic ------------------------------------------------------------------------------- -- Frame Number generation DM_REG_FRAME_COUNT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then -- Clear at reset or stopped or first valid fsync not occured if(prmry_resetn = '0' or dmasr_halt = '1' or (circular_prk_mode = '1' and initial_frame = '0') or num_fstore_equal_one = '1')then frame_number_i <= (others => '0'); -- If Park is enabled then on frame sync transision to -- frame pointer reference. --elsif(fsize_mismatch_err_flag_i= '1')then elsif(flag_to_repeat_after_fsize_less_err= '1')then frame_number_i <= frame_number_i; elsif(valid_frame_sync_d2 = '1' and circular_prk_mode = '0')then frame_number_i <= frame_ptr_ref; ------------------------------------------------------------------------------------------------------------ -- On Repeat Frame simply hold current frame number (CR591965) --elsif(repeat_frame = '1')then elsif(repeat_frame = '1' and dmacr_repeat_en = '1')then frame_number_i <= repeat_frame_nmbr; ------------------------------------------------------------------------------------------------------------ -- Frame count reached terminal count therefore roll count over --elsif(valid_frame_sync_i = '1' and frame_number_i = FRAME_NUMBER_TC)then elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (frame_number_i = "00001") and (slv_frame_ref_out = "00001"))then frame_number_i <= (others => '0'); elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (frame_number_i = "00001") and (slv_frame_ref_out = "00000"))then frame_number_i <= "00001"; elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (frame_number_i = "00000") and (slv_frame_ref_out = "00001"))then frame_number_i <= (others => '0'); elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (frame_number_i = "00000") and (slv_frame_ref_out = "00000"))then frame_number_i <="00001" ; elsif(valid_frame_sync_d2 = '1' and frame_number_i = "00001")then frame_number_i <= (others => '0'); elsif(valid_frame_sync_d2 = '1' and frame_number_i = "00000")then frame_number_i <="00001" ; end if; end if; end process DM_REG_FRAME_COUNT; end generate DM_GEN_FSTORES_EQL_TWO; DM_GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate begin frame_number_i <= (others => '0'); end generate DM_GEN_FSTORES_EQL_ONE; DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF : if C_MM2S_SOF_ENABLE = 1 or C_S2MM_SOF_ENABLE = 1 generate begin DM_REPEAT_EN_FSIZE_LESS_ERR_FLAG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0' or valid_frame_sync_d2 = '1')then flag_to_repeat_after_fsize_less_err <= '0'; elsif(fsize_mismatch_err_i = '1')then flag_to_repeat_after_fsize_less_err <= '1'; end if; end if; end process DM_REPEAT_EN_FSIZE_LESS_ERR_FLAG; end generate DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF; DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_NO_SOF : if C_MM2S_SOF_ENABLE = 0 and C_S2MM_SOF_ENABLE = 0 generate begin flag_to_repeat_after_fsize_less_err <= '0'; end generate DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_NO_SOF; -- If flush on frame sync enabled and genlock repeat frame enabled -- then repeat errored frame on next frame sync. (CR591965) -- DM_GEN_REPEAT_FRM_LOGIC : if C_GENLOCK_REPEAT_EN = 1 and C_ENABLE_FLUSH_ON_FSYNC = 1 generate -- begin DM_REPEAT_FRAME_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then ----if(prmry_resetn = '0' or valid_frame_sync_d2 = '1')then if(prmry_resetn = '0' or (valid_frame_sync_d2 = '1' and flag_to_repeat_after_fsize_less_err = '0'))then repeat_frame_nmbr <= (others => '0'); repeat_frame <= '0'; -- Frame size mismatch elsif(fsize_mismatch_err_i='1' or flag_to_repeat_after_fsize_less_err = '1')then repeat_frame_nmbr <= s_h_frame_number; repeat_frame <= '1'; -- Line size mismatch elsif(lsize_mismatch_err_i='1' or lsize_more_mismatch_err_i ='1')then repeat_frame_nmbr <= frame_number_i; repeat_frame <= '1'; end if; end if; end process DM_REPEAT_FRAME_PROCESS; -- end generate DM_GEN_REPEAT_FRM_LOGIC; ---- -- Not in flush on frame sync mode or repeat frame not enabled (CR591965) ---- DM_GEN_NO_REPEAT_FRM_LOGIC : if C_GENLOCK_REPEAT_EN = 0 or C_ENABLE_FLUSH_ON_FSYNC = 0 generate ---- begin ---- -- never repeat frame ---- repeat_frame <= '0'; ---- repeat_frame_nmbr <= (others => '0'); ---- ---- end generate DM_GEN_NO_REPEAT_FRM_LOGIC; -- Pass Frame sync to video mstr_frame_ref_in <= dm_prev_frame_number; -- Pass frame number out to register module frame_number <= frame_number_i; -- Drive test vector to zero for GenLock master mode --tstvect_frm_ptr_out <= (others => '0'); -- Drive test vector for Dynamic GenLock master mode --tstvect_frm_ptr_out <= slv_frame_ref_out; -- coverage off -- TSTVECT_FTPTR_OUT : process(reg_frame_number_ds) DM_TSTVECT_FTPTR_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frm_ptr_out <= (others => '0'); elsif (dmasr_halt = '0') then tstvect_frm_ptr_out <= slv_frame_ref_out; --else --tstvect_frm_ptr_out <= tstvect_frm_ptr_out; end if; end if; end process DM_TSTVECT_FTPTR_OUT; -- coverage on DM_PREV_FRAME : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then dm_prev_frame_number <= (others => '0'); --elsif(valid_frame_sync_d2 = '1'and repeat_frame = '0' and fsize_mismatch_err_flag_i = '0')then ----elsif(valid_frame_sync_d2 = '1'and repeat_frame = '0' and flag_to_repeat_after_fsize_less_err = '0')then elsif(valid_frame_sync_d2 = '1'and (dmacr_repeat_en = '0' or repeat_frame = '0') and flag_to_repeat_after_fsize_less_err = '0')then dm_prev_frame_number <= frame_number_i; end if; end if; end process DM_PREV_FRAME; REG_CURR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then chnl_current_frame <= (others => '0'); else chnl_current_frame <= frame_number_i; end if; end if; end process REG_CURR_FRM_NUMBER; ----chnl_current_frame <= frame_number_i; ----genlock_pair_frame <= slv_frame_ref_out; REG_PAIR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then genlock_pair_frame <= (others => '0'); else genlock_pair_frame <= slv_frame_ref_out; end if; end if; end process REG_PAIR_FRM_NUMBER; end generate DYNAMIC_MASTER_MODE_FRAME_CNT; --***************************************************************************** -- GEN-LOCK MASTER Mode --***************************************************************************** -- Frame counter for Gen-Lock Master Mode MASTER_MODE_FRAME_CNT : if C_GENLOCK_MODE = 0 generate signal valid_frame_sync_d1 : std_logic := '0'; --signal flag_to_repeat_after_fsize_less_err : std_logic := '0'; --signal valid_frame_sync_d2 : std_logic := '0'; begin -- Register qualified frame sync (i.e. valid parameters and frame_sync) -- for use in IOC Threshold count wr to hold counter at intial -- value until after first frame. This is done in axi_vdma_reg_module.vhd M_REG_VALID_FSYNC_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then valid_frame_sync <= '0'; valid_frame_sync_d1 <= '0'; valid_frame_sync_d2 <= '0'; else valid_frame_sync_d1 <= valid_frame_sync_i; valid_frame_sync_d2 <= valid_frame_sync_d1; valid_frame_sync <= valid_frame_sync_d2; end if; end if; end process M_REG_VALID_FSYNC_OUT; ---- REG_VALID_FSYNC_OUT : process(prmry_aclk) ---- begin ---- if(prmry_aclk'EVENT and prmry_aclk = '1')then ---- if(prmry_resetn = '0')then ---- valid_frame_sync <= '0'; ---- else ---- valid_frame_sync <= valid_frame_sync_i; ---- end if; ---- end if; ---- end process REG_VALID_FSYNC_OUT; -- Frame sync for test vector, delay counter, and threshold counter -- Register test vector signals out. Also used for -- delay timer and threshold counter. ---- PROCESS_TSTVECTOR_REG : process(prmry_aclk) ---- begin ---- if(prmry_aclk'EVENT and prmry_aclk = '1')then ---- if(prmry_resetn = '0')then ---- tstvect_fsync_d1<= '0'; ---- tstvect_frame <= (others => '0'); ---- else ---- tstvect_fsync_d1<= frame_sync; ---- tstvect_frame <= frame_number_i; ---- end if; ---- end if; ---- end process PROCESS_TSTVECTOR_REG; -- coverage off M_TSTVECT_FRM_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frame <= (others => '0'); elsif (dmasr_halt = '0') then tstvect_frame <= frame_number_i; --else -- tstvect_frame <= tstvect_frame; end if; end if; end process M_TSTVECT_FRM_OUT; M_PROCESS_TSTVECTOR_REG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_fsync_d1 <= '0'; tstvect_fsync_d2 <= '0'; tstvect_fsync <= '0'; else tstvect_fsync_d1 <= frame_sync; tstvect_fsync_d2 <= tstvect_fsync_d1; tstvect_fsync <= tstvect_fsync_d2 and video_prmtrs_valid; end if; end if; end process M_PROCESS_TSTVECTOR_REG; -- coverage on -- Mask with valid video parameters to prevent delay counter -- from counting at start up for external fsyncs that can -- be coming in long before starting. -- video_prmtrs_valid asserts on clock cycle following assertion -- of frame_sync, thus pipeline delay to create tstvect_fsync_d1 -- is required to assert first fsync for first valid frame -- Note: tstvect_fsync output needs to be aligned exactly -- with valid_frame_sync output for use in register module to -- reset threshold counter on first frame but not on subsequent -- frames. --tstvect_fsync <= tstvect_fsync_d1 and video_prmtrs_valid; ------------------------------------------------------------------------------- -- Include State Machine and support logic ------------------------------------------------------------------------------- -- Frame Number generation REG_FRAME_COUNT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then -- Clear at reset or stopped or first valid fsync not occured if(prmry_resetn = '0' or dmasr_halt = '1' or (circular_prk_mode = '1' and initial_frame = '0'))then frame_number_i <= (others => '0'); -- If Park is enabled then on frame sync transision to -- frame pointer reference. --elsif(fsize_mismatch_err_flag_i= '1')then elsif(flag_to_repeat_after_fsize_less_err= '1')then frame_number_i <= frame_number_i; elsif(valid_frame_sync_d2 = '1' and circular_prk_mode = '0')then frame_number_i <= frame_ptr_ref; -- On Repeat Frame simply hold current frame number (CR591965) --elsif(repeat_frame = '1')then elsif(repeat_frame = '1' and dmacr_repeat_en = '1')then frame_number_i <= repeat_frame_nmbr; -- Frame count reached terminal count therefore roll count over --elsif(valid_frame_sync_i = '1' and frame_number_i = FRAME_NUMBER_TC)then elsif(valid_frame_sync_d2 = '1' and frame_number_i = num_fstore_minus1)then frame_number_i <= (others => '0'); -- Increment frame count with each sync if valid prmtr values -- stored. elsif(valid_frame_sync_d2 = '1' and video_prmtrs_valid = '1')then frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 1); end if; end if; end process REG_FRAME_COUNT; GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF : if C_MM2S_SOF_ENABLE = 1 or C_S2MM_SOF_ENABLE = 1 generate begin REPEAT_EN_FSIZE_LESS_ERR_FLAG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0' or valid_frame_sync_d2 = '1')then flag_to_repeat_after_fsize_less_err <= '0'; elsif(fsize_mismatch_err_i = '1')then flag_to_repeat_after_fsize_less_err <= '1'; end if; end if; end process REPEAT_EN_FSIZE_LESS_ERR_FLAG; end generate GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF; GEN_REPEAT_FRM_FSIZE_LESS_ERR_NO_SOF : if C_MM2S_SOF_ENABLE = 0 and C_S2MM_SOF_ENABLE = 0 generate begin flag_to_repeat_after_fsize_less_err <= '0'; end generate GEN_REPEAT_FRM_FSIZE_LESS_ERR_NO_SOF; -- If flush on frame sync enabled and genlock repeat frame enabled -- then repeat errored frame on next frame sync. (CR591965) -- GEN_REPEAT_FRM_LOGIC : if C_GENLOCK_REPEAT_EN = 1 and C_ENABLE_FLUSH_ON_FSYNC = 1 generate -- begin REPEAT_FRAME_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then ----if(prmry_resetn = '0' or valid_frame_sync_d2 = '1')then if(prmry_resetn = '0' or (valid_frame_sync_d2 = '1' and flag_to_repeat_after_fsize_less_err = '0'))then repeat_frame_nmbr <= (others => '0'); repeat_frame <= '0'; -- Frame size mismatch --elsif(fsize_mismatch_err_i='1')then elsif(fsize_mismatch_err_i='1' or flag_to_repeat_after_fsize_less_err='1')then repeat_frame_nmbr <= s_h_frame_number; repeat_frame <= '1'; -- Line size mismatch elsif(lsize_mismatch_err_i='1' or lsize_more_mismatch_err_i ='1')then repeat_frame_nmbr <= frame_number_i; repeat_frame <= '1'; end if; end if; end process REPEAT_FRAME_PROCESS; --end generate GEN_REPEAT_FRM_LOGIC; ---- -- Not in flush on frame sync mode or repeat frame not enabled (CR591965) ---- GEN_NO_REPEAT_FRM_LOGIC : if C_GENLOCK_REPEAT_EN = 0 or C_ENABLE_FLUSH_ON_FSYNC = 0 generate ---- begin ---- -- never repeat frame ---- repeat_frame <= '0'; ---- repeat_frame_nmbr <= (others => '0'); ---- ---- end generate GEN_NO_REPEAT_FRM_LOGIC; -- Pass Frame sync to video mstr_frame_ref_in <= frame_number_i; -- Pass frame number out to register module frame_number <= frame_number_i; -- Drive test vector to zero for master mode tstvect_frm_ptr_out <= (others => '0'); ----chnl_current_frame <= frame_number_i; REG_CURR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then chnl_current_frame <= (others => '0'); else chnl_current_frame <= frame_number_i; end if; end if; end process REG_CURR_FRM_NUMBER; ----chnl_current_frame <= frame_number_i; genlock_pair_frame <= (others => '0'); end generate MASTER_MODE_FRAME_CNT; --***************************************************************************** -- Error Handling -- For graceful shut down logic --***************************************************************************** -- Clear run/stop and stop state machines due to errors or soft reset -- Error based on datamover error report or sg fetch error -- SG fetch error included because need to shut down because data maybe corrupt -- therefor do not want to issue the xfer command to primary datamover -- Added run_stop to assertion for when run_stop is de-asserted in middle of video -- frame need to halt datamover to clear out potential pending commands. stop_i <= dma_err -- DMAIntErr, DMADecErr, DMASlvErr, ZeroSize, possibly Frame/Line Mismatch or ftch_err -- SGDecErr, SGSlvErr or soft_reset; -- Soft Reset issued -- Reg stop out REG_STOP_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then stop <= '0'; else stop <= stop_i; end if; end if; end process REG_STOP_OUT; -- For verification only - drive error detection -- out to test vector port, will be stripped during build -- (Broke up in order to capture all errors regardless of -- flush on frame sync mode) -- coverage off REG_DELAY_ERR : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then err_d1 <= '0'; tstvect_err <= '0'; else err_d1 <= slverr -- DMASlvErr or decerr -- DMADecErr or interr -- DMAIntErr, ZeroSize, Frame or lsize_mismatch_err_i -- Line Mismatch or lsize_more_mismatch_err_i -- Line Mismatch or ftch_err; -- SGSlvErr, SGDecErr tstvect_err <= err_d1; end if; end if; end process REG_DELAY_ERR; -- coverage on --***************************************************************************** -- DMA Control --***************************************************************************** --------------------------------------------------------------------------- -- Primary DMA Controller State Machine --------------------------------------------------------------------------- I_SM : entity axi_vdma_v6_2.axi_vdma_sm generic map( C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH , C_INCLUDE_SF => C_INCLUDE_SF , C_USE_FSYNC => C_USE_FSYNC , -- CR591965 C_ENABLE_FLUSH_ON_FSYNC => C_ENABLE_FLUSH_ON_FSYNC , -- CR591965 C_EXTEND_DM_COMMAND => C_EXTEND_DM_COMMAND , C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH , C_MM2S_SOF_ENABLE => C_MM2S_SOF_ENABLE , C_S2MM_SOF_ENABLE => C_S2MM_SOF_ENABLE , C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_INCLUDE_S2MM => C_INCLUDE_S2MM ) port map( prmry_aclk => prmry_aclk , prmry_resetn => prmry_resetn , scndry_aclk => scndry_aclk , scndry_resetn => scndry_resetn , -- AXI Stream Qualifiers packet_sof => packet_sof , -- Raw fsync (must use unqualified frame sync for proper sm operation) frame_sync => frame_sync , -- Valid video parameter available video_prmtrs_valid => video_prmtrs_valid , -- Control and Status run_stop => run_stop , cmnd_idle => cmnd_idle , sts_idle => sts_idle , stop => stop_i , halt => halt , zero_size_err => zero_size_err , mm2s_fsync_out_m => mm2s_fsync_out_m , s2mm_fsync_out_m => s2mm_fsync_out_m , mm2s_fsize_mismatch_err_s => mm2s_fsize_mismatch_err_s , mm2s_fsize_mismatch_err_m => mm2s_fsize_mismatch_err_m , s2mm_fsize_mismatch_err_s => s2mm_fsize_mismatch_err_s , fsize_mismatch_err_flag => fsize_mismatch_err_flag_i , fsize_mismatch_err => fsize_mismatch_err_i , -- CR591965 all_lines_xfred => all_lines_xfred , -- CR616211 all_lasts_rcvd => all_lasts_rcvd , drop_fsync_d_pulse_gen_fsize_less_err => drop_fsync_d_pulse_gen_fsize_less_err , s2mm_strm_all_lines_rcvd => s2mm_strm_all_lines_rcvd , -- : out std_logic; s2mm_fsync_core => s2mm_fsync_core , -- : out std_logic; -- DataMover Command/Status cmnd_wr => cmnd_wr , cmnd_data => cmnd_data , cmnd_pending => cmnd_pending , sts_received => sts_received , -- Descriptor Fields crnt_start_address => crnt_start_address , crnt_vsize => crnt_vsize_i , -- CR575884 crnt_hsize => crnt_hsize , crnt_stride => crnt_stride ); -- If Scatter Gather engine is included then instantiate scatter gather -- interface GEN_SG_INTERFACE : if C_INCLUDE_SG = 1 generate begin --------------------------------------------------------------------------- -- Scatter Gather State Machine --------------------------------------------------------------------------- I_SG_IF : entity axi_vdma_v6_2.axi_vdma_sg_if generic map( ------------------------------------------------------------------- -- Scatter Gather Parameters ------------------------------------------------------------------- C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ) port map( prmry_aclk => prmry_aclk , prmry_resetn => prmry_resetn , dmasr_halt => dmasr_halt , ftch_idle => ftch_idle , ftch_complete => ftch_complete , ftch_complete_clr => ftch_complete_clr , -- SG Descriptor Fetch AXI Stream In m_axis_ftch_tdata => m_axis_ftch_tdata , m_axis_ftch_tvalid => m_axis_ftch_tvalid , m_axis_ftch_tready => m_axis_ftch_tready , m_axis_ftch_tlast => m_axis_ftch_tlast , -- Descriptor Field Output new_curdesc => new_curdesc , new_curdesc_wren => new_curdesc_wren , desc_data_wren => desc_data_wren , desc_strtaddress => desc_strtaddress , desc_vsize => desc_vsize , desc_hsize => desc_hsize , desc_stride => desc_stride , desc_frmdly => desc_frmdly ); end generate GEN_SG_INTERFACE; -- If Scatter Gather engine is excluded then tie off unused signals GEN_NO_SG_INTERFACE : if C_INCLUDE_SG = 0 generate begin -- Map update complete to ftch_complete signal for proper -- video paramter transfer from axi_lite registers to video registers ftch_complete <= prmtr_updt_complete; -- Signals not need for register direct mode m_axis_ftch_tready <= '0'; new_curdesc <= (others => '0'); new_curdesc_wren <= '0'; desc_data_wren <= '0'; desc_strtaddress <= (others => '0'); desc_vsize <= (others => '0'); desc_hsize <= (others => '0'); desc_stride <= (others => '0'); desc_frmdly <= (others => '0'); end generate GEN_NO_SG_INTERFACE; ------------------------------------------------------------------------------- -- Primary DataMover command status interface ------------------------------------------------------------------------------- I_CMDSTS : entity axi_vdma_v6_2.axi_vdma_cmdsts_if generic map( C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH , C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH , C_INCLUDE_MM2S => C_INCLUDE_MM2S , --C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO , C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL , C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 , C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 , C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 , C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 , C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 , C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 , C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 , C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 , C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 , C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 , C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 , C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 , C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 , C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 , C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 , C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 , C_INCLUDE_S2MM => C_INCLUDE_S2MM, C_ENABLE_FLUSH_ON_FSYNC => C_ENABLE_FLUSH_ON_FSYNC ) port map( prmry_aclk => prmry_aclk , prmry_resetn => prmry_resetn , -- Fetch command write interface from sm cmnd_wr => cmnd_wr , cmnd_data => cmnd_data , cmnd_pending => cmnd_pending , sts_received => sts_received , crnt_hsize => crnt_hsize , stop => stop_i , halt => halt , -- CR613214 dmasr_halt => dmasr_halt , -- User Command Interface Ports (AXI Stream) s_axis_cmd_tvalid => s_axis_cmd_tvalid , s_axis_cmd_tready => s_axis_cmd_tready , s_axis_cmd_tdata => s_axis_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_sts_tvalid => m_axis_sts_tvalid , m_axis_sts_tready => m_axis_sts_tready , m_axis_sts_tdata => m_axis_sts_tdata , m_axis_sts_tkeep => m_axis_sts_tkeep , s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late , s2mm_dmasr_lsize_less_err => s2mm_dmasr_lsize_less_err , -- Zero Hsize and/or Vsize. mapped here to combine with interr zero_size_err => zero_size_err , -- Frame Mismatch. mapped here to combine with interr fsize_mismatch_err => fsize_mismatch_err_i , -- CR591965 lsize_mismatch_err => lsize_mismatch_err_i , -- CR591965 lsize_more_mismatch_err => lsize_more_mismatch_err_i , -- CR591965 capture_hsize_at_uf_err => capture_hsize_at_uf_err , -- Primary DataMover Status err => err , done => done , err_o => dma_err , interr_minus_frame_errors => interr_minus_frame_errors , interr => interr , slverr => slverr , decerr => decerr , tag => tag -- Not used ); --------------------------------------------------------------------------- -- Halt / Idle Status Manager --------------------------------------------------------------------------- I_STS_MNGR : entity axi_vdma_v6_2.axi_vdma_sts_mngr port map( prmry_aclk => prmry_aclk , prmry_resetn => prmry_resetn , -- dma control and sg engine status signals run_stop => run_stop , regdir_idle => regdir_idle , ftch_idle => ftch_idle , cmnd_idle => cmnd_idle , sts_idle => sts_idle , line_buffer_empty => line_buffer_empty , dwidth_fifo_pipe_empty => dwidth_fifo_pipe_empty , video_prmtrs_valid => video_prmtrs_valid , prmtr_update_complete => prmtr_update_complete , -- CR605424 -- stop and halt control/status stop => stop_i , halt => halt , -- CR 625278 halt_cmplt => halt_cmplt , -- system state and control all_idle => all_idle_i , ftchcmdsts_idle => ftchcmdsts_idle , cmdsts_idle => cmdsts_idle , halted_clr => halted_clr , halted_set => halted_set , idle_set => idle_set , idle_clr => idle_clr ); --------------------------------------------------------------------------- -- Video Register Bank --------------------------------------------------------------------------- VIDEO_REG_I : entity axi_vdma_v6_2.axi_vdma_vidreg_module generic map( C_INCLUDE_SG => C_INCLUDE_SG , C_NUM_FSTORES => C_NUM_FSTORES , C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION , C_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH , C_FAMILY => C_FAMILY ) port map( prmry_aclk => prmry_aclk , prmry_resetn => prmry_resetn , -- Register update control ftch_complete => ftch_complete , ftch_complete_clr => ftch_complete_clr , parameter_update => parameter_update , video_prmtrs_valid => video_prmtrs_valid , prmtr_update_complete => prmtr_update_complete , -- CR605424 num_fstore_minus1 => num_fstore_minus1 , -- CR607089 -- Register swap control/status frame_sync => frame_sync , run_stop => run_stop , dmasr_halt => dmasr_halt , ftch_idle => ftch_idle , tailpntr_updated => tailpntr_updated , frame_number => frame_number_i , -- Register Direct Mode Video Parameter In reg_module_vsize => reg_module_vsize , reg_module_hsize => reg_module_hsize , reg_module_stride => reg_module_stride , reg_module_frmdly => reg_module_frmdly , reg_module_strt_addr => reg_module_strt_addr , -- Descriptor data/control from sg interface desc_data_wren => desc_data_wren , desc_strtaddress => desc_strtaddress , desc_vsize => desc_vsize , desc_hsize => desc_hsize , desc_stride => desc_stride , desc_frmdly => desc_frmdly , -- Scatter Gather register Bank --crnt_vsize => crnt_vsize , -- CR575884 crnt_vsize => crnt_vsize_i , -- CR575884 crnt_hsize => crnt_hsize , crnt_stride => crnt_stride , crnt_frmdly => crnt_frmdly , crnt_start_address => crnt_start_address ); --------------------------------------------------------------------------- -- Gen Lock --------------------------------------------------------------------------- VIDEO_GENLOCK_I : entity axi_vdma_v6_2.axi_vdma_genlock_mngr generic map( C_GENLOCK_MODE => C_GENLOCK_MODE , C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS , C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE , C_NUM_FSTORES => C_NUM_FSTORES ) port map( -- Secondary Clock Domain prmry_aclk => prmry_aclk , prmry_resetn => prmry_resetn , -- Dynamic Frame Store Support num_frame_store => num_frame_store , num_fstore_minus1 => num_fstore_minus1 , -- Gen-Lock Slave Signals mstr_in_control => mstr_pntr_ref , genlock_select => genlock_select , frame_ptr_in => frame_ptr_in , internal_frame_ptr_in => internal_frame_ptr_in , slv_frame_ref_out => slv_frame_ref_out , -- Gen-Lock Master Signals dmasr_halt => dmasr_halt , circular_prk_mode => circular_prk_mode , fsize_mismatch_err_flag => fsize_mismatch_err_flag_i , mstr_frame_update => valid_frame_sync_d2 , mstr_frame_ref_in => mstr_frame_ref_in , mstrfrm_tstsync_out => mstrfrm_tstsync_out , frame_ptr_out => frame_ptr_out ); end implementation;
------------------------------------------------------------------------------- -- axi_vdma_mngr ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_vdma_mngr.vhd -- Description: This entity is the top level entity for the AXI VDMA Controller -- manager. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_vdma.vhd -- |- axi_vdma_pkg.vhd -- |- axi_vdma_intrpt.vhd -- |- axi_vdma_rst_module.vhd -- | |- axi_vdma_reset.vhd (mm2s) -- | | |- axi_vdma_cdc.vhd -- | |- axi_vdma_reset.vhd (s2mm) -- | | |- axi_vdma_cdc.vhd -- | -- |- axi_vdma_reg_if.vhd -- | |- axi_vdma_lite_if.vhd -- | |- axi_vdma_cdc.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_vdma_sg_cdc.vhd (mm2s) -- |- axi_vdma_vid_cdc.vhd (mm2s) -- |- axi_vdma_fsync_gen.vhd (mm2s) -- |- axi_vdma_sof_gen.vhd (mm2s) -- |- axi_vdma_reg_module.vhd (mm2s) -- | |- axi_vdma_register.vhd (mm2s) -- | |- axi_vdma_regdirect.vhd (mm2s) -- |- axi_vdma_mngr.vhd (mm2s) -- | |- axi_vdma_sg_if.vhd (mm2s) -- | |- axi_vdma_sm.vhd (mm2s) -- | |- axi_vdma_cmdsts_if.vhd (mm2s) -- | |- axi_vdma_vidreg_module.vhd (mm2s) -- | | |- axi_vdma_sgregister.vhd (mm2s) -- | | |- axi_vdma_vregister.vhd (mm2s) -- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s) -- | | |- axi_vdma_blkmem.vhd (mm2s) -- | |- axi_vdma_genlock_mngr.vhd (mm2s) -- | |- axi_vdma_genlock_mux.vhd (mm2s) -- | |- axi_vdma_greycoder.vhd (mm2s) -- |- axi_vdma_mm2s_linebuf.vhd (mm2s) -- | |- axi_vdma_sfifo_autord.vhd (mm2s) -- | |- axi_vdma_afifo_autord.vhd (mm2s) -- | |- axi_vdma_skid_buf.vhd (mm2s) -- | |- axi_vdma_cdc.vhd (mm2s) -- | -- |- axi_vdma_sg_cdc.vhd (s2mm) -- |- axi_vdma_vid_cdc.vhd (s2mm) -- |- axi_vdma_fsync_gen.vhd (s2mm) -- |- axi_vdma_sof_gen.vhd (s2mm) -- |- axi_vdma_reg_module.vhd (s2mm) -- | |- axi_vdma_register.vhd (s2mm) -- | |- axi_vdma_regdirect.vhd (s2mm) -- |- axi_vdma_mngr.vhd (s2mm) -- | |- axi_vdma_sg_if.vhd (s2mm) -- | |- axi_vdma_sm.vhd (s2mm) -- | |- axi_vdma_cmdsts_if.vhd (s2mm) -- | |- axi_vdma_vidreg_module.vhd (s2mm) -- | | |- axi_vdma_sgregister.vhd (s2mm) -- | | |- axi_vdma_vregister.vhd (s2mm) -- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm) -- | | |- axi_vdma_blkmem.vhd (s2mm) -- | |- axi_vdma_genlock_mngr.vhd (s2mm) -- | |- axi_vdma_genlock_mux.vhd (s2mm) -- | |- axi_vdma_greycoder.vhd (s2mm) -- |- axi_vdma_s2mm_linebuf.vhd (s2mm) -- | |- axi_vdma_sfifo_autord.vhd (s2mm) -- | |- axi_vdma_afifo_autord.vhd (s2mm) -- | |- axi_vdma_skid_buf.vhd (s2mm) -- | |- axi_vdma_cdc.vhd (s2mm) -- | -- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL) -- |- axi_sg_v3_00_a.axi_sg.vhd -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_vdma_v6_2; use axi_vdma_v6_2.axi_vdma_pkg.all; ------------------------------------------------------------------------------- entity axi_vdma_mngr is generic( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1; -- Depth of DataMover command FIFO C_INCLUDE_SF : integer range 0 to 1 := 0; -- Include or exclude store and forward module -- 0 = excluded -- 1 = included C_USE_FSYNC : integer range 0 to 1 := 0; -- Specifies DMA oeration synchronized to frame sync input -- 0 = Free running -- 1 = Fsync synchronous --C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 -- --C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 -- C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1; -- Setting this make core backward compatible to 2012.4 version in terms of ports and registers C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1; -- Enable debug information bit 0 C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1; -- Enable debug information bit 1 C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1; -- Enable debug information bit 2 C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1; -- Enable debug information bit 3 C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1; -- Enable debug information bit 4 C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1; -- Enable debug information bit 5 C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1; -- Enable debug information bit 6 C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1; -- Enable debug information bit 7 C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1; -- Enable debug information bit 8 C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1; -- Enable debug information bit 9 C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1; -- Enable debug information bit 10 C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1; -- Enable debug information bit 11 C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1; -- Enable debug information bit 12 C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1; -- Enable debug information bit 13 C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1; -- Enable debug information bit 14 C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1; -- Enable debug information bit 15 C_ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0; -- CR591965 -- Specifies VDMA Flush on Frame sync enabled -- 0 = Disabled -- 1 = Enabled C_NUM_FSTORES : integer range 1 to 32 := 1; -- Number of Frame Stores C_GENLOCK_MODE : integer range 0 to 3 := 0; -- Specifies Gen-Lock Mode of operation -- 0 = Master - Channel configured to be Gen-Lock Master -- 1 = Slave - Channel configured to be Gen-Lock Slave C_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1; -- Number of Gen-Lock masters capable of controlling Gen-Lock Slave --C_GENLOCK_REPEAT_EN : integer range 0 to 1 := 0; -- CR591965 -- In flush on frame sync mode specifies whether frame number -- will increment on error'ed frame or repeat error'ed frame -- 0 = increment frame -- 1 = repeat frame ----------------------------------------------------------------------- C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1; -- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE -- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE -- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE. ----------------------------------------------------------------------- C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0; -- Enable internal genlock bus -- 0 = disable internal genlock bus -- 1 = enable internal genlock bus C_EXTEND_DM_COMMAND : integer range 0 to 1 := 0; -- Extend datamover command by padding BTT with 1's for -- indeterminate BTT mode ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_INCLUDE_SG : integer range 0 to 1 := 1 ; -- Include or Exclude Scatter Gather Engine -- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode) -- 1 = Include Scatter Gather Engine C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- AXI Master Stream in for descriptor fetch ----------------------------------------------------------------------- -- Memory Map Parameters ----------------------------------------------------------------------- C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Read Port C_DM_STATUS_WIDTH : integer := 8 ; -- CR608521 -- DataMover status width - is based on mode of operation C_S2MM_SOF_ENABLE : integer range 0 to 1 := 0; C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0; C_INCLUDE_MM2S : integer range 0 to 1 := 1; -- Include or exclude MM2S primary data path -- 0 = Exclude MM2S primary data path -- 1 = Include MM2S primary data path C_INCLUDE_S2MM : integer range 0 to 1 := 1; -- Include or exclude S2MM primary data path -- 0 = Exclude S2MM primary data path -- 1 = Include S2MM primary data path C_FAMILY : string := "virtex7" -- Target FPGA Device Family ); port ( -- Secondary Clock and Reset prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- soft_reset : in std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- -- Control and Status -- run_stop : in std_logic ; -- dmasr_halt : in std_logic ; -- dmacr_repeat_en : in std_logic ; -- sync_enable : in std_logic ; -- regdir_idle : in std_logic ; -- ftch_idle : in std_logic ; -- halt : in std_logic ; -- halt_cmplt : in std_logic ; -- halted_clr : out std_logic ; -- halted_set : out std_logic ; -- idle_set : out std_logic ; -- idle_clr : out std_logic ; -- chnl_current_frame : out std_logic_vector (FRAME_NUMBER_WIDTH-1 downto 0) ; -- genlock_pair_frame : out std_logic_vector (FRAME_NUMBER_WIDTH-1 downto 0) ; -- frame_number : out std_logic_vector (FRAME_NUMBER_WIDTH-1 downto 0) ; -- new_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0); -- new_curdesc_wren : out std_logic ; -- stop : out std_logic ; -- all_idle : out std_logic ; -- cmdsts_idle : out std_logic ; -- ftchcmdsts_idle : out std_logic ; -- fsize_mismatch_err_flag : out std_logic ; -- CR591965 fsize_mismatch_err : out std_logic ; -- CR591965 lsize_mismatch_err : out std_logic ; -- CR591965 lsize_more_mismatch_err : out std_logic ; -- CR591965 s2mm_fsize_mismatch_err_s : out std_logic ; -- CR591965 mm2s_fsize_mismatch_err_s : in std_logic ; -- CR591965 mm2s_fsize_mismatch_err_m : in std_logic ; -- CR591965 -- -- Register direct support -- prmtr_updt_complete : in std_logic ; -- reg_module_vsize : in std_logic_vector -- (VSIZE_DWIDTH-1 downto 0) ; -- reg_module_hsize : in std_logic_vector -- (HSIZE_DWIDTH-1 downto 0) ; -- reg_module_stride : in std_logic_vector -- (STRIDE_DWIDTH-1 downto 0) ; -- reg_module_frmdly : in std_logic_vector -- (FRMDLY_DWIDTH-1 downto 0) ; -- reg_module_strt_addr : in STARTADDR_ARRAY_TYPE -- (0 to C_NUM_FSTORES - 1) ; -- -- mstr_pntr_ref : in std_logic_vector(3 downto 0) ; -- (master in control) genlock_select : in std_logic ; -- frame_ptr_ref : in std_logic_vector -- (FRAME_NUMBER_WIDTH-1 downto 0) ; -- frame_ptr_in : in std_logic_vector -- ((C_GENLOCK_NUM_MASTERS -- *NUM_FRM_STORE_WIDTH)-1 downto 0) ; -- frame_ptr_out : out std_logic_vector -- (NUM_FRM_STORE_WIDTH-1 downto 0) ; -- internal_frame_ptr_in : in std_logic_vector -- (NUM_FRM_STORE_WIDTH-1 downto 0) ; -- -- update_frmstore : out std_logic ; -- CR582182 frmstr_err_addr : out std_logic_vector -- (FRAME_NUMBER_WIDTH-1 downto 0) ; -- CR582182 valid_frame_sync : out std_logic ; -- valid_frame_sync_cmb : out std_logic ; -- valid_video_prmtrs : out std_logic ; -- parameter_update : out std_logic ; -- tailpntr_updated : in std_logic ; -- frame_sync : in std_logic ; -- circular_prk_mode : in std_logic ; -- line_buffer_empty : in std_logic ; -- dwidth_fifo_pipe_empty : in std_logic ; -- crnt_vsize : out std_logic_vector -- (VSIZE_DWIDTH-1 downto 0) ; -- CR575884 num_frame_store : in std_logic_vector -- (NUM_FRM_STORE_WIDTH-1 downto 0) ; -- all_lines_xfred : in std_logic ; -- CR616211 all_lasts_rcvd : in std_logic ; -- s2mm_strm_all_lines_rcvd : in std_logic ; -- drop_fsync_d_pulse_gen_fsize_less_err : in std_logic ; -- s2mm_fsize_more_or_sof_late : in std_logic ; -- s2mm_dmasr_lsize_less_err : in std_logic ; -- s2mm_fsync_core : in std_logic ; s2mm_fsync_out_m : in std_logic ; mm2s_fsync_out_m : in std_logic ; capture_hsize_at_uf_err : out std_logic_vector(15 downto 0) ; -- Test Vector signals -- tstvect_err : out std_logic ; -- tstvect_fsync : out std_logic ; -- tstvect_frame : out std_logic_vector -- (FRAME_NUMBER_WIDTH-1 downto 0) ; -- tstvect_frm_ptr_out : out std_logic_vector -- (FRAME_NUMBER_WIDTH-1 downto 0) ; -- mstrfrm_tstsync_out : out std_logic ; -- -- -- AXI Stream Signals -- packet_sof : in std_logic ; -- -- -- Primary DMA Errors -- dma_interr_set_minus_frame_errors : out std_logic ; -- dma_interr_set : out std_logic ; -- dma_slverr_set : out std_logic ; -- dma_decerr_set : out std_logic ; -- -- -- SG Descriptor Fetch AXI Stream In -- m_axis_ftch_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_ftch_tvalid : in std_logic ; -- m_axis_ftch_tready : out std_logic ; -- m_axis_ftch_tlast : in std_logic ; -- -- -- User Command Interface Ports (AXI Stream) -- s_axis_cmd_tvalid : out std_logic ; -- s_axis_cmd_tready : in std_logic ; -- s_axis_cmd_tdata : out std_logic_vector -- ((C_M_AXI_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- User Status Interface Ports (AXI Stream) -- m_axis_sts_tvalid : in std_logic ; -- m_axis_sts_tready : out std_logic ; -- m_axis_sts_tdata : in std_logic_vector -- (C_DM_STATUS_WIDTH-1 downto 0); -- CR608521 m_axis_sts_tkeep : in std_logic_vector -- ((C_DM_STATUS_WIDTH/8)-1 downto 0) ; -- CR608521 err : in std_logic ; -- -- ftch_err : in std_logic -- ); end axi_vdma_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_vdma_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Zero vector for tying off unused inputs constant ZERO_VALUE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Primary DataMover Command signals signal cmnd_wr : std_logic := '0'; signal cmnd_data : std_logic_vector ((C_M_AXI_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0'); signal cmnd_pending : std_logic := '0'; signal sts_received : std_logic := '0'; -- Primary DataMover Status signals signal done : std_logic := '0'; signal stop_i : std_logic := '0'; signal interr : std_logic := '0'; signal interr_minus_frame_errors : std_logic := '0'; signal slverr : std_logic := '0'; signal decerr : std_logic := '0'; signal tag : std_logic_vector(3 downto 0) := (others => '0'); signal dma_err : std_logic := '0'; --signal error : std_logic := '0'; signal zero_size_err : std_logic := '0'; signal fsize_mismatch_err_i : std_logic := '0'; -- CR591965 signal lsize_mismatch_err_i : std_logic := '0'; -- CR591965 signal lsize_more_mismatch_err_i : std_logic := '0'; -- CR591965 signal cmnd_idle : std_logic := '0'; signal sts_idle : std_logic := '0'; signal ftch_complete : std_logic := '0'; signal ftch_complete_clr : std_logic := '0'; signal video_prmtrs_valid : std_logic := '0'; signal prmtr_update_complete : std_logic := '0'; -- CR605424 --Descriptor video xfer parameters signal desc_data_wren : std_logic := '0'; signal desc_strtaddress : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal desc_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); signal desc_hsize : std_logic_vector(HSIZE_DWIDTH-1 downto 0) := (others => '0'); signal desc_stride : std_logic_vector(STRIDE_DWIDTH-1 downto 0) := (others => '0'); signal desc_frmdly : std_logic_vector(FRMDLY_DWIDTH-1 downto 0) := (others => '0'); -- Scatter Gather register Bank signal crnt_vsize_i : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884 signal crnt_hsize : std_logic_vector(HSIZE_DWIDTH-1 downto 0) := (others => '0'); signal crnt_stride : std_logic_vector(STRIDE_DWIDTH-1 downto 0) := (others => '0'); signal crnt_frmdly : std_logic_vector(FRMDLY_DWIDTH-1 downto 0) := (others => '0'); signal crnt_start_address : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0'); signal frame_number_i : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal mstr_frame_ref_in : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal slv_frame_ref_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal valid_frame_sync_i : std_logic := '0'; signal valid_frame_sync_d2 : std_logic := '0'; signal initial_frame : std_logic := '0'; signal tstvect_fsync_d1 : std_logic := '0'; signal tstvect_fsync_d2 : std_logic := '0'; signal repeat_frame : std_logic := '0'; -- CR591965 signal repeat_frame_nmbr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); -- CR591965 signal s_h_frame_number : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); -- CR582182 signal dm_prev_frame_number : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); -- CR582182 signal all_idle_d1 : std_logic := '0'; -- CR582182 signal all_idle_re : std_logic := '0'; -- CR582182 signal all_idle_i : std_logic := '0'; -- CR582182 signal late_idle : std_logic := '0'; -- CR582182 signal frame_sync_d1 : std_logic := '0'; signal frame_sync_d2 : std_logic := '0'; signal err_d1 : std_logic := '0'; -- Dynamic frame store support signal num_fstore_minus1_cmb : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0'); signal num_fstore_minus1 : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal num_fstore_equal_one : std_logic := '0'; signal fsize_mismatch_err_flag_i : std_logic := '0'; signal flag_to_repeat_after_fsize_less_err : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin fsize_mismatch_err_flag <= fsize_mismatch_err_flag_i ; -- Number of fstore value set in register is 0x01. num_fstore_equal_one <= '1' when num_fstore_minus1 = ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) else '0'; -- Pass errors to register module dma_interr_set <= interr ; dma_interr_set_minus_frame_errors <= interr_minus_frame_errors ; dma_slverr_set <= slverr ; dma_decerr_set <= decerr ; -- Route out to map to reset module for halt/recover of datamover fsize_mismatch_err <= fsize_mismatch_err_i; -- CR591965 lsize_mismatch_err <= lsize_mismatch_err_i; -- CR591965 lsize_more_mismatch_err <= lsize_more_mismatch_err_i; -- CR591965 -- Pass current vertical size out for line tracking in linebuffers crnt_vsize <= crnt_vsize_i; -- CR575884 -- Pass out to allow masking of fsync_out when parameters are not valid. valid_video_prmtrs <= video_prmtrs_valid; all_idle <= all_idle_i; -- CR582182 --***************************************************************************** -- Frame sync for incrementing frame_number. This sync is qualified with -- video parameter valid to prevent incrementing frame_number on first frame. -- So valid_frame_sync will assert after first frame and then every frame -- after that. --***************************************************************************** -- Qualify frame sync with valid parameters to allow for -- clean video startup valid_frame_sync_i <= frame_sync and video_prmtrs_valid; --***************************************************************************** -- Frame Sync For Masking FSync OUT when shutting down channel for -- FrmCntEn Mode and frame count reached. (cannot move in time) --***************************************************************************** -- Pass combinatorial version for frame_count enable masking in axi_vdma_fsync_gen. valid_frame_sync_cmb <= valid_frame_sync_i; --***************************************************************************** -- INTIAL Frame Flag -- Used to keep frame_number at Zero for intial frame --***************************************************************************** -- Flag used for intializing frame number to 0. Will -- hold frame number at 0 until a valid frame sync -- occurs. REG_INITIAL_FRAME_FLAG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0' or dmasr_halt = '1')then initial_frame <= '0'; elsif(frame_sync = '1')then initial_frame <= '1'; end if; end if; end process REG_INITIAL_FRAME_FLAG; --***************************************************************************** -- Frame Store Error Address (CR582182) -- Frame number currently being operated on from a memory map perspective. -- Needed because axi stream can complete significanly prior to memory map -- completion on S2MM writes allowing for an external fsync to be seen before -- all status is returned from datamover. This memory mapped based frame -- number allows the correct frame store pointer to be updated to the -- PARK_PTR_REF register during error events. --***************************************************************************** GEN_FRMSTORE_EXTFSYNC : if C_USE_FSYNC = 1 generate begin -- Register all idle to generate re pulse for error frame store process REG_IDLE_RE : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0' )then all_idle_d1 <= '0'; else all_idle_d1 <= all_idle_i; end if; end if; end process REG_IDLE_RE; all_idle_re <= all_idle_i and not all_idle_d1; -- Case 2: Fsync asserts before Idle -- If this case and not case 3 (below) then do not sample -- frame_number but use s_h_frame_number. LATE_IDLE_CASE : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0' or all_idle_re = '1' or video_prmtrs_valid = '0')then late_idle <= '0'; elsif(frame_sync = '1' and all_idle_i = '0')then late_idle <= '1'; end if; end if; end process LATE_IDLE_CASE; -- Sample and hold frame number for special "late idle" case -- i.e. when memory map write does not complete before external -- fsync in asserts S_H_FRAME : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then s_h_frame_number <= (others => '0'); elsif(frame_sync = '1')then s_h_frame_number <= frame_number_i; end if; end if; end process S_H_FRAME; -- Sample current frame. If normal fsync to idle relationship -- then pass frame_number. If idle occurs after fsync then -- pass sample-n-held frame number. ---- REG_FRMSTORE_FRAME : process(prmry_aclk) ---- begin ---- if(prmry_aclk'EVENT and prmry_aclk = '1')then ---- -- Reset on reset and also on error delayed 1 to prevent re-assertion on transient ---- -- conditions causing wrong error frame to be logged. ---- --if(prmry_resetn = '0' or zero_size_err_d1 = '1')then ---- if(prmry_resetn = '0')then ---- frmstr_err_addr <= (others => '0'); ---- update_frmstore <= '0'; ---- ---- -- On frame size mismatch, late idle will be asserted and need ---- -- to latch in last frame (i.e. sample and held frame) into ---- -- the frame store register. ---- elsif(late_idle = '1' and fsize_mismatch_err_i = '1')then ---- frmstr_err_addr <= s_h_frame_number; ---- update_frmstore <= '1'; ---- ---- -- CR591965 capture error frame for zero size and frm mismatch ---- -- needed because these two errors are detected at the completion ---- -- of a frame ---- --elsif(zero_size_err_re = '1')then ---- elsif(zero_size_err = '1' or fsize_mismatch_err_i = '1')then ---- frmstr_err_addr <= frame_number_i; ---- update_frmstore <= '1'; ---- ---- -- Not in Park mode and Idle occurs after fsync therefore ---- -- pass sample-n-held frm number ---- -- CR583667 ---- --elsif(late_idle = '1' and all_idle_re = '1')then ---- elsif(late_idle = '1' and all_idle_re = '1' and circular_prk_mode = '1')then ---- frmstr_err_addr <= s_h_frame_number; ---- update_frmstore <= '1'; ---- ---- -- On idle assertion latch current frame number ---- -- CR583667 ---- --elsif(all_idle_re = '1')then ---- elsif(all_idle_re = '1' or circular_prk_mode = '0')then ---- frmstr_err_addr <= frame_number_i; ---- update_frmstore <= '1'; ---- --else ---- -- update_frmstore <= '0'; ---- end if; ---- end if; ---- end process REG_FRMSTORE_FRAME; frmstr_err_addr <= frame_number_i; update_frmstore <= '1'; end generate GEN_FRMSTORE_EXTFSYNC; -- If configured for internal fsync then can simply pass -- frame number to framestore value. GEN_FRMSTORE_INTFSYNC : if C_USE_FSYNC = 0 generate begin frmstr_err_addr <= frame_number_i; update_frmstore <= '1'; end generate GEN_FRMSTORE_INTFSYNC; --***************************************************************************** -- Dynamic Frame Store Support --***************************************************************************** -- One less than setting of number of frame stores. Use for reverse -- flag toggle num_fstore_minus1_cmb <= std_logic_vector(unsigned(num_frame_store) - 1); REG_NUM_FSTR_MINUS1 : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then num_fstore_minus1 <= (others =>'0'); else num_fstore_minus1 <= num_fstore_minus1_cmb(FRAME_NUMBER_WIDTH-1 downto 0); end if; end if; end process REG_NUM_FSTR_MINUS1; --***************************************************************************** -- Dynamic GenLock Slave Mode --***************************************************************************** -- Frame counter for Dynamic GenLock Slave Mode DYNAMIC_SLAVE_MODE_FRAME_CNT : if C_GENLOCK_MODE = 3 generate signal reg_frame_number_ds : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); signal rst_to_frame_zero : std_logic := '0'; signal valid_frame_sync_d1 : std_logic := '0'; --signal valid_frame_sync_d2 : std_logic := '0'; begin -- Register qualified frame sync (i.e. valid parameters and frame_sync) -- for use in IOC Threshold count wr to hold counter at intial -- value until after first frame. This is done in axi_vdma_reg_module.vhd DS_REG_VALID_FSYNC_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then valid_frame_sync <= '0'; valid_frame_sync_d1 <= '0'; valid_frame_sync_d2 <= '0'; else valid_frame_sync_d1 <= valid_frame_sync_i; valid_frame_sync_d2 <= valid_frame_sync_d1; valid_frame_sync <= valid_frame_sync_d2; end if; end if; end process DS_REG_VALID_FSYNC_OUT; -- Frame sync for test vector, delay counter, and threshold counter -- Register test vector signals out. Also used for -- delay timer and threshold counter. -- Mask with valid video parameters to prevent delay counter -- from counting at start up for external fsyncs that can -- be coming in long before starting. -- Note: tstvect_fsync output needs to be aligned exactly -- with valid_frame_sync output for use in register module to -- reset threshold counter on first frame but not on subsequent -- frames. -- coverage off DS_PROCESS_TSTVECTOR_REG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_fsync_d1 <= '0'; tstvect_fsync_d2 <= '0'; tstvect_fsync <= '0'; else tstvect_fsync_d1 <= frame_sync; tstvect_fsync_d2 <= tstvect_fsync_d1; tstvect_fsync <= tstvect_fsync_d2 and video_prmtrs_valid; end if; end if; end process DS_PROCESS_TSTVECTOR_REG; -- coverage on -- Pass frame number out for test vector -- used in verification only --tstvect_frame <= frame_number_i; -- coverage off DS_TSTVECT_FRM_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frame <= (others => '0'); elsif (dmasr_halt = '0') then tstvect_frame <= frame_number_i; --else -- tstvect_frame <= tstvect_frame; end if; end if; end process DS_TSTVECT_FRM_OUT; -- coverage on -- Calculate frame to work on based on frame delay DS_GEN_FSTORE_GRTR_ONE : if C_NUM_FSTORES > 1 generate begin -- Register to break long timing paths DS_REG_EXT_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then reg_frame_number_ds <= (others => '0'); else reg_frame_number_ds <= slv_frame_ref_out; end if; end if; end process DS_REG_EXT_FRM_NUMBER; end generate DS_GEN_FSTORE_GRTR_ONE; DS_GEN_FSTORE_EQL_ONE : if C_NUM_FSTORES = 1 generate begin reg_frame_number_ds <= slv_frame_ref_out; end generate DS_GEN_FSTORE_EQL_ONE; --************************************************************************* --** VERIFICATION ONLY RTL --************************************************************************* -- coverage off -- TSTVECT_FTPTR_OUT : process(reg_frame_number_ds) DS_TSTVECT_FTPTR_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frm_ptr_out <= (others => '0'); elsif (dmasr_halt = '0') then tstvect_frm_ptr_out <= reg_frame_number_ds(FRAME_NUMBER_WIDTH-1 downto 0); --else --tstvect_frm_ptr_out <= tstvect_frm_ptr_out; end if; end if; end process DS_TSTVECT_FTPTR_OUT; -- coverage on --************************************************************************* --** END VERIFICATION ONLY RTL --************************************************************************* ------------------------------------------------------------------------------- -- Include State Machine and support logic ------------------------------------------------------------------------------- rst_to_frame_zero <= '1' when (dmasr_halt = '1') or (initial_frame = '0' and sync_enable = '0' and circular_prk_mode = '1') else '0'; -- CR582183 incorrect frame delay on first frame -- Delay fsync 2 pipeline stages to allow crnt_frmdly to propogate to -- the correct value for frame_number_i sampling for genlock slave mode DS_REG_DELAY_FSYNC : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then frame_sync_d1 <= '0'; frame_sync_d2 <= '0'; else frame_sync_d1 <= frame_sync; frame_sync_d2 <= frame_sync_d1; end if; end if; end process DS_REG_DELAY_FSYNC; -- Frame Number generation DS_REG_FRAME_COUNT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then -- Clear at reset or stopped or first valid fsync not occured if(prmry_resetn = '0' or rst_to_frame_zero = '1')then frame_number_i <= (others => '0'); -- GenLock Mode and Not in Park Mode (i.e. in tail ptr mode) -- elsif(valid_frame_sync_i = '1' and sync_enable = '1' and circular_prk_mode = '1')then -- latch with frame_sync when doing gen lock to proper capture initial frame ptr in. -- CR582183 incorrect frame delay on first frame --elsif(frame_sync = '1' and sync_enable = '1' and circular_prk_mode = '1')then --elsif(frame_sync_d2 = '1' and sync_enable = '1' and circular_prk_mode = '1')then --elsif(fsize_mismatch_err_flag_i= '1')then elsif(flag_to_repeat_after_fsize_less_err= '1')then frame_number_i <= frame_number_i; elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and circular_prk_mode = '1')then frame_number_i <= reg_frame_number_ds(FRAME_NUMBER_WIDTH-1 downto 0); -- Otherwise all other changes are on frame sync boudnary. elsif(valid_frame_sync_d2 = '1')then -- If Park is enabled if(circular_prk_mode = '0')then frame_number_i <= frame_ptr_ref; -- Frame count reached terminal count therefore roll count over --elsif(frame_number_i = FRAME_NUMBER_TC)then elsif(frame_number_i = num_fstore_minus1)then frame_number_i <= (others => '0'); -- Increment frame count with each sync if valid prmtr values -- stored. else frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 1); end if; end if; end if; end process DS_REG_FRAME_COUNT; frame_number <= frame_number_i; --pass Dynamic Genlock Slave's current working frame number for grey encoding and then output mstr_frame_ref_in <= frame_number_i; REG_CURR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then chnl_current_frame <= (others => '0'); else chnl_current_frame <= frame_number_i; end if; end if; end process REG_CURR_FRM_NUMBER; ----chnl_current_frame <= frame_number_i; ----genlock_pair_frame <= slv_frame_ref_out; REG_PAIR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then genlock_pair_frame <= (others => '0'); else genlock_pair_frame <= slv_frame_ref_out; end if; end if; end process REG_PAIR_FRM_NUMBER; end generate DYNAMIC_SLAVE_MODE_FRAME_CNT; --***************************************************************************** -- GEN-LOCK Slave Mode --***************************************************************************** -- Frame counter for Gen-Lock Slave Mode SLAVE_MODE_FRAME_CNT : if C_GENLOCK_MODE = 1 generate constant ONE_FSTORE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(1,NUM_FRM_STORE_WIDTH)); signal ext_frame_number_grtr : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal ext_frame_number_lesr : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal reg_frame_number_grtr : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal reg_frame_number_lesr : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal ext_slv_frmref : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal ext_crnt_frmdly : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal ext_num_fstore : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0'); signal rst_to_frame_zero : std_logic := '0'; signal valid_frame_sync_d1 : std_logic := '0'; --signal valid_frame_sync_d2 : std_logic := '0'; begin -- Register qualified frame sync (i.e. valid parameters and frame_sync) -- for use in IOC Threshold count wr to hold counter at intial -- value until after first frame. This is done in axi_vdma_reg_module.vhd S_REG_VALID_FSYNC_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then valid_frame_sync <= '0'; valid_frame_sync_d1 <= '0'; valid_frame_sync_d2 <= '0'; else valid_frame_sync_d1 <= valid_frame_sync_i; valid_frame_sync_d2 <= valid_frame_sync_d1; valid_frame_sync <= valid_frame_sync_d2; end if; end if; end process S_REG_VALID_FSYNC_OUT; -- Frame sync for test vector, delay counter, and threshold counter -- Register test vector signals out. Also used for -- delay timer and threshold counter. -- Mask with valid video parameters to prevent delay counter -- from counting at start up for external fsyncs that can -- be coming in long before starting. -- Note: tstvect_fsync output needs to be aligned exactly -- with valid_frame_sync output for use in register module to -- reset threshold counter on first frame but not on subsequent -- frames. S_PROCESS_TSTVECTOR_REG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_fsync_d1 <= '0'; tstvect_fsync_d2 <= '0'; tstvect_fsync <= '0'; else tstvect_fsync_d1 <= frame_sync; tstvect_fsync_d2 <= tstvect_fsync_d1; tstvect_fsync <= tstvect_fsync_d2 and video_prmtrs_valid; end if; end if; end process S_PROCESS_TSTVECTOR_REG; -- Pass frame number out for test vector -- used in verification only --tstvect_frame <= frame_number_i; -- coverage off S_TSTVECT_FRM_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frame <= (others => '0'); elsif (dmasr_halt = '0') then tstvect_frame <= frame_number_i; --else -- tstvect_frame <= tstvect_frame; end if; end if; end process S_TSTVECT_FRM_OUT; -- coverage on -- Calculate frame to work on based on frame delay GEN_FSTORE_GRTR_ONE : if C_NUM_FSTORES > 1 generate begin -- Extend unsigned vectors by 1 bit to allow for -- carry out during addition. --ext_slv_frmref <= '0' & slv_frame_ref_out; --ext_crnt_frmdly <= '0' & crnt_frmdly; ext_slv_frmref <= "00" & slv_frame_ref_out; ext_crnt_frmdly <= "00" & crnt_frmdly; ext_num_fstore <= '0' & num_frame_store; -- Calculate for when frame delay less than or equal to slave frame ref. This is -- normal operation where a simple subtraction of frame delay from slave frame ref -- will work. ext_frame_number_lesr <= std_logic_vector(unsigned(ext_slv_frmref) - unsigned(ext_crnt_frmdly)); -- Calculate for when frame delay greater than slave frame ref. This is roll-over -- point, i.e. if slave frame ref = 0 then you want frame number to be C_NUM_FSTORES-1 -- This can be calculated with (C_NUM_FSTORES + Slave Frame Ref) - Frame Delay --ext_frame_number_grtr <= std_logic_vector( (C_NUM_FSTORES + unsigned(ext_slv_frmref)) -- - unsigned(ext_crnt_frmdly)); ext_frame_number_grtr <= std_logic_vector( (unsigned(ext_num_fstore) + unsigned(ext_slv_frmref)) - unsigned(ext_crnt_frmdly)); -- Register to break long timing paths REG_EXT_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then reg_frame_number_grtr <= (others => '0'); reg_frame_number_lesr <= (others => '0'); -- If frame stores set to 1 then simply pass unmodified version -- through elsif(num_frame_store = ONE_FSTORE)then reg_frame_number_grtr <= ext_slv_frmref; reg_frame_number_lesr <= ext_slv_frmref; else reg_frame_number_grtr <= ext_frame_number_grtr; reg_frame_number_lesr <= ext_frame_number_lesr; end if; end if; end process REG_EXT_FRM_NUMBER; end generate GEN_FSTORE_GRTR_ONE; -- For frame stores = 1 then frame delay has no meaning. GEN_FSTORE_EQL_ONE : if C_NUM_FSTORES = 1 generate begin reg_frame_number_grtr <= ext_slv_frmref; reg_frame_number_lesr <= ext_slv_frmref; end generate GEN_FSTORE_EQL_ONE; --************************************************************************* --** VERIFICATION ONLY RTL --************************************************************************* -- coverage off ---- TSTVECT_FTPTR_OUT : process(crnt_frmdly, ---- slv_frame_ref_out, ---- reg_frame_number_lesr, ---- reg_frame_number_grtr) ---- begin ---- if(crnt_frmdly <= slv_frame_ref_out)then ---- tstvect_frm_ptr_out <= reg_frame_number_lesr(FRAME_NUMBER_WIDTH-1 downto 0); ---- else ---- tstvect_frm_ptr_out <= reg_frame_number_grtr(FRAME_NUMBER_WIDTH-1 downto 0); ---- end if; ---- end process TSTVECT_FTPTR_OUT; S_TSTVECT_FTPTR_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frm_ptr_out <= (others => '0'); elsif (dmasr_halt = '0') then if(crnt_frmdly <= slv_frame_ref_out)then tstvect_frm_ptr_out <= reg_frame_number_lesr(FRAME_NUMBER_WIDTH-1 downto 0); else tstvect_frm_ptr_out <= reg_frame_number_grtr(FRAME_NUMBER_WIDTH-1 downto 0); end if; --else --tstvect_frm_ptr_out <= tstvect_frm_ptr_out; end if; end if; end process S_TSTVECT_FTPTR_OUT; -- coverage on --************************************************************************* --** END VERIFICATION ONLY RTL --************************************************************************* ------------------------------------------------------------------------------- -- Include State Machine and support logic ------------------------------------------------------------------------------- rst_to_frame_zero <= '1' when (dmasr_halt = '1') or (initial_frame = '0' and sync_enable = '0' and circular_prk_mode = '1') else '0'; -- CR582183 incorrect frame delay on first frame -- Delay fsync 2 pipeline stages to allow crnt_frmdly to propogate to -- the correct value for frame_number_i sampling for genlock slave mode REG_DELAY_FSYNC : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then frame_sync_d1 <= '0'; frame_sync_d2 <= '0'; else frame_sync_d1 <= frame_sync; frame_sync_d2 <= frame_sync_d1; end if; end if; end process REG_DELAY_FSYNC; -- Frame Number generation REG_FRAME_COUNT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then -- Clear at reset or stopped or first valid fsync not occured if(prmry_resetn = '0' or rst_to_frame_zero = '1')then frame_number_i <= (others => '0'); -- GenLock Mode and Not in Park Mode (i.e. in tail ptr mode) -- elsif(valid_frame_sync_i = '1' and sync_enable = '1' and circular_prk_mode = '1')then -- latch with frame_sync when doing gen lock to proper capture initial frame ptr in. -- CR582183 incorrect frame delay on first frame --elsif(frame_sync = '1' and sync_enable = '1' and circular_prk_mode = '1')then --elsif(fsize_mismatch_err_flag_i= '1')then elsif(flag_to_repeat_after_fsize_less_err= '1')then frame_number_i <= frame_number_i; elsif(frame_sync_d2 = '1' and sync_enable = '1' and circular_prk_mode = '1')then -- If frame delay less than or equal slave frame reference -- then simply subtract if(crnt_frmdly <= slv_frame_ref_out)then frame_number_i <= reg_frame_number_lesr(FRAME_NUMBER_WIDTH-1 downto 0); else frame_number_i <= reg_frame_number_grtr(FRAME_NUMBER_WIDTH-1 downto 0); end if; -- Otherwise all other changes are on frame sync boudnary. elsif(valid_frame_sync_d2 = '1')then -- If Park is enabled if(circular_prk_mode = '0')then frame_number_i <= frame_ptr_ref; -- Frame count reached terminal count therefore roll count over --elsif(frame_number_i = FRAME_NUMBER_TC)then elsif(frame_number_i = num_fstore_minus1)then frame_number_i <= (others => '0'); -- Increment frame count with each sync if valid prmtr values -- stored. else frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 1); end if; end if; end if; end process REG_FRAME_COUNT; frame_number <= frame_number_i; --pass Genlock Slave's current working frame number for grey encoding and then output -- CR 703788 --mstr_frame_ref_in <= (others => '0'); -- Not Used in Slave Mode mstr_frame_ref_in <= frame_number_i; -- CR 703788 REG_CURR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then chnl_current_frame <= (others => '0'); else chnl_current_frame <= frame_number_i; end if; end if; end process REG_CURR_FRM_NUMBER; ----chnl_current_frame <= frame_number_i; ----genlock_pair_frame <= slv_frame_ref_out; REG_PAIR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then genlock_pair_frame <= (others => '0'); else genlock_pair_frame <= slv_frame_ref_out; end if; end if; end process REG_PAIR_FRM_NUMBER; end generate SLAVE_MODE_FRAME_CNT; --***************************************************************************** -- Dynamic GenLock Master Mode --***************************************************************************** -- Frame counter for Gen-Lock Master Mode DYNAMIC_MASTER_MODE_FRAME_CNT : if C_GENLOCK_MODE = 2 generate signal valid_frame_sync_d1 : std_logic := '0'; --signal flag_to_repeat_after_fsize_less_err : std_logic := '0'; --signal valid_frame_sync_d2 : std_logic := '0'; begin -- Register qualified frame sync (i.e. valid parameters and frame_sync) -- for use in IOC Threshold count wr to hold counter at intial -- value until after first frame. This is done in axi_vdma_reg_module.vhd DM_REG_VALID_FSYNC_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then valid_frame_sync <= '0'; valid_frame_sync_d1 <= '0'; valid_frame_sync_d2 <= '0'; else valid_frame_sync_d1 <= valid_frame_sync_i; valid_frame_sync_d2 <= valid_frame_sync_d1; valid_frame_sync <= valid_frame_sync_d2; end if; end if; end process DM_REG_VALID_FSYNC_OUT; -- Frame sync for test vector, delay counter, and threshold counter -- Register test vector signals out. Also used for -- delay timer and threshold counter. ---- DM_PROCESS_TSTVECTOR_REG : process(prmry_aclk) ---- begin ---- if(prmry_aclk'EVENT and prmry_aclk = '1')then ---- if(prmry_resetn = '0')then ---- tstvect_fsync_d1<= '0'; ---- tstvect_fsync_d2<= '0'; ---- tstvect_frame <= (others => '0'); ---- else ---- tstvect_fsync_d1<= frame_sync; ---- tstvect_fsync_d2<= tstvect_fsync_d1; ---- tstvect_frame <= frame_number_i; ---- end if; ---- end if; ---- end process DM_PROCESS_TSTVECTOR_REG; -- coverage off DM_PROCESS_TSTVECTOR_REG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_fsync_d1 <= '0'; tstvect_fsync_d2 <= '0'; tstvect_fsync <= '0'; else tstvect_fsync_d1 <= frame_sync; tstvect_fsync_d2 <= tstvect_fsync_d1; tstvect_fsync <= tstvect_fsync_d2 and video_prmtrs_valid; end if; end if; end process DM_PROCESS_TSTVECTOR_REG; DM_TSTVECT_FRM_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frame <= (others => '0'); elsif (dmasr_halt = '0') then tstvect_frame <= frame_number_i; --else -- tstvect_frame <= tstvect_frame; end if; end if; end process DM_TSTVECT_FRM_OUT; -- coverage on -- Mask with valid video parameters to prevent delay counter -- from counting at start up for external fsyncs that can -- be coming in long before starting. -- video_prmtrs_valid asserts on clock cycle following assertion -- of frame_sync, thus pipeline delay to create tstvect_fsync_d1 -- is required to assert first fsync for first valid frame -- Note: tstvect_fsync output needs to be aligned exactly -- with valid_frame_sync output for use in register module to -- reset threshold counter on first frame but not on subsequent -- frames. --tstvect_fsync <= tstvect_fsync_d1 and video_prmtrs_valid; --tstvect_fsync <= tstvect_fsync_d2 and video_prmtrs_valid; DM_GEN_FSTORE_GRTR_TWO : if C_NUM_FSTORES > 2 generate begin ------------------------------------------------------------------------------- -- Include State Machine and support logic ------------------------------------------------------------------------------- -- Frame Number generation DM_REG_FRAME_COUNT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then -- Clear at reset or stopped or first valid fsync not occured if(prmry_resetn = '0' or dmasr_halt = '1' or (circular_prk_mode = '1' and initial_frame = '0') or num_fstore_equal_one = '1')then frame_number_i <= (others => '0'); -- If Park is enabled then on frame sync transision to -- frame pointer reference. --elsif(fsize_mismatch_err_flag_i= '1')then elsif(flag_to_repeat_after_fsize_less_err= '1')then frame_number_i <= frame_number_i; elsif(valid_frame_sync_d2 = '1' and circular_prk_mode = '0')then frame_number_i <= frame_ptr_ref; ------------------------------------------------------------------------------------------------------------ -- On Repeat Frame simply hold current frame number (CR591965) --elsif(repeat_frame = '1')then elsif(repeat_frame = '1' and dmacr_repeat_en = '1')then frame_number_i <= repeat_frame_nmbr; ------------------------------------------------------------------------------------------------------------ -- Frame count reached terminal count therefore roll count over --elsif(valid_frame_sync_i = '1' and frame_number_i = FRAME_NUMBER_TC)then elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and frame_number_i = num_fstore_minus1 and (slv_frame_ref_out /= "00000"))then frame_number_i <= (others => '0'); elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and frame_number_i = num_fstore_minus1 and (slv_frame_ref_out = "00000"))then frame_number_i <= "00001"; elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and slv_frame_ref_out = num_fstore_minus1 and (frame_number_i = std_logic_vector(unsigned(slv_frame_ref_out) - 1)))then frame_number_i <= (others => '0'); elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (slv_frame_ref_out /= num_fstore_minus1) and (slv_frame_ref_out /= "00000") and (frame_number_i = std_logic_vector(unsigned(slv_frame_ref_out) - 1)))then frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 2); -- Increment frame count with each sync if valid prmtr values -- stored. elsif(valid_frame_sync_d2 = '1' and frame_number_i = num_fstore_minus1)then frame_number_i <= (others => '0'); elsif(valid_frame_sync_d2 = '1')then frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 1); end if; end if; end process DM_REG_FRAME_COUNT; end generate DM_GEN_FSTORE_GRTR_TWO; DM_GEN_FSTORES_EQL_TWO : if C_NUM_FSTORES = 2 generate begin ------------------------------------------------------------------------------- -- Include State Machine and support logic ------------------------------------------------------------------------------- -- Frame Number generation DM_REG_FRAME_COUNT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then -- Clear at reset or stopped or first valid fsync not occured if(prmry_resetn = '0' or dmasr_halt = '1' or (circular_prk_mode = '1' and initial_frame = '0') or num_fstore_equal_one = '1')then frame_number_i <= (others => '0'); -- If Park is enabled then on frame sync transision to -- frame pointer reference. --elsif(fsize_mismatch_err_flag_i= '1')then elsif(flag_to_repeat_after_fsize_less_err= '1')then frame_number_i <= frame_number_i; elsif(valid_frame_sync_d2 = '1' and circular_prk_mode = '0')then frame_number_i <= frame_ptr_ref; ------------------------------------------------------------------------------------------------------------ -- On Repeat Frame simply hold current frame number (CR591965) --elsif(repeat_frame = '1')then elsif(repeat_frame = '1' and dmacr_repeat_en = '1')then frame_number_i <= repeat_frame_nmbr; ------------------------------------------------------------------------------------------------------------ -- Frame count reached terminal count therefore roll count over --elsif(valid_frame_sync_i = '1' and frame_number_i = FRAME_NUMBER_TC)then elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (frame_number_i = "00001") and (slv_frame_ref_out = "00001"))then frame_number_i <= (others => '0'); elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (frame_number_i = "00001") and (slv_frame_ref_out = "00000"))then frame_number_i <= "00001"; elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (frame_number_i = "00000") and (slv_frame_ref_out = "00001"))then frame_number_i <= (others => '0'); elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (frame_number_i = "00000") and (slv_frame_ref_out = "00000"))then frame_number_i <="00001" ; elsif(valid_frame_sync_d2 = '1' and frame_number_i = "00001")then frame_number_i <= (others => '0'); elsif(valid_frame_sync_d2 = '1' and frame_number_i = "00000")then frame_number_i <="00001" ; end if; end if; end process DM_REG_FRAME_COUNT; end generate DM_GEN_FSTORES_EQL_TWO; DM_GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate begin frame_number_i <= (others => '0'); end generate DM_GEN_FSTORES_EQL_ONE; DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF : if C_MM2S_SOF_ENABLE = 1 or C_S2MM_SOF_ENABLE = 1 generate begin DM_REPEAT_EN_FSIZE_LESS_ERR_FLAG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0' or valid_frame_sync_d2 = '1')then flag_to_repeat_after_fsize_less_err <= '0'; elsif(fsize_mismatch_err_i = '1')then flag_to_repeat_after_fsize_less_err <= '1'; end if; end if; end process DM_REPEAT_EN_FSIZE_LESS_ERR_FLAG; end generate DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF; DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_NO_SOF : if C_MM2S_SOF_ENABLE = 0 and C_S2MM_SOF_ENABLE = 0 generate begin flag_to_repeat_after_fsize_less_err <= '0'; end generate DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_NO_SOF; -- If flush on frame sync enabled and genlock repeat frame enabled -- then repeat errored frame on next frame sync. (CR591965) -- DM_GEN_REPEAT_FRM_LOGIC : if C_GENLOCK_REPEAT_EN = 1 and C_ENABLE_FLUSH_ON_FSYNC = 1 generate -- begin DM_REPEAT_FRAME_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then ----if(prmry_resetn = '0' or valid_frame_sync_d2 = '1')then if(prmry_resetn = '0' or (valid_frame_sync_d2 = '1' and flag_to_repeat_after_fsize_less_err = '0'))then repeat_frame_nmbr <= (others => '0'); repeat_frame <= '0'; -- Frame size mismatch elsif(fsize_mismatch_err_i='1' or flag_to_repeat_after_fsize_less_err = '1')then repeat_frame_nmbr <= s_h_frame_number; repeat_frame <= '1'; -- Line size mismatch elsif(lsize_mismatch_err_i='1' or lsize_more_mismatch_err_i ='1')then repeat_frame_nmbr <= frame_number_i; repeat_frame <= '1'; end if; end if; end process DM_REPEAT_FRAME_PROCESS; -- end generate DM_GEN_REPEAT_FRM_LOGIC; ---- -- Not in flush on frame sync mode or repeat frame not enabled (CR591965) ---- DM_GEN_NO_REPEAT_FRM_LOGIC : if C_GENLOCK_REPEAT_EN = 0 or C_ENABLE_FLUSH_ON_FSYNC = 0 generate ---- begin ---- -- never repeat frame ---- repeat_frame <= '0'; ---- repeat_frame_nmbr <= (others => '0'); ---- ---- end generate DM_GEN_NO_REPEAT_FRM_LOGIC; -- Pass Frame sync to video mstr_frame_ref_in <= dm_prev_frame_number; -- Pass frame number out to register module frame_number <= frame_number_i; -- Drive test vector to zero for GenLock master mode --tstvect_frm_ptr_out <= (others => '0'); -- Drive test vector for Dynamic GenLock master mode --tstvect_frm_ptr_out <= slv_frame_ref_out; -- coverage off -- TSTVECT_FTPTR_OUT : process(reg_frame_number_ds) DM_TSTVECT_FTPTR_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frm_ptr_out <= (others => '0'); elsif (dmasr_halt = '0') then tstvect_frm_ptr_out <= slv_frame_ref_out; --else --tstvect_frm_ptr_out <= tstvect_frm_ptr_out; end if; end if; end process DM_TSTVECT_FTPTR_OUT; -- coverage on DM_PREV_FRAME : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then dm_prev_frame_number <= (others => '0'); --elsif(valid_frame_sync_d2 = '1'and repeat_frame = '0' and fsize_mismatch_err_flag_i = '0')then ----elsif(valid_frame_sync_d2 = '1'and repeat_frame = '0' and flag_to_repeat_after_fsize_less_err = '0')then elsif(valid_frame_sync_d2 = '1'and (dmacr_repeat_en = '0' or repeat_frame = '0') and flag_to_repeat_after_fsize_less_err = '0')then dm_prev_frame_number <= frame_number_i; end if; end if; end process DM_PREV_FRAME; REG_CURR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then chnl_current_frame <= (others => '0'); else chnl_current_frame <= frame_number_i; end if; end if; end process REG_CURR_FRM_NUMBER; ----chnl_current_frame <= frame_number_i; ----genlock_pair_frame <= slv_frame_ref_out; REG_PAIR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then genlock_pair_frame <= (others => '0'); else genlock_pair_frame <= slv_frame_ref_out; end if; end if; end process REG_PAIR_FRM_NUMBER; end generate DYNAMIC_MASTER_MODE_FRAME_CNT; --***************************************************************************** -- GEN-LOCK MASTER Mode --***************************************************************************** -- Frame counter for Gen-Lock Master Mode MASTER_MODE_FRAME_CNT : if C_GENLOCK_MODE = 0 generate signal valid_frame_sync_d1 : std_logic := '0'; --signal flag_to_repeat_after_fsize_less_err : std_logic := '0'; --signal valid_frame_sync_d2 : std_logic := '0'; begin -- Register qualified frame sync (i.e. valid parameters and frame_sync) -- for use in IOC Threshold count wr to hold counter at intial -- value until after first frame. This is done in axi_vdma_reg_module.vhd M_REG_VALID_FSYNC_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then valid_frame_sync <= '0'; valid_frame_sync_d1 <= '0'; valid_frame_sync_d2 <= '0'; else valid_frame_sync_d1 <= valid_frame_sync_i; valid_frame_sync_d2 <= valid_frame_sync_d1; valid_frame_sync <= valid_frame_sync_d2; end if; end if; end process M_REG_VALID_FSYNC_OUT; ---- REG_VALID_FSYNC_OUT : process(prmry_aclk) ---- begin ---- if(prmry_aclk'EVENT and prmry_aclk = '1')then ---- if(prmry_resetn = '0')then ---- valid_frame_sync <= '0'; ---- else ---- valid_frame_sync <= valid_frame_sync_i; ---- end if; ---- end if; ---- end process REG_VALID_FSYNC_OUT; -- Frame sync for test vector, delay counter, and threshold counter -- Register test vector signals out. Also used for -- delay timer and threshold counter. ---- PROCESS_TSTVECTOR_REG : process(prmry_aclk) ---- begin ---- if(prmry_aclk'EVENT and prmry_aclk = '1')then ---- if(prmry_resetn = '0')then ---- tstvect_fsync_d1<= '0'; ---- tstvect_frame <= (others => '0'); ---- else ---- tstvect_fsync_d1<= frame_sync; ---- tstvect_frame <= frame_number_i; ---- end if; ---- end if; ---- end process PROCESS_TSTVECTOR_REG; -- coverage off M_TSTVECT_FRM_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_frame <= (others => '0'); elsif (dmasr_halt = '0') then tstvect_frame <= frame_number_i; --else -- tstvect_frame <= tstvect_frame; end if; end if; end process M_TSTVECT_FRM_OUT; M_PROCESS_TSTVECTOR_REG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then tstvect_fsync_d1 <= '0'; tstvect_fsync_d2 <= '0'; tstvect_fsync <= '0'; else tstvect_fsync_d1 <= frame_sync; tstvect_fsync_d2 <= tstvect_fsync_d1; tstvect_fsync <= tstvect_fsync_d2 and video_prmtrs_valid; end if; end if; end process M_PROCESS_TSTVECTOR_REG; -- coverage on -- Mask with valid video parameters to prevent delay counter -- from counting at start up for external fsyncs that can -- be coming in long before starting. -- video_prmtrs_valid asserts on clock cycle following assertion -- of frame_sync, thus pipeline delay to create tstvect_fsync_d1 -- is required to assert first fsync for first valid frame -- Note: tstvect_fsync output needs to be aligned exactly -- with valid_frame_sync output for use in register module to -- reset threshold counter on first frame but not on subsequent -- frames. --tstvect_fsync <= tstvect_fsync_d1 and video_prmtrs_valid; ------------------------------------------------------------------------------- -- Include State Machine and support logic ------------------------------------------------------------------------------- -- Frame Number generation REG_FRAME_COUNT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then -- Clear at reset or stopped or first valid fsync not occured if(prmry_resetn = '0' or dmasr_halt = '1' or (circular_prk_mode = '1' and initial_frame = '0'))then frame_number_i <= (others => '0'); -- If Park is enabled then on frame sync transision to -- frame pointer reference. --elsif(fsize_mismatch_err_flag_i= '1')then elsif(flag_to_repeat_after_fsize_less_err= '1')then frame_number_i <= frame_number_i; elsif(valid_frame_sync_d2 = '1' and circular_prk_mode = '0')then frame_number_i <= frame_ptr_ref; -- On Repeat Frame simply hold current frame number (CR591965) --elsif(repeat_frame = '1')then elsif(repeat_frame = '1' and dmacr_repeat_en = '1')then frame_number_i <= repeat_frame_nmbr; -- Frame count reached terminal count therefore roll count over --elsif(valid_frame_sync_i = '1' and frame_number_i = FRAME_NUMBER_TC)then elsif(valid_frame_sync_d2 = '1' and frame_number_i = num_fstore_minus1)then frame_number_i <= (others => '0'); -- Increment frame count with each sync if valid prmtr values -- stored. elsif(valid_frame_sync_d2 = '1' and video_prmtrs_valid = '1')then frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 1); end if; end if; end process REG_FRAME_COUNT; GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF : if C_MM2S_SOF_ENABLE = 1 or C_S2MM_SOF_ENABLE = 1 generate begin REPEAT_EN_FSIZE_LESS_ERR_FLAG : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0' or valid_frame_sync_d2 = '1')then flag_to_repeat_after_fsize_less_err <= '0'; elsif(fsize_mismatch_err_i = '1')then flag_to_repeat_after_fsize_less_err <= '1'; end if; end if; end process REPEAT_EN_FSIZE_LESS_ERR_FLAG; end generate GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF; GEN_REPEAT_FRM_FSIZE_LESS_ERR_NO_SOF : if C_MM2S_SOF_ENABLE = 0 and C_S2MM_SOF_ENABLE = 0 generate begin flag_to_repeat_after_fsize_less_err <= '0'; end generate GEN_REPEAT_FRM_FSIZE_LESS_ERR_NO_SOF; -- If flush on frame sync enabled and genlock repeat frame enabled -- then repeat errored frame on next frame sync. (CR591965) -- GEN_REPEAT_FRM_LOGIC : if C_GENLOCK_REPEAT_EN = 1 and C_ENABLE_FLUSH_ON_FSYNC = 1 generate -- begin REPEAT_FRAME_PROCESS : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then ----if(prmry_resetn = '0' or valid_frame_sync_d2 = '1')then if(prmry_resetn = '0' or (valid_frame_sync_d2 = '1' and flag_to_repeat_after_fsize_less_err = '0'))then repeat_frame_nmbr <= (others => '0'); repeat_frame <= '0'; -- Frame size mismatch --elsif(fsize_mismatch_err_i='1')then elsif(fsize_mismatch_err_i='1' or flag_to_repeat_after_fsize_less_err='1')then repeat_frame_nmbr <= s_h_frame_number; repeat_frame <= '1'; -- Line size mismatch elsif(lsize_mismatch_err_i='1' or lsize_more_mismatch_err_i ='1')then repeat_frame_nmbr <= frame_number_i; repeat_frame <= '1'; end if; end if; end process REPEAT_FRAME_PROCESS; --end generate GEN_REPEAT_FRM_LOGIC; ---- -- Not in flush on frame sync mode or repeat frame not enabled (CR591965) ---- GEN_NO_REPEAT_FRM_LOGIC : if C_GENLOCK_REPEAT_EN = 0 or C_ENABLE_FLUSH_ON_FSYNC = 0 generate ---- begin ---- -- never repeat frame ---- repeat_frame <= '0'; ---- repeat_frame_nmbr <= (others => '0'); ---- ---- end generate GEN_NO_REPEAT_FRM_LOGIC; -- Pass Frame sync to video mstr_frame_ref_in <= frame_number_i; -- Pass frame number out to register module frame_number <= frame_number_i; -- Drive test vector to zero for master mode tstvect_frm_ptr_out <= (others => '0'); ----chnl_current_frame <= frame_number_i; REG_CURR_FRM_NUMBER : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then chnl_current_frame <= (others => '0'); else chnl_current_frame <= frame_number_i; end if; end if; end process REG_CURR_FRM_NUMBER; ----chnl_current_frame <= frame_number_i; genlock_pair_frame <= (others => '0'); end generate MASTER_MODE_FRAME_CNT; --***************************************************************************** -- Error Handling -- For graceful shut down logic --***************************************************************************** -- Clear run/stop and stop state machines due to errors or soft reset -- Error based on datamover error report or sg fetch error -- SG fetch error included because need to shut down because data maybe corrupt -- therefor do not want to issue the xfer command to primary datamover -- Added run_stop to assertion for when run_stop is de-asserted in middle of video -- frame need to halt datamover to clear out potential pending commands. stop_i <= dma_err -- DMAIntErr, DMADecErr, DMASlvErr, ZeroSize, possibly Frame/Line Mismatch or ftch_err -- SGDecErr, SGSlvErr or soft_reset; -- Soft Reset issued -- Reg stop out REG_STOP_OUT : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then stop <= '0'; else stop <= stop_i; end if; end if; end process REG_STOP_OUT; -- For verification only - drive error detection -- out to test vector port, will be stripped during build -- (Broke up in order to capture all errors regardless of -- flush on frame sync mode) -- coverage off REG_DELAY_ERR : process(prmry_aclk) begin if(prmry_aclk'EVENT and prmry_aclk = '1')then if(prmry_resetn = '0')then err_d1 <= '0'; tstvect_err <= '0'; else err_d1 <= slverr -- DMASlvErr or decerr -- DMADecErr or interr -- DMAIntErr, ZeroSize, Frame or lsize_mismatch_err_i -- Line Mismatch or lsize_more_mismatch_err_i -- Line Mismatch or ftch_err; -- SGSlvErr, SGDecErr tstvect_err <= err_d1; end if; end if; end process REG_DELAY_ERR; -- coverage on --***************************************************************************** -- DMA Control --***************************************************************************** --------------------------------------------------------------------------- -- Primary DMA Controller State Machine --------------------------------------------------------------------------- I_SM : entity axi_vdma_v6_2.axi_vdma_sm generic map( C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH , C_INCLUDE_SF => C_INCLUDE_SF , C_USE_FSYNC => C_USE_FSYNC , -- CR591965 C_ENABLE_FLUSH_ON_FSYNC => C_ENABLE_FLUSH_ON_FSYNC , -- CR591965 C_EXTEND_DM_COMMAND => C_EXTEND_DM_COMMAND , C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH , C_MM2S_SOF_ENABLE => C_MM2S_SOF_ENABLE , C_S2MM_SOF_ENABLE => C_S2MM_SOF_ENABLE , C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_INCLUDE_S2MM => C_INCLUDE_S2MM ) port map( prmry_aclk => prmry_aclk , prmry_resetn => prmry_resetn , scndry_aclk => scndry_aclk , scndry_resetn => scndry_resetn , -- AXI Stream Qualifiers packet_sof => packet_sof , -- Raw fsync (must use unqualified frame sync for proper sm operation) frame_sync => frame_sync , -- Valid video parameter available video_prmtrs_valid => video_prmtrs_valid , -- Control and Status run_stop => run_stop , cmnd_idle => cmnd_idle , sts_idle => sts_idle , stop => stop_i , halt => halt , zero_size_err => zero_size_err , mm2s_fsync_out_m => mm2s_fsync_out_m , s2mm_fsync_out_m => s2mm_fsync_out_m , mm2s_fsize_mismatch_err_s => mm2s_fsize_mismatch_err_s , mm2s_fsize_mismatch_err_m => mm2s_fsize_mismatch_err_m , s2mm_fsize_mismatch_err_s => s2mm_fsize_mismatch_err_s , fsize_mismatch_err_flag => fsize_mismatch_err_flag_i , fsize_mismatch_err => fsize_mismatch_err_i , -- CR591965 all_lines_xfred => all_lines_xfred , -- CR616211 all_lasts_rcvd => all_lasts_rcvd , drop_fsync_d_pulse_gen_fsize_less_err => drop_fsync_d_pulse_gen_fsize_less_err , s2mm_strm_all_lines_rcvd => s2mm_strm_all_lines_rcvd , -- : out std_logic; s2mm_fsync_core => s2mm_fsync_core , -- : out std_logic; -- DataMover Command/Status cmnd_wr => cmnd_wr , cmnd_data => cmnd_data , cmnd_pending => cmnd_pending , sts_received => sts_received , -- Descriptor Fields crnt_start_address => crnt_start_address , crnt_vsize => crnt_vsize_i , -- CR575884 crnt_hsize => crnt_hsize , crnt_stride => crnt_stride ); -- If Scatter Gather engine is included then instantiate scatter gather -- interface GEN_SG_INTERFACE : if C_INCLUDE_SG = 1 generate begin --------------------------------------------------------------------------- -- Scatter Gather State Machine --------------------------------------------------------------------------- I_SG_IF : entity axi_vdma_v6_2.axi_vdma_sg_if generic map( ------------------------------------------------------------------- -- Scatter Gather Parameters ------------------------------------------------------------------- C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ) port map( prmry_aclk => prmry_aclk , prmry_resetn => prmry_resetn , dmasr_halt => dmasr_halt , ftch_idle => ftch_idle , ftch_complete => ftch_complete , ftch_complete_clr => ftch_complete_clr , -- SG Descriptor Fetch AXI Stream In m_axis_ftch_tdata => m_axis_ftch_tdata , m_axis_ftch_tvalid => m_axis_ftch_tvalid , m_axis_ftch_tready => m_axis_ftch_tready , m_axis_ftch_tlast => m_axis_ftch_tlast , -- Descriptor Field Output new_curdesc => new_curdesc , new_curdesc_wren => new_curdesc_wren , desc_data_wren => desc_data_wren , desc_strtaddress => desc_strtaddress , desc_vsize => desc_vsize , desc_hsize => desc_hsize , desc_stride => desc_stride , desc_frmdly => desc_frmdly ); end generate GEN_SG_INTERFACE; -- If Scatter Gather engine is excluded then tie off unused signals GEN_NO_SG_INTERFACE : if C_INCLUDE_SG = 0 generate begin -- Map update complete to ftch_complete signal for proper -- video paramter transfer from axi_lite registers to video registers ftch_complete <= prmtr_updt_complete; -- Signals not need for register direct mode m_axis_ftch_tready <= '0'; new_curdesc <= (others => '0'); new_curdesc_wren <= '0'; desc_data_wren <= '0'; desc_strtaddress <= (others => '0'); desc_vsize <= (others => '0'); desc_hsize <= (others => '0'); desc_stride <= (others => '0'); desc_frmdly <= (others => '0'); end generate GEN_NO_SG_INTERFACE; ------------------------------------------------------------------------------- -- Primary DataMover command status interface ------------------------------------------------------------------------------- I_CMDSTS : entity axi_vdma_v6_2.axi_vdma_cmdsts_if generic map( C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH , C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH , C_INCLUDE_MM2S => C_INCLUDE_MM2S , --C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO , C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL , C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 , C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 , C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 , C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 , C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 , C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 , C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 , C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 , C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 , C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 , C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 , C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 , C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 , C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 , C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 , C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 , C_INCLUDE_S2MM => C_INCLUDE_S2MM, C_ENABLE_FLUSH_ON_FSYNC => C_ENABLE_FLUSH_ON_FSYNC ) port map( prmry_aclk => prmry_aclk , prmry_resetn => prmry_resetn , -- Fetch command write interface from sm cmnd_wr => cmnd_wr , cmnd_data => cmnd_data , cmnd_pending => cmnd_pending , sts_received => sts_received , crnt_hsize => crnt_hsize , stop => stop_i , halt => halt , -- CR613214 dmasr_halt => dmasr_halt , -- User Command Interface Ports (AXI Stream) s_axis_cmd_tvalid => s_axis_cmd_tvalid , s_axis_cmd_tready => s_axis_cmd_tready , s_axis_cmd_tdata => s_axis_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_sts_tvalid => m_axis_sts_tvalid , m_axis_sts_tready => m_axis_sts_tready , m_axis_sts_tdata => m_axis_sts_tdata , m_axis_sts_tkeep => m_axis_sts_tkeep , s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late , s2mm_dmasr_lsize_less_err => s2mm_dmasr_lsize_less_err , -- Zero Hsize and/or Vsize. mapped here to combine with interr zero_size_err => zero_size_err , -- Frame Mismatch. mapped here to combine with interr fsize_mismatch_err => fsize_mismatch_err_i , -- CR591965 lsize_mismatch_err => lsize_mismatch_err_i , -- CR591965 lsize_more_mismatch_err => lsize_more_mismatch_err_i , -- CR591965 capture_hsize_at_uf_err => capture_hsize_at_uf_err , -- Primary DataMover Status err => err , done => done , err_o => dma_err , interr_minus_frame_errors => interr_minus_frame_errors , interr => interr , slverr => slverr , decerr => decerr , tag => tag -- Not used ); --------------------------------------------------------------------------- -- Halt / Idle Status Manager --------------------------------------------------------------------------- I_STS_MNGR : entity axi_vdma_v6_2.axi_vdma_sts_mngr port map( prmry_aclk => prmry_aclk , prmry_resetn => prmry_resetn , -- dma control and sg engine status signals run_stop => run_stop , regdir_idle => regdir_idle , ftch_idle => ftch_idle , cmnd_idle => cmnd_idle , sts_idle => sts_idle , line_buffer_empty => line_buffer_empty , dwidth_fifo_pipe_empty => dwidth_fifo_pipe_empty , video_prmtrs_valid => video_prmtrs_valid , prmtr_update_complete => prmtr_update_complete , -- CR605424 -- stop and halt control/status stop => stop_i , halt => halt , -- CR 625278 halt_cmplt => halt_cmplt , -- system state and control all_idle => all_idle_i , ftchcmdsts_idle => ftchcmdsts_idle , cmdsts_idle => cmdsts_idle , halted_clr => halted_clr , halted_set => halted_set , idle_set => idle_set , idle_clr => idle_clr ); --------------------------------------------------------------------------- -- Video Register Bank --------------------------------------------------------------------------- VIDEO_REG_I : entity axi_vdma_v6_2.axi_vdma_vidreg_module generic map( C_INCLUDE_SG => C_INCLUDE_SG , C_NUM_FSTORES => C_NUM_FSTORES , C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION , C_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH , C_FAMILY => C_FAMILY ) port map( prmry_aclk => prmry_aclk , prmry_resetn => prmry_resetn , -- Register update control ftch_complete => ftch_complete , ftch_complete_clr => ftch_complete_clr , parameter_update => parameter_update , video_prmtrs_valid => video_prmtrs_valid , prmtr_update_complete => prmtr_update_complete , -- CR605424 num_fstore_minus1 => num_fstore_minus1 , -- CR607089 -- Register swap control/status frame_sync => frame_sync , run_stop => run_stop , dmasr_halt => dmasr_halt , ftch_idle => ftch_idle , tailpntr_updated => tailpntr_updated , frame_number => frame_number_i , -- Register Direct Mode Video Parameter In reg_module_vsize => reg_module_vsize , reg_module_hsize => reg_module_hsize , reg_module_stride => reg_module_stride , reg_module_frmdly => reg_module_frmdly , reg_module_strt_addr => reg_module_strt_addr , -- Descriptor data/control from sg interface desc_data_wren => desc_data_wren , desc_strtaddress => desc_strtaddress , desc_vsize => desc_vsize , desc_hsize => desc_hsize , desc_stride => desc_stride , desc_frmdly => desc_frmdly , -- Scatter Gather register Bank --crnt_vsize => crnt_vsize , -- CR575884 crnt_vsize => crnt_vsize_i , -- CR575884 crnt_hsize => crnt_hsize , crnt_stride => crnt_stride , crnt_frmdly => crnt_frmdly , crnt_start_address => crnt_start_address ); --------------------------------------------------------------------------- -- Gen Lock --------------------------------------------------------------------------- VIDEO_GENLOCK_I : entity axi_vdma_v6_2.axi_vdma_genlock_mngr generic map( C_GENLOCK_MODE => C_GENLOCK_MODE , C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS , C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE , C_NUM_FSTORES => C_NUM_FSTORES ) port map( -- Secondary Clock Domain prmry_aclk => prmry_aclk , prmry_resetn => prmry_resetn , -- Dynamic Frame Store Support num_frame_store => num_frame_store , num_fstore_minus1 => num_fstore_minus1 , -- Gen-Lock Slave Signals mstr_in_control => mstr_pntr_ref , genlock_select => genlock_select , frame_ptr_in => frame_ptr_in , internal_frame_ptr_in => internal_frame_ptr_in , slv_frame_ref_out => slv_frame_ref_out , -- Gen-Lock Master Signals dmasr_halt => dmasr_halt , circular_prk_mode => circular_prk_mode , fsize_mismatch_err_flag => fsize_mismatch_err_flag_i , mstr_frame_update => valid_frame_sync_d2 , mstr_frame_ref_in => mstr_frame_ref_in , mstrfrm_tstsync_out => mstrfrm_tstsync_out , frame_ptr_out => frame_ptr_out ); end implementation;
entity ISSUE351 is end ISSUE351; architecture RTL of ISSUE351 is type WORD_TYPE is record KEY : integer; VALUE : integer; end record; constant WORD_NULL : WORD_TYPE := (KEY => 0, VALUE => 0); type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE; procedure dump_words(WORDS: in WORD_VECTOR) is begin end procedure; begin process variable curr_queue : WORD_VECTOR(0 to 3); begin for i in curr_queue'range loop dump_words(curr_queue(i to curr_queue'length-1)); -- Bug? end loop; wait; end process; end RTL;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1040.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s04b00x00p03n01i01040ent IS END c06s04b00x00p03n01i01040ent; ARCHITECTURE c06s04b00x00p03n01i01040arch OF c06s04b00x00p03n01i01040ent IS type A is array (1 to 10) of integer; function foo (f:integer := 3) return A is variable v: A := (1,2,3,4,5,6,7,8,9,10); begin return v; end foo; BEGIN TESTING: PROCESS variable k : integer := 0; BEGIN k := foo(3)(3); assert NOT( k=3 ) report "***PASSED TEST: c06s04b00x00p03n01i01040" severity NOTE; assert ( k=3 ) report "***FAILED TEST: c06s04b00x00p03n01i01040 - The prefix of an indexed name must be appropriate for an array type." severity ERROR; wait; END PROCESS TESTING; END c06s04b00x00p03n01i01040arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1040.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s04b00x00p03n01i01040ent IS END c06s04b00x00p03n01i01040ent; ARCHITECTURE c06s04b00x00p03n01i01040arch OF c06s04b00x00p03n01i01040ent IS type A is array (1 to 10) of integer; function foo (f:integer := 3) return A is variable v: A := (1,2,3,4,5,6,7,8,9,10); begin return v; end foo; BEGIN TESTING: PROCESS variable k : integer := 0; BEGIN k := foo(3)(3); assert NOT( k=3 ) report "***PASSED TEST: c06s04b00x00p03n01i01040" severity NOTE; assert ( k=3 ) report "***FAILED TEST: c06s04b00x00p03n01i01040 - The prefix of an indexed name must be appropriate for an array type." severity ERROR; wait; END PROCESS TESTING; END c06s04b00x00p03n01i01040arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1040.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s04b00x00p03n01i01040ent IS END c06s04b00x00p03n01i01040ent; ARCHITECTURE c06s04b00x00p03n01i01040arch OF c06s04b00x00p03n01i01040ent IS type A is array (1 to 10) of integer; function foo (f:integer := 3) return A is variable v: A := (1,2,3,4,5,6,7,8,9,10); begin return v; end foo; BEGIN TESTING: PROCESS variable k : integer := 0; BEGIN k := foo(3)(3); assert NOT( k=3 ) report "***PASSED TEST: c06s04b00x00p03n01i01040" severity NOTE; assert ( k=3 ) report "***FAILED TEST: c06s04b00x00p03n01i01040 - The prefix of an indexed name must be appropriate for an array type." severity ERROR; wait; END PROCESS TESTING; END c06s04b00x00p03n01i01040arch;
------------------------------------------------- -- VHDL code for 4:1 multiplexor -- (ESD book figure 2.5) -- by Weijun Zhang, 04/2001 -- -- Multiplexor is a device to select different -- inputs to outputs. we use 3 bits vector to -- describe its I/O ports ------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------- entity Mux is port( I3: in std_logic_vector(2 downto 0); I2: in std_logic_vector(2 downto 0); I1: in std_logic_vector(2 downto 0); I0: in std_logic_vector(2 downto 0); S: in std_logic_vector(1 downto 0); O: out std_logic_vector(2 downto 0) ); end Mux; ------------------------------------------------- architecture behv1 of Mux is begin process(I3,I2,I1,I0,S) begin -- use case statement case S is when "00" => O <= I0; when "01" => O <= I1; when "10" => O <= I2; when "11" => O <= I3; when others => O <= "ZZZ"; end case; end process; end behv1; architecture behv2 of Mux is begin -- use when.. else statement O <= I0 when S="00" else I1 when S="01" else I2 when S="10" else I3 when S="11" else "ZZZ"; end behv2; --------------------------------------------------
------------------------------------------------------------------------------- -- Title : DDS Address Generator -- Project : ------------------------------------------------------------------------------- -- File : DDSAddressGenerator.vhd -- Author : Marco Eppenberger <marco@Pierce.home> -- Company : -- Created : 2016-07-30 -- Last update: 2016-07-30 -- Platform : ModelSim, Altera Quartus -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Generator for DDS and Evelope ROM address. ------------------------------------------------------------------------------- -- Copyright (c) 2016 Marco Eppenberger ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-07-30 1.0 marco Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.Helpers_Pkg.all; entity DDSAddressGenerator is generic ( ENV_DECAY_SPEED : integer := 500; -- 500 is one second for the whole envelope (min 1, max 2^16-1) DDS_COUNTER_WIDTH : integer := 29); -- min 12 port ( Clk_CI : in std_logic; Reset_SI : in std_logic; Increment_DI : in std_logic_vector(DDS_COUNTER_WIDTH-1 downto 0); IncrementValid_SI : in std_logic; FreqTick_SI : in std_logic; DDSAddr_DO : out std_logic_vector(11 downto 0); EnvAddr_DO : out std_logic_vector(7 downto 0)); end entity DDSAddressGenerator; architecture RTL of DDSAddressGenerator is -- the last 1/8th of the wave table is the sustain part constant SUSTAIN_BEGIN_ADDR : integer := (2**(DDS_COUNTER_WIDTH-3))*7; -- Envelope Address Generation signal EnvTickCounter_DN : unsigned(15 downto 0) := (others => '0'); signal EnvTickCounter_DP : unsigned(15 downto 0) := (others => '0'); signal EnvTick_S : std_logic := '0'; signal EnvAddr_DN : unsigned(7 downto 0) := (others => '0'); signal EnvAddr_DP : unsigned(7 downto 0) := (others => '0'); signal EnvelopeDone_S : std_logic := '0'; -- DDS Address Generation signal DDSAddr_DN, DDSAddr_DP : unsigned(DDS_COUNTER_WIDTH-1 downto 0) := (others => '0'); signal IncrementBuf_D : unsigned(DDS_COUNTER_WIDTH-1 downto 0) := (others => '0'); signal SustainFlag_SN, SustainFlag_SP : std_logic := '0'; begin -- architecture RTL ----------------------------------------------------------------------------- -- DDS (Waveform) Address Generator ----------------------------------------------------------------------------- -- next DDS addr logic next_dds_addr : process (DDSAddr_DP, FreqTick_SI, IncrementBuf_D, IncrementValid_SI, SustainFlag_SP) is variable addr_tmp : unsigned(DDS_COUNTER_WIDTH-1 downto 0) := (others => '0'); variable dds_in_sustain : boolean := false; begin -- defaults DDSAddr_DN <= DDSAddr_DP; SustainFlag_SN <= SustainFlag_SP; -- add increment to address and check if in sustain region addr_tmp := DDSAddr_DP + IncrementBuf_D; dds_in_sustain := addr_tmp >= SUSTAIN_BEGIN_ADDR; -- get next DDS addr when frequency ticks if FreqTick_SI = '1' then if SustainFlag_SP = '1' and not(dds_in_sustain) then DDSAddr_DN <= addr_tmp + SUSTAIN_BEGIN_ADDR; else DDSAddr_DN <= addr_tmp; end if; end if; -- sustain flag is set from 0 to 1 when the address reaches the sustain -- part the first time if dds_in_sustain then SustainFlag_SN <= '1'; end if; -- reset when we get a new increment if IncrementValid_SI = '1' then SustainFlag_SN <= '0'; DDSAddr_DN <= (others => '0'); end if; end process next_dds_addr; -- DDS generator flipflop DDSAddrGen : process (Clk_CI) is begin -- process DDSAddrGen if Clk_CI'event and Clk_CI = '1' then if Reset_SI = '1' then IncrementBuf_D <= (others => '0'); SustainFlag_SP <= '0'; DDSAddr_DP <= (others => '0'); else if IncrementValid_SI = '1' then IncrementBuf_D <= unsigned(Increment_DI); end if; SustainFlag_SP <= SustainFlag_SN; DDSAddr_DP <= DDSAddr_DN; end if; end if; end process DDSAddrGen; -- output DDSAddr_DO <= std_logic_vector(DDSAddr_DP(DDS_COUNTER_WIDTH-1 downto DDS_COUNTER_WIDTH-12)); ----------------------------------------------------------------------------- -- Envelope Address Generator ----------------------------------------------------------------------------- -- envelope tick if counter reaches out of bounds EnvTick_S <= bool2sl(EnvTickCounter_DP >= ENV_DECAY_SPEED); -- next tick logic env_tick : process (EnvTickCounter_DP, EnvTick_S, FreqTick_SI) is begin EnvTickCounter_DN <= EnvTickCounter_DP; if FreqTick_SI = '1' then if EnvTick_S = '1' then EnvTickCounter_DN <= (others => '0'); else EnvTickCounter_DN <= EnvTickCounter_DP + 1; end if; end if; end process env_tick; -- address done EnvelopeDone_S <= bool2sl(EnvAddr_DP = 255); -- next address logic next_addr_logic : process (EnvAddr_DP, EnvTick_S, EnvelopeDone_S) is begin EnvAddr_DN <= EnvAddr_DP; if EnvTick_S = '1' and EnvelopeDone_S = '0' then EnvAddr_DN <= EnvAddr_DP + 1; end if; end process next_addr_logic; -- envelope address flipflops, also reset when new increment comes in EnvAddrGen : process (Clk_CI) is begin if Clk_CI'event and Clk_CI = '1' then if (Reset_SI = '1' or IncrementValid_SI = '1') then EnvAddr_DP <= (others => '0'); EnvTickCounter_DP <= (others => '0'); else EnvAddr_DP <= EnvAddr_DN; EnvTickCounter_DP <= EnvTickCounter_DN; end if; end if; end process EnvAddrGen; -- output EnvAddr_DO <= std_logic_vector(EnvAddr_DP); end architecture RTL;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 -- Date : Sat Jan 21 14:43:33 2017 -- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_17x16_sim_netlist.vhdl -- Design : mult_17x16 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xcku035-fbva676-3-e -- -------------------------------------------------------------------------------- `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=64) `protect key_block fPF16TcpNgM9dNC6nyb4WjUK+7bY8P+I62AEEiiM/KOMhIKuPOHBoWeWL2UjxSNO68WLeYIZp8lA I7rHN/CieA== `protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block E6OKJxjnDRUVVFwAhrQMAtoyRVVpuMKsXlca4m9CcIt6QI8vnYN0tf7gH3uVuxZ90322B7kUeFw5 Pu0UeqAoBaSyysHuDqXazxHy7oyk4BIWChvcrp7LULlVLcL76obtSwsXi1ORVmpdTi5b+AcD+WUo OP1PSFj5jpodG+LwXm4= `protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-1", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=128) `protect key_block x+agogSsgbiI6PGyBpMY8RQCDzLctIr3EaG23mH5kJHlNmNKNolnP54yJ8Y7nIFi6yl6tlyOLMoF /kxU0pyFmIj8QM0/MArMxPTiemXbDLS2VKtonyK9dDH7VbjFnRWwzK0Ngkas0+nbW3TqGPAY98x3 251QPjQoZCw3A7W9PDc= `protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block KNs7hA49BKKrboRSEkqIGldOa3ndCnhjRkSn8lL1xFfKUn+p+Wbc09ogKV6YYnPU/RaF1LbzyoE4 udPSNea4bST+08IjO5GAxXqUugcig44J+hzpGKmh7oO0TuyNbYq1CnYcsZXaD9vsmNYz8fBDoW2S VK/mYa21mBKTOuTdQ1yp3wi73aJ1G9N6Ngt7ovDUrjyd5oNxxNlvWU8JkJDinbEnci0qjZ3Wu9Wg y44pHUXf6xqwFYJpZ1ZcGRKl83P8p74+pLzt19lw9TPlTfKI++IowVjb6wo36ztNDJS0QjQE5Riv hwbPU/Bt3S82MVCY5NAA6bKC/8NnoWMbmX8Wiw== `protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" `protect encoding = (enctype="BASE64", line_length=76, bytes=256) `protect key_block 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line_length=76, bytes=256) `protect key_block OY2dawYF9tInyCemgCe6QEMkC/7TSGzSBNJnYt/Gc7EF5dCGsTH9VXcGbZ2mUocKtRfoAWdRBBEm bYfl6x6FbPUhb0/G1cVlVEQ4o/H18n5hF99JS0/fz0SNPWznJYrrCaGAm92JkSpjjAnro65+V/o9 mk6n/sqoLm3jlJlbEtRcocwBHWWmGWSA1JVq5EGq6rgZ6BzVS2QJTj0eNwmYiRwHm5C7pGUUPAmV Cpq+NReEyh8QLXu+MkLA6W5HNoZrOImyXs04lBJpjc65dBJP2XhsznwBdKX+HirxB4dO2zUVJzS/ mu4FWq0hsHmaMPi31gZ3qX43Fiv7fOwrRHPkkw== `protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa" `protect encoding = (enctype="base64", line_length=76, bytes=256) `protect key_block UpoKdwYrRaKo+uHA0pT6HjqBoVhgDYFTAVhYUatjhT0TKw0u0W/htQsFb4x/F/1WX+Ff5ztSA22r fuYQOx7SaKdiNQa9T+Uwe5fBhUbZYFfh9CTRMRLTJvjL94RMxL4C3N6tVm8vbbd6nTmK52jCWosD IiQVEYPWzIuJp8HD8re8/XAXVfmgXt582ne9Xr4rk496z2gymo9OsHuubbQsjX/+yJZ8C5lTeifG X2DJC37xBIY7LSqL/rtS2GvoBrJki3WFq8QHBp+BPdk+CbhPHpZAvvv78vOc1ewwE+YHYbjUx4+N YK2WZvPCcFynjhDUTfoohvkEMFVjoWObkMWOjA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 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: in STD_LOGIC_VECTOR ( 16 downto 0 ); B : in STD_LOGIC_VECTOR ( 15 downto 0 ); CE : in STD_LOGIC; SCLR : in STD_LOGIC; ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 ); P : out STD_LOGIC_VECTOR ( 24 downto 0 ); PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 ) ); attribute C_A_TYPE : integer; attribute C_A_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1; attribute C_A_WIDTH : integer; attribute C_A_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 17; attribute C_B_TYPE : integer; attribute C_B_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1; attribute C_B_VALUE : string; attribute C_B_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "10000001"; attribute C_B_WIDTH : integer; attribute C_B_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 16; attribute C_CCM_IMP : integer; attribute C_CCM_IMP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_CE_OVERRIDES_SCLR : integer; attribute C_CE_OVERRIDES_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_CE : integer; attribute C_HAS_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_SCLR : integer; attribute C_HAS_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_HAS_ZERO_DETECT : integer; attribute C_HAS_ZERO_DETECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_LATENCY : integer; attribute C_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 4; attribute C_MODEL_TYPE : integer; attribute C_MODEL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_MULT_TYPE : integer; attribute C_MULT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_OPTIMIZE_GOAL : integer; attribute C_OPTIMIZE_GOAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1; attribute C_OUT_HIGH : integer; attribute C_OUT_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 32; attribute C_OUT_LOW : integer; attribute C_OUT_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 8; attribute C_ROUND_OUTPUT : integer; attribute C_ROUND_OUTPUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_ROUND_PT : integer; attribute C_ROUND_PT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_VERBOSITY : integer; attribute C_VERBOSITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "kintexu"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is signal \<const0>\ : STD_LOGIC; signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_A_TYPE of i_mult : label is 1; attribute C_A_WIDTH of i_mult : label is 17; attribute C_B_TYPE of i_mult : label is 1; attribute C_B_VALUE of i_mult : label is "10000001"; attribute C_B_WIDTH of i_mult : label is 16; attribute C_CCM_IMP of i_mult : label is 0; attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0; attribute C_HAS_CE of i_mult : label is 0; attribute C_HAS_SCLR of i_mult : label is 0; attribute C_HAS_ZERO_DETECT of i_mult : label is 0; attribute C_LATENCY of i_mult : label is 4; attribute C_MODEL_TYPE of i_mult : label is 0; attribute C_MULT_TYPE of i_mult : label is 0; attribute C_OUT_HIGH of i_mult : label is 32; attribute C_OUT_LOW of i_mult : label is 8; attribute C_ROUND_OUTPUT of i_mult : label is 0; attribute C_ROUND_PT of i_mult : label is 0; attribute C_VERBOSITY of i_mult : label is 0; attribute C_XDEVICEFAMILY of i_mult : label is "kintexu"; attribute c_optimize_goal of i_mult : label is 1; attribute downgradeipidentifiedwarnings of i_mult : label is "yes"; begin PCASC(47) <= \<const0>\; PCASC(46) <= \<const0>\; PCASC(45) <= \<const0>\; PCASC(44) <= \<const0>\; PCASC(43) <= \<const0>\; PCASC(42) <= \<const0>\; PCASC(41) <= \<const0>\; PCASC(40) <= \<const0>\; PCASC(39) <= \<const0>\; PCASC(38) <= \<const0>\; PCASC(37) <= \<const0>\; PCASC(36) <= \<const0>\; PCASC(35) <= \<const0>\; PCASC(34) <= \<const0>\; PCASC(33) <= \<const0>\; PCASC(32) <= \<const0>\; PCASC(31) <= \<const0>\; PCASC(30) <= \<const0>\; PCASC(29) <= \<const0>\; PCASC(28) <= \<const0>\; PCASC(27) <= \<const0>\; PCASC(26) <= \<const0>\; PCASC(25) <= \<const0>\; PCASC(24) <= \<const0>\; PCASC(23) <= \<const0>\; PCASC(22) <= \<const0>\; PCASC(21) <= \<const0>\; PCASC(20) <= \<const0>\; PCASC(19) <= \<const0>\; PCASC(18) <= \<const0>\; PCASC(17) <= \<const0>\; PCASC(16) <= \<const0>\; PCASC(15) <= \<const0>\; PCASC(14) <= \<const0>\; PCASC(13) <= \<const0>\; PCASC(12) <= \<const0>\; PCASC(11) <= \<const0>\; PCASC(10) <= \<const0>\; PCASC(9) <= \<const0>\; PCASC(8) <= \<const0>\; PCASC(7) <= \<const0>\; PCASC(6) <= \<const0>\; PCASC(5) <= \<const0>\; PCASC(4) <= \<const0>\; PCASC(3) <= \<const0>\; PCASC(2) <= \<const0>\; PCASC(1) <= \<const0>\; PCASC(0) <= \<const0>\; ZERO_DETECT(1) <= \<const0>\; ZERO_DETECT(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); i_mult: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12_viv port map ( A(16 downto 0) => A(16 downto 0), B(15 downto 0) => B(15 downto 0), CE => '0', CLK => CLK, P(24 downto 0) => P(24 downto 0), PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0), SCLR => '0', ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( CLK : in STD_LOGIC; A : in STD_LOGIC_VECTOR ( 16 downto 0 ); B : in STD_LOGIC_VECTOR ( 15 downto 0 ); P : out STD_LOGIC_VECTOR ( 24 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_17x16,mult_gen_v12_0_12,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_gen_v12_0_12,Vivado 2016.4"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_A_TYPE : integer; attribute C_A_TYPE of U0 : label is 1; attribute C_A_WIDTH : integer; attribute C_A_WIDTH of U0 : label is 17; attribute C_B_TYPE : integer; attribute C_B_TYPE of U0 : label is 1; attribute C_B_VALUE : string; attribute C_B_VALUE of U0 : label is "10000001"; attribute C_B_WIDTH : integer; attribute C_B_WIDTH of U0 : label is 16; attribute C_CCM_IMP : integer; attribute C_CCM_IMP of U0 : label is 0; attribute C_CE_OVERRIDES_SCLR : integer; attribute C_CE_OVERRIDES_SCLR of U0 : label is 0; attribute C_HAS_CE : integer; attribute C_HAS_CE of U0 : label is 0; attribute C_HAS_SCLR : integer; attribute C_HAS_SCLR of U0 : label is 0; attribute C_HAS_ZERO_DETECT : integer; attribute C_HAS_ZERO_DETECT of U0 : label is 0; attribute C_LATENCY : integer; attribute C_LATENCY of U0 : label is 4; attribute C_MODEL_TYPE : integer; attribute C_MODEL_TYPE of U0 : label is 0; attribute C_MULT_TYPE : integer; attribute C_MULT_TYPE of U0 : label is 0; attribute C_OUT_HIGH : integer; attribute C_OUT_HIGH of U0 : label is 32; attribute C_OUT_LOW : integer; attribute C_OUT_LOW of U0 : label is 8; attribute C_ROUND_OUTPUT : integer; attribute C_ROUND_OUTPUT of U0 : label is 0; attribute C_ROUND_PT : integer; attribute C_ROUND_PT of U0 : label is 0; attribute C_VERBOSITY : integer; attribute C_VERBOSITY of U0 : label is 0; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "kintexu"; attribute c_optimize_goal : integer; attribute c_optimize_goal of U0 : label is 1; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 port map ( A(16 downto 0) => A(16 downto 0), B(15 downto 0) => B(15 downto 0), CE => '1', CLK => CLK, P(24 downto 0) => P(24 downto 0), PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0), SCLR => '0', ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0) ); end STRUCTURE;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sts_strm.vhd.vhd -- Description: This entity is the AXI Status Stream Interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_9; use axi_dma_v7_1_9.axi_dma_pkg.all; library lib_srl_fifo_v1_0_2; library lib_cdc_v1_0_2; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sts_strm is generic ( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32; -- Slave AXI Status Stream Data Width C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Descriptor Buffer Length, Transferred Bytes, and Status Stream -- Rx Length Width. Indicates the least significant valid bits of -- descriptor buffer length, transferred bytes, or Rx Length value -- in the status word coincident with tlast. C_ENABLE_SKID : integer range 0 to 1 := 0; C_FAMILY : string := "virtex5" -- Target FPGA Device Family ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- axi_prmry_aclk : in std_logic ; -- p_reset_n : in std_logic ; -- -- s2mm_stop : in std_logic ; -- -- s2mm_rxlength_valid : out std_logic ; -- s2mm_rxlength_clr : in std_logic ; -- s2mm_rxlength : out std_logic_vector -- (C_SG_LENGTH_WIDTH - 1 downto 0) ; -- -- stsstrm_fifo_rden : in std_logic ; -- stsstrm_fifo_empty : out std_logic ; -- stsstrm_fifo_dout : out std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); -- -- -- Stream to Memory Map Status Stream Interface -- s_axis_s2mm_sts_tdata : in std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- s_axis_s2mm_sts_tkeep : in std_logic_vector -- ((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); -- s_axis_s2mm_sts_tvalid : in std_logic ; -- s_axis_s2mm_sts_tready : out std_logic ; -- s_axis_s2mm_sts_tlast : in std_logic -- ); end axi_dma_s2mm_sts_strm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sts_strm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Status Stream FIFO Depth constant STSSTRM_FIFO_DEPTH : integer := 16; -- Status Stream FIFO Data Count Width (Unsused) constant STSSTRM_FIFO_CNT_WIDTH : integer := clog2(STSSTRM_FIFO_DEPTH+1); constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal fifo_full : std_logic := '0'; signal fifo_din : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); signal fifo_wren : std_logic := '0'; signal fifo_sinit : std_logic := '0'; signal rxlength_cdc_from : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_valid_cdc_from : std_logic := '0'; signal rxlength_valid_trdy : std_logic := '0'; --signal sts_tvalid_re : std_logic := '0';-- CR565502 --signal sts_tvalid_d1 : std_logic := '0';-- CR565502 signal sts_tvalid : std_logic := '0'; signal sts_tready : std_logic := '0'; signal sts_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal sts_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sts_tlast : std_logic := '0'; signal m_tvalid : std_logic := '0'; signal m_tready : std_logic := '0'; signal m_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal m_tlast : std_logic := '0'; signal tag_stripped : std_logic := '0'; signal mask_tag_write : std_logic := '0'; --signal mask_tag_hold : std_logic := '0';-- CR565502 signal skid_rst : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Primary Clock is synchronous to Secondary Clock therfore -- instantiate a sync fifo. GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate signal s2mm_stop_d1 : std_logic := '0'; signal s2mm_stop_re : std_logic := '0'; signal sts_rden : std_logic := '0'; signal follower_empty : std_logic := '0'; signal fifo_empty : std_logic := '0'; signal fifo_out : std_logic_vector (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); begin -- Generate Synchronous FIFO -- I_STSSTRM_FIFO : entity lib_srl_fifo_v1_0_2.sync_fifo_fg -- generic map ( -- C_FAMILY => C_FAMILY , -- C_MEMORY_TYPE => USE_LOGIC_FIFOS, -- C_WRITE_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, -- C_WRITE_DEPTH => STSSTRM_FIFO_DEPTH , -- C_READ_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, -- C_READ_DEPTH => STSSTRM_FIFO_DEPTH , -- C_PORTS_DIFFER => 0, -- C_HAS_DCOUNT => 1, --req for proper fifo operation -- C_DCOUNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH, -- C_HAS_ALMOST_FULL => 0, -- C_HAS_RD_ACK => 0, -- C_HAS_RD_ERR => 0, -- C_HAS_WR_ACK => 0, -- C_HAS_WR_ERR => 0, -- C_RD_ACK_LOW => 0, -- C_RD_ERR_LOW => 0, -- C_WR_ACK_LOW => 0, -- C_WR_ERR_LOW => 0, -- C_PRELOAD_REGS => 1,-- 1 = first word fall through -- C_PRELOAD_LATENCY => 0 -- 0 = first word fall through -- -- C_USE_EMBEDDED_REG => 1 -- 0 ; -- ) -- port map ( -- -- Clk => m_axi_sg_aclk , -- Sinit => fifo_sinit , -- Din => fifo_din , -- Wr_en => fifo_wren , -- Rd_en => stsstrm_fifo_rden , -- Dout => stsstrm_fifo_dout , -- Full => fifo_full , -- Empty => stsstrm_fifo_empty , -- Almost_full => open , -- Data_count => open , -- Rd_ack => open , -- Rd_err => open , -- Wr_ack => open , -- Wr_err => open -- -- ); I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f generic map ( C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, C_DEPTH => 16 , C_FAMILY => C_FAMILY ) port map ( Clk => m_axi_sg_aclk , Reset => fifo_sinit , FIFO_Write => fifo_wren , Data_In => fifo_din , FIFO_Read => sts_rden, --sts_queue_rden , Data_Out => fifo_out, --sts_queue_dout , FIFO_Empty => fifo_empty, --sts_queue_empty , FIFO_Full => fifo_full , Addr => open ); sts_rden <= (not fifo_empty) and follower_empty; stsstrm_fifo_empty <= follower_empty; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (fifo_sinit = '1' or stsstrm_fifo_rden = '1') then follower_empty <= '1'; elsif (sts_rden = '1') then follower_empty <= '0'; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (fifo_sinit = '1') then stsstrm_fifo_dout <= (others => '0'); elsif (sts_rden = '1') then stsstrm_fifo_dout <= fifo_out; end if; end if; end process; fifo_sinit <= not m_axi_sg_aresetn; fifo_din <= sts_tlast & sts_tdata; fifo_wren <= sts_tvalid and not fifo_full and not rxlength_valid_cdc_from and not mask_tag_write; sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_cdc_from; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- -- Create register delay of status tvalid in order to create a -- -- rising edge pulse. note xx_re signal will hold at 1 if -- -- fifo full on rising edge of tvalid. -- REG_TVALID : process(axi_prmry_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- sts_tvalid_d1 <= '0'; -- elsif(fifo_full = '0')then -- sts_tvalid_d1 <= sts_tvalid; -- end if; -- end if; -- end process REG_TVALID; -- -- -- rising edge on tvalid used to gate off status tag from being -- -- writen into fifo. -- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1; REG_TAG_STRIPPED : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tag_stripped <= '0'; -- Reset on write of last word elsif(fifo_wren = '1' and sts_tlast = '1')then tag_stripped <= '0'; -- Set on beginning of new status stream elsif(sts_tready = '1' and sts_tvalid = '1')then tag_stripped <= '1'; end if; end if; end process REG_TAG_STRIPPED; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- REG_MASK_TAG : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- mask_tag_hold <= '0'; -- elsif((sts_tvalid_re = '1' and tag_stripped = '0') -- or (fifo_wren = '1' and sts_tlast = '1'))then -- mask_tag_hold <= '1'; -- elsif(tag_stripped = '1')then -- mask_tag_hold <= '0'; -- end if; -- end if; -- end process; -- -- -- Mask TAG if not already masked and rising edge of tvalid -- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold); mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid; -- Generate logic to capture receive length when Use Receive Length is -- enabled GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate begin -- Register receive length on assertion of last and valid -- Mark rxlength as valid for higher processes REG_RXLENGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then rxlength_cdc_from <= (others => '0'); rxlength_valid_cdc_from <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0); rxlength_valid_cdc_from <= '1'; end if; end if; end process REG_RXLENGTH; s2mm_rxlength_valid <= rxlength_valid_cdc_from; s2mm_rxlength <= rxlength_cdc_from; end generate GEN_STS_APP_LENGTH; -- Do NOT generate logic to capture receive length when option disabled GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate begin s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); end generate GEN_NO_STS_APP_LENGTH; -- register stop to create re pulse REG_STOP : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then s2mm_stop_d1 <= '0'; else s2mm_stop_d1 <= s2mm_stop; end if; end if; end process REG_STOP; s2mm_stop_re <= s2mm_stop and not s2mm_stop_d1; skid_rst <= not m_axi_sg_aresetn; ENABLE_SKID : if C_ENABLE_SKID = 1 generate begin --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- STS_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ) port map( -- System Ports ACLK => m_axi_sg_aclk , ARST => skid_rst , skid_stop => s2mm_stop_re , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_sts_tvalid , S_READY => s_axis_s2mm_sts_tready , S_Data => s_axis_s2mm_sts_tdata , S_STRB => s_axis_s2mm_sts_tkeep , S_Last => s_axis_s2mm_sts_tlast , -- Master Side (Stream Data Output M_VALID => sts_tvalid , M_READY => sts_tready , M_Data => sts_tdata , M_STRB => sts_tkeep , M_Last => sts_tlast ); end generate ENABLE_SKID; DISABLE_SKID : if C_ENABLE_SKID = 0 generate begin sts_tvalid <= s_axis_s2mm_sts_tvalid; s_axis_s2mm_sts_tready <= sts_tready; sts_tdata <= s_axis_s2mm_sts_tdata; sts_tkeep <= s_axis_s2mm_sts_tkeep; sts_tlast <= s_axis_s2mm_sts_tlast; end generate DISABLE_SKID; end generate GEN_SYNC_FIFO; -- Primary Clock is asynchronous to Secondary Clock therfore -- instantiate an async fifo. GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate ATTRIBUTE async_reg : STRING; signal s2mm_stop_reg : std_logic := '0'; -- CR605883 signal p_s2mm_stop_d1_cdc_tig : std_logic := '0'; signal p_s2mm_stop_d2 : std_logic := '0'; signal p_s2mm_stop_d3 : std_logic := '0'; signal p_s2mm_stop_re : std_logic := '0'; --ATTRIBUTE async_reg OF p_s2mm_stop_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF p_s2mm_stop_d2 : SIGNAL IS "true"; begin -- Generate Asynchronous FIFO I_STSSTRM_FIFO : entity axi_dma_v7_1_9.axi_dma_afifo_autord generic map( C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1 , -- C_DEPTH => STSSTRM_FIFO_DEPTH , -- C_CNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH , C_DEPTH => 15 , C_CNT_WIDTH => 4 , C_USE_BLKMEM => USE_LOGIC_FIFOS , C_FAMILY => C_FAMILY ) port map( -- Inputs AFIFO_Ainit => fifo_sinit , AFIFO_Wr_clk => axi_prmry_aclk , AFIFO_Wr_en => fifo_wren , AFIFO_Din => fifo_din , AFIFO_Rd_clk => m_axi_sg_aclk , AFIFO_Rd_en => stsstrm_fifo_rden , AFIFO_Clr_Rd_Data_Valid => '0' , -- Outputs AFIFO_DValid => open , AFIFO_Dout => stsstrm_fifo_dout , AFIFO_Full => fifo_full , AFIFO_Empty => stsstrm_fifo_empty , AFIFO_Almost_full => open , AFIFO_Almost_empty => open , AFIFO_Wr_count => open , AFIFO_Rd_count => open , AFIFO_Corr_Rd_count => open , AFIFO_Corr_Rd_count_minus1 => open , AFIFO_Rd_ack => open ); fifo_sinit <= not p_reset_n; fifo_din <= sts_tlast & sts_tdata; fifo_wren <= sts_tvalid -- valid data and not fifo_full -- fifo has room and not rxlength_valid_trdy --rxlength_valid_cdc_from -- not holding a valid length and not mask_tag_write; -- not masking off tag word sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_trdy; --rxlength_valid_cdc_from; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- -- Create register delay of status tvalid in order to create a -- -- rising edge pulse. note xx_re signal will hold at 1 if -- -- fifo full on rising edge of tvalid. -- REG_TVALID : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- sts_tvalid_d1 <= '0'; -- elsif(fifo_full = '0')then -- sts_tvalid_d1 <= sts_tvalid; -- end if; -- end if; -- end process REG_TVALID; -- -- rising edge on tvalid used to gate off status tag from being -- -- writen into fifo. -- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1; REG_TAG_STRIPPED : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then tag_stripped <= '0'; -- Reset on write of last word elsif(fifo_wren = '1' and sts_tlast = '1')then tag_stripped <= '0'; -- Set on beginning of new status stream elsif(sts_tready = '1' and sts_tvalid = '1')then tag_stripped <= '1'; end if; end if; end process REG_TAG_STRIPPED; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- REG_MASK_TAG : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- mask_tag_hold <= '0'; -- elsif(tag_stripped = '1')then -- mask_tag_hold <= '0'; -- -- elsif(sts_tvalid_re = '1' -- or (fifo_wren = '1' and sts_tlast = '1'))then -- mask_tag_hold <= '1'; -- end if; -- end if; -- end process; -- -- -- Mask TAG if not already masked and rising edge of tvalid -- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold); mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid; -- Generate logic to capture receive length when Use Receive Length is -- enabled GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate signal rxlength_clr_d1_cdc_tig : std_logic := '0'; signal rxlength_clr_d2 : std_logic := '0'; signal rxlength_d1_cdc_to : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_d2 : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_valid_d1_cdc_to : std_logic := '0'; signal rxlength_valid_d2_cdc_from : std_logic := '0'; signal rxlength_valid_d3 : std_logic := '0'; signal rxlength_valid_d4 : std_logic := '0'; signal rxlength_valid_d1_back_cdc_to, rxlength_valid_d2_back : std_logic := '0'; ATTRIBUTE async_reg : STRING; --ATTRIBUTE async_reg OF rxlength_d1_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_d2 : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d1_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d1_back_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d2_back : SIGNAL IS "true"; begin -- Double register from secondary clock domain to primary S2P_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_rxlength_clr, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => rxlength_clr_d2, scndry_vect_out => open ); -- S2P_CLK_CROSS : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(p_reset_n = '0')then -- rxlength_clr_d1_cdc_tig <= '0'; -- rxlength_clr_d2 <= '0'; -- else -- rxlength_clr_d1_cdc_tig <= s2mm_rxlength_clr; -- rxlength_clr_d2 <= rxlength_clr_d1_cdc_tig; -- end if; -- end if; -- end process S2P_CLK_CROSS; -- Register receive length on assertion of last and valid -- Mark rxlength as valid for higher processes TRDY_RXLENGTH : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0' or rxlength_clr_d2 = '1')then rxlength_valid_trdy <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_valid_trdy <= '1'; end if; end if; end process TRDY_RXLENGTH; REG_RXLENGTH : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then rxlength_cdc_from <= (others => '0'); rxlength_valid_cdc_from <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0); rxlength_valid_cdc_from <= '1'; elsif (rxlength_valid_d2_back = '1') then rxlength_valid_cdc_from <= '0'; end if; end if; end process REG_RXLENGTH; SYNC_RXLENGTH : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => rxlength_valid_d2_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => rxlength_valid_d2_back, scndry_vect_out => open ); -- SYNC_RXLENGTH : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then -- -- rxlength_valid_d1_back_cdc_to <= '0'; -- rxlength_valid_d2_back <= '0'; -- else -- rxlength_valid_d1_back_cdc_to <= rxlength_valid_d2_cdc_from; -- rxlength_valid_d2_back <= rxlength_valid_d1_back_cdc_to; -- -- end if; -- end if; -- end process SYNC_RXLENGTH; -- Double register from primary clock domain to secondary P2S_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => rxlength_valid_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => rxlength_valid_d2_cdc_from, scndry_vect_out => open ); P2S_CLK_CROSS2 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_SG_LENGTH_WIDTH, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => rxlength_cdc_from, scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => rxlength_d2 ); P2S_CLK_CROSS1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0') then -- or s2mm_rxlength_clr = '1') then -- rxlength_d1_cdc_to <= (others => '0'); -- rxlength_d2 <= (others => '0'); -- rxlength_valid_d1_cdc_to <= '0'; -- rxlength_valid_d2_cdc_from <= '0'; rxlength_valid_d3 <= '0'; else -- rxlength_d1_cdc_to <= rxlength_cdc_from; -- rxlength_d2 <= rxlength_d1_cdc_to; -- rxlength_valid_d1_cdc_to <= rxlength_valid_cdc_from; -- rxlength_valid_d2_cdc_from <= rxlength_valid_d1_cdc_to; rxlength_valid_d3 <= rxlength_valid_d2_cdc_from; end if; end if; end process P2S_CLK_CROSS1; process (m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then rxlength_valid_d4 <= '0'; elsif (rxlength_valid_d3 = '1' and rxlength_valid_d2_cdc_from = '0') then rxlength_valid_d4 <= '1'; end if; end if; end process; s2mm_rxlength <= rxlength_d2; -- s2mm_rxlength_valid <= rxlength_valid_d2; s2mm_rxlength_valid <= rxlength_valid_d4; end generate GEN_STS_APP_LENGTH; -- Do NOT generate logic to capture receive length when option disabled GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); end generate GEN_NO_STS_APP_LENGTH; -- CR605883 -- Register stop to provide pure FF output for synchronizer REG_STOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_stop_reg <= '0'; else s2mm_stop_reg <= s2mm_stop; end if; end if; end process REG_STOP; -- double register s2mm error into primary clock domain REG_ERR2PRMRY : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_stop_reg, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => p_s2mm_stop_d2, scndry_vect_out => open ); REG_ERR2PRMRY1 : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then -- p_s2mm_stop_d1_cdc_tig <= '0'; -- p_s2mm_stop_d2 <= '0'; p_s2mm_stop_d3 <= '0'; else --p_s2mm_stop_d1_cdc_tig <= s2mm_stop; -- CR605883 -- p_s2mm_stop_d1_cdc_tig <= s2mm_stop_reg; -- p_s2mm_stop_d2 <= p_s2mm_stop_d1_cdc_tig; p_s2mm_stop_d3 <= p_s2mm_stop_d2; end if; end if; end process REG_ERR2PRMRY1; p_s2mm_stop_re <= p_s2mm_stop_d2 and not p_s2mm_stop_d3; skid_rst <= not p_reset_n; --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- STS_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ) port map( -- System Ports ACLK => axi_prmry_aclk , ARST => skid_rst , skid_stop => p_s2mm_stop_re , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_sts_tvalid , S_READY => s_axis_s2mm_sts_tready , S_Data => s_axis_s2mm_sts_tdata , S_STRB => s_axis_s2mm_sts_tkeep , S_Last => s_axis_s2mm_sts_tlast , -- Master Side (Stream Data Output M_VALID => sts_tvalid , M_READY => sts_tready , M_Data => sts_tdata , M_STRB => sts_tkeep , M_Last => sts_tlast ); end generate GEN_ASYNC_FIFO; end implementation;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sts_strm.vhd.vhd -- Description: This entity is the AXI Status Stream Interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_9; use axi_dma_v7_1_9.axi_dma_pkg.all; library lib_srl_fifo_v1_0_2; library lib_cdc_v1_0_2; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sts_strm is generic ( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32; -- Slave AXI Status Stream Data Width C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Descriptor Buffer Length, Transferred Bytes, and Status Stream -- Rx Length Width. Indicates the least significant valid bits of -- descriptor buffer length, transferred bytes, or Rx Length value -- in the status word coincident with tlast. C_ENABLE_SKID : integer range 0 to 1 := 0; C_FAMILY : string := "virtex5" -- Target FPGA Device Family ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- axi_prmry_aclk : in std_logic ; -- p_reset_n : in std_logic ; -- -- s2mm_stop : in std_logic ; -- -- s2mm_rxlength_valid : out std_logic ; -- s2mm_rxlength_clr : in std_logic ; -- s2mm_rxlength : out std_logic_vector -- (C_SG_LENGTH_WIDTH - 1 downto 0) ; -- -- stsstrm_fifo_rden : in std_logic ; -- stsstrm_fifo_empty : out std_logic ; -- stsstrm_fifo_dout : out std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); -- -- -- Stream to Memory Map Status Stream Interface -- s_axis_s2mm_sts_tdata : in std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- s_axis_s2mm_sts_tkeep : in std_logic_vector -- ((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); -- s_axis_s2mm_sts_tvalid : in std_logic ; -- s_axis_s2mm_sts_tready : out std_logic ; -- s_axis_s2mm_sts_tlast : in std_logic -- ); end axi_dma_s2mm_sts_strm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sts_strm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Status Stream FIFO Depth constant STSSTRM_FIFO_DEPTH : integer := 16; -- Status Stream FIFO Data Count Width (Unsused) constant STSSTRM_FIFO_CNT_WIDTH : integer := clog2(STSSTRM_FIFO_DEPTH+1); constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal fifo_full : std_logic := '0'; signal fifo_din : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); signal fifo_wren : std_logic := '0'; signal fifo_sinit : std_logic := '0'; signal rxlength_cdc_from : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_valid_cdc_from : std_logic := '0'; signal rxlength_valid_trdy : std_logic := '0'; --signal sts_tvalid_re : std_logic := '0';-- CR565502 --signal sts_tvalid_d1 : std_logic := '0';-- CR565502 signal sts_tvalid : std_logic := '0'; signal sts_tready : std_logic := '0'; signal sts_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal sts_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sts_tlast : std_logic := '0'; signal m_tvalid : std_logic := '0'; signal m_tready : std_logic := '0'; signal m_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal m_tlast : std_logic := '0'; signal tag_stripped : std_logic := '0'; signal mask_tag_write : std_logic := '0'; --signal mask_tag_hold : std_logic := '0';-- CR565502 signal skid_rst : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Primary Clock is synchronous to Secondary Clock therfore -- instantiate a sync fifo. GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate signal s2mm_stop_d1 : std_logic := '0'; signal s2mm_stop_re : std_logic := '0'; signal sts_rden : std_logic := '0'; signal follower_empty : std_logic := '0'; signal fifo_empty : std_logic := '0'; signal fifo_out : std_logic_vector (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); begin -- Generate Synchronous FIFO -- I_STSSTRM_FIFO : entity lib_srl_fifo_v1_0_2.sync_fifo_fg -- generic map ( -- C_FAMILY => C_FAMILY , -- C_MEMORY_TYPE => USE_LOGIC_FIFOS, -- C_WRITE_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, -- C_WRITE_DEPTH => STSSTRM_FIFO_DEPTH , -- C_READ_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, -- C_READ_DEPTH => STSSTRM_FIFO_DEPTH , -- C_PORTS_DIFFER => 0, -- C_HAS_DCOUNT => 1, --req for proper fifo operation -- C_DCOUNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH, -- C_HAS_ALMOST_FULL => 0, -- C_HAS_RD_ACK => 0, -- C_HAS_RD_ERR => 0, -- C_HAS_WR_ACK => 0, -- C_HAS_WR_ERR => 0, -- C_RD_ACK_LOW => 0, -- C_RD_ERR_LOW => 0, -- C_WR_ACK_LOW => 0, -- C_WR_ERR_LOW => 0, -- C_PRELOAD_REGS => 1,-- 1 = first word fall through -- C_PRELOAD_LATENCY => 0 -- 0 = first word fall through -- -- C_USE_EMBEDDED_REG => 1 -- 0 ; -- ) -- port map ( -- -- Clk => m_axi_sg_aclk , -- Sinit => fifo_sinit , -- Din => fifo_din , -- Wr_en => fifo_wren , -- Rd_en => stsstrm_fifo_rden , -- Dout => stsstrm_fifo_dout , -- Full => fifo_full , -- Empty => stsstrm_fifo_empty , -- Almost_full => open , -- Data_count => open , -- Rd_ack => open , -- Rd_err => open , -- Wr_ack => open , -- Wr_err => open -- -- ); I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f generic map ( C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, C_DEPTH => 16 , C_FAMILY => C_FAMILY ) port map ( Clk => m_axi_sg_aclk , Reset => fifo_sinit , FIFO_Write => fifo_wren , Data_In => fifo_din , FIFO_Read => sts_rden, --sts_queue_rden , Data_Out => fifo_out, --sts_queue_dout , FIFO_Empty => fifo_empty, --sts_queue_empty , FIFO_Full => fifo_full , Addr => open ); sts_rden <= (not fifo_empty) and follower_empty; stsstrm_fifo_empty <= follower_empty; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (fifo_sinit = '1' or stsstrm_fifo_rden = '1') then follower_empty <= '1'; elsif (sts_rden = '1') then follower_empty <= '0'; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (fifo_sinit = '1') then stsstrm_fifo_dout <= (others => '0'); elsif (sts_rden = '1') then stsstrm_fifo_dout <= fifo_out; end if; end if; end process; fifo_sinit <= not m_axi_sg_aresetn; fifo_din <= sts_tlast & sts_tdata; fifo_wren <= sts_tvalid and not fifo_full and not rxlength_valid_cdc_from and not mask_tag_write; sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_cdc_from; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- -- Create register delay of status tvalid in order to create a -- -- rising edge pulse. note xx_re signal will hold at 1 if -- -- fifo full on rising edge of tvalid. -- REG_TVALID : process(axi_prmry_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- sts_tvalid_d1 <= '0'; -- elsif(fifo_full = '0')then -- sts_tvalid_d1 <= sts_tvalid; -- end if; -- end if; -- end process REG_TVALID; -- -- -- rising edge on tvalid used to gate off status tag from being -- -- writen into fifo. -- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1; REG_TAG_STRIPPED : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tag_stripped <= '0'; -- Reset on write of last word elsif(fifo_wren = '1' and sts_tlast = '1')then tag_stripped <= '0'; -- Set on beginning of new status stream elsif(sts_tready = '1' and sts_tvalid = '1')then tag_stripped <= '1'; end if; end if; end process REG_TAG_STRIPPED; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- REG_MASK_TAG : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- mask_tag_hold <= '0'; -- elsif((sts_tvalid_re = '1' and tag_stripped = '0') -- or (fifo_wren = '1' and sts_tlast = '1'))then -- mask_tag_hold <= '1'; -- elsif(tag_stripped = '1')then -- mask_tag_hold <= '0'; -- end if; -- end if; -- end process; -- -- -- Mask TAG if not already masked and rising edge of tvalid -- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold); mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid; -- Generate logic to capture receive length when Use Receive Length is -- enabled GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate begin -- Register receive length on assertion of last and valid -- Mark rxlength as valid for higher processes REG_RXLENGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then rxlength_cdc_from <= (others => '0'); rxlength_valid_cdc_from <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0); rxlength_valid_cdc_from <= '1'; end if; end if; end process REG_RXLENGTH; s2mm_rxlength_valid <= rxlength_valid_cdc_from; s2mm_rxlength <= rxlength_cdc_from; end generate GEN_STS_APP_LENGTH; -- Do NOT generate logic to capture receive length when option disabled GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate begin s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); end generate GEN_NO_STS_APP_LENGTH; -- register stop to create re pulse REG_STOP : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then s2mm_stop_d1 <= '0'; else s2mm_stop_d1 <= s2mm_stop; end if; end if; end process REG_STOP; s2mm_stop_re <= s2mm_stop and not s2mm_stop_d1; skid_rst <= not m_axi_sg_aresetn; ENABLE_SKID : if C_ENABLE_SKID = 1 generate begin --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- STS_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ) port map( -- System Ports ACLK => m_axi_sg_aclk , ARST => skid_rst , skid_stop => s2mm_stop_re , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_sts_tvalid , S_READY => s_axis_s2mm_sts_tready , S_Data => s_axis_s2mm_sts_tdata , S_STRB => s_axis_s2mm_sts_tkeep , S_Last => s_axis_s2mm_sts_tlast , -- Master Side (Stream Data Output M_VALID => sts_tvalid , M_READY => sts_tready , M_Data => sts_tdata , M_STRB => sts_tkeep , M_Last => sts_tlast ); end generate ENABLE_SKID; DISABLE_SKID : if C_ENABLE_SKID = 0 generate begin sts_tvalid <= s_axis_s2mm_sts_tvalid; s_axis_s2mm_sts_tready <= sts_tready; sts_tdata <= s_axis_s2mm_sts_tdata; sts_tkeep <= s_axis_s2mm_sts_tkeep; sts_tlast <= s_axis_s2mm_sts_tlast; end generate DISABLE_SKID; end generate GEN_SYNC_FIFO; -- Primary Clock is asynchronous to Secondary Clock therfore -- instantiate an async fifo. GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate ATTRIBUTE async_reg : STRING; signal s2mm_stop_reg : std_logic := '0'; -- CR605883 signal p_s2mm_stop_d1_cdc_tig : std_logic := '0'; signal p_s2mm_stop_d2 : std_logic := '0'; signal p_s2mm_stop_d3 : std_logic := '0'; signal p_s2mm_stop_re : std_logic := '0'; --ATTRIBUTE async_reg OF p_s2mm_stop_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF p_s2mm_stop_d2 : SIGNAL IS "true"; begin -- Generate Asynchronous FIFO I_STSSTRM_FIFO : entity axi_dma_v7_1_9.axi_dma_afifo_autord generic map( C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1 , -- C_DEPTH => STSSTRM_FIFO_DEPTH , -- C_CNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH , C_DEPTH => 15 , C_CNT_WIDTH => 4 , C_USE_BLKMEM => USE_LOGIC_FIFOS , C_FAMILY => C_FAMILY ) port map( -- Inputs AFIFO_Ainit => fifo_sinit , AFIFO_Wr_clk => axi_prmry_aclk , AFIFO_Wr_en => fifo_wren , AFIFO_Din => fifo_din , AFIFO_Rd_clk => m_axi_sg_aclk , AFIFO_Rd_en => stsstrm_fifo_rden , AFIFO_Clr_Rd_Data_Valid => '0' , -- Outputs AFIFO_DValid => open , AFIFO_Dout => stsstrm_fifo_dout , AFIFO_Full => fifo_full , AFIFO_Empty => stsstrm_fifo_empty , AFIFO_Almost_full => open , AFIFO_Almost_empty => open , AFIFO_Wr_count => open , AFIFO_Rd_count => open , AFIFO_Corr_Rd_count => open , AFIFO_Corr_Rd_count_minus1 => open , AFIFO_Rd_ack => open ); fifo_sinit <= not p_reset_n; fifo_din <= sts_tlast & sts_tdata; fifo_wren <= sts_tvalid -- valid data and not fifo_full -- fifo has room and not rxlength_valid_trdy --rxlength_valid_cdc_from -- not holding a valid length and not mask_tag_write; -- not masking off tag word sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_trdy; --rxlength_valid_cdc_from; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- -- Create register delay of status tvalid in order to create a -- -- rising edge pulse. note xx_re signal will hold at 1 if -- -- fifo full on rising edge of tvalid. -- REG_TVALID : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- sts_tvalid_d1 <= '0'; -- elsif(fifo_full = '0')then -- sts_tvalid_d1 <= sts_tvalid; -- end if; -- end if; -- end process REG_TVALID; -- -- rising edge on tvalid used to gate off status tag from being -- -- writen into fifo. -- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1; REG_TAG_STRIPPED : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then tag_stripped <= '0'; -- Reset on write of last word elsif(fifo_wren = '1' and sts_tlast = '1')then tag_stripped <= '0'; -- Set on beginning of new status stream elsif(sts_tready = '1' and sts_tvalid = '1')then tag_stripped <= '1'; end if; end if; end process REG_TAG_STRIPPED; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- REG_MASK_TAG : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- mask_tag_hold <= '0'; -- elsif(tag_stripped = '1')then -- mask_tag_hold <= '0'; -- -- elsif(sts_tvalid_re = '1' -- or (fifo_wren = '1' and sts_tlast = '1'))then -- mask_tag_hold <= '1'; -- end if; -- end if; -- end process; -- -- -- Mask TAG if not already masked and rising edge of tvalid -- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold); mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid; -- Generate logic to capture receive length when Use Receive Length is -- enabled GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate signal rxlength_clr_d1_cdc_tig : std_logic := '0'; signal rxlength_clr_d2 : std_logic := '0'; signal rxlength_d1_cdc_to : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_d2 : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_valid_d1_cdc_to : std_logic := '0'; signal rxlength_valid_d2_cdc_from : std_logic := '0'; signal rxlength_valid_d3 : std_logic := '0'; signal rxlength_valid_d4 : std_logic := '0'; signal rxlength_valid_d1_back_cdc_to, rxlength_valid_d2_back : std_logic := '0'; ATTRIBUTE async_reg : STRING; --ATTRIBUTE async_reg OF rxlength_d1_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_d2 : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d1_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d1_back_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d2_back : SIGNAL IS "true"; begin -- Double register from secondary clock domain to primary S2P_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_rxlength_clr, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => rxlength_clr_d2, scndry_vect_out => open ); -- S2P_CLK_CROSS : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(p_reset_n = '0')then -- rxlength_clr_d1_cdc_tig <= '0'; -- rxlength_clr_d2 <= '0'; -- else -- rxlength_clr_d1_cdc_tig <= s2mm_rxlength_clr; -- rxlength_clr_d2 <= rxlength_clr_d1_cdc_tig; -- end if; -- end if; -- end process S2P_CLK_CROSS; -- Register receive length on assertion of last and valid -- Mark rxlength as valid for higher processes TRDY_RXLENGTH : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0' or rxlength_clr_d2 = '1')then rxlength_valid_trdy <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_valid_trdy <= '1'; end if; end if; end process TRDY_RXLENGTH; REG_RXLENGTH : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then rxlength_cdc_from <= (others => '0'); rxlength_valid_cdc_from <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0); rxlength_valid_cdc_from <= '1'; elsif (rxlength_valid_d2_back = '1') then rxlength_valid_cdc_from <= '0'; end if; end if; end process REG_RXLENGTH; SYNC_RXLENGTH : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => rxlength_valid_d2_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => rxlength_valid_d2_back, scndry_vect_out => open ); -- SYNC_RXLENGTH : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then -- -- rxlength_valid_d1_back_cdc_to <= '0'; -- rxlength_valid_d2_back <= '0'; -- else -- rxlength_valid_d1_back_cdc_to <= rxlength_valid_d2_cdc_from; -- rxlength_valid_d2_back <= rxlength_valid_d1_back_cdc_to; -- -- end if; -- end if; -- end process SYNC_RXLENGTH; -- Double register from primary clock domain to secondary P2S_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => rxlength_valid_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => rxlength_valid_d2_cdc_from, scndry_vect_out => open ); P2S_CLK_CROSS2 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_SG_LENGTH_WIDTH, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => rxlength_cdc_from, scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => rxlength_d2 ); P2S_CLK_CROSS1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0') then -- or s2mm_rxlength_clr = '1') then -- rxlength_d1_cdc_to <= (others => '0'); -- rxlength_d2 <= (others => '0'); -- rxlength_valid_d1_cdc_to <= '0'; -- rxlength_valid_d2_cdc_from <= '0'; rxlength_valid_d3 <= '0'; else -- rxlength_d1_cdc_to <= rxlength_cdc_from; -- rxlength_d2 <= rxlength_d1_cdc_to; -- rxlength_valid_d1_cdc_to <= rxlength_valid_cdc_from; -- rxlength_valid_d2_cdc_from <= rxlength_valid_d1_cdc_to; rxlength_valid_d3 <= rxlength_valid_d2_cdc_from; end if; end if; end process P2S_CLK_CROSS1; process (m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then rxlength_valid_d4 <= '0'; elsif (rxlength_valid_d3 = '1' and rxlength_valid_d2_cdc_from = '0') then rxlength_valid_d4 <= '1'; end if; end if; end process; s2mm_rxlength <= rxlength_d2; -- s2mm_rxlength_valid <= rxlength_valid_d2; s2mm_rxlength_valid <= rxlength_valid_d4; end generate GEN_STS_APP_LENGTH; -- Do NOT generate logic to capture receive length when option disabled GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); end generate GEN_NO_STS_APP_LENGTH; -- CR605883 -- Register stop to provide pure FF output for synchronizer REG_STOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_stop_reg <= '0'; else s2mm_stop_reg <= s2mm_stop; end if; end if; end process REG_STOP; -- double register s2mm error into primary clock domain REG_ERR2PRMRY : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_stop_reg, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => p_s2mm_stop_d2, scndry_vect_out => open ); REG_ERR2PRMRY1 : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then -- p_s2mm_stop_d1_cdc_tig <= '0'; -- p_s2mm_stop_d2 <= '0'; p_s2mm_stop_d3 <= '0'; else --p_s2mm_stop_d1_cdc_tig <= s2mm_stop; -- CR605883 -- p_s2mm_stop_d1_cdc_tig <= s2mm_stop_reg; -- p_s2mm_stop_d2 <= p_s2mm_stop_d1_cdc_tig; p_s2mm_stop_d3 <= p_s2mm_stop_d2; end if; end if; end process REG_ERR2PRMRY1; p_s2mm_stop_re <= p_s2mm_stop_d2 and not p_s2mm_stop_d3; skid_rst <= not p_reset_n; --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- STS_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ) port map( -- System Ports ACLK => axi_prmry_aclk , ARST => skid_rst , skid_stop => p_s2mm_stop_re , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_sts_tvalid , S_READY => s_axis_s2mm_sts_tready , S_Data => s_axis_s2mm_sts_tdata , S_STRB => s_axis_s2mm_sts_tkeep , S_Last => s_axis_s2mm_sts_tlast , -- Master Side (Stream Data Output M_VALID => sts_tvalid , M_READY => sts_tready , M_Data => sts_tdata , M_STRB => sts_tkeep , M_Last => sts_tlast ); end generate GEN_ASYNC_FIFO; end implementation;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sts_strm.vhd.vhd -- Description: This entity is the AXI Status Stream Interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_9; use axi_dma_v7_1_9.axi_dma_pkg.all; library lib_srl_fifo_v1_0_2; library lib_cdc_v1_0_2; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sts_strm is generic ( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32; -- Slave AXI Status Stream Data Width C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Descriptor Buffer Length, Transferred Bytes, and Status Stream -- Rx Length Width. Indicates the least significant valid bits of -- descriptor buffer length, transferred bytes, or Rx Length value -- in the status word coincident with tlast. C_ENABLE_SKID : integer range 0 to 1 := 0; C_FAMILY : string := "virtex5" -- Target FPGA Device Family ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- axi_prmry_aclk : in std_logic ; -- p_reset_n : in std_logic ; -- -- s2mm_stop : in std_logic ; -- -- s2mm_rxlength_valid : out std_logic ; -- s2mm_rxlength_clr : in std_logic ; -- s2mm_rxlength : out std_logic_vector -- (C_SG_LENGTH_WIDTH - 1 downto 0) ; -- -- stsstrm_fifo_rden : in std_logic ; -- stsstrm_fifo_empty : out std_logic ; -- stsstrm_fifo_dout : out std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); -- -- -- Stream to Memory Map Status Stream Interface -- s_axis_s2mm_sts_tdata : in std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- s_axis_s2mm_sts_tkeep : in std_logic_vector -- ((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); -- s_axis_s2mm_sts_tvalid : in std_logic ; -- s_axis_s2mm_sts_tready : out std_logic ; -- s_axis_s2mm_sts_tlast : in std_logic -- ); end axi_dma_s2mm_sts_strm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sts_strm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Status Stream FIFO Depth constant STSSTRM_FIFO_DEPTH : integer := 16; -- Status Stream FIFO Data Count Width (Unsused) constant STSSTRM_FIFO_CNT_WIDTH : integer := clog2(STSSTRM_FIFO_DEPTH+1); constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal fifo_full : std_logic := '0'; signal fifo_din : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); signal fifo_wren : std_logic := '0'; signal fifo_sinit : std_logic := '0'; signal rxlength_cdc_from : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_valid_cdc_from : std_logic := '0'; signal rxlength_valid_trdy : std_logic := '0'; --signal sts_tvalid_re : std_logic := '0';-- CR565502 --signal sts_tvalid_d1 : std_logic := '0';-- CR565502 signal sts_tvalid : std_logic := '0'; signal sts_tready : std_logic := '0'; signal sts_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal sts_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sts_tlast : std_logic := '0'; signal m_tvalid : std_logic := '0'; signal m_tready : std_logic := '0'; signal m_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal m_tlast : std_logic := '0'; signal tag_stripped : std_logic := '0'; signal mask_tag_write : std_logic := '0'; --signal mask_tag_hold : std_logic := '0';-- CR565502 signal skid_rst : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Primary Clock is synchronous to Secondary Clock therfore -- instantiate a sync fifo. GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate signal s2mm_stop_d1 : std_logic := '0'; signal s2mm_stop_re : std_logic := '0'; signal sts_rden : std_logic := '0'; signal follower_empty : std_logic := '0'; signal fifo_empty : std_logic := '0'; signal fifo_out : std_logic_vector (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); begin -- Generate Synchronous FIFO -- I_STSSTRM_FIFO : entity lib_srl_fifo_v1_0_2.sync_fifo_fg -- generic map ( -- C_FAMILY => C_FAMILY , -- C_MEMORY_TYPE => USE_LOGIC_FIFOS, -- C_WRITE_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, -- C_WRITE_DEPTH => STSSTRM_FIFO_DEPTH , -- C_READ_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, -- C_READ_DEPTH => STSSTRM_FIFO_DEPTH , -- C_PORTS_DIFFER => 0, -- C_HAS_DCOUNT => 1, --req for proper fifo operation -- C_DCOUNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH, -- C_HAS_ALMOST_FULL => 0, -- C_HAS_RD_ACK => 0, -- C_HAS_RD_ERR => 0, -- C_HAS_WR_ACK => 0, -- C_HAS_WR_ERR => 0, -- C_RD_ACK_LOW => 0, -- C_RD_ERR_LOW => 0, -- C_WR_ACK_LOW => 0, -- C_WR_ERR_LOW => 0, -- C_PRELOAD_REGS => 1,-- 1 = first word fall through -- C_PRELOAD_LATENCY => 0 -- 0 = first word fall through -- -- C_USE_EMBEDDED_REG => 1 -- 0 ; -- ) -- port map ( -- -- Clk => m_axi_sg_aclk , -- Sinit => fifo_sinit , -- Din => fifo_din , -- Wr_en => fifo_wren , -- Rd_en => stsstrm_fifo_rden , -- Dout => stsstrm_fifo_dout , -- Full => fifo_full , -- Empty => stsstrm_fifo_empty , -- Almost_full => open , -- Data_count => open , -- Rd_ack => open , -- Rd_err => open , -- Wr_ack => open , -- Wr_err => open -- -- ); I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f generic map ( C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, C_DEPTH => 16 , C_FAMILY => C_FAMILY ) port map ( Clk => m_axi_sg_aclk , Reset => fifo_sinit , FIFO_Write => fifo_wren , Data_In => fifo_din , FIFO_Read => sts_rden, --sts_queue_rden , Data_Out => fifo_out, --sts_queue_dout , FIFO_Empty => fifo_empty, --sts_queue_empty , FIFO_Full => fifo_full , Addr => open ); sts_rden <= (not fifo_empty) and follower_empty; stsstrm_fifo_empty <= follower_empty; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (fifo_sinit = '1' or stsstrm_fifo_rden = '1') then follower_empty <= '1'; elsif (sts_rden = '1') then follower_empty <= '0'; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (fifo_sinit = '1') then stsstrm_fifo_dout <= (others => '0'); elsif (sts_rden = '1') then stsstrm_fifo_dout <= fifo_out; end if; end if; end process; fifo_sinit <= not m_axi_sg_aresetn; fifo_din <= sts_tlast & sts_tdata; fifo_wren <= sts_tvalid and not fifo_full and not rxlength_valid_cdc_from and not mask_tag_write; sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_cdc_from; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- -- Create register delay of status tvalid in order to create a -- -- rising edge pulse. note xx_re signal will hold at 1 if -- -- fifo full on rising edge of tvalid. -- REG_TVALID : process(axi_prmry_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- sts_tvalid_d1 <= '0'; -- elsif(fifo_full = '0')then -- sts_tvalid_d1 <= sts_tvalid; -- end if; -- end if; -- end process REG_TVALID; -- -- -- rising edge on tvalid used to gate off status tag from being -- -- writen into fifo. -- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1; REG_TAG_STRIPPED : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tag_stripped <= '0'; -- Reset on write of last word elsif(fifo_wren = '1' and sts_tlast = '1')then tag_stripped <= '0'; -- Set on beginning of new status stream elsif(sts_tready = '1' and sts_tvalid = '1')then tag_stripped <= '1'; end if; end if; end process REG_TAG_STRIPPED; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- REG_MASK_TAG : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- mask_tag_hold <= '0'; -- elsif((sts_tvalid_re = '1' and tag_stripped = '0') -- or (fifo_wren = '1' and sts_tlast = '1'))then -- mask_tag_hold <= '1'; -- elsif(tag_stripped = '1')then -- mask_tag_hold <= '0'; -- end if; -- end if; -- end process; -- -- -- Mask TAG if not already masked and rising edge of tvalid -- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold); mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid; -- Generate logic to capture receive length when Use Receive Length is -- enabled GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate begin -- Register receive length on assertion of last and valid -- Mark rxlength as valid for higher processes REG_RXLENGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then rxlength_cdc_from <= (others => '0'); rxlength_valid_cdc_from <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0); rxlength_valid_cdc_from <= '1'; end if; end if; end process REG_RXLENGTH; s2mm_rxlength_valid <= rxlength_valid_cdc_from; s2mm_rxlength <= rxlength_cdc_from; end generate GEN_STS_APP_LENGTH; -- Do NOT generate logic to capture receive length when option disabled GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate begin s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); end generate GEN_NO_STS_APP_LENGTH; -- register stop to create re pulse REG_STOP : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then s2mm_stop_d1 <= '0'; else s2mm_stop_d1 <= s2mm_stop; end if; end if; end process REG_STOP; s2mm_stop_re <= s2mm_stop and not s2mm_stop_d1; skid_rst <= not m_axi_sg_aresetn; ENABLE_SKID : if C_ENABLE_SKID = 1 generate begin --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- STS_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ) port map( -- System Ports ACLK => m_axi_sg_aclk , ARST => skid_rst , skid_stop => s2mm_stop_re , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_sts_tvalid , S_READY => s_axis_s2mm_sts_tready , S_Data => s_axis_s2mm_sts_tdata , S_STRB => s_axis_s2mm_sts_tkeep , S_Last => s_axis_s2mm_sts_tlast , -- Master Side (Stream Data Output M_VALID => sts_tvalid , M_READY => sts_tready , M_Data => sts_tdata , M_STRB => sts_tkeep , M_Last => sts_tlast ); end generate ENABLE_SKID; DISABLE_SKID : if C_ENABLE_SKID = 0 generate begin sts_tvalid <= s_axis_s2mm_sts_tvalid; s_axis_s2mm_sts_tready <= sts_tready; sts_tdata <= s_axis_s2mm_sts_tdata; sts_tkeep <= s_axis_s2mm_sts_tkeep; sts_tlast <= s_axis_s2mm_sts_tlast; end generate DISABLE_SKID; end generate GEN_SYNC_FIFO; -- Primary Clock is asynchronous to Secondary Clock therfore -- instantiate an async fifo. GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate ATTRIBUTE async_reg : STRING; signal s2mm_stop_reg : std_logic := '0'; -- CR605883 signal p_s2mm_stop_d1_cdc_tig : std_logic := '0'; signal p_s2mm_stop_d2 : std_logic := '0'; signal p_s2mm_stop_d3 : std_logic := '0'; signal p_s2mm_stop_re : std_logic := '0'; --ATTRIBUTE async_reg OF p_s2mm_stop_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF p_s2mm_stop_d2 : SIGNAL IS "true"; begin -- Generate Asynchronous FIFO I_STSSTRM_FIFO : entity axi_dma_v7_1_9.axi_dma_afifo_autord generic map( C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1 , -- C_DEPTH => STSSTRM_FIFO_DEPTH , -- C_CNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH , C_DEPTH => 15 , C_CNT_WIDTH => 4 , C_USE_BLKMEM => USE_LOGIC_FIFOS , C_FAMILY => C_FAMILY ) port map( -- Inputs AFIFO_Ainit => fifo_sinit , AFIFO_Wr_clk => axi_prmry_aclk , AFIFO_Wr_en => fifo_wren , AFIFO_Din => fifo_din , AFIFO_Rd_clk => m_axi_sg_aclk , AFIFO_Rd_en => stsstrm_fifo_rden , AFIFO_Clr_Rd_Data_Valid => '0' , -- Outputs AFIFO_DValid => open , AFIFO_Dout => stsstrm_fifo_dout , AFIFO_Full => fifo_full , AFIFO_Empty => stsstrm_fifo_empty , AFIFO_Almost_full => open , AFIFO_Almost_empty => open , AFIFO_Wr_count => open , AFIFO_Rd_count => open , AFIFO_Corr_Rd_count => open , AFIFO_Corr_Rd_count_minus1 => open , AFIFO_Rd_ack => open ); fifo_sinit <= not p_reset_n; fifo_din <= sts_tlast & sts_tdata; fifo_wren <= sts_tvalid -- valid data and not fifo_full -- fifo has room and not rxlength_valid_trdy --rxlength_valid_cdc_from -- not holding a valid length and not mask_tag_write; -- not masking off tag word sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_trdy; --rxlength_valid_cdc_from; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- -- Create register delay of status tvalid in order to create a -- -- rising edge pulse. note xx_re signal will hold at 1 if -- -- fifo full on rising edge of tvalid. -- REG_TVALID : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- sts_tvalid_d1 <= '0'; -- elsif(fifo_full = '0')then -- sts_tvalid_d1 <= sts_tvalid; -- end if; -- end if; -- end process REG_TVALID; -- -- rising edge on tvalid used to gate off status tag from being -- -- writen into fifo. -- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1; REG_TAG_STRIPPED : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then tag_stripped <= '0'; -- Reset on write of last word elsif(fifo_wren = '1' and sts_tlast = '1')then tag_stripped <= '0'; -- Set on beginning of new status stream elsif(sts_tready = '1' and sts_tvalid = '1')then tag_stripped <= '1'; end if; end if; end process REG_TAG_STRIPPED; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- REG_MASK_TAG : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- mask_tag_hold <= '0'; -- elsif(tag_stripped = '1')then -- mask_tag_hold <= '0'; -- -- elsif(sts_tvalid_re = '1' -- or (fifo_wren = '1' and sts_tlast = '1'))then -- mask_tag_hold <= '1'; -- end if; -- end if; -- end process; -- -- -- Mask TAG if not already masked and rising edge of tvalid -- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold); mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid; -- Generate logic to capture receive length when Use Receive Length is -- enabled GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate signal rxlength_clr_d1_cdc_tig : std_logic := '0'; signal rxlength_clr_d2 : std_logic := '0'; signal rxlength_d1_cdc_to : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_d2 : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_valid_d1_cdc_to : std_logic := '0'; signal rxlength_valid_d2_cdc_from : std_logic := '0'; signal rxlength_valid_d3 : std_logic := '0'; signal rxlength_valid_d4 : std_logic := '0'; signal rxlength_valid_d1_back_cdc_to, rxlength_valid_d2_back : std_logic := '0'; ATTRIBUTE async_reg : STRING; --ATTRIBUTE async_reg OF rxlength_d1_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_d2 : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d1_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d1_back_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d2_back : SIGNAL IS "true"; begin -- Double register from secondary clock domain to primary S2P_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_rxlength_clr, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => rxlength_clr_d2, scndry_vect_out => open ); -- S2P_CLK_CROSS : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(p_reset_n = '0')then -- rxlength_clr_d1_cdc_tig <= '0'; -- rxlength_clr_d2 <= '0'; -- else -- rxlength_clr_d1_cdc_tig <= s2mm_rxlength_clr; -- rxlength_clr_d2 <= rxlength_clr_d1_cdc_tig; -- end if; -- end if; -- end process S2P_CLK_CROSS; -- Register receive length on assertion of last and valid -- Mark rxlength as valid for higher processes TRDY_RXLENGTH : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0' or rxlength_clr_d2 = '1')then rxlength_valid_trdy <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_valid_trdy <= '1'; end if; end if; end process TRDY_RXLENGTH; REG_RXLENGTH : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then rxlength_cdc_from <= (others => '0'); rxlength_valid_cdc_from <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0); rxlength_valid_cdc_from <= '1'; elsif (rxlength_valid_d2_back = '1') then rxlength_valid_cdc_from <= '0'; end if; end if; end process REG_RXLENGTH; SYNC_RXLENGTH : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => rxlength_valid_d2_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => rxlength_valid_d2_back, scndry_vect_out => open ); -- SYNC_RXLENGTH : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then -- -- rxlength_valid_d1_back_cdc_to <= '0'; -- rxlength_valid_d2_back <= '0'; -- else -- rxlength_valid_d1_back_cdc_to <= rxlength_valid_d2_cdc_from; -- rxlength_valid_d2_back <= rxlength_valid_d1_back_cdc_to; -- -- end if; -- end if; -- end process SYNC_RXLENGTH; -- Double register from primary clock domain to secondary P2S_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => rxlength_valid_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => rxlength_valid_d2_cdc_from, scndry_vect_out => open ); P2S_CLK_CROSS2 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_SG_LENGTH_WIDTH, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => rxlength_cdc_from, scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => rxlength_d2 ); P2S_CLK_CROSS1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0') then -- or s2mm_rxlength_clr = '1') then -- rxlength_d1_cdc_to <= (others => '0'); -- rxlength_d2 <= (others => '0'); -- rxlength_valid_d1_cdc_to <= '0'; -- rxlength_valid_d2_cdc_from <= '0'; rxlength_valid_d3 <= '0'; else -- rxlength_d1_cdc_to <= rxlength_cdc_from; -- rxlength_d2 <= rxlength_d1_cdc_to; -- rxlength_valid_d1_cdc_to <= rxlength_valid_cdc_from; -- rxlength_valid_d2_cdc_from <= rxlength_valid_d1_cdc_to; rxlength_valid_d3 <= rxlength_valid_d2_cdc_from; end if; end if; end process P2S_CLK_CROSS1; process (m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then rxlength_valid_d4 <= '0'; elsif (rxlength_valid_d3 = '1' and rxlength_valid_d2_cdc_from = '0') then rxlength_valid_d4 <= '1'; end if; end if; end process; s2mm_rxlength <= rxlength_d2; -- s2mm_rxlength_valid <= rxlength_valid_d2; s2mm_rxlength_valid <= rxlength_valid_d4; end generate GEN_STS_APP_LENGTH; -- Do NOT generate logic to capture receive length when option disabled GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); end generate GEN_NO_STS_APP_LENGTH; -- CR605883 -- Register stop to provide pure FF output for synchronizer REG_STOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_stop_reg <= '0'; else s2mm_stop_reg <= s2mm_stop; end if; end if; end process REG_STOP; -- double register s2mm error into primary clock domain REG_ERR2PRMRY : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_stop_reg, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => p_s2mm_stop_d2, scndry_vect_out => open ); REG_ERR2PRMRY1 : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then -- p_s2mm_stop_d1_cdc_tig <= '0'; -- p_s2mm_stop_d2 <= '0'; p_s2mm_stop_d3 <= '0'; else --p_s2mm_stop_d1_cdc_tig <= s2mm_stop; -- CR605883 -- p_s2mm_stop_d1_cdc_tig <= s2mm_stop_reg; -- p_s2mm_stop_d2 <= p_s2mm_stop_d1_cdc_tig; p_s2mm_stop_d3 <= p_s2mm_stop_d2; end if; end if; end process REG_ERR2PRMRY1; p_s2mm_stop_re <= p_s2mm_stop_d2 and not p_s2mm_stop_d3; skid_rst <= not p_reset_n; --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- STS_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ) port map( -- System Ports ACLK => axi_prmry_aclk , ARST => skid_rst , skid_stop => p_s2mm_stop_re , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_sts_tvalid , S_READY => s_axis_s2mm_sts_tready , S_Data => s_axis_s2mm_sts_tdata , S_STRB => s_axis_s2mm_sts_tkeep , S_Last => s_axis_s2mm_sts_tlast , -- Master Side (Stream Data Output M_VALID => sts_tvalid , M_READY => sts_tready , M_Data => sts_tdata , M_STRB => sts_tkeep , M_Last => sts_tlast ); end generate GEN_ASYNC_FIFO; end implementation;
--***************************************************************************** -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 3.92 -- \ \ Application : MIG -- / / Filename : rank_common.vhd -- /___/ /\ Date Last Modified : $date$ -- \ \ / \ Date Created : Wed Jun 17 2009 -- \___\/\___\ -- --Device : Virtex-6 --Design Name : DDR3 SDRAM --Purpose : --Reference : --Revision History : --***************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --use ieee.std_logic_arith.all; use ieee.numeric_std.all; -- Block for logic common to all rank machines. Contains -- a clock prescaler, and arbiters for refresh and periodic -- read functions. entity rank_common is generic ( TCQ : integer := 100; DRAM_TYPE : string := "DDR3"; MAINT_PRESCALER_DIV : integer := 40; nBANK_MACHS : integer := 4; RANK_WIDTH : integer := 2; RANKS : integer := 4; REFRESH_TIMER_DIV : integer := 39; ZQ_TIMER_DIV : integer := 640000 ); port ( -- Outputs -- Inputs -- ceiling logb2 -- Maintenance and periodic read prescaler. Nominally 200 nS. --clogb2(MAINT_PRESCALER_DIV + 1); maint_prescaler_tick_r : out std_logic; -- Refresh timebase. Nominically 7800 nS. refresh_tick : out std_logic; -- block: maintenance_request maint_zq_r : out std_logic; maint_req_r : out std_logic; maint_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0); -- Periodic reads to maintain PHY alignment. -- Demand insertion of periodic read as soon as -- possible. Since the is a single rank, bank compare mechanism -- must be used, periodic reads must be forced in at the -- expense of not accepting a normal request. clear_periodic_rd_request : out std_logic_vector(RANKS - 1 downto 0); -- Maintenance request pipeline. -- Arbitrate periodic read requests. -- Inputs -- Encode and set periodic read rank into periodic_rd_rank_r. -- Once the request is dropped in the queue, it might be a while before it -- emerges. Can't clear the request based on seeing the read issued. -- Need to clear the request as soon as its made it into the queue. -- block: maintenance_request periodic_rd_r : out std_logic; periodic_rd_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0); clk : in std_logic; rst : in std_logic; dfi_init_complete : in std_logic; app_zq_req : in std_logic; insert_maint_r1 : in std_logic; refresh_request : in std_logic_vector(RANKS - 1 downto 0); maint_wip_r : in std_logic; slot_0_present : in std_logic_vector(7 downto 0); slot_1_present : in std_logic_vector(7 downto 0); periodic_rd_request : in std_logic_vector(RANKS - 1 downto 0); periodic_rd_ack_r : in std_logic ); end entity rank_common; architecture trans of rank_common is component round_robin_arb generic ( TCQ : integer := 100; WIDTH : integer := 3 ); port ( grant_ns : out std_logic_vector(WIDTH - 1 downto 0); grant_r : out std_logic_vector(WIDTH - 1 downto 0); clk : in std_logic; rst : in std_logic; req : in std_logic_vector(WIDTH - 1 downto 0); disable_grant : in std_logic; current_master : in std_logic_vector(WIDTH - 1 downto 0); upd_last_master : in std_logic ); end component; function nCOPY (A : in std_logic; B : in integer) return std_logic_vector is variable tmp : std_logic_vector(B - 1 downto 0); begin for i in 0 to B - 1 loop tmp(i) := A; end loop; return tmp; end function nCOPY; function clogb2(size: integer) return integer is variable tmp : integer := 1; variable tmp_size : std_logic_vector (31 downto 0); begin tmp_size := std_logic_vector(TO_UNSIGNED((size - 1),32)); while ( to_integer(UNSIGNED(tmp_size)) > 1 ) loop tmp_size := std_logic_vector(UNSIGNED(tmp_size) srl 1); tmp := tmp + 1; end loop; return tmp; --for i in 23 downto 0 loop -- if( size <= 2** i) then -- tmp := i; -- end if; --end loop; --return tmp; end function clogb2; function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is begin if A = true then return '1'; else return '0'; end if; end function BOOLEAN_TO_STD_LOGIC; function REDUCTION_OR( A: in std_logic_vector) return std_logic is variable tmp : std_logic := '0'; begin for i in A'range loop tmp := tmp or A(i); end loop; return tmp; end function REDUCTION_OR; constant ONE : integer := 1; constant MAINT_PRESCALER_WIDTH : integer := clogb2(MAINT_PRESCALER_DIV + 1); constant REFRESH_TIMER_WIDTH : integer := clogb2(REFRESH_TIMER_DIV + 1); constant ZQ_TIMER_WIDTH : integer := clogb2(ZQ_TIMER_DIV + 1); signal maint_prescaler_tick_r_lcl : std_logic; signal refresh_tick_lcl : std_logic; signal maint_zq_r_lcl : std_logic; signal zq_request : std_logic := '0'; signal maint_req_r_lcl : std_logic; signal maint_rank_r_lcl : std_logic_vector(RANK_WIDTH - 1 downto 0); signal periodic_rd_r_lcl : std_logic; signal periodic_rd_rank_r_lcl : std_logic_vector(RANK_WIDTH - 1 downto 0); signal periodic_rd_rank_ns : std_logic_vector(RANK_WIDTH - 1 downto 0); signal periodic_rd_grant_r : std_logic_vector(RANKS - 1 downto 0); signal periodic_rd_grant_ns : std_logic_vector(RANKS - 1 downto 0); signal maint_grant_ns : std_logic_vector(RANKS downto 0); signal maint_grant_r : std_logic_vector(RANKS downto 0); signal maint_rank_ns : std_logic_vector(RANK_WIDTH - 1 downto 0); signal periodic_rd_busy : std_logic; signal maint_zq_ns : std_logic; signal upd_last_master_ns : std_logic; signal upd_last_master_r : std_logic; signal new_maint_rank_r : std_logic; signal zq_timer_r : std_logic_vector(ZQ_TIMER_WIDTH - 1 downto 0); signal zq_timer_ns : std_logic_vector(ZQ_TIMER_WIDTH - 1 downto 0); signal refresh_timer_r : std_logic_vector(REFRESH_TIMER_WIDTH - 1 downto 0); signal refresh_timer_ns : std_logic_vector(REFRESH_TIMER_WIDTH - 1 downto 0); signal periodic_upd_last_master_ns : std_logic; -- local signal in verilog code within periodic request signal periodic_upd_last_master_r : std_logic; signal maint_request : std_logic_vector(RANKS downto 0); signal maint_busy : std_logic; signal maint_prescaler_r : std_logic_vector(MAINT_PRESCALER_WIDTH-1 downto 0); signal maint_prescaler_ns : std_logic_vector(MAINT_PRESCALER_WIDTH-1 downto 0); signal maint_prescaler_tick_ns : std_logic; signal zq_request_r : std_logic; signal zq_request_ns : std_logic; signal zq_tick : std_logic := '0'; signal zq_clears_zq_request : std_logic; signal present : std_logic_vector(7 downto 0); signal periodic_rd_ns : std_logic; signal int2 : std_logic; signal int3 : std_logic_vector(RANKS - 1 downto 0); signal tst_rdor_rd_request : std_logic; begin maint_prescaler_tick_ns <= BOOLEAN_TO_STD_LOGIC(maint_prescaler_r = std_logic_vector(TO_UNSIGNED(1,MAINT_PRESCALER_WIDTH))); process (dfi_init_complete, maint_prescaler_r, maint_prescaler_tick_ns) begin maint_prescaler_ns <= maint_prescaler_r; if ((not(dfi_init_complete) or maint_prescaler_tick_ns) = '1') then maint_prescaler_ns <= std_logic_vector(TO_UNSIGNED(MAINT_PRESCALER_DIV,MAINT_PRESCALER_WIDTH)); elsif ((REDUCTION_OR(maint_prescaler_r)) = '1') then maint_prescaler_ns <= maint_prescaler_r - std_logic_vector(TO_UNSIGNED(1,MAINT_PRESCALER_WIDTH)); end if; end process; process (clk) begin if (clk'event and clk = '1') then maint_prescaler_r <= maint_prescaler_ns after (TCQ)*1 ps; end if; end process; process (clk) begin if (clk'event and clk = '1') then maint_prescaler_tick_r_lcl <= maint_prescaler_tick_ns after (TCQ)*1 ps; end if; end process; maint_prescaler_tick_r <= maint_prescaler_tick_r_lcl; process (dfi_init_complete, maint_prescaler_tick_r_lcl, refresh_tick_lcl, refresh_timer_r) begin refresh_timer_ns <= refresh_timer_r; if ((not(dfi_init_complete) or refresh_tick_lcl) = '1') then refresh_timer_ns <= std_logic_vector(TO_UNSIGNED(REFRESH_TIMER_DIV,REFRESH_TIMER_WIDTH )); elsif ((REDUCTION_OR(refresh_timer_r) and maint_prescaler_tick_r_lcl) = '1') then refresh_timer_ns <= refresh_timer_r - std_logic_vector(TO_UNSIGNED(1,REFRESH_TIMER_WIDTH)); end if; end process; process (clk) begin if (clk'event and clk = '1') then refresh_timer_r <= refresh_timer_ns after (TCQ)*1 ps; end if; end process; refresh_tick_lcl <= BOOLEAN_TO_STD_LOGIC(refresh_timer_r = std_logic_vector(TO_UNSIGNED(1,REFRESH_TIMER_WIDTH ))) and maint_prescaler_tick_r_lcl; refresh_tick <= refresh_tick_lcl; int0 : if (DRAM_TYPE = "DDR3") generate int1 : if (ZQ_TIMER_DIV /= 0) generate process (dfi_init_complete, maint_prescaler_tick_r_lcl, zq_tick, zq_timer_r) variable zq_timer_ns_tmp : std_logic_vector(ZQ_TIMER_WIDTH - 1 downto 0); begin zq_timer_ns_tmp := zq_timer_r; if ((not(dfi_init_complete) or zq_tick) = '1') then zq_timer_ns_tmp := std_logic_vector(TO_UNSIGNED(ZQ_TIMER_DIV,ZQ_TIMER_WIDTH )); elsif ((REDUCTION_OR(zq_timer_r) and maint_prescaler_tick_r_lcl) = '1') then zq_timer_ns_tmp := zq_timer_r - std_logic_vector(TO_UNSIGNED(1,ZQ_TIMER_WIDTH )); end if; zq_timer_ns <= zq_timer_ns_tmp ; end process; process (clk) begin if (clk'event and clk = '1') then zq_timer_r <= zq_timer_ns after (TCQ)*1 ps; end if; end process; process (maint_prescaler_tick_r_lcl, zq_timer_r) begin zq_tick <= (BOOLEAN_TO_STD_LOGIC(zq_timer_r = std_logic_vector(TO_UNSIGNED(1,ZQ_TIMER_WIDTH ))) and maint_prescaler_tick_r_lcl); end process; end generate; zq_clears_zq_request <= insert_maint_r1 and maint_zq_r_lcl; zq_request_ns <= not(rst) and BOOLEAN_TO_STD_LOGIC(DRAM_TYPE = "DDR3") and ((not(dfi_init_complete) and BOOLEAN_TO_STD_LOGIC(ZQ_TIMER_DIV /= 0)) or (zq_request_r and not(zq_clears_zq_request)) or zq_tick or (app_zq_req and dfi_init_complete)); process (clk) begin if (clk'event and clk = '1') then zq_request_r <= zq_request_ns after (TCQ)*1 ps; end if; end process; process (dfi_init_complete, zq_request_r) begin zq_request <= dfi_init_complete and zq_request_r; end process; end generate; -- Maintenance_request maint_busy <= upd_last_master_r or new_maint_rank_r or maint_req_r_lcl or maint_wip_r; maint_request <= (zq_request & refresh_request(RANKS - 1 downto 0)); upd_last_master_ns <= REDUCTION_OR(maint_request) and not(maint_busy); process (clk) begin if (clk'event and clk = '1') then upd_last_master_r <= upd_last_master_ns after (TCQ)*1 ps; end if; end process; process (clk) begin if (clk'event and clk = '1') then new_maint_rank_r <= upd_last_master_r after (TCQ)*1 ps; end if; end process; process (clk) begin if (clk'event and clk = '1') then maint_req_r_lcl <= new_maint_rank_r after (TCQ)*1 ps; end if; end process; maint_arb0 : round_robin_arb generic map ( WIDTH => (RANKS + 1) ) port map ( grant_ns => maint_grant_ns, grant_r => maint_grant_r, upd_last_master => upd_last_master_r, current_master => maint_grant_r, req => maint_request, disable_grant => '0', clk => clk, rst => rst ); present <= slot_0_present or slot_1_present; maint_zq_ns <= not(rst) and maint_grant_r(RANKS) when (upd_last_master_r = '1') else not(rst) and maint_zq_r_lcl; process (maint_grant_r, maint_rank_r_lcl, maint_zq_ns, present, rst, upd_last_master_r) variable maint_rank_ns_tmp : std_logic_vector(RANK_WIDTH-1 downto 0); begin if (rst = '1') then maint_rank_ns_tmp := (others => '0' ); else maint_rank_ns_tmp := maint_rank_r_lcl; if (maint_zq_ns = '1') then maint_rank_ns_tmp := maint_rank_r_lcl + std_logic_vector(TO_UNSIGNED(1,RANK_WIDTH )); for i in 0 to 7 loop if ((not(present(to_integer(UNSIGNED(maint_rank_ns_tmp))))) = '1') then maint_rank_ns_tmp := maint_rank_ns_tmp + std_logic_vector(TO_UNSIGNED(1,RANK_WIDTH)); end if; end loop; elsif (upd_last_master_r = '1') then for i in 0 to RANKS - 1 loop if ((maint_grant_r(i)) = '1') then maint_rank_ns_tmp := std_logic_vector(TO_UNSIGNED(i,RANK_WIDTH )); end if; end loop; end if; end if; maint_rank_ns <= maint_rank_ns_tmp; end process; process (clk) begin if (clk'event and clk = '1') then maint_rank_r_lcl <= maint_rank_ns after (TCQ)*1 ps; end if; end process; process (clk) begin if (clk'event and clk = '1') then maint_zq_r_lcl <= maint_zq_ns after (TCQ)*1 ps; end if; end process; maint_zq_r <= maint_zq_r_lcl; maint_req_r <= maint_req_r_lcl; maint_rank_r <= maint_rank_r_lcl; -- generate : periodic_read_request periodic_rd_busy <= periodic_upd_last_master_r or periodic_rd_r_lcl; --upd_last_master_ns <= dfi_init_complete and (REDUCTION_OR(periodic_rd_request) and not(periodic_rd_busy)); periodic_upd_last_master_ns <= dfi_init_complete and (REDUCTION_OR(periodic_rd_request) and not(periodic_rd_busy)); process (clk) begin if (clk'event and clk = '1') then periodic_upd_last_master_r <= periodic_upd_last_master_ns after (TCQ)*1 ps; end if; end process; periodic_rd_ns <= dfi_init_complete and (periodic_upd_last_master_r or (periodic_rd_r_lcl and not(periodic_rd_ack_r))); process (clk) begin if (clk'event and clk = '1') then periodic_rd_r_lcl <= periodic_rd_ns after (TCQ)*1 ps; end if; end process; periodic_rd_arb0 : round_robin_arb generic map ( WIDTH => RANKS ) port map ( grant_ns => periodic_rd_grant_ns(RANKS - 1 downto 0), grant_r => open, upd_last_master => periodic_upd_last_master_r,--upd_last_master_r, current_master => periodic_rd_grant_r(RANKS - 1 downto 0), req => periodic_rd_request(RANKS - 1 downto 0), disable_grant => '0', clk => clk, rst => rst ); int3 <= periodic_rd_grant_ns when (periodic_upd_last_master_ns = '1') else periodic_rd_grant_r; process (clk) begin if (clk'event and clk = '1') then periodic_rd_grant_r <= int3; end if; end process; process (periodic_rd_grant_r, periodic_rd_rank_r_lcl, periodic_upd_last_master_r) begin periodic_rd_rank_ns <= periodic_rd_rank_r_lcl; if (periodic_upd_last_master_r = '1') then for i in 0 to RANKS - 1 loop if ((periodic_rd_grant_r(i)) = '1') then periodic_rd_rank_ns <= std_logic_vector(TO_UNSIGNED(i,RANK_WIDTH )); end if; end loop; end if; end process; process (clk) begin if (clk'event and clk = '1') then periodic_rd_rank_r_lcl <= periodic_rd_rank_ns after (TCQ)*1 ps; end if; end process; clear_periodic_rd_request <= periodic_rd_grant_r and nCOPY(periodic_rd_ack_r,RANKS); periodic_rd_r <= periodic_rd_r_lcl; periodic_rd_rank_r <= periodic_rd_rank_r_lcl; end architecture trans;
--============================================================================ --! --! \file <FILE_NAME> --! --! \project <PROJECT_NAME> --! --! \langv VHDL-1987 --! --! \brief <BRIEF_DESCRIPTION>. --! --! \details <DETAILED_DESCRIPTION>. --! --! \bug <BUGS_OR_KNOWN_ISSUES>. --! --! \see <REFERENCES> --! --! \copyright <COPYRIGHT_OR_LICENSE> --! --! Revision history: --! --! \version <VERSION> --! \date <YYYY-MM-DD> --! \author <AUTHOR_NAME> --! \brief Create file. --! --============================================================================ library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; package template_module_package is component template_module generic ( my_generic : integer := 0 ); port ( my_port : std_logic ); end component; end; library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity template_module is generic ( my_generic : integer := 0 ); port ( my_port : std_logic ); begin end template_module; library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; architecture rtl of template_module is begin end rtl;
-- ********************************************************************/ -- Actel Corporation Proprietary and Confidential -- Copyright 2008 Actel Corporation. All rights reserved. -- -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED -- IN ADVANCE IN WRITING. -- -- Description: PRINTF SUPPORT for cores using std_logic_arith or std_logic_unsigned -- -- -- Revision Information: -- Date Description -- 01Sep07 Initial Release -- 14Sep07 Updated for 1.2 functionality -- 25Sep07 Updated for 1.3 functionality -- 09Nov07 Updated for 1.4 functionality -- 08May08 2.0 for Soft IP Usage -- 22Oct08 3.0 Moved into SVN Properly (TEXTIO Project) -- -- -- SVN Revision Information: -- SVN $Revision: 3758 $ -- SVN $Date: 2008-10-22 01:56:45 -0700 (Wed, 22 Oct 2008) $ -- -- -- Resolved SARs -- SAR Date Who Description -- -- -- Notes: -- -- *********************************************************************/ -- Notes : -- Supported Formats -- %d decimal -- %h hexadecimal Integer or known vector -- %x hexadecimal Integer or vector with X's -- %b binary -- %s string -- %t prints time in ns -- -- Also Supports %6 i.e Width Field -- %0 Fill with Zeros -- --------------------------------------------------------------------------- library std; use std.textio.all; use work.misc.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --------------------------------------------------------------------------- -- Declarations etc -- package textio is -- synthesis translate_off constant MAXSTRLEN : INTEGER := 256; type T_NUMTYPE is ( NONE, INT, VECT, STRG); type T_FMT is record f_type : T_NUMTYPE; f_integer : INTEGER; f_vector : QWORD; f_length : INTEGER; f_string : STRING (1 to MAXSTRLEN); end record; type T_FMT_ARRAY is array ( integer range <> ) of T_FMT; function is01 ( v: std_logic) return BOOLEAN; function is01 ( v: STD_LOGIC_VECTOR; len : INTEGER) return BOOLEAN; function strlen( str: STRING) return INTEGER; function strcopy ( instr : STRING) return STRING; procedure printf( str : STRING; params : T_FMT_ARRAY); procedure printf( str : STRING; params : T_FMT); procedure printf( str : STRING ); procedure sprintf( strout : out STRING; str : STRING; params : T_FMT_ARRAY); procedure sprintf( strout : out STRING; str : STRING; params : T_FMT); procedure sprintf( strout : out STRING; str : STRING ); procedure ifprintf( enable : BOOLEAN; str : STRING; params : T_FMT_ARRAY); procedure ifprintf( enable : BOOLEAN; str : STRING; params : T_FMT); procedure ifprintf( enable : BOOLEAN; str : STRING ); function fmt ( x : INTEGER) return T_FMT; function fmt ( x : STD_LOGIC_VECTOR) return T_FMT; function fmt ( x : string ) return T_FMT; function fmt ( x : character ) return T_FMT; function fmt ( x : boolean ) return T_FMT; function fmt ( x : std_logic) return T_FMT; function inttostr( value : INTEGER; base : INTEGER; numlen : INTEGER :=0; zeros: BOOLEAN:=FALSE) return STRING; function inrange ( x, l: integer) return integer; -- synthesis translate_on end textio; -- synthesis translate_off --------------------------------------------------------------------------- -- The Body -- package body textio is function inrange ( x, l: integer) return integer is begin if x<=l then return(x); else return(l); end if; end inrange; --------------------------------------------------------------------------- -- Basic Character Converters -- function to_char( x : INTEGER range 0 to 15) return character is begin case x is when 0 => return('0'); when 1 => return('1'); when 2 => return('2'); when 3 => return('3'); when 4 => return('4'); when 5 => return('5'); when 6 => return('6'); when 7 => return('7'); when 8 => return('8'); when 9 => return('9'); when 10 => return('A'); when 11 => return('B'); when 12 => return('C'); when 13 => return('D'); when 14 => return('E'); when 15 => return('F'); end case; end to_char; function to_char( v : std_logic ) return CHARACTER is begin case v is when '0' => return('0'); when '1' => return('1'); when 'L' => return('L'); when 'H' => return('H'); when 'Z' => return('Z'); when 'X' => return('X'); when 'U' => return('U'); when '-' => return('-'); when 'W' => return('W'); end case; end to_char; --------------------------------------------------------------------------- -- special std_logic_vector handling -- function is01 ( v: std_logic) return BOOLEAN is begin return ( v='0' or v='1'); end is01; function is01 ( v: STD_LOGIC_VECTOR ; len : INTEGER) return BOOLEAN is variable ok : BOOLEAN; begin ok := TRUE; for i in 0 to len-1 loop ok := ok and is01( v(i)); end loop; return (ok); end is01; --------------------------------------------------------------------------- -- String Functions -- function strlen( str: STRING) return INTEGER is variable i: INTEGER; begin i:=1; while i<= MAXSTRLEN and str(i)/=NUL loop i:=i+1; end loop; return(i-1); end strlen; function strcopy ( instr : STRING) return STRING is variable outstr : STRING (1 to MAXSTRLEN); variable i: INTEGER; begin outstr(1 to instr'length) := instr; outstr(instr'length+1) := NUL; return(outstr); end strcopy; --------------------------------------------------------------------------- -- Number Printing Routines -- function hexchar ( vect : STD_LOGIC_VECTOR) return character is variable v : STD_LOGIC_VECTOR ( 3 downto 0); variable char : CHARACTER; begin v := vect; if is01(v(0)) and is01(v(1)) and is01(v(2)) and is01(v(3)) then char := to_char (to_integer(v)); elsif v(0)=v(1) and v(0)=v(2) and v(0)=v(3) then char:= to_char(v(0)); else char:='?'; end if; return(char); end hexchar; function inttostr( value : INTEGER; base : INTEGER; numlen : INTEGER :=0; zeros: BOOLEAN:=FALSE) return STRING is variable str : STRING (1 to MAXSTRLEN); variable s1 : STRING (MAXSTRLEN downto 1); variable pos,x,xn,x1 : INTEGER; begin if value=-2147483648 then case base is when 2 => str(1 to 33) := ( 1=> '1', 33 => NUL, others => '0'); when 10 => str(1 to 12) := "-2147483648" & NUL; when 16 => str(1 to 9) := "80000000" & NUL; when others => str ( 1 to 12) := "MAXNEGVALUE" & NUL; end case; else x := abs(value); pos := 0; while x>0 or pos=0 loop pos:=pos+1; xn := x / base; x1 := x - xn * base ; x := xn; s1(pos) := to_char(x1); end loop; if value<0 then pos:=pos+1; s1(pos):='-'; end if; if pos>numlen then str(1 to pos) := s1 (pos downto 1); str(pos+1) := NUL; else str := (others => ' '); if ZEROS and base/=10 then str := (others => '0'); end if; str( (1+numlen-pos) to numlen) := s1(pos downto 1); str(numlen+1) := NUL; end if; end if; return(str); end inttostr; function vecttostr( value : STD_LOGIC_VECTOR; len : INTEGER; base : INTEGER; numlen : INTEGER :=0; zeros: BOOLEAN:=FALSE) return STRING is variable str : STRING (1 to MAXSTRLEN); variable s1 : STRING (MAXSTRLEN downto 1); variable pos, len4 : INTEGER; variable x : QWORD; variable vect4 : std_logic_vector(3 downto 0); begin x:=value; if len<64 then x(63 downto len) := (others =>'0'); end if; case base is when 2 => for i in 0 to len-1 loop s1(i+1) := to_char(value(i)); end loop; pos:=len; when 16 => len4 := ((len+3)/4); for i in 0 to len4-1 loop vect4 := x( 3+(4*i) downto 4*i); s1(i+1) := hexchar(vect4); end loop; pos:=len4; when others => s1:=strcopy("ESAB LAGELLI"); end case; if pos>numlen then str(1 to pos) := s1 (pos downto 1); str(pos+1) := NUL; else case ZEROS is when TRUE => str := (others => '0'); when FALSE => str := (others => ' '); end case; str( (1+numlen-pos) to numlen) := s1(pos downto 1); str(numlen+1) := NUL; end if; return(str); end vecttostr; --------------------------------------------------------------------------- -- Multi Type input handlers -- function fmt ( x : BOOLEAN) return T_FMT is variable fm : T_FMT; begin fm.f_type := INT; if x then fm.f_integer := 1; else fm.f_integer := 0; end if; return(fm); end fmt; function fmt ( x : INTEGER) return T_FMT is variable fm : T_FMT; begin fm.f_type := INT; fm.f_integer := x; return(fm); end fmt; function fmt ( x : STD_LOGIC_VECTOR) return T_FMT is variable fm : T_FMT; begin fm.f_type := VECT; fm.f_vector(x'length-1 downto 0) := x; fm.f_length := x'length; return(fm); end fmt; function fmt ( x : string ) return T_FMT is variable fm : T_FMT; begin fm.f_type := STRG; fm.f_string(x'range) := x; if x'length+1<MAXSTRLEN then fm.f_string(x'length+1) := NUL; end if; fm.f_length := x'length; return(fm); end fmt; function fmt ( x : character ) return T_FMT is variable fm : T_FMT; begin fm.f_type := STRG; fm.f_string(1) := x; fm.f_string(2) := NUL; fm.f_length := 1; return(fm); end fmt; function fmt ( x : std_logic) return T_FMT is variable fm : T_FMT; variable x1 : STD_LOGIC_VECTOR ( 0 downto 0); begin x1(0) := x; fm.f_type := VECT; fm.f_vector(x1'length-1 downto 0) := x1; fm.f_length := x1'length; return(fm); end fmt; --------------------------------------------------------------------------- -- The Main Print Routine -- procedure theprintf( SPRINTF : BOOLEAN; strout : out string; str : STRING; Params : T_FMT_ARRAY ) is variable ll : LINE; variable str1,pstr : STRING (1 to MAXSTRLEN); variable ip,op,pp,iplen : INTEGER; variable numlen : INTEGER; variable zeros : BOOLEAN; variable more : BOOLEAN; variable intval : INTEGER; variable vectval: QWORD; variable len : INTEGER; variable ftype : T_NUMTYPE; variable tnow : INTEGER; begin iplen := str'length; ip:=1; op:=0; pp:=params'low; while ip<=iplen and str( inrange(ip,iplen))/=NUL loop if str(ip) = '%' then more:=TRUE; numlen:=0; zeros:=FALSE; while more loop more:=FALSE; ip:=ip+1; ftype := params(pp).f_type; intval := params(pp).f_integer; vectval:= params(pp).f_vector; len := params(pp).f_length; case str(ip) is when '0' => ZEROS:=TRUE; more:=TRUE; when '1' to '9' => numlen:= 10* numlen + character'pos(str(ip))-48; more := TRUE; when '%' => pstr := strcopy("%"); when 'd' => case ftype is when INT => pstr := inttostr(intval,10,numlen,zeros); when VECT => if is01(vectval,len) then intval:= to_integer(vectval(len-1 downto 0)); pstr := inttostr(intval,10,numlen,zeros); else pstr := strcopy("UNKNOWN" ); end if; when others => pstr := strcopy("INVALID PRINTF d:" & str); end case; pp:=pp+1; when 't' => tnow := NOW / 1 ns; pstr := inttostr(tnow,10,numlen,zeros); when 'h' => case ftype is when INT => vectval(31 downto 0) := conv_STD_LOGIC_VECTOR(intval,32); len := 32; pstr := vecttostr(vectval,len,16,numlen,zeros); when VECT => pstr := vecttostr(vectval,len,16,numlen,zeros); when others => pstr := strcopy("INVALID PRINTF h:" & str); end case; pp:=pp+1; when 'u' => case ftype is when INT => vectval(31 downto 0) := conv_STD_LOGIC_VECTOR(intval,32); len := 32; pstr := vecttostr(vectval,len,16,numlen,zeros); when VECT => pstr := vecttostr(vectval,len,16,numlen,zeros); when others => pstr := strcopy("INVALID PRINTF h:" & str); end case; pp:=pp+1; when 'b' => case ftype is when INT => vectval := ( others => '0'); vectval(31 downto 0) := conv_STD_LOGIC_VECTOR(intval,32); len:=1; for i in 1 to 31 loop if vectval(i)='1' then len:=i+1; -- Fix 3Oct06 CoreABC end if; end loop; pstr := vecttostr(vectval,len,2,numlen,zeros); when VECT => pstr := vecttostr(vectval,len,2,numlen,zeros); when others => pstr := strcopy("INVALID PRINTF b:" & str); end case; pp:=pp+1; when 'x' => case ftype is when INT => vectval(31 downto 0) := conv_STD_LOGIC_VECTOR(intval,32); len := 32; pstr := vecttostr(vectval,len,16,numlen,zeros); when VECT => pstr := vecttostr(vectval,len,16,numlen,zeros); when others => pstr := strcopy("INVALID PRINTF x:" & str); end case; pp:=pp+1; when 's' => case ftype is when STRG => pstr:=params(pp).f_string; when others => pstr := strcopy("INVALID PRINTF s:" & str); end case; pp:=pp+1; when 'c' => case ftype is when STRG => pstr:=params(pp).f_string; when others => pstr := strcopy("INVALID PRINTF s:" & str); end case; pp:=pp+1; when others => pstr := strcopy("ILLEGAL FORMAT"); assert FALSE report "TEXTIO Processing Problem" severity FAILURE; end case; end loop; len := strlen(pstr); for i in 1 to len loop str1(op+i) := pstr(i); end loop; ip:=ip+1; op:=op+len; elsif str(ip)='\' then case str(ip+1) is when 'n' => str1(op+1):= NUL; if not SPRINTF then write( ll , str1 ); writeline( output, ll); end if; op := 0; ip:=ip+1; str1(op+1) := NUL; when others => end case; ip:=ip+1; else op:=op+1; str1(op) := str(ip); ip:=ip+1; end if; end loop; if op>0 then str1(op+1):=NUL; if SPRINTF then strout := str1(strout'range); else write( ll , str1 ); writeline(output, ll); end if; end if; end theprintf; ------------------------------------------------------------------------------------- procedure printf( str : STRING; params : T_FMT ) is variable strout : STRING (1 to MAXSTRLEN); variable f_fmt : T_FMT_ARRAY ( 1 to 1); begin f_fmt(1) := params; theprintf(FALSE,strout,str,f_fmt); end printf; procedure printf( str : STRING ) is variable strout : STRING (1 to MAXSTRLEN); variable fm : T_FMT_ARRAY ( 1 to 1); begin fm(1).f_type := NONE; theprintf(FALSE,strout,str,fm); end printf; procedure printf( str : STRING; Params : T_FMT_ARRAY ) is variable strout : STRING (1 to MAXSTRLEN); begin theprintf(FALSE,strout,str,Params); end printf; ------------------------------------------------------------------------------------- procedure sprintf( strout : out STRING; str : STRING; Params : T_FMT_ARRAY ) is begin theprintf( TRUE, strout, str,Params); end sprintf; procedure sprintf( strout : out STRING; str : STRING; params : T_FMT ) is variable f_fmt : T_FMT_ARRAY ( 1 to 1); begin f_fmt(1) := params; theprintf( TRUE,strout,str,f_fmt); end sprintf; procedure sprintf( strout : out STRING; str : STRING ) is variable fm : T_FMT_ARRAY ( 1 to 1); begin fm(1).f_type := NONE; theprintf( TRUE,strout,str,fm); end sprintf; ------------------------------------------------------------------------------------- procedure ifprintf( enable : BOOLEAN; str : STRING; Params : T_FMT_ARRAY ) is begin if enable then printf(str,params); end if; end ifprintf; procedure ifprintf( enable : BOOLEAN; str : STRING; params : T_FMT ) is variable f_fmt : T_FMT_ARRAY ( 1 to 1); begin if enable then f_fmt(1) := params; printf(str,f_fmt); end if; end ifprintf; procedure ifprintf( enable : BOOLEAN; str : STRING ) is variable fm : T_FMT_ARRAY ( 1 to 1); begin if enable then fm(1).f_type := NONE; printf(str,fm); end if; end ifprintf; end textio; --------------------------------------------------------------------------- -- This a Test For the above Routines -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use std.textio.all; use work.textio.all; entity textio_test is end textio_test; architecture TB of textio_test is begin process variable dw : std_logic_vector ( 9 downto 0); variable xx : std_logic_vector(15 downto 0); variable xv : std_logic_vector(31 downto 0); variable xi : integer; variable ll : LINE; file FSTR : text open write_mode is "Cpulog.txt" ; variable strout : STRING(1 to 80); begin wait for 1 ns ; printf("Textio Test strings v1.2"); printf("Note I think MTI uses variable width Fonts"); xx:= conv_std_logic_vector( 16#AAAA#,16); printf("Using 04x %04x",fmt(xx)); printf("Using 04u %04u",fmt(xx)); printf("-d...123456 = %d",fmt(123456)); printf("-8d..123456 = %8d",fmt(123456)); printf("-08d.123456 = %08d",fmt(123456)); printf("-02d.123456 = %02d",fmt(123456)); printf("This is a Binary %016b",fmt(16#55AA#)); printf("This is a Decimal %d",fmt(1234)); printf("This is a Hex %h",fmt(16#1234#)); printf("This is a Simple String"); printf("This is a Simple String with a CRLF\nin the middle"); printf("Read Location %d = %h",fmt(123456)&fmt(16#654321#)); printf("-d...-123456 = %d",fmt(-123456)); printf("-d...-123456 = %08d",fmt(-123456)); dw := ( others => '0'); printf("-x...000 = %x",fmt(dw)); dw := "0101010101"; printf("-x...155 = %x",fmt(dw)); printf("-b...155 = %b",fmt(dw)); dw := "0101U10101"; printf("-x...1?5 = %x",fmt(dw)); printf("-b...1?5 = %b",fmt(dw)); dw := "01UUUU0101"; printf("-x...1U5 = %x",fmt(dw)); printf("-b...1U5 = %b",fmt(dw)); printf(" Time is %t ns "); wait for 1500 ps; printf(" Time 1.5ns later is %t ns "); sprintf( strout , "SPRINTF Read Location %d = %h",fmt(123456)&fmt(16#654321#)); printf("OUT STRING %s",fmt(strout)); write( ll , strout ); writeline(FSTR, ll); file_close( FSTR); printf("Around Zero Handling"); for i in 2 downto -2 loop xi := i; printf("Value Integer (d x u h) %d %x %u %h ",fmt(xi)&fmt(xi)&fmt(xi)&fmt(xi)); end loop; for i in 2 downto -2 loop case i is when -2 => xv := ( others => '1'); xv(0) := '0'; when -1 => xv := ( others => '1'); when 0 => xv := ( others => '0'); when 1 => xv := ( others => '0'); xv(0) := '1'; when 2 => xv := ( others => '0'); xv(1) := '1'; end case; printf("Value std_logic (d x u h) %d %x %u %h ",fmt(xv)&fmt(xv)&fmt(xv)&fmt(xv)); end loop; printf("Negative Handling Extended Print"); for i in 2 downto -2 loop xi := i; printf("Value Integer (d x u h) %0d %0x %0u %0h ",fmt(xi)&fmt(xi)&fmt(xi)&fmt(xi)); end loop; for i in 2 downto -2 loop case i is when -2 => xv := ( others => '1'); xv(0) := '0'; when -1 => xv := ( others => '1'); when 0 => xv := ( others => '0'); when 1 => xv := ( others => '0'); xv(0) := '1'; when 2 => xv := ( others => '0'); xv(1) := '1'; end case; printf("Value std_logic (d x u h) %08d %08x %08u %08h ",fmt(xv)&fmt(xv)&fmt(xv)&fmt(xv)); end loop; printf("Negative Handling Extended Print with dont cares"); for i in 2 downto -2 loop case i is when -2 => xv := ( others => '1'); xv(0) := '0'; when -1 => xv := ( others => '1'); when 0 => xv := ( others => '0'); when 1 => xv := ( others => '0'); xv(0) := '1'; when 2 => xv := ( others => '0'); xv(1) := '1'; end case; xv(6) := 'X'; printf("Value std_logic (d x u h) %08d %08x %08u %08h ",fmt(xv)&fmt(xv)&fmt(xv)&fmt(xv)); end loop; printf("Max Values Positive"); for i in 0 to 2 loop case i is when 0 => xi := 16#7FFFFFFD#; when 1 => xi := 16#7FFFFFFE#; when 2 => xi := 16#7FFFFFFF#; end case; printf("Value Integer (d x u h) %0d %0x %0u %0h ",fmt(xi)&fmt(xi)&fmt(xi)&fmt(xi)); end loop; for i in 0 to 2 loop case i is when 0 => xv := ( others => '1'); xv(31) := '0'; xv(1) := '0'; when 1 => xv := ( others => '1'); xv(31) := '0'; xv(0) := '0'; when 2 => xv := ( others => '1'); xv(31) := '0'; xv(0) := '1'; end case; printf("Value std_logic (d x u h) %08d %08x %08u %08h ",fmt(xv)&fmt(xv)&fmt(xv)&fmt(xv)); end loop; printf("Max Values Negative"); for i in 0 to 2 loop -- if extended to most positive simulator loops for ever case i is -- Put these three lines back in for real testing -- commented out to stop warnings! -- when 0 => xi := 16#80000002#; -- when 1 => xi := 16#80000001#; -- when 2 => xi := 16#80000000#; when others => xi:=1000; end case; printf("Value Integer (d x u h) %0d %0x %0u %0h ",fmt(xi)&fmt(xi)&fmt(xi)&fmt(xi)); end loop; for i in 0 to 2 loop case i is when 0 => xv := ( others => '0'); xv(31) := '1'; xv(1) := '1'; when 1 => xv := ( others => '0'); xv(31) := '1'; xv(0) := '1'; when 2 => xv := ( others => '0'); xv(31) := '1'; xv(0) := '0'; end case; printf("Value std_logic (d x u h) %08d %08x %08u %08h ",fmt(xv)&fmt(xv)&fmt(xv)&fmt(xv)); end loop; wait for 1 ns; wait; end process; end TB; -- synthesis translate_off
library verilog; use verilog.vl_types.all; entity ALUcontrol is generic( NOP : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0); ADD : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1); SUB : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0); \AND\ : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi1); \OR\ : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi0); \XOR\ : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi1); SLT : vl_logic_vector(2 downto 0) := (Hi1, Hi1, Hi0); \SLL\ : vl_logic_vector(2 downto 0) := (Hi1, Hi1, Hi1) ); port( ALUop : in vl_logic; instr : in vl_logic_vector(5 downto 0); ALUin : out vl_logic_vector(2 downto 0) ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of NOP : constant is 2; attribute mti_svvh_generic_type of ADD : constant is 2; attribute mti_svvh_generic_type of SUB : constant is 2; attribute mti_svvh_generic_type of \AND\ : constant is 2; attribute mti_svvh_generic_type of \OR\ : constant is 2; attribute mti_svvh_generic_type of \XOR\ : constant is 2; attribute mti_svvh_generic_type of SLT : constant is 2; attribute mti_svvh_generic_type of \SLL\ : constant is 2; end ALUcontrol;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com -- -- The FreeBSD license -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- The views and conclusions contained in the software and documentation -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := 'X'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"32"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 27; constant maxAddrBitBRAM : integer := 14; constant maxIOBit: integer := maxAddrBitIncIO - 1; constant minIOBit: integer := 2; constant stackSize_bits: integer := 9; -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); constant enable_fmul16: boolean := false; constant Undefined: std_logic := '0'; end zpu_config;
-- Copyright (c) 2014 CERN -- Maciej Suminski <maciej.suminski@cern.ch> -- -- This source code is free software; you can redistribute it -- and/or modify it in source code form under the terms of the GNU -- General Public License as published by the Free Software -- Foundation; either version 2 of the License, or (at your option) -- any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA -- Test for VHDL procedure calls. library ieee; use ieee.std_logic_1164.all; entity vhdl_procedure is port(run : in std_logic); end entity vhdl_procedure; architecture test of vhdl_procedure is procedure proc(word_i : std_logic_vector(3 downto 0)) is begin report "Procedure executed"; end procedure; begin process(run) begin report "before rising_edge"; if rising_edge(run) then proc("0000"); end if; report "after rising_edge"; end process; end test;
-- Copyright (c) 2014 CERN -- Maciej Suminski <maciej.suminski@cern.ch> -- -- This source code is free software; you can redistribute it -- and/or modify it in source code form under the terms of the GNU -- General Public License as published by the Free Software -- Foundation; either version 2 of the License, or (at your option) -- any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA -- Test for VHDL procedure calls. library ieee; use ieee.std_logic_1164.all; entity vhdl_procedure is port(run : in std_logic); end entity vhdl_procedure; architecture test of vhdl_procedure is procedure proc(word_i : std_logic_vector(3 downto 0)) is begin report "Procedure executed"; end procedure; begin process(run) begin report "before rising_edge"; if rising_edge(run) then proc("0000"); end if; report "after rising_edge"; end process; end test;
-- Copyright (c) 2014 CERN -- Maciej Suminski <maciej.suminski@cern.ch> -- -- This source code is free software; you can redistribute it -- and/or modify it in source code form under the terms of the GNU -- General Public License as published by the Free Software -- Foundation; either version 2 of the License, or (at your option) -- any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA -- Test for VHDL procedure calls. library ieee; use ieee.std_logic_1164.all; entity vhdl_procedure is port(run : in std_logic); end entity vhdl_procedure; architecture test of vhdl_procedure is procedure proc(word_i : std_logic_vector(3 downto 0)) is begin report "Procedure executed"; end procedure; begin process(run) begin report "before rising_edge"; if rising_edge(run) then proc("0000"); end if; report "after rising_edge"; end process; end test;
-- -- BananaCore - A processor written in VHDL -- -- Created by Rogiel Sulzbach. -- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved. -- library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; use ieee.std_logic_1164.std_logic; library BananaCore; use BananaCore.Core.all; use BananaCore.Memory.all; use BananaCore.RegisterPackage.all; -- The JumpIfCarryInstructionExecutor entity entity JumpIfCarryInstructionExecutor is port( -- the processor main clock clock: in BananaCore.Core.Clock; -- enables the instruction enable: in std_logic; -- the first register to operate on (argument 0) arg0_address: in MemoryAddress; -- a bus indicating if the instruction is ready or not instruction_ready: out std_logic := '0'; ------------------------------------------ -- MEMORY BUS ------------------------------------------ -- the address to read/write memory from/to memory_address: out MemoryAddress := (others => '0'); -- the memory being read to memory_data_read: in MemoryData; -- the memory being written to memory_data_write: out MemoryData := (others => '0'); -- the operation to perform on the memory memory_operation: out MemoryOperation := MEMORY_OP_DISABLED; -- a flag indicating if a memory operation should be performed memory_enable: out std_logic := '0'; -- a flag indicating if a memory operation has completed memory_ready: in std_logic; ------------------------------------------ -- REGISTER BUS ------------------------------------------ -- the processor register address bus register_address: out RegisterAddress := (others => '0'); -- the processor register data bus register_data_read: in RegisterData; -- the processor register data bus register_data_write: out RegisterData := (others => '0'); -- the processor register operation signal register_operation: out RegisterOperation := OP_REG_DISABLED; -- the processor register enable signal register_enable: out std_logic := '0'; -- a flag indicating if a register operation has completed register_ready: in std_logic; ------------------------------------------ -- PROGRAM COUNTER ------------------------------------------ -- the program counter new value program_counter: out MemoryAddress; -- the program counter set flag program_counter_set: out std_logic := '0' ); end JumpIfCarryInstructionExecutor; architecture JumpIfCarryInstructionExecutorImpl of JumpIfCarryInstructionExecutor is type state_type is ( fetch_control_register, store_control_register, execute, complete ); signal state: state_type := fetch_control_register; signal arg0: RegisterData; begin process (clock) begin if clock'event and clock = '1' then if enable = '1' then case state is when fetch_control_register => instruction_ready <= '0'; register_address <= SpecialRegister; register_operation <= OP_REG_GET; register_enable <= '1'; state <= store_control_register; when store_control_register => if register_ready = '1' then arg0 <= register_data_read; register_enable <= '0'; state <= execute; else state <= store_control_register; end if; when execute => if arg0(CarryBit) = '1' then program_counter <= arg0_address; program_counter_set <= '1'; end if; state <= complete; when complete => instruction_ready <= '1'; state <= complete; end case; else instruction_ready <= '0'; program_counter_set <= '0'; state <= fetch_control_register; end if; end if; end process; end JumpIfCarryInstructionExecutorImpl;
library IEEE; use IEEE.std_logic_1164.all; entity Interface is port ( clock : in std_logic; reset : in std_logic; dado : in std_logic; prontoRecep : in std_logic; paridadeOK : in std_logic; prontoTransm : in std_logic; recebe_dado : in std_logic; transmite_dado : in std_logic; dado_trans : in std_logic_vector(6 downto 0); -- Chaves SW6 a SW0 dado_rec : out std_logic_vector(6 downto 0); transm_andamento : out std_logic; tem_dado_rec : out std_logic; partida : out std_logic; dados_ascii : out std_logic ); end Interface; architecture hierarquica of Interface is begin end hierarquica;
----------------------------------------------------------------------------- -- Definition of a single port ROM for RATASM defined by prog_rom.psm -- -- Generated by RATASM Assembler -- -- Standard IEEE libraries -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; ----------------------------------------------------------------------------- entity prog_rom is port ( ADDRESS : in std_logic_vector(9 downto 0); INSTRUCTION : out std_logic_vector(17 downto 0); CLK : in std_logic); end prog_rom; architecture low_level_definition of prog_rom is ----------------------------------------------------------------------------- -- Attributes to define ROM contents during implementation synthesis. -- The information is repeated in the generic map for functional simulation. ----------------------------------------------------------------------------- attribute INIT_00 : string; attribute INIT_01 : string; attribute INIT_02 : string; attribute INIT_03 : string; attribute INIT_04 : string; attribute INIT_05 : string; attribute INIT_06 : string; attribute INIT_07 : string; attribute INIT_08 : string; attribute INIT_09 : string; attribute INIT_0A : string; attribute INIT_0B : string; attribute INIT_0C : string; attribute INIT_0D : string; attribute INIT_0E : string; attribute INIT_0F : string; attribute INIT_10 : string; attribute INIT_11 : string; attribute INIT_12 : string; attribute INIT_13 : string; attribute INIT_14 : string; attribute INIT_15 : string; attribute INIT_16 : string; attribute INIT_17 : string; attribute INIT_18 : string; attribute INIT_19 : string; attribute INIT_1A : string; attribute INIT_1B : string; attribute INIT_1C : string; attribute INIT_1D : string; attribute INIT_1E : string; attribute INIT_1F : string; attribute INIT_20 : string; attribute INIT_21 : string; attribute INIT_22 : string; attribute INIT_23 : string; attribute INIT_24 : string; attribute INIT_25 : string; attribute INIT_26 : string; attribute INIT_27 : string; attribute INIT_28 : string; attribute INIT_29 : string; attribute INIT_2A : string; attribute INIT_2B : string; attribute INIT_2C : string; attribute INIT_2D : string; attribute INIT_2E : string; attribute INIT_2F : string; attribute INIT_30 : string; attribute INIT_31 : string; attribute INIT_32 : string; attribute INIT_33 : string; attribute INIT_34 : string; attribute INIT_35 : string; attribute INIT_36 : string; attribute INIT_37 : string; attribute INIT_38 : string; attribute INIT_39 : string; attribute INIT_3A : string; attribute INIT_3B : string; attribute INIT_3C : string; attribute INIT_3D : string; attribute INIT_3E : string; attribute INIT_3F : string; attribute INITP_00 : string; attribute INITP_01 : string; attribute INITP_02 : string; attribute INITP_03 : string; attribute INITP_04 : string; attribute INITP_05 : string; attribute INITP_06 : string; attribute INITP_07 : string; ---------------------------------------------------------------------- -- Attributes to define ROM contents during implementation synthesis. ---------------------------------------------------------------------- attribute INIT_00 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_01 of ram_1024_x_18 : label is "3F08820181E141A960077F00170F160F360036003600360057A156A134103510"; attribute INIT_02 of ram_1024_x_18 : label is "81E141B160043F0A81E141A960023F0A81E141A960033F0AA20081E141A96004"; attribute INIT_03 of ram_1024_x_18 : label is "800281E3C001010240095F313FB83F0A81E141B160013F0A81E141B160023F08"; attribute INIT_04 of ram_1024_x_18 : label is "000000000000000000000000000000000000000000000000000000008002DF01"; attribute INIT_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_08 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_09 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_00 of ram_1024_x_18 : label is "0000000000000000000000000000000649300C0C0C0C0C0300FA550F00000000"; attribute INITP_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; begin ---------------------------------------------------------------------- --Instantiate the Xilinx primitive for a block RAM --INIT values repeated to define contents for functional simulation ---------------------------------------------------------------------- ram_1024_x_18: RAMB16_S18 --synthesitranslate_off --INIT values repeated to define contents for functional simulation generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"3F08820181E141A960077F00170F160F360036003600360057A156A134103510", INIT_02 => X"81E141B160043F0A81E141A960023F0A81E141A960033F0AA20081E141A96004", INIT_03 => X"800281E3C001010240095F313FB83F0A81E141B160013F0A81E141B160023F08", INIT_04 => X"000000000000000000000000000000000000000000000000000000008002DF01", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"0000000000000000000000000000000649300C0C0C0C0C0300FA550F00000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") --synthesis translate_on port map( DI => "0000000000000000", DIP => "00", EN => '1', WE => '0', SSR => '0', CLK => clk, ADDR => address, DO => INSTRUCTION(15 downto 0), DOP => INSTRUCTION(17 downto 16)); -- end low_level_definition; -- ---------------------------------------------------------------------- -- END OF FILE prog_rom.vhd ----------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; entity shifter is port ( clk : in std_logic; input : in std_logic_vector(15 downto 0); enable : in std_logic; shift_over_flag : out std_logic; ---for pipelined shifter active_output: out std_logic_vector(31 downto 0) ); end shifter; architecture Behavioral of shifter is signal acticv_mul_en : std_logic ; signal input_temp : std_logic_vector(15 downto 0); constant const_one : std_logic_vector(15 downto 0) := "0001000000000000"; --signal shifted_output : std_logic_vector(15 downto 0); signal shifted_output_temp : std_logic_vector(15 downto 0); COMPONENT acticv_mul PORT ( clk : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR(15 DOWNTO 0); b : IN STD_LOGIC_VECTOR(15 DOWNTO 0); d : IN STD_LOGIC_VECTOR(15 DOWNTO 0); p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; begin acticv_mul_map : acticv_mul port map (clk,acticv_mul_en,shifted_output_temp,input_temp,const_one,active_output); shifter : process (clk,enable) variable temp_reg: std_logic_vector(15 downto 0) := (Others => '0'); variable shift_counter: integer := 0; begin if(enable = '0') then temp_reg := (others => '0'); shift_counter := 0; shifted_output_temp <= (others => '0'); input_temp <= (others => '0'); shift_over_flag <= '0'; acticv_mul_en <= '0'; else if rising_edge(clk) then acticv_mul_en <= '0'; if (shift_counter = 0) then temp_reg := input; input_temp <= input; elsif (shift_counter > 2) then --- The activation function is approximated as shifted_output_temp <= temp_reg; --- x(1+0.25*x) . The term 0.25*x is done by temp_reg := input; --- shifting x by 4 times if shift_counter > 4 then acticv_mul_en <= '0'; shift_over_flag <= '1'; else acticv_mul_en <= '1'; end if; else for i in 0 to 13 loop temp_reg(i) := temp_reg(i+1); end loop; temp_reg(14) := '0'; end if; shift_counter := shift_counter + 1; end if; end if; end process; end Behavioral;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: UC3M:MISEA_Thesis:feedforward:1.4 -- IP Revision: 1609011434 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY design_SWandHW_standalone_feedforward_0_0 IS PORT ( s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_AXILiteS_AWVALID : IN STD_LOGIC; s_axi_AXILiteS_AWREADY : OUT STD_LOGIC; s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_AXILiteS_WVALID : IN STD_LOGIC; s_axi_AXILiteS_WREADY : OUT STD_LOGIC; s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_AXILiteS_BVALID : OUT STD_LOGIC; s_axi_AXILiteS_BREADY : IN STD_LOGIC; s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_AXILiteS_ARVALID : IN STD_LOGIC; s_axi_AXILiteS_ARREADY : OUT STD_LOGIC; s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_AXILiteS_RVALID : OUT STD_LOGIC; s_axi_AXILiteS_RREADY : IN STD_LOGIC; ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; interrupt : OUT STD_LOGIC; P_config_TVALID : IN STD_LOGIC; P_config_TREADY : OUT STD_LOGIC; P_config_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); P_WandB_TVALID : IN STD_LOGIC; P_WandB_TREADY : OUT STD_LOGIC; P_WandB_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); P_uOut_TVALID : OUT STD_LOGIC; P_uOut_TREADY : IN STD_LOGIC; P_uOut_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); P_netIn_TVALID : IN STD_LOGIC; P_netIn_TREADY : OUT STD_LOGIC; P_netIn_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); P_netOut_TVALID : OUT STD_LOGIC; P_netOut_TREADY : IN STD_LOGIC; P_netOut_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END design_SWandHW_standalone_feedforward_0_0; ARCHITECTURE design_SWandHW_standalone_feedforward_0_0_arch OF design_SWandHW_standalone_feedforward_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_feedforward_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT feedforward IS GENERIC ( C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER; C_S_AXI_AXILITES_DATA_WIDTH : INTEGER ); PORT ( s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_AXILiteS_AWVALID : IN STD_LOGIC; s_axi_AXILiteS_AWREADY : OUT STD_LOGIC; s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_AXILiteS_WVALID : IN STD_LOGIC; s_axi_AXILiteS_WREADY : OUT STD_LOGIC; s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_AXILiteS_BVALID : OUT STD_LOGIC; s_axi_AXILiteS_BREADY : IN STD_LOGIC; s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axi_AXILiteS_ARVALID : IN STD_LOGIC; s_axi_AXILiteS_ARREADY : OUT STD_LOGIC; s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_AXILiteS_RVALID : OUT STD_LOGIC; s_axi_AXILiteS_RREADY : IN STD_LOGIC; ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; interrupt : OUT STD_LOGIC; P_config_TVALID : IN STD_LOGIC; P_config_TREADY : OUT STD_LOGIC; P_config_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); P_WandB_TVALID : IN STD_LOGIC; P_WandB_TREADY : OUT STD_LOGIC; P_WandB_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); P_uOut_TVALID : OUT STD_LOGIC; P_uOut_TREADY : IN STD_LOGIC; P_uOut_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); P_netIn_TVALID : IN STD_LOGIC; P_netIn_TREADY : OUT STD_LOGIC; P_netIn_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); P_netOut_TVALID : OUT STD_LOGIC; P_netOut_TREADY : IN STD_LOGIC; P_netOut_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT feedforward; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_feedforward_0_0_arch: ARCHITECTURE IS "feedforward,Vivado 2015.4.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_feedforward_0_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_feedforward_0_0,feedforward,{}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RREADY"; ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST"; ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF P_config_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 P_config TVALID"; ATTRIBUTE X_INTERFACE_INFO OF P_config_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 P_config TREADY"; ATTRIBUTE X_INTERFACE_INFO OF P_config_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 P_config TDATA"; ATTRIBUTE X_INTERFACE_INFO OF P_WandB_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 P_WandB TVALID"; ATTRIBUTE X_INTERFACE_INFO OF P_WandB_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 P_WandB TREADY"; ATTRIBUTE X_INTERFACE_INFO OF P_WandB_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 P_WandB TDATA"; ATTRIBUTE X_INTERFACE_INFO OF P_uOut_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 P_uOut TVALID"; ATTRIBUTE X_INTERFACE_INFO OF P_uOut_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 P_uOut TREADY"; ATTRIBUTE X_INTERFACE_INFO OF P_uOut_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 P_uOut TDATA"; ATTRIBUTE X_INTERFACE_INFO OF P_netIn_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 P_netIn TVALID"; ATTRIBUTE X_INTERFACE_INFO OF P_netIn_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 P_netIn TREADY"; ATTRIBUTE X_INTERFACE_INFO OF P_netIn_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 P_netIn TDATA"; ATTRIBUTE X_INTERFACE_INFO OF P_netOut_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 P_netOut TVALID"; ATTRIBUTE X_INTERFACE_INFO OF P_netOut_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 P_netOut TREADY"; ATTRIBUTE X_INTERFACE_INFO OF P_netOut_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 P_netOut TDATA"; BEGIN U0 : feedforward GENERIC MAP ( C_S_AXI_AXILITES_ADDR_WIDTH => 5, C_S_AXI_AXILITES_DATA_WIDTH => 32 ) PORT MAP ( s_axi_AXILiteS_AWADDR => s_axi_AXILiteS_AWADDR, s_axi_AXILiteS_AWVALID => s_axi_AXILiteS_AWVALID, s_axi_AXILiteS_AWREADY => s_axi_AXILiteS_AWREADY, s_axi_AXILiteS_WDATA => s_axi_AXILiteS_WDATA, s_axi_AXILiteS_WSTRB => s_axi_AXILiteS_WSTRB, s_axi_AXILiteS_WVALID => s_axi_AXILiteS_WVALID, s_axi_AXILiteS_WREADY => s_axi_AXILiteS_WREADY, s_axi_AXILiteS_BRESP => s_axi_AXILiteS_BRESP, s_axi_AXILiteS_BVALID => s_axi_AXILiteS_BVALID, s_axi_AXILiteS_BREADY => s_axi_AXILiteS_BREADY, s_axi_AXILiteS_ARADDR => s_axi_AXILiteS_ARADDR, s_axi_AXILiteS_ARVALID => s_axi_AXILiteS_ARVALID, s_axi_AXILiteS_ARREADY => s_axi_AXILiteS_ARREADY, s_axi_AXILiteS_RDATA => s_axi_AXILiteS_RDATA, s_axi_AXILiteS_RRESP => s_axi_AXILiteS_RRESP, s_axi_AXILiteS_RVALID => s_axi_AXILiteS_RVALID, s_axi_AXILiteS_RREADY => s_axi_AXILiteS_RREADY, ap_clk => ap_clk, ap_rst_n => ap_rst_n, interrupt => interrupt, P_config_TVALID => P_config_TVALID, P_config_TREADY => P_config_TREADY, P_config_TDATA => P_config_TDATA, P_WandB_TVALID => P_WandB_TVALID, P_WandB_TREADY => P_WandB_TREADY, P_WandB_TDATA => P_WandB_TDATA, P_uOut_TVALID => P_uOut_TVALID, P_uOut_TREADY => P_uOut_TREADY, P_uOut_TDATA => P_uOut_TDATA, P_netIn_TVALID => P_netIn_TVALID, P_netIn_TREADY => P_netIn_TREADY, P_netIn_TDATA => P_netIn_TDATA, P_netOut_TVALID => P_netOut_TVALID, P_netOut_TREADY => P_netOut_TREADY, P_netOut_TDATA => P_netOut_TDATA ); END design_SWandHW_standalone_feedforward_0_0_arch;
LIBRARY IEEE; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY marcador IS PORT ( numero : IN UNSIGNED(3 DOWNTO 0); hex0 : OUT STD_LOGIC; hex1 : OUT STD_LOGIC; hex2 : OUT STD_LOGIC; hex3 : OUT STD_LOGIC; hex4 : OUT STD_LOGIC; hex5 : OUT STD_LOGIC; hex6 : OUT STD_LOGIC ); END marcador; ARCHITECTURE funcional OF marcador IS BEGIN PROCESS (numero) BEGIN CASE numero IS WHEN x"0" => hex0 <= '0'; hex1 <= '0'; hex2 <= '0'; hex3 <= '0'; hex4 <= '0'; hex5 <= '0'; hex6 <= '1'; WHEN x"1" => hex0 <= '1'; hex1 <= '0'; hex2 <= '0'; hex3 <= '1'; hex4 <= '1'; hex5 <= '1'; hex6 <= '1'; WHEN x"2" => hex0 <= '0'; hex1 <= '0'; hex2 <= '1'; hex3 <= '0'; hex4 <= '0'; hex5 <= '1'; hex6 <= '0'; WHEN x"3" => hex0 <= '0'; hex1 <= '0'; hex2 <= '0'; hex3 <= '0'; hex4 <= '1'; hex5 <= '1'; hex6 <= '0'; WHEN x"4" => hex0 <= '0'; hex1 <= '1'; hex2 <= '0'; hex3 <= '1'; hex4 <= '1'; hex5 <= '0'; hex6 <= '0'; WHEN x"5" => hex0 <= '0'; hex1 <= '1'; hex2 <= '0'; hex3 <= '0'; hex4 <= '1'; hex5 <= '0'; hex6 <= '0'; WHEN x"6" => hex0 <= '0'; hex1 <= '1'; hex2 <= '0'; hex3 <= '0'; hex4 <= '0'; hex5 <= '0'; hex6 <= '0'; WHEN x"7" => hex0 <= '0'; hex1 <= '0'; hex2 <= '0'; hex3 <= '1'; hex4 <= '1'; hex5 <= '0'; hex6 <= '1'; WHEN x"8" => hex0 <= '0'; hex1 <= '0'; hex2 <= '0'; hex3 <= '0'; hex4 <= '0'; hex5 <= '0'; hex6 <= '0'; WHEN x"9" => hex0 <= '0'; hex1 <= '0'; hex2 <= '0'; hex3 <= '1'; hex4 <= '1'; hex5 <= '0'; hex6 <= '0'; WHEN OTHERS => hex0 <= '0'; hex1 <= '0'; hex2 <= '0'; hex3 <= '0'; hex4 <= '0'; hex5 <= '0'; hex6 <= '0'; END CASE; END process; END funcional;
architecture behavior of tb_SPIFrqDiv is constant SPPRWidth : integer range 1 to 8 := 3; constant SPRWidth : integer range 1 to 8 := 3; -- Component Declaration for the Unit Under Test (UUT) component SPIFrqDiv is Generic ( SPPRWidth : integer range 1 to 8 := 3; SPRWidth : integer range 1 to 8 := 3); Port ( Reset_n : in STD_LOGIC; Clk : in STD_LOGIC; SPPR_i : in STD_LOGIC_VECTOR(SPPRWidth-1 downto 0); SPR_i : in STD_LOGIC_VECTOR(SPRWidth-1 downto 0); EnFrqDivider_i : in STD_LOGIC; NextStep_o : out STD_LOGIC); end component; -- Inputs signal Reset_n : STD_LOGIC := '0'; signal Clk : STD_LOGIC := '0'; signal SPPR : STD_LOGIC_VECTOR(SPPRWidth-1 downto 0) := (others => '0'); signal SPR : STD_LOGIC_VECTOR(SPRWidth-1 downto 0) := (others => '0'); signal EnFrqDivider : STD_LOGIC := '0'; -- Outputs signal NextStep : STD_LOGIC; -- Clock period definitions constant Clk_period : time := 10 us; constant Clk_delay : time := Clk_period/10; -- test procedure procedure Testcase ( Testcase : in integer; SPPR_in : in integer; SPR_in : in integer; signal SPPR : out STD_LOGIC_VECTOR(SPPRWidth-1 downto 0); signal SPR : out STD_LOGIC_VECTOR(SPRWidth-1 downto 0); signal EnFrqDivider : out STD_LOGIC; signal NextStep : in STD_LOGIC) is begin wait until Clk'event and Clk = '1'; report "testcase " & integer'image(Testcase) severity note; wait for Clk_delay; SPPR <= std_logic_vector(to_unsigned(SPPR_in, SPPRWidth)); SPR <= std_logic_vector(to_unsigned(SPR_in, SPRWidth)); EnFrqDivider <= '1'; for repetition in 2 downto 0 loop for SPPRCycle in SPPR_in downto 0 loop for SPRCycle in 2**SPR_in-1 downto 0 loop wait until Clk'event and Clk = '1'; wait for Clk_delay; -- assert if SPPRCycle = 0 and SPRCycle = 0 then assert NextStep = '1' report "NextStep should be '1'" severity error; else assert NextStep = '0' report "NextStep should be '0'" severity error; end if; -- stop frequency divider if repetition = 0 and SPPRcycle = 0 and SPRCycle = 0 then EnFrqDivider <= '0'; end if; end loop; end loop; end loop; wait until Clk'event and Clk = '1'; wait until Clk'event and Clk = '1'; end procedure Testcase; begin -- Instantiate the Unit Under Test (UUT) uut: SPIFrqDiv Generic Map ( SPPRWidth => SPPRWidth, SPRWidth => SPRWidth) Port Map ( Reset_n => Reset_n, Clk => Clk, SPPR_i => SPPR, SPR_i => SPR, EnFrqDivider_i => EnFrqDivider, NextStep_o => NextStep); -- Clock process definitions Clk_process: process begin Clk <= '0'; wait for Clk_period/2; Clk <= '1'; wait for Clk_period/2; end process Clk_process; -- Stimulus process stim_proc: process begin -- hold reset state for Clk_period*5. wait for Clk_period*5; Reset_n <= '1'; wait for Clk_period*5; -- testcase 1: test for initial state report "testcase 1" severity note; assert NextStep = '1' report "NextStep should be '1' after reset" severity error; -- end testcase 1; -- testcase 2: Testcase(2, 0, 0, SPPR, SPR, EnFrqDivider, NextStep); -- end testcase 2; -- testcase 3: Testcase(3, 1, 0, SPPR, SPR, EnFrqDivider, NextStep); -- end testcase 3; -- testcase 4: Testcase(4, 2, 0, SPPR, SPR, EnFrqDivider, NextStep); -- end testcase 4; -- testcase 5: Testcase(5, 7, 0, SPPR, SPR, EnFrqDivider, NextStep); -- end testcase 5; -- testcase 6: Testcase(6, 0, 1, SPPR, SPR, EnFrqDivider, NextStep); -- end testcase 6; -- testcase 7: Testcase(7, 0, 2, SPPR, SPR, EnFrqDivider, NextStep); -- end testcase 7; -- testcase 8: Testcase(8, 0, 7, SPPR, SPR, EnFrqDivider, NextStep); -- end testcase 8; -- testcase 9: Testcase(9, 1, 1, SPPR, SPR, EnFrqDivider, NextStep); -- end testcase 9; -- testcase 10: Testcase(10, 2, 2, SPPR, SPR, EnFrqDivider, NextStep); -- end testcase 10; -- testcase 11: Testcase(11, 7, 7, SPPR, SPR, EnFrqDivider, NextStep); -- end testcase 11; -- insert some space time wait for Clk_period*5; -- end simulation report "NONE. Simulation finished" severity failure; -- used to stop simulation end process; end behavior;
entity test is type test1 is (foo, bar); type test2 is (foo, baz); begin end;
--############################### --# Project Name : --# File : --# Author : --# Description : --# Modification History --# --############################### library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity tb_MPU6050 is end tb_MPU6050; architecture stimulus of tb_MPU6050 is -- COMPONENTS -- component MPU6050 port( MCLK : in std_logic; nRST : in std_logic; TIC : in std_logic; SRST : out std_logic; DOUT : out std_logic_vector(7 downto 0); RD : out std_logic; WE : out std_logic; QUEUED : in std_logic; NACK : in std_logic; STOP : in std_logic; DATA_VALID : in std_logic; DIN : in std_logic_vector(7 downto 0); ADR : out std_logic_vector(3 downto 0); DATA : out std_logic_vector(7 downto 0); LOAD : out std_logic; COMPLETED : out std_logic; RESCAN : in std_logic ); end component; component I2CMASTER generic( DEVICE : std_logic_vector(7 downto 0) ); port( MCLK : in std_logic; nRST : in std_logic; SRST : in std_logic; TIC : in std_logic; DIN : in std_logic_vector(7 downto 0); DOUT : out std_logic_vector(7 downto 0); RD : in std_logic; WE : in std_logic; NACK : out std_logic; QUEUED : out std_logic; DATA_VALID : out std_logic; STATUS : out std_logic_vector(2 downto 0); STOP : out std_logic; SCL_IN : in std_logic; SCL_OUT : out std_logic; SDA_IN : in std_logic; SDA_OUT : out std_logic ); end component; -- -- SIGNALS -- signal MCLK : std_logic; signal nRST : std_logic; signal TIC : std_logic; signal SRST : std_logic; signal DOUT : std_logic_vector(7 downto 0); signal RD : std_logic; signal WE : std_logic; signal QUEUED : std_logic; signal NACK : std_logic; signal STOP : std_logic; signal DATA_VALID : std_logic; signal DIN : std_logic_vector(7 downto 0); signal ADR : std_logic_vector(3 downto 0); signal DATA : std_logic_vector(7 downto 0); signal LOAD : std_logic; signal COMPLETED : std_logic; signal RESCAN : std_logic; signal STATUS : std_logic_vector(2 downto 0); signal SCL_IN : std_logic; signal SCL_OUT : std_logic; signal SDA_IN : std_logic; signal SDA_OUT : std_logic; -- signal RUNNING : std_logic := '1'; signal counter : std_logic_vector(7 downto 0); begin -- PORT MAP -- I_MPU6050_0 : MPU6050 port map ( MCLK => MCLK, nRST => nRST, TIC => TIC, SRST => SRST, DOUT => DIN, RD => RD, WE => WE, QUEUED => QUEUED, NACK => NACK, STOP => STOP, DATA_VALID => DATA_VALID, DIN => DOUT, ADR => ADR, DATA => DATA, LOAD => LOAD, COMPLETED => COMPLETED, RESCAN => RESCAN ); -- PORT MAP -- I_I2CMASTER_0 : I2CMASTER generic map ( DEVICE => x"68" ) port map ( MCLK => MCLK, nRST => nRST, SRST => SRST, TIC => TIC, DIN => DIN, DOUT => DOUT, RD => RD, WE => WE, NACK => NACK, QUEUED => QUEUED, DATA_VALID => DATA_VALID, STOP => STOP, STATUS => STATUS, SCL_IN => SCL_IN, SCL_OUT => SCL_OUT, SDA_IN => SDA_IN, SDA_OUT => SDA_OUT ); -- TIC <= counter(7) and counter(5); -- 2.56 + 0.64 uS (~300 khz ) for ~100 kbit GEN: process(MCLK, nRST) begin if (nRST = '0') then counter <= (others=>'0'); elsif (MCLK'event and MCLK='1') then if (TIC = '1') then counter <= (others=>'0'); else counter <= std_logic_vector(to_unsigned(to_integer(unsigned( counter )) + 1, 8)); end if; end if; end process GEN; -- CLOCK: process begin while (RUNNING = '1') loop MCLK <= '1'; wait for 10 ns; MCLK <= '0'; wait for 10 ns; end loop; wait; end process CLOCK; GO: process begin nRST <= '0'; RESCAN <= '0'; SDA_IN <= '0'; SCL_IN <= '0'; wait for 1000 ns; nRST <= '1'; wait until COMPLETED = '1'; RESCAN <= '1'; wait until TIC'event and TIC='0'; RESCAN <= '0'; wait until COMPLETED = '1'; RUNNING <= '0'; wait; end process GO; end stimulus;
------------------------------------------------------------------------------ -- Copyright (c) 2009 Xilinx, Inc. -- This design is confidential and proprietary of Xilinx, All Rights Reserved. ------------------------------------------------------------------------------ -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: 1.0 -- \ \ Filename: clock_generator_ddr_s8_diff.vhd -- / / Date Last Modified: November 5 2009 -- /___/ /\ Date Created: August 1 2008 -- \ \ / \ -- \___\/\___\ -- --Device: Spartan 6 --Purpose: BUFIO2 Based DDR clock generator. Takes in a differential clock -- and instantiates two sets of 2 BUFIO2s, one for each half bank -- --Reference: -- --Revision History: -- Rev 1.0 - First created (nicks) ------------------------------------------------------------------------------ -- -- Disclaimer: -- -- This disclaimer is not a license and does not grant any rights to the materials -- distributed herewith. Except as otherwise provided in a valid license issued to you -- by Xilinx, and to the maximum extent permitted by applicable law: -- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, -- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, -- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR -- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract -- or tort, including negligence, or under any other theory of liability) for any loss or damage -- of any kind or nature related to, arising under or in connection with these materials, -- including for any direct, or any indirect, special, incidental, or consequential loss -- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered -- as a result of any action brought by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the possibility of the same. -- -- Critical Applications: -- -- Xilinx products are not designed or intended to be fail-safe, or for use in any application -- requiring fail-safe performance, such as life-support or safety devices or systems, -- Class III medical devices, nuclear facilities, applications related to the deployment of airbags, -- or any other applications that could lead to death, personal injury, or severe property or -- environmental damage (individually and collectively, "Critical Applications"). Customer assumes -- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only -- to applicable laws and regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all ; library unisim ; use unisim.vcomponents.all ; entity clock_generator_ddr_s8_diff is generic ( S : integer := 8 ; -- Parameter to set the serdes factor DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination port ( clkin_p, clkin_n : in std_logic ; -- differential clock input ioclkap : out std_logic ; -- A P ioclock from BUFIO2 ioclkan : out std_logic ; -- A N ioclock from BUFIO2 serdesstrobea : out std_logic ; -- A serdes strobe from BUFIO2 ioclkbp : out std_logic ; -- B P ioclock from BUFIO2 - leave open if not required ioclkbn : out std_logic ; -- B N ioclock from BUFIO2 - leave open if not required serdesstrobeb : out std_logic ; -- B serdes strobe from BUFIO2 - leave open if not required gclk : out std_logic) ; -- global clock output from BUFIO2 end clock_generator_ddr_s8_diff ; architecture arch_clock_generator_ddr_s8_diff of clock_generator_ddr_s8_diff is signal clkint : std_logic ; -- signal gclk_int : std_logic ; -- signal freqgen_in_p : std_logic ; -- signal tx_bufio2_x1 : std_logic ; -- begin gclk <= gclk_int ; iob_freqgen_in : IBUFGDS generic map( DIFF_TERM => DIFF_TERM) port map ( I => clkin_p, IB => clkin_n, O => freqgen_in_p); bufio2_inst1 : BUFIO2 generic map( DIVIDE => S, -- The DIVCLK divider divide-by value; default 1 I_INVERT => FALSE, -- DIVIDE_BYPASS => FALSE, -- USE_DOUBLER => TRUE) -- port map ( I => freqgen_in_p, -- Input source clock 0 degrees IOCLK => ioclkap, -- Output Clock for IO DIVCLK => tx_bufio2_x1, -- Output Divided Clock SERDESSTROBE => serdesstrobea) ; -- Output SERDES strobe (Clock Enable) bufio2_inst2 : BUFIO2 generic map( I_INVERT => TRUE, -- DIVIDE_BYPASS => FALSE, -- USE_DOUBLER => FALSE) -- port map ( I => freqgen_in_p, -- N_clk input from IDELAY IOCLK => ioclkan, -- Output Clock DIVCLK => open, -- Output Divided Clock SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable) bufio2_inst3 : BUFIO2 generic map( DIVIDE => S, -- The DIVCLK divider divide-by value; default 1 I_INVERT => FALSE, -- DIVIDE_BYPASS => FALSE, -- USE_DOUBLER => TRUE) -- port map ( I => freqgen_in_p, -- Input source clock 0 degrees IOCLK => ioclkbp, -- Output Clock for IO DIVCLK => open, -- Output Divided Clock SERDESSTROBE => serdesstrobeb) ; -- Output SERDES strobe (Clock Enable) bufio2_inst4 : BUFIO2 generic map( I_INVERT => TRUE, -- DIVIDE_BYPASS => FALSE, -- USE_DOUBLER => FALSE) -- port map ( I => freqgen_in_p, -- N_clk input from IDELAY IOCLK => ioclkbn, -- Output Clock DIVCLK => open, -- Output Divided Clock SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable) bufg_tx : BUFG port map (I => tx_bufio2_x1, O => gclk_int) ; end arch_clock_generator_ddr_s8_diff ;
-- ------------------------------------------------------------- -- -- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_modulator/hdl_modulator_sin_hdl.vhd -- Created: 2018-02-27 13:25:15 -- -- Generated by MATLAB 9.3 and HDL Coder 3.11 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: hdl_modulator_sin_hdl -- Source Path: hdl_modulator/wave_generator/sincos hdl/sin_hdl -- Hierarchy Level: 4 -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; USE work.hdl_modulator_hdl_modulator_pkg.ALL; ENTITY hdl_modulator_sin_hdl IS PORT( In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 y : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14 ); END hdl_modulator_sin_hdl; ARCHITECTURE rtl OF hdl_modulator_sin_hdl IS -- Constants CONSTANT nc : vector_of_signed16(0 TO 511) := (to_signed(16#0000#, 16), to_signed(16#0032#, 16), to_signed(16#0065#, 16), to_signed(16#0097#, 16), to_signed(16#00C9#, 16), to_signed(16#00FC#, 16), to_signed(16#012E#, 16), to_signed(16#0161#, 16), to_signed(16#0193#, 16), to_signed(16#01C5#, 16), to_signed(16#01F8#, 16), to_signed(16#022A#, 16), to_signed(16#025C#, 16), to_signed(16#028F#, 16), to_signed(16#02C1#, 16), to_signed(16#02F3#, 16), to_signed(16#0325#, 16), to_signed(16#0358#, 16), to_signed(16#038A#, 16), to_signed(16#03BC#, 16), to_signed(16#03EF#, 16), to_signed(16#0421#, 16), to_signed(16#0453#, 16), to_signed(16#0485#, 16), to_signed(16#04B8#, 16), to_signed(16#04EA#, 16), to_signed(16#051C#, 16), to_signed(16#054E#, 16), to_signed(16#0580#, 16), to_signed(16#05B3#, 16), to_signed(16#05E5#, 16), to_signed(16#0617#, 16), to_signed(16#0649#, 16), to_signed(16#067B#, 16), to_signed(16#06AD#, 16), to_signed(16#06DF#, 16), to_signed(16#0711#, 16), to_signed(16#0743#, 16), to_signed(16#0775#, 16), to_signed(16#07A7#, 16), to_signed(16#07D9#, 16), to_signed(16#080B#, 16), to_signed(16#083D#, 16), to_signed(16#086F#, 16), to_signed(16#08A1#, 16), to_signed(16#08D3#, 16), to_signed(16#0905#, 16), to_signed(16#0937#, 16), to_signed(16#0969#, 16), to_signed(16#099B#, 16), to_signed(16#09CC#, 16), to_signed(16#09FE#, 16), to_signed(16#0A30#, 16), to_signed(16#0A61#, 16), to_signed(16#0A93#, 16), to_signed(16#0AC5#, 16), to_signed(16#0AF6#, 16), to_signed(16#0B28#, 16), to_signed(16#0B5A#, 16), to_signed(16#0B8B#, 16), to_signed(16#0BBD#, 16), to_signed(16#0BEE#, 16), to_signed(16#0C20#, 16), to_signed(16#0C51#, 16), to_signed(16#0C83#, 16), to_signed(16#0CB4#, 16), to_signed(16#0CE5#, 16), to_signed(16#0D17#, 16), to_signed(16#0D48#, 16), to_signed(16#0D79#, 16), to_signed(16#0DAA#, 16), to_signed(16#0DDC#, 16), to_signed(16#0E0D#, 16), to_signed(16#0E3E#, 16), to_signed(16#0E6F#, 16), to_signed(16#0EA0#, 16), to_signed(16#0ED1#, 16), to_signed(16#0F02#, 16), to_signed(16#0F33#, 16), to_signed(16#0F64#, 16), to_signed(16#0F95#, 16), to_signed(16#0FC5#, 16), to_signed(16#0FF6#, 16), to_signed(16#1027#, 16), to_signed(16#1058#, 16), to_signed(16#1088#, 16), to_signed(16#10B9#, 16), to_signed(16#10EA#, 16), to_signed(16#111A#, 16), to_signed(16#114B#, 16), to_signed(16#117B#, 16), to_signed(16#11AC#, 16), to_signed(16#11DC#, 16), to_signed(16#120C#, 16), to_signed(16#123D#, 16), to_signed(16#126D#, 16), to_signed(16#129D#, 16), to_signed(16#12CD#, 16), to_signed(16#12FD#, 16), to_signed(16#132D#, 16), to_signed(16#135D#, 16), to_signed(16#138D#, 16), to_signed(16#13BD#, 16), to_signed(16#13ED#, 16), to_signed(16#141D#, 16), to_signed(16#144D#, 16), to_signed(16#147D#, 16), to_signed(16#14AC#, 16), to_signed(16#14DC#, 16), to_signed(16#150C#, 16), to_signed(16#153B#, 16), to_signed(16#156B#, 16), to_signed(16#159A#, 16), to_signed(16#15C9#, 16), to_signed(16#15F9#, 16), to_signed(16#1628#, 16), to_signed(16#1657#, 16), to_signed(16#1686#, 16), to_signed(16#16B5#, 16), to_signed(16#16E5#, 16), to_signed(16#1714#, 16), to_signed(16#1742#, 16), to_signed(16#1771#, 16), to_signed(16#17A0#, 16), to_signed(16#17CF#, 16), to_signed(16#17FE#, 16), to_signed(16#182C#, 16), to_signed(16#185B#, 16), to_signed(16#188A#, 16), to_signed(16#18B8#, 16), to_signed(16#18E6#, 16), to_signed(16#1915#, 16), to_signed(16#1943#, 16), to_signed(16#1971#, 16), to_signed(16#19A0#, 16), to_signed(16#19CE#, 16), to_signed(16#19FC#, 16), to_signed(16#1A2A#, 16), to_signed(16#1A58#, 16), to_signed(16#1A85#, 16), to_signed(16#1AB3#, 16), to_signed(16#1AE1#, 16), to_signed(16#1B0F#, 16), to_signed(16#1B3C#, 16), to_signed(16#1B6A#, 16), to_signed(16#1B97#, 16), to_signed(16#1BC5#, 16), to_signed(16#1BF2#, 16), to_signed(16#1C1F#, 16), to_signed(16#1C4D#, 16), to_signed(16#1C7A#, 16), to_signed(16#1CA7#, 16), to_signed(16#1CD4#, 16), to_signed(16#1D01#, 16), to_signed(16#1D2E#, 16), to_signed(16#1D5A#, 16), to_signed(16#1D87#, 16), to_signed(16#1DB4#, 16), to_signed(16#1DE0#, 16), to_signed(16#1E0D#, 16), to_signed(16#1E39#, 16), to_signed(16#1E66#, 16), to_signed(16#1E92#, 16), to_signed(16#1EBE#, 16), to_signed(16#1EEA#, 16), to_signed(16#1F16#, 16), to_signed(16#1F42#, 16), to_signed(16#1F6E#, 16), to_signed(16#1F9A#, 16), to_signed(16#1FC6#, 16), to_signed(16#1FF1#, 16), to_signed(16#201D#, 16), to_signed(16#2049#, 16), to_signed(16#2074#, 16), to_signed(16#209F#, 16), to_signed(16#20CB#, 16), to_signed(16#20F6#, 16), to_signed(16#2121#, 16), to_signed(16#214C#, 16), to_signed(16#2177#, 16), to_signed(16#21A2#, 16), to_signed(16#21CD#, 16), to_signed(16#21F7#, 16), to_signed(16#2222#, 16), to_signed(16#224D#, 16), to_signed(16#2277#, 16), to_signed(16#22A2#, 16), to_signed(16#22CC#, 16), to_signed(16#22F6#, 16), to_signed(16#2320#, 16), to_signed(16#234A#, 16), to_signed(16#2374#, 16), to_signed(16#239E#, 16), to_signed(16#23C8#, 16), to_signed(16#23F2#, 16), to_signed(16#241B#, 16), to_signed(16#2445#, 16), to_signed(16#246E#, 16), to_signed(16#2498#, 16), to_signed(16#24C1#, 16), to_signed(16#24EA#, 16), to_signed(16#2513#, 16), to_signed(16#253C#, 16), to_signed(16#2565#, 16), to_signed(16#258E#, 16), to_signed(16#25B7#, 16), to_signed(16#25DF#, 16), to_signed(16#2608#, 16), to_signed(16#2630#, 16), to_signed(16#2659#, 16), to_signed(16#2681#, 16), to_signed(16#26A9#, 16), to_signed(16#26D1#, 16), to_signed(16#26F9#, 16), to_signed(16#2721#, 16), to_signed(16#2749#, 16), to_signed(16#2771#, 16), to_signed(16#2798#, 16), to_signed(16#27C0#, 16), to_signed(16#27E7#, 16), to_signed(16#280F#, 16), to_signed(16#2836#, 16), to_signed(16#285D#, 16), to_signed(16#2884#, 16), to_signed(16#28AB#, 16), to_signed(16#28D2#, 16), to_signed(16#28F9#, 16), to_signed(16#291F#, 16), to_signed(16#2946#, 16), to_signed(16#296C#, 16), to_signed(16#2992#, 16), to_signed(16#29B9#, 16), to_signed(16#29DF#, 16), to_signed(16#2A05#, 16), to_signed(16#2A2B#, 16), to_signed(16#2A51#, 16), to_signed(16#2A76#, 16), to_signed(16#2A9C#, 16), to_signed(16#2AC2#, 16), to_signed(16#2AE7#, 16), to_signed(16#2B0C#, 16), to_signed(16#2B32#, 16), to_signed(16#2B57#, 16), to_signed(16#2B7C#, 16), to_signed(16#2BA1#, 16), to_signed(16#2BC5#, 16), to_signed(16#2BEA#, 16), to_signed(16#2C0F#, 16), to_signed(16#2C33#, 16), to_signed(16#2C57#, 16), to_signed(16#2C7C#, 16), to_signed(16#2CA0#, 16), to_signed(16#2CC4#, 16), to_signed(16#2CE8#, 16), to_signed(16#2D0C#, 16), to_signed(16#2D2F#, 16), to_signed(16#2D53#, 16), to_signed(16#2D77#, 16), to_signed(16#2D9A#, 16), to_signed(16#2DBD#, 16), to_signed(16#2DE0#, 16), to_signed(16#2E03#, 16), to_signed(16#2E26#, 16), to_signed(16#2E49#, 16), to_signed(16#2E6C#, 16), to_signed(16#2E8F#, 16), to_signed(16#2EB1#, 16), to_signed(16#2ED3#, 16), to_signed(16#2EF6#, 16), to_signed(16#2F18#, 16), to_signed(16#2F3A#, 16), to_signed(16#2F5C#, 16), to_signed(16#2F7E#, 16), to_signed(16#2F9F#, 16), to_signed(16#2FC1#, 16), to_signed(16#2FE2#, 16), to_signed(16#3004#, 16), to_signed(16#3025#, 16), to_signed(16#3046#, 16), to_signed(16#3067#, 16), to_signed(16#3088#, 16), to_signed(16#30A9#, 16), to_signed(16#30CA#, 16), to_signed(16#30EA#, 16), to_signed(16#310A#, 16), to_signed(16#312B#, 16), to_signed(16#314B#, 16), to_signed(16#316B#, 16), to_signed(16#318B#, 16), to_signed(16#31AB#, 16), to_signed(16#31CA#, 16), to_signed(16#31EA#, 16), to_signed(16#320A#, 16), to_signed(16#3229#, 16), to_signed(16#3248#, 16), to_signed(16#3267#, 16), to_signed(16#3286#, 16), to_signed(16#32A5#, 16), to_signed(16#32C4#, 16), to_signed(16#32E2#, 16), to_signed(16#3301#, 16), to_signed(16#331F#, 16), to_signed(16#333D#, 16), to_signed(16#335C#, 16), to_signed(16#337A#, 16), to_signed(16#3397#, 16), to_signed(16#33B5#, 16), to_signed(16#33D3#, 16), to_signed(16#33F0#, 16), to_signed(16#340E#, 16), to_signed(16#342B#, 16), to_signed(16#3448#, 16), to_signed(16#3465#, 16), to_signed(16#3482#, 16), to_signed(16#349F#, 16), to_signed(16#34BB#, 16), to_signed(16#34D8#, 16), to_signed(16#34F4#, 16), to_signed(16#3510#, 16), to_signed(16#352C#, 16), to_signed(16#3548#, 16), to_signed(16#3564#, 16), to_signed(16#3580#, 16), to_signed(16#359B#, 16), to_signed(16#35B7#, 16), to_signed(16#35D2#, 16), to_signed(16#35ED#, 16), to_signed(16#3608#, 16), to_signed(16#3623#, 16), to_signed(16#363E#, 16), to_signed(16#3659#, 16), to_signed(16#3673#, 16), to_signed(16#368E#, 16), to_signed(16#36A8#, 16), to_signed(16#36C2#, 16), to_signed(16#36DC#, 16), to_signed(16#36F6#, 16), to_signed(16#3710#, 16), to_signed(16#3729#, 16), to_signed(16#3743#, 16), to_signed(16#375C#, 16), to_signed(16#3775#, 16), to_signed(16#378E#, 16), to_signed(16#37A7#, 16), to_signed(16#37C0#, 16), to_signed(16#37D9#, 16), to_signed(16#37F1#, 16), to_signed(16#380A#, 16), to_signed(16#3822#, 16), to_signed(16#383A#, 16), to_signed(16#3852#, 16), to_signed(16#386A#, 16), to_signed(16#3882#, 16), to_signed(16#3899#, 16), to_signed(16#38B1#, 16), to_signed(16#38C8#, 16), to_signed(16#38DF#, 16), to_signed(16#38F6#, 16), to_signed(16#390D#, 16), to_signed(16#3924#, 16), to_signed(16#393A#, 16), to_signed(16#3951#, 16), to_signed(16#3967#, 16), to_signed(16#397D#, 16), to_signed(16#3994#, 16), to_signed(16#39A9#, 16), to_signed(16#39BF#, 16), to_signed(16#39D5#, 16), to_signed(16#39EA#, 16), to_signed(16#3A00#, 16), to_signed(16#3A15#, 16), to_signed(16#3A2A#, 16), to_signed(16#3A3F#, 16), to_signed(16#3A54#, 16), to_signed(16#3A68#, 16), to_signed(16#3A7D#, 16), to_signed(16#3A91#, 16), to_signed(16#3AA6#, 16), to_signed(16#3ABA#, 16), to_signed(16#3ACE#, 16), to_signed(16#3AE1#, 16), to_signed(16#3AF5#, 16), to_signed(16#3B09#, 16), to_signed(16#3B1C#, 16), to_signed(16#3B2F#, 16), to_signed(16#3B42#, 16), to_signed(16#3B55#, 16), to_signed(16#3B68#, 16), to_signed(16#3B7B#, 16), to_signed(16#3B8D#, 16), to_signed(16#3BA0#, 16), to_signed(16#3BB2#, 16), to_signed(16#3BC4#, 16), to_signed(16#3BD6#, 16), to_signed(16#3BE8#, 16), to_signed(16#3BF9#, 16), to_signed(16#3C0B#, 16), to_signed(16#3C1C#, 16), to_signed(16#3C2D#, 16), to_signed(16#3C3F#, 16), to_signed(16#3C4F#, 16), to_signed(16#3C60#, 16), to_signed(16#3C71#, 16), to_signed(16#3C81#, 16), to_signed(16#3C92#, 16), to_signed(16#3CA2#, 16), to_signed(16#3CB2#, 16), to_signed(16#3CC2#, 16), to_signed(16#3CD2#, 16), to_signed(16#3CE1#, 16), to_signed(16#3CF1#, 16), to_signed(16#3D00#, 16), to_signed(16#3D0F#, 16), to_signed(16#3D1E#, 16), to_signed(16#3D2D#, 16), to_signed(16#3D3C#, 16), to_signed(16#3D4A#, 16), to_signed(16#3D59#, 16), to_signed(16#3D67#, 16), to_signed(16#3D75#, 16), to_signed(16#3D83#, 16), to_signed(16#3D91#, 16), to_signed(16#3D9F#, 16), to_signed(16#3DAC#, 16), to_signed(16#3DBA#, 16), to_signed(16#3DC7#, 16), to_signed(16#3DD4#, 16), to_signed(16#3DE1#, 16), to_signed(16#3DEE#, 16), to_signed(16#3DFA#, 16), to_signed(16#3E07#, 16), to_signed(16#3E13#, 16), to_signed(16#3E1F#, 16), to_signed(16#3E2B#, 16), to_signed(16#3E37#, 16), to_signed(16#3E43#, 16), to_signed(16#3E4F#, 16), to_signed(16#3E5A#, 16), to_signed(16#3E65#, 16), to_signed(16#3E70#, 16), to_signed(16#3E7B#, 16), to_signed(16#3E86#, 16), to_signed(16#3E91#, 16), to_signed(16#3E9B#, 16), to_signed(16#3EA6#, 16), to_signed(16#3EB0#, 16), to_signed(16#3EBA#, 16), to_signed(16#3EC4#, 16), to_signed(16#3ECE#, 16), to_signed(16#3ED7#, 16), to_signed(16#3EE1#, 16), to_signed(16#3EEA#, 16), to_signed(16#3EF3#, 16), to_signed(16#3EFC#, 16), to_signed(16#3F05#, 16), to_signed(16#3F0E#, 16), to_signed(16#3F16#, 16), to_signed(16#3F1F#, 16), to_signed(16#3F27#, 16), to_signed(16#3F2F#, 16), to_signed(16#3F37#, 16), to_signed(16#3F3F#, 16), to_signed(16#3F46#, 16), to_signed(16#3F4E#, 16), to_signed(16#3F55#, 16), to_signed(16#3F5C#, 16), to_signed(16#3F63#, 16), to_signed(16#3F6A#, 16), to_signed(16#3F71#, 16), to_signed(16#3F78#, 16), to_signed(16#3F7E#, 16), to_signed(16#3F84#, 16), to_signed(16#3F8A#, 16), to_signed(16#3F90#, 16), to_signed(16#3F96#, 16), to_signed(16#3F9C#, 16), to_signed(16#3FA1#, 16), to_signed(16#3FA7#, 16), to_signed(16#3FAC#, 16), to_signed(16#3FB1#, 16), to_signed(16#3FB6#, 16), to_signed(16#3FBA#, 16), to_signed(16#3FBF#, 16), to_signed(16#3FC3#, 16), to_signed(16#3FC8#, 16), to_signed(16#3FCC#, 16), to_signed(16#3FD0#, 16), to_signed(16#3FD3#, 16), to_signed(16#3FD7#, 16), to_signed(16#3FDB#, 16), to_signed(16#3FDE#, 16), to_signed(16#3FE1#, 16), to_signed(16#3FE4#, 16), to_signed(16#3FE7#, 16), to_signed(16#3FEA#, 16), to_signed(16#3FEC#, 16), to_signed(16#3FEF#, 16), to_signed(16#3FF1#, 16), to_signed(16#3FF3#, 16), to_signed(16#3FF5#, 16), to_signed(16#3FF7#, 16), to_signed(16#3FF8#, 16), to_signed(16#3FFA#, 16), to_signed(16#3FFB#, 16), to_signed(16#3FFC#, 16), to_signed(16#3FFD#, 16), to_signed(16#3FFE#, 16), to_signed(16#3FFF#, 16), to_signed(16#3FFF#, 16), to_signed(16#4000#, 16), to_signed(16#4000#, 16), to_signed(16#4000#, 16)); -- sfix16 [512] -- Signals SIGNAL In1_signed : signed(15 DOWNTO 0); -- sfix16_En14 SIGNAL insig_out1 : unsigned(8 DOWNTO 0); -- ufix9_En9 SIGNAL Point50_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16 SIGNAL LTEp50_1_cast : unsigned(15 DOWNTO 0); -- ufix16_En16 SIGNAL LTEp50_relop1 : std_logic; SIGNAL pow2switch_out1 : std_logic; SIGNAL Amp50_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16 SIGNAL Amp50_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16 SIGNAL Amp50_out1 : signed(16 DOWNTO 0); -- sfix17_En16 SIGNAL insig_out1_dtc : signed(16 DOWNTO 0); -- sfix17_En16 SIGNAL QuadHandle1_out1 : signed(16 DOWNTO 0); -- sfix17_En16 SIGNAL Point25_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16 SIGNAL LTEp25_1_cast : signed(16 DOWNTO 0); -- sfix17_En16 SIGNAL LTEp25_relop1 : std_logic; SIGNAL p50mA_sub_cast : signed(17 DOWNTO 0); -- sfix18_En16 SIGNAL p50mA_sub_cast_1 : signed(17 DOWNTO 0); -- sfix18_En16 SIGNAL p50mA_out1 : signed(17 DOWNTO 0); -- sfix18_En16 SIGNAL p50mA_out1_dtc : unsigned(8 DOWNTO 0); -- ufix9_En9 SIGNAL QuadHandle1_out1_dtc : unsigned(8 DOWNTO 0); -- ufix9_En9 SIGNAL QuadHandle2_out1 : unsigned(8 DOWNTO 0); -- ufix9_En9 SIGNAL CastU16En2_out1 : unsigned(8 DOWNTO 0); -- ufix9 SIGNAL CastU16En4_out1 : unsigned(9 DOWNTO 0); -- ufix10 SIGNAL x4_out1 : unsigned(9 DOWNTO 0); -- ufix10 SIGNAL CastU16En3_out1 : unsigned(8 DOWNTO 0); -- ufix9 SIGNAL Switch_out1 : unsigned(8 DOWNTO 0); -- ufix9 SIGNAL Look_Up_Table_k : unsigned(8 DOWNTO 0); -- ufix9 SIGNAL Look_Up_Table_out1 : signed(15 DOWNTO 0); -- sfix16_En14 SIGNAL Negate_cast : signed(16 DOWNTO 0); -- sfix17_En14 SIGNAL Negate_cast_1 : signed(16 DOWNTO 0); -- sfix17_En14 SIGNAL Negate_out1 : signed(15 DOWNTO 0); -- sfix16_En14 SIGNAL Sine : signed(15 DOWNTO 0); -- sfix16_En14 BEGIN -- (C) 2016 Mathworks, Inc In1_signed <= signed(In1); insig_out1 <= unsigned(In1_signed(13 DOWNTO 5)); Point50_out1 <= to_unsigned(16#8000#, 16); LTEp50_1_cast <= insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0'; LTEp50_relop1 <= '1' WHEN LTEp50_1_cast <= Point50_out1 ELSE '0'; pow2switch_out1 <= '0'; Amp50_sub_cast <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17)); Amp50_sub_cast_1 <= signed(resize(Point50_out1, 17)); Amp50_out1 <= Amp50_sub_cast - Amp50_sub_cast_1; insig_out1_dtc <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17)); QuadHandle1_out1 <= Amp50_out1 WHEN LTEp50_relop1 = '0' ELSE insig_out1_dtc; Point25_out1 <= to_unsigned(16#4000#, 16); LTEp25_1_cast <= signed(resize(Point25_out1, 17)); LTEp25_relop1 <= '1' WHEN QuadHandle1_out1 <= LTEp25_1_cast ELSE '0'; p50mA_sub_cast <= signed(resize(Point50_out1, 18)); p50mA_sub_cast_1 <= resize(QuadHandle1_out1, 18); p50mA_out1 <= p50mA_sub_cast - p50mA_sub_cast_1; p50mA_out1_dtc <= unsigned(p50mA_out1(15 DOWNTO 7)); QuadHandle1_out1_dtc <= unsigned(QuadHandle1_out1(15 DOWNTO 7)); QuadHandle2_out1 <= p50mA_out1_dtc WHEN LTEp25_relop1 = '0' ELSE QuadHandle1_out1_dtc; CastU16En2_out1 <= QuadHandle2_out1; CastU16En4_out1 <= resize(CastU16En2_out1, 10); -- equivalent to multiply -- by 4 with saturation x4_out1 <= CastU16En4_out1 sll 2; -- saturation block maybe optimized away -- if the NumDataPoints is a power of 2 CastU16En3_out1 <= "111111111" WHEN x4_out1(9) /= '0' ELSE x4_out1(8 DOWNTO 0); Switch_out1 <= CastU16En3_out1 WHEN pow2switch_out1 = '0' ELSE CastU16En3_out1; Look_Up_Table_k <= to_unsigned(16#000#, 9) WHEN Switch_out1 = to_unsigned(16#000#, 9) ELSE to_unsigned(16#1FF#, 9) WHEN Switch_out1 = to_unsigned(16#1FF#, 9) ELSE Switch_out1; Look_Up_Table_out1 <= nc(to_integer(Look_Up_Table_k)); Negate_cast <= resize(Look_Up_Table_out1, 17); Negate_cast_1 <= - (Negate_cast); Negate_out1 <= Negate_cast_1(15 DOWNTO 0); Sine <= Negate_out1 WHEN LTEp50_relop1 = '0' ELSE Look_Up_Table_out1; y <= std_logic_vector(Sine); END rtl;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:08:51 06/04/2016 -- Design Name: -- Module Name: Mux4to1_8bit - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Mux4to1_12bit is port(A, B, C, D : in std_logic_vector(11 downto 0); sel : in std_logic_vector(1 downto 0); S : out std_logic_vector(11 downto 0)); end Mux4to1_12bit; architecture Behavioral of Mux4to1_12bit is begin with sel select s <= A when "00", B when "01", C when "10", D when "11", "XXXXXXXXXXXX" when others; end Behavioral;
-- file: clk_base.vhd -- -- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ -- User entered comments ------------------------------------------------------------------------------ -- None -- ------------------------------------------------------------------------------ -- Output Output Phase Duty Cycle Pk-to-Pk Phase -- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) ------------------------------------------------------------------------------ -- CLK_OUT1___250.000______0.000______50.0______110.209_____98.575 -- ------------------------------------------------------------------------------ -- Input Clock Freq (MHz) Input Jitter (UI) ------------------------------------------------------------------------------ -- __primary_________100.000____________0.010 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity clk_base is port (-- Clock in ports clk_100MHz : in std_logic; -- Clock out ports clk_250MHz : out std_logic; -- Status and control signals locked : out std_logic ); end clk_base; architecture xilinx of clk_base is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; component clk_base_clk_wiz port (-- Clock in ports clk_100MHz : in std_logic; -- Clock out ports clk_250MHz : out std_logic; -- Status and control signals locked : out std_logic ); end component; begin U0: clk_base_clk_wiz port map ( -- Clock in ports clk_100MHz => clk_100MHz, -- Clock out ports clk_250MHz => clk_250MHz, -- Status and control signals locked => locked ); end xilinx;
-- file: clk_base.vhd -- -- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ -- User entered comments ------------------------------------------------------------------------------ -- None -- ------------------------------------------------------------------------------ -- Output Output Phase Duty Cycle Pk-to-Pk Phase -- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) ------------------------------------------------------------------------------ -- CLK_OUT1___250.000______0.000______50.0______110.209_____98.575 -- ------------------------------------------------------------------------------ -- Input Clock Freq (MHz) Input Jitter (UI) ------------------------------------------------------------------------------ -- __primary_________100.000____________0.010 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity clk_base is port (-- Clock in ports clk_100MHz : in std_logic; -- Clock out ports clk_250MHz : out std_logic; -- Status and control signals locked : out std_logic ); end clk_base; architecture xilinx of clk_base is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; component clk_base_clk_wiz port (-- Clock in ports clk_100MHz : in std_logic; -- Clock out ports clk_250MHz : out std_logic; -- Status and control signals locked : out std_logic ); end component; begin U0: clk_base_clk_wiz port map ( -- Clock in ports clk_100MHz => clk_100MHz, -- Clock out ports clk_250MHz => clk_250MHz, -- Status and control signals locked => locked ); end xilinx;
-- ================================================================================= -- // Name: Bryan Mason, James Batcheler, & Brad McMahon -- // File: PC.vhd -- // Date: 12/9/2004 -- // Description: Program Counter -- // Class: CSE 378 -- ================================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity PC is port ( d : in STD_LOGIC_VECTOR (15 downto 0); clr : in STD_LOGIC; clk : in STD_LOGIC; inc : in STD_LOGIC; pload : in STD_LOGIC; q : out STD_LOGIC_VECTOR (15 downto 0) ); end PC; architecture PC_arch of PC is signal COUNT: STD_LOGIC_VECTOR (15 downto 0); begin process (clk, clr) begin if clr = '1' then COUNT <= "0000000000000000"; elsif clk'event and clk='1' then if pload = '0' then if inc = '1' then COUNT <= COUNT + 1; end if; else COUNT <= d; end if; end if; q <= COUNT; end process; end PC_arch;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity regfile is generic (N : integer := 3; M : integer := 16); port (readaddr1, readaddr2 : in std_logic_vector (N - 1 downto 0); writeaddr : in std_logic_vector (N - 1 downto 0); data : in std_logic_vector (M - 1 downto 0); write, clk : in std_logic; O1, O2 : out std_logic_vector (M - 1 downto 0)); end entity; architecture rtl of regfile is type mem is array (natural range <>) of std_logic_vector (M - 1 downto 0); constant memsize : integer := 2 ** N; signal memory : mem (0 to memsize - 1) := (others => (others => '0')); begin process (clk) begin if clk'event and clk = '1' then if write = '1' then memory(to_integer(unsigned(writeaddr))) <= data; else O1 <= memory(to_integer(unsigned(readaddr1))); O2 <= memory(to_integer(unsigned(readaddr2))); end if; end if; end process; end architecture rtl;
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ram_dq_INST_mb.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ram_dq_INST_mb IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ram_dq_INST_mb; ARCHITECTURE SYN OF ram_dq_inst_mb IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_mb", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "N_mb" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_mb" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ram_dq_INST_mb.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ram_dq_INST_mb IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ram_dq_INST_mb; ARCHITECTURE SYN OF ram_dq_inst_mb IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; read_during_write_mode_port_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock0 : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren_a : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_mb", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 8, width_a => 8, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, data_a => data, wren_a => wren, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "N_mb" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_mb" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_mb_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
------------------------------------------------------------------------------- --! @project Unrolled (2) hardware implementation of Asconv1286 --! @author Michael Fivez --! @license This project is released under the GNU Public License. --! The license and distribution terms for this file may be --! found in the file LICENSE in this distribution or at --! http://www.gnu.org/licenses/gpl-3.0.txt --! @note This is an hardware implementation made for my graduation thesis --! at the KULeuven, in the COSIC department (year 2015-2016) --! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions', --! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications) ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Fullrounds is port( Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : in std_logic_vector(63 downto 0); RoundNr : in std_logic_vector(2 downto 0); RoundOut0,RoundOut1,RoundOut2,RoundOut3,RoundOut4 : out std_logic_vector(63 downto 0)); end entity Fullrounds; architecture structural of Fullrounds is signal RoundNr_0, RoundNr_1 : std_logic_vector(3 downto 0); signal SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4 : std_logic_vector(63 downto 0); signal SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4 : std_logic_vector(63 downto 0); signal DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4 : std_logic_vector(63 downto 0); begin -- declare and connect all sub entities sbox1: entity work.Sbox port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr_0, SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4); difflayer1: entity work.FullDiffusionLayer port map(SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4, DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4); sbox2: entity work.Sbox port map(DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4,RoundNr_1, SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4); difflayer2: entity work.FullDiffusionLayer port map(SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4, RoundOut0,RoundOut1,RoundOut2,RoundOut3,RoundOut4); RoundNr_0 <= RoundNr & '0'; RoundNr_1 <= RoundNr & '1'; end architecture structural;
-- ******************** -- * Flip Flop tipo D * -- ******************** -- Con reinicio asíncrono library ieee; use ieee.std_logic_1164.all; entity ffdr is port( clk: in std_logic; -- Reloj rst: in std_logic; -- Reinicio d: in std_logic; q: out std_logic ); end ffdr; architecture arq of ffdr is begin process(clk, rst) begin if (rst='1') then q <='0'; elsif (clk'event and clk='1') then q <= d; end if; end process; end arq;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_LNLUTPOW.VHD *** --*** *** --*** Function: Look Up Table - LN() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_lnlutpow IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_lnlutpow; ARCHITECTURE rtl OF dp_lnlutpow IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28); logexp <= conv_std_logic_vector(0,11); WHEN "0000000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1022,11); WHEN "0000000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1023,11); WHEN "0000000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1024,11); WHEN "0000000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1024,11); WHEN "0000000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1024,11); WHEN "0000000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6526370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(7976716,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6617222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(58241350,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6708074,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(108505984,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6798926,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(158770618,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6889778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209035252,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6980630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259299886,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7071483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(41129064,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7162335,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(91393698,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7253187,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(141658332,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7344039,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(191922966,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7434891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(242187600,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7525744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(24016777,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7616596,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(74281411,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7707448,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(124546045,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7798300,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174810679,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7889152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(225075313,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7980005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(6904491,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8070857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57169125,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8161709,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(107433759,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8252561,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(157698393,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8343413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(207963027,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8434265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(258227661,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8525118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40056839,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8615970,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90321473,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8706822,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140586107,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8797674,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(190850741,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8888526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(241115374,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8979379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(22944552,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9070231,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(73209186,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9161083,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(123473820,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9251935,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173738454,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9342787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(224003088,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9433640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5832266,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9524492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(56096900,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9615344,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106361534,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9706196,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(156626168,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9797048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(206890802,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9887900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257155436,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9978753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(38984614,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10069605,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(89249248,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10160457,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(139513882,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10251309,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(189778515,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10342161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(240043149,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10433014,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21872327,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10523866,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72136961,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10614718,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(122401595,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10705570,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172666229,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10796422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222930863,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10887275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4760041,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10978127,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(55024675,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11068979,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(105289309,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11159831,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155553943,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11250683,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205818577,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11341535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256083211,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11432388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37912389,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11523240,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(88177023,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11614092,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(138441657,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11704944,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188706290,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11795796,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238970924,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11886649,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20800102,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11977501,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71064736,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12068353,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(121329370,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12159205,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171594004,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12250057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221858638,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12340910,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3687816,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12431762,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53952450,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12522614,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104217084,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12613466,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(154481718,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12704318,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204746352,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12795170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255010986,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12886023,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36840164,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12976875,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87104798,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13067727,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137369431,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13158579,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187634065,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13249431,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237898699,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13340284,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19727877,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13431136,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69992511,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13521988,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120257145,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13612840,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170521779,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13703692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220786413,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13794545,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2615591,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13885397,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52880225,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13976249,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103144859,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14067101,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153409493,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14157953,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203674127,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14248805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253938761,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14339658,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35767939,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14430510,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86032572,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14521362,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136297206,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14612214,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186561840,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14703066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236826474,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14793919,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18655652,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14884771,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68920286,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14975623,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119184920,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15066475,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(169449554,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15157327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219714188,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15248180,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1543366,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15339032,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51808000,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15429884,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102072634,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15520736,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152337268,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15611588,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202601902,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15702440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252866536,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15793293,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34695713,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15884145,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84960347,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15974997,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135224981,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16065849,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(185489615,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16156701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235754249,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16247554,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17583427,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16338406,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67848061,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16429258,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118112695,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16520110,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168377329,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16610962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218641963,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16701815,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(471141,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(159585615,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(53151,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184717932,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(98577,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209850249,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(144003,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234982566,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(189429,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260114883,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(234856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(16811744,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(280282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(41944061,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(325708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67076378,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(371134,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92208695,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(416560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117341012,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(461986,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142473329,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(507412,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167605646,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(552838,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192737963,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(598264,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217870280,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(643690,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243002597,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(689116,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268134914,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(734543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(24831775,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(779969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49964092,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(825395,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75096409,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(870821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100228726,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(916247,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125361043,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(961673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150493360,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1007099,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175625677,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1052525,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(200757994,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1097951,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(225890311,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1143377,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251022628,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1188804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(7719489,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1234230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32851805,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1279656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57984122,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1325082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83116439,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1370508,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(108248756,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1415934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133381073,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1461360,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(158513390,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1506786,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183645707,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1552212,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(208778024,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1597638,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233910341,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1643064,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259042658,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1688491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15739519,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1733917,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40871836,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1779343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(66004153,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1824769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(91136470,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1870195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116268787,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1915621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(141401104,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1961047,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166533421,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2006473,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(191665738,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2051899,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(216798055,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2097325,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(241930372,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2142751,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267062689,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2188178,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(23759550,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2233604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48891867,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2279030,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(74024184,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2324456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99156501,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2369882,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(124288818,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2415308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149421135,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2460734,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174553452,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2506160,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199685769,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2551586,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(224818086,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2597012,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249950403,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2642439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(6647263,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2687865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(31779580,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2733291,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(56911897,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2778717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82044214,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2824143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(107176531,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2869569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132308848,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2914995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(157441165,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2960421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182573482,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3005847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(207705799,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3051273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232838116,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3096699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257970433,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3142126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14667294,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3187552,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39799611,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3232978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64931928,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3278404,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90064245,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3323830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115196562,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3369256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140328879,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3414682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165461196,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3460108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(190593513,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3505534,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215725830,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3550960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(240858147,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3596386,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265990464,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3641813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(22687325,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3687239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47819642,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3732665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72951959,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3778091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98084276,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3823517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(123216593,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3868943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148348910,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3914369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173481227,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3959795,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198613544,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4005221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(223745860,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4050647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248878177,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4096074,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5575038,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4141500,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30707355,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4186926,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(55839672,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4232352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80971989,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4277778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106104306,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4323204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131236623,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4368630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(156368940,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4414056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181501257,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4459482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(206633574,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4504908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(231765891,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4550334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256898208,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4595761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13595069,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4641187,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(38727386,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4686613,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(63859703,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4732039,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(88992020,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4777465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114124337,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4822891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(139256654,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4868317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164388971,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4913743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(189521288,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4959169,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214653605,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5004595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(239785922,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5050021,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264918239,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5095448,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21615100,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5140874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(46747417,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5186300,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71879734,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5231726,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97012051,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5277152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(122144368,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5322578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147276685,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5368004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172409002,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5413430,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197541318,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5458856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222673635,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5504282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(247805952,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5549709,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4502813,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5595135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29635130,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5640561,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54767447,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5685987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79899764,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5731413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(105032081,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5776839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130164398,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5822265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155296715,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5867691,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180429032,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5913117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205561349,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5958543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230693666,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6003969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255825983,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6049396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12522844,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6094822,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37655161,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6140248,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62787478,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6185674,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87919795,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6231100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113052112,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6276526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(138184429,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6321952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163316746,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6367378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188449063,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6412804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213581380,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6458230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238713697,28); logexp <= conv_std_logic_vector(1032,11); WHEN others => logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28); logexp <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_LNLUTPOW.VHD *** --*** *** --*** Function: Look Up Table - LN() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_lnlutpow IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_lnlutpow; ARCHITECTURE rtl OF dp_lnlutpow IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28); logexp <= conv_std_logic_vector(0,11); WHEN "0000000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1022,11); WHEN "0000000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1023,11); WHEN "0000000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1024,11); WHEN "0000000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1024,11); WHEN "0000000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1024,11); WHEN "0000000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6526370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(7976716,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6617222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(58241350,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6708074,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(108505984,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6798926,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(158770618,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6889778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209035252,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6980630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259299886,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7071483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(41129064,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7162335,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(91393698,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7253187,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(141658332,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7344039,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(191922966,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7434891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(242187600,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7525744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(24016777,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7616596,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(74281411,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7707448,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(124546045,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7798300,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174810679,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7889152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(225075313,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7980005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(6904491,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8070857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57169125,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8161709,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(107433759,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8252561,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(157698393,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8343413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(207963027,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8434265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(258227661,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8525118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40056839,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8615970,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90321473,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8706822,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140586107,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8797674,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(190850741,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8888526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(241115374,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8979379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(22944552,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9070231,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(73209186,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9161083,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(123473820,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9251935,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173738454,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9342787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(224003088,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9433640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5832266,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9524492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(56096900,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9615344,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106361534,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9706196,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(156626168,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9797048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(206890802,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9887900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257155436,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9978753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(38984614,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10069605,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(89249248,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10160457,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(139513882,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10251309,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(189778515,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10342161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(240043149,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10433014,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21872327,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10523866,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72136961,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10614718,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(122401595,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10705570,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172666229,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10796422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222930863,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10887275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4760041,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10978127,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(55024675,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11068979,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(105289309,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11159831,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155553943,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11250683,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205818577,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11341535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256083211,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11432388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37912389,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11523240,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(88177023,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11614092,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(138441657,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11704944,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188706290,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11795796,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238970924,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11886649,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20800102,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11977501,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71064736,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12068353,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(121329370,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12159205,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171594004,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12250057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221858638,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12340910,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3687816,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12431762,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53952450,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12522614,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104217084,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12613466,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(154481718,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12704318,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204746352,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12795170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255010986,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12886023,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36840164,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12976875,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87104798,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13067727,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137369431,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13158579,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187634065,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13249431,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237898699,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13340284,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19727877,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13431136,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69992511,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13521988,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120257145,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13612840,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170521779,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13703692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220786413,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13794545,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2615591,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13885397,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52880225,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13976249,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103144859,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14067101,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153409493,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14157953,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203674127,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14248805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253938761,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14339658,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35767939,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14430510,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86032572,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14521362,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136297206,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14612214,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186561840,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14703066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236826474,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14793919,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18655652,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14884771,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68920286,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14975623,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119184920,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15066475,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(169449554,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15157327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219714188,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15248180,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1543366,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15339032,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51808000,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15429884,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102072634,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15520736,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152337268,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15611588,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202601902,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15702440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252866536,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15793293,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34695713,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15884145,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84960347,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15974997,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135224981,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16065849,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(185489615,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16156701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235754249,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16247554,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17583427,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16338406,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67848061,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16429258,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118112695,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16520110,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168377329,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16610962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218641963,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16701815,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(471141,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(159585615,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(53151,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184717932,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(98577,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209850249,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(144003,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234982566,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(189429,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260114883,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(234856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(16811744,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(280282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(41944061,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(325708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67076378,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(371134,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92208695,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(416560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117341012,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(461986,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142473329,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(507412,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167605646,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(552838,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192737963,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(598264,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217870280,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(643690,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243002597,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(689116,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268134914,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(734543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(24831775,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(779969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49964092,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(825395,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75096409,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(870821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100228726,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(916247,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125361043,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(961673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150493360,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1007099,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175625677,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1052525,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(200757994,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1097951,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(225890311,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1143377,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251022628,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1188804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(7719489,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1234230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32851805,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1279656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57984122,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1325082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83116439,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1370508,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(108248756,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1415934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133381073,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1461360,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(158513390,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1506786,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183645707,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1552212,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(208778024,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1597638,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233910341,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1643064,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259042658,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1688491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15739519,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1733917,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40871836,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1779343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(66004153,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1824769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(91136470,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1870195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116268787,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1915621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(141401104,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1961047,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166533421,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2006473,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(191665738,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2051899,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(216798055,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2097325,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(241930372,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2142751,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267062689,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2188178,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(23759550,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2233604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48891867,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2279030,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(74024184,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2324456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99156501,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2369882,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(124288818,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2415308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149421135,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2460734,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174553452,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2506160,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199685769,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2551586,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(224818086,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2597012,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249950403,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2642439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(6647263,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2687865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(31779580,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2733291,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(56911897,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2778717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82044214,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2824143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(107176531,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2869569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132308848,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2914995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(157441165,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2960421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182573482,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3005847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(207705799,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3051273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232838116,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3096699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257970433,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3142126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14667294,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3187552,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39799611,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3232978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64931928,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3278404,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90064245,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3323830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115196562,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3369256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140328879,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3414682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165461196,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3460108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(190593513,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3505534,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215725830,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3550960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(240858147,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3596386,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265990464,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3641813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(22687325,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3687239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47819642,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3732665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72951959,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3778091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98084276,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3823517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(123216593,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3868943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148348910,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3914369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173481227,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3959795,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198613544,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4005221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(223745860,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4050647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248878177,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4096074,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5575038,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4141500,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30707355,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4186926,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(55839672,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4232352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80971989,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4277778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106104306,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4323204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131236623,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4368630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(156368940,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4414056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181501257,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4459482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(206633574,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4504908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(231765891,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4550334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256898208,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4595761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13595069,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4641187,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(38727386,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4686613,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(63859703,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4732039,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(88992020,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4777465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114124337,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4822891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(139256654,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4868317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164388971,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4913743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(189521288,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4959169,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214653605,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5004595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(239785922,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5050021,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264918239,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5095448,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21615100,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5140874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(46747417,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5186300,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71879734,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5231726,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97012051,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5277152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(122144368,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5322578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147276685,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5368004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172409002,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5413430,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197541318,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5458856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222673635,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5504282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(247805952,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5549709,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4502813,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5595135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29635130,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5640561,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54767447,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5685987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79899764,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5731413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(105032081,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5776839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130164398,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5822265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155296715,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5867691,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180429032,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5913117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205561349,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5958543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230693666,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6003969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255825983,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6049396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12522844,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6094822,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37655161,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6140248,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62787478,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6185674,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87919795,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6231100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113052112,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6276526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(138184429,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6321952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163316746,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6367378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188449063,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6412804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213581380,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6458230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238713697,28); logexp <= conv_std_logic_vector(1032,11); WHEN others => logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28); logexp <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_LNLUTPOW.VHD *** --*** *** --*** Function: Look Up Table - LN() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_lnlutpow IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_lnlutpow; ARCHITECTURE rtl OF dp_lnlutpow IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28); logexp <= conv_std_logic_vector(0,11); WHEN "0000000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1022,11); WHEN "0000000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1023,11); WHEN "0000000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1024,11); WHEN "0000000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1024,11); WHEN "0000000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1024,11); WHEN "0000000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6526370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(7976716,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6617222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(58241350,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6708074,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(108505984,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6798926,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(158770618,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6889778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209035252,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6980630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259299886,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7071483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(41129064,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7162335,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(91393698,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7253187,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(141658332,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7344039,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(191922966,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7434891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(242187600,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7525744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(24016777,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7616596,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(74281411,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7707448,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(124546045,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7798300,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174810679,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7889152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(225075313,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7980005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(6904491,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8070857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57169125,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8161709,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(107433759,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8252561,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(157698393,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8343413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(207963027,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8434265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(258227661,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8525118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40056839,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8615970,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90321473,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8706822,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140586107,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8797674,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(190850741,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8888526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(241115374,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8979379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(22944552,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9070231,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(73209186,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9161083,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(123473820,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9251935,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173738454,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9342787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(224003088,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9433640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5832266,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9524492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(56096900,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9615344,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106361534,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9706196,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(156626168,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9797048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(206890802,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9887900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257155436,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9978753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(38984614,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10069605,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(89249248,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10160457,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(139513882,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10251309,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(189778515,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10342161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(240043149,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10433014,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21872327,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10523866,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72136961,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10614718,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(122401595,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10705570,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172666229,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10796422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222930863,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10887275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4760041,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10978127,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(55024675,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11068979,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(105289309,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11159831,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155553943,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11250683,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205818577,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11341535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256083211,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11432388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37912389,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11523240,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(88177023,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11614092,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(138441657,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11704944,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188706290,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11795796,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238970924,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11886649,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20800102,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11977501,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71064736,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12068353,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(121329370,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12159205,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171594004,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12250057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221858638,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12340910,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3687816,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12431762,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53952450,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12522614,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104217084,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12613466,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(154481718,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12704318,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204746352,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12795170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255010986,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12886023,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36840164,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12976875,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87104798,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13067727,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137369431,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13158579,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187634065,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13249431,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237898699,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13340284,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19727877,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13431136,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69992511,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13521988,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120257145,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13612840,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170521779,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13703692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220786413,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13794545,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2615591,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13885397,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52880225,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13976249,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103144859,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14067101,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153409493,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14157953,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203674127,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14248805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253938761,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14339658,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35767939,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14430510,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86032572,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14521362,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136297206,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14612214,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186561840,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14703066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236826474,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14793919,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18655652,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14884771,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68920286,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14975623,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119184920,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15066475,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(169449554,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15157327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219714188,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15248180,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1543366,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15339032,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51808000,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15429884,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102072634,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15520736,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152337268,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15611588,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202601902,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15702440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252866536,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15793293,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34695713,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15884145,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84960347,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15974997,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135224981,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16065849,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(185489615,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16156701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235754249,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16247554,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17583427,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16338406,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67848061,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16429258,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118112695,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16520110,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168377329,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16610962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218641963,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16701815,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(471141,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(159585615,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(53151,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184717932,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(98577,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209850249,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(144003,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234982566,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(189429,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260114883,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(234856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(16811744,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(280282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(41944061,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(325708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67076378,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(371134,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92208695,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(416560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117341012,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(461986,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142473329,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(507412,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167605646,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(552838,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192737963,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(598264,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217870280,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(643690,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243002597,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(689116,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268134914,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(734543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(24831775,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(779969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49964092,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(825395,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75096409,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(870821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100228726,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(916247,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125361043,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(961673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150493360,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1007099,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175625677,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1052525,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(200757994,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1097951,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(225890311,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1143377,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251022628,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1188804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(7719489,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1234230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32851805,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1279656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57984122,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1325082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83116439,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1370508,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(108248756,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1415934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133381073,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1461360,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(158513390,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1506786,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183645707,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1552212,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(208778024,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1597638,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233910341,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1643064,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259042658,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1688491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15739519,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1733917,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40871836,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1779343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(66004153,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1824769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(91136470,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1870195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116268787,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1915621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(141401104,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1961047,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166533421,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2006473,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(191665738,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2051899,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(216798055,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2097325,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(241930372,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2142751,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267062689,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2188178,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(23759550,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2233604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48891867,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2279030,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(74024184,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2324456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99156501,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2369882,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(124288818,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2415308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149421135,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2460734,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174553452,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2506160,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199685769,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2551586,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(224818086,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2597012,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249950403,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2642439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(6647263,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2687865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(31779580,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2733291,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(56911897,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2778717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82044214,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2824143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(107176531,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2869569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132308848,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2914995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(157441165,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2960421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182573482,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3005847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(207705799,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3051273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232838116,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3096699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257970433,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3142126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14667294,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3187552,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39799611,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3232978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64931928,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3278404,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90064245,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3323830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115196562,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3369256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140328879,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3414682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165461196,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3460108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(190593513,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3505534,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215725830,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3550960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(240858147,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3596386,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265990464,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3641813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(22687325,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3687239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47819642,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3732665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72951959,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3778091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98084276,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3823517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(123216593,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3868943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148348910,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3914369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173481227,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3959795,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198613544,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4005221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(223745860,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4050647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248878177,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4096074,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5575038,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4141500,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30707355,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4186926,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(55839672,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4232352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80971989,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4277778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106104306,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4323204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131236623,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4368630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(156368940,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4414056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181501257,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4459482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(206633574,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4504908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(231765891,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4550334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256898208,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4595761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13595069,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4641187,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(38727386,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4686613,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(63859703,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4732039,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(88992020,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4777465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114124337,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4822891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(139256654,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4868317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164388971,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4913743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(189521288,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4959169,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214653605,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5004595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(239785922,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5050021,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264918239,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5095448,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21615100,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5140874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(46747417,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5186300,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71879734,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5231726,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97012051,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5277152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(122144368,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5322578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147276685,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5368004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172409002,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5413430,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197541318,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5458856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222673635,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5504282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(247805952,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5549709,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4502813,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5595135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29635130,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5640561,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54767447,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5685987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79899764,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5731413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(105032081,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5776839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130164398,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5822265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155296715,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5867691,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180429032,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5913117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205561349,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5958543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230693666,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6003969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255825983,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6049396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12522844,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6094822,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37655161,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6140248,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62787478,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6185674,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87919795,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6231100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113052112,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6276526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(138184429,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6321952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163316746,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6367378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188449063,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6412804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213581380,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6458230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238713697,28); logexp <= conv_std_logic_vector(1032,11); WHEN others => logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28); logexp <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_LNLUTPOW.VHD *** --*** *** --*** Function: Look Up Table - LN() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_lnlutpow IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_lnlutpow; ARCHITECTURE rtl OF dp_lnlutpow IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28); logexp <= conv_std_logic_vector(0,11); WHEN "0000000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1022,11); WHEN "0000000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1023,11); WHEN "0000000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1024,11); WHEN "0000000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1024,11); WHEN "0000000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1024,11); WHEN "0000000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1025,11); WHEN "0000001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1026,11); WHEN "0000011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1027,11); WHEN "0000101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0000111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1028,11); WHEN "0001011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0001111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1029,11); WHEN "0010111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0010111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0011111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0100111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28); logexp <= conv_std_logic_vector(1030,11); WHEN "0101110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0101111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0110111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28); logexp <= conv_std_logic_vector(1031,11); WHEN "0111111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6480943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251279855,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6526370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(7976716,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6571796,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33109033,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6617222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(58241350,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6662648,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83373667,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6708074,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(108505984,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6753500,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133638301,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6798926,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(158770618,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6844352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183902935,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6889778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209035252,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6935204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234167569,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6980630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259299886,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7026057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15996747,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7071483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(41129064,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7116909,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(66261381,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7162335,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(91393698,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7207761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116526015,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7253187,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(141658332,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7298613,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166790649,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7344039,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(191922966,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7389465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217055283,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7434891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(242187600,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7480317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267319916,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7525744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(24016777,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7571170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49149094,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7616596,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(74281411,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7662022,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99413728,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7707448,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(124546045,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7752874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149678362,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7798300,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174810679,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7843726,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199942996,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7889152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(225075313,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7934578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250207630,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7980005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(6904491,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8025431,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32036808,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8070857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57169125,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8116283,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82301442,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8161709,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(107433759,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8207135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132566076,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8252561,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(157698393,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8297987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182830710,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8343413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(207963027,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8388839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233095344,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8434265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(258227661,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8479692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14924522,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8525118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40056839,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8570544,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(65189156,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8615970,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90321473,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8661396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115453790,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8706822,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140586107,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8752248,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165718424,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8797674,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(190850741,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8843100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215983058,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8888526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(241115374,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8933952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(266247691,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(8979379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(22944552,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9024805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48076869,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9070231,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(73209186,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9115657,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98341503,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9161083,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(123473820,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9206509,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148606137,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9251935,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173738454,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9297361,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198870771,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1000111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9342787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(224003088,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9388213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249135405,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9433640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5832266,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9479066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30964583,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9524492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(56096900,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9569918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81229217,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9615344,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106361534,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9660770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131493851,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9706196,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(156626168,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9751622,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181758485,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9797048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(206890802,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9842474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232023119,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9887900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257155436,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9933327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13852297,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(9978753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(38984614,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10024179,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64116931,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10069605,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(89249248,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10115031,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114381565,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10160457,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(139513882,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10205883,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164646199,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10251309,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(189778515,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10296735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214910832,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10342161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(240043149,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10387587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265175466,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10433014,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21872327,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10478440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47004644,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10523866,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72136961,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10569292,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97269278,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10614718,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(122401595,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10660144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147533912,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10705570,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172666229,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10750996,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197798546,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10796422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222930863,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10841848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248063180,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10887275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4760041,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10932701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29892358,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(10978127,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(55024675,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11023553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80156992,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11068979,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(105289309,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11114405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130421626,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11159831,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155553943,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11205257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180686260,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11250683,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205818577,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11296109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230950894,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11341535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256083211,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11386962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12780072,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11432388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37912389,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11477814,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(63044706,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11523240,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(88177023,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11568666,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113309340,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11614092,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(138441657,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11659518,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163573973,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11704944,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188706290,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11750370,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213838607,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11795796,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238970924,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11841222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264103241,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11886649,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20800102,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11932075,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45932419,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(11977501,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71064736,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12022927,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(96197053,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12068353,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(121329370,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12113779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146461687,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12159205,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171594004,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12204631,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196726321,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1001111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12250057,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221858638,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12295483,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246990955,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12340910,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3687816,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12386336,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28820133,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12431762,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53952450,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12477188,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79084767,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12522614,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104217084,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12568040,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129349401,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12613466,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(154481718,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12658892,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179614035,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12704318,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204746352,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12749744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229878669,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12795170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255010986,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12840597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11707847,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12886023,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36840164,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12931449,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61972481,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(12976875,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87104798,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13022301,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112237114,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13067727,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137369431,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13113153,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162501748,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13158579,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187634065,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13204005,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212766382,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13249431,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237898699,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13294857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263031016,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13340284,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19727877,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13385710,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44860194,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13431136,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69992511,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13476562,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95124828,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13521988,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120257145,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13567414,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145389462,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13612840,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170521779,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13658266,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195654096,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13703692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220786413,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13749118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245918730,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13794545,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2615591,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13839971,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27747908,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13885397,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52880225,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13930823,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78012542,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(13976249,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103144859,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14021675,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128277176,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14067101,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153409493,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14112527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178541810,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14157953,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203674127,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14203379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228806444,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14248805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253938761,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14294232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10635622,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14339658,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35767939,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14385084,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60900256,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14430510,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86032572,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14475936,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111164889,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14521362,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136297206,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14566788,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161429523,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14612214,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186561840,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14657640,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211694157,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14703066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236826474,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14748492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261958791,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14793919,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18655652,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14839345,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43787969,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14884771,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68920286,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14930197,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94052603,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(14975623,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119184920,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15021049,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144317237,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15066475,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(169449554,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15111901,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194581871,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1010111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15157327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219714188,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15202753,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244846505,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15248180,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1543366,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15293606,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26675683,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15339032,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51808000,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15384458,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76940317,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15429884,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102072634,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15475310,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127204951,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15520736,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152337268,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15566162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177469585,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15611588,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202601902,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15657014,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227734219,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15702440,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252866536,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15747867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9563397,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15793293,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34695713,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15838719,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59828030,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15884145,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84960347,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15929571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110092664,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(15974997,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135224981,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16020423,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160357298,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16065849,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(185489615,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16111275,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210621932,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16156701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235754249,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16202127,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260886566,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16247554,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17583427,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16292980,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42715744,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16338406,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67848061,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16383832,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92980378,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16429258,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118112695,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16474684,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143245012,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16520110,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168377329,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16565536,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(193509646,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16610962,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218641963,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16656388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243774280,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16701815,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(471141,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(16747241,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25603458,28); logexp <= conv_std_logic_vector(1031,11); WHEN "1011100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(7725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(159585615,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(30438,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172151774,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(53151,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184717932,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(75864,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197284091,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(98577,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209850249,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(121290,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222416408,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(144003,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234982566,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(166716,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(247548725,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(189429,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260114883,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(212143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4245586,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(234856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(16811744,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(257569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29377903,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(280282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(41944061,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(302995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54510220,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(325708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67076378,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(348421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79642537,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(371134,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92208695,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(393847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104774854,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(416560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117341012,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(439273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129907171,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(461986,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142473329,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(484699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155039488,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(507412,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167605646,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(530125,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180171805,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(552838,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192737963,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(575551,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205304121,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(598264,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217870280,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(620977,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230436438,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1011111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(643690,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243002597,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(666403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255568755,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(689116,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268134914,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(711830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12265616,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(734543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(24831775,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(757256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37397933,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(779969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49964092,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(802682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62530250,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(825395,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75096409,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(848108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87662567,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(870821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100228726,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(893534,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112794884,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(916247,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125361043,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(938960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137927201,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(961673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150493360,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(984386,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163059518,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1007099,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175625677,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1029812,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188191835,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1052525,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(200757994,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1075238,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213324152,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1097951,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(225890311,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1120664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238456469,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1143377,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251022628,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1166090,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263588786,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1188804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(7719489,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1211517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20285647,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1234230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32851805,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1256943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45417964,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1279656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57984122,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1302369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70550281,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1325082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83116439,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1347795,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95682598,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1370508,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(108248756,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1393221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120814915,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1415934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133381073,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1438647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145947232,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1461360,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(158513390,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1484073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171079549,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1506786,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183645707,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1529499,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196211866,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1552212,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(208778024,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1574925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221344183,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1597638,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233910341,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1620351,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246476500,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1643064,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259042658,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1665778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3173361,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1688491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15739519,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1711204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28305678,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1733917,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40871836,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1756630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53437995,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1779343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(66004153,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1802056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78570312,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1824769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(91136470,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1847482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103702629,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1870195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116268787,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1892908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(128834946,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1915621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(141401104,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1938334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153967262,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1961047,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166533421,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(1983760,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179099579,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2006473,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(191665738,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2029186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204231896,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2051899,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(216798055,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2074612,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229364213,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1100111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2097325,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(241930372,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2120038,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254496530,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2142751,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267062689,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2165465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11193391,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2188178,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(23759550,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2210891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36325708,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2233604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48891867,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2256317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(61458025,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2279030,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(74024184,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2301743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86590342,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2324456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99156501,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2347169,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111722659,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2369882,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(124288818,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2392595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136854976,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2415308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149421135,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2438021,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161987293,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2460734,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174553452,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2483447,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(187119610,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2506160,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199685769,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2528873,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212251927,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2551586,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(224818086,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2574299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237384244,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2597012,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(249950403,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2619725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(262516561,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2642439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(6647263,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2665152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19213422,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2687865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(31779580,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2710578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(44345739,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2733291,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(56911897,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2756004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69478056,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2778717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82044214,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2801430,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94610373,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2824143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(107176531,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2846856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(119742690,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2869569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132308848,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2892282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144875007,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2914995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(157441165,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2937708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170007324,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2960421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182573482,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(2983134,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195139641,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3005847,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(207705799,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3028560,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220271958,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3051273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232838116,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3073986,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245404275,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3096699,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257970433,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3119413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2101136,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3142126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14667294,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3164839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27233453,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3187552,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39799611,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3210265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52365770,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3232978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64931928,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3255691,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(77498087,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3278404,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90064245,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3301117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102630404,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3323830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115196562,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3346543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127762720,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3369256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140328879,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3391969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152895037,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3414682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165461196,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3437395,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178027354,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3460108,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(190593513,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3482821,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203159671,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3505534,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215725830,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3528247,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(228291988,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1101111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3550960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(240858147,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3573673,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253424305,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3596386,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265990464,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3619100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10121166,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3641813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(22687325,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3664526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(35253483,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3687239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47819642,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3709952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60385800,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3732665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72951959,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3755378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85518117,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3778091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98084276,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3800804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110650434,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3823517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(123216593,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3846230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135782751,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3868943,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148348910,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3891656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160915068,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3914369,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173481227,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3937082,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186047385,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3959795,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198613544,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(3982508,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211179702,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4005221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(223745860,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4027934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236312019,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4050647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248878177,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4073360,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261444336,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4096074,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5575038,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4118787,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18141197,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4141500,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30707355,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4164213,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43273514,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4186926,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(55839672,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4209639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68405831,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4232352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80971989,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4255065,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(93538148,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4277778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106104306,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4300491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118670465,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4323204,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131236623,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4345917,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143802782,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4368630,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(156368940,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4391343,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168935099,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4414056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181501257,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4436769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194067416,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4459482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(206633574,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4482195,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(219199733,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4504908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(231765891,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4527621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244332050,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4550334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256898208,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4573048,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1028911,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4595761,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13595069,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4618474,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26161228,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4641187,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(38727386,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4663900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51293545,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4686613,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(63859703,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4709326,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76425861,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4732039,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(88992020,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4754752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101558178,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4777465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114124337,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4800178,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(126690495,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4822891,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(139256654,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4845604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(151822812,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4868317,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164388971,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4891030,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(176955129,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4913743,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(189521288,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4936456,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202087446,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4959169,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214653605,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(4981882,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227219763,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1110111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5004595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(239785922,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5027308,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252352080,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5050021,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264918239,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5072735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9048941,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5095448,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21615100,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5118161,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34181258,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5140874,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(46747417,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5163587,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59313575,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111000111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5186300,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71879734,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5209013,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(84445892,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5231726,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97012051,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5254439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(109578209,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5277152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(122144368,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5299865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(134710526,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5322578,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147276685,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5345291,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(159842843,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111001111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5368004,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172409002,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5390717,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184975160,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5413430,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197541318,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5436143,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210107477,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5458856,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222673635,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5481569,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235239794,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5504282,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(247805952,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5526995,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260372111,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111010111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5549709,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4502813,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5572422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17068972,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5595135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29635130,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5617848,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42201289,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5640561,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54767447,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5663274,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67333606,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5685987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79899764,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5708700,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92465923,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111011111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5731413,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(105032081,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5754126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117598240,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5776839,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130164398,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5799552,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142730557,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5822265,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(155296715,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5844978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(167862874,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5867691,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180429032,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5890404,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192995191,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111100111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5913117,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(205561349,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5935830,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218127508,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5958543,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230693666,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(5981256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243259825,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6003969,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(255825983,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6026682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268392142,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6049396,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12522844,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6072109,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25089003,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111101111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6094822,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37655161,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6117535,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50221319,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6140248,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62787478,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6162961,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75353636,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6185674,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87919795,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6208387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100485953,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6231100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113052112,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6253813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125618270,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111110111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6276526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(138184429,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111000" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6299239,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150750587,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111001" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6321952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163316746,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111010" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6344665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175882904,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111011" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6367378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(188449063,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111100" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6390091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201015221,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111101" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6412804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213581380,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111110" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6435517,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(226147538,28); logexp <= conv_std_logic_vector(1032,11); WHEN "1111111111" => logman(52 DOWNTO 29) <= conv_std_logic_vector(6458230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238713697,28); logexp <= conv_std_logic_vector(1032,11); WHEN others => logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28); logexp <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;