content stringlengths 1 1.04M ⌀ |
|---|
-- NEED RESULT: ARCH00071.P1: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P2: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00071.P3: Multi transport transactions occurred on signal asg with simpl... |
-- $Id: rb_sres_or_3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_3 - syn
-- Description: rbus r... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
ENTITY GreenDroidADDMPCore IS
PORT (
i00 : IN std_logic_vector(31 DOWNTO 0);
i01 : IN std_logic_vector(31 DOWNTO 0);
r00 : OUT std_logic_vector(31 DOWNTO 0);
r01 : OUT std... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:42:38 12/26/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_clockedround2.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versi... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:42:38 12/26/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_clockedround2.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versi... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_1_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_1_e-... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.49... |
-------------------------------------------------------------------------------
-- axi_vdma_sts_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All right... |
-------------------------------------------------------------------------------
-- axi_vdma_sts_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All right... |
-------------------------------------------------------------------------------
-- axi_vdma_sts_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All right... |
-------------------------------------------------------------------------------
-- axi_vdma_sts_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All right... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Tue Sep 17 15:49:29 2019
-- Host : varun-laptop running 64-bit Serv... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- system_tb.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- START USER CODE (Do not remove this line)
-- User:... |
--This should pass
context c1 is
end context c1;
--This should fail
context c1 is
end context c1;
context c1 is
end context c1; context c2 is end context c2;
context c1 is
end context c1;
|
-----------------------------------------------------------------------------------------------------------
--
-- NONRESTORING INTEGER OPERANDS DIVIDER
--
-- Created by Claudio Brunelli, 2004
--
-----------------------------------------------------------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package debounce_pkg is
component debounce is
generic(
counter_size : INTEGER := 19 --counter size (19 bits gives 10.5ms with 50MHz clock)
);
port(
clk : IN STD_LOGIC; --input clock
button : ... |
-- file: pll_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaim... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: Jochem Govers
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4... |
library ieee;
use ieee.std_logic_1164.all;
entity writeback is
port(
AluOutW, ReadDataW: in std_logic_vector(31 downto 0);
MemToReg: in std_logic;
ResultW: out std_logic_vector(31 downto 0));
end entity;
architecture wb_arq of writeback is
component mux2
generic (MAX : integer ... |
library ieee;
use ieee.std_logic_1164.all;
entity writeback is
port(
AluOutW, ReadDataW: in std_logic_vector(31 downto 0);
MemToReg: in std_logic;
ResultW: out std_logic_vector(31 downto 0));
end entity;
architecture wb_arq of writeback is
component mux2
generic (MAX : integer ... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY control IS
PORT
(
instruction : IN std_logic_vector(5 downto 0);
RegDst : OUT std_logic;
Branch : OUT std_logic_vector(1 downto 0);
MemtoReg : OUT std_logic;
ALUOp : OUT std_logic_vector(3 downto 0);
MemWrite : OUT std_logic;
ALUSrc : OU... |
-- $Id: serport_1clock.vhd 438 2011-12-11 23:40:52Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versio... |
-------------------------------------------------------------------------------
-- axi_vdma_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights re... |
-------------------------------------------------------------------------------
-- axi_vdma_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights re... |
entity ISSUE351 is
end ISSUE351;
architecture RTL of ISSUE351 is
type WORD_TYPE is record
KEY : integer;
VALUE : integer;
end record;
constant WORD_NULL : WORD_TYPE := (KEY => 0, VALUE => 0);
type WORD_VECTOR is array (INTEGER range <... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------
-- VHDL code for 4:1 multiplexor
-- (ESD book figure 2.5)
-- by Weijun Zhang, 04/2001
--
-- Multiplexor is a device to select different
-- inputs to outputs. we use 3 bits vector to
-- describe its I/O ports
-------------------------------------------------
library i... |
-------------------------------------------------------------------------------
-- Title : DDS Address Generator
-- Project :
-------------------------------------------------------------------------------
-- File : DDSAddressGenerator.vhd
-- Author : Marco Eppenberger <marco@Pierce.home>
-- Company... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:43:33 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bi... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
--============================================================================
--!
--! \file <FILE_NAME>
--!
--! \project <PROJECT_NAME>
--!
--! \langv VHDL-1987
--!
--! \brief <BRIEF_DESCRIPTION>.
--!
--! \details <DETAILED_DESCRIPTION>.
--!
--! \bug <BUGS_OR_KNOWN_ISSUES>.
--!
--! \see <R... |
-- ********************************************************************/
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROV... |
library verilog;
use verilog.vl_types.all;
entity ALUcontrol is
generic(
NOP : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
ADD : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1);
SUB : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0);
\AND\ ... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Me... |
library IEEE;
use IEEE.std_logic_1164.all;
entity Interface is
port (
clock : in std_logic;
reset : in std_logic;
dado : in std_logic;
prontoRecep : in std_logic;
paridadeOK : in std_logic;
prontoTransm : in std_logic;
recebe_dado : in std_logic;
transmite_dado ... |
-----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
--------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity shifter is
port ( clk : in std_logic;
input : in std_logic_vector(15 downto 0);
enable : in std_logic;
shift_over_flag : out std_logic; ---for pipelined shifter
active_output: out std_logic_vector(31 downto 0)
);
end shif... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY marcador IS
PORT (
numero : IN UNSIGNED(3 DOWNTO 0);
hex0 : OUT STD_LOGIC;
hex1 : OUT STD_LOGIC;
hex2 : OUT STD_LOGIC;
hex3 : OUT STD_LOGIC;
... |
architecture behavior of tb_SPIFrqDiv is
constant SPPRWidth : integer range 1 to 8 := 3;
constant SPRWidth : integer range 1 to 8 := 3;
-- Component Declaration for the Unit Under Test (UUT)
component SPIFrqDiv is
Generic (
SPPRWidth : integer range 1 to 8 := 3;
SPRWidth : integer range 1 to 8... |
entity test is
type test1 is (foo, bar);
type test2 is (foo, baz);
begin end;
|
--###############################
--# Project Name :
--# File :
--# Author :
--# Description :
--# Modification History
--#
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_MPU6050 is
end tb_MPU6050;
architecture stimulus of tb_MPU605... |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / ... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_modulator/hdl_modulator_sin_hdl.vhd
-- Created: 2018-02-27 13:25:15
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- --------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:08:51 06/04/2016
-- Design Name:
-- Module Name: Mux4to1_8bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... |
-- file: clk_base.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a... |
-- file: clk_base.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a... |
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: PC.vhd
-- // Date: 12/9/2004
-- // Description: Program Counter
-- // Class: CSE 378
-- ===================================================... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity regfile is
generic (N : integer := 3;
M : integer := 16);
port (readaddr1, readaddr2 : in std_logic_vector (N - 1 downto 0);
writeaddr : in std_logic_vector (N - 1 downto 0);
data : in std_logic_vector (M - 1 downto 0);
write, clk : ... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_INST_mb.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =======================... |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_INST_mb.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- =======================... |
-------------------------------------------------------------------------------
--! @project Unrolled (2) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may... |
-- ********************
-- * Flip Flop tipo D *
-- ********************
-- Con reinicio asíncrono
library ieee; use ieee.std_logic_1164.all;
entity ffdr is
port(
clk: in std_logic; -- Reloj
rst: in std_logic; -- Reinicio
d: in std_logic;
q: out std_logic
);
end ffdr;
architectu... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** *... |
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