content stringlengths 1 1.04M ⌀ |
|---|
--/////////////////////////////////////////////////IIR_Biquad////////////////////////////////////////////////////////////
-- FileName: IIR_Biquad_II_v3.vhd
-- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at:
-- https://eewiki.net/display/LOGIC/IIR+F... |
--/////////////////////////////////////////////////IIR_Biquad////////////////////////////////////////////////////////////
-- FileName: IIR_Biquad_II_v3.vhd
-- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at:
-- https://eewiki.net/display/LOGIC/IIR+F... |
component pr_region_default_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X'; -- reset_req
address : in std... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity wb_spimaster is
generic (
dat_sz : natural := 8;
slv_bits: natural := 3
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
--
-- Whishbone Interface
--
adr_i : in std_logic_vector(1 downto 0);
dat_... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity wb_spimaster is
generic (
dat_sz : natural := 8;
slv_bits: natural := 3
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
--
-- Whishbone Interface
--
adr_i : in std_logic_vector(1 downto 0);
dat_... |
-----Library statements -----
library ieee;
use ieee.std_logic_1164.all;
-----Entity declaration -----
entity GuessGame is
port(
inputs : in std_logic_vector(7 downto 0);
set : in std_logic; -- set predefined value
show : in std_logic; -- Show predefined value
try : in std_logic; -- Evaluate guess
hex1 : out ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library verilog;
use verilog.vl_types.all;
entity Counter16anDisplay_vlg_sample_tst is
port(
clear : in vl_logic;
clk : in vl_logic;
enable : in vl_logic;
sampler_tx : out vl_logic
);
end Counter16anDisplay_vlg_sample_tst;
|
package pkg3 is
type my_rec is record
adr : bit_vector (7 downto 0);
end record;
end pkg3;
use work.pkg3.all;
entity ent3 is
port (v : out my_rec;
b : in bit);
end ent3;
architecture behav of ent3 is
begin
v.adr <= (others => b);
end behav;
entity top3 is
end top3;
use work.pkg3.all;
architectu... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
port ( input_1 : in std_logic_vector (31 downto 0);
input_2 : in std_logic_vector (31 downto 0);
funct : in std_logic_vector (4 downto 0);
flags_current : in std_logic_vector(3 downto 0);
o... |
library ieee;
use ieee.std_logic_1164.all;
use work.cryptopan.all;
entity sbsr_tb is
end sbsr_tb;
architecture tb of sbsr_tb is
component subbytesshiftrows
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
clk : in std_logic;
reset : in std_logic);
end com... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:07:54 09/29/2014
-- Design Name:
-- Module Name: C:/Users/ael10jso/Xilinx/embedded_bruteforce/brutus_system/ISE/fsl_test/tb_fsl_test.vhd
-- Project Name: fsl_test
-- Target Device:
... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TrafficLightsTop is
port(CLOCK_50 : in std_logic;
KEY : in std_logic_vector(0 downto 0);
SW : in std_logic_vector(0 downto 0);
LEDR : out std_logic_vector(17 downto 0));
end TrafficLightsTop;
architecture Shell of TrafficLightsTop is
signal s_cl... |
-- fft16.vhd
--
-- Created on: 15 Jul 2017
-- Author: Fabian Meyer
--
-- Integration component for 16-point FFT. Implements pipelining of data and timing between components.
-- This architecture is based on the paper of George Slade:
-- https://www.researchgate.net/publication/235995761_The_Fast_Fourier_Transform_i... |
---------------------------------------------------------------------
-- Optimized multiplier
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- This multiplier is designed for technologies that don't provide
-- fast 16x16 multipliers. One multiplication takes 6 cycles.
--
-- The multiplica... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.st... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity Zone is
Generic (
nb_bits_Zone : natural := 8; -- 2^8 = 256 zones differentes possibles
nb_bits_AdrPixel : natural := 9 -- coordonnees de la souris (X,Y) sur 9 bits
);
Port (
clk : in STD_LOGI... |
-- This is multi-stage shift register designed to limit fanout
-- There is at least one register, there may be more depending on wanted fanout
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity distribuf is
generic(
WDATA : natural := 20;
NBOUT : natural := 20;
FANOUT : natural := 2... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex5_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex5_hot;
architecture behaviour of ex5_hot is
constant s1: std_logic_vector(8 downto 0) := "1000... |
------------------------------------------------------------------------------
-- @file <Name of the file>
-- @brief <TO ADD>
-- @details <TO ADD>
-- @see <TESTBENCH>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity <MODULE_NAME> is
... |
-- VHDL Entity My_Lib.interceptor.symbol
--
-- Created:
-- by - mg55.bin (srge02.ecn.purdue.edu)
-- at - 14:37:58 04/21/12
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2010.2a (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY interceptor IS
PORT( ... |
package attributes_pkg is
attribute period :time;
end package;
library work;
use work.attributes_pkg.period;
entity inner is
port(
signal clk :in bit
);
end entity;
architecture arch of inner is
constant CLK_PERIOD :time := clk'period;
begin
end architecture;
library work;
use work.attributes_pkg.period;
enti... |
package attributes_pkg is
attribute period :time;
end package;
library work;
use work.attributes_pkg.period;
entity inner is
port(
signal clk :in bit
);
end entity;
architecture arch of inner is
constant CLK_PERIOD :time := clk'period;
begin
end architecture;
library work;
use work.attributes_pkg.period;
enti... |
package attributes_pkg is
attribute period :time;
end package;
library work;
use work.attributes_pkg.period;
entity inner is
port(
signal clk :in bit
);
end entity;
architecture arch of inner is
constant CLK_PERIOD :time := clk'period;
begin
end architecture;
library work;
use work.attributes_pkg.period;
enti... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer modul... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer modul... |
entity tb_ent1 is
end tb_ent1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent1 is
signal clk : std_logic;
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.ent1
port map (clk => clk, o => dout);
process
procedure pulse is
begin
clk <= '0';
wa... |
library ieee;
use ieee.std_logic_1164.all;
entity device_ram_blocks is
generic ( INTENDED_DEVICE_FAMILY : string := "SmartFusion"; -- or "ZynqSoC"
WIDTH_AD : natural := 10; -- WIDTH_RDAD = WIDTH_WRAD
WIDTH_DATA : natural := 66; -- WIDTH_DATAIN = WIDTH_DATAOU... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Wed Oct 25 12:44:01 2017
-- Host : vldmr-PC running 64-bit Service ... |
entity e is
end entity;
architecture a of e is
signal x : integer := -3 * 4 + 2;
type t is range -5 to 11 - 3;
constant c : integer := +4 + 1;
signal y : t;
type int_array is array (integer range <>) of integer;
constant a1 : int_array(1 to 5) := (1, 2, 3, 4, 5);
constant a2 : int_array(1 t... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Button Press Synchronizer para keys que são ativas baixas (ou seja, quando pressionadas vao para nivel baixo)
library ieee;
use ieee.std_logic_1164.all;
entity ButtonSync is
port
(
-- Input ports
key0 : in std_logic;
key1 : in std_logic;
key2 : in std_logic;
key3 : in std_logic;
clk : in std_lo... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Me... |
--
-- This file is part of giovanni_card
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either versio... |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
i_wr_en : in std_logic;
i_data : out std_logic_vector(31 downto 0);
i_rd_en : ... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
-- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.15:50:58
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is
port (
sop : in std_logic ... |
-- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.15:50:58
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is
port (
sop : in std_logic ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.01.2016 17:22:42
-- Design Name:
-- Module Name: serialLoader - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00335
--
-- AUTHOR:
--
-- A. Wilm... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--pragma translate off
--vhdl_comp_off
/*
--vhdl_comp_on
library aldec;
use aldec.matlab.all;
--vhdl_comp_off
*/
--vhdl_comp_on
--pragma translate on
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use std.textio.all;
library work;
use work.fixed_float_types... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity ps_converter_tb is
end ps_converter_tb;
architecture tb of ps_converter_tb is
-- interface signals
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal clk_en : std_logic := '0';
signal start :... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
package cmos_sensor_output_generator_constants is
constant CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH : positive := 32;
-- register offsets
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST : std_logic_vector(2 downto 0... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_cycle_sequence is
constant assert_name : string := "OVL_CYCLE_SEQUENCE";
... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY KCVGA IS PORT
(
pin_nRESET : IN STD_LOGIC;
pin_CLK : IN STD_LOGIC;
pin_PIC32_DATA : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
pin_PIC32_ADDRESS : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
pin_PIC32_nWR : IN STD_LOGIC;
pin_PIC32_nRD : IN STD_LOG... |
-------------------------------------------------------------------------------
--
-- Title : regfile_decode
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_... |
-- File: gray_counter_24.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_24 is
port (
gray_count: out unsigned(23 downto 0);
enable: in std_l... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Pdashofkplusone is
port (
clock : in std_logic;
Vsigactofkofzero : in std_logic_vector(31 downto 0);
Vsigactofkofone : in std_logic_vector(31 downto 0);
Vsigactofkoftwo ... |
-- $Id: sys_w11a_b3.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_b3 - syn
-- Description: w11a tes... |
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\s... |
architecture rtl of fifo is
variable sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0)
,
elementB(3 downto 0)
),
element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),
element5(
elementE
(3 downto
... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
entity test is
package a is new b generic map(c => foo(open, open));
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
end ent;
architecture a of ent is
constant c : std_logic_vector(7 downto 0) := x"00";
begin
process(all)
begin
case c is
when others =>
end case;
end process;
end a;
|
--===========================================================================--
-- --
-- keyboard.vhd - Synthesizable Interface to PS/2 Keyboard Module --
-- --
... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity LUTRAM is
generic
(
B : NATURAL := 8; -- Address Bus width
W : NATURAL := 2 -- Data Bus width
);
port
(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
... |
--------------------------------------------------------------------------------
-- company:
-- engineer:
--
-- vhdl test bench created by ise for module: random_number
--
-- dependencies:
--
-- revision:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_lo... |
package uart_constants is
constant baud_rate : integer := 115200;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity sub is
port (
clk : out std_logic;
cnt : inout integer );
end entity;
architecture test of sub is
signal clk_i : bit := '0';
signal clk_std : std_logic;
begin
clk_i <= not clk_i after 1 ns;
clk_std <= to_stdulogic(clk_i);
c... |
library ieee;
use ieee.std_logic_1164.all;
entity sub is
port (
clk : out std_logic;
cnt : inout integer );
end entity;
architecture test of sub is
signal clk_i : bit := '0';
signal clk_std : std_logic;
begin
clk_i <= not clk_i after 1 ns;
clk_std <= to_stdulogic(clk_i);
c... |
library ieee;
use ieee.std_logic_1164.all;
entity sub is
port (
clk : out std_logic;
cnt : inout integer );
end entity;
architecture test of sub is
signal clk_i : bit := '0';
signal clk_std : std_logic;
begin
clk_i <= not clk_i after 1 ns;
clk_std <= to_stdulogic(clk_i);
c... |
library ieee;
use ieee.std_logic_1164.all;
entity sub is
port (
clk : out std_logic;
cnt : inout integer );
end entity;
architecture test of sub is
signal clk_i : bit := '0';
signal clk_std : std_logic;
begin
clk_i <= not clk_i after 1 ns;
clk_std <= to_stdulogic(clk_i);
c... |
-------------------------------------------------------------------------------
-- Title : Servo Module
-------------------------------------------------------------------------------
-- File : servo_module.vhd
-- Author : Fabian <fabian@kleinvieh>
-- Standard : VHDL'87
--------------------------------... |
-------------------------------------------------------------------------------
-- Title : Servo Module
-------------------------------------------------------------------------------
-- File : servo_module.vhd
-- Author : Fabian <fabian@kleinvieh>
-- Standard : VHDL'87
--------------------------------... |
---------------------------------------------------------------------
---- 4digit.vhdl ----
---- ----
---- Drives 4-digit seven segment display.
---- ck should be 100Hz to 1KHz
----
----------------------------... |
-------------------------------------------------------------------------------
-- lite_ecc_reg.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-... |
-------------------------------------------------------------------------------
-- lite_ecc_reg.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-... |
-------------------------------------------------------------------------------
-- lite_ecc_reg.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-... |
-------------------------------------------------------------------------------
-- lite_ecc_reg.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-... |
-------------------------------------------------------------------------------
-- lite_ecc_reg.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-... |
-------------------------------------------------------------------------------
-- lite_ecc_reg.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-... |
-------------------------------------------------------------------------------
-- lite_ecc_reg.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-... |
library verilog;
use verilog.vl_types.all;
entity ln_x_controller is
generic(
RAEDY : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
\INIT\ : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1);
CALC_POW : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0);
CALC_SUM... |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Syndrome_Calculator_N_Pipe
-- Module Name: Syndrome_Calculator_N_Pipe
-- Projec... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
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