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--/////////////////////////////////////////////////IIR_Biquad//////////////////////////////////////////////////////////// -- FileName: IIR_Biquad_II_v3.vhd -- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at: -- https://eewiki.net/display/LOGIC/IIR+Filter+Design+in+VHDL+Targeted+for+18-Bit,+48+KHz+Audio+Signal+Use#IIRFilterDesigninVHDLTargetedfor18-Bit,48KHzAudioSignalUse-InstantiatingtheIIR_Biquad.vhdFilterModule -- Credit must be given to Tony Storey of DIGI-KEY for providing the original code upon which this version has been created from. -- -- Original Version History -- Version 1.0 7/31/2012 Tony Storey -- Initial Public Releaselibrary ieee; -- -- Current Version History -- Version 3.0 27/05/2015 Ovie, Tsotne, Juri, and Silvester. -- -- A lot of changes and updates have been made to this version. This version uses a single "shift add" multiplier instead of five DSP multipliers. -- This version has a reduced area size due to the scheduling and sharing of resource, but with a trade off of time. -- -- -- IIR_Biquad_II_v3.vhd IS PROVIDED "AS IS." WE EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL WE -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- WE ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT -- INFRINGEMENT. -- --/////////////////////////////////Recommendations on how to use this component./////////////////////////////////////////// -- The current configuration has coefficient width of 32 bits and sample data width of 32 bits (24 bits but padded with zeros) -- , it takes approximately 350 clock circles to perform a -- single filter operation. With this configuration the approximate minimum frequency of operation of the filter should be -- 16.8Mhz --///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity IIR_Biquad_II_v3 is port( Coef_b0 : std_logic_vector(31 downto 0); Coef_b1 : std_logic_vector(31 downto 0); Coef_b2 : std_logic_vector(31 downto 0); Coef_a1 : std_logic_vector(31 downto 0); Coef_a2 : std_logic_vector(31 downto 0); clk : in STD_LOGIC; rst : in STD_LOGIC; sample_trig : in STD_LOGIC; X_in : in STD_LOGIC_VECTOR(23 downto 0); filter_done : out STD_LOGIC; Y_out : out STD_LOGIC_VECTOR(23 downto 0) ); end IIR_Biquad_II_v3; architecture arch of IIR_Biquad_II_v3 is signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0'); -- define each post gain 64 bit sample signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : signed(63 downto 0) := (others => '0'); signal mul_result : signed(63 downto 0) := (others => '0'); -- define each post gain 32 but truncated sample signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0'); -- define output double reg signal Y_out_double : std_logic_vector(31 downto 0) := (others => '0'); -- state machine signals type state_type is (idle, run); signal state_reg, state_next : state_type; -- counter signals signal q_reg, q_next : unsigned(2 downto 0); signal q_reset, q_add : std_logic; signal counter : integer := 1; signal rst_cnt, s_trigger, s_multiply : std_logic; constant shiftAddMultiply : boolean := true; -- constant DSPMultiply : boolean := false; signal mul_coefs, trunc_prods, sum_stg_a, trunc_out, Mul_stage_over, Mul_Ready : std_logic; signal ZFF, Coef : std_logic_vector(31 downto 0) := (others => '0'); begin -- process to shift samples process(clk) begin if (rising_edge(clk)) then if (rst = '1') then ZFF_X0 <= (others => '0'); ZFF_X1 <= (others => '0'); ZFF_X2 <= (others => '0'); ZFF_Y1 <= (others => '0'); ZFF_Y2 <= (others => '0'); else if (sample_trig = '1' and state_reg = idle) then ZFF_X0 <= X_in(23) & X_in(23) & X_in & B"0000_00"; ZFF_X1 <= ZFF_X0; ZFF_X2 <= ZFF_X1; ZFF_Y1 <= Y_out_double; ZFF_Y2 <= ZFF_Y1; end if; end if; end if; end process; -- STATE UPDATE AND TIMING process(clk) begin if (rising_edge(clk)) then if (rst = '1') then state_reg <= idle; q_reg <= (others => '0'); -- reset counter else state_reg <= state_next; -- update the state q_reg <= q_next; end if; end if; end process; -- COUNTER FOR TIMING q_next <= (others => '0') when q_reset = '1' else -- resets the counter q_reg + 2 when q_add = '1' and q_reg = 1 else q_reg + 1 when q_add = '1' else -- increment count if commanded q_reg; -- process for control of data path flags process(q_reg, state_reg, sample_trig, Mul_stage_over) begin -- defaults q_reset <= '0'; q_add <= '0'; mul_coefs <= '0'; trunc_prods <= '0'; sum_stg_a <= '0'; trunc_out <= '0'; filter_done <= '0'; rst_cnt <= '1'; case state_reg is when idle => if (sample_trig = '1') then state_next <= run; else state_next <= idle; end if; when run => if (q_reg < B"001") then q_add <= '1'; state_next <= run; elsif (q_reg < "011") then rst_cnt <= '0'; -- allow counter to run so that it can count how many multiplication has been performed. mul_coefs <= '1'; q_add <= '0'; -- seize the counter from counting until if Mul_stage_over = '1' then -- multiplication is done. q_add <= '1'; end if; state_next <= run; elsif (q_reg < "100") then trunc_prods <= '1'; q_add <= '1'; state_next <= run; elsif (q_reg < "101") then sum_stg_a <= '1'; q_add <= '1'; state_next <= run; elsif (q_reg < "110") then trunc_out <= '1'; q_add <= '1'; state_next <= run; else q_reset <= '1'; filter_done <= '1'; state_next <= idle; end if; end case; end process; --Mul_Ready<= Mul_Ready1 and Mul_Ready2 and Mul_Ready3 and Mul_Ready4 and Mul_Ready5; mul : entity work.multiplier generic map( MultiplierIsShiftAdd => shiftAddMultiply, --DSPMultiply,-- BIT_WIDTH => 32, COUNT_WIDTH => 6) port map(CLK => clk, TRIGGER => s_multiply, A => signed(Coef), B => signed(ZFF), RES => mul_result, READY => Mul_Ready); s_multiply <= mul_coefs and s_trigger; Count_Multiplication : process(rst_cnt, Mul_Ready, rst) begin --if rising_edge(clk) then if rst_cnt = '1' or rst = '1' then counter <= 0; elsif rising_edge(Mul_Ready) then if mul_coefs = '1' then counter <= counter + 1; end if; end if; --end if; end process; --Mul_stage_over <= '1' when counter = 5 else '0'; Stage_input_values_for_multiplier : process(counter, Coef_b0, Coef_b1, Coef_b2, Coef_a1, Coef_a2, ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2) begin case counter is when 0 => Coef <= Coef_b0; ZFF <= ZFF_X0; when 1 => Coef <= Coef_b1; ZFF <= ZFF_X1; when 2 => Coef <= Coef_b2; ZFF <= ZFF_X2; when 3 => Coef <= Coef_a1; ZFF <= ZFF_Y1; when 4 => Coef <= Coef_a2; ZFF <= ZFF_Y2; when others => Coef <= (others => '0'); ZFF <= (others => '0'); end case; end process; Stage_Multiplication_Result : process(clk) begin if rising_edge(clk) then if rst = '1' then pgZFF_X0_quad <= (others => '0'); pgZFF_X1_quad <= (others => '0'); pgZFF_X2_quad <= (others => '0'); pgZFF_Y1_quad <= (others => '0'); pgZFF_Y2_quad <= (others => '0'); s_trigger <= '1'; else s_trigger <= '1'; Mul_stage_over <= '0'; case counter is when 1 => if Mul_Ready = '1' then pgZFF_X0_quad <= mul_result; s_trigger <= '0'; end if; when 2 => if Mul_Ready = '1' then pgZFF_X1_quad <= mul_result; s_trigger <= '0'; end if; when 3 => if Mul_Ready = '1' then pgZFF_X2_quad <= mul_result; s_trigger <= '0'; end if; when 4 => if Mul_Ready = '1' then pgZFF_Y1_quad <= mul_result; s_trigger <= '0'; end if; when 5 => if Mul_Ready = '1' then pgZFF_Y2_quad <= mul_result; --s_trigger <= '0'; Mul_stage_over <= '1'; end if; when others => -- pgZFF_X0_quad <= (others => '0'); -- pgZFF_X1_quad <= (others => '0'); -- pgZFF_X2_quad <= (others => '0'); -- pgZFF_Y1_quad <= (others => '0'); -- pgZFF_Y2_quad <= (others => '0'); end case; end if; end if; end process; -- truncate the output to summation block process(clk) begin if rising_edge(clk) then if (trunc_prods = '1') then pgZFF_X0 <= std_logic_vector(pgZFF_X0_quad(61 downto 30)); pgZFF_X2 <= std_logic_vector(pgZFF_X2_quad(61 downto 30)); pgZFF_X1 <= std_logic_vector(pgZFF_X1_quad(61 downto 30)); pgZFF_Y1 <= std_logic_vector(pgZFF_Y1_quad(61 downto 30)); pgZFF_Y2 <= std_logic_vector(pgZFF_Y2_quad(61 downto 30)); end if; end if; end process; -- sum all post gain feedback and feedfoward paths -- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2 process(clk) begin if (rising_edge(clk)) then if (sum_stg_a = '1') then Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2)); end if; end if; end process; -- output truncation block process(clk) begin if rising_edge(clk) then if (trunc_out = '1') then Y_out <= Y_out_double(30 downto 7); end if; end if; end process; end arch;
--/////////////////////////////////////////////////IIR_Biquad//////////////////////////////////////////////////////////// -- FileName: IIR_Biquad_II_v3.vhd -- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at: -- https://eewiki.net/display/LOGIC/IIR+Filter+Design+in+VHDL+Targeted+for+18-Bit,+48+KHz+Audio+Signal+Use#IIRFilterDesigninVHDLTargetedfor18-Bit,48KHzAudioSignalUse-InstantiatingtheIIR_Biquad.vhdFilterModule -- Credit must be given to Tony Storey of DIGI-KEY for providing the original code upon which this version has been created from. -- -- Original Version History -- Version 1.0 7/31/2012 Tony Storey -- Initial Public Releaselibrary ieee; -- -- Current Version History -- Version 3.0 27/05/2015 Ovie, Tsotne, Juri, and Silvester. -- -- A lot of changes and updates have been made to this version. This version uses a single "shift add" multiplier instead of five DSP multipliers. -- This version has a reduced area size due to the scheduling and sharing of resource, but with a trade off of time. -- -- -- IIR_Biquad_II_v3.vhd IS PROVIDED "AS IS." WE EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL WE -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- WE ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT -- INFRINGEMENT. -- --/////////////////////////////////Recommendations on how to use this component./////////////////////////////////////////// -- The current configuration has coefficient width of 32 bits and sample data width of 32 bits (24 bits but padded with zeros) -- , it takes approximately 350 clock circles to perform a -- single filter operation. With this configuration the approximate minimum frequency of operation of the filter should be -- 16.8Mhz --///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity IIR_Biquad_II_v3 is port( Coef_b0 : std_logic_vector(31 downto 0); Coef_b1 : std_logic_vector(31 downto 0); Coef_b2 : std_logic_vector(31 downto 0); Coef_a1 : std_logic_vector(31 downto 0); Coef_a2 : std_logic_vector(31 downto 0); clk : in STD_LOGIC; rst : in STD_LOGIC; sample_trig : in STD_LOGIC; X_in : in STD_LOGIC_VECTOR(23 downto 0); filter_done : out STD_LOGIC; Y_out : out STD_LOGIC_VECTOR(23 downto 0) ); end IIR_Biquad_II_v3; architecture arch of IIR_Biquad_II_v3 is signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0'); -- define each post gain 64 bit sample signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : signed(63 downto 0) := (others => '0'); signal mul_result : signed(63 downto 0) := (others => '0'); -- define each post gain 32 but truncated sample signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0'); -- define output double reg signal Y_out_double : std_logic_vector(31 downto 0) := (others => '0'); -- state machine signals type state_type is (idle, run); signal state_reg, state_next : state_type; -- counter signals signal q_reg, q_next : unsigned(2 downto 0); signal q_reset, q_add : std_logic; signal counter : integer := 1; signal rst_cnt, s_trigger, s_multiply : std_logic; constant shiftAddMultiply : boolean := true; -- constant DSPMultiply : boolean := false; signal mul_coefs, trunc_prods, sum_stg_a, trunc_out, Mul_stage_over, Mul_Ready : std_logic; signal ZFF, Coef : std_logic_vector(31 downto 0) := (others => '0'); begin -- process to shift samples process(clk) begin if (rising_edge(clk)) then if (rst = '1') then ZFF_X0 <= (others => '0'); ZFF_X1 <= (others => '0'); ZFF_X2 <= (others => '0'); ZFF_Y1 <= (others => '0'); ZFF_Y2 <= (others => '0'); else if (sample_trig = '1' and state_reg = idle) then ZFF_X0 <= X_in(23) & X_in(23) & X_in & B"0000_00"; ZFF_X1 <= ZFF_X0; ZFF_X2 <= ZFF_X1; ZFF_Y1 <= Y_out_double; ZFF_Y2 <= ZFF_Y1; end if; end if; end if; end process; -- STATE UPDATE AND TIMING process(clk) begin if (rising_edge(clk)) then if (rst = '1') then state_reg <= idle; q_reg <= (others => '0'); -- reset counter else state_reg <= state_next; -- update the state q_reg <= q_next; end if; end if; end process; -- COUNTER FOR TIMING q_next <= (others => '0') when q_reset = '1' else -- resets the counter q_reg + 2 when q_add = '1' and q_reg = 1 else q_reg + 1 when q_add = '1' else -- increment count if commanded q_reg; -- process for control of data path flags process(q_reg, state_reg, sample_trig, Mul_stage_over) begin -- defaults q_reset <= '0'; q_add <= '0'; mul_coefs <= '0'; trunc_prods <= '0'; sum_stg_a <= '0'; trunc_out <= '0'; filter_done <= '0'; rst_cnt <= '1'; case state_reg is when idle => if (sample_trig = '1') then state_next <= run; else state_next <= idle; end if; when run => if (q_reg < B"001") then q_add <= '1'; state_next <= run; elsif (q_reg < "011") then rst_cnt <= '0'; -- allow counter to run so that it can count how many multiplication has been performed. mul_coefs <= '1'; q_add <= '0'; -- seize the counter from counting until if Mul_stage_over = '1' then -- multiplication is done. q_add <= '1'; end if; state_next <= run; elsif (q_reg < "100") then trunc_prods <= '1'; q_add <= '1'; state_next <= run; elsif (q_reg < "101") then sum_stg_a <= '1'; q_add <= '1'; state_next <= run; elsif (q_reg < "110") then trunc_out <= '1'; q_add <= '1'; state_next <= run; else q_reset <= '1'; filter_done <= '1'; state_next <= idle; end if; end case; end process; --Mul_Ready<= Mul_Ready1 and Mul_Ready2 and Mul_Ready3 and Mul_Ready4 and Mul_Ready5; mul : entity work.multiplier generic map( MultiplierIsShiftAdd => shiftAddMultiply, --DSPMultiply,-- BIT_WIDTH => 32, COUNT_WIDTH => 6) port map(CLK => clk, TRIGGER => s_multiply, A => signed(Coef), B => signed(ZFF), RES => mul_result, READY => Mul_Ready); s_multiply <= mul_coefs and s_trigger; Count_Multiplication : process(rst_cnt, Mul_Ready, rst) begin --if rising_edge(clk) then if rst_cnt = '1' or rst = '1' then counter <= 0; elsif rising_edge(Mul_Ready) then if mul_coefs = '1' then counter <= counter + 1; end if; end if; --end if; end process; --Mul_stage_over <= '1' when counter = 5 else '0'; Stage_input_values_for_multiplier : process(counter, Coef_b0, Coef_b1, Coef_b2, Coef_a1, Coef_a2, ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2) begin case counter is when 0 => Coef <= Coef_b0; ZFF <= ZFF_X0; when 1 => Coef <= Coef_b1; ZFF <= ZFF_X1; when 2 => Coef <= Coef_b2; ZFF <= ZFF_X2; when 3 => Coef <= Coef_a1; ZFF <= ZFF_Y1; when 4 => Coef <= Coef_a2; ZFF <= ZFF_Y2; when others => Coef <= (others => '0'); ZFF <= (others => '0'); end case; end process; Stage_Multiplication_Result : process(clk) begin if rising_edge(clk) then if rst = '1' then pgZFF_X0_quad <= (others => '0'); pgZFF_X1_quad <= (others => '0'); pgZFF_X2_quad <= (others => '0'); pgZFF_Y1_quad <= (others => '0'); pgZFF_Y2_quad <= (others => '0'); s_trigger <= '1'; else s_trigger <= '1'; Mul_stage_over <= '0'; case counter is when 1 => if Mul_Ready = '1' then pgZFF_X0_quad <= mul_result; s_trigger <= '0'; end if; when 2 => if Mul_Ready = '1' then pgZFF_X1_quad <= mul_result; s_trigger <= '0'; end if; when 3 => if Mul_Ready = '1' then pgZFF_X2_quad <= mul_result; s_trigger <= '0'; end if; when 4 => if Mul_Ready = '1' then pgZFF_Y1_quad <= mul_result; s_trigger <= '0'; end if; when 5 => if Mul_Ready = '1' then pgZFF_Y2_quad <= mul_result; --s_trigger <= '0'; Mul_stage_over <= '1'; end if; when others => -- pgZFF_X0_quad <= (others => '0'); -- pgZFF_X1_quad <= (others => '0'); -- pgZFF_X2_quad <= (others => '0'); -- pgZFF_Y1_quad <= (others => '0'); -- pgZFF_Y2_quad <= (others => '0'); end case; end if; end if; end process; -- truncate the output to summation block process(clk) begin if rising_edge(clk) then if (trunc_prods = '1') then pgZFF_X0 <= std_logic_vector(pgZFF_X0_quad(61 downto 30)); pgZFF_X2 <= std_logic_vector(pgZFF_X2_quad(61 downto 30)); pgZFF_X1 <= std_logic_vector(pgZFF_X1_quad(61 downto 30)); pgZFF_Y1 <= std_logic_vector(pgZFF_Y1_quad(61 downto 30)); pgZFF_Y2 <= std_logic_vector(pgZFF_Y2_quad(61 downto 30)); end if; end if; end process; -- sum all post gain feedback and feedfoward paths -- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2 process(clk) begin if (rising_edge(clk)) then if (sum_stg_a = '1') then Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2)); end if; end if; end process; -- output truncation block process(clk) begin if rising_edge(clk) then if (trunc_out = '1') then Y_out <= Y_out_double(30 downto 7); end if; end if; end process; end arch;
component pr_region_default_onchip_memory2_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset reset_req : in std_logic := 'X'; -- reset_req address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address clken : in std_logic := 'X'; -- clken chipselect : in std_logic := 'X'; -- chipselect write : in std_logic := 'X'; -- write readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable ); end component pr_region_default_onchip_memory2_0; u0 : component pr_region_default_onchip_memory2_0 port map ( clk => CONNECTED_TO_clk, -- clk1.clk reset => CONNECTED_TO_reset, -- reset1.reset reset_req => CONNECTED_TO_reset_req, -- .reset_req address => CONNECTED_TO_address, -- s1.address clken => CONNECTED_TO_clken, -- .clken chipselect => CONNECTED_TO_chipselect, -- .chipselect write => CONNECTED_TO_write, -- .write readdata => CONNECTED_TO_readdata, -- .readdata writedata => CONNECTED_TO_writedata, -- .writedata byteenable => CONNECTED_TO_byteenable -- .byteenable );
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2012.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b02x00p10n01i02012ent IS END c07s02b02x00p10n01i02012ent; ARCHITECTURE c07s02b02x00p10n01i02012arch OF c07s02b02x00p10n01i02012ent IS SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE) SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index SUBTYPE st_scl1 IS CHARACTER ; SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH; TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1; TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3; SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 ); SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 ); CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ; CONSTANT C2_scl1 : st_scl1 := 'Z' ; CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ; CONSTANT C2_scl3 : st_scl3 := 8 ; CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1); CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1, OTHERS =>C0_scl1); CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3); CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3, OTHERS =>C0_scl3); BEGIN TESTING: PROCESS -- -- Constant declarations - for unconstrained types -- other composite type declarations are in package "COMPOSITE" -- CONSTANT C0_usa1_1 : t_usa1_1 (st_ind1 ) := C0_csa1_1; CONSTANT C0_usa1_3 : t_usa1_3 (st_ind3 ) := C0_csa1_3; CONSTANT C2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1; CONSTANT C2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3; -- -- Composite VARIABLE declarations -- VARIABLE V0_usa1_1 : t_usa1_1 (st_ind1 ) ; VARIABLE V0_usa1_3 : t_usa1_3 (st_ind3 ) ; VARIABLE V0_csa1_1 : t_csa1_1 ; VARIABLE V0_csa1_3 : t_csa1_3 ; VARIABLE V2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1; VARIABLE V2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3; VARIABLE V2_csa1_1 : t_csa1_1 := C2_csa1_1; VARIABLE V2_csa1_3 : t_csa1_3 := C2_csa1_3; -- -- Arrays of the same type, element values, different length -- VARIABLE V3_usa1_1 : t_usa1_1 ( 1 TO 7 ) ; VARIABLE V3_usa1_3 : t_usa1_3 ('a' TO 'c' ) ; -- CONSTANT msg1 : STRING := "ERROR: less than operator failure: "; CONSTANT msg2 : STRING := "ERROR: less than or equal operator failure: "; BEGIN -- -- Check less than operator - CONSTANTS (from package 'composite') -- ASSERT C0_usa1_1 < C2_usa1_1 REPORT msg1 & "C0<C2_usa1_1" SEVERITY FAILURE; ASSERT C0_usa1_3 < C2_usa1_3 REPORT msg1 & "C0<C2_usa1_3" SEVERITY FAILURE; ASSERT C0_csa1_1 < C2_csa1_1 REPORT msg1 & "C0<C2_csa1_1" SEVERITY FAILURE; ASSERT C0_csa1_3 < C2_csa1_3 REPORT msg1 & "C0<C2_csa1_3" SEVERITY FAILURE; -- -- Check less than operator - VARIABLES -- ASSERT V0_usa1_1 < V2_usa1_1 REPORT msg1 & "V0<V2_usa1_1" SEVERITY FAILURE; ASSERT V0_usa1_3 < V2_usa1_3 REPORT msg1 & "V0<V2_usa1_3" SEVERITY FAILURE; ASSERT V0_csa1_1 < V2_csa1_1 REPORT msg1 & "V0<V2_csa1_1" SEVERITY FAILURE; ASSERT V0_csa1_3 < V2_csa1_3 REPORT msg1 & "V0<V2_csa1_3" SEVERITY FAILURE; -- -- Check less than operator - VARIABLES and CONSTANTS -- ASSERT V0_usa1_1 < C2_usa1_1 REPORT msg1 & "V0<C2_usa1_1" SEVERITY FAILURE; ASSERT V0_usa1_3 < C2_usa1_3 REPORT msg1 & "V0<C2_usa1_3" SEVERITY FAILURE; ASSERT V0_csa1_1 < C2_csa1_1 REPORT msg1 & "V0<C2_csa1_1" SEVERITY FAILURE; ASSERT V0_csa1_3 < C2_csa1_3 REPORT msg1 & "V0<C2_csa1_3" SEVERITY FAILURE; -- -- Check less than operator - same type, element values : diff array length -- ASSERT V3_usa1_1 < V2_usa1_1 REPORT msg1 & "V3<V2_usa1_1" SEVERITY FAILURE; ASSERT V3_usa1_3 < V2_usa1_3 REPORT msg1 & "V3<V2_usa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - CONSTANTS (from package 'composite') -- ASSERT C0_usa1_1 <= C2_usa1_1 REPORT msg2 & "C0<=C2_usa1_1" SEVERITY FAILURE; ASSERT C0_usa1_3 <= C2_usa1_3 REPORT msg2 & "C0<=C2_usa1_3" SEVERITY FAILURE; ASSERT C0_csa1_1 <= C2_csa1_1 REPORT msg2 & "C0<=C2_csa1_1" SEVERITY FAILURE; ASSERT C0_csa1_3 <= C2_csa1_3 REPORT msg2 & "C0<=C2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - VARIABLES -- ASSERT V0_usa1_1 <= V2_usa1_1 REPORT msg2 & "V0<=V2_usa1_1" SEVERITY FAILURE; ASSERT V0_usa1_3 <= V2_usa1_3 REPORT msg2 & "V0<=V2_usa1_3" SEVERITY FAILURE; ASSERT V0_csa1_1 <= V2_csa1_1 REPORT msg2 & "V0<=V2_csa1_1" SEVERITY FAILURE; ASSERT V0_csa1_3 <= V2_csa1_3 REPORT msg2 & "V0<=V2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - VARIABLES and CONSTANTS -- ASSERT V0_usa1_1 <= C2_usa1_1 REPORT msg2 & "V0<=C2_usa1_1" SEVERITY FAILURE; ASSERT V0_usa1_3 <= C2_usa1_3 REPORT msg2 & "V0<=C2_usa1_3" SEVERITY FAILURE; ASSERT V0_csa1_1 <= C2_csa1_1 REPORT msg2 & "V0<=C2_csa1_1" SEVERITY FAILURE; ASSERT V0_csa1_3 <= C2_csa1_3 REPORT msg2 & "V0<=C2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - same type, element values : diff array length -- ASSERT V3_usa1_1 <= V2_usa1_1 REPORT msg2 & "V3<=V2_usa1_1" SEVERITY FAILURE; ASSERT V3_usa1_3 <= V2_usa1_3 REPORT msg2 & "V3<=V2_usa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - CONSTANTS (from package 'composite') -- ASSERT C2_usa1_1 <= C2_usa1_1 REPORT msg2 & "C2<=C2_usa1_1" SEVERITY FAILURE; ASSERT C2_usa1_3 <= C2_usa1_3 REPORT msg2 & "C2<=C2_usa1_3" SEVERITY FAILURE; ASSERT C2_csa1_1 <= C2_csa1_1 REPORT msg2 & "C2<=C2_csa1_1" SEVERITY FAILURE; ASSERT C2_csa1_3 <= C2_csa1_3 REPORT msg2 & "C2<=C2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - VARIABLES -- ASSERT V2_usa1_1 <= V2_usa1_1 REPORT msg2 & "V2<=V2_usa1_1" SEVERITY FAILURE; ASSERT V2_usa1_3 <= V2_usa1_3 REPORT msg2 & "V2<=V2_usa1_3" SEVERITY FAILURE; ASSERT V2_csa1_1 <= V2_csa1_1 REPORT msg2 & "V2<=V2_csa1_1" SEVERITY FAILURE; ASSERT V2_csa1_3 <= V2_csa1_3 REPORT msg2 & "V2<=V2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - VARIABLES and CONSTANTS -- ASSERT V2_usa1_1 <= C2_usa1_1 REPORT msg2 & "V2<=C2_usa1_1" SEVERITY FAILURE; ASSERT V2_usa1_3 <= C2_usa1_3 REPORT msg2 & "V2<=C2_usa1_3" SEVERITY FAILURE; ASSERT V2_csa1_1 <= C2_csa1_1 REPORT msg2 & "V2<=C2_csa1_1" SEVERITY FAILURE; ASSERT V2_csa1_3 <= C2_csa1_3 REPORT msg2 & "V2<=C2_csa1_3" SEVERITY FAILURE; assert NOT( C0_usa1_1 < C2_usa1_1 and C0_usa1_3 < C2_usa1_3 and C0_csa1_1 < C2_csa1_1 and C0_csa1_3 < C2_csa1_3 and V0_usa1_1 < V2_usa1_1 and V0_usa1_3 < V2_usa1_3 and V0_csa1_1 < V2_csa1_1 and V0_csa1_3 < V2_csa1_3 and V0_usa1_1 < C2_usa1_1 and V0_usa1_3 < C2_usa1_3 and V0_csa1_1 < C2_csa1_1 and V0_csa1_3 < C2_csa1_3 and V3_usa1_1 < V2_usa1_1 and V3_usa1_3 < V2_usa1_3 and C0_usa1_1 <= C2_usa1_1 and C0_usa1_3 <= C2_usa1_3 and C0_csa1_1 <= C2_csa1_1 and C0_csa1_3 <= C2_csa1_3 and V0_usa1_1 <= V2_usa1_1 and V0_usa1_3 <= V2_usa1_3 and V0_csa1_1 <= V2_csa1_1 and V0_csa1_3 <= V2_csa1_3 and V0_usa1_1 <= C2_usa1_1 and V0_usa1_3 <= C2_usa1_3 and V0_csa1_1 <= C2_csa1_1 and V0_csa1_3 <= C2_csa1_3 and V3_usa1_1 <= V2_usa1_1 and V3_usa1_3 <= V2_usa1_3 and C2_usa1_1 <= C2_usa1_1 and C2_usa1_3 <= C2_usa1_3 and C2_csa1_1 <= C2_csa1_1 and C2_csa1_3 <= C2_csa1_3 and V2_usa1_1 <= V2_usa1_1 and V2_usa1_3 <= V2_usa1_3 and V2_csa1_1 <= V2_csa1_1 and V2_csa1_3 <= V2_csa1_3 and V2_usa1_1 <= C2_usa1_1 and V2_usa1_3 <= C2_usa1_3 and V2_csa1_1 <= C2_csa1_1 and V2_csa1_3 <= C2_csa1_3 ) report "***PASSED TEST: c07s02b02x00p10n01i02012" severity NOTE; assert ( C0_usa1_1 < C2_usa1_1 and C0_usa1_3 < C2_usa1_3 and C0_csa1_1 < C2_csa1_1 and C0_csa1_3 < C2_csa1_3 and V0_usa1_1 < V2_usa1_1 and V0_usa1_3 < V2_usa1_3 and V0_csa1_1 < V2_csa1_1 and V0_csa1_3 < V2_csa1_3 and V0_usa1_1 < C2_usa1_1 and V0_usa1_3 < C2_usa1_3 and V0_csa1_1 < C2_csa1_1 and V0_csa1_3 < C2_csa1_3 and V3_usa1_1 < V2_usa1_1 and V3_usa1_3 < V2_usa1_3 and C0_usa1_1 <= C2_usa1_1 and C0_usa1_3 <= C2_usa1_3 and C0_csa1_1 <= C2_csa1_1 and C0_csa1_3 <= C2_csa1_3 and V0_usa1_1 <= V2_usa1_1 and V0_usa1_3 <= V2_usa1_3 and V0_csa1_1 <= V2_csa1_1 and V0_csa1_3 <= V2_csa1_3 and V0_usa1_1 <= C2_usa1_1 and V0_usa1_3 <= C2_usa1_3 and V0_csa1_1 <= C2_csa1_1 and V0_csa1_3 <= C2_csa1_3 and V3_usa1_1 <= V2_usa1_1 and V3_usa1_3 <= V2_usa1_3 and C2_usa1_1 <= C2_usa1_1 and C2_usa1_3 <= C2_usa1_3 and C2_csa1_1 <= C2_csa1_1 and C2_csa1_3 <= C2_csa1_3 and V2_usa1_1 <= V2_usa1_1 and V2_usa1_3 <= V2_usa1_3 and V2_csa1_1 <= V2_csa1_1 and V2_csa1_3 <= V2_csa1_3 and V2_usa1_1 <= C2_usa1_1 and V2_usa1_3 <= C2_usa1_3 and V2_csa1_1 <= C2_csa1_1 and V2_csa1_3 <= C2_csa1_3 ) report "***FAILED TEST: c07s02b02x00p10n01i02012 - Ordering operators <, <= for composite type test failed." severity ERROR; wait; END PROCESS TESTING; END c07s02b02x00p10n01i02012arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2012.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b02x00p10n01i02012ent IS END c07s02b02x00p10n01i02012ent; ARCHITECTURE c07s02b02x00p10n01i02012arch OF c07s02b02x00p10n01i02012ent IS SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE) SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index SUBTYPE st_scl1 IS CHARACTER ; SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH; TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1; TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3; SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 ); SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 ); CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ; CONSTANT C2_scl1 : st_scl1 := 'Z' ; CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ; CONSTANT C2_scl3 : st_scl3 := 8 ; CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1); CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1, OTHERS =>C0_scl1); CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3); CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3, OTHERS =>C0_scl3); BEGIN TESTING: PROCESS -- -- Constant declarations - for unconstrained types -- other composite type declarations are in package "COMPOSITE" -- CONSTANT C0_usa1_1 : t_usa1_1 (st_ind1 ) := C0_csa1_1; CONSTANT C0_usa1_3 : t_usa1_3 (st_ind3 ) := C0_csa1_3; CONSTANT C2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1; CONSTANT C2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3; -- -- Composite VARIABLE declarations -- VARIABLE V0_usa1_1 : t_usa1_1 (st_ind1 ) ; VARIABLE V0_usa1_3 : t_usa1_3 (st_ind3 ) ; VARIABLE V0_csa1_1 : t_csa1_1 ; VARIABLE V0_csa1_3 : t_csa1_3 ; VARIABLE V2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1; VARIABLE V2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3; VARIABLE V2_csa1_1 : t_csa1_1 := C2_csa1_1; VARIABLE V2_csa1_3 : t_csa1_3 := C2_csa1_3; -- -- Arrays of the same type, element values, different length -- VARIABLE V3_usa1_1 : t_usa1_1 ( 1 TO 7 ) ; VARIABLE V3_usa1_3 : t_usa1_3 ('a' TO 'c' ) ; -- CONSTANT msg1 : STRING := "ERROR: less than operator failure: "; CONSTANT msg2 : STRING := "ERROR: less than or equal operator failure: "; BEGIN -- -- Check less than operator - CONSTANTS (from package 'composite') -- ASSERT C0_usa1_1 < C2_usa1_1 REPORT msg1 & "C0<C2_usa1_1" SEVERITY FAILURE; ASSERT C0_usa1_3 < C2_usa1_3 REPORT msg1 & "C0<C2_usa1_3" SEVERITY FAILURE; ASSERT C0_csa1_1 < C2_csa1_1 REPORT msg1 & "C0<C2_csa1_1" SEVERITY FAILURE; ASSERT C0_csa1_3 < C2_csa1_3 REPORT msg1 & "C0<C2_csa1_3" SEVERITY FAILURE; -- -- Check less than operator - VARIABLES -- ASSERT V0_usa1_1 < V2_usa1_1 REPORT msg1 & "V0<V2_usa1_1" SEVERITY FAILURE; ASSERT V0_usa1_3 < V2_usa1_3 REPORT msg1 & "V0<V2_usa1_3" SEVERITY FAILURE; ASSERT V0_csa1_1 < V2_csa1_1 REPORT msg1 & "V0<V2_csa1_1" SEVERITY FAILURE; ASSERT V0_csa1_3 < V2_csa1_3 REPORT msg1 & "V0<V2_csa1_3" SEVERITY FAILURE; -- -- Check less than operator - VARIABLES and CONSTANTS -- ASSERT V0_usa1_1 < C2_usa1_1 REPORT msg1 & "V0<C2_usa1_1" SEVERITY FAILURE; ASSERT V0_usa1_3 < C2_usa1_3 REPORT msg1 & "V0<C2_usa1_3" SEVERITY FAILURE; ASSERT V0_csa1_1 < C2_csa1_1 REPORT msg1 & "V0<C2_csa1_1" SEVERITY FAILURE; ASSERT V0_csa1_3 < C2_csa1_3 REPORT msg1 & "V0<C2_csa1_3" SEVERITY FAILURE; -- -- Check less than operator - same type, element values : diff array length -- ASSERT V3_usa1_1 < V2_usa1_1 REPORT msg1 & "V3<V2_usa1_1" SEVERITY FAILURE; ASSERT V3_usa1_3 < V2_usa1_3 REPORT msg1 & "V3<V2_usa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - CONSTANTS (from package 'composite') -- ASSERT C0_usa1_1 <= C2_usa1_1 REPORT msg2 & "C0<=C2_usa1_1" SEVERITY FAILURE; ASSERT C0_usa1_3 <= C2_usa1_3 REPORT msg2 & "C0<=C2_usa1_3" SEVERITY FAILURE; ASSERT C0_csa1_1 <= C2_csa1_1 REPORT msg2 & "C0<=C2_csa1_1" SEVERITY FAILURE; ASSERT C0_csa1_3 <= C2_csa1_3 REPORT msg2 & "C0<=C2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - VARIABLES -- ASSERT V0_usa1_1 <= V2_usa1_1 REPORT msg2 & "V0<=V2_usa1_1" SEVERITY FAILURE; ASSERT V0_usa1_3 <= V2_usa1_3 REPORT msg2 & "V0<=V2_usa1_3" SEVERITY FAILURE; ASSERT V0_csa1_1 <= V2_csa1_1 REPORT msg2 & "V0<=V2_csa1_1" SEVERITY FAILURE; ASSERT V0_csa1_3 <= V2_csa1_3 REPORT msg2 & "V0<=V2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - VARIABLES and CONSTANTS -- ASSERT V0_usa1_1 <= C2_usa1_1 REPORT msg2 & "V0<=C2_usa1_1" SEVERITY FAILURE; ASSERT V0_usa1_3 <= C2_usa1_3 REPORT msg2 & "V0<=C2_usa1_3" SEVERITY FAILURE; ASSERT V0_csa1_1 <= C2_csa1_1 REPORT msg2 & "V0<=C2_csa1_1" SEVERITY FAILURE; ASSERT V0_csa1_3 <= C2_csa1_3 REPORT msg2 & "V0<=C2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - same type, element values : diff array length -- ASSERT V3_usa1_1 <= V2_usa1_1 REPORT msg2 & "V3<=V2_usa1_1" SEVERITY FAILURE; ASSERT V3_usa1_3 <= V2_usa1_3 REPORT msg2 & "V3<=V2_usa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - CONSTANTS (from package 'composite') -- ASSERT C2_usa1_1 <= C2_usa1_1 REPORT msg2 & "C2<=C2_usa1_1" SEVERITY FAILURE; ASSERT C2_usa1_3 <= C2_usa1_3 REPORT msg2 & "C2<=C2_usa1_3" SEVERITY FAILURE; ASSERT C2_csa1_1 <= C2_csa1_1 REPORT msg2 & "C2<=C2_csa1_1" SEVERITY FAILURE; ASSERT C2_csa1_3 <= C2_csa1_3 REPORT msg2 & "C2<=C2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - VARIABLES -- ASSERT V2_usa1_1 <= V2_usa1_1 REPORT msg2 & "V2<=V2_usa1_1" SEVERITY FAILURE; ASSERT V2_usa1_3 <= V2_usa1_3 REPORT msg2 & "V2<=V2_usa1_3" SEVERITY FAILURE; ASSERT V2_csa1_1 <= V2_csa1_1 REPORT msg2 & "V2<=V2_csa1_1" SEVERITY FAILURE; ASSERT V2_csa1_3 <= V2_csa1_3 REPORT msg2 & "V2<=V2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - VARIABLES and CONSTANTS -- ASSERT V2_usa1_1 <= C2_usa1_1 REPORT msg2 & "V2<=C2_usa1_1" SEVERITY FAILURE; ASSERT V2_usa1_3 <= C2_usa1_3 REPORT msg2 & "V2<=C2_usa1_3" SEVERITY FAILURE; ASSERT V2_csa1_1 <= C2_csa1_1 REPORT msg2 & "V2<=C2_csa1_1" SEVERITY FAILURE; ASSERT V2_csa1_3 <= C2_csa1_3 REPORT msg2 & "V2<=C2_csa1_3" SEVERITY FAILURE; assert NOT( C0_usa1_1 < C2_usa1_1 and C0_usa1_3 < C2_usa1_3 and C0_csa1_1 < C2_csa1_1 and C0_csa1_3 < C2_csa1_3 and V0_usa1_1 < V2_usa1_1 and V0_usa1_3 < V2_usa1_3 and V0_csa1_1 < V2_csa1_1 and V0_csa1_3 < V2_csa1_3 and V0_usa1_1 < C2_usa1_1 and V0_usa1_3 < C2_usa1_3 and V0_csa1_1 < C2_csa1_1 and V0_csa1_3 < C2_csa1_3 and V3_usa1_1 < V2_usa1_1 and V3_usa1_3 < V2_usa1_3 and C0_usa1_1 <= C2_usa1_1 and C0_usa1_3 <= C2_usa1_3 and C0_csa1_1 <= C2_csa1_1 and C0_csa1_3 <= C2_csa1_3 and V0_usa1_1 <= V2_usa1_1 and V0_usa1_3 <= V2_usa1_3 and V0_csa1_1 <= V2_csa1_1 and V0_csa1_3 <= V2_csa1_3 and V0_usa1_1 <= C2_usa1_1 and V0_usa1_3 <= C2_usa1_3 and V0_csa1_1 <= C2_csa1_1 and V0_csa1_3 <= C2_csa1_3 and V3_usa1_1 <= V2_usa1_1 and V3_usa1_3 <= V2_usa1_3 and C2_usa1_1 <= C2_usa1_1 and C2_usa1_3 <= C2_usa1_3 and C2_csa1_1 <= C2_csa1_1 and C2_csa1_3 <= C2_csa1_3 and V2_usa1_1 <= V2_usa1_1 and V2_usa1_3 <= V2_usa1_3 and V2_csa1_1 <= V2_csa1_1 and V2_csa1_3 <= V2_csa1_3 and V2_usa1_1 <= C2_usa1_1 and V2_usa1_3 <= C2_usa1_3 and V2_csa1_1 <= C2_csa1_1 and V2_csa1_3 <= C2_csa1_3 ) report "***PASSED TEST: c07s02b02x00p10n01i02012" severity NOTE; assert ( C0_usa1_1 < C2_usa1_1 and C0_usa1_3 < C2_usa1_3 and C0_csa1_1 < C2_csa1_1 and C0_csa1_3 < C2_csa1_3 and V0_usa1_1 < V2_usa1_1 and V0_usa1_3 < V2_usa1_3 and V0_csa1_1 < V2_csa1_1 and V0_csa1_3 < V2_csa1_3 and V0_usa1_1 < C2_usa1_1 and V0_usa1_3 < C2_usa1_3 and V0_csa1_1 < C2_csa1_1 and V0_csa1_3 < C2_csa1_3 and V3_usa1_1 < V2_usa1_1 and V3_usa1_3 < V2_usa1_3 and C0_usa1_1 <= C2_usa1_1 and C0_usa1_3 <= C2_usa1_3 and C0_csa1_1 <= C2_csa1_1 and C0_csa1_3 <= C2_csa1_3 and V0_usa1_1 <= V2_usa1_1 and V0_usa1_3 <= V2_usa1_3 and V0_csa1_1 <= V2_csa1_1 and V0_csa1_3 <= V2_csa1_3 and V0_usa1_1 <= C2_usa1_1 and V0_usa1_3 <= C2_usa1_3 and V0_csa1_1 <= C2_csa1_1 and V0_csa1_3 <= C2_csa1_3 and V3_usa1_1 <= V2_usa1_1 and V3_usa1_3 <= V2_usa1_3 and C2_usa1_1 <= C2_usa1_1 and C2_usa1_3 <= C2_usa1_3 and C2_csa1_1 <= C2_csa1_1 and C2_csa1_3 <= C2_csa1_3 and V2_usa1_1 <= V2_usa1_1 and V2_usa1_3 <= V2_usa1_3 and V2_csa1_1 <= V2_csa1_1 and V2_csa1_3 <= V2_csa1_3 and V2_usa1_1 <= C2_usa1_1 and V2_usa1_3 <= C2_usa1_3 and V2_csa1_1 <= C2_csa1_1 and V2_csa1_3 <= C2_csa1_3 ) report "***FAILED TEST: c07s02b02x00p10n01i02012 - Ordering operators <, <= for composite type test failed." severity ERROR; wait; END PROCESS TESTING; END c07s02b02x00p10n01i02012arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2012.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b02x00p10n01i02012ent IS END c07s02b02x00p10n01i02012ent; ARCHITECTURE c07s02b02x00p10n01i02012arch OF c07s02b02x00p10n01i02012ent IS SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE) SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index SUBTYPE st_scl1 IS CHARACTER ; SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH; TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1; TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3; SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 ); SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 ); CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ; CONSTANT C2_scl1 : st_scl1 := 'Z' ; CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ; CONSTANT C2_scl3 : st_scl3 := 8 ; CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1); CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1, OTHERS =>C0_scl1); CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3); CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3, OTHERS =>C0_scl3); BEGIN TESTING: PROCESS -- -- Constant declarations - for unconstrained types -- other composite type declarations are in package "COMPOSITE" -- CONSTANT C0_usa1_1 : t_usa1_1 (st_ind1 ) := C0_csa1_1; CONSTANT C0_usa1_3 : t_usa1_3 (st_ind3 ) := C0_csa1_3; CONSTANT C2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1; CONSTANT C2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3; -- -- Composite VARIABLE declarations -- VARIABLE V0_usa1_1 : t_usa1_1 (st_ind1 ) ; VARIABLE V0_usa1_3 : t_usa1_3 (st_ind3 ) ; VARIABLE V0_csa1_1 : t_csa1_1 ; VARIABLE V0_csa1_3 : t_csa1_3 ; VARIABLE V2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1; VARIABLE V2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3; VARIABLE V2_csa1_1 : t_csa1_1 := C2_csa1_1; VARIABLE V2_csa1_3 : t_csa1_3 := C2_csa1_3; -- -- Arrays of the same type, element values, different length -- VARIABLE V3_usa1_1 : t_usa1_1 ( 1 TO 7 ) ; VARIABLE V3_usa1_3 : t_usa1_3 ('a' TO 'c' ) ; -- CONSTANT msg1 : STRING := "ERROR: less than operator failure: "; CONSTANT msg2 : STRING := "ERROR: less than or equal operator failure: "; BEGIN -- -- Check less than operator - CONSTANTS (from package 'composite') -- ASSERT C0_usa1_1 < C2_usa1_1 REPORT msg1 & "C0<C2_usa1_1" SEVERITY FAILURE; ASSERT C0_usa1_3 < C2_usa1_3 REPORT msg1 & "C0<C2_usa1_3" SEVERITY FAILURE; ASSERT C0_csa1_1 < C2_csa1_1 REPORT msg1 & "C0<C2_csa1_1" SEVERITY FAILURE; ASSERT C0_csa1_3 < C2_csa1_3 REPORT msg1 & "C0<C2_csa1_3" SEVERITY FAILURE; -- -- Check less than operator - VARIABLES -- ASSERT V0_usa1_1 < V2_usa1_1 REPORT msg1 & "V0<V2_usa1_1" SEVERITY FAILURE; ASSERT V0_usa1_3 < V2_usa1_3 REPORT msg1 & "V0<V2_usa1_3" SEVERITY FAILURE; ASSERT V0_csa1_1 < V2_csa1_1 REPORT msg1 & "V0<V2_csa1_1" SEVERITY FAILURE; ASSERT V0_csa1_3 < V2_csa1_3 REPORT msg1 & "V0<V2_csa1_3" SEVERITY FAILURE; -- -- Check less than operator - VARIABLES and CONSTANTS -- ASSERT V0_usa1_1 < C2_usa1_1 REPORT msg1 & "V0<C2_usa1_1" SEVERITY FAILURE; ASSERT V0_usa1_3 < C2_usa1_3 REPORT msg1 & "V0<C2_usa1_3" SEVERITY FAILURE; ASSERT V0_csa1_1 < C2_csa1_1 REPORT msg1 & "V0<C2_csa1_1" SEVERITY FAILURE; ASSERT V0_csa1_3 < C2_csa1_3 REPORT msg1 & "V0<C2_csa1_3" SEVERITY FAILURE; -- -- Check less than operator - same type, element values : diff array length -- ASSERT V3_usa1_1 < V2_usa1_1 REPORT msg1 & "V3<V2_usa1_1" SEVERITY FAILURE; ASSERT V3_usa1_3 < V2_usa1_3 REPORT msg1 & "V3<V2_usa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - CONSTANTS (from package 'composite') -- ASSERT C0_usa1_1 <= C2_usa1_1 REPORT msg2 & "C0<=C2_usa1_1" SEVERITY FAILURE; ASSERT C0_usa1_3 <= C2_usa1_3 REPORT msg2 & "C0<=C2_usa1_3" SEVERITY FAILURE; ASSERT C0_csa1_1 <= C2_csa1_1 REPORT msg2 & "C0<=C2_csa1_1" SEVERITY FAILURE; ASSERT C0_csa1_3 <= C2_csa1_3 REPORT msg2 & "C0<=C2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - VARIABLES -- ASSERT V0_usa1_1 <= V2_usa1_1 REPORT msg2 & "V0<=V2_usa1_1" SEVERITY FAILURE; ASSERT V0_usa1_3 <= V2_usa1_3 REPORT msg2 & "V0<=V2_usa1_3" SEVERITY FAILURE; ASSERT V0_csa1_1 <= V2_csa1_1 REPORT msg2 & "V0<=V2_csa1_1" SEVERITY FAILURE; ASSERT V0_csa1_3 <= V2_csa1_3 REPORT msg2 & "V0<=V2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - VARIABLES and CONSTANTS -- ASSERT V0_usa1_1 <= C2_usa1_1 REPORT msg2 & "V0<=C2_usa1_1" SEVERITY FAILURE; ASSERT V0_usa1_3 <= C2_usa1_3 REPORT msg2 & "V0<=C2_usa1_3" SEVERITY FAILURE; ASSERT V0_csa1_1 <= C2_csa1_1 REPORT msg2 & "V0<=C2_csa1_1" SEVERITY FAILURE; ASSERT V0_csa1_3 <= C2_csa1_3 REPORT msg2 & "V0<=C2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - same type, element values : diff array length -- ASSERT V3_usa1_1 <= V2_usa1_1 REPORT msg2 & "V3<=V2_usa1_1" SEVERITY FAILURE; ASSERT V3_usa1_3 <= V2_usa1_3 REPORT msg2 & "V3<=V2_usa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - CONSTANTS (from package 'composite') -- ASSERT C2_usa1_1 <= C2_usa1_1 REPORT msg2 & "C2<=C2_usa1_1" SEVERITY FAILURE; ASSERT C2_usa1_3 <= C2_usa1_3 REPORT msg2 & "C2<=C2_usa1_3" SEVERITY FAILURE; ASSERT C2_csa1_1 <= C2_csa1_1 REPORT msg2 & "C2<=C2_csa1_1" SEVERITY FAILURE; ASSERT C2_csa1_3 <= C2_csa1_3 REPORT msg2 & "C2<=C2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - VARIABLES -- ASSERT V2_usa1_1 <= V2_usa1_1 REPORT msg2 & "V2<=V2_usa1_1" SEVERITY FAILURE; ASSERT V2_usa1_3 <= V2_usa1_3 REPORT msg2 & "V2<=V2_usa1_3" SEVERITY FAILURE; ASSERT V2_csa1_1 <= V2_csa1_1 REPORT msg2 & "V2<=V2_csa1_1" SEVERITY FAILURE; ASSERT V2_csa1_3 <= V2_csa1_3 REPORT msg2 & "V2<=V2_csa1_3" SEVERITY FAILURE; -- -- Check less than or equal operator - VARIABLES and CONSTANTS -- ASSERT V2_usa1_1 <= C2_usa1_1 REPORT msg2 & "V2<=C2_usa1_1" SEVERITY FAILURE; ASSERT V2_usa1_3 <= C2_usa1_3 REPORT msg2 & "V2<=C2_usa1_3" SEVERITY FAILURE; ASSERT V2_csa1_1 <= C2_csa1_1 REPORT msg2 & "V2<=C2_csa1_1" SEVERITY FAILURE; ASSERT V2_csa1_3 <= C2_csa1_3 REPORT msg2 & "V2<=C2_csa1_3" SEVERITY FAILURE; assert NOT( C0_usa1_1 < C2_usa1_1 and C0_usa1_3 < C2_usa1_3 and C0_csa1_1 < C2_csa1_1 and C0_csa1_3 < C2_csa1_3 and V0_usa1_1 < V2_usa1_1 and V0_usa1_3 < V2_usa1_3 and V0_csa1_1 < V2_csa1_1 and V0_csa1_3 < V2_csa1_3 and V0_usa1_1 < C2_usa1_1 and V0_usa1_3 < C2_usa1_3 and V0_csa1_1 < C2_csa1_1 and V0_csa1_3 < C2_csa1_3 and V3_usa1_1 < V2_usa1_1 and V3_usa1_3 < V2_usa1_3 and C0_usa1_1 <= C2_usa1_1 and C0_usa1_3 <= C2_usa1_3 and C0_csa1_1 <= C2_csa1_1 and C0_csa1_3 <= C2_csa1_3 and V0_usa1_1 <= V2_usa1_1 and V0_usa1_3 <= V2_usa1_3 and V0_csa1_1 <= V2_csa1_1 and V0_csa1_3 <= V2_csa1_3 and V0_usa1_1 <= C2_usa1_1 and V0_usa1_3 <= C2_usa1_3 and V0_csa1_1 <= C2_csa1_1 and V0_csa1_3 <= C2_csa1_3 and V3_usa1_1 <= V2_usa1_1 and V3_usa1_3 <= V2_usa1_3 and C2_usa1_1 <= C2_usa1_1 and C2_usa1_3 <= C2_usa1_3 and C2_csa1_1 <= C2_csa1_1 and C2_csa1_3 <= C2_csa1_3 and V2_usa1_1 <= V2_usa1_1 and V2_usa1_3 <= V2_usa1_3 and V2_csa1_1 <= V2_csa1_1 and V2_csa1_3 <= V2_csa1_3 and V2_usa1_1 <= C2_usa1_1 and V2_usa1_3 <= C2_usa1_3 and V2_csa1_1 <= C2_csa1_1 and V2_csa1_3 <= C2_csa1_3 ) report "***PASSED TEST: c07s02b02x00p10n01i02012" severity NOTE; assert ( C0_usa1_1 < C2_usa1_1 and C0_usa1_3 < C2_usa1_3 and C0_csa1_1 < C2_csa1_1 and C0_csa1_3 < C2_csa1_3 and V0_usa1_1 < V2_usa1_1 and V0_usa1_3 < V2_usa1_3 and V0_csa1_1 < V2_csa1_1 and V0_csa1_3 < V2_csa1_3 and V0_usa1_1 < C2_usa1_1 and V0_usa1_3 < C2_usa1_3 and V0_csa1_1 < C2_csa1_1 and V0_csa1_3 < C2_csa1_3 and V3_usa1_1 < V2_usa1_1 and V3_usa1_3 < V2_usa1_3 and C0_usa1_1 <= C2_usa1_1 and C0_usa1_3 <= C2_usa1_3 and C0_csa1_1 <= C2_csa1_1 and C0_csa1_3 <= C2_csa1_3 and V0_usa1_1 <= V2_usa1_1 and V0_usa1_3 <= V2_usa1_3 and V0_csa1_1 <= V2_csa1_1 and V0_csa1_3 <= V2_csa1_3 and V0_usa1_1 <= C2_usa1_1 and V0_usa1_3 <= C2_usa1_3 and V0_csa1_1 <= C2_csa1_1 and V0_csa1_3 <= C2_csa1_3 and V3_usa1_1 <= V2_usa1_1 and V3_usa1_3 <= V2_usa1_3 and C2_usa1_1 <= C2_usa1_1 and C2_usa1_3 <= C2_usa1_3 and C2_csa1_1 <= C2_csa1_1 and C2_csa1_3 <= C2_csa1_3 and V2_usa1_1 <= V2_usa1_1 and V2_usa1_3 <= V2_usa1_3 and V2_csa1_1 <= V2_csa1_1 and V2_csa1_3 <= V2_csa1_3 and V2_usa1_1 <= C2_usa1_1 and V2_usa1_3 <= C2_usa1_3 and V2_csa1_1 <= C2_csa1_1 and V2_csa1_3 <= C2_csa1_3 ) report "***FAILED TEST: c07s02b02x00p10n01i02012 - Ordering operators <, <= for composite type test failed." severity ERROR; wait; END PROCESS TESTING; END c07s02b02x00p10n01i02012arch;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity wb_spimaster is generic ( dat_sz : natural := 8; slv_bits: natural := 3 ); port ( clk_i : in std_logic; rst_i : in std_logic; -- -- Whishbone Interface -- adr_i : in std_logic_vector(1 downto 0); dat_i : in std_logic_vector((dat_sz - 1) downto 0); dat_o : out std_logic_vector((dat_sz - 1) downto 0); cyc_i : in std_logic; lock_i : in std_logic; sel_i : in std_logic; we_i : in std_logic; ack_o : out std_logic; err_o : out std_logic; rty_o : out std_logic; stall_o: out std_logic; stb_i : in std_logic; -- -- SPI Master Signals -- spi_mosi_o : out std_logic; spi_miso_i : in std_logic; spi_nsel_o : out std_logic_vector(((2 ** slv_bits) - 1) downto 0); spi_sclk_o : out std_logic ); end wb_spimaster; architecture Behavioral of wb_spimaster is component shift_engine is generic ( -- Width of parallel data width : natural := 8; -- Delay after NSEL is pulled low, in ticks of clk_i delay : natural := 2 ); port ( -- Clocking clk_i : in std_logic; rst_i : in std_logic; -- Data dat_i : in std_logic_vector((width - 1) downto 0); dat_o : out std_logic_vector((width - 1) downto 0); -- Control Signals cpol_i : in std_logic; -- SPI Clock Polarity cpha_i : in std_logic; -- SPI Clock Phase div_i : in natural range 2 to width; -- SPI Clock Divider, relative to clk_i cnt_i : in integer range 1 to (width - 1); -- Number of Bits to Shift start_i : in std_logic; done_o : out std_logic; -- Shift Signals sclk_o : out std_logic; mosi_o : out std_logic; miso_i : in std_logic ); end component shift_engine; -- Internal Registers signal tx_dat : std_logic_vector((dat_sz - 1) downto 0) := (others => '-'); signal rx_dat : std_logic_vector((dat_sz - 1) downto 0) := (others => '-'); signal ctrl : std_logic_vector((dat_sz - 2) downto 0) := (others => '0'); signal nsel : std_logic_vector(((2 ** slv_bits) - 1) downto 0) := (others => '1'); signal div : std_logic_vector((dat_sz - 1) downto 0) := (others => '1'); signal start : std_logic; signal done : std_logic; signal tmp_div : integer := 2; signal tmp_cnt : integer := (dat_sz - 1); begin shift : shift_engine generic map ( -- Width of parallel data width => dat_sz, -- Delay after NSEL is pulled low, in ticks of clk_i delay => 2 ) port map ( -- Clocking clk_i => clk_i, rst_i => rst_i, -- Data dat_i => tx_dat, dat_o => rx_dat, -- Control Signals cpol_i => ctrl(4), cpha_i => ctrl(5), div_i => tmp_div, cnt_i => tmp_cnt, start_i => start, done_o => done, -- Shift Signals sclk_o => spi_sclk_o, mosi_o => spi_mosi_o, miso_i => spi_miso_i ); tmp_cnt <= to_integer(unsigned(ctrl(2 downto 0))); tmp_div <= to_integer(unsigned(div)); process (clk_i) begin if (rising_edge(clk_i)) then start <= '0'; ack_o <= stb_i; err_o <= '0'; if ((stb_i = '1') and (we_i = '1')) then case adr_i is when "00" => tx_dat <= dat_i; when "01" => ctrl((dat_i'high - 1) downto 0) <= dat_i((dat_i'high - 1) downto 0); if ((done = '0') and (dat_i(7) = '1')) then ack_o <= '0'; err_o <= '1'; else start <= dat_i(dat_i'high); end if; when "10" => nsel(((2 ** slv_bits) - 1) downto 0) <= dat_i(((2 ** slv_bits) - 1) downto 0); when "11" => div <= dat_i; when others => end case; else case adr_i is when "00" => dat_o <= rx_dat; when "01" => dat_o(6 downto 0) <= ctrl(6 downto 0); dat_o(7) <= not done; when "10" => dat_o(nsel'high downto 0) <= nsel; when "11" => dat_o <= div; when others => dat_o <= (others => '-'); end case; end if; end if; end process; rty_o <= '0'; spi_nsel_o <= nsel; stall_o <= stb_i; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity wb_spimaster is generic ( dat_sz : natural := 8; slv_bits: natural := 3 ); port ( clk_i : in std_logic; rst_i : in std_logic; -- -- Whishbone Interface -- adr_i : in std_logic_vector(1 downto 0); dat_i : in std_logic_vector((dat_sz - 1) downto 0); dat_o : out std_logic_vector((dat_sz - 1) downto 0); cyc_i : in std_logic; lock_i : in std_logic; sel_i : in std_logic; we_i : in std_logic; ack_o : out std_logic; err_o : out std_logic; rty_o : out std_logic; stall_o: out std_logic; stb_i : in std_logic; -- -- SPI Master Signals -- spi_mosi_o : out std_logic; spi_miso_i : in std_logic; spi_nsel_o : out std_logic_vector(((2 ** slv_bits) - 1) downto 0); spi_sclk_o : out std_logic ); end wb_spimaster; architecture Behavioral of wb_spimaster is component shift_engine is generic ( -- Width of parallel data width : natural := 8; -- Delay after NSEL is pulled low, in ticks of clk_i delay : natural := 2 ); port ( -- Clocking clk_i : in std_logic; rst_i : in std_logic; -- Data dat_i : in std_logic_vector((width - 1) downto 0); dat_o : out std_logic_vector((width - 1) downto 0); -- Control Signals cpol_i : in std_logic; -- SPI Clock Polarity cpha_i : in std_logic; -- SPI Clock Phase div_i : in natural range 2 to width; -- SPI Clock Divider, relative to clk_i cnt_i : in integer range 1 to (width - 1); -- Number of Bits to Shift start_i : in std_logic; done_o : out std_logic; -- Shift Signals sclk_o : out std_logic; mosi_o : out std_logic; miso_i : in std_logic ); end component shift_engine; -- Internal Registers signal tx_dat : std_logic_vector((dat_sz - 1) downto 0) := (others => '-'); signal rx_dat : std_logic_vector((dat_sz - 1) downto 0) := (others => '-'); signal ctrl : std_logic_vector((dat_sz - 2) downto 0) := (others => '0'); signal nsel : std_logic_vector(((2 ** slv_bits) - 1) downto 0) := (others => '1'); signal div : std_logic_vector((dat_sz - 1) downto 0) := (others => '1'); signal start : std_logic; signal done : std_logic; signal tmp_div : integer := 2; signal tmp_cnt : integer := (dat_sz - 1); begin shift : shift_engine generic map ( -- Width of parallel data width => dat_sz, -- Delay after NSEL is pulled low, in ticks of clk_i delay => 2 ) port map ( -- Clocking clk_i => clk_i, rst_i => rst_i, -- Data dat_i => tx_dat, dat_o => rx_dat, -- Control Signals cpol_i => ctrl(4), cpha_i => ctrl(5), div_i => tmp_div, cnt_i => tmp_cnt, start_i => start, done_o => done, -- Shift Signals sclk_o => spi_sclk_o, mosi_o => spi_mosi_o, miso_i => spi_miso_i ); tmp_cnt <= to_integer(unsigned(ctrl(2 downto 0))); tmp_div <= to_integer(unsigned(div)); process (clk_i) begin if (rising_edge(clk_i)) then start <= '0'; ack_o <= stb_i; err_o <= '0'; if ((stb_i = '1') and (we_i = '1')) then case adr_i is when "00" => tx_dat <= dat_i; when "01" => ctrl((dat_i'high - 1) downto 0) <= dat_i((dat_i'high - 1) downto 0); if ((done = '0') and (dat_i(7) = '1')) then ack_o <= '0'; err_o <= '1'; else start <= dat_i(dat_i'high); end if; when "10" => nsel(((2 ** slv_bits) - 1) downto 0) <= dat_i(((2 ** slv_bits) - 1) downto 0); when "11" => div <= dat_i; when others => end case; else case adr_i is when "00" => dat_o <= rx_dat; when "01" => dat_o(6 downto 0) <= ctrl(6 downto 0); dat_o(7) <= not done; when "10" => dat_o(nsel'high downto 0) <= nsel; when "11" => dat_o <= div; when others => dat_o <= (others => '-'); end case; end if; end if; end process; rty_o <= '0'; spi_nsel_o <= nsel; stall_o <= stb_i; end Behavioral;
-----Library statements ----- library ieee; use ieee.std_logic_1164.all; -----Entity declaration ----- entity GuessGame is port( inputs : in std_logic_vector(7 downto 0); set : in std_logic; -- set predefined value show : in std_logic; -- Show predefined value try : in std_logic; -- Evaluate guess hex1 : out std_logic_vector(6 downto 0); -- 7seg ones hex10 : out std_logic_vector(6 downto 0) -- 7seg tens ); end GuessGame; architecture guessing of GuessGame is -- declare signals, components here... signal setValue, dispValue : std_logic_vector(7 downto 0) := "00000000"; begin ones: entity work.DecimalSeg port map(bin => dispValue(3 downto 0), seg => hex1); tens: entity work.DecimalSeg port map(bin => dispValue(7 downto 4), seg => hex10); -- architecture body... process(show, set, try) begin if set = '0' then setValue <= inputs; dispValue <= setValue; -- to avoid inferred latch for dispValue elsif show = '0' then dispValue <= setValue; elsif try = '0' then if inputs < setValue then dispValue <= "10101011"; elsif inputs > setValue then dispValue <= "11001101"; else dispValue <= "11101110"; end if; else dispValue <= inputs; end if; end process; end architecture;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_dma_afifo_autord.vhd -- Version: initial -- Description: -- This file contains the logic to generate a CoreGen call to create a -- asynchronous FIFO as part of the synthesis process of XST. This eliminates -- the need for multiple fixed netlists for various sizes and widths of FIFOs. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library lib_cdc_v1_0_2; library lib_fifo_v1_0_4; use lib_fifo_v1_0_4.async_fifo_fg; library axi_dma_v7_1_8; use axi_dma_v7_1_8.axi_dma_pkg.all; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- entity axi_dma_afifo_autord is generic ( C_DWIDTH : integer := 32; C_DEPTH : integer := 16; C_CNT_WIDTH : Integer := 5; C_USE_BLKMEM : Integer := 0 ; C_USE_AUTORD : Integer := 1; C_PRMRY_IS_ACLK_ASYNC : integer := 1; C_FAMILY : String := "virtex7" ); port ( -- Inputs AFIFO_Ainit : In std_logic; -- AFIFO_Wr_clk : In std_logic; -- AFIFO_Wr_en : In std_logic; -- AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); -- AFIFO_Rd_clk : In std_logic; -- AFIFO_Rd_en : In std_logic; -- AFIFO_Clr_Rd_Data_Valid : In std_logic; -- -- -- Outputs -- AFIFO_DValid : Out std_logic; -- AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); -- AFIFO_Full : Out std_logic; -- AFIFO_Empty : Out std_logic; -- AFIFO_Almost_full : Out std_logic; -- AFIFO_Almost_empty : Out std_logic; -- AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); -- AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); -- AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); -- AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); -- AFIFO_Rd_ack : Out std_logic -- ); end entity axi_dma_afifo_autord; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture imp of axi_dma_afifo_autord is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; -- Constant declarations ATTRIBUTE async_reg : STRING; -- Signal declarations signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0'); signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0'); signal rd_count_int : integer range 0 to C_DEPTH+1 := 0; signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0; signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0; Signal corrected_empty : std_logic := '0'; Signal corrected_almost_empty : std_logic := '0'; Signal sig_afifo_empty : std_logic := '0'; Signal sig_afifo_almost_empty : std_logic := '0'; -- backend fifo read ack sample and hold Signal sig_rddata_valid : std_logic := '0'; Signal hold_ff_q : std_logic := '0'; Signal ored_ack_ff_reset : std_logic := '0'; Signal autoread : std_logic := '0'; Signal sig_wrfifo_rdack : std_logic := '0'; Signal fifo_read_enable : std_logic := '0'; Signal first_write : std_logic := '0'; Signal first_read_cdc_tig : std_logic := '0'; Signal first_read1 : std_logic := '0'; Signal first_read2 : std_logic := '0'; signal AFIFO_Ainit_d1_cdc_tig : std_logic; signal AFIFO_Ainit_d2 : std_logic; --ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true"; --ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true"; -- Component declarations ----------------------------------------------------------------------------- -- Begin architecture ----------------------------------------------------------------------------- begin -- Bit ordering translations write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little -- endian. AFIFO_Rd_ack <= sig_wrfifo_rdack; AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to -- Big endian. AFIFO_Almost_empty <= corrected_almost_empty; GEN_EMPTY : if (C_USE_AUTORD = 1) generate begin AFIFO_Empty <= corrected_empty; end generate GEN_EMPTY; GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate begin AFIFO_Empty <= sig_afifo_empty; end generate GEN_EMPTY1; AFIFO_Wr_count <= wr_count_lil_end; AFIFO_Rd_count <= rd_count_lil_end; AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr, C_CNT_WIDTH+1); AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1, C_CNT_WIDTH+1); AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator fifo_read_enable <= AFIFO_Rd_en or autoread; ------------------------------------------------------------------------------- -- Instantiate the CoreGen FIFO -- -- NOTE: -- This instance refers to a wrapper file that interm will use the -- CoreGen FIFO Generator Async FIFO utility. -- ------------------------------------------------------------------------------- I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg generic map ( -- C_ALLOW_2N_DEPTH => 1, C_ALLOW_2N_DEPTH => 0, C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DWIDTH, C_ENABLE_RLOCS => 0, C_FIFO_DEPTH => C_DEPTH, C_HAS_ALMOST_EMPTY => 1, C_HAS_ALMOST_FULL => 1, C_HAS_RD_ACK => 1, C_HAS_RD_COUNT => 1, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_COUNT => 1, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_COUNT_WIDTH => C_CNT_WIDTH, C_RD_ERR_LOW => 0, C_USE_BLOCKMEM => C_USE_BLKMEM, C_WR_ACK_LOW => 0, C_WR_COUNT_WIDTH => C_CNT_WIDTH, C_WR_ERR_LOW => 0, C_SYNCHRONIZER_STAGE => C_FIFO_MTBF -- C_USE_EMBEDDED_REG => 1, -- 0 ; -- C_PRELOAD_REGS => 0, -- 0 ; -- C_PRELOAD_LATENCY => 1 -- 1 ; ) port Map ( Din => write_data_lil_end, Wr_en => AFIFO_Wr_en, Wr_clk => AFIFO_Wr_clk, Rd_en => fifo_read_enable, Rd_clk => AFIFO_Rd_clk, Ainit => AFIFO_Ainit, Dout => read_data_lil_end, Full => AFIFO_Full, Empty => sig_afifo_empty, Almost_full => AFIFO_Almost_full, Almost_empty => sig_afifo_almost_empty, Wr_count => wr_count_lil_end, Rd_count => rd_count_lil_end, Rd_ack => sig_wrfifo_rdack, Rd_err => open, -- Not used by axi_dma Wr_ack => open, -- Not used by axi_dma Wr_err => open -- Not used by axi_dma ); ---------------------------------------------------------------------------- -- Read Ack assert & hold logic (needed because: -- 1) The Async FIFO has to be read once to get valid -- data to the read data port (data is discarded). -- 2) The Read ack from the fifo is only asserted for 1 clock. -- 3) A signal is needed that indicates valid data is at the read -- port of the FIFO and has not yet been read. This signal needs -- to be held until the next read operation occurs or a clear -- signal is received. ored_ack_ff_reset <= fifo_read_enable or AFIFO_Ainit_d2 or AFIFO_Clr_Rd_Data_Valid; sig_rddata_valid <= hold_ff_q or sig_wrfifo_rdack; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ACK_HOLD_FLOP -- -- Process Description: -- Flop for registering the hold flag -- ------------------------------------------------------------- ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => AFIFO_Ainit, prmry_vect_in => (others => '0'), scndry_aclk => AFIFO_Rd_clk, scndry_resetn => '0', scndry_out => AFIFO_Ainit_d2, scndry_vect_out => open ); end generate ASYNC_CDC_SYNC; SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate AFIFO_Ainit_d2 <= AFIFO_Ainit; end generate SYNC_CDC_SYNC; -- IMP_SYNC_FLOP : process (AFIFO_Rd_clk) -- begin -- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then -- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit; -- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig; -- end if; -- end process IMP_SYNC_FLOP; IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk) begin if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then if (ored_ack_ff_reset = '1') then hold_ff_q <= '0'; else hold_ff_q <= sig_rddata_valid; end if; end if; end process IMP_ACK_HOLD_FLOP; -- I_ACK_HOLD_FF : FDRE -- port map( -- Q => hold_ff_q, -- C => AFIFO_Rd_clk, -- CE => '1', -- D => sig_rddata_valid, -- R => ored_ack_ff_reset -- ); -- generate auto-read enable. This keeps fresh data at the output -- of the FIFO whenever it is available. GEN_AUTORD1 : if C_USE_AUTORD = 1 generate autoread <= '1' -- create a read strobe when the when (sig_rddata_valid = '0' and -- output data is NOT valid sig_afifo_empty = '0') -- and the FIFO is not empty Else '0'; end generate GEN_AUTORD1; GEN_AUTORD2 : if C_USE_AUTORD = 0 generate process (AFIFO_Wr_clk) begin if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then if (AFIFO_Ainit = '0') then first_write <= '0'; elsif (AFIFO_Wr_en = '1') then first_write <= '1'; end if; end if; end process; IMP_SYNC_FLOP1 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => first_write, prmry_vect_in => (others => '0'), scndry_aclk => AFIFO_Rd_clk, scndry_resetn => '0', scndry_out => first_read1, scndry_vect_out => open ); process (AFIFO_Rd_clk) begin if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then if (AFIFO_Ainit_d2 = '0') then first_read2 <= '0'; elsif (sig_afifo_empty = '0') then first_read2 <= first_read1; end if; end if; end process; autoread <= first_read1 xor first_read2; end generate GEN_AUTORD2; rd_count_int <= CONV_INTEGER(rd_count_lil_end); ------------------------------------------------------------- -- Combinational Process -- -- Label: CORRECT_RD_CNT -- -- Process Description: -- This process corrects the FIFO Read Count output for the -- auto read function. -- ------------------------------------------------------------- CORRECT_RD_CNT : process (sig_rddata_valid, sig_afifo_empty, sig_afifo_almost_empty, rd_count_int) begin if (sig_rddata_valid = '0') then rd_count_int_corr <= 0; rd_count_int_corr_minus1 <= 0; corrected_empty <= '1'; corrected_almost_empty <= '0'; elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty rd_count_int_corr <= 1; rd_count_int_corr_minus1 <= 0; corrected_empty <= '0'; corrected_almost_empty <= '1'; Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty rd_count_int_corr <= 2; rd_count_int_corr_minus1 <= 1; corrected_empty <= '0'; corrected_almost_empty <= '0'; else -- rddata valid and modify rd count from FIFO rd_count_int_corr <= rd_count_int+1; rd_count_int_corr_minus1 <= rd_count_int; corrected_empty <= '0'; corrected_almost_empty <= '0'; end if; end process CORRECT_RD_CNT; end imp;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_dma_afifo_autord.vhd -- Version: initial -- Description: -- This file contains the logic to generate a CoreGen call to create a -- asynchronous FIFO as part of the synthesis process of XST. This eliminates -- the need for multiple fixed netlists for various sizes and widths of FIFOs. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library lib_cdc_v1_0_2; library lib_fifo_v1_0_4; use lib_fifo_v1_0_4.async_fifo_fg; library axi_dma_v7_1_8; use axi_dma_v7_1_8.axi_dma_pkg.all; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- entity axi_dma_afifo_autord is generic ( C_DWIDTH : integer := 32; C_DEPTH : integer := 16; C_CNT_WIDTH : Integer := 5; C_USE_BLKMEM : Integer := 0 ; C_USE_AUTORD : Integer := 1; C_PRMRY_IS_ACLK_ASYNC : integer := 1; C_FAMILY : String := "virtex7" ); port ( -- Inputs AFIFO_Ainit : In std_logic; -- AFIFO_Wr_clk : In std_logic; -- AFIFO_Wr_en : In std_logic; -- AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); -- AFIFO_Rd_clk : In std_logic; -- AFIFO_Rd_en : In std_logic; -- AFIFO_Clr_Rd_Data_Valid : In std_logic; -- -- -- Outputs -- AFIFO_DValid : Out std_logic; -- AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); -- AFIFO_Full : Out std_logic; -- AFIFO_Empty : Out std_logic; -- AFIFO_Almost_full : Out std_logic; -- AFIFO_Almost_empty : Out std_logic; -- AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); -- AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); -- AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); -- AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); -- AFIFO_Rd_ack : Out std_logic -- ); end entity axi_dma_afifo_autord; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture imp of axi_dma_afifo_autord is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; -- Constant declarations ATTRIBUTE async_reg : STRING; -- Signal declarations signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0'); signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0'); signal rd_count_int : integer range 0 to C_DEPTH+1 := 0; signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0; signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0; Signal corrected_empty : std_logic := '0'; Signal corrected_almost_empty : std_logic := '0'; Signal sig_afifo_empty : std_logic := '0'; Signal sig_afifo_almost_empty : std_logic := '0'; -- backend fifo read ack sample and hold Signal sig_rddata_valid : std_logic := '0'; Signal hold_ff_q : std_logic := '0'; Signal ored_ack_ff_reset : std_logic := '0'; Signal autoread : std_logic := '0'; Signal sig_wrfifo_rdack : std_logic := '0'; Signal fifo_read_enable : std_logic := '0'; Signal first_write : std_logic := '0'; Signal first_read_cdc_tig : std_logic := '0'; Signal first_read1 : std_logic := '0'; Signal first_read2 : std_logic := '0'; signal AFIFO_Ainit_d1_cdc_tig : std_logic; signal AFIFO_Ainit_d2 : std_logic; --ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true"; --ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true"; -- Component declarations ----------------------------------------------------------------------------- -- Begin architecture ----------------------------------------------------------------------------- begin -- Bit ordering translations write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little -- endian. AFIFO_Rd_ack <= sig_wrfifo_rdack; AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to -- Big endian. AFIFO_Almost_empty <= corrected_almost_empty; GEN_EMPTY : if (C_USE_AUTORD = 1) generate begin AFIFO_Empty <= corrected_empty; end generate GEN_EMPTY; GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate begin AFIFO_Empty <= sig_afifo_empty; end generate GEN_EMPTY1; AFIFO_Wr_count <= wr_count_lil_end; AFIFO_Rd_count <= rd_count_lil_end; AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr, C_CNT_WIDTH+1); AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1, C_CNT_WIDTH+1); AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator fifo_read_enable <= AFIFO_Rd_en or autoread; ------------------------------------------------------------------------------- -- Instantiate the CoreGen FIFO -- -- NOTE: -- This instance refers to a wrapper file that interm will use the -- CoreGen FIFO Generator Async FIFO utility. -- ------------------------------------------------------------------------------- I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg generic map ( -- C_ALLOW_2N_DEPTH => 1, C_ALLOW_2N_DEPTH => 0, C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DWIDTH, C_ENABLE_RLOCS => 0, C_FIFO_DEPTH => C_DEPTH, C_HAS_ALMOST_EMPTY => 1, C_HAS_ALMOST_FULL => 1, C_HAS_RD_ACK => 1, C_HAS_RD_COUNT => 1, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_COUNT => 1, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_COUNT_WIDTH => C_CNT_WIDTH, C_RD_ERR_LOW => 0, C_USE_BLOCKMEM => C_USE_BLKMEM, C_WR_ACK_LOW => 0, C_WR_COUNT_WIDTH => C_CNT_WIDTH, C_WR_ERR_LOW => 0, C_SYNCHRONIZER_STAGE => C_FIFO_MTBF -- C_USE_EMBEDDED_REG => 1, -- 0 ; -- C_PRELOAD_REGS => 0, -- 0 ; -- C_PRELOAD_LATENCY => 1 -- 1 ; ) port Map ( Din => write_data_lil_end, Wr_en => AFIFO_Wr_en, Wr_clk => AFIFO_Wr_clk, Rd_en => fifo_read_enable, Rd_clk => AFIFO_Rd_clk, Ainit => AFIFO_Ainit, Dout => read_data_lil_end, Full => AFIFO_Full, Empty => sig_afifo_empty, Almost_full => AFIFO_Almost_full, Almost_empty => sig_afifo_almost_empty, Wr_count => wr_count_lil_end, Rd_count => rd_count_lil_end, Rd_ack => sig_wrfifo_rdack, Rd_err => open, -- Not used by axi_dma Wr_ack => open, -- Not used by axi_dma Wr_err => open -- Not used by axi_dma ); ---------------------------------------------------------------------------- -- Read Ack assert & hold logic (needed because: -- 1) The Async FIFO has to be read once to get valid -- data to the read data port (data is discarded). -- 2) The Read ack from the fifo is only asserted for 1 clock. -- 3) A signal is needed that indicates valid data is at the read -- port of the FIFO and has not yet been read. This signal needs -- to be held until the next read operation occurs or a clear -- signal is received. ored_ack_ff_reset <= fifo_read_enable or AFIFO_Ainit_d2 or AFIFO_Clr_Rd_Data_Valid; sig_rddata_valid <= hold_ff_q or sig_wrfifo_rdack; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ACK_HOLD_FLOP -- -- Process Description: -- Flop for registering the hold flag -- ------------------------------------------------------------- ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => AFIFO_Ainit, prmry_vect_in => (others => '0'), scndry_aclk => AFIFO_Rd_clk, scndry_resetn => '0', scndry_out => AFIFO_Ainit_d2, scndry_vect_out => open ); end generate ASYNC_CDC_SYNC; SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate AFIFO_Ainit_d2 <= AFIFO_Ainit; end generate SYNC_CDC_SYNC; -- IMP_SYNC_FLOP : process (AFIFO_Rd_clk) -- begin -- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then -- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit; -- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig; -- end if; -- end process IMP_SYNC_FLOP; IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk) begin if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then if (ored_ack_ff_reset = '1') then hold_ff_q <= '0'; else hold_ff_q <= sig_rddata_valid; end if; end if; end process IMP_ACK_HOLD_FLOP; -- I_ACK_HOLD_FF : FDRE -- port map( -- Q => hold_ff_q, -- C => AFIFO_Rd_clk, -- CE => '1', -- D => sig_rddata_valid, -- R => ored_ack_ff_reset -- ); -- generate auto-read enable. This keeps fresh data at the output -- of the FIFO whenever it is available. GEN_AUTORD1 : if C_USE_AUTORD = 1 generate autoread <= '1' -- create a read strobe when the when (sig_rddata_valid = '0' and -- output data is NOT valid sig_afifo_empty = '0') -- and the FIFO is not empty Else '0'; end generate GEN_AUTORD1; GEN_AUTORD2 : if C_USE_AUTORD = 0 generate process (AFIFO_Wr_clk) begin if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then if (AFIFO_Ainit = '0') then first_write <= '0'; elsif (AFIFO_Wr_en = '1') then first_write <= '1'; end if; end if; end process; IMP_SYNC_FLOP1 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => first_write, prmry_vect_in => (others => '0'), scndry_aclk => AFIFO_Rd_clk, scndry_resetn => '0', scndry_out => first_read1, scndry_vect_out => open ); process (AFIFO_Rd_clk) begin if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then if (AFIFO_Ainit_d2 = '0') then first_read2 <= '0'; elsif (sig_afifo_empty = '0') then first_read2 <= first_read1; end if; end if; end process; autoread <= first_read1 xor first_read2; end generate GEN_AUTORD2; rd_count_int <= CONV_INTEGER(rd_count_lil_end); ------------------------------------------------------------- -- Combinational Process -- -- Label: CORRECT_RD_CNT -- -- Process Description: -- This process corrects the FIFO Read Count output for the -- auto read function. -- ------------------------------------------------------------- CORRECT_RD_CNT : process (sig_rddata_valid, sig_afifo_empty, sig_afifo_almost_empty, rd_count_int) begin if (sig_rddata_valid = '0') then rd_count_int_corr <= 0; rd_count_int_corr_minus1 <= 0; corrected_empty <= '1'; corrected_almost_empty <= '0'; elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty rd_count_int_corr <= 1; rd_count_int_corr_minus1 <= 0; corrected_empty <= '0'; corrected_almost_empty <= '1'; Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty rd_count_int_corr <= 2; rd_count_int_corr_minus1 <= 1; corrected_empty <= '0'; corrected_almost_empty <= '0'; else -- rddata valid and modify rd count from FIFO rd_count_int_corr <= rd_count_int+1; rd_count_int_corr_minus1 <= rd_count_int; corrected_empty <= '0'; corrected_almost_empty <= '0'; end if; end process CORRECT_RD_CNT; end imp;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_dma_afifo_autord.vhd -- Version: initial -- Description: -- This file contains the logic to generate a CoreGen call to create a -- asynchronous FIFO as part of the synthesis process of XST. This eliminates -- the need for multiple fixed netlists for various sizes and widths of FIFOs. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library lib_cdc_v1_0_2; library lib_fifo_v1_0_4; use lib_fifo_v1_0_4.async_fifo_fg; library axi_dma_v7_1_8; use axi_dma_v7_1_8.axi_dma_pkg.all; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- entity axi_dma_afifo_autord is generic ( C_DWIDTH : integer := 32; C_DEPTH : integer := 16; C_CNT_WIDTH : Integer := 5; C_USE_BLKMEM : Integer := 0 ; C_USE_AUTORD : Integer := 1; C_PRMRY_IS_ACLK_ASYNC : integer := 1; C_FAMILY : String := "virtex7" ); port ( -- Inputs AFIFO_Ainit : In std_logic; -- AFIFO_Wr_clk : In std_logic; -- AFIFO_Wr_en : In std_logic; -- AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); -- AFIFO_Rd_clk : In std_logic; -- AFIFO_Rd_en : In std_logic; -- AFIFO_Clr_Rd_Data_Valid : In std_logic; -- -- -- Outputs -- AFIFO_DValid : Out std_logic; -- AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); -- AFIFO_Full : Out std_logic; -- AFIFO_Empty : Out std_logic; -- AFIFO_Almost_full : Out std_logic; -- AFIFO_Almost_empty : Out std_logic; -- AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); -- AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); -- AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); -- AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); -- AFIFO_Rd_ack : Out std_logic -- ); end entity axi_dma_afifo_autord; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture imp of axi_dma_afifo_autord is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; -- Constant declarations ATTRIBUTE async_reg : STRING; -- Signal declarations signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0'); signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0'); signal rd_count_int : integer range 0 to C_DEPTH+1 := 0; signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0; signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0; Signal corrected_empty : std_logic := '0'; Signal corrected_almost_empty : std_logic := '0'; Signal sig_afifo_empty : std_logic := '0'; Signal sig_afifo_almost_empty : std_logic := '0'; -- backend fifo read ack sample and hold Signal sig_rddata_valid : std_logic := '0'; Signal hold_ff_q : std_logic := '0'; Signal ored_ack_ff_reset : std_logic := '0'; Signal autoread : std_logic := '0'; Signal sig_wrfifo_rdack : std_logic := '0'; Signal fifo_read_enable : std_logic := '0'; Signal first_write : std_logic := '0'; Signal first_read_cdc_tig : std_logic := '0'; Signal first_read1 : std_logic := '0'; Signal first_read2 : std_logic := '0'; signal AFIFO_Ainit_d1_cdc_tig : std_logic; signal AFIFO_Ainit_d2 : std_logic; --ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true"; --ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true"; -- Component declarations ----------------------------------------------------------------------------- -- Begin architecture ----------------------------------------------------------------------------- begin -- Bit ordering translations write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little -- endian. AFIFO_Rd_ack <= sig_wrfifo_rdack; AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to -- Big endian. AFIFO_Almost_empty <= corrected_almost_empty; GEN_EMPTY : if (C_USE_AUTORD = 1) generate begin AFIFO_Empty <= corrected_empty; end generate GEN_EMPTY; GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate begin AFIFO_Empty <= sig_afifo_empty; end generate GEN_EMPTY1; AFIFO_Wr_count <= wr_count_lil_end; AFIFO_Rd_count <= rd_count_lil_end; AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr, C_CNT_WIDTH+1); AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1, C_CNT_WIDTH+1); AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator fifo_read_enable <= AFIFO_Rd_en or autoread; ------------------------------------------------------------------------------- -- Instantiate the CoreGen FIFO -- -- NOTE: -- This instance refers to a wrapper file that interm will use the -- CoreGen FIFO Generator Async FIFO utility. -- ------------------------------------------------------------------------------- I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg generic map ( -- C_ALLOW_2N_DEPTH => 1, C_ALLOW_2N_DEPTH => 0, C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DWIDTH, C_ENABLE_RLOCS => 0, C_FIFO_DEPTH => C_DEPTH, C_HAS_ALMOST_EMPTY => 1, C_HAS_ALMOST_FULL => 1, C_HAS_RD_ACK => 1, C_HAS_RD_COUNT => 1, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_COUNT => 1, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_COUNT_WIDTH => C_CNT_WIDTH, C_RD_ERR_LOW => 0, C_USE_BLOCKMEM => C_USE_BLKMEM, C_WR_ACK_LOW => 0, C_WR_COUNT_WIDTH => C_CNT_WIDTH, C_WR_ERR_LOW => 0, C_SYNCHRONIZER_STAGE => C_FIFO_MTBF -- C_USE_EMBEDDED_REG => 1, -- 0 ; -- C_PRELOAD_REGS => 0, -- 0 ; -- C_PRELOAD_LATENCY => 1 -- 1 ; ) port Map ( Din => write_data_lil_end, Wr_en => AFIFO_Wr_en, Wr_clk => AFIFO_Wr_clk, Rd_en => fifo_read_enable, Rd_clk => AFIFO_Rd_clk, Ainit => AFIFO_Ainit, Dout => read_data_lil_end, Full => AFIFO_Full, Empty => sig_afifo_empty, Almost_full => AFIFO_Almost_full, Almost_empty => sig_afifo_almost_empty, Wr_count => wr_count_lil_end, Rd_count => rd_count_lil_end, Rd_ack => sig_wrfifo_rdack, Rd_err => open, -- Not used by axi_dma Wr_ack => open, -- Not used by axi_dma Wr_err => open -- Not used by axi_dma ); ---------------------------------------------------------------------------- -- Read Ack assert & hold logic (needed because: -- 1) The Async FIFO has to be read once to get valid -- data to the read data port (data is discarded). -- 2) The Read ack from the fifo is only asserted for 1 clock. -- 3) A signal is needed that indicates valid data is at the read -- port of the FIFO and has not yet been read. This signal needs -- to be held until the next read operation occurs or a clear -- signal is received. ored_ack_ff_reset <= fifo_read_enable or AFIFO_Ainit_d2 or AFIFO_Clr_Rd_Data_Valid; sig_rddata_valid <= hold_ff_q or sig_wrfifo_rdack; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ACK_HOLD_FLOP -- -- Process Description: -- Flop for registering the hold flag -- ------------------------------------------------------------- ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => AFIFO_Ainit, prmry_vect_in => (others => '0'), scndry_aclk => AFIFO_Rd_clk, scndry_resetn => '0', scndry_out => AFIFO_Ainit_d2, scndry_vect_out => open ); end generate ASYNC_CDC_SYNC; SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate AFIFO_Ainit_d2 <= AFIFO_Ainit; end generate SYNC_CDC_SYNC; -- IMP_SYNC_FLOP : process (AFIFO_Rd_clk) -- begin -- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then -- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit; -- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig; -- end if; -- end process IMP_SYNC_FLOP; IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk) begin if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then if (ored_ack_ff_reset = '1') then hold_ff_q <= '0'; else hold_ff_q <= sig_rddata_valid; end if; end if; end process IMP_ACK_HOLD_FLOP; -- I_ACK_HOLD_FF : FDRE -- port map( -- Q => hold_ff_q, -- C => AFIFO_Rd_clk, -- CE => '1', -- D => sig_rddata_valid, -- R => ored_ack_ff_reset -- ); -- generate auto-read enable. This keeps fresh data at the output -- of the FIFO whenever it is available. GEN_AUTORD1 : if C_USE_AUTORD = 1 generate autoread <= '1' -- create a read strobe when the when (sig_rddata_valid = '0' and -- output data is NOT valid sig_afifo_empty = '0') -- and the FIFO is not empty Else '0'; end generate GEN_AUTORD1; GEN_AUTORD2 : if C_USE_AUTORD = 0 generate process (AFIFO_Wr_clk) begin if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then if (AFIFO_Ainit = '0') then first_write <= '0'; elsif (AFIFO_Wr_en = '1') then first_write <= '1'; end if; end if; end process; IMP_SYNC_FLOP1 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => first_write, prmry_vect_in => (others => '0'), scndry_aclk => AFIFO_Rd_clk, scndry_resetn => '0', scndry_out => first_read1, scndry_vect_out => open ); process (AFIFO_Rd_clk) begin if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then if (AFIFO_Ainit_d2 = '0') then first_read2 <= '0'; elsif (sig_afifo_empty = '0') then first_read2 <= first_read1; end if; end if; end process; autoread <= first_read1 xor first_read2; end generate GEN_AUTORD2; rd_count_int <= CONV_INTEGER(rd_count_lil_end); ------------------------------------------------------------- -- Combinational Process -- -- Label: CORRECT_RD_CNT -- -- Process Description: -- This process corrects the FIFO Read Count output for the -- auto read function. -- ------------------------------------------------------------- CORRECT_RD_CNT : process (sig_rddata_valid, sig_afifo_empty, sig_afifo_almost_empty, rd_count_int) begin if (sig_rddata_valid = '0') then rd_count_int_corr <= 0; rd_count_int_corr_minus1 <= 0; corrected_empty <= '1'; corrected_almost_empty <= '0'; elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty rd_count_int_corr <= 1; rd_count_int_corr_minus1 <= 0; corrected_empty <= '0'; corrected_almost_empty <= '1'; Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty rd_count_int_corr <= 2; rd_count_int_corr_minus1 <= 1; corrected_empty <= '0'; corrected_almost_empty <= '0'; else -- rddata valid and modify rd count from FIFO rd_count_int_corr <= rd_count_int+1; rd_count_int_corr_minus1 <= rd_count_int; corrected_empty <= '0'; corrected_almost_empty <= '0'; end if; end process CORRECT_RD_CNT; end imp;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_dma_afifo_autord.vhd -- Version: initial -- Description: -- This file contains the logic to generate a CoreGen call to create a -- asynchronous FIFO as part of the synthesis process of XST. This eliminates -- the need for multiple fixed netlists for various sizes and widths of FIFOs. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library lib_cdc_v1_0_2; library lib_fifo_v1_0_4; use lib_fifo_v1_0_4.async_fifo_fg; library axi_dma_v7_1_8; use axi_dma_v7_1_8.axi_dma_pkg.all; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- entity axi_dma_afifo_autord is generic ( C_DWIDTH : integer := 32; C_DEPTH : integer := 16; C_CNT_WIDTH : Integer := 5; C_USE_BLKMEM : Integer := 0 ; C_USE_AUTORD : Integer := 1; C_PRMRY_IS_ACLK_ASYNC : integer := 1; C_FAMILY : String := "virtex7" ); port ( -- Inputs AFIFO_Ainit : In std_logic; -- AFIFO_Wr_clk : In std_logic; -- AFIFO_Wr_en : In std_logic; -- AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); -- AFIFO_Rd_clk : In std_logic; -- AFIFO_Rd_en : In std_logic; -- AFIFO_Clr_Rd_Data_Valid : In std_logic; -- -- -- Outputs -- AFIFO_DValid : Out std_logic; -- AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); -- AFIFO_Full : Out std_logic; -- AFIFO_Empty : Out std_logic; -- AFIFO_Almost_full : Out std_logic; -- AFIFO_Almost_empty : Out std_logic; -- AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); -- AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); -- AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); -- AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); -- AFIFO_Rd_ack : Out std_logic -- ); end entity axi_dma_afifo_autord; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture imp of axi_dma_afifo_autord is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; -- Constant declarations ATTRIBUTE async_reg : STRING; -- Signal declarations signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0'); signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0'); signal rd_count_int : integer range 0 to C_DEPTH+1 := 0; signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0; signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0; Signal corrected_empty : std_logic := '0'; Signal corrected_almost_empty : std_logic := '0'; Signal sig_afifo_empty : std_logic := '0'; Signal sig_afifo_almost_empty : std_logic := '0'; -- backend fifo read ack sample and hold Signal sig_rddata_valid : std_logic := '0'; Signal hold_ff_q : std_logic := '0'; Signal ored_ack_ff_reset : std_logic := '0'; Signal autoread : std_logic := '0'; Signal sig_wrfifo_rdack : std_logic := '0'; Signal fifo_read_enable : std_logic := '0'; Signal first_write : std_logic := '0'; Signal first_read_cdc_tig : std_logic := '0'; Signal first_read1 : std_logic := '0'; Signal first_read2 : std_logic := '0'; signal AFIFO_Ainit_d1_cdc_tig : std_logic; signal AFIFO_Ainit_d2 : std_logic; --ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true"; --ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true"; -- Component declarations ----------------------------------------------------------------------------- -- Begin architecture ----------------------------------------------------------------------------- begin -- Bit ordering translations write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little -- endian. AFIFO_Rd_ack <= sig_wrfifo_rdack; AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to -- Big endian. AFIFO_Almost_empty <= corrected_almost_empty; GEN_EMPTY : if (C_USE_AUTORD = 1) generate begin AFIFO_Empty <= corrected_empty; end generate GEN_EMPTY; GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate begin AFIFO_Empty <= sig_afifo_empty; end generate GEN_EMPTY1; AFIFO_Wr_count <= wr_count_lil_end; AFIFO_Rd_count <= rd_count_lil_end; AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr, C_CNT_WIDTH+1); AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1, C_CNT_WIDTH+1); AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator fifo_read_enable <= AFIFO_Rd_en or autoread; ------------------------------------------------------------------------------- -- Instantiate the CoreGen FIFO -- -- NOTE: -- This instance refers to a wrapper file that interm will use the -- CoreGen FIFO Generator Async FIFO utility. -- ------------------------------------------------------------------------------- I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg generic map ( -- C_ALLOW_2N_DEPTH => 1, C_ALLOW_2N_DEPTH => 0, C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DWIDTH, C_ENABLE_RLOCS => 0, C_FIFO_DEPTH => C_DEPTH, C_HAS_ALMOST_EMPTY => 1, C_HAS_ALMOST_FULL => 1, C_HAS_RD_ACK => 1, C_HAS_RD_COUNT => 1, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_COUNT => 1, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_COUNT_WIDTH => C_CNT_WIDTH, C_RD_ERR_LOW => 0, C_USE_BLOCKMEM => C_USE_BLKMEM, C_WR_ACK_LOW => 0, C_WR_COUNT_WIDTH => C_CNT_WIDTH, C_WR_ERR_LOW => 0, C_SYNCHRONIZER_STAGE => C_FIFO_MTBF -- C_USE_EMBEDDED_REG => 1, -- 0 ; -- C_PRELOAD_REGS => 0, -- 0 ; -- C_PRELOAD_LATENCY => 1 -- 1 ; ) port Map ( Din => write_data_lil_end, Wr_en => AFIFO_Wr_en, Wr_clk => AFIFO_Wr_clk, Rd_en => fifo_read_enable, Rd_clk => AFIFO_Rd_clk, Ainit => AFIFO_Ainit, Dout => read_data_lil_end, Full => AFIFO_Full, Empty => sig_afifo_empty, Almost_full => AFIFO_Almost_full, Almost_empty => sig_afifo_almost_empty, Wr_count => wr_count_lil_end, Rd_count => rd_count_lil_end, Rd_ack => sig_wrfifo_rdack, Rd_err => open, -- Not used by axi_dma Wr_ack => open, -- Not used by axi_dma Wr_err => open -- Not used by axi_dma ); ---------------------------------------------------------------------------- -- Read Ack assert & hold logic (needed because: -- 1) The Async FIFO has to be read once to get valid -- data to the read data port (data is discarded). -- 2) The Read ack from the fifo is only asserted for 1 clock. -- 3) A signal is needed that indicates valid data is at the read -- port of the FIFO and has not yet been read. This signal needs -- to be held until the next read operation occurs or a clear -- signal is received. ored_ack_ff_reset <= fifo_read_enable or AFIFO_Ainit_d2 or AFIFO_Clr_Rd_Data_Valid; sig_rddata_valid <= hold_ff_q or sig_wrfifo_rdack; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ACK_HOLD_FLOP -- -- Process Description: -- Flop for registering the hold flag -- ------------------------------------------------------------- ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => AFIFO_Ainit, prmry_vect_in => (others => '0'), scndry_aclk => AFIFO_Rd_clk, scndry_resetn => '0', scndry_out => AFIFO_Ainit_d2, scndry_vect_out => open ); end generate ASYNC_CDC_SYNC; SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate AFIFO_Ainit_d2 <= AFIFO_Ainit; end generate SYNC_CDC_SYNC; -- IMP_SYNC_FLOP : process (AFIFO_Rd_clk) -- begin -- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then -- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit; -- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig; -- end if; -- end process IMP_SYNC_FLOP; IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk) begin if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then if (ored_ack_ff_reset = '1') then hold_ff_q <= '0'; else hold_ff_q <= sig_rddata_valid; end if; end if; end process IMP_ACK_HOLD_FLOP; -- I_ACK_HOLD_FF : FDRE -- port map( -- Q => hold_ff_q, -- C => AFIFO_Rd_clk, -- CE => '1', -- D => sig_rddata_valid, -- R => ored_ack_ff_reset -- ); -- generate auto-read enable. This keeps fresh data at the output -- of the FIFO whenever it is available. GEN_AUTORD1 : if C_USE_AUTORD = 1 generate autoread <= '1' -- create a read strobe when the when (sig_rddata_valid = '0' and -- output data is NOT valid sig_afifo_empty = '0') -- and the FIFO is not empty Else '0'; end generate GEN_AUTORD1; GEN_AUTORD2 : if C_USE_AUTORD = 0 generate process (AFIFO_Wr_clk) begin if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then if (AFIFO_Ainit = '0') then first_write <= '0'; elsif (AFIFO_Wr_en = '1') then first_write <= '1'; end if; end if; end process; IMP_SYNC_FLOP1 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => first_write, prmry_vect_in => (others => '0'), scndry_aclk => AFIFO_Rd_clk, scndry_resetn => '0', scndry_out => first_read1, scndry_vect_out => open ); process (AFIFO_Rd_clk) begin if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then if (AFIFO_Ainit_d2 = '0') then first_read2 <= '0'; elsif (sig_afifo_empty = '0') then first_read2 <= first_read1; end if; end if; end process; autoread <= first_read1 xor first_read2; end generate GEN_AUTORD2; rd_count_int <= CONV_INTEGER(rd_count_lil_end); ------------------------------------------------------------- -- Combinational Process -- -- Label: CORRECT_RD_CNT -- -- Process Description: -- This process corrects the FIFO Read Count output for the -- auto read function. -- ------------------------------------------------------------- CORRECT_RD_CNT : process (sig_rddata_valid, sig_afifo_empty, sig_afifo_almost_empty, rd_count_int) begin if (sig_rddata_valid = '0') then rd_count_int_corr <= 0; rd_count_int_corr_minus1 <= 0; corrected_empty <= '1'; corrected_almost_empty <= '0'; elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty rd_count_int_corr <= 1; rd_count_int_corr_minus1 <= 0; corrected_empty <= '0'; corrected_almost_empty <= '1'; Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty rd_count_int_corr <= 2; rd_count_int_corr_minus1 <= 1; corrected_empty <= '0'; corrected_almost_empty <= '0'; else -- rddata valid and modify rd count from FIFO rd_count_int_corr <= rd_count_int+1; rd_count_int_corr_minus1 <= rd_count_int; corrected_empty <= '0'; corrected_almost_empty <= '0'; end if; end process CORRECT_RD_CNT; end imp;
library verilog; use verilog.vl_types.all; entity Counter16anDisplay_vlg_sample_tst is port( clear : in vl_logic; clk : in vl_logic; enable : in vl_logic; sampler_tx : out vl_logic ); end Counter16anDisplay_vlg_sample_tst;
package pkg3 is type my_rec is record adr : bit_vector (7 downto 0); end record; end pkg3; use work.pkg3.all; entity ent3 is port (v : out my_rec; b : in bit); end ent3; architecture behav of ent3 is begin v.adr <= (others => b); end behav; entity top3 is end top3; use work.pkg3.all; architecture behav of top3 is signal s : bit_vector (7 downto 0); signal b : bit; begin dut : entity work.ent3 port map ( -- ERROR: missing 1 downto 0! v.adr (3 downto 2) => s (3 downto 2), v.adr (7 downto 6) => s (7 downto 6), b => b); b <= '0'; end behav;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity alu is port ( input_1 : in std_logic_vector (31 downto 0); input_2 : in std_logic_vector (31 downto 0); funct : in std_logic_vector (4 downto 0); flags_current : in std_logic_vector(3 downto 0); output : out std_logic_vector (31 downto 0); flags_next : out std_logic_vector (3 downto 0); flags_update : out std_logic_vector (1 downto 0)); -- 0:none 1:NZ 2:NZC 3:NZCV end alu; architecture Behavioral of alu is component mul32 is port ( a : in std_logic_vector (31 downto 0); b : in std_logic_vector (31 downto 0); p : out std_logic_vector (31 downto 0)); end component mul32; component shift is port ( mode : in std_logic_vector (1 downto 0);--0:LSLS 1:LSRS 2:ASRS 3:RORS shift : in std_logic_vector (4 downto 0); input : in std_logic_vector (31 downto 0); carry : out std_logic; output : out std_logic_vector (31 downto 0)); end component shift; component add32 is port ( a : in std_logic_vector(31 downto 0); b : in std_logic_vector(31 downto 0); cin : in std_logic; sum : out std_logic_vector(31 downto 0); cout : out std_logic); end component add32; signal zero, carry_out, overflow : std_logic; signal output_mux, output_mul, output_shift, output_add, output_mvn : std_logic_vector(31 downto 0); signal carry_mux, carry_shift, carry_in_add, carry_add : std_logic; signal shift_mode : std_logic_vector(1 downto 0); signal input_add_2 : std_logic_vector(31 downto 0); begin --FIX OP CODE --00000 AND ok --00001 EOR ok --00010 LSL ok --00011 LSR ok --00100 ASR ok --00101 ADC ok, V not implemented --00110 SBC ok, V not implemented --00111 ROR ok --01000 TST --01001 NEG --01010 CMP ok, V not implemented, same as sub, not implemented not outputting result --01011 CMN ok, V not implemented, same as add, not implemented not outputting result --01100 ORR ok --01101 MUL ok --01110 BIC ok --01111 MVN ok --10000 MOV ok --10001 ADD ok, V not implemented --10010 SUB ok, V not implemented mul_block : mul32 port map ( a => input_1 , b => input_2 , p => output_mul ); shift_mode <= "00" when funct = "00010" else "01" when funct = "00011" else "10" when funct = "00100" else "11"; shift_block : shift port map ( mode => shift_mode , shift => input_2( 4 downto 0) , input => input_1 , carry => carry_shift , output => output_shift ); input_add_2 <= input_2 when funct = "00101" or funct = "10001" or funct = "01011" else std_logic_vector(unsigned(not(input_2)) + 1); carry_in_add <= flags_current(1) when funct = "00101" or funct = "00110" else '0'; add_block : add32 port map ( a => input_1 , b => input_add_2 , cin => carry_in_add , sum => output_add , cout => carry_add ); output_mvn <= not( input_1 ); output_mux <= input_1 and input_2 when funct = "00000" else input_1 xor input_2 when funct = "00001" else input_1 or input_2 when funct = "01100" else input_1 and not(input_2) when funct = "01110" else output_mul when funct = "01101" else output_shift when funct = "00010" or funct = "00011" or funct = "00100" or funct = "00111" else output_add when funct = "00101" or funct = "10001" or funct = "00110" or funct = "10010" or funct = "01011" or funct = "01010" else -- wrong "01011" , wrong "01010" output_mvn when funct = "01111" else input_1 when funct = "10000" else (others=> '0'); output <= output_mux; zero <= not ( output_mux(31) or output_mux(30) or output_mux(29) or output_mux(28) or output_mux(27) or output_mux(26) or output_mux(25) or output_mux(24) or output_mux(23) or output_mux(22) or output_mux(21) or output_mux(20) or output_mux(19) or output_mux(18) or output_mux(17) or output_mux(16) or output_mux(15) or output_mux(14) or output_mux(13) or output_mux(12) or output_mux(11) or output_mux(10) or output_mux( 9) or output_mux( 8) or output_mux( 7) or output_mux( 6) or output_mux( 5) or output_mux( 4) or output_mux( 3) or output_mux( 2) or output_mux( 1) or output_mux( 0) ); carry_mux <= carry_shift when funct = "00010" or funct = "00011" or funct = "00100" or funct = "00111" else carry_add when funct = "00101" or funct = "10001" or funct = "00110" or funct = "10010" or funct = "01011" or funct = "01010" else '0'; overflow <= '1' when funct = "" else '0'; flags_next <= output_mux(31) & zero & carry_mux & overflow; flags_update <= "01" when funct = "01101" or funct = "00000" or funct = "00001" or funct = "01100" or funct = "01110" or funct = "01000" or funct = "01111" or funct = "10000" else "10" when funct = "00010" or funct = "00011" or funct = "00100" or funct = "00111" else "11" when funct = "00101" or funct = "00110" or funct = "01001" or funct = "01010" or funct = "01011" or funct = "10001" or funct = "10010" else "00"; end Behavioral;
library ieee; use ieee.std_logic_1164.all; use work.cryptopan.all; entity sbsr_tb is end sbsr_tb; architecture tb of sbsr_tb is component subbytesshiftrows port ( bytes_in : in s_vector; bytes_out : out s_vector; clk : in std_logic; reset : in std_logic); end component; component mixcolumns port ( bytes_in : in s_vector; bytes_out : out s_vector; clk : in std_logic; reset : in std_logic); end component; signal clk : std_logic; signal reset : std_logic; signal bytes_in : s_vector; signal bytes_out : s_vector; signal mix_bytes_out : s_vector; begin -- tb CLKGEN: process begin -- process CLKGEN clk <= '1'; wait for 5 ns; clk <= '0'; wait for 5 ns; end process CLKGEN; SUBBYTESSHIFTROWS0: subbytesshiftrows port map ( bytes_in => bytes_in, bytes_out => bytes_out, clk => clk, reset => reset); MIX0: mixcolumns port map ( bytes_in => bytes_out, bytes_out => mix_bytes_out, clk => clk, reset => reset); TB: process begin -- process TB reset <= '1'; wait for 55 ns; reset <= '0'; wait for 20 ns; bytes_in(0) <= X"19"; bytes_in(1) <= X"A0"; bytes_in(2) <= X"9A"; bytes_in(3) <= X"E9"; bytes_in(4) <= X"3D"; bytes_in(5) <= X"F4"; bytes_in(6) <= X"C6"; bytes_in(7) <= X"F8"; bytes_in(8) <= X"E3"; bytes_in(9) <= X"E2"; bytes_in(10) <= X"8D"; bytes_in(11) <= X"48"; bytes_in(12) <= X"BE"; bytes_in(13) <= X"2B"; bytes_in(14) <= X"2A"; bytes_in(15) <= X"08"; wait for 10 ns; bytes_in(0) <= X"A4"; bytes_in(1) <= X"68"; bytes_in(2) <= X"6B"; bytes_in(3) <= X"02"; bytes_in(4) <= X"9C"; bytes_in(5) <= X"9F"; bytes_in(6) <= X"5B"; bytes_in(7) <= X"6A"; bytes_in(8) <= X"7F"; bytes_in(9) <= X"35"; bytes_in(10) <= X"EA"; bytes_in(11) <= X"50"; bytes_in(12) <= X"F2"; bytes_in(13) <= X"2B"; bytes_in(14) <= X"43"; bytes_in(15) <= X"49"; wait for 10 ns; wait; end process TB; end tb;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:07:54 09/29/2014 -- Design Name: -- Module Name: C:/Users/ael10jso/Xilinx/embedded_bruteforce/brutus_system/ISE/fsl_test/tb_fsl_test.vhd -- Project Name: fsl_test -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: test -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tb_fsl_test IS END tb_fsl_test; ARCHITECTURE behavior OF tb_fsl_test IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT test PORT( FSL_Clk : IN std_logic; FSL_Rst : IN std_logic; FSL_S_Clk : IN std_logic; FSL_S_Read : OUT std_logic; FSL_S_Data : IN std_logic_vector(0 to 31); FSL_S_Control : IN std_logic; FSL_S_Exists : IN std_logic; FSL_M_Clk : IN std_logic; FSL_M_Write : OUT std_logic; FSL_M_Data : OUT std_logic_vector(0 to 31); FSL_M_Control : OUT std_logic; FSL_M_Full : IN std_logic ); END COMPONENT; --Inputs signal FSL_Clk : std_logic := '0'; signal FSL_Rst : std_logic := '0'; signal FSL_S_Clk : std_logic := '0'; signal FSL_S_Data : std_logic_vector(0 to 31) := (others => '0'); signal FSL_S_Control : std_logic := '0'; signal FSL_S_Exists : std_logic := '0'; signal FSL_M_Clk : std_logic := '0'; signal FSL_M_Full : std_logic := '0'; --Outputs signal FSL_S_Read : std_logic; signal FSL_M_Write : std_logic; signal FSL_M_Data : std_logic_vector(0 to 31); signal FSL_M_Control : std_logic; -- Clock period definitions constant FSL_Clk_period : time := 10 ns; constant FSL_S_Clk_period : time := 10 ns; constant FSL_M_Clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: test PORT MAP ( FSL_Clk => FSL_Clk, FSL_Rst => FSL_Rst, FSL_S_Clk => FSL_S_Clk, FSL_S_Read => FSL_S_Read, FSL_S_Data => FSL_S_Data, FSL_S_Control => FSL_S_Control, FSL_S_Exists => FSL_S_Exists, FSL_M_Clk => FSL_M_Clk, FSL_M_Write => FSL_M_Write, FSL_M_Data => FSL_M_Data, FSL_M_Control => FSL_M_Control, FSL_M_Full => FSL_M_Full ); -- Clock process definitions FSL_Clk_process :process begin FSL_Clk <= '0'; wait for FSL_Clk_period/2; FSL_Clk <= '1'; wait for FSL_Clk_period/2; end process; FSL_S_Clk_process :process begin FSL_S_Clk <= '0'; wait for FSL_S_Clk_period/2; FSL_S_Clk <= '1'; wait for FSL_S_Clk_period/2; end process; FSL_M_Clk_process :process begin FSL_M_Clk <= '0'; wait for FSL_M_Clk_period/2; FSL_M_Clk <= '1'; wait for FSL_M_Clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for FSL_Clk_period*10; -- insert stimulus here wait; end process; END;
library IEEE; use IEEE.STD_LOGIC_1164.all; entity TrafficLightsTop is port(CLOCK_50 : in std_logic; KEY : in std_logic_vector(0 downto 0); SW : in std_logic_vector(0 downto 0); LEDR : out std_logic_vector(17 downto 0)); end TrafficLightsTop; architecture Shell of TrafficLightsTop is signal s_clk1Hz : std_logic; signal s_newTime, s_timeExp : std_logic; signal s_timeVal : std_logic_vector(7 downto 0); signal s_yBlink : std_logic; signal s_yellow1, s_yellow2 : std_logic; begin clk_div_1hz : entity work.ClkDividerN(RTL) generic map(divFactor => 50000000) port map(clkIn => CLOCK_50, clkOut => s_clk1Hz); main_fsm : entity work.TrafficLightsFSM(Behavioral) port map(reset => not KEY(0), clk => s_clk1Hz, intermit => SW(0), newTime => s_newTime, timeVal => s_timeVal, timeExp => s_timeExp, yBlink => s_yBlink, red1 => LEDR(15), yellow1 => s_yellow1, green1 => LEDR(17), red2 => LEDR(2), yellow2 => s_yellow2, green2 => LEDR(0)); LEDR(16) <= s_yellow1 and (not s_yBlink or s_clk1Hz); LEDR(1) <= s_yellow2 and (not s_yBlink or s_clk1Hz); timer_fsm : entity work.TimerAuxFSM(Behavioral) port map(reset => not KEY(0), clk => not s_clk1Hz, newTime => s_newTime, timeVal => s_timeVal, timeExp => s_timeExp); end Shell;
-- fft16.vhd -- -- Created on: 15 Jul 2017 -- Author: Fabian Meyer -- -- Integration component for 16-point FFT. Implements pipelining of data and timing between components. -- This architecture is based on the paper of George Slade: -- https://www.researchgate.net/publication/235995761_The_Fast_Fourier_Transform_in_Hardware_A_Tutorial_Based_on_an_FPGA_Implementation library ieee; library work; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.fft_helpers.all; entity fft16 is generic(RSTDEF: std_logic := '0'); port(rst: in std_logic; -- reset, RSTDEF active clk: in std_logic; -- clock, rising edge swrst: in std_logic; -- software reset, RSTDEF active en: in std_logic; -- enable, high active start: in std_logic; -- start FFT, high active set: in std_logic; -- load FFT with values, high active get: in std_logic; -- read FFT results, high active din: in complex; -- datain for loading FFT done: out std_logic; -- FFT is done, active high dout: out complex); -- data out for reading results end fft16; architecture behavioral of fft16 is -- import addr_gen component component addr_gen generic(RSTDEF: std_logic := '0'; FFTEXP: natural := 4); port(rst: in std_logic; -- reset, RSTDEF active clk: in std_logic; -- clock, rising edge swrst: in std_logic; -- software reset, RSTDEF active en: in std_logic; -- enable, high active lvl: in std_logic_vector(FFTEXP-2 downto 0); -- iteration level of butterflies bfno: in std_logic_vector(FFTEXP-2 downto 0); -- butterfly number in current level addra1: out std_logic_vector(FFTEXP-1 downto 0); -- address1 for membank A addra2: out std_logic_vector(FFTEXP-1 downto 0); -- address2 for membank A en_wrta: out std_logic; -- write enable for membank A, high active addrb1: out std_logic_vector(FFTEXP-1 downto 0); -- address1 for membank B addrb2: out std_logic_vector(FFTEXP-1 downto 0); -- address2 for membank B en_wrtb: out std_logic; -- write enable for membank B, high active addrtf: out std_logic_vector(FFTEXP-2 downto 0)); -- twiddle factor address end component; -- import membank component component membank generic(RSTDEF: std_logic := '0'; FFTEXP: natural := 4); port(rst: in std_logic; -- reset, RSTDEF active clk: in std_logic; -- clock, rising edge swrst: in std_logic; -- software reset, RSTDEF active en: in std_logic; -- enable, high active addr1: in std_logic_vector(FFTEXP-1 downto 0); -- address1 addr2: in std_logic_vector(FFTEXP-1 downto 0); -- address2 en_wrt: in std_logic; -- write enable for bank1, high active din1: in complex; -- input1 that will be stored din2: in complex; -- input2 that will be stored dout1: out complex; -- output1 that is read from memory dout2: out complex); -- output2 that is read from memory end component; -- import butterfly component component butterfly generic(RSTDEF: std_logic := '0'); port(rst: in std_logic; -- reset, RSTDEF active clk: in std_logic; -- clock, rising edge swrst: in std_logic; -- software reset, RSTDEF active en: in std_logic; -- enable, high active din1: in complex; -- first complex in val din2: in complex; -- second complex in val w: in complex; -- twiddle factor dout1: out complex; -- first complex out val dout2: out complex); -- second complex out val end component; -- import delay elemnt for logic vectors component delay_vec generic(RSTDEF: std_logic := '0'; DATALEN: natural := 8; DELAYLEN: natural := 8); port(rst: in std_logic; -- reset, RSTDEF active clk: in std_logic; -- clock, rising edge swrst: in std_logic; -- software reset, RSTDEF active en: in std_logic; -- enable, high active din: in std_logic_vector(DATALEN-1 downto 0); -- data in dout: out std_logic_vector(DATALEN-1 downto 0)); -- data out end component; -- import delay element for bits component delay_bit generic(RSTDEF: std_logic := '0'; DELAYLEN: natural := 8); port(rst: in std_logic; -- reset, RSTDEF active clk: in std_logic; -- clock, rising edge swrst: in std_logic; -- software reset, RSTDEF active en: in std_logic; -- enable, high active din: in std_logic; -- data in dout: out std_logic); -- data out end component; -- import twiddle factor component component tf16 generic(RSTDEF: std_logic := '0'; FFTEXP: natural := 4); port(rst: in std_logic; -- reset, RSTDEF active clk: in std_logic; -- clock, rising edge swrst: in std_logic; -- software reset, RSTDEF active en: in std_logic; -- enable, high active addr: in std_logic_vector(FFTEXP-2 downto 0); -- address of twiddle factor w: out complex); -- twiddle factor end component; -- define this FFT as 16-point (exponent = 4) constant FFTEXP: natural := 4; -- delay write address by 3 cycles constant DELWADDR: natural := 3; constant DELENAGU: natural := 3; constant DELENDFFT: natural := 1; -- INTERNALS -- ========= -- define states for FSM of FFT type TState is (SIDLE, SSET, SGET, SRUN); signal state: TState := SIDLE; -- intermediate signal for dout; used for muxing signal dout_tmp: complex := COMPZERO; -- signal to control enable of agu; used for muxing signal en_agu_con: std_logic := '0'; -- signal to control software reset of agu; used for muxing signal swrst_agu_con: std_logic := not RSTDEF; -- address counter for get and set signal addr_cnt: unsigned(FFTEXP downto 0) := (others => '0'); -- bit reversed address; async set from addr_cnt signal addr_rev: std_logic_vector(FFTEXP-1 downto 0); -- ====== -- INPUTS -- ====== -- data in port of delay for end fft signal signal din_end_fft: std_logic := '0'; -- enable signal for agu signal en_agu: std_logic := '0'; -- current FFT stage / level for agu signal lvl_agu: std_logic_vector(FFTEXP-2 downto 0) := (others => '0'); -- current butterfly number within current stage for agu signal bfno_agu: std_logic_vector(FFTEXP-2 downto 0) := (others => '0'); -- address signals for membank A signal addr1_mema: std_logic_vector(FFTEXP-1 downto 0) := (others => '0'); signal addr2_mema: std_logic_vector(FFTEXP-1 downto 0) := (others => '0'); -- write signal for membank A signal en_wrt_mema: std_logic := '0'; -- data in ports for membank A signal din1_mema: complex := COMPZERO; signal din2_mema: complex := COMPZERO; -- address signals for membank B signal addr1_memb: std_logic_vector(FFTEXP-1 downto 0) := (others => '0'); signal addr2_memb: std_logic_vector(FFTEXP-1 downto 0) := (others => '0'); -- write signal for membank B signal en_wrt_memb: std_logic := '0'; -- data in ports for membank B signal din1_memb: complex := COMPZERO; signal din2_memb: complex := COMPZERO; -- data in ports for butterfly signal din1_bf: complex := COMPZERO; signal din2_bf: complex := COMPZERO; -- twiddle factor for butterfly signal w_bf: complex := COMPZERO; -- address signal for twiddle factor unit signal addr_tf: std_logic_vector(FFTEXP-2 downto 0) := (others => '0'); -- data in ports for write address delay signal din_waddr1: std_logic_vector(FFTEXP-1 downto 0) := (others => '0'); signal din_waddr2: std_logic_vector(FFTEXP-1 downto 0) := (others => '0'); -- data in port for enable agu delay signal din_enagu: std_logic := '0'; -- ======= -- OUTPUTS -- ======= -- data out port of delay for end fft signal signal dout_end_fft: std_logic; -- address signals from agu for membank A signal addra1_agu: std_logic_vector(FFTEXP-1 downto 0); signal addra2_agu: std_logic_vector(FFTEXP-1 downto 0); signal en_wrta_agu: std_logic; -- address signals from agu for membank B signal addrb1_agu: std_logic_vector(FFTEXP-1 downto 0); signal addrb2_agu: std_logic_vector(FFTEXP-1 downto 0); signal en_wrtb_agu: std_logic; -- address signal for twiddle factor signal addrtf_agu: std_logic_vector(FFTEXP-2 downto 0); -- software reset signal for agu signal swrst_agu: std_logic; --data out ports for membank A signal dout1_mema: complex; signal dout2_mema: complex; --data out ports for membank B signal dout1_memb: complex; signal dout2_memb: complex; -- data out ports for butterfly signal dout1_bf: complex; signal dout2_bf: complex; -- data out port for twiddle factor unit signal w_tf: complex; -- data out ports for write address delay signal dout_waddr1: std_logic_vector(FFTEXP-1 downto 0); signal dout_waddr2: std_logic_vector(FFTEXP-1 downto 0); -- data out port for enable agu delay signal dout_enagu: std_logic; begin dout <= dout_tmp; -- done is set if we are in IDLE state done <= '1' when state = SIDLE else '0'; -- multiplex enable signal for agu en_agu <= '0' when en = '0' else en_agu_con; -- multiplex swrst signal for agu swrst_agu <= swrst when swrst = RSTDEF else swrst_agu_con; -- calc bit reversed address gen_rev: for i in 0 to FFTEXP-1 generate addr_rev(i) <= std_logic(addr_cnt(FFTEXP-1 - i)); end generate; process(clk, rst) is -- reset this component procedure reset is begin state <= SIDLE; -- reset agu lvl_agu <= (others => '0'); bfno_agu <= (others => '0'); en_agu_con <= '0'; swrst_agu_con <= not RSTDEF; -- reset membank A addr1_mema <= (others => '0'); addr2_mema <= (others => '0'); din1_mema <= COMPZERO; din2_mema <= COMPZERO; en_wrt_mema <= '0'; -- reset membank B addr1_memb <= (others => '0'); addr2_memb <= (others => '0'); din1_memb <= COMPZERO; din2_memb <= COMPZERO; en_wrt_memb <= '0'; -- reset butterfly din1_bf <= COMPZERO; din2_bf <= COMPZERO; w_bf <= COMPZERO; -- reset twiddle factor unit addr_tf <= (others => '0'); -- reset write address delay element din_waddr1 <= (others => '0'); din_waddr2 <= (others => '0'); -- reset enable agu delay element din_enagu <= '0'; --reset address counter addr_cnt <= (others => '0'); -- reset delay for end_fft din_end_fft <= '0'; end; begin if rst = RSTDEF then reset; elsif rising_edge(clk) then if swrst = RSTDEF then reset; elsif en = '1' then -- process state machine case state is when SIDLE => if set = '1' then -- "set" signal received state <= SSET; -- store transmitted values in membank A in -- bit reversed order -- already store first value from din addr_cnt <= addr_cnt + 1; addr1_mema <= addr_rev; din1_mema <= din; -- also set addr2 and din2 and leave them so they -- will not overwrite any values in the process addr2_mema <= addr_rev; din2_mema <= din; -- enable write mode for membank A en_wrt_mema <= '1'; elsif get = '1' then -- "get" signal received state <= SGET; -- read values from membank A in normal order -- addr_cnt defines address to be read -- membanks should always be in read mode when -- FSM is idle addr_cnt <= addr_cnt + 1; addr1_mema <= std_logic_vector(addr_cnt(FFTEXP-1 downto 0)); elsif start = '1' then -- "start" signal received state <= SRUN; -- enable agu en_agu_con <= '1'; end if; when SSET => -- increment address count -- bit reversed address will be updated automatically addr_cnt <= addr_cnt + 1; addr1_mema <= addr_rev; din1_mema <= din; -- if counter had overflow go back to idle state -- and reset all used resources if addr_cnt(FFTEXP) = '1' then -- reset membank addresses and data in ports addr1_mema <= (others => '0'); din1_mema <= COMPZERO; addr2_mema <= (others => '0'); din2_mema <= COMPZERO; -- disable write mode on membank A en_wrt_mema <= '0'; -- reset addr_cnt addr_cnt <= (others => '0'); -- go back to idle mode state <= SIDLE; end if; when SGET => -- increment address count -- this is the address that we read from addr_cnt <= addr_cnt + 1; addr1_mema <= std_logic_vector(addr_cnt(FFTEXP-1 downto 0)); dout_tmp <= dout1_mema; -- if counter had overflow go back to idle state -- and reset all used resources if addr_cnt(FFTEXP) = '1' and addr_cnt(0) = '1' then -- reset addr1 of membank A addr1_mema <= (others => '0'); -- reset addr_cnt addr_cnt <= (others => '0'); -- go back to idle mode state <= SIDLE; end if; when SRUN => -- ================ -- BEGIN execute pipeline -- apply write enables from agu en_wrt_mema <= en_wrta_agu; en_wrt_memb <= en_wrtb_agu; -- apply address twiddle factor addr_tf <= addrtf_agu; -- apply twiddle factor w_bf <= w_tf; -- apply addresses for membanks and -- values from membanks if en_wrta_agu = '1' then -- membank A is in write mode -- feed address of A into delay element din_waddr1 <= addra1_agu; din_waddr2 <= addra2_agu; -- get address for A from delay element addr1_mema <= dout_waddr1; addr2_mema <= dout_waddr2; -- get address directly from AGU addr1_memb <= addrb1_agu; addr2_memb <= addrb2_agu; -- apply values from membank B to butterfly din1_bf <= dout1_memb; din2_bf <= dout2_memb; -- apply values from butterfly to membank A din1_mema <= dout1_bf; din2_mema <= dout2_bf; else -- membank B is in write mode -- feed address of B into delay element din_waddr1 <= addrb1_agu; din_waddr2 <= addrb2_agu; -- get address for mema from delay element addr1_memb <= dout_waddr1; addr2_memb <= dout_waddr2; -- get address directly from AGU addr1_mema <= addra1_agu; addr2_mema <= addra2_agu; -- apply values from membank A to butterfly din1_bf <= dout1_mema; din2_bf <= dout2_mema; -- apply values from butterfly to membank B din1_memb <= dout1_bf; din2_memb <= dout2_bf; end if; -- END execute pipeline -- ==================== -- din_enagu only stays high for one cycle din_enagu <= '0'; -- din_end_fft only stays high for one cycle din_end_fft <= '0'; -- if agu is still enabled keep incrementing butterflies if en_agu_con = '1' then bfno_agu <= std_logic_vector(unsigned(bfno_agu) + 1); end if; -- if we have reached last butterfly wait for pipeline -- to finish if bfno_agu = "111" then en_agu_con <= '0'; din_enagu <= '1'; end if; -- this will only be the case if we have reached last butterfly -- and agu was disabled if dout_enagu = '1' then -- reset butterfly number bfno_agu <= (others => '0'); if lvl_agu = "011" then -- set end_fft din_end_fft <= '1'; --swrst_agu_con <= RSTDEF; else -- go to next level -- enable agu again lvl_agu <= std_logic_vector(unsigned(lvl_agu) + 1); en_agu_con <= '1'; end if; end if; -- this will only be the case if we have reached last butterfly -- and last level if dout_end_fft = '1' then -- final level was reached: we are done -- reset all internal states -- membanks not included! state <= SIDLE; reset; end if; end case; end if; end if; end process; -- create instance of address generation unit agu: addr_gen generic map(RSTDEF => RSTDEF, FFTEXP => FFTEXP) port map(rst => rst, clk => clk, swrst => swrst_agu, en => en_agu, lvl => lvl_agu, bfno => bfno_agu, addra1 => addra1_agu, addra2 => addra2_agu, en_wrta => en_wrta_agu, addrb1 => addrb1_agu, addrb2 => addrb2_agu, en_wrtb => en_wrtb_agu, addrtf => addrtf_agu); -- create instance of twiddle factor unit tfu: tf16 generic map(RSTDEF => RSTDEF, FFTEXP => FFTEXP) port map(rst => rst, clk => clk, swrst => swrst, en => en, addr => addr_tf, w => w_tf); -- create instance of memory bank A mem_a: membank generic map(RSTDEF => RSTDEF, FFTEXP => FFTEXP) port map(rst => rst, clk => clk, swrst => swrst, en => en, addr1 => addr1_mema, addr2 => addr2_mema, en_wrt => en_wrt_mema, din1 => din1_mema, din2 => din2_mema, dout1 => dout1_mema, dout2 => dout2_mema); -- create instance of memory bank B mem_b: membank generic map(RSTDEF => RSTDEF, FFTEXP => FFTEXP) port map(rst => rst, clk => clk, swrst => swrst, en => en, addr1 => addr1_memb, addr2 => addr2_memb, en_wrt => en_wrt_memb, din1 => din1_memb, din2 => din2_memb, dout1 => dout1_memb, dout2 => dout2_memb); -- create instance of butterfly unit bfu: butterfly generic map(RSTDEF => RSTDEF) port map(rst => rst, clk => clk, swrst => swrst, en => en, din1 => din1_bf, din2 => din2_bf, w => w_bf, dout1 => dout1_bf, dout2 => dout2_bf); -- create instance of delay unit for write address 1 del_waddr1: delay_vec generic map(RSTDEF => RSTDEF, DATALEN => FFTEXP, DELAYLEN => DELWADDR) port map(rst => rst, clk => clk, swrst => swrst, en => en, din => din_waddr1, dout => dout_waddr1); -- create instance of delay unit for write address 1 del_waddr2: delay_vec generic map(RSTDEF => RSTDEF, DATALEN => FFTEXP, DELAYLEN => DELWADDR) port map(rst => rst, clk => clk, swrst => swrst, en => en, din => din_waddr2, dout => dout_waddr2); -- create instance of delay unit for enable signal of agu del_enagu: delay_bit generic map(RSTDEF => RSTDEF, DELAYLEN => DELENAGU) port map(rst => rst, clk => clk, swrst => swrst, en => en, din => din_enagu, dout => dout_enagu); del_end_fft: delay_bit generic map(RSTDEF => RSTDEF, DELAYLEN => DELENDFFT) port map(rst => rst, clk => clk, swrst => swrst, en => en, din => din_end_fft, dout => dout_end_fft); end;
--------------------------------------------------------------------- -- Optimized multiplier -- -- Part of the LXP32 CPU -- -- Copyright (c) 2016 by Alex I. Kuznetsov -- -- This multiplier is designed for technologies that don't provide -- fast 16x16 multipliers. One multiplication takes 6 cycles. -- -- The multiplication algorithm is based on carry-save accumulation -- of partial products. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity lxp32_mul_opt is port( clk_i: in std_logic; rst_i: in std_logic; ce_i: in std_logic; op1_i: in std_logic_vector(31 downto 0); op2_i: in std_logic_vector(31 downto 0); ce_o: out std_logic; result_o: out std_logic_vector(31 downto 0) ); end entity; architecture rtl of lxp32_mul_opt is function csa_sum(a: unsigned; b: unsigned; c: unsigned; n: integer) return unsigned is variable r: unsigned(n-1 downto 0); begin for i in r'range loop r(i):=a(i) xor b(i) xor c(i); end loop; return r; end function; function csa_carry(a: unsigned; b: unsigned; c: unsigned; n: integer) return unsigned is variable r: unsigned(n-1 downto 0); begin for i in r'range loop r(i):=(a(i) and b(i)) or (a(i) and c(i)) or (b(i) and c(i)); end loop; return r&"0"; end function; signal reg1: unsigned(op1_i'range); signal reg2: unsigned(op2_i'range); type pp_type is array (7 downto 0) of unsigned(31 downto 0); signal pp: pp_type; type pp_sum_type is array (7 downto 0) of unsigned(31 downto 0); signal pp_sum: pp_sum_type; type pp_carry_type is array (7 downto 0) of unsigned(32 downto 0); signal pp_carry: pp_carry_type; signal acc_sum: unsigned(31 downto 0); signal acc_carry: unsigned(31 downto 0); signal cnt: integer range 0 to 4:=0; signal result: std_logic_vector(result_o'range); signal ceo: std_logic:='0'; begin -- Calculate 8 partial products in parallel pp_gen: for i in pp'range generate pp(i)<=shift_left(reg1,i) when reg2(i)='1' else (others=>'0'); end generate; -- Add partial products to the accumulator using carry-save adder tree pp_sum(0)<=csa_sum(pp(0),pp(1),pp(2),32); pp_carry(0)<=csa_carry(pp(0),pp(1),pp(2),32); pp_sum(1)<=csa_sum(pp(3),pp(4),pp(5),32); pp_carry(1)<=csa_carry(pp(3),pp(4),pp(5),32); pp_sum(2)<=csa_sum(pp(6),pp(7),acc_sum,32); pp_carry(2)<=csa_carry(pp(6),pp(7),acc_sum,32); pp_sum(3)<=csa_sum(pp_sum(0),pp_carry(0),pp_sum(1),32); pp_carry(3)<=csa_carry(pp_sum(0),pp_carry(0),pp_sum(1),32); pp_sum(4)<=csa_sum(pp_carry(1),pp_sum(2),pp_carry(2),32); pp_carry(4)<=csa_carry(pp_carry(1),pp_sum(2),pp_carry(2),32); pp_sum(5)<=csa_sum(pp_sum(3),pp_carry(3),pp_sum(4),32); pp_carry(5)<=csa_carry(pp_sum(3),pp_carry(3),pp_sum(4),32); pp_sum(6)<=csa_sum(pp_sum(5),pp_carry(5),pp_carry(4),32); pp_carry(6)<=csa_carry(pp_sum(5),pp_carry(5),pp_carry(4),32); pp_sum(7)<=csa_sum(pp_sum(6),pp_carry(6),acc_carry,32); pp_carry(7)<=csa_carry(pp_sum(6),pp_carry(6),acc_carry,32); -- Multiplier state machine process (clk_i) is begin if rising_edge(clk_i) then if rst_i='1' then ceo<='0'; cnt<=0; reg1<=(others=>'-'); reg2<=(others=>'-'); acc_sum<=(others=>'-'); acc_carry<=(others=>'-'); else if cnt=1 then ceo<='1'; else ceo<='0'; end if; if ce_i='1' then cnt<=4; reg1<=unsigned(op1_i); reg2<=unsigned(op2_i); acc_sum<=(others=>'0'); acc_carry<=(others=>'0'); else acc_sum<=pp_sum(7); acc_carry<=pp_carry(7)(acc_carry'range); reg1<=reg1(reg1'high-8 downto 0)&X"00"; reg2<=X"00"&reg2(reg2'high downto 8); if cnt>0 then cnt<=cnt-1; end if; end if; end if; end if; end process; result<=std_logic_vector(acc_sum+acc_carry); result_o<=result; ce_o<=ceo; -- A simulation-time multiplication check -- synthesis translate_off process (clk_i) is variable p: unsigned(op1_i'length+op2_i'length-1 downto 0); begin if rising_edge(clk_i) then if ce_i='1' then p:=unsigned(op1_i)*unsigned(op2_i); elsif ceo='1' then assert result=std_logic_vector(p(result'range)) report "Incorrect multiplication result" severity failure; end if; end if; end process; -- synthesis translate_on end architecture;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_dmask_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_dmask_rows_V_shiftReg; architecture rtl of FIFO_image_filter_dmask_rows_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_dmask_rows_V is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_dmask_rows_V is component FIFO_image_filter_dmask_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_dmask_rows_V_shiftReg : FIFO_image_filter_dmask_rows_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_dmask_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_dmask_rows_V_shiftReg; architecture rtl of FIFO_image_filter_dmask_rows_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_dmask_rows_V is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_dmask_rows_V is component FIFO_image_filter_dmask_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_dmask_rows_V_shiftReg : FIFO_image_filter_dmask_rows_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL; entity Zone is Generic ( nb_bits_Zone : natural := 8; -- 2^8 = 256 zones differentes possibles nb_bits_AdrPixel : natural := 9 -- coordonnees de la souris (X,Y) sur 9 bits ); Port ( clk : in STD_LOGIC; reset_n : in STD_LOGIC; MouseX : in STD_LOGIC_VECTOR ( (nb_bits_AdrPixel - 1) downto 0); MouseY : in STD_LOGIC_VECTOR ( (nb_bits_AdrPixel - 1) downto 0); NumZone : out STD_LOGIC_VECTOR ( (nb_bits_Zone - 1) downto 0) ); end Zone; architecture Behavioral of Zone is Constant Z0_x : integer := 0; Constant Z0_y : integer := 45; -- zone dessin --Constant Z1_x : integer := 0; Constant Z1_y : integer := 0; -- zone selection Constant Z2_x : integer := 10; Constant Z2_y : integer := 2; -- crayon Constant Z3_x : integer := 32; Constant Z3_y : integer := 2; -- pot de peinture Constant Z4_x : integer := 10; Constant Z4_y : integer := 24; -- gomme Constant Z5_x : integer := 32; Constant Z5_y : integer := 24; -- pipette Constant Z6_x : integer := 56; Constant Z6_y : integer := 2; -- clear all Constant Z7_x : integer := 80; Constant Z7_y : integer := 2; -- Forme : trait Constant Z8_x : integer := 102; Constant Z8_y : integer := 2; -- Forme : cercle Constant Z9_x : integer := 80; Constant Z9_y : integer := 24; -- Forme : carre Constant Z10_x : integer := 102; Constant Z10_y : integer := 24; -- Forme : rectangle Constant Z11_x : integer := 126; Constant Z11_y : integer := 2; -- taille : petite (taille par defaut) Constant Z12_x : integer := 148; Constant Z12_y : integer := 2; -- taille : moyenne Constant Z13_x : integer := 126; Constant Z13_y : integer := 24; -- taille : grande Constant Z47_x : integer := 368; Constant Z47_y : integer := 12; -- COULEUR SELECTIONNEE Constant Z14_x : integer := 176; Constant Z14_y : integer := 3; -- couleur bandeau haut Constant Z15_x : integer := 196; Constant Z15_y : integer := 3; -- couleur Constant Z16_x : integer := 216; Constant Z16_y : integer := 3; -- couleur Constant Z17_x : integer := 236; Constant Z17_y : integer := 3; -- couleur Constant Z18_x : integer := 256; Constant Z18_y : integer := 3; -- couleur Constant Z19_x : integer := 276; Constant Z19_y : integer := 3; -- couleur Constant Z20_x : integer := 296; Constant Z20_y : integer := 3; -- couleur Constant Z21_x : integer := 316; Constant Z21_y : integer := 3; -- couleur Constant Z22_x : integer := 336; Constant Z22_y : integer := 3; -- couleur Constant Z23_x : integer := 176; Constant Z23_y : integer := 23; -- couleur bandeau bas Constant Z24_x : integer := 196; Constant Z24_y : integer := 23; -- couleur Constant Z25_x : integer := 216; Constant Z25_y : integer := 23; -- couleur Constant Z26_x : integer := 236; Constant Z26_y : integer := 23; -- couleur Constant Z27_x : integer := 256; Constant Z27_y : integer := 23; -- couleur Constant Z28_x : integer := 276; Constant Z28_y : integer := 23; -- couleur Constant Z29_x : integer := 296; Constant Z29_y : integer := 23; -- couleur Constant Z30_x : integer := 316; Constant Z30_y : integer := 23; -- couleur Constant Z31_x : integer := 336; Constant Z31_y : integer := 23; -- couleur constant L_icone : integer := 20; signal MouseX_Dec : integer; signal MouseY_Dec : integer; begin -- conversions permanente des vecteurs "MouseX" et MouseY" en nombre decimal pour une meilleur lisibilite de la description ci-apres MouseX_Dec <= to_integer(unsigned(MouseX)); MouseY_Dec <= to_integer(unsigned(MouseY)); -- Process process(Clk) is begin if Clk'event and Clk='1' then if reset_n = '0' then -- initialization : on active synchronous reset NumZone <= std_logic_vector(to_unsigned(1,NumZone'length)); -- Zone 1 par defaut (selection) else if MouseY_Dec > Z0_y then NumZone <= (others => '0'); elsif MouseX_Dec >= Z2_x and MouseX_Dec <= (Z2_x + L_icone) and MouseY_Dec >= Z2_y and MouseY_Dec <= (Z2_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(2,NumZone'length)); elsif MouseX_Dec >= Z3_x and MouseX_Dec <= (Z3_x + L_icone) and MouseY_Dec >= Z3_y and MouseY_Dec <= (Z3_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(3,NumZone'length)); elsif MouseX_Dec >= Z4_x and MouseX_Dec <= (Z4_x + L_icone) and MouseY_Dec >= Z4_y and MouseY_Dec <= (Z4_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(4,NumZone'length)); elsif MouseX_Dec >= Z5_x and MouseX_Dec <= (Z5_x + L_icone) and MouseY_Dec >= Z5_y and MouseY_Dec <= (Z5_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(5,NumZone'length)); elsif MouseX_Dec >= Z6_x and MouseX_Dec <= (Z6_x + L_icone) and MouseY_Dec >= Z6_y and MouseY_Dec <= (Z6_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(6,NumZone'length)); elsif MouseX_Dec >= Z7_x and MouseX_Dec <= (Z7_x + L_icone) and MouseY_Dec >= Z7_y and MouseY_Dec <= (Z7_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(7,NumZone'length)); elsif MouseX_Dec >= Z8_x and MouseX_Dec <= (Z8_x + L_icone) and MouseY_Dec >= Z8_y and MouseY_Dec <= (Z8_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(8,NumZone'length)); elsif MouseX_Dec >= Z9_x and MouseX_Dec <= (Z9_x + L_icone) and MouseY_Dec >= Z9_y and MouseY_Dec <= (Z9_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(9,NumZone'length)); elsif MouseX_Dec >= Z10_x and MouseX_Dec <= (Z10_x + L_icone) and MouseY_Dec >= Z10_y and MouseY_Dec <= (Z10_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(10,NumZone'length)); elsif MouseX_Dec >= Z11_x and MouseX_Dec <= (Z11_x + L_icone) and MouseY_Dec >= Z11_y and MouseY_Dec <= (Z11_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(11,NumZone'length)); elsif MouseX_Dec >= Z12_x and MouseX_Dec <= (Z12_x + L_icone) and MouseY_Dec >= Z12_y and MouseY_Dec <= (Z12_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(12,NumZone'length)); elsif MouseX_Dec >= Z13_x and MouseX_Dec <= (Z13_x + L_icone) and MouseY_Dec >= Z13_y and MouseY_Dec <= (Z13_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(13,NumZone'length)); -- couleurs elsif MouseX_Dec >= Z14_x and MouseX_Dec <= (Z14_x + L_icone) and MouseY_Dec >= Z14_y and MouseY_Dec <= (Z14_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(14,NumZone'length)); elsif MouseX_Dec >= Z15_x and MouseX_Dec <= (Z15_x + L_icone) and MouseY_Dec >= Z15_y and MouseY_Dec <= (Z15_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(15,NumZone'length)); elsif MouseX_Dec >= Z16_x and MouseX_Dec <= (Z16_x + L_icone) and MouseY_Dec >= Z16_y and MouseY_Dec <= (Z16_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(16,NumZone'length)); elsif MouseX_Dec >= Z17_x and MouseX_Dec <= (Z17_x + L_icone) and MouseY_Dec >= Z17_y and MouseY_Dec <= (Z17_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(17,NumZone'length)); elsif MouseX_Dec >= Z18_x and MouseX_Dec <= (Z18_x + L_icone) and MouseY_Dec >= Z18_y and MouseY_Dec <= (Z18_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(18,NumZone'length)); elsif MouseX_Dec >= Z19_x and MouseX_Dec <= (Z19_x + L_icone) and MouseY_Dec >= Z19_y and MouseY_Dec <= (Z19_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(19,NumZone'length)); elsif MouseX_Dec >= Z20_x and MouseX_Dec <= (Z20_x + L_icone) and MouseY_Dec >= Z20_y and MouseY_Dec <= (Z20_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(20,NumZone'length)); elsif MouseX_Dec >= Z21_x and MouseX_Dec <= (Z21_x + L_icone) and MouseY_Dec >= Z21_y and MouseY_Dec <= (Z21_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(21,NumZone'length)); elsif MouseX_Dec >= Z22_x and MouseX_Dec <= (Z22_x + L_icone) and MouseY_Dec >= Z22_y and MouseY_Dec <= (Z22_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(22,NumZone'length)); elsif MouseX_Dec >= Z23_x and MouseX_Dec <= (Z23_x + L_icone) and MouseY_Dec >= Z23_y and MouseY_Dec <= (Z23_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(23,NumZone'length)); elsif MouseX_Dec >= Z24_x and MouseX_Dec <= (Z24_x + L_icone) and MouseY_Dec >= Z24_y and MouseY_Dec <= (Z24_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(24,NumZone'length)); elsif MouseX_Dec >= Z25_x and MouseX_Dec <= (Z25_x + L_icone) and MouseY_Dec >= Z25_y and MouseY_Dec <= (Z25_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(25,NumZone'length)); elsif MouseX_Dec >= Z26_x and MouseX_Dec <= (Z26_x + L_icone) and MouseY_Dec >= Z26_y and MouseY_Dec <= (Z26_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(26,NumZone'length)); elsif MouseX_Dec >= Z27_x and MouseX_Dec <= (Z27_x + L_icone) and MouseY_Dec >= Z27_y and MouseY_Dec <= (Z27_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(27,NumZone'length)); elsif MouseX_Dec >= Z28_x and MouseX_Dec <= (Z28_x + L_icone) and MouseY_Dec >= Z28_y and MouseY_Dec <= (Z28_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(28,NumZone'length)); elsif MouseX_Dec >= Z29_x and MouseX_Dec <= (Z29_x + L_icone) and MouseY_Dec >= Z29_y and MouseY_Dec <= (Z29_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(29,NumZone'length)); elsif MouseX_Dec >= Z30_x and MouseX_Dec <= (Z30_x + L_icone) and MouseY_Dec >= Z30_y and MouseY_Dec <= (Z30_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(30,NumZone'length)); elsif MouseX_Dec >= Z31_x and MouseX_Dec <= (Z31_x + L_icone) and MouseY_Dec >= Z31_y and MouseY_Dec <= (Z31_y + L_icone) then NumZone <= std_logic_vector(to_unsigned(31,NumZone'length)); else NumZone <= std_logic_vector(to_unsigned(1,NumZone'length)); -- Zone 1 par defaut (selection) end if; end if; end if; end process; end Behavioral;
-- This is multi-stage shift register designed to limit fanout -- There is at least one register, there may be more depending on wanted fanout library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity distribuf is generic( WDATA : natural := 20; NBOUT : natural := 20; FANOUT : natural := 20 ); port( clk : in std_logic; -- Input idata : in std_logic_vector(WDATA-1 downto 0); -- Output odata : out std_logic_vector(WDATA*NBOUT-1 downto 0) ); end distribuf; architecture synth of distribuf is -- Stupid compnent declaration for recursive instantiation component distribuf is generic( WDATA : natural := 20; NBOUT : natural := 20; FANOUT : natural := 20 ); port( clk : in std_logic; -- Input idata : in std_logic_vector(WDATA-1 downto 0); -- Outputs odata : out std_logic_vector(WDATA*NBOUT-1 downto 0) ); end component; -- The number of registers needed in the local stage constant NBREGS : natural := (NBOUT + FANOUT - 1) / FANOUT; -- The registers, and the signal to compute their input signal regs, regs_n : std_logic_vector(NBREGS*WDATA-1 downto 0) := (others => '0'); begin -- If the fanout is low enough, just connect the input port to the registers gen_lowfan_in: if NBREGS <= FANOUT generate gen_lowfan_in_loop: for i in 0 to NBREGS-1 generate regs_n((i+1)*WDATA-1 downto i*WDATA) <= idata; end generate; end generate; -- If the fanout is high enough, recursively instantiate a sub-component gen_highfan_in: if NBREGS > FANOUT generate -- Instantiate the sub-stage i_stage: distribuf generic map ( WDATA => WDATA, NBOUT => NBREGS, FANOUT => FANOUT ) port map ( clk => clk, idata => idata, odata => regs_n ); end generate; -- Write to registers process(clk) begin if rising_edge(clk) then regs <= regs_n; end if; end process; -- Connect outputs: first guaranteed max-fanout outputs gen_maxfan: if NBREGS > 1 generate gen_maxfan_reg: for r in 0 to NBREGS-2 generate gen_maxfan_regloop: for i in r * FANOUT to (r+1) * FANOUT - 1 generate odata((i+1)*WDATA-1 downto i*WDATA) <= regs((r+1) * WDATA - 1 downto r * WDATA); end generate; end generate; end generate; -- Connect last outputs gen_lastout_loop: for i in (NBREGS-1) * FANOUT to NBOUT - 1 generate odata((i+1)*WDATA-1 downto i*WDATA) <= regs(NBREGS * WDATA - 1 downto (NBREGS-1) * WDATA); end generate; end architecture;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7.1 Core - Top-level wrapper -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -------------------------------------------------------------------------------- -- -- Filename: startBtn_prod.vhd -- -- Description: -- This is the top-level BMG wrapper (over BMG core). -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: August 31, 2005 - First Release -------------------------------------------------------------------------------- -- -- Configured Core Parameter Values: -- (Refer to the SIM Parameters table in the datasheet for more information on -- the these parameters.) -- C_FAMILY : artix7 -- C_XDEVICEFAMILY : artix7 -- C_INTERFACE_TYPE : 0 -- C_ENABLE_32BIT_ADDRESS : 0 -- C_AXI_TYPE : 1 -- C_AXI_SLAVE_TYPE : 0 -- C_AXI_ID_WIDTH : 4 -- C_MEM_TYPE : 3 -- C_BYTE_SIZE : 9 -- C_ALGORITHM : 1 -- C_PRIM_TYPE : 1 -- C_LOAD_INIT_FILE : 1 -- C_INIT_FILE_NAME : startBtn.mif -- C_USE_DEFAULT_DATA : 0 -- C_DEFAULT_DATA : 0 -- C_RST_TYPE : SYNC -- C_HAS_RSTA : 0 -- C_RST_PRIORITY_A : CE -- C_RSTRAM_A : 0 -- C_INITA_VAL : 0 -- C_HAS_ENA : 0 -- C_HAS_REGCEA : 0 -- C_USE_BYTE_WEA : 0 -- C_WEA_WIDTH : 1 -- C_WRITE_MODE_A : WRITE_FIRST -- C_WRITE_WIDTH_A : 12 -- C_READ_WIDTH_A : 12 -- C_WRITE_DEPTH_A : 10000 -- C_READ_DEPTH_A : 10000 -- C_ADDRA_WIDTH : 14 -- C_HAS_RSTB : 0 -- C_RST_PRIORITY_B : CE -- C_RSTRAM_B : 0 -- C_INITB_VAL : 0 -- C_HAS_ENB : 0 -- C_HAS_REGCEB : 0 -- C_USE_BYTE_WEB : 0 -- C_WEB_WIDTH : 1 -- C_WRITE_MODE_B : WRITE_FIRST -- C_WRITE_WIDTH_B : 12 -- C_READ_WIDTH_B : 12 -- C_WRITE_DEPTH_B : 10000 -- C_READ_DEPTH_B : 10000 -- C_ADDRB_WIDTH : 14 -- C_HAS_MEM_OUTPUT_REGS_A : 0 -- C_HAS_MEM_OUTPUT_REGS_B : 0 -- C_HAS_MUX_OUTPUT_REGS_A : 0 -- C_HAS_MUX_OUTPUT_REGS_B : 0 -- C_HAS_SOFTECC_INPUT_REGS_A : 0 -- C_HAS_SOFTECC_OUTPUT_REGS_B : 0 -- C_MUX_PIPELINE_STAGES : 0 -- C_USE_ECC : 0 -- C_USE_SOFTECC : 0 -- C_HAS_INJECTERR : 0 -- C_SIM_COLLISION_CHECK : ALL -- C_COMMON_CLK : 0 -- C_DISABLE_WARN_BHV_COLL : 0 -- C_DISABLE_WARN_BHV_RANGE : 0 -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY UNISIM; USE UNISIM.VCOMPONENTS.ALL; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- ENTITY startBtn_prod IS PORT ( --Port A CLKA : IN STD_LOGIC; RSTA : IN STD_LOGIC; --opt port ENA : IN STD_LOGIC; --optional port REGCEA : IN STD_LOGIC; --optional port WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(11 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --Port B CLKB : IN STD_LOGIC; RSTB : IN STD_LOGIC; --opt port ENB : IN STD_LOGIC; --optional port REGCEB : IN STD_LOGIC; --optional port WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRB : IN STD_LOGIC_VECTOR(13 DOWNTO 0); DINB : IN STD_LOGIC_VECTOR(11 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --ECC INJECTSBITERR : IN STD_LOGIC; --optional port INJECTDBITERR : IN STD_LOGIC; --optional port SBITERR : OUT STD_LOGIC; --optional port DBITERR : OUT STD_LOGIC; --optional port RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); --optional port -- AXI BMG Input and Output Port Declarations -- AXI Global Signals S_ACLK : IN STD_LOGIC; S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_AWVALID : IN STD_LOGIC; S_AXI_AWREADY : OUT STD_LOGIC; S_AXI_WDATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0); S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); S_AXI_WLAST : IN STD_LOGIC; S_AXI_WVALID : IN STD_LOGIC; S_AXI_WREADY : OUT STD_LOGIC; S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_BVALID : OUT STD_LOGIC; S_AXI_BREADY : IN STD_LOGIC; -- AXI Full/Lite Slave Read (Write side) S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_ARVALID : IN STD_LOGIC; S_AXI_ARREADY : OUT STD_LOGIC; S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); S_AXI_RDATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_RLAST : OUT STD_LOGIC; S_AXI_RVALID : OUT STD_LOGIC; S_AXI_RREADY : IN STD_LOGIC; -- AXI Full/Lite Sideband Signals S_AXI_INJECTSBITERR : IN STD_LOGIC; S_AXI_INJECTDBITERR : IN STD_LOGIC; S_AXI_SBITERR : OUT STD_LOGIC; S_AXI_DBITERR : OUT STD_LOGIC; S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); S_ARESETN : IN STD_LOGIC ); END startBtn_prod; ARCHITECTURE xilinx OF startBtn_prod IS COMPONENT startBtn_exdes IS PORT ( --Port A ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); CLKA : IN STD_LOGIC ); END COMPONENT; BEGIN bmg0 : startBtn_exdes PORT MAP ( --Port A ADDRA => ADDRA, DOUTA => DOUTA, CLKA => CLKA ); END xilinx;
library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity ex5_hot is port( clock: in std_logic; input: in std_logic_vector(1 downto 0); output: out std_logic_vector(1 downto 0) ); end ex5_hot; architecture behaviour of ex5_hot is constant s1: std_logic_vector(8 downto 0) := "100000000"; constant s0: std_logic_vector(8 downto 0) := "010000000"; constant s7: std_logic_vector(8 downto 0) := "001000000"; constant s5: std_logic_vector(8 downto 0) := "000100000"; constant s4: std_logic_vector(8 downto 0) := "000010000"; constant s2: std_logic_vector(8 downto 0) := "000001000"; constant s3: std_logic_vector(8 downto 0) := "000000100"; constant s6: std_logic_vector(8 downto 0) := "000000010"; constant s8: std_logic_vector(8 downto 0) := "000000001"; signal current_state, next_state: std_logic_vector(8 downto 0); begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= "---------"; output <= "--"; case current_state is when s1 => if std_match(input, "00") then next_state <= s0; output <= "--"; elsif std_match(input, "01") then next_state <= s7; output <= "00"; elsif std_match(input, "10") then next_state <= s5; output <= "11"; elsif std_match(input, "11") then next_state <= s4; output <= "--"; end if; when s2 => if std_match(input, "00") then next_state <= s1; output <= "--"; elsif std_match(input, "01") then next_state <= s4; output <= "--"; elsif std_match(input, "10") then next_state <= s0; output <= "--"; elsif std_match(input, "11") then next_state <= s0; output <= "00"; end if; when s3 => if std_match(input, "00") then next_state <= s3; output <= "--"; elsif std_match(input, "01") then next_state <= s0; output <= "00"; elsif std_match(input, "10") then next_state <= s0; output <= "--"; elsif std_match(input, "11") then next_state <= s7; output <= "11"; end if; when s4 => if std_match(input, "00") then next_state <= s5; output <= "00"; elsif std_match(input, "01") then next_state <= s0; output <= "--"; elsif std_match(input, "10") then next_state <= s1; output <= "--"; elsif std_match(input, "11") then next_state <= s0; output <= "--"; end if; when s5 => if std_match(input, "00") then next_state <= s0; output <= "11"; elsif std_match(input, "01") then next_state <= s6; output <= "--"; elsif std_match(input, "10") then next_state <= s0; output <= "11"; elsif std_match(input, "11") then next_state <= s0; output <= "11"; end if; when s6 => if std_match(input, "00") then next_state <= s0; output <= "11"; elsif std_match(input, "01") then next_state <= s5; output <= "--"; elsif std_match(input, "10") then next_state <= s1; output <= "11"; elsif std_match(input, "11") then next_state <= s0; output <= "11"; end if; when s7 => if std_match(input, "00") then next_state <= s6; output <= "--"; elsif std_match(input, "01") then next_state <= s0; output <= "11"; elsif std_match(input, "10") then next_state <= s2; output <= "--"; elsif std_match(input, "11") then next_state <= s8; output <= "--"; end if; when s8 => if std_match(input, "00") then next_state <= s3; output <= "--"; elsif std_match(input, "01") then next_state <= s0; output <= "--"; elsif std_match(input, "10") then next_state <= s1; output <= "00"; elsif std_match(input, "11") then next_state <= s0; output <= "--"; end if; when others => next_state <= "---------"; output <= "--"; end case; end process; end behaviour;
------------------------------------------------------------------------------ -- @file <Name of the file> -- @brief <TO ADD> -- @details <TO ADD> -- @see <TESTBENCH> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity <MODULE_NAME> is generic ( -- module generics like port widths go here ); port( -- port list goes here ) end entity <MODULE_NAME>; architecture rtl of <MODULE_NAME> is -- Signal declarations go here begin -- The guts of the module go here. end architecture rtl;
-- VHDL Entity My_Lib.interceptor.symbol -- -- Created: -- by - mg55.bin (srge02.ecn.purdue.edu) -- at - 14:37:58 04/21/12 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2010.2a (Build 7) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY interceptor IS PORT( clk : IN std_logic; eop : IN std_logic; intercept : IN std_logic; inst : IN std_logic_vector (3 DOWNTO 0); rst : IN std_logic; usbclk : IN std_logic; dataPlus : OUT std_logic; dataMinus : OUT std_logic; computerMinus : INOUT std_logic; computerPlus : INOUT std_logic; usbMinus : INOUT std_logic; usbPlus : INOUT std_logic ); -- Declarations END interceptor ; -- -- VHDL Architecture My_Lib.interceptor.struct -- -- Created: -- by - mg55.bin (srge02.ecn.purdue.edu) -- at - 14:37:58 04/21/12 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2010.2a (Build 7) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; ARCHITECTURE struct OF interceptor IS -- Architecture declarations -- Internal signal declarations SIGNAL computerDataMinus : std_logic; SIGNAL computerDataMinusOutput : std_logic; SIGNAL computerDataPlus : std_logic; SIGNAL computerDataPlusOutput : std_logic; SIGNAL computerLock : std_logic; SIGNAL usbDataMinus : std_logic; SIGNAL usbDataMinusOutput : std_logic; SIGNAL usbDataPlus : std_logic; SIGNAL usbDataPlusOutput : std_logic; SIGNAL usbLock : std_logic; -- Component Declarations COMPONENT computerInterceptor PORT ( clk : IN std_logic; computerDataMinus : IN std_logic; computerDataPlus : IN std_logic; computerLock : IN std_logic; eop : in std_logic; rst : IN std_logic; usbClk : IN std_logic; computerDataMinusOutput : OUT std_logic; computerDataPlusOutput : OUT std_logic ); END COMPONENT; COMPONENT lockingDetector PORT ( clk : IN std_logic; endOfPacket : IN std_logic; inst : IN std_logic_vector ( 3 DOWNTO 0 ); rst : IN std_logic; computerLock : OUT std_logic; usbLock : OUT std_logic ); END COMPONENT; COMPONENT tristate PORT ( interceptorOutput : IN std_logic; lock : IN std_logic; interceptorInput : OUT std_logic; dataLine : INOUT std_logic ); END COMPONENT; COMPONENT usbInterceptor PORT ( clk : IN std_logic; intercept : IN std_logic; rst : IN std_logic; usbClk : IN std_logic; eop : in std_logic; usbDataMinus : IN std_logic; usbDataPlus : IN std_logic; usbLock : IN std_logic; usbDataMinusOutput : OUT std_logic; usbDataPlusOutput : OUT std_logic ); END COMPONENT; -- Optional embedded configurations -- pragma synthesis_off -- pragma synthesis_on BEGIN -- Instance port mappings. U_0 : computerInterceptor PORT MAP ( usbClk => usbclk, rst => rst, computerDataPlus => computerDataPlus, computerDataMinus => computerDataMinus, computerLock => computerLock, clk => clk, eop => eop, computerDataPlusOutput => computerDataPlusOutput, computerDataMinusOutput => computerDataMinusOutput ); U_1 : lockingDetector PORT MAP ( endOfPacket => eop, rst => rst, clk => clk, inst => inst, usbLock => usbLock, computerLock => computerLock ); U_2 : tristate -- D- usb to computer PORT MAP ( lock => computerLock, interceptorOutput => computerDataMinusOutput, interceptorInput => usbDataMinus, dataLine => usbMinus ); U_3 : tristate -- D+ computer to USB PORT MAP ( lock => usbLock, interceptorOutput => usbDataPlusOutput, interceptorInput => computerDataPlus, dataLine => computerPlus ); U_5 : tristate -- D+ usb PORT MAP ( lock => computerLock, interceptorOutput => computerDataPlusOutput, interceptorInput => usbDataPlus, dataLine => usbPlus ); U_6 : tristate -- D- computer PORT MAP ( lock => usbLock, interceptorOutput => usbDataMinusOutput, interceptorInput => computerDataMinus, dataLine => computerMinus ); U_4 : usbInterceptor PORT MAP ( usbClk => usbclk, rst => rst, intercept => intercept, usbDataPlus => usbDataPlus, eop => eop, usbDataMinus => usbDataMinus, usbLock => usbLock, clk => clk, usbDataPlusOutput => usbDataPlusOutput, usbDataMinusOutput => usbDataMinusOutput ); dataPlus <= usbPlus when usbLock = '1' -- logic for the output to the detector for the D+ line else computerPlus when computerLock = '1' else '1'; dataMinus <= usbMinus when usbLock = '1' -- logic for the output to the detector for the D- line else computerMinus when computerLock = '1' else '1'; END struct;
package attributes_pkg is attribute period :time; end package; library work; use work.attributes_pkg.period; entity inner is port( signal clk :in bit ); end entity; architecture arch of inner is constant CLK_PERIOD :time := clk'period; begin end architecture; library work; use work.attributes_pkg.period; entity outer is end entity; architecture arch of outer is signal clk :bit; attribute period of clk :signal is 1 ns; begin inst: entity work.inner port map(clk); end architecture;
package attributes_pkg is attribute period :time; end package; library work; use work.attributes_pkg.period; entity inner is port( signal clk :in bit ); end entity; architecture arch of inner is constant CLK_PERIOD :time := clk'period; begin end architecture; library work; use work.attributes_pkg.period; entity outer is end entity; architecture arch of outer is signal clk :bit; attribute period of clk :signal is 1 ns; begin inst: entity work.inner port map(clk); end architecture;
package attributes_pkg is attribute period :time; end package; library work; use work.attributes_pkg.period; entity inner is port( signal clk :in bit ); end entity; architecture arch of inner is constant CLK_PERIOD :time := clk'period; begin end architecture; library work; use work.attributes_pkg.period; entity outer is end entity; architecture arch of outer is signal clk :bit; attribute period of clk :signal is 1 ns; begin inst: entity work.inner port map(clk); end architecture;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Module: A generic buffer module for the PoC.Stream protocol. -- -- Description: -- ------------------------------------ -- This module implements a generic buffer (FifO) for the PoC.Stream protocol. -- It is generic in DATA_BITS and in META_BITS as well as in FifO depths for -- data and meta information. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.config.all; use PoC.utils.all; use PoC.vectors.all; entity Stream_DeMux is generic ( portS : POSITIVE := 2; DATA_BITS : POSITIVE := 8; META_BITS : NATURAL := 8; META_REV_BITS : NATURAL := 2 ); port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; -- Control interface DeMuxControl : in STD_LOGIC_VECTOR(portS - 1 downto 0); -- IN Port In_Valid : in STD_LOGIC; In_Data : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); In_Meta : in STD_LOGIC_VECTOR(META_BITS - 1 downto 0); In_Meta_rev : out STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0); In_SOF : in STD_LOGIC; In_EOF : in STD_LOGIC; In_Ack : out STD_LOGIC; -- OUT Ports Out_Valid : out STD_LOGIC_VECTOR(portS - 1 downto 0); Out_Data : out T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0); Out_Meta : out T_SLM(portS - 1 downto 0, META_BITS - 1 downto 0); Out_Meta_rev : in T_SLM(portS - 1 downto 0, META_REV_BITS - 1 downto 0); Out_SOF : out STD_LOGIC_VECTOR(portS - 1 downto 0); Out_EOF : out STD_LOGIC_VECTOR(portS - 1 downto 0); Out_Ack : in STD_LOGIC_VECTOR(portS - 1 downto 0) ); end; architecture rtl of Stream_DeMux is attribute KEEP : BOOLEAN; attribute FSM_ENCODING : STRING; subtype T_CHANNEL_INDEX is NATURAL range 0 to portS - 1; type T_STATE is (ST_IDLE, ST_DATAFLOW, ST_DISCARD_FRAME); signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; signal Is_SOF : STD_LOGIC; signal Is_EOF : STD_LOGIC; signal In_Ack_i : STD_LOGIC; signal Out_Valid_i : STD_LOGIC; signal DiscardFrame : STD_LOGIC; signal ChannelPointer_rst : STD_LOGIC; signal ChannelPointer_en : STD_LOGIC; signal ChannelPointer : STD_LOGIC_VECTOR(portS - 1 downto 0); signal ChannelPointer_d : STD_LOGIC_VECTOR(portS - 1 downto 0) := (others => '0'); signal ChannelPointer_bin : UNSIGNED(log2ceilnz(portS) - 1 downto 0); signal idx : T_CHANNEL_INDEX; signal Out_Data_i : T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal Out_Meta_i : T_SLM(portS - 1 downto 0, META_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) begin In_Ack_i <= slv_or(Out_Ack and ChannelPointer); DiscardFrame <= slv_nor(DeMuxControl); Is_SOF <= In_Valid and In_SOF; Is_EOF <= In_Valid and In_EOF; process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then State <= ST_IDLE; else State <= NextState; end if; end if; end process; process(State, In_Ack_i, In_Valid, Is_SOF, Is_EOF, DiscardFrame, DeMuxControl, ChannelPointer_d) begin NextState <= State; ChannelPointer_rst <= Is_EOF; ChannelPointer_en <= '0'; ChannelPointer <= ChannelPointer_d; In_Ack <= '0'; Out_Valid_i <= '0'; case State is when ST_IDLE => ChannelPointer <= DeMuxControl; if (Is_SOF = '1') then if (DiscardFrame = '0') then ChannelPointer_en <= '1'; In_Ack <= In_Ack_i; Out_Valid_i <= '1'; NextState <= ST_DATAFLOW; else In_Ack <= '1'; NextState <= ST_DISCARD_FRAME; end if; end if; when ST_DATAFLOW => In_Ack <= In_Ack_i; Out_Valid_i <= In_Valid; ChannelPointer <= ChannelPointer_d; if (Is_EOF = '1') then NextState <= ST_IDLE; end if; when ST_DISCARD_FRAME => In_Ack <= '1'; if (Is_EOF = '1') then NextState <= ST_IDLE; end if; end case; end process; process(Clock) begin if rising_edge(Clock) then if ((Reset or ChannelPointer_rst) = '1') then ChannelPointer_d <= (others => '0'); else if (ChannelPointer_en = '1') then ChannelPointer_d <= DeMuxControl; end if; end if; end if; end process; ChannelPointer_bin <= onehot2bin(ChannelPointer_d); idx <= to_integer(ChannelPointer_bin); In_Meta_rev <= get_row(Out_Meta_rev, idx); genOutput : for i in 0 to portS - 1 generate Out_Valid(i) <= Out_Valid_i and ChannelPointer(i); assign_row(Out_Data_i, In_Data, i); assign_row(Out_Meta_i, In_Meta, i); Out_SOF(i) <= In_SOF; Out_EOF(i) <= In_EOF; end generate; Out_Data <= Out_Data_i; Out_Meta <= Out_Meta_i; end architecture;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Module: A generic buffer module for the PoC.Stream protocol. -- -- Description: -- ------------------------------------ -- This module implements a generic buffer (FifO) for the PoC.Stream protocol. -- It is generic in DATA_BITS and in META_BITS as well as in FifO depths for -- data and meta information. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.config.all; use PoC.utils.all; use PoC.vectors.all; entity Stream_DeMux is generic ( portS : POSITIVE := 2; DATA_BITS : POSITIVE := 8; META_BITS : NATURAL := 8; META_REV_BITS : NATURAL := 2 ); port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; -- Control interface DeMuxControl : in STD_LOGIC_VECTOR(portS - 1 downto 0); -- IN Port In_Valid : in STD_LOGIC; In_Data : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0); In_Meta : in STD_LOGIC_VECTOR(META_BITS - 1 downto 0); In_Meta_rev : out STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0); In_SOF : in STD_LOGIC; In_EOF : in STD_LOGIC; In_Ack : out STD_LOGIC; -- OUT Ports Out_Valid : out STD_LOGIC_VECTOR(portS - 1 downto 0); Out_Data : out T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0); Out_Meta : out T_SLM(portS - 1 downto 0, META_BITS - 1 downto 0); Out_Meta_rev : in T_SLM(portS - 1 downto 0, META_REV_BITS - 1 downto 0); Out_SOF : out STD_LOGIC_VECTOR(portS - 1 downto 0); Out_EOF : out STD_LOGIC_VECTOR(portS - 1 downto 0); Out_Ack : in STD_LOGIC_VECTOR(portS - 1 downto 0) ); end; architecture rtl of Stream_DeMux is attribute KEEP : BOOLEAN; attribute FSM_ENCODING : STRING; subtype T_CHANNEL_INDEX is NATURAL range 0 to portS - 1; type T_STATE is (ST_IDLE, ST_DATAFLOW, ST_DISCARD_FRAME); signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; signal Is_SOF : STD_LOGIC; signal Is_EOF : STD_LOGIC; signal In_Ack_i : STD_LOGIC; signal Out_Valid_i : STD_LOGIC; signal DiscardFrame : STD_LOGIC; signal ChannelPointer_rst : STD_LOGIC; signal ChannelPointer_en : STD_LOGIC; signal ChannelPointer : STD_LOGIC_VECTOR(portS - 1 downto 0); signal ChannelPointer_d : STD_LOGIC_VECTOR(portS - 1 downto 0) := (others => '0'); signal ChannelPointer_bin : UNSIGNED(log2ceilnz(portS) - 1 downto 0); signal idx : T_CHANNEL_INDEX; signal Out_Data_i : T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) signal Out_Meta_i : T_SLM(portS - 1 downto 0, META_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) begin In_Ack_i <= slv_or(Out_Ack and ChannelPointer); DiscardFrame <= slv_nor(DeMuxControl); Is_SOF <= In_Valid and In_SOF; Is_EOF <= In_Valid and In_EOF; process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then State <= ST_IDLE; else State <= NextState; end if; end if; end process; process(State, In_Ack_i, In_Valid, Is_SOF, Is_EOF, DiscardFrame, DeMuxControl, ChannelPointer_d) begin NextState <= State; ChannelPointer_rst <= Is_EOF; ChannelPointer_en <= '0'; ChannelPointer <= ChannelPointer_d; In_Ack <= '0'; Out_Valid_i <= '0'; case State is when ST_IDLE => ChannelPointer <= DeMuxControl; if (Is_SOF = '1') then if (DiscardFrame = '0') then ChannelPointer_en <= '1'; In_Ack <= In_Ack_i; Out_Valid_i <= '1'; NextState <= ST_DATAFLOW; else In_Ack <= '1'; NextState <= ST_DISCARD_FRAME; end if; end if; when ST_DATAFLOW => In_Ack <= In_Ack_i; Out_Valid_i <= In_Valid; ChannelPointer <= ChannelPointer_d; if (Is_EOF = '1') then NextState <= ST_IDLE; end if; when ST_DISCARD_FRAME => In_Ack <= '1'; if (Is_EOF = '1') then NextState <= ST_IDLE; end if; end case; end process; process(Clock) begin if rising_edge(Clock) then if ((Reset or ChannelPointer_rst) = '1') then ChannelPointer_d <= (others => '0'); else if (ChannelPointer_en = '1') then ChannelPointer_d <= DeMuxControl; end if; end if; end if; end process; ChannelPointer_bin <= onehot2bin(ChannelPointer_d); idx <= to_integer(ChannelPointer_bin); In_Meta_rev <= get_row(Out_Meta_rev, idx); genOutput : for i in 0 to portS - 1 generate Out_Valid(i) <= Out_Valid_i and ChannelPointer(i); assign_row(Out_Data_i, In_Data, i); assign_row(Out_Meta_i, In_Meta, i); Out_SOF(i) <= In_SOF; Out_EOF(i) <= In_EOF; end generate; Out_Data <= Out_Data_i; Out_Meta <= Out_Meta_i; end architecture;
entity tb_ent1 is end tb_ent1; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_ent1 is signal clk : std_logic; signal dout : std_logic_vector (7 downto 0); begin dut: entity work.ent1 port map (clk => clk, o => dout); process procedure pulse is begin clk <= '0'; wait for 1 ns; clk <= '1'; wait for 1 ns; end pulse; begin wait for 1 ns; assert dout = x"10" severity failure; pulse; assert dout = x"11" severity failure; pulse; assert dout = x"12" severity failure; pulse; assert dout = x"13" severity failure; pulse; assert dout = x"14" severity failure; pulse; assert dout = x"15" severity failure; pulse; assert dout = x"16" severity failure; pulse; assert dout = x"17" severity failure; pulse; assert dout = x"00" severity failure; pulse; assert dout = x"00" severity failure; wait; end process; end behav;
library ieee; use ieee.std_logic_1164.all; entity device_ram_blocks is generic ( INTENDED_DEVICE_FAMILY : string := "SmartFusion"; -- or "ZynqSoC" WIDTH_AD : natural := 10; -- WIDTH_RDAD = WIDTH_WRAD WIDTH_DATA : natural := 66; -- WIDTH_DATAIN = WIDTH_DATAOUT OUP_REG : string := "UNREGISTERED" -- Set to "CLOCK0" if ouput data is to be registered ); port( clock : in std_logic := '1'; aclr : in std_logic := '0'; rden : in std_logic := '1'; rdaddress : in std_logic_vector(WIDTH_AD-1 downto 0); data_in : in std_logic_vector(WIDTH_DATA-1 downto 0); wren : in std_logic := '0'; wraddress : in std_logic_vector(WIDTH_AD-1 downto 0); data_out : out std_logic_vector(WIDTH_DATA-1 downto 0) ); end entity device_ram_blocks; architecture arch of device_ram_blocks is begin end arch;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 -- Date : Wed Oct 25 12:44:01 2017 -- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.vhdl -- Design : srio_gen2_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7k325tffg676-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is Port ( sys_clkp : in STD_LOGIC; sys_clkn : in STD_LOGIC; sys_rst : in STD_LOGIC; log_clk_out : out STD_LOGIC; phy_clk_out : out STD_LOGIC; gt_clk_out : out STD_LOGIC; gt_pcs_clk_out : out STD_LOGIC; drpclk_out : out STD_LOGIC; refclk_out : out STD_LOGIC; clk_lock_out : out STD_LOGIC; cfg_rst_out : out STD_LOGIC; log_rst_out : out STD_LOGIC; buf_rst_out : out STD_LOGIC; phy_rst_out : out STD_LOGIC; gt_pcs_rst_out : out STD_LOGIC; gt0_qpll_clk_out : out STD_LOGIC; gt0_qpll_out_refclk_out : out STD_LOGIC; srio_rxn0 : in STD_LOGIC; srio_rxp0 : in STD_LOGIC; srio_rxn1 : in STD_LOGIC; srio_rxp1 : in STD_LOGIC; srio_rxn2 : in STD_LOGIC; srio_rxp2 : in STD_LOGIC; srio_rxn3 : in STD_LOGIC; srio_rxp3 : in STD_LOGIC; srio_txn0 : out STD_LOGIC; srio_txp0 : out STD_LOGIC; srio_txn1 : out STD_LOGIC; srio_txp1 : out STD_LOGIC; srio_txn2 : out STD_LOGIC; srio_txp2 : out STD_LOGIC; srio_txn3 : out STD_LOGIC; srio_txp3 : out STD_LOGIC; s_axis_iotx_tvalid : in STD_LOGIC; s_axis_iotx_tready : out STD_LOGIC; s_axis_iotx_tlast : in STD_LOGIC; s_axis_iotx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); s_axis_iotx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_iotx_tuser : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axis_iorx_tvalid : out STD_LOGIC; m_axis_iorx_tready : in STD_LOGIC; m_axis_iorx_tlast : out STD_LOGIC; m_axis_iorx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axis_iorx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axis_iorx_tuser : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_maintr_rst : in STD_LOGIC; s_axi_maintr_awvalid : in STD_LOGIC; s_axi_maintr_awready : out STD_LOGIC; s_axi_maintr_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_maintr_wvalid : in STD_LOGIC; s_axi_maintr_wready : out STD_LOGIC; s_axi_maintr_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_maintr_bvalid : out STD_LOGIC; s_axi_maintr_bready : in STD_LOGIC; s_axi_maintr_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_maintr_arvalid : in STD_LOGIC; s_axi_maintr_arready : out STD_LOGIC; s_axi_maintr_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_maintr_rvalid : out STD_LOGIC; s_axi_maintr_rready : in STD_LOGIC; s_axi_maintr_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_maintr_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); sim_train_en : in STD_LOGIC; force_reinit : in STD_LOGIC; phy_mce : in STD_LOGIC; phy_link_reset : in STD_LOGIC; phy_rcvd_mce : out STD_LOGIC; phy_rcvd_link_reset : out STD_LOGIC; phy_debug : out STD_LOGIC_VECTOR ( 223 downto 0 ); gtrx_disperr_or : out STD_LOGIC; gtrx_notintable_or : out STD_LOGIC; port_error : out STD_LOGIC; port_timeout : out STD_LOGIC_VECTOR ( 23 downto 0 ); srio_host : out STD_LOGIC; port_decode_error : out STD_LOGIC; deviceid : out STD_LOGIC_VECTOR ( 15 downto 0 ); idle2_selected : out STD_LOGIC; phy_lcl_master_enable_out : out STD_LOGIC; buf_lcl_response_only_out : out STD_LOGIC; buf_lcl_tx_flow_control_out : out STD_LOGIC; buf_lcl_phy_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); phy_lcl_phy_next_fm_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); phy_lcl_phy_last_ack_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); phy_lcl_phy_rewind_out : out STD_LOGIC; phy_lcl_phy_rcvd_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); phy_lcl_maint_only_out : out STD_LOGIC; port_initialized : out STD_LOGIC; link_initialized : out STD_LOGIC; idle_selected : out STD_LOGIC; mode_1x : out STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_rxn1,srio_rxp1,srio_rxn2,srio_rxp2,srio_rxn3,srio_rxp3,srio_txn0,srio_txp0,srio_txn1,srio_txp1,srio_txn2,srio_txp2,srio_txn3,srio_txp3,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "srio_gen2_v4_0_5,Vivado 2015.1.0"; begin end;
entity e is end entity; architecture a of e is signal x : integer := -3 * 4 + 2; type t is range -5 to 11 - 3; constant c : integer := +4 + 1; signal y : t; type int_array is array (integer range <>) of integer; constant a1 : int_array(1 to 5) := (1, 2, 3, 4, 5); constant a2 : int_array(1 to 7) := (2 to 3 => 6, others => 5); constant a3 : int_array(1 to 9) := (8 => 24, others => 0); constant a4 : int_array(5 downto 1) := (1, 2, 3, 4, 5); constant a5 : int_array(5 downto 1) := (5 downto 3 => -1, others => 1); begin process is variable b : boolean; variable d : time; begin x <= c / 2; y <= t'high; y <= t'left; b := t'right = 8; b := (t'right - t'left) = 2; b := t'high /= 2; b := true and true; b := true and false; b := true or false; b := true xor true; b := not true; b := not false; b := true xnor false; b := false nand false; b := false nor true; b := 7 > 5 and 6 < 2; x <= a1(2); x <= a2(1); x <= a2(3); x <= a3(8); x <= a1'length; x <= a4(2); x <= a5(4); x <= 2 ** 4; d := -5 ns; end process; process is begin if true then x <= 1; end if; if false then x <= 5; end if; if false then null; else x <= 5; end if; while false loop null; end loop; if true then x <= 1; x <= 5; null; end if; end process; process is variable r : real; variable b : boolean; begin r := 1.0 + 0.0; r := 1.5 * 4.0; r := 2.0 / 2.0; b := 4.6 > 1.2; end process; process variable k : time; begin end process; process type int2_vec is array (66 to 67) of integer; variable b : boolean; begin b := a1'length = 5; b := a1'low(1) = 1; b := a1'high(1) = 5; b := a1'left = 1; b := a1'right = 5; b := int2_vec'length = 2; b := int2_vec'low = 66; end process; process is begin case 1 is when 1 => null; when others => report "bang"; end case; end process; process is variable r : real; begin r := 1.5 * 2; r := 3 * 0.2; r := 5.0 / 2; r := 2.0 ** 4; end process; process is constant one : bit := '1'; variable b : boolean; begin b := one = '1'; b := '0' /= one; end process; -- Billowitch tc3170 tc3170: process is constant L : REAL := -10.0; constant R : REAL := 10.0; type RT1 is range L to R; begin assert ( RT1'right = RT1(R) ); -- Should be removed end process; bitvec: process is constant x : bit_vector(1 to 3) := "101"; constant y : bit_vector(1 to 3) := "110"; constant z : bit_vector(3 downto 1) := "011"; variable b : boolean; begin b := (x and y) = "100"; b := (y and z) = "010"; b := (x or y) = "111"; b := not x = "010"; b := (x xor y) = "011"; b := (x xnor y) = "100"; b := (x nand y) = "011"; b := (x nor y) = "000"; end process; end architecture;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: clkmux -- File: clkmux.vhd -- Author: Edvin Catovic - Gaisler Research -- Description: Glitch-free clock multiplexer ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use work.gencomp.all; use work.allclkgen.all; entity clkmux is generic(tech : integer := 0; rsel : integer range 0 to 1 := 0); -- registered sel port( i0, i1 : in std_ulogic; sel : in std_ulogic; o : out std_ulogic; rst : in std_ulogic := '1' ); end entity; architecture rtl of clkmux is signal seli, sel0, sel1, cg0, cg1 : std_ulogic; begin rs : if rsel = 1 generate rsproc : process(i0) begin if rising_edge(i0) then seli <= sel; end if; end process; end generate; cs : if rsel = 0 generate seli <= sel; end generate; tec : if has_clkmux(tech) = 1 generate xil : if is_unisim(tech) = 1 generate buf : clkmux_unisim port map(sel => seli, I0 => i0, I1 => i1, O => o); end generate; rhl : if tech = rhlib18t generate buf : clkmux_rhlib18t port map(sel => seli, I0 => i0, I1 => i1, O => o); end generate; ut13 : if tech = ut130 generate x0 : clkmux_ut130hbd port map (i0 => i0, i1 => i1, sel => sel, o => o); end generate; n2x : if tech = easic45 generate mux : clkmux_n2x port map (i0 => i0, i1 => i1, sel => sel, o => o); end generate; ut90n : if tech = ut90 generate x0 : clkmux_ut90nhbd port map (i0 => i0, i1 => i1, sel => seli, o => o); end generate; saed : if tech = saed32 generate x0 : clkmux_saed32 port map (i0 => i0, i1 => i1, sel => seli, o => o); end generate; dar : if tech = dare generate x0 : clkmux_dare port map (i0 => i0, i1 => i1, sel => seli, o => o); end generate; rhu : if tech = rhumc generate x0 : clkmux_rhumc port map (i0 => i0, i1 => i1, sel => seli, o => o); end generate; noxil : if not((is_unisim(tech) = 1) or (tech = rhlib18t) or (tech = ut130) or (tech = easic45) or (tech = ut90) or (tech = saed32) or (tech = dare) or (tech = rhumc)) generate o <= i0 when seli = '0' else i1; end generate; end generate; gen : if has_clkmux(tech) = 0 generate p0 : process(i0, rst) begin if rst = '0' then sel0 <= '1'; elsif falling_edge(i0) then sel0 <= (not seli) and (not sel1); end if; end process; p1 : process(i1, rst) begin if rst = '0' then sel1 <= '0'; elsif falling_edge(i1) then sel1 <= seli and (not sel0); end if; end process; cg0 <= i0 and sel0; cg1 <= i1 and sel1; o <= cg0 or cg1; end generate; end architecture;
-- Button Press Synchronizer para keys que são ativas baixas (ou seja, quando pressionadas vao para nivel baixo) library ieee; use ieee.std_logic_1164.all; entity ButtonSync is port ( -- Input ports key0 : in std_logic; key1 : in std_logic; key2 : in std_logic; key3 : in std_logic; clk : in std_logic; -- Output ports btn0 : out std_logic; btn1 : out std_logic; btn2 : out std_logic; btn3 : out std_logic ); end ButtonSync; -- Definicao de Arquitetura architecture ButtonSyncImpl of ButtonSync is type STATES is (EsperaApertar, SaidaAtiva, EsperaSoltar); signal btn0state, btn1state, btn2state, btn3state : STATES := EsperaApertar; signal btn0next, btn1next, btn2next, btn3next : STATES := EsperaApertar; begin process (clk) begin if clk'event and clk = '1' then -- Resposta na transicao positiva do clock btn0state <= btn0next; btn1state <= btn1next; btn2state <= btn2next; btn3state <= btn3next; end if; end process; process (key0,btn0state) -- Processo para botao 0 begin case btn0state is when EsperaApertar => -- esperar apertar o botao if key0 = '0' then btn0next <= SaidaAtiva; else btn0next <= EsperaApertar; end if; btn0 <= '1'; when SaidaAtiva => -- saida ativa por 1 ciclo de clock if key0 = '0' then btn0next <= EsperaSoltar; else btn0next <= EsperaApertar; end if; btn0 <= '0'; when EsperaSoltar => -- enquanto esta apertando o botao if key0 = '0' then btn0next <= EsperaSoltar; else btn0next <= EsperaApertar; end if; btn0 <= '1'; end case; end process; process (key1,btn1state) -- Processo para botao 1 begin case btn1state is when EsperaApertar => -- espera apertar o botao if key1 = '0' then btn1next <= SaidaAtiva; else btn1next <= EsperaApertar; end if; btn1 <= '1'; when SaidaAtiva => -- saida ativa por 1 ciclo de clock if key1 = '0' then btn1next <= EsperaSoltar; else btn1next <= EsperaApertar; end if; btn1 <= '0'; when EsperaSoltar => -- enquanto esta apertando o botao if key1 = '0' then btn1next <= EsperaSoltar; else btn1next <= EsperaApertar; end if; btn1 <= '1'; end case; end process; process (key2,btn2state) -- Processo para botao 2 begin case btn2state is when EsperaApertar => -- espera apertar o botao if key2 = '0' then btn2next <= SaidaAtiva; else btn2next <= EsperaApertar; end if; btn2 <= '1'; when SaidaAtiva => -- saida ativa para 1 ciclo de clock if key2 = '0' then btn2next <= EsperaSoltar; else btn2next <= EsperaApertar; end if; btn2 <= '0'; when EsperaSoltar => -- enquanto esta apertando o botao if key2 = '0' then btn2next <= EsperaSoltar; else btn2next <= EsperaApertar; end if; btn2 <= '1'; end case; end process; process (key3,btn3state) -- Processo para botao 3 begin case btn3state is when EsperaApertar => -- espera apertar o botao if key3 = '0' then btn3next <= SaidaAtiva; else btn3next <= EsperaApertar; end if; btn3 <= '1'; when SaidaAtiva => -- saida ativa para 1 ciclo de clock if key3 = '0' then btn3next <= EsperaSoltar; else btn3next <= EsperaApertar; end if; btn3 <= '0'; when EsperaSoltar => -- enquanto esta apertando o botao if key3 = '0' then btn3next <= EsperaSoltar; else btn3next <= EsperaApertar; end if; btn3 <= '1'; end case; end process; end ButtonSyncImpl;
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-- -- BananaCore - A processor written in VHDL -- -- Created by Rogiel Sulzbach. -- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved. -- library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; use ieee.std_logic_1164.std_logic; library BananaCore; use BananaCore.Core.all; use BananaCore.Memory.all; use BananaCore.RegisterPackage.all; -- The GreaterThanInstructionExecutor entity entity GreaterThanInstructionExecutor is port( -- the processor main clock clock: in BananaCore.Core.Clock; -- enables the instruction enable: in std_logic; -- the first register to operate on (argument 0) arg0_address: in RegisterAddress; -- the first register to operate on (argument 1) arg1_address: in RegisterAddress; -- a bus indicating if the instruction is ready or not instruction_ready: out std_logic := '0'; ------------------------------------------ -- MEMORY BUS ------------------------------------------ -- the address to read/write memory from/to memory_address: out MemoryAddress := (others => '0'); -- the memory being read to memory_data_read: in MemoryData; -- the memory being written to memory_data_write: out MemoryData := (others => '0'); -- the operation to perform on the memory memory_operation: out MemoryOperation := MEMORY_OP_DISABLED; -- a flag indicating if a memory operation should be performed memory_enable: out std_logic; -- a flag indicating if a memory operation has completed memory_ready: in std_logic; ------------------------------------------ -- REGISTER BUS ------------------------------------------ -- the processor register address bus register_address: out RegisterAddress := (others => '0'); -- the processor register data bus register_data_read: in RegisterData; -- the processor register data bus register_data_write: out RegisterData := (others => '0'); -- the processor register operation signal register_operation: out RegisterOperation := OP_REG_DISABLED; -- the processor register enable signal register_enable: out std_logic := '0'; -- a flag indicating if a register operation has completed register_ready: in std_logic ); end GreaterThanInstructionExecutor; architecture GreaterThanInstructionExecutorImpl of GreaterThanInstructionExecutor is type state_type is ( fetch_arg0, store_arg0, fetch_arg1, store_arg1, execute, store_result, complete ); signal state: state_type := fetch_arg0; signal arg0: RegisterData; signal arg1: RegisterData; signal result: std_logic; begin process (clock) begin if clock'event and clock = '1' then if enable = '1' then case state is when fetch_arg0 => instruction_ready <= '0'; register_address <= arg0_address; register_operation <= OP_REG_GET; register_enable <= '1'; state <= store_arg0; when store_arg0 => if register_ready = '1' then arg0 <= register_data_read; register_enable <= '0'; state <= fetch_arg1; else state <= store_arg0; end if; when fetch_arg1 => register_address <= arg1_address; register_operation <= OP_REG_GET; register_enable <= '1'; state <= store_arg1; when store_arg1 => if register_ready = '1' then arg1 <= register_data_read; register_enable <= '0'; state <= execute; else state <= store_arg1; end if; when execute => if arg0 > arg1 then result <= '1'; else result <= '0'; end if; state <= store_result; when store_result => register_address <= SpecialRegister; register_operation <= OP_REG_SET; register_data_write(CarryBit) <= result; register_enable <= '1'; instruction_ready <= '1'; state <= complete; when complete => state <= complete; end case; else instruction_ready <= '0'; state <= fetch_arg0; end if; end if; end process; end GreaterThanInstructionExecutorImpl;
-- -- This file is part of giovanni_card -- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr ) -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/> -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity giovanni_card is Port ( w1a : inout STD_LOGIC_VECTOR (15 downto 0); w1b : inout STD_LOGIC_VECTOR (15 downto 0); scr_red : in STD_LOGIC_VECTOR (5 downto 0); scr_green : in STD_LOGIC_VECTOR (5 downto 0); scr_blue : in STD_LOGIC_VECTOR (5 downto 0); scr_clk : in STD_LOGIC; scr_hsync : in STD_LOGIC; scr_vsync : in STD_LOGIC; scr_enable : in STD_LOGIC; scr_right_left : in STD_LOGIC; scr_up_down : in STD_LOGIC; audio_right : in STD_LOGIC; --pin 2 audio audio_left : in STD_LOGIC; -- pin 3 audio audio_stereo_ok : out STD_LOGIC; -- pin 4 audio audio_plugged : out STD_LOGIC; -- pin 5 audio io : inout STD_LOGIC_VECTOR (3 downto 0)); end giovanni_card; architecture Behavioral of giovanni_card is signal reg_scr_red : std_logic_vector(5 downto 0) := (others => '0'); signal reg_scr_green : std_logic_vector(5 downto 0) := (others => '0'); signal reg_scr_blue : std_logic_vector(5 downto 0) := (others => '0'); signal reg_scr_hsync : std_logic := '0'; signal reg_scr_vsync : std_logic := '0'; signal reg_scr_enable : std_logic := '0'; begin screens_signals_register : process(scr_clk) begin if rising_edge(scr_clk) then reg_scr_red <= scr_red; reg_scr_green <= scr_green; reg_scr_blue <= scr_blue; reg_scr_hsync <= scr_hsync; reg_scr_vsync <= scr_vsync; reg_scr_enable <= scr_enable; end if; end process; w1a(0) <= io(0); w1a(1) <= io(1); w1a(2) <= scr_up_down; -- LCD_31 w1a(3) <= reg_scr_enable; -- LCD_27 w1a(4) <= reg_scr_blue(5); -- LCD_25 w1a(5) <= reg_scr_blue(3); -- LCD_23 w1a(6) <= reg_scr_blue(1); -- LCD_21 w1a(7) <= reg_scr_green(4); -- LCD_17 w1a(8) <= reg_scr_green(2); -- LCD_15 w1a(9) <= reg_scr_green(0); -- LCD_13 w1a(10) <= reg_scr_red(5); -- LCD_11 w1a(11) <= reg_scr_red(3); -- LCD_9 w1a(12) <= reg_scr_red(1); -- LCD_7 w1a(13) <= reg_scr_hsync; -- LCD_3 w1a(14) <= audio_right; w1a(15) <= audio_left; audio_stereo_ok <= w1b(0); audio_plugged <= w1b(1); w1b(2) <= scr_clk; -- LCD 2 w1b(3) <= reg_scr_vsync; -- LCD 4 w1b(4) <= reg_scr_red(0); -- LCD_6 w1b(5) <= reg_scr_red(2); -- LCD_8 w1b(6) <= reg_scr_red(4); -- LCD_10 w1b(7) <= reg_scr_green(1); -- LCD_14 w1b(8) <= reg_scr_green(3); -- LCD_16 w1b(9) <= reg_scr_green(5); -- LCD_18 w1b(10) <= reg_scr_blue(0); -- LCD_20 w1b(11) <= reg_scr_blue(2); -- LCD_22 w1b(12) <= reg_scr_blue(4); -- LCD_24 w1b(13) <= scr_right_left; --LCD_30 w1b(14) <= io(2); w1b(15) <= io(3); end Behavioral;
entity FIFO is port ( I_WR_EN : in std_logic; I_DATA : out std_logic_vector(31 downto 0); I_RD_EN : in std_logic; O_DATA : out std_logic_vector(31 downto 0) ); end entity FIFO; entity FIFO is port ( i_wr_en : in std_logic; i_data : out std_logic_vector(31 downto 0); i_rd_en : in std_logic; o_data : out std_logic_vector(31 downto 0) ); end entity FIFO;
------------------------------------------------------------------------------------------------- -- Company : CNES -- Author : Mickael Carl (CNES) -- Copyright : Copyright (c) CNES. -- Licensing : GNU GPLv3 ------------------------------------------------------------------------------------------------- -- Version : V1 -- Version history : -- V1 : 2015-04-09 : Mickael Carl (CNES): Creation ------------------------------------------------------------------------------------------------- -- File name : STD_06500_good.vhd -- File Creation date : 2015-04-09 -- Project name : VHDL Handbook CNES Edition ------------------------------------------------------------------------------------------------- -- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor) ------------------------------------------------------------------------------------------------- -- Description : Handbook example: Counters end of counting: good example -- -- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at -- demonstrating good practices in VHDL and as such, its design is minimalistic. -- It is provided as is, without any warranty. -- This example is compliant with the Handbook version 1. -- ------------------------------------------------------------------------------------------------- -- Naming conventions: -- -- i_Port: Input entity port -- o_Port: Output entity port -- b_Port: Bidirectional entity port -- g_My_Generic: Generic entity port -- -- c_My_Constant: Constant definition -- t_My_Type: Custom type definition -- -- My_Signal_n: Active low signal -- v_My_Variable: Variable -- sm_My_Signal: FSM signal -- pkg_Param: Element Param coming from a package -- -- My_Signal_re: Rising edge detection of My_Signal -- My_Signal_fe: Falling edge detection of My_Signal -- My_Signal_rX: X times registered My_Signal signal -- -- P_Process_Name: Process -- ------------------------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity STD_06500_good is port ( i_Clock : in std_logic; -- Main clock signal i_Reset_n : in std_logic; -- Main reset signal i_Enable : in std_logic; -- Enables the counter i_Length : in std_logic_vector(3 downto 0); -- Unsigned Value for Counter Period o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value) ); end STD_06500_good; --CODE architecture Behavioral of STD_06500_good is signal Count : unsigned(3 downto 0); -- Counter output signal (unsigned converted) signal Count_Length : unsigned(3 downto 0); -- Length input signal (unsigned converted) begin Count_Length <= unsigned(i_Length); -- Will count undefinitely from 0 to i_Length while i_Enable is asserted P_Count : process(i_Reset_n, i_Clock) begin if (i_Reset_n = '0') then Count <= (others => '0'); elsif (rising_edge(i_Clock)) then if (Count >= Count_Length) then -- Counter restarts from 0 Count <= (others => '0'); elsif (i_Enable = '1') then -- Increment counter value Count <= Count + 1; end if; end if; end process; o_Count <= std_logic_vector(Count); end Behavioral; --CODE
-- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module.vhd -- Generated using ACDS version 13.1 162 at 2015.02.12.15:50:58 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is port ( sop : in std_logic := '0'; -- sop.wire Clock : in std_logic := '0'; -- Clock.clk aclr : in std_logic := '0'; -- .reset data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire data_out : out std_logic_vector(23 downto 0); -- data_out.wire writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire addr : in std_logic_vector(1 downto 0) := (others => '0'); -- addr.wire eop : in std_logic := '0'; -- eop.wire write : in std_logic := '0' -- write.wire ); end entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module; architecture rtl of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is component alt_dspbuilder_clock_GNQFU4PUDH is port ( aclr : in std_logic := 'X'; -- reset aclr_n : in std_logic := 'X'; -- reset_n aclr_out : out std_logic; -- reset clock : in std_logic := 'X'; -- clk clock_out : out std_logic -- clk ); end component alt_dspbuilder_clock_GNQFU4PUDH; component alt_dspbuilder_cast_GNLF52SJQ3 is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(7 downto 0) -- wire ); end component alt_dspbuilder_cast_GNLF52SJQ3; component alt_dspbuilder_cast_GNJGR7GQ2L is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(17 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(7 downto 0) -- wire ); end component alt_dspbuilder_cast_GNJGR7GQ2L; component alt_dspbuilder_cast_GNKXX25S2S is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(7 downto 0) -- wire ); end component alt_dspbuilder_cast_GNKXX25S2S; component alt_dspbuilder_cast_GN6OMCQQS7 is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(7 downto 0) -- wire ); end component alt_dspbuilder_cast_GN6OMCQQS7; component alt_dspbuilder_port_GNEPKLLZKY is port ( input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(31 downto 0) -- wire ); end component alt_dspbuilder_port_GNEPKLLZKY; component alt_dspbuilder_multiplexer_GNCALBUTDR is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; use_one_hot_select_bus : natural := 0; width : positive := 8; pipeline : natural := 0; number_inputs : natural := 4 ); port ( clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset sel : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire result : out std_logic_vector(23 downto 0); -- wire ena : in std_logic := 'X'; -- wire user_aclr : in std_logic := 'X'; -- wire in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire in1 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire ); end component alt_dspbuilder_multiplexer_GNCALBUTDR; component alt_dspbuilder_gnd_GN is port ( output : out std_logic -- wire ); end component alt_dspbuilder_gnd_GN; component alt_dspbuilder_vcc_GN is port ( output : out std_logic -- wire ); end component alt_dspbuilder_vcc_GN; component alt_dspbuilder_port_GN6TDLHAW6 is port ( input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(1 downto 0) -- wire ); end component alt_dspbuilder_port_GN6TDLHAW6; component alt_dspbuilder_constant_GNZEH3JAKA is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; BitPattern : string := "0000"; width : natural := 4 ); port ( output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_constant_GNZEH3JAKA; component alt_dspbuilder_constant_GNPXZ5JSVR is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; BitPattern : string := "0000"; width : natural := 4 ); port ( output : out std_logic_vector(3 downto 0) -- wire ); end component alt_dspbuilder_constant_GNPXZ5JSVR; component alt_dspbuilder_bus_concat_GN55ETJ4VI is generic ( widthB : natural := 8; widthA : natural := 8 ); port ( a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire aclr : in std_logic := 'X'; -- clk b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire clock : in std_logic := 'X'; -- clk output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire ); end component alt_dspbuilder_bus_concat_GN55ETJ4VI; component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is generic ( LogicalOp : string := "AltAND"; number_inputs : positive := 2 ); port ( result : out std_logic; -- wire data0 : in std_logic := 'X'; -- wire data1 : in std_logic := 'X' -- wire ); end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V; component alt_dspbuilder_bus_concat_GNIIOZRPJD is generic ( widthB : natural := 8; widthA : natural := 8 ); port ( a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire aclr : in std_logic := 'X'; -- clk b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire clock : in std_logic := 'X'; -- clk output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire ); end component alt_dspbuilder_bus_concat_GNIIOZRPJD; component alt_dspbuilder_constant_GNNKZSYI73 is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; BitPattern : string := "0000"; width : natural := 4 ); port ( output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_constant_GNNKZSYI73; component alt_dspbuilder_if_statement_GNYT6HZJI5 is generic ( use_else_output : natural := 0; bwr : natural := 0; use_else_input : natural := 0; signed : natural := 1; HDLTYPE : string := "STD_LOGIC_VECTOR"; if_expression : string := "a"; number_inputs : integer := 1; width : natural := 8 ); port ( true : out std_logic; -- wire a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire b : in std_logic_vector(7 downto 0) := (others => 'X') -- wire ); end component alt_dspbuilder_if_statement_GNYT6HZJI5; component alt_dspbuilder_constant_GNLMV7GZFA is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; BitPattern : string := "0000"; width : natural := 4 ); port ( output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_constant_GNLMV7GZFA; component alt_dspbuilder_delay_GNUECIBFDH is generic ( ClockPhase : string := "1"; delay : positive := 1; use_init : natural := 0; BitPattern : string := "00000001"; width : positive := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk ena : in std_logic := 'X'; -- wire input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(width-1 downto 0); -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_delay_GNUECIBFDH; component alt_dspbuilder_port_GN37ALZBS4 is port ( input : in std_logic := 'X'; -- wire output : out std_logic -- wire ); end component alt_dspbuilder_port_GN37ALZBS4; component alt_dspbuilder_decoder_GNA3ETEQ66 is generic ( decode : string := "00000000"; pipeline : natural := 0; width : natural := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire dec : out std_logic; -- wire ena : in std_logic := 'X'; -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_decoder_GNA3ETEQ66; component alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "00000000"; pipeline : natural := 0; width : natural := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire dec : out std_logic; -- wire ena : in std_logic := 'X'; -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_decoder_GNSCEXJCJK; component alt_dspbuilder_barrelshifter_GNV5DVAGHT is generic ( DISTANCE_WIDTH : natural := 3; NDIRECTION : natural := 0; SIGNED : integer := 1; use_dedicated_circuitry : string := "false"; PIPELINE : natural := 0; WIDTH : natural := 8 ); port ( a : in std_logic_vector(WIDTH-1 downto 0) := (others => 'X'); -- wire aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk direction : in std_logic := 'X'; -- wire distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0) := (others => 'X'); -- wire ena : in std_logic := 'X'; -- wire r : out std_logic_vector(WIDTH-1 downto 0); -- wire user_aclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_barrelshifter_GNV5DVAGHT; component alt_dspbuilder_multiply_add_GNKLXFKAO3 is generic ( family : string := "Stratix"; direction : string := "AddAdd"; data3b_const : string := "00000000"; data2b_const : string := "00000000"; representation : string := "SIGNED"; dataWidth : integer := 8; data4b_const : string := "00000000"; number_multipliers : integer := 2; pipeline_register : string := "NoRegister"; use_dedicated_circuitry : integer := 0; data1b_const : string := "00000000"; use_b_consts : natural := 0 ); port ( clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset data1a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire data2a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire data3a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire result : out std_logic_vector(17 downto 0); -- wire user_aclr : in std_logic := 'X'; -- wire ena : in std_logic := 'X' -- wire ); end component alt_dspbuilder_multiply_add_GNKLXFKAO3; component alt_dspbuilder_delay_GND2PGZRBZ is generic ( ClockPhase : string := "1"; delay : positive := 1; use_init : natural := 0; BitPattern : string := "00000001"; width : positive := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk ena : in std_logic := 'X'; -- wire input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(width-1 downto 0); -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_delay_GND2PGZRBZ; component alt_dspbuilder_delay_GNHYCSAEGT is generic ( ClockPhase : string := "1"; delay : positive := 1; use_init : natural := 0; BitPattern : string := "00000001"; width : positive := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk ena : in std_logic := 'X'; -- wire input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(width-1 downto 0); -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_delay_GNHYCSAEGT; component alt_dspbuilder_if_statement_GN7VA7SRUP is generic ( use_else_output : natural := 0; bwr : natural := 0; use_else_input : natural := 0; signed : natural := 1; HDLTYPE : string := "STD_LOGIC_VECTOR"; if_expression : string := "a"; number_inputs : integer := 1; width : natural := 8 ); port ( true : out std_logic; -- wire a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire ); end component alt_dspbuilder_if_statement_GN7VA7SRUP; component alt_dspbuilder_delay_GNVTJPHWYT is generic ( ClockPhase : string := "1"; delay : positive := 1; use_init : natural := 0; BitPattern : string := "00000001"; width : positive := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk ena : in std_logic := 'X'; -- wire input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(width-1 downto 0); -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_delay_GNVTJPHWYT; component alt_dspbuilder_port_GNOC3SGKQJ is port ( input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_port_GNOC3SGKQJ; component alt_dspbuilder_decoder_GNM4LOIHXZ is generic ( decode : string := "00000000"; pipeline : natural := 0; width : natural := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire dec : out std_logic; -- wire ena : in std_logic := 'X'; -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_decoder_GNM4LOIHXZ; component alt_dspbuilder_cast_GNZ5LMFB5D is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(0 downto 0) -- wire ); end component alt_dspbuilder_cast_GNZ5LMFB5D; component alt_dspbuilder_cast_GN7IAAYCSZ is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(7 downto 0) -- wire ); end component alt_dspbuilder_cast_GN7IAAYCSZ; component alt_dspbuilder_cast_GNSB3OXIQS is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire output : out std_logic -- wire ); end component alt_dspbuilder_cast_GNSB3OXIQS; component alt_dspbuilder_cast_GN46N4UJ5S is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic := 'X'; -- wire output : out std_logic_vector(0 downto 0) -- wire ); end component alt_dspbuilder_cast_GN46N4UJ5S; signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena signal decoder2sclrgnd_output_wire : std_logic; -- Decoder2sclrGND:output -> Decoder2:sclr signal decoder2enavcc_output_wire : std_logic; -- Decoder2enaVCC:output -> Decoder2:ena signal decoder3sclrgnd_output_wire : std_logic; -- Decoder3sclrGND:output -> Decoder3:sclr signal decoder3enavcc_output_wire : std_logic; -- Decoder3enaVCC:output -> Decoder3:ena signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena signal barrel_shifteruser_aclrgnd_output_wire : std_logic; -- Barrel_Shifteruser_aclrGND:output -> Barrel_Shifter:user_aclr signal barrel_shifterenavcc_output_wire : std_logic; -- Barrel_ShifterenaVCC:output -> Barrel_Shifter:ena signal multiply_adduser_aclrgnd_output_wire : std_logic; -- Multiply_Adduser_aclrGND:output -> Multiply_Add:user_aclr signal multiply_addenavcc_output_wire : std_logic; -- Multiply_AddenaVCC:output -> Multiply_Add:ena signal delay6sclrgnd_output_wire : std_logic; -- Delay6sclrGND:output -> Delay6:sclr signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr signal delay4enavcc_output_wire : std_logic; -- Delay4enaVCC:output -> Delay4:ena signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena signal multiplexer2user_aclrgnd_output_wire : std_logic; -- Multiplexer2user_aclrGND:output -> Multiplexer2:user_aclr signal multiplexer2enavcc_output_wire : std_logic; -- Multiplexer2enaVCC:output -> Multiplexer2:ena signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena signal bus_concatenation_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation:output -> Bus_Concatenation1:b signal bus_concatenation1_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation1:output -> [Bus_Conversion:input, Multiplexer2:in0] signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> [Bus_Conversion1:input, Bus_Conversion6:input] signal barrel_shifter_r_wire : std_logic_vector(17 downto 0); -- Barrel_Shifter:r -> Bus_Conversion2:input signal bus_conversion2_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion2:output -> [Bus_Concatenation1:a, Bus_Concatenation:a, Bus_Concatenation:b] signal constant5_output_wire : std_logic_vector(3 downto 0); -- Constant5:output -> Barrel_Shifter:distance signal addr_0_output_wire : std_logic_vector(1 downto 0); -- addr_0:output -> [Decoder2:data, Decoder:data] signal bus_conversion1_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion1:output -> Delay2:input signal delay2_output_wire : std_logic_vector(7 downto 0); -- Delay2:output -> Delay3:input signal delay4_output_wire : std_logic_vector(0 downto 0); -- Delay4:output -> [Delay:input, cast49:input] signal bus_conversion6_output_wire : std_logic_vector(0 downto 0); -- Bus_Conversion6:output -> Delay5:input signal delay5_output_wire : std_logic_vector(0 downto 0); -- Delay5:output -> Delay6:input signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Bus_Conversion3:input, Bus_Conversion4:input, Bus_Conversion5:input, Decoder1:data, Decoder3:data, If_Statement1:a, Multiplexer:in0] signal bus_conversion_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion:output -> If_Statement:a signal delay3_output_wire : std_logic_vector(7 downto 0); -- Delay3:output -> If_Statement:b signal constant3_output_wire : std_logic_vector(23 downto 0); -- Constant3:output -> If_Statement1:b signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> If_Statement1:c signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Logical_Bit_Operator:data0 signal sop_0_output_wire : std_logic; -- sop_0:output -> [Logical_Bit_Operator3:data0, Logical_Bit_Operator5:data0, Logical_Bit_Operator:data1] signal eop_0_output_wire : std_logic; -- eop_0:output -> Logical_Bit_Operator1:data0 signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator2:data0 signal write_0_output_wire : std_logic; -- write_0:output -> [Logical_Bit_Operator2:data1, Logical_Bit_Operator4:data1] signal logical_bit_operator2_result_wire : std_logic; -- Logical_Bit_Operator2:result -> Delay2:ena signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator3:data1 signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Delay3:ena signal decoder2_dec_wire : std_logic; -- Decoder2:dec -> Logical_Bit_Operator4:data0 signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Delay5:ena signal decoder3_dec_wire : std_logic; -- Decoder3:dec -> Logical_Bit_Operator5:data1 signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> Delay6:ena signal delay_output_wire : std_logic_vector(0 downto 0); -- Delay:output -> [Multiplexer:sel, cast51:input] signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Multiplexer1:in0 signal constant2_output_wire : std_logic_vector(23 downto 0); -- Constant2:output -> Multiplexer1:in1 signal delay6_output_wire : std_logic_vector(0 downto 0); -- Delay6:output -> Multiplexer2:sel signal multiplexer1_result_wire : std_logic_vector(23 downto 0); -- Multiplexer1:result -> Multiplexer2:in1 signal multiplexer2_result_wire : std_logic_vector(23 downto 0); -- Multiplexer2:result -> Multiplexer:in1 signal bus_conversion5_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion5:output -> Multiply_Add:data1a signal bus_conversion4_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion4:output -> Multiply_Add:data2a signal bus_conversion3_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion3:output -> Multiply_Add:data3a signal multiply_add_result_wire : std_logic_vector(17 downto 0); -- Multiply_Add:result -> Barrel_Shifter:a signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> data_out_0:input signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> cast48:input signal cast48_output_wire : std_logic; -- cast48:output -> Delay:sclr signal cast49_output_wire : std_logic; -- cast49:output -> Delay:ena signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> cast50:input signal cast50_output_wire : std_logic_vector(0 downto 0); -- cast50:output -> Delay4:input signal cast51_output_wire : std_logic; -- cast51:output -> Logical_Bit_Operator1:data1 signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> cast52:input signal cast52_output_wire : std_logic_vector(0 downto 0); -- cast52:output -> Delay1:input signal if_statement_true_wire : std_logic; -- If_Statement:true -> cast53:input signal cast53_output_wire : std_logic_vector(0 downto 0); -- cast53:output -> Multiplexer1:sel signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Barrel_Shifter:aclr, Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Decoder1:aclr, Decoder2:aclr, Decoder3:aclr, Decoder:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay4:aclr, Delay5:aclr, Delay6:aclr, Delay:aclr, Multiplexer1:aclr, Multiplexer2:aclr, Multiplexer:aclr, Multiply_Add:aclr] signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Barrel_Shifter:clock, Bus_Concatenation1:clock, Bus_Concatenation:clock, Decoder1:clock, Decoder2:clock, Decoder3:clock, Decoder:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay4:clock, Delay5:clock, Delay6:clock, Delay:clock, Multiplexer1:clock, Multiplexer2:clock, Multiplexer:clock, Multiply_Add:clock] begin clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH port map ( clock_out => clock_0_clock_output_clk, -- clock_output.clk aclr_out => clock_0_clock_output_reset, -- .reset clock => Clock, -- clock.clk aclr => aclr -- .reset ); bus_conversion1 : component alt_dspbuilder_cast_GNLF52SJQ3 generic map ( round => 0, saturate => 0 ) port map ( input => writedata_0_output_wire, -- input.wire output => bus_conversion1_output_wire -- output.wire ); bus_conversion2 : component alt_dspbuilder_cast_GNJGR7GQ2L generic map ( round => 0, saturate => 0 ) port map ( input => barrel_shifter_r_wire, -- input.wire output => bus_conversion2_output_wire -- output.wire ); bus_conversion3 : component alt_dspbuilder_cast_GNKXX25S2S generic map ( round => 0, saturate => 0 ) port map ( input => data_in_0_output_wire, -- input.wire output => bus_conversion3_output_wire -- output.wire ); bus_conversion4 : component alt_dspbuilder_cast_GN6OMCQQS7 generic map ( round => 0, saturate => 0 ) port map ( input => data_in_0_output_wire, -- input.wire output => bus_conversion4_output_wire -- output.wire ); writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY port map ( input => writedata, -- input.wire output => writedata_0_output_wire -- output.wire ); multiplexer : component alt_dspbuilder_multiplexer_GNCALBUTDR generic map ( HDLTYPE => "STD_LOGIC_VECTOR", use_one_hot_select_bus => 0, width => 24, pipeline => 0, number_inputs => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset sel => delay_output_wire, -- sel.wire result => multiplexer_result_wire, -- result.wire ena => multiplexerenavcc_output_wire, -- ena.wire user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire in0 => data_in_0_output_wire, -- in0.wire in1 => multiplexer2_result_wire -- in1.wire ); multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN port map ( output => multiplexeruser_aclrgnd_output_wire -- output.wire ); multiplexerenavcc : component alt_dspbuilder_vcc_GN port map ( output => multiplexerenavcc_output_wire -- output.wire ); bus_conversion : component alt_dspbuilder_cast_GNKXX25S2S generic map ( round => 0, saturate => 0 ) port map ( input => bus_concatenation1_output_wire, -- input.wire output => bus_conversion_output_wire -- output.wire ); addr_0 : component alt_dspbuilder_port_GN6TDLHAW6 port map ( input => addr, -- input.wire output => addr_0_output_wire -- output.wire ); constant4 : component alt_dspbuilder_constant_GNZEH3JAKA generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "000000000000000000001111", width => 24 ) port map ( output => constant4_output_wire -- output.wire ); constant5 : component alt_dspbuilder_constant_GNPXZ5JSVR generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "1000", width => 4 ) port map ( output => constant5_output_wire -- output.wire ); bus_concatenation1 : component alt_dspbuilder_bus_concat_GN55ETJ4VI generic map ( widthB => 16, widthA => 8 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset a => bus_conversion2_output_wire, -- a.wire b => bus_concatenation_output_wire, -- b.wire output => bus_concatenation1_output_wire -- output.wire ); logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator5_result_wire, -- result.wire data0 => sop_0_output_wire, -- data0.wire data1 => decoder3_dec_wire -- data1.wire ); logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator4_result_wire, -- result.wire data0 => decoder2_dec_wire, -- data0.wire data1 => write_0_output_wire -- data1.wire ); bus_concatenation : component alt_dspbuilder_bus_concat_GNIIOZRPJD generic map ( widthB => 8, widthA => 8 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset a => bus_conversion2_output_wire, -- a.wire b => bus_conversion2_output_wire, -- b.wire output => bus_concatenation_output_wire -- output.wire ); constant3 : component alt_dspbuilder_constant_GNNKZSYI73 generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "000000000000000000000000", width => 24 ) port map ( output => constant3_output_wire -- output.wire ); if_statement : component alt_dspbuilder_if_statement_GNYT6HZJI5 generic map ( use_else_output => 0, bwr => 0, use_else_input => 0, signed => 0, HDLTYPE => "STD_LOGIC_VECTOR", if_expression => "a>b", number_inputs => 2, width => 8 ) port map ( true => if_statement_true_wire, -- true.wire a => bus_conversion_output_wire, -- a.wire b => delay3_output_wire -- b.wire ); constant2 : component alt_dspbuilder_constant_GNLMV7GZFA generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "111111111111111111111111", width => 24 ) port map ( output => constant2_output_wire -- output.wire ); delay : component alt_dspbuilder_delay_GNUECIBFDH generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "0", width => 1 ) port map ( input => delay4_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay_output_wire, -- output.wire sclr => cast48_output_wire, -- sclr.wire ena => cast49_output_wire -- ena.wire ); constant1 : component alt_dspbuilder_constant_GNNKZSYI73 generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "000000000000000000000000", width => 24 ) port map ( output => constant1_output_wire -- output.wire ); write_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => write, -- input.wire output => write_0_output_wire -- output.wire ); logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator3_result_wire, -- result.wire data0 => sop_0_output_wire, -- data0.wire data1 => decoder1_dec_wire -- data1.wire ); logical_bit_operator2 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator2_result_wire, -- result.wire data0 => decoder_dec_wire, -- data0.wire data1 => write_0_output_wire -- data1.wire ); eop_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => eop, -- input.wire output => eop_0_output_wire -- output.wire ); logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator1_result_wire, -- result.wire data0 => eop_0_output_wire, -- data0.wire data1 => cast51_output_wire -- data1.wire ); decoder2 : component alt_dspbuilder_decoder_GNA3ETEQ66 generic map ( decode => "00", pipeline => 1, width => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset data => addr_0_output_wire, -- data.wire dec => decoder2_dec_wire, -- dec.wire sclr => decoder2sclrgnd_output_wire, -- sclr.wire ena => decoder2enavcc_output_wire -- ena.wire ); decoder2sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => decoder2sclrgnd_output_wire -- output.wire ); decoder2enavcc : component alt_dspbuilder_vcc_GN port map ( output => decoder2enavcc_output_wire -- output.wire ); decoder3 : component alt_dspbuilder_decoder_GNSCEXJCJK generic map ( decode => "000000000000000000001111", pipeline => 0, width => 24 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset data => data_in_0_output_wire, -- data.wire dec => decoder3_dec_wire, -- dec.wire sclr => decoder3sclrgnd_output_wire, -- sclr.wire ena => decoder3enavcc_output_wire -- ena.wire ); decoder3sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => decoder3sclrgnd_output_wire -- output.wire ); decoder3enavcc : component alt_dspbuilder_vcc_GN port map ( output => decoder3enavcc_output_wire -- output.wire ); decoder1 : component alt_dspbuilder_decoder_GNSCEXJCJK generic map ( decode => "000000000000000000001111", pipeline => 0, width => 24 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset data => data_in_0_output_wire, -- data.wire dec => decoder1_dec_wire, -- dec.wire sclr => decoder1sclrgnd_output_wire, -- sclr.wire ena => decoder1enavcc_output_wire -- ena.wire ); decoder1sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => decoder1sclrgnd_output_wire -- output.wire ); decoder1enavcc : component alt_dspbuilder_vcc_GN port map ( output => decoder1enavcc_output_wire -- output.wire ); logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator_result_wire, -- result.wire data0 => if_statement1_true_wire, -- data0.wire data1 => sop_0_output_wire -- data1.wire ); barrel_shifter : component alt_dspbuilder_barrelshifter_GNV5DVAGHT generic map ( DISTANCE_WIDTH => 4, NDIRECTION => 1, SIGNED => 0, use_dedicated_circuitry => "false", PIPELINE => 0, WIDTH => 18 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset a => multiply_add_result_wire, -- a.wire r => barrel_shifter_r_wire, -- r.wire distance => constant5_output_wire, -- distance.wire ena => barrel_shifterenavcc_output_wire, -- ena.wire user_aclr => barrel_shifteruser_aclrgnd_output_wire -- user_aclr.wire ); barrel_shifteruser_aclrgnd : component alt_dspbuilder_gnd_GN port map ( output => barrel_shifteruser_aclrgnd_output_wire -- output.wire ); barrel_shifterenavcc : component alt_dspbuilder_vcc_GN port map ( output => barrel_shifterenavcc_output_wire -- output.wire ); multiply_add : component alt_dspbuilder_multiply_add_GNKLXFKAO3 generic map ( family => "Cyclone V", direction => "AddAdd", data3b_const => "00011110", data2b_const => "10010110", representation => "UNSIGNED", dataWidth => 8, data4b_const => "01001100", number_multipliers => 3, pipeline_register => "NoRegister", use_dedicated_circuitry => 1, data1b_const => "01001100", use_b_consts => 1 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset data1a => bus_conversion5_output_wire, -- data1a.wire data2a => bus_conversion4_output_wire, -- data2a.wire data3a => bus_conversion3_output_wire, -- data3a.wire result => multiply_add_result_wire, -- result.wire user_aclr => multiply_adduser_aclrgnd_output_wire, -- user_aclr.wire ena => multiply_addenavcc_output_wire -- ena.wire ); multiply_adduser_aclrgnd : component alt_dspbuilder_gnd_GN port map ( output => multiply_adduser_aclrgnd_output_wire -- output.wire ); multiply_addenavcc : component alt_dspbuilder_vcc_GN port map ( output => multiply_addenavcc_output_wire -- output.wire ); delay6 : component alt_dspbuilder_delay_GND2PGZRBZ generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "1", width => 1 ) port map ( input => delay5_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay6_output_wire, -- output.wire sclr => delay6sclrgnd_output_wire, -- sclr.wire ena => logical_bit_operator5_result_wire -- ena.wire ); delay6sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay6sclrgnd_output_wire -- output.wire ); delay5 : component alt_dspbuilder_delay_GND2PGZRBZ generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "1", width => 1 ) port map ( input => bus_conversion6_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay5_output_wire, -- output.wire sclr => delay5sclrgnd_output_wire, -- sclr.wire ena => logical_bit_operator4_result_wire -- ena.wire ); delay5sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay5sclrgnd_output_wire -- output.wire ); delay4 : component alt_dspbuilder_delay_GNHYCSAEGT generic map ( ClockPhase => "1", delay => 1, use_init => 0, BitPattern => "0", width => 1 ) port map ( input => cast50_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay4_output_wire, -- output.wire sclr => delay4sclrgnd_output_wire, -- sclr.wire ena => delay4enavcc_output_wire -- ena.wire ); delay4sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay4sclrgnd_output_wire -- output.wire ); delay4enavcc : component alt_dspbuilder_vcc_GN port map ( output => delay4enavcc_output_wire -- output.wire ); if_statement1 : component alt_dspbuilder_if_statement_GN7VA7SRUP generic map ( use_else_output => 0, bwr => 0, use_else_input => 0, signed => 0, HDLTYPE => "STD_LOGIC_VECTOR", if_expression => "(a=b) and (a /= c)", number_inputs => 3, width => 24 ) port map ( true => if_statement1_true_wire, -- true.wire a => data_in_0_output_wire, -- a.wire b => constant3_output_wire, -- b.wire c => constant4_output_wire -- c.wire ); delay3 : component alt_dspbuilder_delay_GNVTJPHWYT generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "01111111", width => 8 ) port map ( input => delay2_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay3_output_wire, -- output.wire sclr => delay3sclrgnd_output_wire, -- sclr.wire ena => logical_bit_operator3_result_wire -- ena.wire ); delay3sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay3sclrgnd_output_wire -- output.wire ); sop_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => sop, -- input.wire output => sop_0_output_wire -- output.wire ); multiplexer1 : component alt_dspbuilder_multiplexer_GNCALBUTDR generic map ( HDLTYPE => "STD_LOGIC_VECTOR", use_one_hot_select_bus => 0, width => 24, pipeline => 0, number_inputs => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset sel => cast53_output_wire, -- sel.wire result => multiplexer1_result_wire, -- result.wire ena => multiplexer1enavcc_output_wire, -- ena.wire user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire in0 => constant1_output_wire, -- in0.wire in1 => constant2_output_wire -- in1.wire ); multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN port map ( output => multiplexer1user_aclrgnd_output_wire -- output.wire ); multiplexer1enavcc : component alt_dspbuilder_vcc_GN port map ( output => multiplexer1enavcc_output_wire -- output.wire ); delay1 : component alt_dspbuilder_delay_GNHYCSAEGT generic map ( ClockPhase => "1", delay => 1, use_init => 0, BitPattern => "0", width => 1 ) port map ( input => cast52_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay1_output_wire, -- output.wire sclr => delay1sclrgnd_output_wire, -- sclr.wire ena => delay1enavcc_output_wire -- ena.wire ); delay1sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay1sclrgnd_output_wire -- output.wire ); delay1enavcc : component alt_dspbuilder_vcc_GN port map ( output => delay1enavcc_output_wire -- output.wire ); multiplexer2 : component alt_dspbuilder_multiplexer_GNCALBUTDR generic map ( HDLTYPE => "STD_LOGIC_VECTOR", use_one_hot_select_bus => 0, width => 24, pipeline => 0, number_inputs => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset sel => delay6_output_wire, -- sel.wire result => multiplexer2_result_wire, -- result.wire ena => multiplexer2enavcc_output_wire, -- ena.wire user_aclr => multiplexer2user_aclrgnd_output_wire, -- user_aclr.wire in0 => bus_concatenation1_output_wire, -- in0.wire in1 => multiplexer1_result_wire -- in1.wire ); multiplexer2user_aclrgnd : component alt_dspbuilder_gnd_GN port map ( output => multiplexer2user_aclrgnd_output_wire -- output.wire ); multiplexer2enavcc : component alt_dspbuilder_vcc_GN port map ( output => multiplexer2enavcc_output_wire -- output.wire ); delay2 : component alt_dspbuilder_delay_GNVTJPHWYT generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "01111111", width => 8 ) port map ( input => bus_conversion1_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay2_output_wire, -- output.wire sclr => delay2sclrgnd_output_wire, -- sclr.wire ena => logical_bit_operator2_result_wire -- ena.wire ); delay2sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay2sclrgnd_output_wire -- output.wire ); data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ port map ( input => multiplexer_result_wire, -- input.wire output => data_out -- output.wire ); data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ port map ( input => data_in, -- input.wire output => data_in_0_output_wire -- output.wire ); decoder : component alt_dspbuilder_decoder_GNM4LOIHXZ generic map ( decode => "01", pipeline => 1, width => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset data => addr_0_output_wire, -- data.wire dec => decoder_dec_wire, -- dec.wire sclr => decodersclrgnd_output_wire, -- sclr.wire ena => decoderenavcc_output_wire -- ena.wire ); decodersclrgnd : component alt_dspbuilder_gnd_GN port map ( output => decodersclrgnd_output_wire -- output.wire ); decoderenavcc : component alt_dspbuilder_vcc_GN port map ( output => decoderenavcc_output_wire -- output.wire ); bus_conversion6 : component alt_dspbuilder_cast_GNZ5LMFB5D generic map ( round => 0, saturate => 0 ) port map ( input => writedata_0_output_wire, -- input.wire output => bus_conversion6_output_wire -- output.wire ); bus_conversion5 : component alt_dspbuilder_cast_GN7IAAYCSZ generic map ( round => 0, saturate => 0 ) port map ( input => data_in_0_output_wire, -- input.wire output => bus_conversion5_output_wire -- output.wire ); cast48 : component alt_dspbuilder_cast_GNSB3OXIQS generic map ( round => 0, saturate => 0 ) port map ( input => delay1_output_wire, -- input.wire output => cast48_output_wire -- output.wire ); cast49 : component alt_dspbuilder_cast_GNSB3OXIQS generic map ( round => 0, saturate => 0 ) port map ( input => delay4_output_wire, -- input.wire output => cast49_output_wire -- output.wire ); cast50 : component alt_dspbuilder_cast_GN46N4UJ5S generic map ( round => 0, saturate => 0 ) port map ( input => logical_bit_operator_result_wire, -- input.wire output => cast50_output_wire -- output.wire ); cast51 : component alt_dspbuilder_cast_GNSB3OXIQS generic map ( round => 0, saturate => 0 ) port map ( input => delay_output_wire, -- input.wire output => cast51_output_wire -- output.wire ); cast52 : component alt_dspbuilder_cast_GN46N4UJ5S generic map ( round => 0, saturate => 0 ) port map ( input => logical_bit_operator1_result_wire, -- input.wire output => cast52_output_wire -- output.wire ); cast53 : component alt_dspbuilder_cast_GN46N4UJ5S generic map ( round => 0, saturate => 0 ) port map ( input => if_statement_true_wire, -- input.wire output => cast53_output_wire -- output.wire ); end architecture rtl; -- of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module
-- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module.vhd -- Generated using ACDS version 13.1 162 at 2015.02.12.15:50:58 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is port ( sop : in std_logic := '0'; -- sop.wire Clock : in std_logic := '0'; -- Clock.clk aclr : in std_logic := '0'; -- .reset data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire data_out : out std_logic_vector(23 downto 0); -- data_out.wire writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire addr : in std_logic_vector(1 downto 0) := (others => '0'); -- addr.wire eop : in std_logic := '0'; -- eop.wire write : in std_logic := '0' -- write.wire ); end entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module; architecture rtl of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is component alt_dspbuilder_clock_GNQFU4PUDH is port ( aclr : in std_logic := 'X'; -- reset aclr_n : in std_logic := 'X'; -- reset_n aclr_out : out std_logic; -- reset clock : in std_logic := 'X'; -- clk clock_out : out std_logic -- clk ); end component alt_dspbuilder_clock_GNQFU4PUDH; component alt_dspbuilder_cast_GNLF52SJQ3 is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(7 downto 0) -- wire ); end component alt_dspbuilder_cast_GNLF52SJQ3; component alt_dspbuilder_cast_GNJGR7GQ2L is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(17 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(7 downto 0) -- wire ); end component alt_dspbuilder_cast_GNJGR7GQ2L; component alt_dspbuilder_cast_GNKXX25S2S is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(7 downto 0) -- wire ); end component alt_dspbuilder_cast_GNKXX25S2S; component alt_dspbuilder_cast_GN6OMCQQS7 is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(7 downto 0) -- wire ); end component alt_dspbuilder_cast_GN6OMCQQS7; component alt_dspbuilder_port_GNEPKLLZKY is port ( input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(31 downto 0) -- wire ); end component alt_dspbuilder_port_GNEPKLLZKY; component alt_dspbuilder_multiplexer_GNCALBUTDR is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; use_one_hot_select_bus : natural := 0; width : positive := 8; pipeline : natural := 0; number_inputs : natural := 4 ); port ( clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset sel : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire result : out std_logic_vector(23 downto 0); -- wire ena : in std_logic := 'X'; -- wire user_aclr : in std_logic := 'X'; -- wire in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire in1 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire ); end component alt_dspbuilder_multiplexer_GNCALBUTDR; component alt_dspbuilder_gnd_GN is port ( output : out std_logic -- wire ); end component alt_dspbuilder_gnd_GN; component alt_dspbuilder_vcc_GN is port ( output : out std_logic -- wire ); end component alt_dspbuilder_vcc_GN; component alt_dspbuilder_port_GN6TDLHAW6 is port ( input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(1 downto 0) -- wire ); end component alt_dspbuilder_port_GN6TDLHAW6; component alt_dspbuilder_constant_GNZEH3JAKA is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; BitPattern : string := "0000"; width : natural := 4 ); port ( output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_constant_GNZEH3JAKA; component alt_dspbuilder_constant_GNPXZ5JSVR is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; BitPattern : string := "0000"; width : natural := 4 ); port ( output : out std_logic_vector(3 downto 0) -- wire ); end component alt_dspbuilder_constant_GNPXZ5JSVR; component alt_dspbuilder_bus_concat_GN55ETJ4VI is generic ( widthB : natural := 8; widthA : natural := 8 ); port ( a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire aclr : in std_logic := 'X'; -- clk b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire clock : in std_logic := 'X'; -- clk output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire ); end component alt_dspbuilder_bus_concat_GN55ETJ4VI; component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is generic ( LogicalOp : string := "AltAND"; number_inputs : positive := 2 ); port ( result : out std_logic; -- wire data0 : in std_logic := 'X'; -- wire data1 : in std_logic := 'X' -- wire ); end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V; component alt_dspbuilder_bus_concat_GNIIOZRPJD is generic ( widthB : natural := 8; widthA : natural := 8 ); port ( a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire aclr : in std_logic := 'X'; -- clk b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire clock : in std_logic := 'X'; -- clk output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire ); end component alt_dspbuilder_bus_concat_GNIIOZRPJD; component alt_dspbuilder_constant_GNNKZSYI73 is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; BitPattern : string := "0000"; width : natural := 4 ); port ( output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_constant_GNNKZSYI73; component alt_dspbuilder_if_statement_GNYT6HZJI5 is generic ( use_else_output : natural := 0; bwr : natural := 0; use_else_input : natural := 0; signed : natural := 1; HDLTYPE : string := "STD_LOGIC_VECTOR"; if_expression : string := "a"; number_inputs : integer := 1; width : natural := 8 ); port ( true : out std_logic; -- wire a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire b : in std_logic_vector(7 downto 0) := (others => 'X') -- wire ); end component alt_dspbuilder_if_statement_GNYT6HZJI5; component alt_dspbuilder_constant_GNLMV7GZFA is generic ( HDLTYPE : string := "STD_LOGIC_VECTOR"; BitPattern : string := "0000"; width : natural := 4 ); port ( output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_constant_GNLMV7GZFA; component alt_dspbuilder_delay_GNUECIBFDH is generic ( ClockPhase : string := "1"; delay : positive := 1; use_init : natural := 0; BitPattern : string := "00000001"; width : positive := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk ena : in std_logic := 'X'; -- wire input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(width-1 downto 0); -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_delay_GNUECIBFDH; component alt_dspbuilder_port_GN37ALZBS4 is port ( input : in std_logic := 'X'; -- wire output : out std_logic -- wire ); end component alt_dspbuilder_port_GN37ALZBS4; component alt_dspbuilder_decoder_GNA3ETEQ66 is generic ( decode : string := "00000000"; pipeline : natural := 0; width : natural := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire dec : out std_logic; -- wire ena : in std_logic := 'X'; -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_decoder_GNA3ETEQ66; component alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "00000000"; pipeline : natural := 0; width : natural := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire dec : out std_logic; -- wire ena : in std_logic := 'X'; -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_decoder_GNSCEXJCJK; component alt_dspbuilder_barrelshifter_GNV5DVAGHT is generic ( DISTANCE_WIDTH : natural := 3; NDIRECTION : natural := 0; SIGNED : integer := 1; use_dedicated_circuitry : string := "false"; PIPELINE : natural := 0; WIDTH : natural := 8 ); port ( a : in std_logic_vector(WIDTH-1 downto 0) := (others => 'X'); -- wire aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk direction : in std_logic := 'X'; -- wire distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0) := (others => 'X'); -- wire ena : in std_logic := 'X'; -- wire r : out std_logic_vector(WIDTH-1 downto 0); -- wire user_aclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_barrelshifter_GNV5DVAGHT; component alt_dspbuilder_multiply_add_GNKLXFKAO3 is generic ( family : string := "Stratix"; direction : string := "AddAdd"; data3b_const : string := "00000000"; data2b_const : string := "00000000"; representation : string := "SIGNED"; dataWidth : integer := 8; data4b_const : string := "00000000"; number_multipliers : integer := 2; pipeline_register : string := "NoRegister"; use_dedicated_circuitry : integer := 0; data1b_const : string := "00000000"; use_b_consts : natural := 0 ); port ( clock : in std_logic := 'X'; -- clk aclr : in std_logic := 'X'; -- reset data1a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire data2a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire data3a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire result : out std_logic_vector(17 downto 0); -- wire user_aclr : in std_logic := 'X'; -- wire ena : in std_logic := 'X' -- wire ); end component alt_dspbuilder_multiply_add_GNKLXFKAO3; component alt_dspbuilder_delay_GND2PGZRBZ is generic ( ClockPhase : string := "1"; delay : positive := 1; use_init : natural := 0; BitPattern : string := "00000001"; width : positive := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk ena : in std_logic := 'X'; -- wire input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(width-1 downto 0); -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_delay_GND2PGZRBZ; component alt_dspbuilder_delay_GNHYCSAEGT is generic ( ClockPhase : string := "1"; delay : positive := 1; use_init : natural := 0; BitPattern : string := "00000001"; width : positive := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk ena : in std_logic := 'X'; -- wire input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(width-1 downto 0); -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_delay_GNHYCSAEGT; component alt_dspbuilder_if_statement_GN7VA7SRUP is generic ( use_else_output : natural := 0; bwr : natural := 0; use_else_input : natural := 0; signed : natural := 1; HDLTYPE : string := "STD_LOGIC_VECTOR"; if_expression : string := "a"; number_inputs : integer := 1; width : natural := 8 ); port ( true : out std_logic; -- wire a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire ); end component alt_dspbuilder_if_statement_GN7VA7SRUP; component alt_dspbuilder_delay_GNVTJPHWYT is generic ( ClockPhase : string := "1"; delay : positive := 1; use_init : natural := 0; BitPattern : string := "00000001"; width : positive := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk ena : in std_logic := 'X'; -- wire input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(width-1 downto 0); -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_delay_GNVTJPHWYT; component alt_dspbuilder_port_GNOC3SGKQJ is port ( input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(23 downto 0) -- wire ); end component alt_dspbuilder_port_GNOC3SGKQJ; component alt_dspbuilder_decoder_GNM4LOIHXZ is generic ( decode : string := "00000000"; pipeline : natural := 0; width : natural := 8 ); port ( aclr : in std_logic := 'X'; -- clk clock : in std_logic := 'X'; -- clk data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire dec : out std_logic; -- wire ena : in std_logic := 'X'; -- wire sclr : in std_logic := 'X' -- wire ); end component alt_dspbuilder_decoder_GNM4LOIHXZ; component alt_dspbuilder_cast_GNZ5LMFB5D is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(0 downto 0) -- wire ); end component alt_dspbuilder_cast_GNZ5LMFB5D; component alt_dspbuilder_cast_GN7IAAYCSZ is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire output : out std_logic_vector(7 downto 0) -- wire ); end component alt_dspbuilder_cast_GN7IAAYCSZ; component alt_dspbuilder_cast_GNSB3OXIQS is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire output : out std_logic -- wire ); end component alt_dspbuilder_cast_GNSB3OXIQS; component alt_dspbuilder_cast_GN46N4UJ5S is generic ( round : natural := 0; saturate : natural := 0 ); port ( input : in std_logic := 'X'; -- wire output : out std_logic_vector(0 downto 0) -- wire ); end component alt_dspbuilder_cast_GN46N4UJ5S; signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena signal decoder2sclrgnd_output_wire : std_logic; -- Decoder2sclrGND:output -> Decoder2:sclr signal decoder2enavcc_output_wire : std_logic; -- Decoder2enaVCC:output -> Decoder2:ena signal decoder3sclrgnd_output_wire : std_logic; -- Decoder3sclrGND:output -> Decoder3:sclr signal decoder3enavcc_output_wire : std_logic; -- Decoder3enaVCC:output -> Decoder3:ena signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena signal barrel_shifteruser_aclrgnd_output_wire : std_logic; -- Barrel_Shifteruser_aclrGND:output -> Barrel_Shifter:user_aclr signal barrel_shifterenavcc_output_wire : std_logic; -- Barrel_ShifterenaVCC:output -> Barrel_Shifter:ena signal multiply_adduser_aclrgnd_output_wire : std_logic; -- Multiply_Adduser_aclrGND:output -> Multiply_Add:user_aclr signal multiply_addenavcc_output_wire : std_logic; -- Multiply_AddenaVCC:output -> Multiply_Add:ena signal delay6sclrgnd_output_wire : std_logic; -- Delay6sclrGND:output -> Delay6:sclr signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr signal delay4enavcc_output_wire : std_logic; -- Delay4enaVCC:output -> Delay4:ena signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena signal multiplexer2user_aclrgnd_output_wire : std_logic; -- Multiplexer2user_aclrGND:output -> Multiplexer2:user_aclr signal multiplexer2enavcc_output_wire : std_logic; -- Multiplexer2enaVCC:output -> Multiplexer2:ena signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena signal bus_concatenation_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation:output -> Bus_Concatenation1:b signal bus_concatenation1_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation1:output -> [Bus_Conversion:input, Multiplexer2:in0] signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> [Bus_Conversion1:input, Bus_Conversion6:input] signal barrel_shifter_r_wire : std_logic_vector(17 downto 0); -- Barrel_Shifter:r -> Bus_Conversion2:input signal bus_conversion2_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion2:output -> [Bus_Concatenation1:a, Bus_Concatenation:a, Bus_Concatenation:b] signal constant5_output_wire : std_logic_vector(3 downto 0); -- Constant5:output -> Barrel_Shifter:distance signal addr_0_output_wire : std_logic_vector(1 downto 0); -- addr_0:output -> [Decoder2:data, Decoder:data] signal bus_conversion1_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion1:output -> Delay2:input signal delay2_output_wire : std_logic_vector(7 downto 0); -- Delay2:output -> Delay3:input signal delay4_output_wire : std_logic_vector(0 downto 0); -- Delay4:output -> [Delay:input, cast49:input] signal bus_conversion6_output_wire : std_logic_vector(0 downto 0); -- Bus_Conversion6:output -> Delay5:input signal delay5_output_wire : std_logic_vector(0 downto 0); -- Delay5:output -> Delay6:input signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Bus_Conversion3:input, Bus_Conversion4:input, Bus_Conversion5:input, Decoder1:data, Decoder3:data, If_Statement1:a, Multiplexer:in0] signal bus_conversion_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion:output -> If_Statement:a signal delay3_output_wire : std_logic_vector(7 downto 0); -- Delay3:output -> If_Statement:b signal constant3_output_wire : std_logic_vector(23 downto 0); -- Constant3:output -> If_Statement1:b signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> If_Statement1:c signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Logical_Bit_Operator:data0 signal sop_0_output_wire : std_logic; -- sop_0:output -> [Logical_Bit_Operator3:data0, Logical_Bit_Operator5:data0, Logical_Bit_Operator:data1] signal eop_0_output_wire : std_logic; -- eop_0:output -> Logical_Bit_Operator1:data0 signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator2:data0 signal write_0_output_wire : std_logic; -- write_0:output -> [Logical_Bit_Operator2:data1, Logical_Bit_Operator4:data1] signal logical_bit_operator2_result_wire : std_logic; -- Logical_Bit_Operator2:result -> Delay2:ena signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator3:data1 signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Delay3:ena signal decoder2_dec_wire : std_logic; -- Decoder2:dec -> Logical_Bit_Operator4:data0 signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Delay5:ena signal decoder3_dec_wire : std_logic; -- Decoder3:dec -> Logical_Bit_Operator5:data1 signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> Delay6:ena signal delay_output_wire : std_logic_vector(0 downto 0); -- Delay:output -> [Multiplexer:sel, cast51:input] signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Multiplexer1:in0 signal constant2_output_wire : std_logic_vector(23 downto 0); -- Constant2:output -> Multiplexer1:in1 signal delay6_output_wire : std_logic_vector(0 downto 0); -- Delay6:output -> Multiplexer2:sel signal multiplexer1_result_wire : std_logic_vector(23 downto 0); -- Multiplexer1:result -> Multiplexer2:in1 signal multiplexer2_result_wire : std_logic_vector(23 downto 0); -- Multiplexer2:result -> Multiplexer:in1 signal bus_conversion5_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion5:output -> Multiply_Add:data1a signal bus_conversion4_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion4:output -> Multiply_Add:data2a signal bus_conversion3_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion3:output -> Multiply_Add:data3a signal multiply_add_result_wire : std_logic_vector(17 downto 0); -- Multiply_Add:result -> Barrel_Shifter:a signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> data_out_0:input signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> cast48:input signal cast48_output_wire : std_logic; -- cast48:output -> Delay:sclr signal cast49_output_wire : std_logic; -- cast49:output -> Delay:ena signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> cast50:input signal cast50_output_wire : std_logic_vector(0 downto 0); -- cast50:output -> Delay4:input signal cast51_output_wire : std_logic; -- cast51:output -> Logical_Bit_Operator1:data1 signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> cast52:input signal cast52_output_wire : std_logic_vector(0 downto 0); -- cast52:output -> Delay1:input signal if_statement_true_wire : std_logic; -- If_Statement:true -> cast53:input signal cast53_output_wire : std_logic_vector(0 downto 0); -- cast53:output -> Multiplexer1:sel signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Barrel_Shifter:aclr, Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Decoder1:aclr, Decoder2:aclr, Decoder3:aclr, Decoder:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay4:aclr, Delay5:aclr, Delay6:aclr, Delay:aclr, Multiplexer1:aclr, Multiplexer2:aclr, Multiplexer:aclr, Multiply_Add:aclr] signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Barrel_Shifter:clock, Bus_Concatenation1:clock, Bus_Concatenation:clock, Decoder1:clock, Decoder2:clock, Decoder3:clock, Decoder:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay4:clock, Delay5:clock, Delay6:clock, Delay:clock, Multiplexer1:clock, Multiplexer2:clock, Multiplexer:clock, Multiply_Add:clock] begin clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH port map ( clock_out => clock_0_clock_output_clk, -- clock_output.clk aclr_out => clock_0_clock_output_reset, -- .reset clock => Clock, -- clock.clk aclr => aclr -- .reset ); bus_conversion1 : component alt_dspbuilder_cast_GNLF52SJQ3 generic map ( round => 0, saturate => 0 ) port map ( input => writedata_0_output_wire, -- input.wire output => bus_conversion1_output_wire -- output.wire ); bus_conversion2 : component alt_dspbuilder_cast_GNJGR7GQ2L generic map ( round => 0, saturate => 0 ) port map ( input => barrel_shifter_r_wire, -- input.wire output => bus_conversion2_output_wire -- output.wire ); bus_conversion3 : component alt_dspbuilder_cast_GNKXX25S2S generic map ( round => 0, saturate => 0 ) port map ( input => data_in_0_output_wire, -- input.wire output => bus_conversion3_output_wire -- output.wire ); bus_conversion4 : component alt_dspbuilder_cast_GN6OMCQQS7 generic map ( round => 0, saturate => 0 ) port map ( input => data_in_0_output_wire, -- input.wire output => bus_conversion4_output_wire -- output.wire ); writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY port map ( input => writedata, -- input.wire output => writedata_0_output_wire -- output.wire ); multiplexer : component alt_dspbuilder_multiplexer_GNCALBUTDR generic map ( HDLTYPE => "STD_LOGIC_VECTOR", use_one_hot_select_bus => 0, width => 24, pipeline => 0, number_inputs => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset sel => delay_output_wire, -- sel.wire result => multiplexer_result_wire, -- result.wire ena => multiplexerenavcc_output_wire, -- ena.wire user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire in0 => data_in_0_output_wire, -- in0.wire in1 => multiplexer2_result_wire -- in1.wire ); multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN port map ( output => multiplexeruser_aclrgnd_output_wire -- output.wire ); multiplexerenavcc : component alt_dspbuilder_vcc_GN port map ( output => multiplexerenavcc_output_wire -- output.wire ); bus_conversion : component alt_dspbuilder_cast_GNKXX25S2S generic map ( round => 0, saturate => 0 ) port map ( input => bus_concatenation1_output_wire, -- input.wire output => bus_conversion_output_wire -- output.wire ); addr_0 : component alt_dspbuilder_port_GN6TDLHAW6 port map ( input => addr, -- input.wire output => addr_0_output_wire -- output.wire ); constant4 : component alt_dspbuilder_constant_GNZEH3JAKA generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "000000000000000000001111", width => 24 ) port map ( output => constant4_output_wire -- output.wire ); constant5 : component alt_dspbuilder_constant_GNPXZ5JSVR generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "1000", width => 4 ) port map ( output => constant5_output_wire -- output.wire ); bus_concatenation1 : component alt_dspbuilder_bus_concat_GN55ETJ4VI generic map ( widthB => 16, widthA => 8 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset a => bus_conversion2_output_wire, -- a.wire b => bus_concatenation_output_wire, -- b.wire output => bus_concatenation1_output_wire -- output.wire ); logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator5_result_wire, -- result.wire data0 => sop_0_output_wire, -- data0.wire data1 => decoder3_dec_wire -- data1.wire ); logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator4_result_wire, -- result.wire data0 => decoder2_dec_wire, -- data0.wire data1 => write_0_output_wire -- data1.wire ); bus_concatenation : component alt_dspbuilder_bus_concat_GNIIOZRPJD generic map ( widthB => 8, widthA => 8 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset a => bus_conversion2_output_wire, -- a.wire b => bus_conversion2_output_wire, -- b.wire output => bus_concatenation_output_wire -- output.wire ); constant3 : component alt_dspbuilder_constant_GNNKZSYI73 generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "000000000000000000000000", width => 24 ) port map ( output => constant3_output_wire -- output.wire ); if_statement : component alt_dspbuilder_if_statement_GNYT6HZJI5 generic map ( use_else_output => 0, bwr => 0, use_else_input => 0, signed => 0, HDLTYPE => "STD_LOGIC_VECTOR", if_expression => "a>b", number_inputs => 2, width => 8 ) port map ( true => if_statement_true_wire, -- true.wire a => bus_conversion_output_wire, -- a.wire b => delay3_output_wire -- b.wire ); constant2 : component alt_dspbuilder_constant_GNLMV7GZFA generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "111111111111111111111111", width => 24 ) port map ( output => constant2_output_wire -- output.wire ); delay : component alt_dspbuilder_delay_GNUECIBFDH generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "0", width => 1 ) port map ( input => delay4_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay_output_wire, -- output.wire sclr => cast48_output_wire, -- sclr.wire ena => cast49_output_wire -- ena.wire ); constant1 : component alt_dspbuilder_constant_GNNKZSYI73 generic map ( HDLTYPE => "STD_LOGIC_VECTOR", BitPattern => "000000000000000000000000", width => 24 ) port map ( output => constant1_output_wire -- output.wire ); write_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => write, -- input.wire output => write_0_output_wire -- output.wire ); logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator3_result_wire, -- result.wire data0 => sop_0_output_wire, -- data0.wire data1 => decoder1_dec_wire -- data1.wire ); logical_bit_operator2 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator2_result_wire, -- result.wire data0 => decoder_dec_wire, -- data0.wire data1 => write_0_output_wire -- data1.wire ); eop_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => eop, -- input.wire output => eop_0_output_wire -- output.wire ); logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator1_result_wire, -- result.wire data0 => eop_0_output_wire, -- data0.wire data1 => cast51_output_wire -- data1.wire ); decoder2 : component alt_dspbuilder_decoder_GNA3ETEQ66 generic map ( decode => "00", pipeline => 1, width => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset data => addr_0_output_wire, -- data.wire dec => decoder2_dec_wire, -- dec.wire sclr => decoder2sclrgnd_output_wire, -- sclr.wire ena => decoder2enavcc_output_wire -- ena.wire ); decoder2sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => decoder2sclrgnd_output_wire -- output.wire ); decoder2enavcc : component alt_dspbuilder_vcc_GN port map ( output => decoder2enavcc_output_wire -- output.wire ); decoder3 : component alt_dspbuilder_decoder_GNSCEXJCJK generic map ( decode => "000000000000000000001111", pipeline => 0, width => 24 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset data => data_in_0_output_wire, -- data.wire dec => decoder3_dec_wire, -- dec.wire sclr => decoder3sclrgnd_output_wire, -- sclr.wire ena => decoder3enavcc_output_wire -- ena.wire ); decoder3sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => decoder3sclrgnd_output_wire -- output.wire ); decoder3enavcc : component alt_dspbuilder_vcc_GN port map ( output => decoder3enavcc_output_wire -- output.wire ); decoder1 : component alt_dspbuilder_decoder_GNSCEXJCJK generic map ( decode => "000000000000000000001111", pipeline => 0, width => 24 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset data => data_in_0_output_wire, -- data.wire dec => decoder1_dec_wire, -- dec.wire sclr => decoder1sclrgnd_output_wire, -- sclr.wire ena => decoder1enavcc_output_wire -- ena.wire ); decoder1sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => decoder1sclrgnd_output_wire -- output.wire ); decoder1enavcc : component alt_dspbuilder_vcc_GN port map ( output => decoder1enavcc_output_wire -- output.wire ); logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V generic map ( LogicalOp => "AltAND", number_inputs => 2 ) port map ( result => logical_bit_operator_result_wire, -- result.wire data0 => if_statement1_true_wire, -- data0.wire data1 => sop_0_output_wire -- data1.wire ); barrel_shifter : component alt_dspbuilder_barrelshifter_GNV5DVAGHT generic map ( DISTANCE_WIDTH => 4, NDIRECTION => 1, SIGNED => 0, use_dedicated_circuitry => "false", PIPELINE => 0, WIDTH => 18 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset a => multiply_add_result_wire, -- a.wire r => barrel_shifter_r_wire, -- r.wire distance => constant5_output_wire, -- distance.wire ena => barrel_shifterenavcc_output_wire, -- ena.wire user_aclr => barrel_shifteruser_aclrgnd_output_wire -- user_aclr.wire ); barrel_shifteruser_aclrgnd : component alt_dspbuilder_gnd_GN port map ( output => barrel_shifteruser_aclrgnd_output_wire -- output.wire ); barrel_shifterenavcc : component alt_dspbuilder_vcc_GN port map ( output => barrel_shifterenavcc_output_wire -- output.wire ); multiply_add : component alt_dspbuilder_multiply_add_GNKLXFKAO3 generic map ( family => "Cyclone V", direction => "AddAdd", data3b_const => "00011110", data2b_const => "10010110", representation => "UNSIGNED", dataWidth => 8, data4b_const => "01001100", number_multipliers => 3, pipeline_register => "NoRegister", use_dedicated_circuitry => 1, data1b_const => "01001100", use_b_consts => 1 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset data1a => bus_conversion5_output_wire, -- data1a.wire data2a => bus_conversion4_output_wire, -- data2a.wire data3a => bus_conversion3_output_wire, -- data3a.wire result => multiply_add_result_wire, -- result.wire user_aclr => multiply_adduser_aclrgnd_output_wire, -- user_aclr.wire ena => multiply_addenavcc_output_wire -- ena.wire ); multiply_adduser_aclrgnd : component alt_dspbuilder_gnd_GN port map ( output => multiply_adduser_aclrgnd_output_wire -- output.wire ); multiply_addenavcc : component alt_dspbuilder_vcc_GN port map ( output => multiply_addenavcc_output_wire -- output.wire ); delay6 : component alt_dspbuilder_delay_GND2PGZRBZ generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "1", width => 1 ) port map ( input => delay5_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay6_output_wire, -- output.wire sclr => delay6sclrgnd_output_wire, -- sclr.wire ena => logical_bit_operator5_result_wire -- ena.wire ); delay6sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay6sclrgnd_output_wire -- output.wire ); delay5 : component alt_dspbuilder_delay_GND2PGZRBZ generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "1", width => 1 ) port map ( input => bus_conversion6_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay5_output_wire, -- output.wire sclr => delay5sclrgnd_output_wire, -- sclr.wire ena => logical_bit_operator4_result_wire -- ena.wire ); delay5sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay5sclrgnd_output_wire -- output.wire ); delay4 : component alt_dspbuilder_delay_GNHYCSAEGT generic map ( ClockPhase => "1", delay => 1, use_init => 0, BitPattern => "0", width => 1 ) port map ( input => cast50_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay4_output_wire, -- output.wire sclr => delay4sclrgnd_output_wire, -- sclr.wire ena => delay4enavcc_output_wire -- ena.wire ); delay4sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay4sclrgnd_output_wire -- output.wire ); delay4enavcc : component alt_dspbuilder_vcc_GN port map ( output => delay4enavcc_output_wire -- output.wire ); if_statement1 : component alt_dspbuilder_if_statement_GN7VA7SRUP generic map ( use_else_output => 0, bwr => 0, use_else_input => 0, signed => 0, HDLTYPE => "STD_LOGIC_VECTOR", if_expression => "(a=b) and (a /= c)", number_inputs => 3, width => 24 ) port map ( true => if_statement1_true_wire, -- true.wire a => data_in_0_output_wire, -- a.wire b => constant3_output_wire, -- b.wire c => constant4_output_wire -- c.wire ); delay3 : component alt_dspbuilder_delay_GNVTJPHWYT generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "01111111", width => 8 ) port map ( input => delay2_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay3_output_wire, -- output.wire sclr => delay3sclrgnd_output_wire, -- sclr.wire ena => logical_bit_operator3_result_wire -- ena.wire ); delay3sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay3sclrgnd_output_wire -- output.wire ); sop_0 : component alt_dspbuilder_port_GN37ALZBS4 port map ( input => sop, -- input.wire output => sop_0_output_wire -- output.wire ); multiplexer1 : component alt_dspbuilder_multiplexer_GNCALBUTDR generic map ( HDLTYPE => "STD_LOGIC_VECTOR", use_one_hot_select_bus => 0, width => 24, pipeline => 0, number_inputs => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset sel => cast53_output_wire, -- sel.wire result => multiplexer1_result_wire, -- result.wire ena => multiplexer1enavcc_output_wire, -- ena.wire user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire in0 => constant1_output_wire, -- in0.wire in1 => constant2_output_wire -- in1.wire ); multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN port map ( output => multiplexer1user_aclrgnd_output_wire -- output.wire ); multiplexer1enavcc : component alt_dspbuilder_vcc_GN port map ( output => multiplexer1enavcc_output_wire -- output.wire ); delay1 : component alt_dspbuilder_delay_GNHYCSAEGT generic map ( ClockPhase => "1", delay => 1, use_init => 0, BitPattern => "0", width => 1 ) port map ( input => cast52_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay1_output_wire, -- output.wire sclr => delay1sclrgnd_output_wire, -- sclr.wire ena => delay1enavcc_output_wire -- ena.wire ); delay1sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay1sclrgnd_output_wire -- output.wire ); delay1enavcc : component alt_dspbuilder_vcc_GN port map ( output => delay1enavcc_output_wire -- output.wire ); multiplexer2 : component alt_dspbuilder_multiplexer_GNCALBUTDR generic map ( HDLTYPE => "STD_LOGIC_VECTOR", use_one_hot_select_bus => 0, width => 24, pipeline => 0, number_inputs => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset sel => delay6_output_wire, -- sel.wire result => multiplexer2_result_wire, -- result.wire ena => multiplexer2enavcc_output_wire, -- ena.wire user_aclr => multiplexer2user_aclrgnd_output_wire, -- user_aclr.wire in0 => bus_concatenation1_output_wire, -- in0.wire in1 => multiplexer1_result_wire -- in1.wire ); multiplexer2user_aclrgnd : component alt_dspbuilder_gnd_GN port map ( output => multiplexer2user_aclrgnd_output_wire -- output.wire ); multiplexer2enavcc : component alt_dspbuilder_vcc_GN port map ( output => multiplexer2enavcc_output_wire -- output.wire ); delay2 : component alt_dspbuilder_delay_GNVTJPHWYT generic map ( ClockPhase => "1", delay => 1, use_init => 1, BitPattern => "01111111", width => 8 ) port map ( input => bus_conversion1_output_wire, -- input.wire clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset output => delay2_output_wire, -- output.wire sclr => delay2sclrgnd_output_wire, -- sclr.wire ena => logical_bit_operator2_result_wire -- ena.wire ); delay2sclrgnd : component alt_dspbuilder_gnd_GN port map ( output => delay2sclrgnd_output_wire -- output.wire ); data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ port map ( input => multiplexer_result_wire, -- input.wire output => data_out -- output.wire ); data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ port map ( input => data_in, -- input.wire output => data_in_0_output_wire -- output.wire ); decoder : component alt_dspbuilder_decoder_GNM4LOIHXZ generic map ( decode => "01", pipeline => 1, width => 2 ) port map ( clock => clock_0_clock_output_clk, -- clock_aclr.clk aclr => clock_0_clock_output_reset, -- .reset data => addr_0_output_wire, -- data.wire dec => decoder_dec_wire, -- dec.wire sclr => decodersclrgnd_output_wire, -- sclr.wire ena => decoderenavcc_output_wire -- ena.wire ); decodersclrgnd : component alt_dspbuilder_gnd_GN port map ( output => decodersclrgnd_output_wire -- output.wire ); decoderenavcc : component alt_dspbuilder_vcc_GN port map ( output => decoderenavcc_output_wire -- output.wire ); bus_conversion6 : component alt_dspbuilder_cast_GNZ5LMFB5D generic map ( round => 0, saturate => 0 ) port map ( input => writedata_0_output_wire, -- input.wire output => bus_conversion6_output_wire -- output.wire ); bus_conversion5 : component alt_dspbuilder_cast_GN7IAAYCSZ generic map ( round => 0, saturate => 0 ) port map ( input => data_in_0_output_wire, -- input.wire output => bus_conversion5_output_wire -- output.wire ); cast48 : component alt_dspbuilder_cast_GNSB3OXIQS generic map ( round => 0, saturate => 0 ) port map ( input => delay1_output_wire, -- input.wire output => cast48_output_wire -- output.wire ); cast49 : component alt_dspbuilder_cast_GNSB3OXIQS generic map ( round => 0, saturate => 0 ) port map ( input => delay4_output_wire, -- input.wire output => cast49_output_wire -- output.wire ); cast50 : component alt_dspbuilder_cast_GN46N4UJ5S generic map ( round => 0, saturate => 0 ) port map ( input => logical_bit_operator_result_wire, -- input.wire output => cast50_output_wire -- output.wire ); cast51 : component alt_dspbuilder_cast_GNSB3OXIQS generic map ( round => 0, saturate => 0 ) port map ( input => delay_output_wire, -- input.wire output => cast51_output_wire -- output.wire ); cast52 : component alt_dspbuilder_cast_GN46N4UJ5S generic map ( round => 0, saturate => 0 ) port map ( input => logical_bit_operator1_result_wire, -- input.wire output => cast52_output_wire -- output.wire ); cast53 : component alt_dspbuilder_cast_GN46N4UJ5S generic map ( round => 0, saturate => 0 ) port map ( input => if_statement_true_wire, -- input.wire output => cast53_output_wire -- output.wire ); end architecture rtl; -- of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 25.01.2016 17:22:42 -- Design Name: -- Module Name: serialLoader - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity serialLoader is Port ( --serial control data S_Send : out STD_LOGIC:='0'; S_DataOut : out std_logic_vector (7 downto 0); S_Ready : in STD_LOGIC; --FIFO DATA FIFO_Empty : in STD_LOGIC; -- flag if no data is left FIFO_Data : in STD_LOGIC_VECTOR (7 downto 0); -- actual data FIFO_ReadEn : out STD_LOGIC := '0'; -- enable read -- global clock clk : in STD_LOGIC; reset: in STD_LOGIC ); end serialLoader; architecture Behavioral of serialLoader is type state_type is ( STATE_WAIT, STATE_STARTREAD, STATE_ENDREAD, STATE_STARTWRITE, STATE_ENDWRITE, STATE_CLOCKIN); signal state_reg: state_type := STATE_WAIT; begin process (clk, FIFO_Empty, S_Ready, reset) -- process to handle the next state begin if (reset = '1') then --reset state: FIFO_ReadEn <= '0'; S_Send <= '0'; state_reg <= STATE_WAIT; else if rising_edge (clk) then case state_reg is when STATE_WAIT => if (FIFO_Empty = '1' or S_Ready = '0') then state_reg <= STATE_WAIT; else state_reg <= STATE_STARTREAD; end if; when STATE_STARTREAD => -- request the data FIFO_ReadEn <= '1'; state_reg <= STATE_ENDREAD; when STATE_ENDREAD => FIFO_ReadEn <= '0'; state_reg <= STATE_CLOCKIN; when STATE_CLOCKIN => --clock the data out S_DataOut <= FIFO_Data; state_reg <= STATE_STARTWRITE; when STATE_STARTWRITE => -- tell the serial module to pickup the data S_Send <= '1'; state_reg <= STATE_ENDWRITE; when STATE_ENDWRITE => -- close all the modules down S_Send <= '0'; --if (FIFO_Empty = '0' and S_Ready = '1') then -- state_reg <= STATE_STARTREAD; --else state_reg <= STATE_WAIT; --end if; when others => state_reg <= STATE_WAIT; end case; end if; end if; end process; end Behavioral;
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00335 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.3 (1) -- 7.2.3 (2) -- 7.2.3 (8) -- 7.2.3 (9) -- 7.2.3 (10) -- -- DESIGN UNIT ORDERING: -- -- ENT00335(ARCH00335) -- ENT00335_Test_Bench(ARCH00335_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.ARITHMETIC.all ; entity ENT00335 is generic ( i_real_1 : real := c_real_1 ; i_real_2 : real := c_real_2 ; i_t_real_1 : t_real := c_t_real_1 ; i_t_real_2 : t_real := c_t_real_2 ; i_st_real_1 : st_real := c_st_real_1 ; i_st_real_2 : st_real := c_st_real_2 ) ; port ( locally_static_correct : out boolean ; globally_static_correct : out boolean ; dynamic_correct : out boolean ) ; end ENT00335 ; architecture ARCH00335 of ENT00335 is begin process variable bool : boolean := true ; variable cons_correct, gen_correct, dyn_correct : boolean := true ; -- variable v_real_1, v2_real_1 : real := c_real_1 ; variable v_real_2, v2_real_2 : real := c_real_2 ; variable v_t_real_1, v2_t_real_1 : t_real := c_t_real_1 ; variable v_t_real_2, v2_t_real_2 : t_real := c_t_real_2 ; variable v_st_real_1, v2_st_real_1 : st_real := c_st_real_1 ; variable v_st_real_2, v2_st_real_2 : st_real := c_st_real_2 ; -- constant c2_real_1 : real := (((+i_real_1) + (-i_real_2)) + ((-i_real_1) + (-i_real_2))) - (((+i_real_1) - (-c_real_2)) - ((-c_real_2) - (-i_real_1))) - 29.2 ; constant c2_t_real_1 : t_real := (((+i_t_real_1) + (-i_t_real_2)) + ((-i_t_real_1) + (-i_t_real_2))) - (((+i_t_real_1) - (-c_t_real_2)) - ((-c_t_real_2) - (-i_t_real_1))) - 5.0 ; constant c2_st_real_1 : st_real := -(((+i_st_real_1) + (-i_t_real_2)) + ((-i_st_real_1) + (-i_st_real_2))) - (((+i_st_real_1) - (-c_st_real_2)) - ((-c_t_real_2) - (-i_st_real_1))) - 6.8 ; begin -- static expression case bool is when ( abs ( (((+c_real_1) + (-c_real_2)) + ((-c_real_1) + (-c_real_2))) - (((+c_real_1) - (-c_real_2)) - ((-c_real_2) - (-c_real_1))) - 29.2 - ans_real1) < acceptable_error and abs ( (((+c_t_real_1) + (-c_t_real_2)) + ((-c_t_real_1) + (-c_t_real_2))) - (((+c_t_real_1) - (-c_t_real_2)) - ((-c_t_real_2) - (-c_t_real_1))) - 5.0 - ans_real2) < t_acceptable_error and abs ( -(((+c_st_real_1) + (-c_t_real_2)) + ((-c_st_real_1) + (-c_st_real_2))) - (((+c_st_real_1) - (-c_st_real_2)) - ((-c_t_real_2) - (-c_st_real_1))) - 6.8 - ans_real3) < t_acceptable_error ) => null ; when others => cons_correct := false ; end case ; -- generic expression gen_correct := abs(c2_real_1 - ans_real1) < acceptable_error and abs(c2_t_real_1 - ans_real2) < t_acceptable_error and abs(c2_st_real_1 - ans_real3) < t_acceptable_error ; -- dynamic expression v_real_1 := (((+v2_real_1) + (-v2_real_2)) + ((-v2_real_1) + (-v2_real_2))) - (((+v2_real_1) - (-c_real_2)) - ((-c_real_2) - (-v2_real_1))) - 29.2 ; v_t_real_1 := (((+v2_t_real_1) + (-v2_t_real_2)) + ((-v2_t_real_1) + (-v2_t_real_2))) - (((+v2_t_real_1) - (-i_t_real_2)) - ((-c_t_real_2) - (-v2_t_real_1))) - 5.0 ; v_st_real_1 := -(((+v2_st_real_1) + (-v2_t_real_2)) + ((-v2_st_real_1) + (-v2_st_real_2))) - (((+v2_st_real_1) - (-c_st_real_2)) - ((-i_t_real_2) - (-v2_st_real_1))) - 6.8 ; dyn_correct := abs(v_real_1 - ans_real1) < acceptable_error and abs(v_t_real_1 - ans_real2) < t_acceptable_error and abs(v_st_real_1 - ans_real3) < t_acceptable_error ; locally_static_correct <= cons_correct ; globally_static_correct <= gen_correct ; dynamic_correct <= dyn_correct ; wait ; end process ; end ARCH00335 ; use WORK.STANDARD_TYPES.all ; entity ENT00335_Test_Bench is end ENT00335_Test_Bench ; architecture ARCH00335_Test_Bench of ENT00335_Test_Bench is begin L1: block signal locally_static_correct, globally_static_correct, dynamic_correct : boolean := false ; component UUT port ( locally_static_correct : out boolean ; globally_static_correct : out boolean ; dynamic_correct : out boolean ) ; end component ; for CIS1 : UUT use entity WORK.ENT00335 ( ARCH00335 ) ; begin CIS1 : UUT port map ( locally_static_correct, globally_static_correct, dynamic_correct ) ; process ( locally_static_correct, globally_static_correct, dynamic_correct ) begin if locally_static_correct and globally_static_correct and dynamic_correct then test_report ( "ARCH00335" , "+ and - unary and binary operators are correctly" & " predefined for real types" , true ) ; end if ; end process ; end block L1 ; end ARCH00335_Test_Bench ;
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 -- IP Revision: 7 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY proc_sys_reset_v5_0; USE proc_sys_reset_v5_0.proc_sys_reset; ENTITY design_gpio_led_rst_processing_system7_0_100M_1 IS PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END design_gpio_led_rst_processing_system7_0_100M_1; ARCHITECTURE design_gpio_led_rst_processing_system7_0_100M_1_arch OF design_gpio_led_rst_processing_system7_0_100M_1 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_gpio_led_rst_processing_system7_0_100M_1_arch: ARCHITECTURE IS "yes"; COMPONENT proc_sys_reset IS GENERIC ( C_FAMILY : STRING; C_EXT_RST_WIDTH : INTEGER; C_AUX_RST_WIDTH : INTEGER; C_EXT_RESET_HIGH : STD_LOGIC; C_AUX_RESET_HIGH : STD_LOGIC; C_NUM_BUS_RST : INTEGER; C_NUM_PERP_RST : INTEGER; C_NUM_INTERCONNECT_ARESETN : INTEGER; C_NUM_PERP_ARESETN : INTEGER ); PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT proc_sys_reset; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF design_gpio_led_rst_processing_system7_0_100M_1_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.2.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF design_gpio_led_rst_processing_system7_0_100M_1_arch : ARCHITECTURE IS "design_gpio_led_rst_processing_system7_0_100M_1,proc_sys_reset,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF design_gpio_led_rst_processing_system7_0_100M_1_arch: ARCHITECTURE IS "design_gpio_led_rst_processing_system7_0_100M_1,proc_sys_reset,{x_ipProduct=Vivado 2015.2.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; BEGIN U0 : proc_sys_reset GENERIC MAP ( C_FAMILY => "zynq", C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '0', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) PORT MAP ( slowest_sync_clk => slowest_sync_clk, ext_reset_in => ext_reset_in, aux_reset_in => aux_reset_in, mb_debug_sys_rst => mb_debug_sys_rst, dcm_locked => dcm_locked, mb_reset => mb_reset, bus_struct_reset => bus_struct_reset, peripheral_reset => peripheral_reset, interconnect_aresetn => interconnect_aresetn, peripheral_aresetn => peripheral_aresetn ); END design_gpio_led_rst_processing_system7_0_100M_1_arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2166.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b04x00p22n01i02166ent IS END c07s02b04x00p22n01i02166ent; ARCHITECTURE c07s02b04x00p22n01i02166arch OF c07s02b04x00p22n01i02166ent IS TYPE real_v is array (integer range <>) of real; SUBTYPE real_2 is real_v (1 to 2); BEGIN TESTING: PROCESS variable result : real_2; variable l_operand : real := 12.345; variable r_operand : real := -67.890; BEGIN -- -- The element is treated as an implicit single element array ! -- result := l_operand & r_operand; wait for 5 ns; assert NOT((result = ( 12.345, -67.890 )) and (result(1) = 12.345)) report "***PASSED TEST: c07s02b04x00p22n01i02166" severity NOTE; assert ((result = ( 12.345, -67.890 )) and (result(1) = 12.345)) report "***FAILED TEST: c07s02b04x00p22n01i02166 - Concatenation of element and element failed." severity ERROR; wait; END PROCESS TESTING; END c07s02b04x00p22n01i02166arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2166.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b04x00p22n01i02166ent IS END c07s02b04x00p22n01i02166ent; ARCHITECTURE c07s02b04x00p22n01i02166arch OF c07s02b04x00p22n01i02166ent IS TYPE real_v is array (integer range <>) of real; SUBTYPE real_2 is real_v (1 to 2); BEGIN TESTING: PROCESS variable result : real_2; variable l_operand : real := 12.345; variable r_operand : real := -67.890; BEGIN -- -- The element is treated as an implicit single element array ! -- result := l_operand & r_operand; wait for 5 ns; assert NOT((result = ( 12.345, -67.890 )) and (result(1) = 12.345)) report "***PASSED TEST: c07s02b04x00p22n01i02166" severity NOTE; assert ((result = ( 12.345, -67.890 )) and (result(1) = 12.345)) report "***FAILED TEST: c07s02b04x00p22n01i02166 - Concatenation of element and element failed." severity ERROR; wait; END PROCESS TESTING; END c07s02b04x00p22n01i02166arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2166.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b04x00p22n01i02166ent IS END c07s02b04x00p22n01i02166ent; ARCHITECTURE c07s02b04x00p22n01i02166arch OF c07s02b04x00p22n01i02166ent IS TYPE real_v is array (integer range <>) of real; SUBTYPE real_2 is real_v (1 to 2); BEGIN TESTING: PROCESS variable result : real_2; variable l_operand : real := 12.345; variable r_operand : real := -67.890; BEGIN -- -- The element is treated as an implicit single element array ! -- result := l_operand & r_operand; wait for 5 ns; assert NOT((result = ( 12.345, -67.890 )) and (result(1) = 12.345)) report "***PASSED TEST: c07s02b04x00p22n01i02166" severity NOTE; assert ((result = ( 12.345, -67.890 )) and (result(1) = 12.345)) report "***FAILED TEST: c07s02b04x00p22n01i02166 - Concatenation of element and element failed." severity ERROR; wait; END PROCESS TESTING; END c07s02b04x00p22n01i02166arch;
--pragma translate off --vhdl_comp_off /* --vhdl_comp_on library aldec; use aldec.matlab.all; --vhdl_comp_off */ --vhdl_comp_on --pragma translate on library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use std.textio.all; library work; use work.fixed_float_types.all; use work.fixed_generic_pkg.all; use work.common_pkg.all; use work.common_data_types_pkg.all; use work.permutation_pkg.all; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ entity permutation_core is generic ( INPUT_INDEXES : integer_v; OUTPUT_INDEXES : integer_v; INPUT_HIGH : natural; INPUT_LOW : natural ); port( Clk : in std_ulogic; input : in sulv_v; start : in std_ulogic; output : out sulv_v(INPUT_HIGH downto INPUT_LOW); finish : out std_ulogic ); end entity; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ architecture permutation_core_1 of permutation_core is constant INPUT_LENGTH : positive := input'length; constant CHECKS : boolean := permutation_checks(INPUT_LENGTH, INPUT_INDEXES, OUTPUT_INDEXES); constant DIMENSIONS : positive := OUTPUT_INDEXES'length; constant PARALLEL_DIMENSIONS : natural := integer(log2(real(INPUT_LENGTH))); /* file constants */ /***********************************************************************************************/ constant FILE_PATH_M : string := DATA_FILE_DIRECTORY_M & "\\" & generate_perm_file_name(PARALLEL_DIMENSIONS, INPUT_INDEXES, OUTPUT_INDEXES); --for Matlab constant FILE_PATH : string := DATA_FILE_DIRECTORY & "\"/*"*/ & generate_perm_file_name(PARALLEL_DIMENSIONS, INPUT_INDEXES, OUTPUT_INDEXES); file solution_input : text; --pragma translate off --vhdl_comp_off /* --vhdl_comp_on ---------------------------------------------------------------------------------------------------- function execute_Matlab_script return integer is variable in_indexes_id : integer := 0; variable out_indexes_id : integer := 0; variable size_i : TDims(1 to 1) := (1 => DIMENSIONS); begin ml_setup(desktop => false); --send data to Matlab: path name, number of parallel dimensions, input and output indexes put_variable("file_path", FILE_PATH_M); put_variable("p", PARALLEL_DIMENSIONS); out_indexes_id := create_array("Po", 1, size_i); for i in 1 to DIMENSIONS loop put_item (OUTPUT_INDEXES(i-1), out_indexes_id, (1 => i)); end loop; hdl2ml(out_indexes_id); in_indexes_id := create_array("Pi", 1, size_i); for i in 1 to DIMENSIONS loop put_item (INPUT_INDEXES(i-1), in_indexes_id, (1 => i)); end loop; hdl2ml(in_indexes_id); ml_start_dir(ACTIVE_HDL_PROJECT_PATH & "\src"); eval_string("optPerm_interface"); destroy_array(in_indexes_id); destroy_array(out_indexes_id); return 0; end function; constant DUMMY : integer := execute_Matlab_script; ---------------------------------------------------------------------------------------------------- --vhdl_comp_off */ --vhdl_comp_on --pragma translate on --reads the number of elemental bit-exchange opertations in the solution that is in the file. --Produces an error if the file doesn't exist and we are in synthesis trying to read it impure function read_elemental_ops return natural is variable currentline : line; variable currentchar : character; variable solution : natural := 0; begin --read solution file file_open(solution_input, FILE_PATH, READ_MODE); if endfile(solution_input) then assert false report "The values needed to generate optimum permutations have not yet been " & "generated. It is first required to launch the simulation in order to achieve this" severity error; end if; if not endfile(solution_input) then readline(solution_input, currentline); for i in 1 to currentline'length loop read(currentline, currentchar); solution := 10*solution + (character'pos(currentchar)-character'pos('0')); end loop; end if; file_close(solution_input); return solution; end function; constant ELEMENTAL_OPS : natural := read_elemental_ops; --reads the solution vertexes and returns a static structure with the data impure function read_optimal_perm return integer_vv is variable result : integer_vv(1 to ELEMENTAL_OPS)(1 to 2); variable currentline : line; variable currentchar : character; variable aux : natural := 0; begin file_open(solution_input, FILE_PATH, READ_MODE); if not endfile(solution_input) then readline(solution_input, currentline);--discard first line if not endfile(solution_input) then for i in 1 to ELEMENTAL_OPS loop readline(solution_input, currentline); for j in 1 to currentline'length loop read(currentline, currentchar); if currentchar = ' ' then result(i)(1) := aux; aux := 0; else aux := 10*aux + (character'pos(currentchar)-character'pos('0')); end if; end loop; --add the last read member result(i)(2) := aux; aux := 0; end loop; end if; end if; file_close(solution_input); return result; end function; constant OPTIMAL_PERM : integer_vv(1 to ELEMENTAL_OPS)(1 to 2) := read_optimal_perm; /* signals */ /***********************************************************************************************/ signal inter : sulv_vv(0 to ELEMENTAL_OPS)(INPUT_LENGTH-1 downto 0)(input'element'length-1 downto 0); signal start_delayed : std_ulogic_vector(0 to ELEMENTAL_OPS); /*================================================================================================*/ /*================================================================================================*/ begin check_if_permutations_are_needed: if ELEMENTAL_OPS > 0 generate begin --control part start_delayed(0) <= start; finish <= start_delayed(ELEMENTAL_OPS); --signal part inter(0) <= input; output <= inter(ELEMENTAL_OPS); generate_elemental_operations: for i in 1 to ELEMENTAL_OPS generate begin parallel_parallel: if is_pp_perm(OPTIMAL_PERM(i), PARALLEL_DIMENSIONS) generate begin perm_pp: entity work.perm_pp generic map( indexes => OPTIMAL_PERM(i) ) port map( input => inter(i-1), start => start_delayed(i-1), output => inter(i), finish => start_delayed(i) ); end; end generate; serial_parallel: if is_sp_perm(OPTIMAL_PERM(i), PARALLEL_DIMENSIONS) generate constant aux_left : natural := contiguous_ps_latency(OPTIMAL_PERM, PARALLEL_DIMENSIONS, i, left => true); constant aux_right : natural := contiguous_ps_latency(OPTIMAL_PERM, PARALLEL_DIMENSIONS, i, left => false); begin perm_sp: entity work.perm_sp generic map( dimensions => DIMENSIONS, p_dimensions => PARALLEL_DIMENSIONS, serial_dim => maximum(OPTIMAL_PERM(i)), parallel_dim => minimum(OPTIMAL_PERM(i)), left_ps_latency => aux_left, right_ps_latency => aux_right ) port map( clk => clk, input => inter(i-1), start => start_delayed(i-1), output => inter(i), finish => start_delayed(i) ); end; end generate; serial_serial: if is_ss_perm(OPTIMAL_PERM(i), PARALLEL_DIMENSIONS) generate begin perm_ss: entity work.perm_ss generic map( indexes => OPTIMAL_PERM(i), dimensions => DIMENSIONS ) port map( clk => clk, input => inter(i-1), start => start_delayed(i-1), output => inter(i), finish => start_delayed(i) ); end; end generate; end; end generate; end; else generate begin output <= input; finish <= start; end; end generate; end architecture;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity ps_converter_tb is end ps_converter_tb; architecture tb of ps_converter_tb is -- interface signals signal clk : std_logic := '0'; signal rst : std_logic := '1'; signal clk_en : std_logic := '0'; signal start : std_logic := '0'; signal d : std_logic_vector(7 downto 0) := (others => '0'); signal q : std_logic; -- number of bits to check constant n_byte : positive := 100; -- test vector type byte_array is array(0 to n_byte-1) of std_logic_vector(7 downto 0); signal rand_vector : byte_array; begin dut : entity work.ps_converter port map(clk => clk, rst => rst, clk_en => clk_en, start => start, d => d, q => q); clk <= not clk after 100 ns; rst <= '0' after 500 ns; prepare : process variable seed1, seed2 : positive; variable rand : real; variable rand_unsigned : std_logic_vector(7 downto 0); begin for i in 0 to n_byte-1 loop uniform(seed1, seed2, rand); rand_unsigned := std_logic_vector(to_unsigned(integer(round(255.0*rand)),8)); rand_vector(i) <= rand_unsigned; end loop; wait; end process; test : process begin wait until falling_edge(rst); wait until rising_edge(clk); wait until falling_edge(clk); for i in 0 to n_byte - 1 loop clk_en <= '1'; start <= '1'; d <= rand_vector(i); for j in 0 to 7 loop wait until rising_edge(clk); start <= '0'; wait until falling_edge(clk); assert q = rand_vector(i)(7-j) report "Q output error with i = " & integer'image(i) & " and j = " & integer'image(j) & "." severity warning; end loop; end loop; end process; end tb;
library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; package cmos_sensor_output_generator_constants is constant CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH : positive := 32; -- register offsets constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST : std_logic_vector(2 downto 0) := "000"; -- RW constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_OFST : std_logic_vector(2 downto 0) := "001"; -- RW constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_OFST : std_logic_vector(2 downto 0) := "010"; -- RW constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_OFST : std_logic_vector(2 downto 0) := "011"; -- RW constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_OFST : std_logic_vector(2 downto 0) := "100"; -- RW constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_OFST : std_logic_vector(2 downto 0) := "101"; -- RW constant CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST : std_logic_vector(2 downto 0) := "110"; -- WO constant CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_OFST : std_logic_vector(2 downto 0) := "111"; -- RO -- CONFIG register minimum values constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_MIN : positive := 1; constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_MIN : positive := 1; constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_MIN : positive := 1; constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_MIN : natural := 0; constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_MIN : positive := 1; constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_MIN : natural := 0; -- COMMAND register constant CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_WIDTH : positive := 1; constant CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_STOP : std_logic_vector(0 downto 0) := "0"; constant CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_START : std_logic_vector(0 downto 0) := "1"; -- STATUS register constant CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_IDLE : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0) := X"00000001"; constant CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_BUSY : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0) := X"00000000"; function ceil_log2(num : positive) return natural; function bit_width(num : positive) return positive; function max(left : positive; right : positive) return positive; end package cmos_sensor_output_generator_constants; package body cmos_sensor_output_generator_constants is function ceil_log2(num : positive) return natural is begin return integer(ceil(log2(real(num)))); end function ceil_log2; function bit_width(num : positive) return positive is begin return ceil_log2(num + 1); end function bit_width; function max(left : positive; right : positive) return positive is begin if left > right then return left; else return right; end if; end max; end package body cmos_sensor_output_generator_constants;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2844.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity UNTIL is end UNTIL; ENTITY c13s09b00x00p99n01i02844ent IS END c13s09b00x00p99n01i02844ent; ARCHITECTURE c13s09b00x00p99n01i02844arch OF c13s09b00x00p99n01i02844ent IS BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c13s09b00x00p99n01i02844 - Reserved word UNTIL can not be used as an entity name." severity ERROR; wait; END PROCESS TESTING; END c13s09b00x00p99n01i02844arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2844.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity UNTIL is end UNTIL; ENTITY c13s09b00x00p99n01i02844ent IS END c13s09b00x00p99n01i02844ent; ARCHITECTURE c13s09b00x00p99n01i02844arch OF c13s09b00x00p99n01i02844ent IS BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c13s09b00x00p99n01i02844 - Reserved word UNTIL can not be used as an entity name." severity ERROR; wait; END PROCESS TESTING; END c13s09b00x00p99n01i02844arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2844.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity UNTIL is end UNTIL; ENTITY c13s09b00x00p99n01i02844ent IS END c13s09b00x00p99n01i02844ent; ARCHITECTURE c13s09b00x00p99n01i02844arch OF c13s09b00x00p99n01i02844ent IS BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c13s09b00x00p99n01i02844 - Reserved word UNTIL can not be used as an entity name." severity ERROR; wait; END PROCESS TESTING; END c13s09b00x00p99n01i02844arch;
-- Accellera Standard V2.3 Open Verification Library (OVL). -- Accellera Copyright (c) 2008. All rights reserved. library ieee; use ieee.std_logic_1164.all; use work.std_ovl.all; use work.std_ovl_procs.all; architecture rtl of ovl_cycle_sequence is constant assert_name : string := "OVL_CYCLE_SEQUENCE"; constant path : string := rtl'path_name; constant trig_on_most_pipe : boolean := (necessary_condition = OVL_TRIGGER_ON_MOST_PIPE); constant trig_on_first_pipe : boolean := (necessary_condition = OVL_TRIGGER_ON_FIRST_PIPE); constant trig_on_first_nopipe : boolean := (necessary_condition = OVL_TRIGGER_ON_FIRST_NOPIPE); constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default); constant cover_basic : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_BASIC); signal reset_n : std_logic; signal clk : std_logic; signal fatal_sig : std_logic; signal event_sequence_x01 : std_logic_vector(num_cks - 1 downto 0); signal seq_queue : std_logic_vector(num_cks - 1 downto 0); shared variable error_count : natural; shared variable cover_count : natural; begin event_sequence_x01 <= to_x01(event_sequence); ------------------------------------------------------------------------------ -- Gating logic -- ------------------------------------------------------------------------------ reset_gating : entity work.std_ovl_reset_gating generic map (reset_polarity => reset_polarity, gating_type => gating_type, controls => controls) port map (reset => reset, enable => enable, reset_n => reset_n); clock_gating : entity work.std_ovl_clock_gating generic map (clock_edge => clock_edge, gating_type => gating_type, controls => controls) port map (clock => clock, enable => enable, clk => clk); ------------------------------------------------------------------------------ -- Initialization message -- ------------------------------------------------------------------------------ ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls); end generate ovl_init_msg_gen; ------------------------------------------------------------------------------ -- Shared logic -- ------------------------------------------------------------------------------ ovl_seq_queue_gen : if (ovl_2state_is_on(controls, property_type) or ((controls.cover_ctrl = OVL_ON) and (coverage_level_ctrl /= OVL_COVER_NONE))) generate ovl_seq_queue_p : process (clk) begin if (rising_edge(clk)) then if (reset_n = '0') then seq_queue <= (others => '0'); else if (trig_on_first_nopipe) then seq_queue(num_cks - 1) <= not(or_reduce(seq_queue(num_cks - 1 downto 1))) and event_sequence_x01(num_cks - 1); else seq_queue(num_cks - 1) <= event_sequence_x01(num_cks - 1); end if; seq_queue(num_cks - 2 downto 0) <= seq_queue(num_cks - 1 downto 1) and event_sequence_x01(num_cks - 2 downto 0); end if; end if; end process ovl_seq_queue_p; end generate ovl_seq_queue_gen; ------------------------------------------------------------------------------ -- Assertion - 2-STATE -- ------------------------------------------------------------------------------ ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate ovl_assert_p : process (clk) begin if (rising_edge(clk)) then fatal_sig <= 'Z'; if (reset_n = '0') then fire(0) <= '0'; else fire(0) <= '0'; if (trig_on_first_pipe or trig_on_first_nopipe) then if (and_reduce((seq_queue(num_cks -1 downto 1) and event_sequence_x01(num_cks - 2 downto 0)) or not(seq_queue(num_cks -1 downto 1))) = '0') then fire(0) <= '1'; ovl_error_proc("First event occured but it is not followed by the rest of the events in sequence", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); end if; else -- trig_on_most_pipe if ((not(seq_queue(1)) or (seq_queue(1) and event_sequence_x01(0))) = '0') then fire(0) <= '1'; ovl_error_proc("First num_cks-1 events occured but they are not followed by the last event in sequence", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); end if; end if; end if; -- reset_n = '0' end if; -- rising_edge(clk) end process ovl_assert_p; ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig); end generate ovl_assert_on_gen; ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate fire(0) <= '0'; end generate ovl_assert_off_gen; ------------------------------------------------------------------------------ -- Assertion - X-CHECK -- ------------------------------------------------------------------------------ ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate ovl_xcheck_p : process (clk) function init_valid_sequence_gate return std_logic_vector is variable set : std_logic_vector(num_cks - 2 downto 0); begin if (num_cks > 2) then set(num_cks - 2 downto 1) := (others => '1'); end if; if (trig_on_most_pipe) then set(0) := '0'; else set(0) := '1'; end if; return set; end function init_valid_sequence_gate; variable valid_first_event : std_logic; variable valid_sequence : std_logic; variable valid_last_event : std_logic; constant valid_sequence_gate : std_logic_vector(num_cks - 2 downto 0) := init_valid_sequence_gate; begin if (rising_edge(clk)) then fatal_sig <= 'Z'; valid_first_event := event_sequence_x01(num_cks - 1); valid_last_event := seq_queue(1) and event_sequence_x01(0); valid_sequence := xor_reduce(seq_queue(num_cks - 1 downto 1) and event_sequence_x01(num_cks - 2 downto 0) and valid_sequence_gate); if (reset_n = '0') then fire(1) <= '0'; else fire(1) <= '0'; if (ovl_is_x(valid_first_event)) then if (trig_on_most_pipe or trig_on_first_pipe) then fire(1) <= '1'; ovl_error_proc("First event in the sequence contains X, Z, U, W or -", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); elsif (not(or_reduce(seq_queue(num_cks - 1 downto 1))) = '1') then fire(1) <= '1'; ovl_error_proc("First event in the sequence contains X, Z, U, W or -", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); end if; end if; if (ovl_is_x(valid_sequence)) then if (trig_on_first_pipe or trig_on_first_nopipe) then fire(1) <= '1'; ovl_error_proc("Subsequent events in the sequence contain X, Z, U, W or -", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); else fire(1) <= '1'; ovl_error_proc("First num_cks-1 events in the sequence contain X, Z, U, W or -", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); end if; end if; if (trig_on_most_pipe) then if (ovl_is_x(valid_last_event)) then if (seq_queue(1) = '1') then fire(1) <= '1'; ovl_error_proc("Last event in the sequence contain X, Z, U, W or -", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); else fire(1) <= '1'; ovl_error_proc("First num_cks-1 events in the sequence contain X, Z, U, W or -", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); end if; end if; end if; end if; -- reset_n = '0' end if; -- rising_edge(clk) end process ovl_xcheck_p; end generate ovl_xcheck_on_gen; ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate fire(1) <= '0'; end generate ovl_xcheck_off_gen; ------------------------------------------------------------------------------ -- Coverage -- ------------------------------------------------------------------------------ ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and cover_basic) generate ovl_cover_p : process (clk) begin if (rising_edge(clk)) then if (reset_n = '0') then fire(2) <= '0'; elsif (((trig_on_first_pipe or trig_on_first_nopipe) and (event_sequence_x01(num_cks - 1) = '1')) or (trig_on_most_pipe and (seq_queue(1) = '1'))) then fire(2) <= '1'; ovl_cover_proc("sequence_trigger covered", assert_name, path, controls, cover_count); else fire(2) <= '0'; end if; end if; end process ovl_cover_p; end generate ovl_cover_on_gen; ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or not cover_basic) generate fire(2) <= '0'; end generate ovl_cover_off_gen; end architecture rtl;
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY KCVGA IS PORT ( pin_nRESET : IN STD_LOGIC; pin_CLK : IN STD_LOGIC; pin_PIC32_DATA : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); pin_PIC32_ADDRESS : IN STD_LOGIC_VECTOR(1 DOWNTO 0); pin_PIC32_nWR : IN STD_LOGIC; pin_PIC32_nRD : IN STD_LOGIC; -- pin_KC_CLK : IN STD_LOGIC; -- external video clock 7.09 MHz -- pin_KC_R, pin_KC_G, pin_KC_B : IN STD_LOGIC; -- pixel colors -- pin_KC_EZ : IN STD_LOGIC; -- foreground/background bit -- pin_KC_EX : IN STD_LOGIC; -- intensity bit -- pin_KC_HSYNC : IN STD_LOGIC; -- horizontal sync input -- pin_KC_VSYNC : IN STD_LOGIC; -- vertical sync input -- pin_VGA_R, pin_VGA_G, pin_VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- pin_VGA_VSYNC, pin_VGA_HSYNC : OUT STD_LOGIC; -- pin_JUMPER0 : IN STD_LOGIC -- SCANLINES -- pin_JUMPER1: in STD_LOGIC; -- pin_JUMPER2: in STD_LOGIC; -- pin_JUMPER3: in STD_LOGIC; -- pin_JUMPER4: in STD_LOGIC; -- pin_JUMPER5: in STD_LOGIC pin_SRAM_A : OUT STD_LOGIC_VECTOR (16 DOWNTO 0); -- SRAM address output pin_SRAM_D : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0); -- SRAM data output pin_SRAM_nCE : OUT STD_LOGIC; -- SRAM chip enable pin_SRAM_nOE : OUT STD_LOGIC; -- SRAM output enable pin_SRAM_nWE : OUT STD_LOGIC; -- SRAM write enable pin_SRAM_nBHE : OUT STD_LOGIC; -- SRAM H byte enable pin_SRAM_nBLE : OUT STD_LOGIC -- SRAM L byte enable ); END KCVGA; ARCHITECTURE Behavioral OF KCVGA IS SIGNAL sig_CLK_108MHZ, sig_RESET : STD_LOGIC; -- SIGNAL sig_FRAMESYNC : STD_LOGIC; -- start of frame from VGA module for screensaver -- SIGNAL sig_PIC32_WR_FIFO_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0); -- SIGNAL sig_PIC32_WR_FIFO_IN : STD_LOGIC_VECTOR (31 DOWNTO 0); -- SIGNAL sig_PIC32_WR_FIFO_WR : STD_LOGIC; -- SIGNAL sig_PIC32_WR_FIFO_FULL : STD_LOGIC; -- SIGNAL sig_PIC32_WR_FIFO_RD : STD_LOGIC; -- SIGNAL sig_PIC32_WR_FIFO_EMPTY : STD_LOGIC; -- signal sig_PIC32_RD_FIFO_OUT: STD_LOGIC_VECTOR (31 downto 0); -- signal sig_PIC32_RD_FIFO_IN: STD_LOGIC_VECTOR (31 downto 0); -- signal sig_PIC32_RD_FIFO_WR: STD_LOGIC; -- signal sig_PIC32_RD_FIFO_FULL: STD_LOGIC; -- signal sig_PIC32_RD_FIFO_RD: STD_LOGIC; -- signal sig_PIC32_RD_FIFO_EMPTY: STD_LOGIC; -- SIGNAL sig_KC_FIFO_WR : STD_LOGIC; -- SIGNAL sig_KC_FIFO_FULL : STD_LOGIC; -- SIGNAL sig_KC_FIFO_RD : STD_LOGIC; -- SIGNAL sig_KC_FIFO_EMPTY : STD_LOGIC; -- SIGNAL sig_KC_FIFO_OUT : STD_LOGIC_VECTOR (4 DOWNTO 0); -- SIGNAL sig_KC_FIFO_IN : STD_LOGIC_VECTOR (4 DOWNTO 0); -- SIGNAL sig_KC_ADDR_WR : STD_LOGIC; -- SIGNAL sig_KC_ADDR : STD_LOGIC_VECTOR(16 DOWNTO 0); -- SIGNAL sig_VGA_ADDR_WR : STD_LOGIC; -- SIGNAL sig_VGA_ADDR : STD_LOGIC_VECTOR(16 DOWNTO 0); -- SIGNAL sig_VGA_FIFO_RST : STD_LOGIC; -- SIGNAL sig_VGA_FIFO_RST_COMBINED : STD_LOGIC; -- SIGNAL sig_VGA_FIFO_RD : STD_LOGIC; -- SIGNAL sig_VGA_FIFO_WR : STD_LOGIC; -- SIGNAL sig_VGA_FIFO_IN : STD_LOGIC_VECTOR(4 DOWNTO 0); -- SIGNAL sig_VGA_FIFO_OUT : STD_LOGIC_VECTOR(4 DOWNTO 0); -- SIGNAL sig_VGA_FIFO_EMPTY : STD_LOGIC; -- SIGNAL sig_VGA_FIFO_FULL : STD_LOGIC; -- SIGNAL sig_FLAG_REGISTER : STD_LOGIC_VECTOR(7 DOWNTO 0); -- -- SIGNAL sig_DEBUG_REGISTER : STD_LOGIC_VECTOR(31 DOWNTO 0); -- SIGNAL suppress_no_load_pins_warning : STD_LOGIC; BEGIN -- -- +-------------------+ -- | KCVIDEO_INTERFACE | -- | | -- ====>| R,G,B,EX,EZ | -- | | -- ---->| KC_CLK | -- ---->| HSYNC | -- ---->| VSYNC | -- +-------------------+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- suppress_no_load_pins_warning <= -- pin_KC_EX -- OR pin_KC_EZ -- OR pin_KC_HSYNC -- OR pin_KC_VSYNC -- OR pin_KC_R -- OR pin_KC_G -- OR pin_KC_B -- OR pin_JUMPER0 -- OR pin_KC_CLK; i_CLK : ENTITY work.CLK PORT MAP ( reset => sig_RESET, clk_input => pin_CLK, clk_output => sig_CLK_108MHZ ); sig_RESET <= NOT pin_nRESET; -- sig_FLAG_REGISTER <= '1' & '1' -- & sig_PIC32_WR_FIFO_FULL & sig_PIC32_WR_FIFO_EMPTY -- & sig_KC_FIFO_FULL & sig_KC_FIFO_EMPTY -- & sig_VGA_FIFO_FULL & sig_VGA_FIFO_EMPTY; -- always drive SRAM chip enable, high byte enable and low byte enable with -- active signals -- pin_SRAM_nCE <= '0'; -- pin_SRAM_nBHE <= '0'; -- pin_SRAM_nBLE <= '0'; i_PIC32_INTERFACE : ENTITY work.PIC32_INTERFACE PORT MAP ( CLK => sig_CLK_108MHZ, RESET => sig_RESET, A => pin_PIC32_ADDRESS, D => pin_PIC32_DATA, -- SRAM => sig_PIC32_WR_FIFO_IN, -- OUT_FIFO_WR => sig_PIC32_WR_FIFO_WR, -- OUT_FIFO_FULL => sig_PIC32_WR_FIFO_FULL, nWR => pin_PIC32_nWR, nRD => pin_PIC32_nRD, -- FLAGS => sig_FLAG_REGISTER, -- DEBUG => sig_DEBUG_REGISTER, SRAM_A => pin_SRAM_A, SRAM_D => pin_SRAM_D, SRAM_nOE => pin_SRAM_nOE, SRAM_nWE => pin_SRAM_nWE, SRAM_nCE => pin_SRAM_nCE, SRAM_nBLE => pin_SRAM_nBLE, SRAM_nBHE => pin_SRAM_nBHE -- suppress_no_load_pins_warning => suppress_no_load_pins_warning ); -- i_PIC32_WR_FIFO : ENTITY work.FIFO GENERIC -- MAP( -- RAM_WIDTH => 32, -- RAM_DEPTH => 128 -- ) PORT -- MAP( -- clk => sig_CLK_108MHZ, -- rst => sig_RESET, -- wr_en => sig_PIC32_WR_FIFO_WR, -- wr_data => sig_PIC32_WR_FIFO_IN, -- rd_en => sig_PIC32_WR_FIFO_RD, -- rd_data => sig_PIC32_WR_FIFO_OUT, -- empty => sig_PIC32_WR_FIFO_EMPTY, -- full => sig_PIC32_WR_FIFO_FULL -- ); -- i_KCVIDEO_INTERFACE : ENTITY work.KCVIDEO_INTERFACE PORT -- MAP( -- CLK => sig_CLK_108MHZ, -- KC_CLK => pin_KC_CLK, -- R => pin_KC_R, -- G => pin_KC_G, -- B => pin_KC_B, -- EZ => pin_KC_EZ, -- EX => pin_KC_EX, -- HSYNC => pin_KC_HSYNC, -- VSYNC => pin_KC_VSYNC, -- nRESET => pin_nRESET, -- FIFO_WR => sig_KC_FIFO_WR, -- FIFO_FULL => sig_KC_FIFO_FULL, -- FRAMESYNC => sig_FRAMESYNC, -- DATA_OUT => sig_KC_FIFO_IN, -- SRAM_ADDR => sig_KC_ADDR, -- SRAM_ADDR_WR => sig_KC_ADDR_WR -- ); -- i_KC_FIFO : ENTITY work.FIFO GENERIC -- MAP( -- RAM_WIDTH => 5, -- RAM_DEPTH => 512 -- ) PORT -- MAP( -- clk => sig_CLK_108MHZ, -- rst => sig_RESET, -- wr_en => sig_KC_FIFO_WR, -- wr_data => sig_KC_FIFO_IN, -- rd_en => sig_KC_FIFO_RD, -- rd_data => sig_KC_FIFO_OUT, -- empty => sig_KC_FIFO_EMPTY, -- full => sig_KC_FIFO_FULL -- ); -- -- video mode definition -- -- 1280x1024 @ 60 Hz, 108 MHz pixel clock, positive sync -- i_VGA_OUTPUT : ENTITY work.VGA_OUTPUT GENERIC -- MAP( -- -- see https://www.mythtv.org/wiki/Modeline_Database -- 1280, 1328, 1440, 1688, 1024, 1025, 1028, 1066, '1', '1' -- ) PORT -- MAP( -- CLK => sig_CLK_108MHZ, -- HSYNC => pin_VGA_HSYNC, -- VSYNC => pin_VGA_VSYNC, -- R => pin_VGA_R, G => pin_VGA_G, B => pin_VGA_B, -- nRESET => pin_nRESET, -- SCANLINES => pin_JUMPER0, -- FRAMESYNC => sig_FRAMESYNC, -- FIFO_RD => sig_VGA_FIFO_RD, -- VGA_ADDR_WR => sig_VGA_ADDR_WR, -- VGA_ADDR => sig_VGA_ADDR, -- DATA_IN => sig_VGA_FIFO_OUT, -- VGA_FIFO_EMPTY => sig_VGA_FIFO_EMPTY -- ); -- sig_VGA_FIFO_RST_COMBINED <= sig_VGA_FIFO_RST OR sig_RESET; -- i_VGA_FIFO : ENTITY work.FIFO GENERIC -- MAP( -- RAM_WIDTH => 5, -- RAM_DEPTH => 512 -- ) PORT -- MAP( -- clk => sig_CLK_108MHZ, -- rst => sig_VGA_FIFO_RST_COMBINED, -- wr_en => sig_VGA_FIFO_WR, -- wr_data => sig_VGA_FIFO_IN, -- rd_en => sig_VGA_FIFO_RD, -- rd_data => sig_VGA_FIFO_OUT, -- empty => sig_VGA_FIFO_EMPTY, -- full => sig_VGA_FIFO_FULL -- ); -- i_SRAM_INTERFACE : ENTITY work.SRAM_INTERFACE PORT -- MAP( -- VGA_ADDR => sig_VGA_ADDR, -- address requested from VGA module -- VGA_DATA => sig_VGA_FIFO_IN, -- data out to VGA module -- VGA_ADDR_WR => sig_VGA_ADDR_WR, -- VGA address write input -- VGA_FIFO_WR => sig_VGA_FIFO_WR, -- VGA FIFO write output -- VGA_FIFO_RST => sig_VGA_FIFO_RST, -- VGA_FIFO_FULL => sig_VGA_FIFO_FULL, -- KCVIDEO_DATA => sig_KC_FIFO_OUT, -- KCVIDEO_FIFO_RD => sig_KC_FIFO_RD, -- KCVIDEO_FIFO_EMPTY => sig_KC_FIFO_EMPTY, -- PIC32_DATA => sig_PIC32_WR_FIFO_OUT, -- PIC32_FIFO_RD => sig_PIC32_WR_FIFO_RD, -- PIC32_FIFO_EMPTY => sig_PIC32_WR_FIFO_EMPTY, -- A => pin_SRAM_A, -- D => pin_SRAM_D, -- nOE => pin_SRAM_nOE, -- nWE => pin_SRAM_nWE, -- nCE => pin_SRAM_nCE, -- nBLE => pin_SRAM_nBLE, -- nBHE => pin_SRAM_nBHE, -- reset => sig_RESET, -- CLK => sig_CLK_108MHZ, -- KCVIDEO_ADDR => sig_KC_ADDR, -- KCVIDEO_ADDR_WR => sig_KC_ADDR_WR, -- DEBUG => sig_DEBUG_REGISTER -- ); END Behavioral;
------------------------------------------------------------------------------- -- -- Title : regfile_decode -- Design : ALU -- Author : riczhang -- Company : Stony Brook University -- ------------------------------------------------------------------------------- -- -- File : c:\My_Designs\ESE345_PROJECT\ALU\src\regfile_decode.vhd -- Generated : Wed Dec 7 00:53:08 2016 -- From : interface description file -- By : Itf2Vhdl ver. 1.22 -- ------------------------------------------------------------------------------- -- -- Description : -- ------------------------------------------------------------------------------- --{{ Section below this comment is automatically maintained -- and may be overwritten --{entity {regfile_decode} architecture {behavioral}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity regfile_decode is port( instruction: in std_logic_vector(15 downto 0); op_code, rs1_addr, rs2_addr, rd_addr : out std_logic_vector(3 downto 0) ); end regfile_decode; --}} End of automatically maintained section architecture behavioral of regfile_decode is begin op_code <= instruction(15 downto 12); rs2_addr <= instruction(11 downto 8); rs1_addr <= instruction(7 downto 4); rd_addr <= instruction(3 downto 0); end behavioral;
-- File: gray_counter_24.vhd -- Generated by MyHDL 0.8dev -- Date: Sun Feb 3 17:16:41 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_08.all; entity gray_counter_24 is port ( gray_count: out unsigned(23 downto 0); enable: in std_logic; clock: in std_logic; reset: in std_logic ); end entity gray_counter_24; architecture MyHDL of gray_counter_24 is signal even: std_logic; signal gray: unsigned(23 downto 0); begin GRAY_COUNTER_24_SEQ: process (clock, reset) is variable found: std_logic; variable word: unsigned(23 downto 0); begin if (reset = '1') then even <= '1'; gray <= (others => '0'); elsif rising_edge(clock) then word := unsigned'("1" & gray((24 - 2)-1 downto 0) & even); if bool(enable) then found := '0'; for i in 0 to 24-1 loop if ((word(i) = '1') and (not bool(found))) then gray(i) <= stdl((not bool(gray(i)))); found := '1'; end if; end loop; even <= stdl((not bool(even))); end if; end if; end process GRAY_COUNTER_24_SEQ; gray_count <= gray; end architecture MyHDL;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity k_ukf_Pdashofkplusone is port ( clock : in std_logic; Vsigactofkofzero : in std_logic_vector(31 downto 0); Vsigactofkofone : in std_logic_vector(31 downto 0); Vsigactofkoftwo : in std_logic_vector(31 downto 0); Wofcofzero : in std_logic_vector(31 downto 0); Wofcofone : in std_logic_vector(31 downto 0); Wofcoftwo : in std_logic_vector(31 downto 0); Vactcapdashofkplusone : in std_logic_vector(31 downto 0); Q : in std_logic_vector(31 downto 0); Pdashofkplusone : out std_logic_vector(31 downto 0) ); end k_ukf_Pdashofkplusone; architecture struct of k_ukf_Pdashofkplusone is component k_ukf_mult IS PORT ( clock : IN STD_LOGIC ; dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component k_ukf_add IS PORT ( clock : IN STD_LOGIC ; dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component k_ukf_sub IS PORT ( clock : IN STD_LOGIC ; dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; signal Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11 : std_logic_vector(31 downto 0); begin M1 : k_ukf_sub port map ( clock => clock, dataa => Vsigactofkofzero, datab => Vactcapdashofkplusone, result => Z1); M2 : k_ukf_sub port map ( clock => clock, dataa => Vsigactofkofone, datab => Vactcapdashofkplusone, result => Z4); M3 : k_ukf_sub port map ( clock => clock, dataa => Vsigactofkoftwo, datab => Vactcapdashofkplusone, result => Z7); M4 : k_ukf_mult port map ( clock => clock, dataa => Z1, datab => Z1, result => Z2); M5 : k_ukf_mult port map ( clock => clock, dataa => Z4, datab => Z4, result => Z5); M6 : k_ukf_mult port map ( clock => clock, dataa => Z7, datab => Z7, result => Z8); M7 : k_ukf_mult port map ( clock => clock, dataa => Z2, datab => Wofcofzero, result => Z3); M8 : k_ukf_mult port map ( clock => clock, dataa => Z5, datab => Wofcofone, result => Z6); M9 : k_ukf_mult port map ( clock => clock, dataa => Z8, datab => Wofcoftwo, result => Z9); M10 : k_ukf_add port map ( clock => clock, dataa => Z3, datab => Z6, result => Z10); M11 : k_ukf_add port map ( clock => clock, dataa => Z10, datab => Z9, result => Z11); M12 : k_ukf_add port map ( clock => clock, dataa => Q, datab => Z11, result => Pdashofkplusone); end struct;
-- $Id: sys_w11a_b3.vhd 1247 2022-07-06 07:04:33Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> -- ------------------------------------------------------------------------------ -- Module Name: sys_w11a_b3 - syn -- Description: w11a test design for basys3 -- -- Dependencies: bplib/bpgen/s7_cmt_1ce1ce -- bplib/bpgen/bp_rs232_2line_iob -- vlib/rlink/rlink_sp2c -- w11a/pdp11_sys70 -- ibus/ibdr_maxisys -- w11a/pdp11_bram_memctl -- vlib/rlink/ioleds_sp1c -- w11a/pdp11_hio70 -- bplib/bpgen/sn_humanio_rbus -- bplib/sysmon/sysmonx_rbus_base -- vlib/rbus/rbd_usracc -- vlib/rbus/rb_sres_or_4 -- -- Test bench: tb/tb_sys_w11a_b3 -- -- Target Devices: generic -- Tool versions: viv 2014.4-2022.1; ghdl 0.31-2.0.0 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic -- 2022-07-05 1247 2022.1 xc7a35t-1 3011 5669 267 48.0 1906 -- 2019-05-19 1150 2017.2 xc7a35t-1 2968 6360 273 48.0 1963 +dz11 -- 2019-04-27 1140 2017.2 xc7a35t-1 2835 6032 248 47.5 1879 +*buf -- 2019-03-02 1116 2017.2 xc7a35t-1 2748 5725 186 47.5 1811 +ibtst -- 2019-02-02 1108 2018.3 xc7a35t-1 2711 5910 170 47.5 1825 -- 2019-02-02 1108 2017.2 xc7a35t-1 2698 5636 170 47.5 1728 -- 2018-10-13 1055 2017.2 xc7a35t-1 2698 5636 170 47.5 1723 +dmpcnt -- 2018-09-15 1045 2017.2 xc7a35t-1 2475 5282 138 47.5 1643 +KW11P -- 2017-04-16 881 2016.4 xc7a35t-1 2412 5228 138 47.5 1608 +DEUNA -- 2017-01-29 846 2016.4 xc7a35t-1 2362 5239 138 47.5 1619 +int24 -- 2016-05-26 768 2016.1 xc7a35t-1 2361 5203 138 47.5 1600 fsm+dsm=0 -- 2016-05-22 767 2016.1 xc7a35t-1 2362 5340 138 48.5 1660 fsm -- 2016-03-29 756 2015.4 xc7a35t-1 2240 4518 138 48.5 1430 serport2 -- 2016-03-27 753 2015.4 xc7a35t-1 2131 4398 138 48.5 1362 meminf -- 2016-03-13 742 2015.4 xc7a35t-1 2135 4420 162 48.5 1396 +XADC -- 2015-06-04 686 2014.4 xc7a35t-1 1919 4372 162 47.5 1408 +TM11 17% -- 2015-05-14 680 2014.4 xc7a35t-1 1837 4304 162 47.5 1354 +RHRP 17% -- 2015-02-21 649 2014.4 xc7a35t-1 1637 3767 146 47.5 1195 -- -- Revision History: -- Date Rev Version Comment -- 2018-12-16 1086 1.5 use s7_cmt_1ce1ce -- 2018-10-13 1055 2.4 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT -- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access) -- 2016-03-28 755 2.3 use serport_2clock2 -- 2016-03-19 748 2.2.2 define rlink SYSID -- 2016-03-18 745 2.2.1 hardwire XON=1 -- 2016-03-13 742 2.2 add sysmon_rbus -- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul -- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 -- 2015-04-11 666 1.1.1 rearrange XON handling -- 2015-02-21 649 1.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) -- 2015-02-08 644 1.0 Initial version (derived from sys_w11a_n4) ------------------------------------------------------------------------------ -- -- w11a test design for basys3 -- w11a + rlink + serport -- -- Usage of Basys 3 Switches, Buttons, LEDs -- -- SWI(15:6): no function (only connected to sn_humanio_rbus) -- SWI(5:4): select DSP -- 00 abclkdiv & abclkdiv_f -- 01 PC -- 10 DISPREG -- 11 DR emulation -- SWI(3): select LED display -- 0 overall status -- 1 DR emulation -- SWI(2): unused-reserved (USB port select) -- SWI(1): unused-reserved (XON, is hardwired to '1') -- SWI(0): unused-reserved (serial port select) -- -- LEDs if SWI(3) = 1 -- (15:0) DR emulation; shows R0 during wait like 11/45+70 -- -- LEDs if SWI(3) = 0 -- (7) MEM_ACT_W -- (6) MEM_ACT_R -- (5) cmdbusy (all rlink access, mostly rdma) -- (4:0) if cpugo=1 show cpu mode activity -- (4) kernel mode, pri>0 -- (3) kernel mode, pri=0 -- (2) kernel mode, wait -- (1) supervisor mode -- (0) user mode -- if cpugo=0 shows cpurust -- (4) '1' -- (3:0) cpurust code -- -- DSP(7:4) shows abclkdiv & abclkdiv_f or PS depending on SWI(4) -- DSP(3:0) shows DISPREG -- DP(3:0) shows IO activity -- (3) not SER_MONI.txok (shows tx back pressure) -- (2) SER_MONI.txact (shows tx activity) -- (1) not SER_MONI.rxok (shows rx back pressure) -- (0) SER_MONI.rxact (shows rx activity) -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.serportlib.all; use work.rblib.all; use work.rbdlib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.bpgenrbuslib.all; use work.sysmonrbuslib.all; use work.iblib.all; use work.ibdlib.all; use work.pdp11.all; use work.sys_conf.all; -- ---------------------------------------------------------------------------- entity sys_w11a_b3 is -- top level -- implements basys3_aif port ( I_CLK100 : in slbit; -- 100 MHz clock I_RXD : in slbit; -- receive data (board view) O_TXD : out slbit; -- transmit data (board view) I_SWI : in slv16; -- b3 switches I_BTN : in slv5; -- b3 buttons O_LED : out slv16; -- b3 leds O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) ); end sys_w11a_b3; architecture syn of sys_w11a_b3 is signal CLK : slbit := '0'; signal RESET : slbit := '0'; signal CE_USEC : slbit := '0'; signal CE_MSEC : slbit := '0'; signal CLKS : slbit := '0'; signal CES_MSEC : slbit := '0'; signal RXD : slbit := '1'; signal TXD : slbit := '0'; signal RB_MREQ : rb_mreq_type := rb_mreq_init; signal RB_SRES : rb_sres_type := rb_sres_init; signal RB_SRES_CPU : rb_sres_type := rb_sres_init; signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); signal SER_MONI : serport_moni_type := serport_moni_init; signal GRESET : slbit := '0'; -- general reset (from rbus) signal CRESET : slbit := '0'; -- cpu reset (from cp) signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) signal PERFEXT : slv8 := (others=>'0'); signal EI_PRI : slv3 := (others=>'0'); signal EI_VECT : slv9_2 := (others=>'0'); signal EI_ACKM : slbit := '0'; signal CP_STAT : cp_stat_type := cp_stat_init; signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init; signal MEM_REQ : slbit := '0'; signal MEM_WE : slbit := '0'; signal MEM_BUSY : slbit := '0'; signal MEM_ACK_R : slbit := '0'; signal MEM_ACT_R : slbit := '0'; signal MEM_ACT_W : slbit := '0'; signal MEM_ADDR : slv20 := (others=>'0'); signal MEM_BE : slv4 := (others=>'0'); signal MEM_DI : slv32 := (others=>'0'); signal MEM_DO : slv32 := (others=>'0'); signal IB_MREQ : ib_mreq_type := ib_mreq_init; signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; signal DISPREG : slv16 := (others=>'0'); signal ABCLKDIV : slv16 := (others=>'0'); signal SWI : slv16 := (others=>'0'); signal BTN : slv5 := (others=>'0'); signal LED : slv16 := (others=>'0'); signal DSP_DAT : slv16 := (others=>'0'); signal DSP_DP : slv4 := (others=>'0'); constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx constant sysid_proj : slv16 := x"0201"; -- w11a constant sysid_board : slv8 := x"06"; -- basys3 constant sysid_vers : slv8 := x"00"; begin assert (sys_conf_clksys mod 1000000) = 0 report "assert sys_conf_clksys on MHz grid" severity failure; GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------ generic map ( CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, CLK0_VCODIV => sys_conf_clksys_vcodivide, CLK0_VCOMUL => sys_conf_clksys_vcomultiply, CLK0_OUTDIV => sys_conf_clksys_outdivide, CLK0_GENTYPE => sys_conf_clksys_gentype, CLK0_CDUWIDTH => 7, CLK0_USECDIV => sys_conf_clksys_mhz, CLK0_MSECDIV => 1000, CLK1_VCODIV => sys_conf_clkser_vcodivide, CLK1_VCOMUL => sys_conf_clkser_vcomultiply, CLK1_OUTDIV => sys_conf_clkser_outdivide, CLK1_GENTYPE => sys_conf_clkser_gentype, CLK1_CDUWIDTH => 7, CLK1_USECDIV => sys_conf_clkser_mhz, CLK1_MSECDIV => 1000) port map ( CLKIN => I_CLK100, CLK0 => CLK, CE0_USEC => CE_USEC, CE0_MSEC => CE_MSEC, CLK1 => CLKS, CE1_USEC => open, CE1_MSEC => CES_MSEC, LOCKED => open ); IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- port map ( CLK => CLKS, RXD => RXD, TXD => TXD, I_RXD => I_RXD, O_TXD => O_TXD ); RLINK : rlink_sp2c -- rlink for serport ----------------- generic map ( BTOWIDTH => 7, -- 128 cycles access timeout RTAWIDTH => 12, SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, -- 32 word input fifo OFAWIDTH => 5, -- 32 word output fifo ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 12, CDINIT => sys_conf_ser2rri_cdinit, RBMON_AWIDTH => sys_conf_rbmon_awidth, RBMON_RBADDR => rbaddr_rbmon) port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC, CE_INT => CE_MSEC, RESET => RESET, CLKS => CLKS, CES_MSEC => CES_MSEC, ENAXON => '1', ESCFILL => '0', RXSD => RXD, TXSD => TXD, CTS_N => '0', RTS_N => open, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES, RB_LAM => RB_LAM, RB_STAT => RB_STAT, RL_MONI => open, SER_MONI => SER_MONI ); PERFEXT(0) <= '0'; -- unused (ext_rdrhit) PERFEXT(1) <= '0'; -- unused (ext_wrrhit) PERFEXT(2) <= '0'; -- unused (ext_wrflush) PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback PERFEXT(7) <= CE_USEC; -- ext_usec SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- port map ( CLK => CLK, RESET => RESET, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_CPU, RB_STAT => RB_STAT, RB_LAM_CPU => RB_LAM(0), GRESET => GRESET, CRESET => CRESET, BRESET => BRESET, CP_STAT => CP_STAT, EI_PRI => EI_PRI, EI_VECT => EI_VECT, EI_ACKM => EI_ACKM, PERFEXT => PERFEXT, IB_MREQ => IB_MREQ, IB_SRES => IB_SRES_IBDR, MEM_REQ => MEM_REQ, MEM_WE => MEM_WE, MEM_BUSY => MEM_BUSY, MEM_ACK_R => MEM_ACK_R, MEM_ADDR => MEM_ADDR, MEM_BE => MEM_BE, MEM_DI => MEM_DI, MEM_DO => MEM_DO, DM_STAT_EXP => DM_STAT_EXP ); IBDR_SYS : ibdr_maxisys -- IO system ------------------------- port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC, RESET => GRESET, BRESET => BRESET, ITIMER => DM_STAT_EXP.se_itimer, IDEC => DM_STAT_EXP.se_idec, CPUSUSP => CP_STAT.cpususp, RB_LAM => RB_LAM(15 downto 1), IB_MREQ => IB_MREQ, IB_SRES => IB_SRES_IBDR, EI_ACKM => EI_ACKM, EI_PRI => EI_PRI, EI_VECT => EI_VECT, DISPREG => DISPREG ); BRAM_CTL: pdp11_bram_memctl -- memory controller ----------------- generic map ( MAWIDTH => sys_conf_memctl_mawidth, NBLOCK => sys_conf_memctl_nblock) port map ( CLK => CLK, RESET => GRESET, REQ => MEM_REQ, WE => MEM_WE, BUSY => MEM_BUSY, ACK_R => MEM_ACK_R, ACK_W => open, ACT_R => MEM_ACT_R, ACT_W => MEM_ACT_W, ADDR => MEM_ADDR, BE => MEM_BE, DI => MEM_DI, DO => MEM_DO ); LED_IO : ioleds_sp1c -- hio leds from serport ------------- port map ( SER_MONI => SER_MONI, IOLEDS => DSP_DP ); ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; HIO70 : pdp11_hio70 -- hio from sys70 -------------------- generic map ( LWIDTH => LED'length, DCWIDTH => 2) port map ( SEL_LED => SWI(3), SEL_DSP => SWI(5 downto 4), MEM_ACT_R => MEM_ACT_R, MEM_ACT_W => MEM_ACT_W, CP_STAT => CP_STAT, DM_STAT_EXP => DM_STAT_EXP, ABCLKDIV => ABCLKDIV, DISPREG => DISPREG, LED => LED, DSP_DAT => DSP_DAT ); HIO : sn_humanio_rbus -- hio manager ----------------------- generic map ( SWIDTH => 16, BWIDTH => 5, LWIDTH => 16, DCWIDTH => 2, DEBOUNCE => sys_conf_hio_debounce, RB_ADDR => rbaddr_hio) port map ( CLK => CLK, RESET => RESET, CE_MSEC => CE_MSEC, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_HIO, SWI => SWI, BTN => BTN, LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP, I_SWI => I_SWI, I_BTN => I_BTN, O_LED => O_LED, O_ANO_N => O_ANO_N, O_SEG_N => O_SEG_N ); SMRB : if sys_conf_rbd_sysmon generate I0: sysmonx_rbus_base generic map ( -- use default INIT_ (Vccint=1.00) CLK_MHZ => sys_conf_clksys_mhz, RB_ADDR => rbaddr_sysmon) port map ( CLK => CLK, RESET => RESET, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_SYSMON, ALM => open, OT => open, TEMP => open ); end generate SMRB; UARB : rbd_usracc port map ( CLK => CLK, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_USRACC ); RB_SRES_OR : rb_sres_or_4 -- rbus or --------------------------- port map ( RB_SRES_1 => RB_SRES_CPU, RB_SRES_2 => RB_SRES_HIO, RB_SRES_3 => RB_SRES_SYSMON, RB_SRES_4 => RB_SRES_USRACC, RB_SRES_OR => RB_SRES ); end syn;
------------------------------------------------------------------------------- -- -- Title : No Title -- Design : -- Author : Shadowmaker -- Company : Home -- ------------------------------------------------------------------------------- -- -- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task1_TB\Task1_tb3.vhd -- Generated : 10/18/14 15:54:05 -- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task1.asf -- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005 -- ------------------------------------------------------------------------------- -- -- Description : -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library IEEE; use IEEE.STD_LOGIC_TEXTIO.all; use STD.TEXTIO.all; entity Task1_ent_tb3 is end entity Task1_ent_tb3; architecture Task1_arch_tb3 of Task1_ent_tb3 is constant delay_wr_in : Time := 5 ns; constant delay_pos_edge : Time := 5 ns; constant delay_wr_out : Time := 5 ns; constant delay_neg_edge : Time := 5 ns; file RESULTS : Text open WRITE_MODE is "results.txt"; procedure WRITE_RESULTS( constant CLK : in Std_logic; constant RST : in Std_logic; constant IP : in Std_logic_Vector (3 downto 0); constant OP : in Std_logic_Vector (1 downto 0) ) is variable l_out : Line; begin WRITE(l_out, now, right, 15, ps); -- write input signals WRITE(l_out, CLK, right, 8); WRITE(l_out, RST, right, 8); WRITE(l_out, IP, right, 11); -- write output signals WRITE(l_out, OP, right, 9); WRITELINE(RESULTS, l_out); end; component Task1 is port( CLK : in Std_logic; RST : in Std_logic; IP : in Std_logic_Vector (3 downto 0); OP :out Std_logic_Vector (1 downto 0)); end component; -- Task1; signal CLK : Std_logic; signal RST : Std_logic; signal IP : Std_logic_Vector (3 downto 0); signal OP : Std_logic_Vector (1 downto 0); signal cycle_num : Integer; -- takt number -- this signal is added for compare test simulation results only type test_state_type is (S0, S1, S2, S3, S4, any_state); signal test_state : test_state_type; begin UUT : Task1 port map( CLK => CLK, RST => RST, IP => IP, OP => OP); STIMULI : process begin -- Test reset - state(i) CLK <= '0'; cycle_num <= 0; wait for delay_wr_in; RST <= '1'; IP <= "0000"; wait for delay_pos_edge; test_state <= S0; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S0 CLK <= '0'; cycle_num <= 1; wait for delay_wr_in; RST <= '0'; wait for delay_pos_edge; test_state <= S1; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S1 CLK <= '0'; cycle_num <= 2; wait for delay_wr_in; RST <= '1'; wait for delay_pos_edge; test_state <= S0; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S0 CLK <= '0'; cycle_num <= 3; wait for delay_wr_in; RST <= '0'; wait for delay_pos_edge; test_state <= S1; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S1 CLK <= '0'; cycle_num <= 4; wait for delay_wr_in; RST <= '0'; IP <= "1101"; wait for delay_pos_edge; test_state <= S2; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S2 CLK <= '0'; cycle_num <= 5; wait for delay_wr_in; RST <= '1'; wait for delay_pos_edge; test_state <= S0; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S0 CLK <= '0'; cycle_num <= 6; wait for delay_wr_in; RST <= '0'; wait for delay_pos_edge; test_state <= S1; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S1 CLK <= '0'; cycle_num <= 7; wait for delay_wr_in; RST <= '0'; IP <= "1101"; wait for delay_pos_edge; test_state <= S2; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S2 CLK <= '0'; cycle_num <= 8; wait for delay_wr_in; RST <= '0'; IP <= "1111"; wait for delay_pos_edge; test_state <= S3; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S3 CLK <= '0'; cycle_num <= 9; wait for delay_wr_in; RST <= '1'; wait for delay_pos_edge; test_state <= S0; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S0 CLK <= '0'; cycle_num <= 10; wait for delay_wr_in; RST <= '0'; wait for delay_pos_edge; test_state <= S1; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S1 CLK <= '0'; cycle_num <= 11; wait for delay_wr_in; RST <= '0'; IP <= "1101"; wait for delay_pos_edge; test_state <= S2; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S2 CLK <= '0'; cycle_num <= 12; wait for delay_wr_in; RST <= '0'; IP <= "0001"; wait for delay_pos_edge; test_state <= S4; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S4 CLK <= '0'; cycle_num <= 13; wait for delay_wr_in; RST <= '1'; wait for delay_pos_edge; test_state <= S0; CLK <= '1'; wait for delay_wr_out; wait for delay_neg_edge; -- S0 -- Test length 14 wait; -- stop simulation end process; -- STIMULI; WRITE_RESULTS(CLK,RST,IP,OP); end architecture Task1_arch_tb3; configuration Task1_cfg_tb3 of Task1_ent_tb3 is for Task1_arch_tb3 for UUT : Task1 use entity work.Task1(Beh); end for; end for; end Task1_cfg_tb3;
architecture rtl of fifo is variable sig8 : record_type_3( element1(7 downto 0), element2(4 downto 0)(7 downto 0) ( elementA(7 downto 0) , elementB(3 downto 0) ), element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)), element5( elementE (3 downto 0) (6 downto 0) , elementF(7 downto 0) ), element6(4 downto 0), element7(7 downto 0)); variable sig9 : t_data_struct(data(7 downto 0)); variable sig9 : t_data_struct( data(7 downto 0) ); begin end architecture rtl;
-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_queue.vhd -- Description: This entity is the descriptor fetch queue interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library proc_common_v4_0; use proc_common_v4_0.sync_fifo_fg; use proc_common_v4_0.proc_common_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_ftch_q_mngr is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Stream Data width C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_INCLUDE_CH1 : integer range 0 to 1 := 1; -- Include or Exclude channel 1 scatter gather engine -- 0 = Exclude Channel 1 SG Engine -- 1 = Include Channel 1 SG Engine C_INCLUDE_CH2 : integer range 0 to 1 := 1; -- Include or Exclude channel 2 scatter gather engine -- 0 = Exclude Channel 2 SG Engine -- 1 = Include Channel 2 SG Engine C_ENABLE_CDMA : integer range 0 to 1 := 0; C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_mm2s_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- p_reset_n : in std_logic ; ch2_sg_idle : in std_logic ; -- -- Channel 1 Control -- ch1_desc_flush : in std_logic ; -- ch1_cyclic : in std_logic ; -- ch1_cntrl_strm_stop : in std_logic ; ch1_ftch_active : in std_logic ; -- ch1_nxtdesc_wren : out std_logic ; -- ch1_ftch_queue_empty : out std_logic ; -- ch1_ftch_queue_full : out std_logic ; -- ch1_ftch_pause : out std_logic ; -- -- -- Channel 2 Control -- ch2_desc_flush : in std_logic ; -- ch2_cyclic : in std_logic ; -- ch2_ftch_active : in std_logic ; -- ch2_nxtdesc_wren : out std_logic ; -- ch2_ftch_queue_empty : out std_logic ; -- ch2_ftch_queue_full : out std_logic ; -- ch2_ftch_pause : out std_logic ; -- nxtdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- -- DataMover Command -- ftch_cmnd_wr : in std_logic ; -- ftch_cmnd_data : in std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- ftch_stale_desc : out std_logic ; -- -- -- MM2S Stream In from DataMover -- m_axis_mm2s_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_mm2s_tkeep : in std_logic_vector -- ((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0); -- m_axis_mm2s_tlast : in std_logic ; -- m_axis_mm2s_tvalid : in std_logic ; -- m_axis_mm2s_tready : out std_logic ; -- -- -- -- Channel 1 AXI Fetch Stream Out -- m_axis_ch1_ftch_aclk : in std_logic ; m_axis_ch1_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_ch1_ftch_tvalid : out std_logic ; -- m_axis_ch1_ftch_tready : in std_logic ; -- m_axis_ch1_ftch_tlast : out std_logic ; -- m_axis_ch1_ftch_tdata_new : out std_logic_vector -- (96+31*C_ENABLE_CDMA downto 0); -- m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ch1_ftch_tvalid_new : out std_logic ; -- m_axis_ftch1_desc_available : out std_logic ; -- m_axis_ch2_ftch_tdata_new : out std_logic_vector -- (96+31*C_ENABLE_CDMA downto 0); -- m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector -- (31 downto 0); -- m_axis_ch2_ftch_tvalid_new : out std_logic ; -- m_axis_ftch2_desc_available : out std_logic ; -- -- Channel 2 AXI Fetch Stream Out -- m_axis_ch2_ftch_aclk : in std_logic ; -- m_axis_ch2_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_ch2_ftch_tvalid : out std_logic ; -- m_axis_ch2_ftch_tready : in std_logic ; -- m_axis_ch2_ftch_tlast : out std_logic ; -- m_axis_mm2s_cntrl_tdata : out std_logic_vector -- (31 downto 0); -- m_axis_mm2s_cntrl_tkeep : out std_logic_vector -- (3 downto 0); -- m_axis_mm2s_cntrl_tvalid : out std_logic ; -- m_axis_mm2s_cntrl_tready : in std_logic := '0'; -- m_axis_mm2s_cntrl_tlast : out std_logic -- ); end axi_sg_ftch_q_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_q_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Determine the maximum word count for use in setting the word counter width -- Set bit width on max num words to fetch constant FETCH_COUNT : integer := max2(C_SG_CH1_WORDS_TO_FETCH ,C_SG_CH2_WORDS_TO_FETCH); -- LOG2 to get width of counter constant WORDS2FETCH_BITWIDTH : integer := clog2(FETCH_COUNT); -- Zero value for counter constant WORD_ZERO : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0'); -- One value for counter constant WORD_ONE : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0) := std_logic_vector(to_unsigned(1,WORDS2FETCH_BITWIDTH)); -- Seven value for counter constant WORD_SEVEN : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0) := std_logic_vector(to_unsigned(7,WORDS2FETCH_BITWIDTH)); constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal m_axis_mm2s_tready_i : std_logic := '0'; signal ch1_ftch_tready : std_logic := '0'; signal ch2_ftch_tready : std_logic := '0'; -- Misc Signals signal writing_curdesc : std_logic := '0'; signal fetch_word_count : std_logic_vector (WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0'); signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0'); signal lsbnxtdesc_tready : std_logic := '0'; signal msbnxtdesc_tready : std_logic := '0'; signal nxtdesc_tready : std_logic := '0'; signal ch1_writing_curdesc : std_logic := '0'; signal ch2_writing_curdesc : std_logic := '0'; signal m_axis_ch2_ftch_tvalid_1 : std_logic := '0'; -- KAPIL signal ch_desc_flush : std_logic := '0'; signal m_axis_ch_ftch_tready : std_logic := '0'; signal ch_ftch_queue_empty : std_logic := '0'; signal ch_ftch_queue_full : std_logic := '0'; signal ch_ftch_pause : std_logic := '0'; signal ch_writing_curdesc : std_logic := '0'; signal ch_ftch_tready : std_logic := '0'; signal m_axis_ch_ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_axis_ch_ftch_tvalid : std_logic := '0'; signal m_axis_ch_ftch_tlast : std_logic := '0'; signal data_concat : std_logic_vector (95 downto 0) := (others => '0'); signal data_concat_mcdma : std_logic_vector (63 downto 0) := (others => '0'); signal next_bd : std_logic_vector (31 downto 0) := (others => '0'); signal data_concat_valid, tvalid_new : std_logic; attribute mark_debug of data_concat_valid : signal is "true"; attribute mark_debug of tvalid_new : signal is "true"; signal data_concat_tlast, tlast_new : std_logic; attribute mark_debug of data_concat_tlast : signal is "true"; attribute mark_debug of tlast_new : signal is "true"; signal counter : std_logic_vector (C_SG_CH1_WORDS_TO_FETCH-1 downto 0); attribute mark_debug of counter : signal is "true"; signal sof_ftch_desc : std_logic; signal nxtdesc_int : std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- attribute mark_debug of nxtdesc_int : signal is "true"; signal cyclic_enable : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin cyclic_enable <= ch1_cyclic when ch1_ftch_active = '1' else ch2_cyclic; nxtdesc <= nxtdesc_int; TLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH = 13) generate -- TLAST is generated when 8th beat is received tlast_new <= counter (7) and m_axis_mm2s_tvalid; tvalid_new <= counter (7) and m_axis_mm2s_tvalid; SOF_CHECK : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tlast = '1'))then sof_ftch_desc <= '0'; elsif(counter (6) = '1' and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tdata(27) = '1' )then sof_ftch_desc <= '1'; end if; end if; end process SOF_CHECK; end generate TLAST_GEN; NOTLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH /= 13) generate sof_ftch_desc <= '0'; CDMA : if C_ENABLE_CDMA = 1 generate -- For CDMA TLAST is generated when 7th beat is received -- because last one is not needed tlast_new <= counter (6) and m_axis_mm2s_tvalid; tvalid_new <=counter (6) and m_axis_mm2s_tvalid; end generate CDMA; NOCDMA : if C_ENABLE_CDMA = 0 generate -- For DMA tlast is generated with 8th beat tlast_new <= counter (7) and m_axis_mm2s_tvalid; tvalid_new <= counter (7) and m_axis_mm2s_tvalid; end generate NOCDMA; end generate NOTLAST_GEN; -- Following shift register keeps track of number of data beats -- of BD that is being read DATA_BEAT_REG : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1')) then counter (0) <= '1'; counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= (others => '0'); Elsif (m_axis_mm2s_tvalid = '1') then counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= counter (C_SG_CH1_WORDS_TO_FETCH-2 downto 0); counter (0) <= '0'; end if; end if; end process DATA_BEAT_REG; -- Registering the Buffer address from BD, 3rd beat -- Common for DMA, CDMA DATA_REG1 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (31 downto 0) <= (others => '0'); Elsif (counter (2) = '1') then data_concat (31 downto 0) <= m_axis_mm2s_tdata; end if; end if; end process DATA_REG1; DMA_REG2 : if C_ENABLE_CDMA = 0 generate begin -- For DMA, the 7th beat has the control information DATA_REG2 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (63 downto 32) <= (others => '0'); Elsif (counter (6) = '1') then data_concat (63 downto 32) <= m_axis_mm2s_tdata; end if; end if; end process DATA_REG2; end generate DMA_REG2; CDMA_REG2 : if C_ENABLE_CDMA = 1 generate begin -- For CDMA, the 5th beat has the DA information DATA_REG2 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (63 downto 32) <= (others => '0'); Elsif (counter (4) = '1') then data_concat (63 downto 32) <= m_axis_mm2s_tdata; end if; end if; end process DATA_REG2; end generate CDMA_REG2; NOFLOP_FOR_QUEUE : if C_SG_CH1_WORDS_TO_FETCH = 8 generate begin -- Last beat is directly concatenated and passed to FIFO -- Masking the CMPLT bit with cyclic_enable data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0); data_concat_valid <= tvalid_new; data_concat_tlast <= tlast_new; end generate NOFLOP_FOR_QUEUE; -- In absence of queuing option the last beat needs to be floped FLOP_FOR_NOQUEUE : if C_SG_CH1_WORDS_TO_FETCH = 13 generate begin NO_FETCH_Q : if C_SG_FTCH_DESC2QUEUE = 0 generate DATA_REG3 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (95 downto 64) <= (others => '0'); Elsif (counter (7) = '1') then data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0); end if; end if; end process DATA_REG3; end generate NO_FETCH_Q; FETCH_Q : if C_SG_FTCH_DESC2QUEUE /= 0 generate DATA_REG3 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (95) <= '0'; Elsif (counter (7) = '1') then data_concat (95) <= m_axis_mm2s_tdata (31) and (not cyclic_enable); end if; end if; end process DATA_REG3; data_concat (94 downto 64) <= (others => '0'); end generate FETCH_Q; DATA_CNTRL : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat_valid <= '0'; data_concat_tlast <= '0'; Else data_concat_valid <= tvalid_new; data_concat_tlast <= tlast_new; end if; end if; end process DATA_CNTRL; end generate FLOP_FOR_NOQUEUE; -- Since the McDMA BD has two more fields to be captured -- following procedures are needed NOMCDMA_FTECH : if C_ENABLE_MULTI_CHANNEL = 0 generate begin data_concat_mcdma <= (others => '0'); end generate NOMCDMA_FTECH; MCDMA_BD_FETCH : if C_ENABLE_MULTI_CHANNEL = 1 generate begin DATA_MCDMA_REG1 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat_mcdma (31 downto 0) <= (others => '0'); Elsif (counter (4) = '1') then data_concat_mcdma (31 downto 0) <= m_axis_mm2s_tdata; end if; end if; end process DATA_MCDMA_REG1; DATA_MCDMA_REG2 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat_mcdma (63 downto 32) <= (others => '0'); Elsif (counter (5) = '1') then data_concat_mcdma (63 downto 32) <= m_axis_mm2s_tdata; end if; end if; end process DATA_MCDMA_REG2; end generate MCDMA_BD_FETCH; --------------------------------------------------------------------------- -- For 32-bit SG addresses then drive zero on msb --------------------------------------------------------------------------- GEN_CURDESC_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin msb_curdesc <= (others => '0'); end generate GEN_CURDESC_32; --------------------------------------------------------------------------- -- For 64-bit SG addresses then capture upper order adder to msb --------------------------------------------------------------------------- GEN_CURDESC_64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin CAPTURE_CURADDR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then msb_curdesc <= (others => '0'); elsif(ftch_cmnd_wr = '1')then msb_curdesc <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto DATAMOVER_CMD_ADDRMSB_BOFST + DATAMOVER_CMD_ADDRLSB_BIT + 1); end if; end if; end process CAPTURE_CURADDR; end generate GEN_CURDESC_64; --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_LSB_NXTPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then nxtdesc_int(31 downto 0) <= (others => '0'); -- On valid and word count at 0 and channel active capture LSB next pointer elsif(m_axis_mm2s_tvalid = '1' and counter (0) = '1')then nxtdesc_int(31 downto 6) <= m_axis_mm2s_tdata (31 downto 6); -- BD addresses are always 16 word 32-bit aligned nxtdesc_int(5 downto 0) <= (others => '0'); end if; end if; end process REG_LSB_NXTPNTR; lsbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1' and counter (0) = '1' --etch_word_count = WORD_ZERO else '0'; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_NXTPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then nxtdesc_int(63 downto 32) <= (others => '0'); ch1_nxtdesc_wren <= '0'; ch2_nxtdesc_wren <= '0'; -- Capture upper pointer, drive ready to progress DataMover -- and also write nxtdesc out elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then nxtdesc_int(63 downto 32) <= m_axis_mm2s_tdata; ch1_nxtdesc_wren <= ch1_ftch_active; ch2_nxtdesc_wren <= ch2_ftch_active; -- Assert tready/wren for only 1 clock else ch1_nxtdesc_wren <= '0'; ch2_nxtdesc_wren <= '0'; end if; end if; end process REG_MSB_NXTPNTR; msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1' and counter (1) = '1' --fetch_word_count = WORD_ONE else '0'; end generate GEN_UPPER_MSB_NXTDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_NXTPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then ch1_nxtdesc_wren <= '0'; ch2_nxtdesc_wren <= '0'; -- Throw away second word but drive ready to progress DataMover -- and also write nxtdesc out elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then --fetch_word_count = WORD_ONE)then ch1_nxtdesc_wren <= ch1_ftch_active; ch2_nxtdesc_wren <= ch2_ftch_active; -- Assert for only 1 clock else ch1_nxtdesc_wren <= '0'; ch2_nxtdesc_wren <= '0'; end if; end if; end process REG_MSB_NXTPNTR; msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1' and counter (1) = '1' --fetch_word_count = WORD_ONE else '0'; end generate GEN_NO_UPR_MSB_NXTDESC; -- Drive ready to DataMover for ether lsb or msb capture nxtdesc_tready <= msbnxtdesc_tready or lsbnxtdesc_tready; -- Generate logic for checking stale descriptor GEN_STALE_DESC_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 or C_SG_CH2_ENBL_STALE_ERROR = 1 generate begin --------------------------------------------------------------------------- -- Examine Completed BIT to determine if stale descriptor fetched --------------------------------------------------------------------------- CMPLTD_CHECK : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then ftch_stale_desc <= '0'; -- On valid and word count at 0 and channel active capture LSB next pointer elsif(m_axis_mm2s_tvalid = '1' and counter (7) = '1' --fetch_word_count = WORD_SEVEN and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tdata(DESC_STS_CMPLTD_BIT) = '1' )then ftch_stale_desc <= '1' and (not cyclic_enable); else ftch_stale_desc <= '0'; end if; end if; end process CMPLTD_CHECK; end generate GEN_STALE_DESC_CHECK; -- No needed logic for checking stale descriptor GEN_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 and C_SG_CH2_ENBL_STALE_ERROR = 0 generate begin ftch_stale_desc <= '0'; end generate GEN_NO_STALE_CHECK; --------------------------------------------------------------------------- -- SG Queueing therefore pass stream signals to -- FIFO --------------------------------------------------------------------------- GEN_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate begin -- Instantiate the queue version FTCH_QUEUE_I : entity axi_sg_v4_1.axi_sg_ftch_queue generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE , C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH , C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC , C_ASYNC => C_ASYNC , C_FAMILY => C_FAMILY , C_SG2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH , C_INCLUDE_MM2S => C_INCLUDE_CH1, C_INCLUDE_S2MM => C_INCLUDE_CH2, C_ENABLE_CDMA => C_ENABLE_CDMA, C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_primary_aclk => m_axi_mm2s_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , p_reset_n => p_reset_n , ch2_sg_idle => '0' , -- Channel Control desc1_flush => ch1_desc_flush , desc2_flush => ch2_desc_flush , ch1_cntrl_strm_stop => ch1_cntrl_strm_stop , ftch1_active => ch1_ftch_active , ftch2_active => ch2_ftch_active , ftch1_queue_empty => ch1_ftch_queue_empty , ftch2_queue_empty => ch2_ftch_queue_empty , ftch1_queue_full => ch1_ftch_queue_full , ftch2_queue_full => ch2_ftch_queue_full , ftch1_pause => ch1_ftch_pause , ftch2_pause => ch2_ftch_pause , writing_nxtdesc_in => nxtdesc_tready , writing1_curdesc_out => ch1_writing_curdesc , writing2_curdesc_out => ch2_writing_curdesc , -- DataMover Command ftch_cmnd_wr => ftch_cmnd_wr , ftch_cmnd_data => ftch_cmnd_data , -- MM2S Stream In from DataMover m_axis_mm2s_tdata => m_axis_mm2s_tdata , m_axis_mm2s_tlast => m_axis_mm2s_tlast , m_axis_mm2s_tvalid => m_axis_mm2s_tvalid , sof_ftch_desc => sof_ftch_desc , next_bd => nxtdesc_int , data_concat => data_concat, data_concat_mcdma => data_concat_mcdma, data_concat_valid => data_concat_valid, data_concat_tlast => data_concat_tlast, m_axis1_mm2s_tready => ch1_ftch_tready , m_axis2_mm2s_tready => ch2_ftch_tready , -- Channel 1 AXI Fetch Stream Out m_axis_ftch_aclk => m_axi_sg_aclk, --m_axis_ch_ftch_aclk , m_axis_ftch1_tdata => m_axis_ch1_ftch_tdata , m_axis_ftch1_tvalid => m_axis_ch1_ftch_tvalid , m_axis_ftch1_tready => m_axis_ch1_ftch_tready , m_axis_ftch1_tlast => m_axis_ch1_ftch_tlast , m_axis_ftch1_tdata_new => m_axis_ch1_ftch_tdata_new , m_axis_ftch1_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new , m_axis_ftch1_tvalid_new => m_axis_ch1_ftch_tvalid_new , m_axis_ftch1_desc_available => m_axis_ftch1_desc_available , m_axis_ftch2_tdata_new => m_axis_ch2_ftch_tdata_new , m_axis_ftch2_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new , m_axis_ftch2_tvalid_new => m_axis_ch2_ftch_tvalid_new , m_axis_ftch2_desc_available => m_axis_ftch2_desc_available , m_axis_ftch2_tdata => m_axis_ch2_ftch_tdata , m_axis_ftch2_tvalid => m_axis_ch2_ftch_tvalid , m_axis_ftch2_tready => m_axis_ch2_ftch_tready , m_axis_ftch2_tlast => m_axis_ch2_ftch_tlast , m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata , m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep , m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid , m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready , m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ); m_axis_ch2_ftch_tdata_mcdma_nxt <= (others => '0'); end generate GEN_QUEUE; -- No SG Queueing therefore pass stream signals straight -- out channel port GEN_NO_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate begin -- Instantiate the No queue version NO_FTCH_QUEUE_I : entity axi_sg_v4_1.axi_sg_ftch_noqueue generic map ( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH, C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL, C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC , C_ASYNC => C_ASYNC , C_FAMILY => C_FAMILY , C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH , C_ENABLE_CH1 => C_INCLUDE_CH1 ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_primary_aclk => m_axi_mm2s_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , p_reset_n => p_reset_n , -- Channel Control desc_flush => ch1_desc_flush , ch1_cntrl_strm_stop => ch1_cntrl_strm_stop , ftch_active => ch1_ftch_active , ftch_queue_empty => ch1_ftch_queue_empty , ftch_queue_full => ch1_ftch_queue_full , desc2_flush => ch2_desc_flush , ftch2_active => ch2_ftch_active , ftch2_queue_empty => ch2_ftch_queue_empty , ftch2_queue_full => ch2_ftch_queue_full , writing_nxtdesc_in => nxtdesc_tready , writing_curdesc_out => ch1_writing_curdesc , writing2_curdesc_out => ch2_writing_curdesc , -- DataMover Command ftch_cmnd_wr => ftch_cmnd_wr , ftch_cmnd_data => ftch_cmnd_data , -- MM2S Stream In from DataMover m_axis_mm2s_tdata => m_axis_mm2s_tdata , m_axis_mm2s_tlast => m_axis_mm2s_tlast , m_axis_mm2s_tvalid => m_axis_mm2s_tvalid , m_axis_mm2s_tready => ch1_ftch_tready , m_axis2_mm2s_tready => ch2_ftch_tready , sof_ftch_desc => sof_ftch_desc , next_bd => nxtdesc_int , data_concat => data_concat, data_concat_mcdma => data_concat_mcdma, data_concat_valid => data_concat_valid, data_concat_tlast => data_concat_tlast, -- Channel 1 AXI Fetch Stream Out m_axis_ftch_tdata => m_axis_ch1_ftch_tdata , m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid , m_axis_ftch_tready => m_axis_ch1_ftch_tready , m_axis_ftch_tlast => m_axis_ch1_ftch_tlast , m_axis_ftch_tdata_new => m_axis_ch1_ftch_tdata_new , m_axis_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new , m_axis_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new , m_axis_ftch_desc_available => m_axis_ftch1_desc_available , m_axis2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new , m_axis2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new , m_axis2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt , m_axis2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new , m_axis2_ftch_desc_available => m_axis_ftch2_desc_available , m_axis2_ftch_tdata => m_axis_ch2_ftch_tdata , m_axis2_ftch_tvalid => m_axis_ch2_ftch_tvalid , m_axis2_ftch_tready => m_axis_ch2_ftch_tready , m_axis2_ftch_tlast => m_axis_ch2_ftch_tlast , m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata , m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep , m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid , m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready , m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ); ch1_ftch_pause <= '0'; ch2_ftch_pause <= '0'; end generate GEN_NO_QUEUE; ------------------------------------------------------------------------------- -- DataMover TREADY MUX ------------------------------------------------------------------------------- writing_curdesc <= ch1_writing_curdesc or ch2_writing_curdesc or ftch_cmnd_wr; TREADY_MUX : process(writing_curdesc, fetch_word_count, nxtdesc_tready, -- channel 1 signals ch1_ftch_active, ch1_desc_flush, ch1_ftch_tready, -- channel 2 signals ch2_ftch_active, ch2_desc_flush, counter(0), counter(1), ch2_ftch_tready) begin -- If commmanded to flush descriptor then assert ready -- to datamover until active de-asserts. this allows -- any commanded fetches to complete. if( (ch1_desc_flush = '1' and ch1_ftch_active = '1') or(ch2_desc_flush = '1' and ch2_ftch_active = '1'))then m_axis_mm2s_tready_i <= '1'; -- NOT ready if cmnd being written because -- curdesc gets written to queue elsif(writing_curdesc = '1')then m_axis_mm2s_tready_i <= '0'; -- First two words drive ready from internal logic elsif(counter(0) = '1' or counter(1)='1')then m_axis_mm2s_tready_i <= nxtdesc_tready; -- Remainder stream words drive ready from channel input else m_axis_mm2s_tready_i <= (ch1_ftch_active and ch1_ftch_tready) or (ch2_ftch_active and ch2_ftch_tready); end if; end process TREADY_MUX; m_axis_mm2s_tready <= m_axis_mm2s_tready_i; end implementation;
entity test is package a is new b generic map(c => foo(open, open)); end;
library ieee; use ieee.std_logic_1164.all; entity ent is end ent; architecture a of ent is constant c : std_logic_vector(7 downto 0) := x"00"; begin process(all) begin case c is when others => end case; end process; end a;
--===========================================================================-- -- -- -- keyboard.vhd - Synthesizable Interface to PS/2 Keyboard Module -- -- -- --===========================================================================-- -- -- File name : keyboard.vhd -- -- Entity name : keyboard -- -- Purpose : Implements a CPU interface to John Clayton's PS/2 Keyboard -- -- Dependencies : ieee.std_logic_1164 -- ieee.std_logic_arith -- ieee.std_logic_unsigned -- ieee.numeric_std -- -- Uses : ps2_keyboard_interface -- -- Author : John E. Kent -- -- Email : dilbert57@opencores.org -- -- Web : http://opencores.org/project,system09 -- -- Registers : -- -- IO address + 0 read - Status Register -- -- Bit[0] - RX Data Ready -- Bit[1] - TX Data Empty -- Bit[2] - Extended -- Bit[3] - Released -- Bit[4] - Shift On -- Bit[5] - Error (no keyboard acknowledge received) -- Bit[6] - TX Interrupt Flag -- Bit[7] - RX Interrupt Flag -- -- IO address + 0 write - Control Register -- -- Bit[0] - Undefined -- Bit[1] - Undefined -- Bit[2] - Undefined -- Bit[3] - Undefined -- Bit[4] - Undefined -- Bit[5] - Undefined -- Bit[6] - TX Interrupt Enable -- Bit[7] - RX Interrupt Enable -- -- IO address + 1 read - Receive Data Register -- -- IO address + 1 write - Transmit Data Register -- -- Copyright (C) 2004 - 2010 John Kent -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- --===========================================================================-- -- -- -- Revision History -- -- -- --===========================================================================-- -- -- Version Author Date Description -- 0.1 John Kent 2nd April 2004 Interface to John Clayton's PS2 keyboard -- 0.2 John Kent 7th Februaury 2007 Added Generics for Keyboard Timing -- 0.3 John Kent 30th May 2010 Updated Header, added unisim library -- 0.4 John Kent 17th June 2010 Cleaned up signal names, -- added TX interrupt enable -- Modified assignment of status register -- Revised hanshake control and input registers -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; --library unisim; -- use unisim.vcomponents.all; entity keyboard is generic ( KBD_CLK_FREQ : integer ); port( -- -- CPU Interface Signals -- clk : in std_logic; rst : in std_logic; cs : in std_logic; addr : in std_logic; rw : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); irq : out std_logic; -- -- Keyboard Interface Signals -- kbd_clk : inout std_logic; kbd_data : inout std_logic ); end keyboard; architecture rtl of keyboard is constant CLK_FREQ_MHZ : integer := KBD_CLK_FREQ / 1000000; signal kbd_status : std_logic_vector(7 downto 0); signal kbd_control : std_logic_vector(7 downto 0); signal kbd_rx_data : std_logic_vector(7 downto 0); signal kbd_tx_data : std_logic_vector(7 downto 0); signal kbd_read : std_logic; signal kbd_write : std_logic; signal kbd_data_ready : std_logic; -- => kbd_status(0) signal kbd_data_empty : std_logic; -- => kbd_status(1) signal kbd_extended : std_logic; -- => kbd_status(2) signal kbd_released : std_logic; -- => kbd_status(3) signal kbd_shift_on : std_logic; -- => kbd_status(4) signal kbd_error : std_logic; -- => kbd_status(5) (No receive acknowledge) component ps2_keyboard generic ( CLK_FREQ_MHZ : integer := CLK_FREQ_MHZ ); port( clk : in std_logic; reset : in std_logic; rx_data : out std_logic_vector(7 downto 0); rx_read : in std_logic; rx_data_ready : out std_logic; rx_extended : out std_logic; rx_released : out std_logic; rx_shift_on : out std_logic; tx_data : in std_logic_vector(7 downto 0); tx_write : in std_logic; tx_data_empty : out std_logic; tx_error : out std_logic; ps2_clk : inout std_logic; ps2_data : inout std_logic ); end component; begin my_ps2_keyboard : ps2_keyboard generic map ( CLK_FREQ_MHZ => CLK_FREQ_MHz ) port map( clk => clk, reset => rst, rx_data => kbd_rx_data, rx_read => kbd_read, rx_data_ready => kbd_data_ready, rx_extended => kbd_extended, rx_released => kbd_released, rx_shift_on => kbd_shift_on, tx_data => kbd_tx_data, tx_write => kbd_write, tx_data_empty => kbd_data_empty, tx_error => kbd_error, ps2_clk => kbd_clk, ps2_data => kbd_data ); -- -- Keyboard Read strobe -- keyboard_read : process( clk, rst, cs, rw, kbd_data_ready ) begin if rst = '1' then kbd_read <= '0'; elsif( clk'event and clk='0' ) then if( cs = '1' and addr = '1' and rw = '1' ) then kbd_read <= '1'; elsif kbd_data_ready = '1' then kbd_read <= '0'; end if; end if; end process; -- -- Keyboard Write strobe -- keyboard_write : process( clk, rst, cs, rw, addr, kbd_write, kbd_data_empty ) begin if rst = '1' then kbd_write <= '0'; elsif( clk'event and clk='0' ) then if( cs = '1' and addr = '1' and rw = '0' ) then kbd_write <= '1'; elsif kbd_data_empty = '1' then kbd_write <= '0'; end if; end if; end process; -- -- Keyboard register input -- keyboard_in : process( clk, rst, cs, rw, addr, data_in, kbd_rx_data ) begin if rst = '1' then kbd_control <= (others => '0'); kbd_tx_data <= (others => '0'); elsif( clk'event and clk='0' ) then if( cs = '1' and rw = '0' ) then if addr = '0' then kbd_control <= data_in; else kbd_tx_data <= data_in; end if; end if; end if; end process; -- -- Keyboard register output -- keyboard_out : process( addr, kbd_rx_data, kbd_status ) begin if( addr = '0' ) then data_out <= kbd_status; else data_out <= kbd_rx_data; end if; end process; -- -- Assign Keyboard Status bits -- keyboard_status : process( kbd_data_ready, kbd_data_empty, kbd_extended, kbd_released, kbd_shift_on, kbd_error, kbd_control, kbd_status ) begin kbd_status(0) <= kbd_data_ready; kbd_status(1) <= kbd_data_empty; kbd_status(2) <= kbd_extended; kbd_status(3) <= kbd_released; kbd_status(4) <= kbd_shift_on; kbd_status(5) <= kbd_error; kbd_status(6) <= kbd_control(6) and kbd_data_empty; -- TX Interrupt Flag kbd_status(7) <= kbd_control(7) and kbd_data_ready; -- RX Interrupt Flag irq <= kbd_status(7) or kbd_status(6); end process; end rtl;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; ------------------------------------------------------------------------- entity LUTRAM is generic ( B : NATURAL := 8; -- Address Bus width W : NATURAL := 2 -- Data Bus width ); port ( clk : in STD_LOGIC; reset : in STD_LOGIC; wr_en : in STD_LOGIC; w_addr : in STD_LOGIC_VECTOR(W-1 downto 0); r_addr : in STD_LOGIC_VECTOR(W-1 downto 0); w_data : in STD_LOGIC_VECTOR(B-1 downto 0); r_data : out STD_LOGIC_VECTOR(B-1 downto 0) ); end LUTRAM; ------------------------------------------------------------------------- architecture Behavioral of LUTRAM is type REG_FILE_TYPE is array (2**W-1 downto 0) of STD_LOGIC_VECTOR (B-1 downto 0); signal array_reg : REG_FILE_TYPE; begin process(clk) begin if (rising_edge(clk)) then if (wr_en = '1') then array_reg(to_integer(unsigned(w_addr))) <= w_data; end if; end if; end process; r_data <= array_reg(to_integer(unsigned(r_addr))); end Behavioral;
-------------------------------------------------------------------------------- -- company: -- engineer: -- -- vhdl test bench created by ise for module: random_number -- -- dependencies: -- -- revision: -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use IEEE.math_real.all; entity tb_Paint_top is end tb_Paint_top; architecture arch_tb_Paint_top of tb_Paint_top is -- clock period definitions constant clk_period : time := 10 ns; -- 100 MHz component Paint_top is port( ------globally routed signals------- clk100M : in std_logic; btnCpuReset : in std_logic; --=========== Inputs =============== -- ------------ Buttons --------------- -- BTNL : in std_logic; -- BTNR : in std_logic; -- BTNU : in std_logic; -- BTND : in std_logic; -- BTNC : in std_logic; ------------ Switchs --------------- sw0 : in std_logic; sw1 : in std_logic; pdb : in std_logic_vector(7 downto 2); sw : in std_logic_vector(15 downto 8); ------------ Mouse ---------------- --TBC --=========== Outputs ============== --------------- VGA ---------------- vgaRed : out std_logic_vector (3 downto 0); vgaBlue : out std_logic_vector (3 downto 0); vgaGreen : out std_logic_vector (3 downto 0); Hsync : out std_logic; Vsync : out std_logic ); end component Paint_top; --inputs signal Clk : std_logic ; signal reset_n : std_logic ; signal BTNL : std_logic; signal BTNR : std_logic; signal BTNU : std_logic; signal BTND : std_logic; signal BTNC : std_logic; signal sw0 : std_logic; signal sw1 : std_logic; signal vgaRed : std_logic_vector(3 downto 0); signal vgaBlue : std_logic_vector(3 downto 0); signal vgaGreen : std_logic_vector(3 downto 0); signal Hsync : std_logic; signal Vsync : std_logic; begin -- instantiate the unit under test (uut) uut: Paint_top port map( ------globally routed signals------- clk100M => Clk, --: in std_logic; btnCpuReset => reset_n, --: in std_logic; --=========== Inputs =============== -- ------------ Buttons --------------- -- BTNL => BTNL, --: in std_logic; -- BTNR => BTNR, --: in std_logic; -- BTNU => BTNU, --: in std_logic; -- BTND => BTND, --: in std_logic; -- BTNC => BTNC, --: in std_logic; ------------ Switchs --------------- sw0 => sw0,--: in std_logic; sw1 => '1', pdb => (others => '1'), sw => (others => '1'), ------------ Mouse ---------------- --TBC --=========== Outputs ============== --------------- VGA ---------------- vgaRed => vgaRed, --: out std_logic_vector (3 downto 0); vgaBlue => vgaBlue, --: out std_logic_vector (3 downto 0); vgaGreen => vgaGreen,--: out std_logic_vector (3 downto 0); Hsync => Hsync, --: out std_logic; Vsync => Vsync --: out std_logic ); -- clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- reset process reset_proc: process begin reset_n <= '0'; wait for clk_period; reset_n <= '1'; wait; end process; -- Read/write process readn_write_proc: process begin --No action BTNL <= '0'; BTNR <= '0'; BTNU <= '0'; BTND <= '0'; BTNC <= '0'; sw0 <= '0'; wait for 3000*clk_period; wait for 100 ns; end process; end arch_tb_Paint_top;
package uart_constants is constant baud_rate : integer := 115200; end;
library ieee; use ieee.std_logic_1164.all; entity sub is port ( clk : out std_logic; cnt : inout integer ); end entity; architecture test of sub is signal clk_i : bit := '0'; signal clk_std : std_logic; begin clk_i <= not clk_i after 1 ns; clk_std <= to_stdulogic(clk_i); clk <= clk_std; process (clk_std) is begin if rising_edge(clk_std) then cnt <= cnt + 1; end if; end process; end architecture; ------------------------------------------------------------------------------- entity ieee2 is end entity; library ieee; use ieee.std_logic_1164.all; architecture test of ieee2 is signal cnt : integer := 0; signal clk : std_logic; begin sub_i: entity work.sub port map ( clk, cnt ); process (clk) is begin if rising_edge(clk) then report "clock!"; end if; end process; process is begin wait for 10 ns; report integer'image(cnt); assert cnt = 5; wait; end process; end architecture;
library ieee; use ieee.std_logic_1164.all; entity sub is port ( clk : out std_logic; cnt : inout integer ); end entity; architecture test of sub is signal clk_i : bit := '0'; signal clk_std : std_logic; begin clk_i <= not clk_i after 1 ns; clk_std <= to_stdulogic(clk_i); clk <= clk_std; process (clk_std) is begin if rising_edge(clk_std) then cnt <= cnt + 1; end if; end process; end architecture; ------------------------------------------------------------------------------- entity ieee2 is end entity; library ieee; use ieee.std_logic_1164.all; architecture test of ieee2 is signal cnt : integer := 0; signal clk : std_logic; begin sub_i: entity work.sub port map ( clk, cnt ); process (clk) is begin if rising_edge(clk) then report "clock!"; end if; end process; process is begin wait for 10 ns; report integer'image(cnt); assert cnt = 5; wait; end process; end architecture;
library ieee; use ieee.std_logic_1164.all; entity sub is port ( clk : out std_logic; cnt : inout integer ); end entity; architecture test of sub is signal clk_i : bit := '0'; signal clk_std : std_logic; begin clk_i <= not clk_i after 1 ns; clk_std <= to_stdulogic(clk_i); clk <= clk_std; process (clk_std) is begin if rising_edge(clk_std) then cnt <= cnt + 1; end if; end process; end architecture; ------------------------------------------------------------------------------- entity ieee2 is end entity; library ieee; use ieee.std_logic_1164.all; architecture test of ieee2 is signal cnt : integer := 0; signal clk : std_logic; begin sub_i: entity work.sub port map ( clk, cnt ); process (clk) is begin if rising_edge(clk) then report "clock!"; end if; end process; process is begin wait for 10 ns; report integer'image(cnt); assert cnt = 5; wait; end process; end architecture;
library ieee; use ieee.std_logic_1164.all; entity sub is port ( clk : out std_logic; cnt : inout integer ); end entity; architecture test of sub is signal clk_i : bit := '0'; signal clk_std : std_logic; begin clk_i <= not clk_i after 1 ns; clk_std <= to_stdulogic(clk_i); clk <= clk_std; process (clk_std) is begin if rising_edge(clk_std) then cnt <= cnt + 1; end if; end process; end architecture; ------------------------------------------------------------------------------- entity ieee2 is end entity; library ieee; use ieee.std_logic_1164.all; architecture test of ieee2 is signal cnt : integer := 0; signal clk : std_logic; begin sub_i: entity work.sub port map ( clk, cnt ); process (clk) is begin if rising_edge(clk) then report "clock!"; end if; end process; process is begin wait for 10 ns; report integer'image(cnt); assert cnt = 5; wait; end process; end architecture;
------------------------------------------------------------------------------- -- Title : Servo Module ------------------------------------------------------------------------------- -- File : servo_module.vhd -- Author : Fabian <fabian@kleinvieh> -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.bus_pkg.all; package servo_module_pkg is component servo_module is generic ( BASE_ADDRESS : integer range 0 to 16#7FFF#; SERVO_COUNT : positive); port ( servo_p : out std_logic_vector(SERVO_COUNT-1 downto 0); bus_o : out busdevice_out_type; bus_i : in busdevice_in_type; clk : in std_logic); end component servo_module; end package servo_module_pkg; ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.bus_pkg.all; use work.utils_pkg.all; use work.servo_sequencer_pkg.all; use work.servo_channel_pkg.all; entity servo_module is generic ( BASE_ADDRESS : integer range 0 to 16#7FFF#; SERVO_COUNT : positive -- Number of conntected servos ); port ( servo_p : out std_logic_vector(SERVO_COUNT-1 downto 0); bus_o : out busdevice_out_type; bus_i : in busdevice_in_type; clk : in std_logic ); end servo_module; ------------------------------------------------------------------------------- architecture behavioral of servo_module is -- Maximum servo index constant SERVO_MAX : natural := SERVO_COUNT - 1; -- Number of Bits needed to encode the given number of servos constant SERVO_BUS_WIDTH : natural := required_bits(SERVO_MAX); -- Base address converted to a logic vector for easier access. constant BASE_ADDRESS_VECTOR : std_logic_vector(14 downto 0) := std_logic_vector(to_unsigned(BASE_ADDRESS, 15)); subtype servo_value_type is std_logic_vector(15 downto 0); type servo_value_array_type is array (natural range 0 to SERVO_MAX) of servo_value_type; signal counter : std_logic_vector(15 downto 0); -- Servo counter -- Servo channel enable (can be connected to multiple channels) signal enable : std_logic_vector(7 downto 0); signal load : std_logic_vector(7 downto 0); -- Load new compare value type servo_module_type is record servo_value : servo_value_array_type; end record; signal r, rin : servo_module_type := (servo_value => (others => (others => '0'))); begin seq_proc : process(clk) begin if rising_edge(clk) then r <= rin; end if; end process seq_proc; comb_proc : process(bus_i.addr(14 downto SERVO_BUS_WIDTH), bus_i.data, bus_i.addr(SERVO_BUS_WIDTH downto 0), bus_i.we, r) variable index : integer range 0 to 2**SERVO_BUS_WIDTH - 1; variable v : servo_module_type; begin v := r; -- Check Bus Address if bus_i.addr(14 downto SERVO_BUS_WIDTH) = BASE_ADDRESS_VECTOR(14 downto SERVO_BUS_WIDTH) then index := to_integer(unsigned(bus_i.addr(SERVO_BUS_WIDTH downto 0))); if index <= SERVO_MAX then if bus_i.we = '1' then v.servo_value(index) := bus_i.data; --elsif bus_i.re = '1' then -- v.dout := din_p; end if; end if; end if; rin <= v; end process comb_proc; servo_sequencer_1 : servo_sequencer port map ( load_p => load, enable_p => enable, counter_p => counter, reset => '0', clk => clk); servo_channels : for i in 0 to SERVO_MAX generate servo_channel_1 : servo_channel port map ( servo_p => servo_p(i), compare_value_p => r.servo_value(i), load_p => load(i mod 8), enable_p => enable(i mod 8), counter_p => counter, clk => clk); end generate servo_channels; end behavioral;
------------------------------------------------------------------------------- -- Title : Servo Module ------------------------------------------------------------------------------- -- File : servo_module.vhd -- Author : Fabian <fabian@kleinvieh> -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.bus_pkg.all; package servo_module_pkg is component servo_module is generic ( BASE_ADDRESS : integer range 0 to 16#7FFF#; SERVO_COUNT : positive); port ( servo_p : out std_logic_vector(SERVO_COUNT-1 downto 0); bus_o : out busdevice_out_type; bus_i : in busdevice_in_type; clk : in std_logic); end component servo_module; end package servo_module_pkg; ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.bus_pkg.all; use work.utils_pkg.all; use work.servo_sequencer_pkg.all; use work.servo_channel_pkg.all; entity servo_module is generic ( BASE_ADDRESS : integer range 0 to 16#7FFF#; SERVO_COUNT : positive -- Number of conntected servos ); port ( servo_p : out std_logic_vector(SERVO_COUNT-1 downto 0); bus_o : out busdevice_out_type; bus_i : in busdevice_in_type; clk : in std_logic ); end servo_module; ------------------------------------------------------------------------------- architecture behavioral of servo_module is -- Maximum servo index constant SERVO_MAX : natural := SERVO_COUNT - 1; -- Number of Bits needed to encode the given number of servos constant SERVO_BUS_WIDTH : natural := required_bits(SERVO_MAX); -- Base address converted to a logic vector for easier access. constant BASE_ADDRESS_VECTOR : std_logic_vector(14 downto 0) := std_logic_vector(to_unsigned(BASE_ADDRESS, 15)); subtype servo_value_type is std_logic_vector(15 downto 0); type servo_value_array_type is array (natural range 0 to SERVO_MAX) of servo_value_type; signal counter : std_logic_vector(15 downto 0); -- Servo counter -- Servo channel enable (can be connected to multiple channels) signal enable : std_logic_vector(7 downto 0); signal load : std_logic_vector(7 downto 0); -- Load new compare value type servo_module_type is record servo_value : servo_value_array_type; end record; signal r, rin : servo_module_type := (servo_value => (others => (others => '0'))); begin seq_proc : process(clk) begin if rising_edge(clk) then r <= rin; end if; end process seq_proc; comb_proc : process(bus_i.addr(14 downto SERVO_BUS_WIDTH), bus_i.data, bus_i.addr(SERVO_BUS_WIDTH downto 0), bus_i.we, r) variable index : integer range 0 to 2**SERVO_BUS_WIDTH - 1; variable v : servo_module_type; begin v := r; -- Check Bus Address if bus_i.addr(14 downto SERVO_BUS_WIDTH) = BASE_ADDRESS_VECTOR(14 downto SERVO_BUS_WIDTH) then index := to_integer(unsigned(bus_i.addr(SERVO_BUS_WIDTH downto 0))); if index <= SERVO_MAX then if bus_i.we = '1' then v.servo_value(index) := bus_i.data; --elsif bus_i.re = '1' then -- v.dout := din_p; end if; end if; end if; rin <= v; end process comb_proc; servo_sequencer_1 : servo_sequencer port map ( load_p => load, enable_p => enable, counter_p => counter, reset => '0', clk => clk); servo_channels : for i in 0 to SERVO_MAX generate servo_channel_1 : servo_channel port map ( servo_p => servo_p(i), compare_value_p => r.servo_value(i), load_p => load(i mod 8), enable_p => enable(i mod 8), counter_p => counter, clk => clk); end generate servo_channels; end behavioral;
--------------------------------------------------------------------- ---- 4digit.vhdl ---- ---- ---- ---- Drives 4-digit seven segment display. ---- ck should be 100Hz to 1KHz ---- --------------------------------------------------------------------- ---- This program is free software: you can redistribute it ---- ---- and/or modify it under the terms of the GNU Lesser General ---- ---- Public License as published by the Free Software ---- ---- Foundation, either version 3 of the License, or (at your ---- ---- option) any later version. ---- --------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity leds_4 is port(thousands, hundreds, tens, ones: in STD_LOGIC_VECTOR(3 downto 0); ck: in STD_LOGIC; seven: out STD_LOGIC_VECTOR(7 downto 1); anodes: out STD_LOGIC_VECTOR(3 downto 0)); end entity leds_4; architecture behavioral of leds_4 is component bcd_seven is port(bcd: in STD_LOGIC_VECTOR(3 downto 0); seven: out STD_LOGIC_VECTOR(7 downto 1)); ---MSB is segment a, LSB is g end component bcd_seven; type anodes_array is array (3 downto 0) of STD_LOGIC_VECTOR(3 downto 0); constant anode_select: anodes_array := ("0111", "1011", "1101", "1110"); signal anode: integer range 0 to 3 := 0; signal number: STD_LOGIC_VECTOR(3 downto 0); begin seven_segment: bcd_seven port map(number, seven); anodes <= anode_select(anode); process (ck) begin if rising_edge(ck) then case anode is when 0 => anode <= 1; number <= tens; when 1 => anode <= 2; number <= hundreds; when 2 => anode <= 3; number <= thousands; when 3 => anode <= 0; number <= ones; end case; end if; end process; end architecture behavioral;
------------------------------------------------------------------------------- -- lite_ecc_reg.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: lite_ecc_reg.vhd -- -- Description: This module contains the register components for the -- ECC status & control data when enabled. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/17/2011 v1.03a -- ~~~~~~ -- Add ECC support for 128-bit BRAM data width. -- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and -- modify BRAM address registers. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_lite_if; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity lite_ecc_reg is generic ( C_S_AXI_PROTOCOL : string := "AXI4"; -- Used in this module to differentiate timing for error capture C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : INTEGER := 1; -- Enable single port usage of BRAM C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Clock and Reset S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- *** AXI-Lite ECC Register Interface Signals *** -- All synchronized to S_AXI_CTRL_AClk -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- *** Memory Controller Interface Signals *** -- All synchronized to S_AXI_AClk Enable_ECC : out std_logic; -- Indicates if and when ECC is enabled FaultInjectClr : in std_logic; -- Clear for Fault Inject Registers CE_Failing_We : in std_logic; -- WE for CE Failing Registers -- UE_Failing_We : in std_logic; -- WE for CE Failing Registers CE_CounterReg_Inc : in std_logic; -- Increment CE Counter Register Sl_CE : in std_logic; -- Correctable Error Flag Sl_UE : in std_logic; -- Uncorrectable Error Flag BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_En : in std_logic; Active_Wr : in std_logic; -- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- Outputs FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1) ); end entity lite_ecc_reg; ------------------------------------------------------------------------------- architecture implementation of lite_ecc_reg is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Start LMB BRAM v3.00a HDL constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1; constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1; constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1; constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1; constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1; constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0; -- Register accesses -- Register addresses use word address, i.e 2 LSB don't care -- Don't decode MSB, i.e. mirrorring of registers in address space of module constant C_REGADDR_WIDTH : integer := 8; constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00 constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01 constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10 constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11 constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00 constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01 constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10 constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11 constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00 constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00 constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01 constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00 constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01 constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10 constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11 constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00 constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00 constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00 constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00 constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01 constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10 constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11 constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00 -- ECC Status register bit positions constant C_ECC_STATUS_CE : natural := 30; constant C_ECC_STATUS_UE : natural := 31; constant C_ECC_STATUS_WIDTH : natural := 2; constant C_ECC_ENABLE_IRQ_CE : natural := 30; constant C_ECC_ENABLE_IRQ_UE : natural := 31; constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2; constant C_ECC_ON_OFF_WIDTH : natural := 1; -- End LMB BRAM v3.00a HDL constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0'); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal S_AXI_AReset : std_logic; -- Start LMB BRAM v3.00a HDL -- Read and write data to internal registers constant C_DWIDTH : integer := 32; signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegWr : std_logic; signal RegWr_i : std_logic; --signal RegWr_d1 : std_logic; --signal RegWr_d2 : std_logic; -- Fault Inject Register signal FaultInjectData_WE_0 : std_logic := '0'; signal FaultInjectData_WE_1 : std_logic := '0'; signal FaultInjectData_WE_2 : std_logic := '0'; signal FaultInjectData_WE_3 : std_logic := '0'; signal FaultInjectECC_WE : std_logic := '0'; --signal FaultInjectClr : std_logic := '0'; -- Correctable Error First Failing Register signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0'); signal CE_Failing_We_i : std_logic := '0'; -- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- Uncorrectable Error First Failing Register -- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0'); -- signal UE_Failing_We_i : std_logic := '0'; -- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0'); -- ECC Status and Control register signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg_WE : std_logic := '0'; -- ECC On/Off Control register signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0'); signal ECC_OnOffReg_WE : std_logic := '0'; -- Correctable Error Counter signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0'); signal CE_CounterReg_WE : std_logic := '0'; signal CE_CounterReg_Inc_i : std_logic := '0'; -- End LMB BRAM v3.00a HDL signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0'); signal Enable_ECC_i : std_logic := '0'; signal ECC_UE_i : std_logic := '0'; signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin FaultInjectData <= FaultInjectData_i; FaultInjectECC <= FaultInjectECC_i; -- Reserve for future support. -- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn); S_AXI_AReset <= not (S_AXI_AResetn); --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- -- Description: -- This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. -- -- Synchronized to AXI-Lite clock and reset. -- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to -- the AXI clock. -- --------------------------------------------------------------------------- I_AXI_LITE_IF : entity work.axi_lite_if generic map( C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH, C_REGADDR_WIDTH => C_REGADDR_WIDTH, C_DWIDTH => C_DWIDTH ) port map ( -- Reserve for future support. -- LMB_Clk => S_AXI_CTRL_AClk, -- LMB_Rst => S_AXI_CTRL_AReset, LMB_Clk => S_AXI_AClk, LMB_Rst => S_AXI_AReset, S_AXI_AWADDR => AXI_CTRL_AWADDR, S_AXI_AWVALID => AXI_CTRL_AWVALID, S_AXI_AWREADY => AXI_CTRL_AWREADY, S_AXI_WDATA => AXI_CTRL_WDATA, S_AXI_WSTRB => axi_lite_wstrb_int, S_AXI_WVALID => AXI_CTRL_WVALID, S_AXI_WREADY => AXI_CTRL_WREADY, S_AXI_BRESP => AXI_CTRL_BRESP, S_AXI_BVALID => AXI_CTRL_BVALID, S_AXI_BREADY => AXI_CTRL_BREADY, S_AXI_ARADDR => AXI_CTRL_ARADDR, S_AXI_ARVALID => AXI_CTRL_ARVALID, S_AXI_ARREADY => AXI_CTRL_ARREADY, S_AXI_RDATA => AXI_CTRL_RDATA, S_AXI_RRESP => AXI_CTRL_RRESP, S_AXI_RVALID => AXI_CTRL_RVALID, S_AXI_RREADY => AXI_CTRL_RREADY, RegWr => RegWr_i, RegWrData => RegWrData_i, RegAddr => RegAddr_i, RegRdData => RegRdData_i ); -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- -- Save HDL -- If it is decided to go back and use seperate clock inputs -- One for AXI4 and one for AXI4-Lite on this core. -- For now, temporarily comment out and replace the *_i signal -- assignments. RegWr <= RegWr_i; RegWrData <= RegWrData_i; RegAddr <= RegAddr_i; RegRdData_i <= RegRdData; -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- -- -- All registers must be synchronized to the correct clock. -- -- RegWr must be synchronized to the S_AXI_Clk -- -- RegWrData must be synchronized to the S_AXI_Clk -- -- RegAddr must be synchronized to the S_AXI_Clk -- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk -- -- -- --------------------------------------------------------------------------- -- -- SYNC_AXI_CLK: process (S_AXI_AClk) -- begin -- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- RegWr_d1 <= RegWr_i; -- RegWr_d2 <= RegWr_d1; -- RegWrData_d1 <= RegWrData_i; -- RegWrData_d2 <= RegWrData_d1; -- RegAddr_d1 <= RegAddr_i; -- RegAddr_d2 <= RegAddr_d1; -- end if; -- end process SYNC_AXI_CLK; -- -- RegWr <= RegWr_d2; -- RegWrData <= RegWrData_d2; -- RegAddr <= RegAddr_d2; -- -- -- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk) -- begin -- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then -- RegRdData_d1 <= RegRdData; -- RegRdData_d2 <= RegRdData_d1; -- end if; -- end process SYNC_AXI_LITE_CLK; -- -- RegRdData_i <= RegRdData_d2; -- --------------------------------------------------------------------------- axi_lite_wstrb_int <= (others => '1'); --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_SNG -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If single port, only register Port A address. -- -- With CE flag being registered, must account for one more -- pipeline stage in stored BRAM addresss that correlates to -- failing ECC. --------------------------------------------------------------------------- GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate -- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_A_d2 <= BRAM_Addr_A_d1; BRAM_Addr_A_d3 <= BRAM_Addr_A_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_A_d2 <= BRAM_Addr_A_d2; BRAM_Addr_A_d3 <= BRAM_Addr_A_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time. end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline). -- During read operaitons, use 3-deep address pipeline to store address values. FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_SNG; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_DUAL -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If dual port BRAM, register Port A & Port B address. -- -- Account for CE flag register delay, add 3rd BRAM address -- pipeline stage. -- --------------------------------------------------------------------------- GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate -- Port B pipeline stages only used in a dual port mode configuration. signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_B_d1 <= BRAM_Addr_B; BRAM_Addr_B_d2 <= BRAM_Addr_B_d1; BRAM_Addr_B_d3 <= BRAM_Addr_B_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_B_d1 <= BRAM_Addr_B_d1; BRAM_Addr_B_d2 <= BRAM_Addr_B_d2; BRAM_Addr_B_d3 <= BRAM_Addr_B_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin -- Only one active operation at a time. -- Use one deep address pipeline. Determine if Port A or B based on active read or write. FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A). -- During read operations, use 3-deep address pipeline to store address values (and from Port B). FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_DUAL; --------------------------------------------------------------------------- -- Generate: FAULT_INJECT -- Purpose: Implement fault injection registers -- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB) --------------------------------------------------------------------------- FAULT_INJECT : if C_HAS_FAULT_INJECT generate begin -- FaultInjectClr added to top level port list. -- Original LMB BRAM HDL -- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0'; --------------------------------------------------------------------------- -- Generate: GEN_32_FAULT -- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 32-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (25:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_32_FAULT; --------------------------------------------------------------------------- -- Generate: GEN_64_FAULT -- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 64-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (24:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_64_FAULT; -- v1.03a --------------------------------------------------------------------------- -- Generate: GEN_128_FAULT -- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0'; FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 128-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (96 to 127) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (64 to 95) <= RegWrData; elsif FaultInjectData_WE_2 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_3 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_128_FAULT; end generate FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: NO_FAULT_INJECT -- Purpose: Set default outputs when no fault inject capabilities. -- Remove check from C_WRITE_ACCESS (from LMB) --------------------------------------------------------------------------- NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate begin FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end generate NO_FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: CE_FAILING_REGISTERS -- Purpose: Implement Correctable Error First Failing Register --------------------------------------------------------------------------- CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate begin -- TBD (could come from axi_lite) -- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') -- else '0'; CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') else '0'; CE_FailingReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then CE_FailingAddress <= (others => '0'); -- Reserve for future support. -- CE_FailingData <= (others => '0'); elsif CE_Failing_We_i = '1' then --As the AXI Addr Width can now be lesser than 32, the address is getting shifted --Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000 CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0); --CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ; -- Reserve for future support. -- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1); end if; end if; end process CE_FailingReg; -- Note: Remove storage of CE_FFE & CE_FFD registers. -- Here for future support. -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_64; end generate CE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_CE_FAILING_REGISTERS -- Purpose: No Correctable Error Failing registers. --------------------------------------------------------------------------- NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate begin CE_FailingAddress <= (others => '0'); -- CE_FailingData <= (others => '0'); -- CE_FailingECC <= (others => '0'); end generate NO_CE_FAILING_REGISTERS; -- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0 -- This generate clause will never be evaluated. -- Here for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: UE_FAILING_REGISTERS -- -- Purpose: Implement Unorrectable Error First Failing Register -- --------------------------------------------------------------------------- -- -- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate -- begin -- -- -- TBD (could come from axi_lite) -- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- -- else '0'; -- -- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- else '0'; -- -- -- UE_FailingReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingAddress <= FailingAddr_Ld; -- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1); -- end if; -- end if; -- end process UE_FailingReg; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_64; -- -- end generate UE_FAILING_REGISTERS; -- -- -- --------------------------------------------------------------------------- -- -- Generate: NO_UE_FAILING_REGISTERS -- -- Purpose: No Uncorrectable Error Failing registers. -- --------------------------------------------------------------------------- -- -- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate -- begin -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- UE_FailingECC <= (others => '0'); -- end generate NO_UE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: ECC_STATUS_REGISTERS -- Purpose: Enable ECC status and interrupt enable registers. --------------------------------------------------------------------------- ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate begin ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE; ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE; StatusReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_StatusReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then -- CE Interrupt status bit if RegWrData(C_ECC_STATUS_CE) = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1' end if; -- UE Interrupt status bit if RegWrData(C_ECC_STATUS_UE) = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1' end if; else if Sl_CE = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs end if; if Sl_UE = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs end if; end if; end if; end process StatusReg; ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_EnableIRQReg <= (others => '0'); elsif ECC_EnableIRQReg_WE = '1' then -- CE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE); -- UE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE); end if; end if; end process EnableIRQReg; Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or (ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE)); --------------------------------------------------------------------------- -- Generate output flag for UE sticky bit -- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted. REG_UE : process (S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE or (Enable_ECC_i = '0') then ECC_UE_i <= '0'; elsif Sl_UE = '1' then ECC_UE_i <= '1'; elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then ECC_UE_i <= '0'; else ECC_UE_i <= ECC_UE_i; end if; end if; end process REG_UE; ECC_UE <= ECC_UE_i; --------------------------------------------------------------------------- end generate ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_ECC_STATUS_REGISTERS -- Purpose: No ECC status or interrupt registers enabled. --------------------------------------------------------------------------- NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate begin ECC_EnableIRQReg <= (others => '0'); ECC_StatusReg <= (others => '0'); Interrupt <= '0'; ECC_UE <= '0'; end generate NO_ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: GEN_ECC_ONOFF -- Purpose: Implement ECC on/off control register. --------------------------------------------------------------------------- GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate begin ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then if (C_ECC_ONOFF_RESET_VALUE = 0) then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; else ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1'; end if; -- ECC on by default at reset (but can be disabled) elsif ECC_OnOffReg_WE = '1' then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH); end if; end if; end process EnableIRQReg; Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH); Enable_ECC <= Enable_ECC_i; end generate GEN_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC_ONOFF -- Purpose: No ECC on/off control register. --------------------------------------------------------------------------- GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate begin Enable_ECC <= '0'; -- ECC ON/OFF register is only enabled when C_ECC = 1. -- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then -- ECC should be disabled. ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; end generate GEN_NO_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: CE_COUNTER -- Purpose: Enable Correctable Error Counter -- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits. -- Parameterized here for future enhancements. --------------------------------------------------------------------------- CE_COUNTER : if C_HAS_CE_COUNTER generate -- One extra bit compare to CE_CounterReg to handle carry bit signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31); begin CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0'; -- TBD (could come from axi_lite) -- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and -- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') -- else '0'; CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') else '0'; CountReg : process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then CE_CounterReg <= (others => '0'); elsif CE_CounterReg_WE = '1' then -- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1); CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31); elsif CE_CounterReg_Inc_i = '1' then CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31); end if; end if; end process CountReg; CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1); end generate CE_COUNTER; -- Note: Hit this generate when C_ECC = 0. -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: NO_CE_COUNTER -- -- Purpose: Default for no CE counter register. -- --------------------------------------------------------------------------- -- -- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate -- begin -- CE_CounterReg <= (others => '0'); -- end generate NO_CE_COUNTER; --------------------------------------------------------------------------- -- Generate: GEN_REG_32_DATA -- Purpose: Generate read register values & signal assignments based on -- 32-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress; when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_32_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_64_DATA -- Purpose: Generate read register values & signal assignments based on -- 64-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_64_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_128_DATA -- Purpose: Generate read register values & signal assignments based on -- 128-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95); when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_128_DATA; --------------------------------------------------------------------------- end architecture implementation;
------------------------------------------------------------------------------- -- lite_ecc_reg.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: lite_ecc_reg.vhd -- -- Description: This module contains the register components for the -- ECC status & control data when enabled. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/17/2011 v1.03a -- ~~~~~~ -- Add ECC support for 128-bit BRAM data width. -- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and -- modify BRAM address registers. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_lite_if; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity lite_ecc_reg is generic ( C_S_AXI_PROTOCOL : string := "AXI4"; -- Used in this module to differentiate timing for error capture C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : INTEGER := 1; -- Enable single port usage of BRAM C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Clock and Reset S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- *** AXI-Lite ECC Register Interface Signals *** -- All synchronized to S_AXI_CTRL_AClk -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- *** Memory Controller Interface Signals *** -- All synchronized to S_AXI_AClk Enable_ECC : out std_logic; -- Indicates if and when ECC is enabled FaultInjectClr : in std_logic; -- Clear for Fault Inject Registers CE_Failing_We : in std_logic; -- WE for CE Failing Registers -- UE_Failing_We : in std_logic; -- WE for CE Failing Registers CE_CounterReg_Inc : in std_logic; -- Increment CE Counter Register Sl_CE : in std_logic; -- Correctable Error Flag Sl_UE : in std_logic; -- Uncorrectable Error Flag BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_En : in std_logic; Active_Wr : in std_logic; -- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- Outputs FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1) ); end entity lite_ecc_reg; ------------------------------------------------------------------------------- architecture implementation of lite_ecc_reg is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Start LMB BRAM v3.00a HDL constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1; constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1; constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1; constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1; constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1; constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0; -- Register accesses -- Register addresses use word address, i.e 2 LSB don't care -- Don't decode MSB, i.e. mirrorring of registers in address space of module constant C_REGADDR_WIDTH : integer := 8; constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00 constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01 constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10 constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11 constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00 constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01 constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10 constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11 constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00 constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00 constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01 constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00 constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01 constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10 constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11 constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00 constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00 constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00 constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00 constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01 constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10 constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11 constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00 -- ECC Status register bit positions constant C_ECC_STATUS_CE : natural := 30; constant C_ECC_STATUS_UE : natural := 31; constant C_ECC_STATUS_WIDTH : natural := 2; constant C_ECC_ENABLE_IRQ_CE : natural := 30; constant C_ECC_ENABLE_IRQ_UE : natural := 31; constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2; constant C_ECC_ON_OFF_WIDTH : natural := 1; -- End LMB BRAM v3.00a HDL constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0'); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal S_AXI_AReset : std_logic; -- Start LMB BRAM v3.00a HDL -- Read and write data to internal registers constant C_DWIDTH : integer := 32; signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegWr : std_logic; signal RegWr_i : std_logic; --signal RegWr_d1 : std_logic; --signal RegWr_d2 : std_logic; -- Fault Inject Register signal FaultInjectData_WE_0 : std_logic := '0'; signal FaultInjectData_WE_1 : std_logic := '0'; signal FaultInjectData_WE_2 : std_logic := '0'; signal FaultInjectData_WE_3 : std_logic := '0'; signal FaultInjectECC_WE : std_logic := '0'; --signal FaultInjectClr : std_logic := '0'; -- Correctable Error First Failing Register signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0'); signal CE_Failing_We_i : std_logic := '0'; -- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- Uncorrectable Error First Failing Register -- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0'); -- signal UE_Failing_We_i : std_logic := '0'; -- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0'); -- ECC Status and Control register signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg_WE : std_logic := '0'; -- ECC On/Off Control register signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0'); signal ECC_OnOffReg_WE : std_logic := '0'; -- Correctable Error Counter signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0'); signal CE_CounterReg_WE : std_logic := '0'; signal CE_CounterReg_Inc_i : std_logic := '0'; -- End LMB BRAM v3.00a HDL signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0'); signal Enable_ECC_i : std_logic := '0'; signal ECC_UE_i : std_logic := '0'; signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin FaultInjectData <= FaultInjectData_i; FaultInjectECC <= FaultInjectECC_i; -- Reserve for future support. -- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn); S_AXI_AReset <= not (S_AXI_AResetn); --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- -- Description: -- This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. -- -- Synchronized to AXI-Lite clock and reset. -- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to -- the AXI clock. -- --------------------------------------------------------------------------- I_AXI_LITE_IF : entity work.axi_lite_if generic map( C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH, C_REGADDR_WIDTH => C_REGADDR_WIDTH, C_DWIDTH => C_DWIDTH ) port map ( -- Reserve for future support. -- LMB_Clk => S_AXI_CTRL_AClk, -- LMB_Rst => S_AXI_CTRL_AReset, LMB_Clk => S_AXI_AClk, LMB_Rst => S_AXI_AReset, S_AXI_AWADDR => AXI_CTRL_AWADDR, S_AXI_AWVALID => AXI_CTRL_AWVALID, S_AXI_AWREADY => AXI_CTRL_AWREADY, S_AXI_WDATA => AXI_CTRL_WDATA, S_AXI_WSTRB => axi_lite_wstrb_int, S_AXI_WVALID => AXI_CTRL_WVALID, S_AXI_WREADY => AXI_CTRL_WREADY, S_AXI_BRESP => AXI_CTRL_BRESP, S_AXI_BVALID => AXI_CTRL_BVALID, S_AXI_BREADY => AXI_CTRL_BREADY, S_AXI_ARADDR => AXI_CTRL_ARADDR, S_AXI_ARVALID => AXI_CTRL_ARVALID, S_AXI_ARREADY => AXI_CTRL_ARREADY, S_AXI_RDATA => AXI_CTRL_RDATA, S_AXI_RRESP => AXI_CTRL_RRESP, S_AXI_RVALID => AXI_CTRL_RVALID, S_AXI_RREADY => AXI_CTRL_RREADY, RegWr => RegWr_i, RegWrData => RegWrData_i, RegAddr => RegAddr_i, RegRdData => RegRdData_i ); -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- -- Save HDL -- If it is decided to go back and use seperate clock inputs -- One for AXI4 and one for AXI4-Lite on this core. -- For now, temporarily comment out and replace the *_i signal -- assignments. RegWr <= RegWr_i; RegWrData <= RegWrData_i; RegAddr <= RegAddr_i; RegRdData_i <= RegRdData; -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- -- -- All registers must be synchronized to the correct clock. -- -- RegWr must be synchronized to the S_AXI_Clk -- -- RegWrData must be synchronized to the S_AXI_Clk -- -- RegAddr must be synchronized to the S_AXI_Clk -- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk -- -- -- --------------------------------------------------------------------------- -- -- SYNC_AXI_CLK: process (S_AXI_AClk) -- begin -- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- RegWr_d1 <= RegWr_i; -- RegWr_d2 <= RegWr_d1; -- RegWrData_d1 <= RegWrData_i; -- RegWrData_d2 <= RegWrData_d1; -- RegAddr_d1 <= RegAddr_i; -- RegAddr_d2 <= RegAddr_d1; -- end if; -- end process SYNC_AXI_CLK; -- -- RegWr <= RegWr_d2; -- RegWrData <= RegWrData_d2; -- RegAddr <= RegAddr_d2; -- -- -- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk) -- begin -- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then -- RegRdData_d1 <= RegRdData; -- RegRdData_d2 <= RegRdData_d1; -- end if; -- end process SYNC_AXI_LITE_CLK; -- -- RegRdData_i <= RegRdData_d2; -- --------------------------------------------------------------------------- axi_lite_wstrb_int <= (others => '1'); --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_SNG -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If single port, only register Port A address. -- -- With CE flag being registered, must account for one more -- pipeline stage in stored BRAM addresss that correlates to -- failing ECC. --------------------------------------------------------------------------- GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate -- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_A_d2 <= BRAM_Addr_A_d1; BRAM_Addr_A_d3 <= BRAM_Addr_A_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_A_d2 <= BRAM_Addr_A_d2; BRAM_Addr_A_d3 <= BRAM_Addr_A_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time. end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline). -- During read operaitons, use 3-deep address pipeline to store address values. FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_SNG; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_DUAL -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If dual port BRAM, register Port A & Port B address. -- -- Account for CE flag register delay, add 3rd BRAM address -- pipeline stage. -- --------------------------------------------------------------------------- GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate -- Port B pipeline stages only used in a dual port mode configuration. signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_B_d1 <= BRAM_Addr_B; BRAM_Addr_B_d2 <= BRAM_Addr_B_d1; BRAM_Addr_B_d3 <= BRAM_Addr_B_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_B_d1 <= BRAM_Addr_B_d1; BRAM_Addr_B_d2 <= BRAM_Addr_B_d2; BRAM_Addr_B_d3 <= BRAM_Addr_B_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin -- Only one active operation at a time. -- Use one deep address pipeline. Determine if Port A or B based on active read or write. FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A). -- During read operations, use 3-deep address pipeline to store address values (and from Port B). FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_DUAL; --------------------------------------------------------------------------- -- Generate: FAULT_INJECT -- Purpose: Implement fault injection registers -- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB) --------------------------------------------------------------------------- FAULT_INJECT : if C_HAS_FAULT_INJECT generate begin -- FaultInjectClr added to top level port list. -- Original LMB BRAM HDL -- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0'; --------------------------------------------------------------------------- -- Generate: GEN_32_FAULT -- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 32-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (25:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_32_FAULT; --------------------------------------------------------------------------- -- Generate: GEN_64_FAULT -- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 64-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (24:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_64_FAULT; -- v1.03a --------------------------------------------------------------------------- -- Generate: GEN_128_FAULT -- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0'; FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 128-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (96 to 127) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (64 to 95) <= RegWrData; elsif FaultInjectData_WE_2 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_3 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_128_FAULT; end generate FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: NO_FAULT_INJECT -- Purpose: Set default outputs when no fault inject capabilities. -- Remove check from C_WRITE_ACCESS (from LMB) --------------------------------------------------------------------------- NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate begin FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end generate NO_FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: CE_FAILING_REGISTERS -- Purpose: Implement Correctable Error First Failing Register --------------------------------------------------------------------------- CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate begin -- TBD (could come from axi_lite) -- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') -- else '0'; CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') else '0'; CE_FailingReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then CE_FailingAddress <= (others => '0'); -- Reserve for future support. -- CE_FailingData <= (others => '0'); elsif CE_Failing_We_i = '1' then --As the AXI Addr Width can now be lesser than 32, the address is getting shifted --Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000 CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0); --CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ; -- Reserve for future support. -- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1); end if; end if; end process CE_FailingReg; -- Note: Remove storage of CE_FFE & CE_FFD registers. -- Here for future support. -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_64; end generate CE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_CE_FAILING_REGISTERS -- Purpose: No Correctable Error Failing registers. --------------------------------------------------------------------------- NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate begin CE_FailingAddress <= (others => '0'); -- CE_FailingData <= (others => '0'); -- CE_FailingECC <= (others => '0'); end generate NO_CE_FAILING_REGISTERS; -- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0 -- This generate clause will never be evaluated. -- Here for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: UE_FAILING_REGISTERS -- -- Purpose: Implement Unorrectable Error First Failing Register -- --------------------------------------------------------------------------- -- -- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate -- begin -- -- -- TBD (could come from axi_lite) -- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- -- else '0'; -- -- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- else '0'; -- -- -- UE_FailingReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingAddress <= FailingAddr_Ld; -- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1); -- end if; -- end if; -- end process UE_FailingReg; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_64; -- -- end generate UE_FAILING_REGISTERS; -- -- -- --------------------------------------------------------------------------- -- -- Generate: NO_UE_FAILING_REGISTERS -- -- Purpose: No Uncorrectable Error Failing registers. -- --------------------------------------------------------------------------- -- -- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate -- begin -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- UE_FailingECC <= (others => '0'); -- end generate NO_UE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: ECC_STATUS_REGISTERS -- Purpose: Enable ECC status and interrupt enable registers. --------------------------------------------------------------------------- ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate begin ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE; ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE; StatusReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_StatusReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then -- CE Interrupt status bit if RegWrData(C_ECC_STATUS_CE) = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1' end if; -- UE Interrupt status bit if RegWrData(C_ECC_STATUS_UE) = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1' end if; else if Sl_CE = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs end if; if Sl_UE = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs end if; end if; end if; end process StatusReg; ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_EnableIRQReg <= (others => '0'); elsif ECC_EnableIRQReg_WE = '1' then -- CE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE); -- UE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE); end if; end if; end process EnableIRQReg; Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or (ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE)); --------------------------------------------------------------------------- -- Generate output flag for UE sticky bit -- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted. REG_UE : process (S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE or (Enable_ECC_i = '0') then ECC_UE_i <= '0'; elsif Sl_UE = '1' then ECC_UE_i <= '1'; elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then ECC_UE_i <= '0'; else ECC_UE_i <= ECC_UE_i; end if; end if; end process REG_UE; ECC_UE <= ECC_UE_i; --------------------------------------------------------------------------- end generate ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_ECC_STATUS_REGISTERS -- Purpose: No ECC status or interrupt registers enabled. --------------------------------------------------------------------------- NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate begin ECC_EnableIRQReg <= (others => '0'); ECC_StatusReg <= (others => '0'); Interrupt <= '0'; ECC_UE <= '0'; end generate NO_ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: GEN_ECC_ONOFF -- Purpose: Implement ECC on/off control register. --------------------------------------------------------------------------- GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate begin ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then if (C_ECC_ONOFF_RESET_VALUE = 0) then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; else ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1'; end if; -- ECC on by default at reset (but can be disabled) elsif ECC_OnOffReg_WE = '1' then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH); end if; end if; end process EnableIRQReg; Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH); Enable_ECC <= Enable_ECC_i; end generate GEN_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC_ONOFF -- Purpose: No ECC on/off control register. --------------------------------------------------------------------------- GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate begin Enable_ECC <= '0'; -- ECC ON/OFF register is only enabled when C_ECC = 1. -- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then -- ECC should be disabled. ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; end generate GEN_NO_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: CE_COUNTER -- Purpose: Enable Correctable Error Counter -- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits. -- Parameterized here for future enhancements. --------------------------------------------------------------------------- CE_COUNTER : if C_HAS_CE_COUNTER generate -- One extra bit compare to CE_CounterReg to handle carry bit signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31); begin CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0'; -- TBD (could come from axi_lite) -- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and -- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') -- else '0'; CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') else '0'; CountReg : process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then CE_CounterReg <= (others => '0'); elsif CE_CounterReg_WE = '1' then -- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1); CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31); elsif CE_CounterReg_Inc_i = '1' then CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31); end if; end if; end process CountReg; CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1); end generate CE_COUNTER; -- Note: Hit this generate when C_ECC = 0. -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: NO_CE_COUNTER -- -- Purpose: Default for no CE counter register. -- --------------------------------------------------------------------------- -- -- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate -- begin -- CE_CounterReg <= (others => '0'); -- end generate NO_CE_COUNTER; --------------------------------------------------------------------------- -- Generate: GEN_REG_32_DATA -- Purpose: Generate read register values & signal assignments based on -- 32-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress; when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_32_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_64_DATA -- Purpose: Generate read register values & signal assignments based on -- 64-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_64_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_128_DATA -- Purpose: Generate read register values & signal assignments based on -- 128-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95); when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_128_DATA; --------------------------------------------------------------------------- end architecture implementation;
------------------------------------------------------------------------------- -- lite_ecc_reg.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: lite_ecc_reg.vhd -- -- Description: This module contains the register components for the -- ECC status & control data when enabled. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/17/2011 v1.03a -- ~~~~~~ -- Add ECC support for 128-bit BRAM data width. -- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and -- modify BRAM address registers. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_lite_if; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity lite_ecc_reg is generic ( C_S_AXI_PROTOCOL : string := "AXI4"; -- Used in this module to differentiate timing for error capture C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : INTEGER := 1; -- Enable single port usage of BRAM C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Clock and Reset S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- *** AXI-Lite ECC Register Interface Signals *** -- All synchronized to S_AXI_CTRL_AClk -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- *** Memory Controller Interface Signals *** -- All synchronized to S_AXI_AClk Enable_ECC : out std_logic; -- Indicates if and when ECC is enabled FaultInjectClr : in std_logic; -- Clear for Fault Inject Registers CE_Failing_We : in std_logic; -- WE for CE Failing Registers -- UE_Failing_We : in std_logic; -- WE for CE Failing Registers CE_CounterReg_Inc : in std_logic; -- Increment CE Counter Register Sl_CE : in std_logic; -- Correctable Error Flag Sl_UE : in std_logic; -- Uncorrectable Error Flag BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_En : in std_logic; Active_Wr : in std_logic; -- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- Outputs FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1) ); end entity lite_ecc_reg; ------------------------------------------------------------------------------- architecture implementation of lite_ecc_reg is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Start LMB BRAM v3.00a HDL constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1; constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1; constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1; constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1; constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1; constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0; -- Register accesses -- Register addresses use word address, i.e 2 LSB don't care -- Don't decode MSB, i.e. mirrorring of registers in address space of module constant C_REGADDR_WIDTH : integer := 8; constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00 constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01 constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10 constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11 constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00 constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01 constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10 constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11 constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00 constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00 constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01 constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00 constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01 constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10 constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11 constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00 constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00 constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00 constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00 constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01 constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10 constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11 constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00 -- ECC Status register bit positions constant C_ECC_STATUS_CE : natural := 30; constant C_ECC_STATUS_UE : natural := 31; constant C_ECC_STATUS_WIDTH : natural := 2; constant C_ECC_ENABLE_IRQ_CE : natural := 30; constant C_ECC_ENABLE_IRQ_UE : natural := 31; constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2; constant C_ECC_ON_OFF_WIDTH : natural := 1; -- End LMB BRAM v3.00a HDL constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0'); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal S_AXI_AReset : std_logic; -- Start LMB BRAM v3.00a HDL -- Read and write data to internal registers constant C_DWIDTH : integer := 32; signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegWr : std_logic; signal RegWr_i : std_logic; --signal RegWr_d1 : std_logic; --signal RegWr_d2 : std_logic; -- Fault Inject Register signal FaultInjectData_WE_0 : std_logic := '0'; signal FaultInjectData_WE_1 : std_logic := '0'; signal FaultInjectData_WE_2 : std_logic := '0'; signal FaultInjectData_WE_3 : std_logic := '0'; signal FaultInjectECC_WE : std_logic := '0'; --signal FaultInjectClr : std_logic := '0'; -- Correctable Error First Failing Register signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0'); signal CE_Failing_We_i : std_logic := '0'; -- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- Uncorrectable Error First Failing Register -- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0'); -- signal UE_Failing_We_i : std_logic := '0'; -- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0'); -- ECC Status and Control register signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg_WE : std_logic := '0'; -- ECC On/Off Control register signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0'); signal ECC_OnOffReg_WE : std_logic := '0'; -- Correctable Error Counter signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0'); signal CE_CounterReg_WE : std_logic := '0'; signal CE_CounterReg_Inc_i : std_logic := '0'; -- End LMB BRAM v3.00a HDL signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0'); signal Enable_ECC_i : std_logic := '0'; signal ECC_UE_i : std_logic := '0'; signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin FaultInjectData <= FaultInjectData_i; FaultInjectECC <= FaultInjectECC_i; -- Reserve for future support. -- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn); S_AXI_AReset <= not (S_AXI_AResetn); --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- -- Description: -- This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. -- -- Synchronized to AXI-Lite clock and reset. -- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to -- the AXI clock. -- --------------------------------------------------------------------------- I_AXI_LITE_IF : entity work.axi_lite_if generic map( C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH, C_REGADDR_WIDTH => C_REGADDR_WIDTH, C_DWIDTH => C_DWIDTH ) port map ( -- Reserve for future support. -- LMB_Clk => S_AXI_CTRL_AClk, -- LMB_Rst => S_AXI_CTRL_AReset, LMB_Clk => S_AXI_AClk, LMB_Rst => S_AXI_AReset, S_AXI_AWADDR => AXI_CTRL_AWADDR, S_AXI_AWVALID => AXI_CTRL_AWVALID, S_AXI_AWREADY => AXI_CTRL_AWREADY, S_AXI_WDATA => AXI_CTRL_WDATA, S_AXI_WSTRB => axi_lite_wstrb_int, S_AXI_WVALID => AXI_CTRL_WVALID, S_AXI_WREADY => AXI_CTRL_WREADY, S_AXI_BRESP => AXI_CTRL_BRESP, S_AXI_BVALID => AXI_CTRL_BVALID, S_AXI_BREADY => AXI_CTRL_BREADY, S_AXI_ARADDR => AXI_CTRL_ARADDR, S_AXI_ARVALID => AXI_CTRL_ARVALID, S_AXI_ARREADY => AXI_CTRL_ARREADY, S_AXI_RDATA => AXI_CTRL_RDATA, S_AXI_RRESP => AXI_CTRL_RRESP, S_AXI_RVALID => AXI_CTRL_RVALID, S_AXI_RREADY => AXI_CTRL_RREADY, RegWr => RegWr_i, RegWrData => RegWrData_i, RegAddr => RegAddr_i, RegRdData => RegRdData_i ); -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- -- Save HDL -- If it is decided to go back and use seperate clock inputs -- One for AXI4 and one for AXI4-Lite on this core. -- For now, temporarily comment out and replace the *_i signal -- assignments. RegWr <= RegWr_i; RegWrData <= RegWrData_i; RegAddr <= RegAddr_i; RegRdData_i <= RegRdData; -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- -- -- All registers must be synchronized to the correct clock. -- -- RegWr must be synchronized to the S_AXI_Clk -- -- RegWrData must be synchronized to the S_AXI_Clk -- -- RegAddr must be synchronized to the S_AXI_Clk -- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk -- -- -- --------------------------------------------------------------------------- -- -- SYNC_AXI_CLK: process (S_AXI_AClk) -- begin -- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- RegWr_d1 <= RegWr_i; -- RegWr_d2 <= RegWr_d1; -- RegWrData_d1 <= RegWrData_i; -- RegWrData_d2 <= RegWrData_d1; -- RegAddr_d1 <= RegAddr_i; -- RegAddr_d2 <= RegAddr_d1; -- end if; -- end process SYNC_AXI_CLK; -- -- RegWr <= RegWr_d2; -- RegWrData <= RegWrData_d2; -- RegAddr <= RegAddr_d2; -- -- -- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk) -- begin -- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then -- RegRdData_d1 <= RegRdData; -- RegRdData_d2 <= RegRdData_d1; -- end if; -- end process SYNC_AXI_LITE_CLK; -- -- RegRdData_i <= RegRdData_d2; -- --------------------------------------------------------------------------- axi_lite_wstrb_int <= (others => '1'); --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_SNG -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If single port, only register Port A address. -- -- With CE flag being registered, must account for one more -- pipeline stage in stored BRAM addresss that correlates to -- failing ECC. --------------------------------------------------------------------------- GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate -- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_A_d2 <= BRAM_Addr_A_d1; BRAM_Addr_A_d3 <= BRAM_Addr_A_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_A_d2 <= BRAM_Addr_A_d2; BRAM_Addr_A_d3 <= BRAM_Addr_A_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time. end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline). -- During read operaitons, use 3-deep address pipeline to store address values. FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_SNG; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_DUAL -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If dual port BRAM, register Port A & Port B address. -- -- Account for CE flag register delay, add 3rd BRAM address -- pipeline stage. -- --------------------------------------------------------------------------- GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate -- Port B pipeline stages only used in a dual port mode configuration. signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_B_d1 <= BRAM_Addr_B; BRAM_Addr_B_d2 <= BRAM_Addr_B_d1; BRAM_Addr_B_d3 <= BRAM_Addr_B_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_B_d1 <= BRAM_Addr_B_d1; BRAM_Addr_B_d2 <= BRAM_Addr_B_d2; BRAM_Addr_B_d3 <= BRAM_Addr_B_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin -- Only one active operation at a time. -- Use one deep address pipeline. Determine if Port A or B based on active read or write. FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A). -- During read operations, use 3-deep address pipeline to store address values (and from Port B). FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_DUAL; --------------------------------------------------------------------------- -- Generate: FAULT_INJECT -- Purpose: Implement fault injection registers -- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB) --------------------------------------------------------------------------- FAULT_INJECT : if C_HAS_FAULT_INJECT generate begin -- FaultInjectClr added to top level port list. -- Original LMB BRAM HDL -- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0'; --------------------------------------------------------------------------- -- Generate: GEN_32_FAULT -- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 32-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (25:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_32_FAULT; --------------------------------------------------------------------------- -- Generate: GEN_64_FAULT -- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 64-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (24:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_64_FAULT; -- v1.03a --------------------------------------------------------------------------- -- Generate: GEN_128_FAULT -- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0'; FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 128-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (96 to 127) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (64 to 95) <= RegWrData; elsif FaultInjectData_WE_2 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_3 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_128_FAULT; end generate FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: NO_FAULT_INJECT -- Purpose: Set default outputs when no fault inject capabilities. -- Remove check from C_WRITE_ACCESS (from LMB) --------------------------------------------------------------------------- NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate begin FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end generate NO_FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: CE_FAILING_REGISTERS -- Purpose: Implement Correctable Error First Failing Register --------------------------------------------------------------------------- CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate begin -- TBD (could come from axi_lite) -- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') -- else '0'; CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') else '0'; CE_FailingReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then CE_FailingAddress <= (others => '0'); -- Reserve for future support. -- CE_FailingData <= (others => '0'); elsif CE_Failing_We_i = '1' then --As the AXI Addr Width can now be lesser than 32, the address is getting shifted --Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000 CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0); --CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ; -- Reserve for future support. -- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1); end if; end if; end process CE_FailingReg; -- Note: Remove storage of CE_FFE & CE_FFD registers. -- Here for future support. -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_64; end generate CE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_CE_FAILING_REGISTERS -- Purpose: No Correctable Error Failing registers. --------------------------------------------------------------------------- NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate begin CE_FailingAddress <= (others => '0'); -- CE_FailingData <= (others => '0'); -- CE_FailingECC <= (others => '0'); end generate NO_CE_FAILING_REGISTERS; -- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0 -- This generate clause will never be evaluated. -- Here for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: UE_FAILING_REGISTERS -- -- Purpose: Implement Unorrectable Error First Failing Register -- --------------------------------------------------------------------------- -- -- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate -- begin -- -- -- TBD (could come from axi_lite) -- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- -- else '0'; -- -- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- else '0'; -- -- -- UE_FailingReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingAddress <= FailingAddr_Ld; -- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1); -- end if; -- end if; -- end process UE_FailingReg; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_64; -- -- end generate UE_FAILING_REGISTERS; -- -- -- --------------------------------------------------------------------------- -- -- Generate: NO_UE_FAILING_REGISTERS -- -- Purpose: No Uncorrectable Error Failing registers. -- --------------------------------------------------------------------------- -- -- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate -- begin -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- UE_FailingECC <= (others => '0'); -- end generate NO_UE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: ECC_STATUS_REGISTERS -- Purpose: Enable ECC status and interrupt enable registers. --------------------------------------------------------------------------- ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate begin ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE; ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE; StatusReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_StatusReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then -- CE Interrupt status bit if RegWrData(C_ECC_STATUS_CE) = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1' end if; -- UE Interrupt status bit if RegWrData(C_ECC_STATUS_UE) = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1' end if; else if Sl_CE = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs end if; if Sl_UE = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs end if; end if; end if; end process StatusReg; ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_EnableIRQReg <= (others => '0'); elsif ECC_EnableIRQReg_WE = '1' then -- CE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE); -- UE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE); end if; end if; end process EnableIRQReg; Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or (ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE)); --------------------------------------------------------------------------- -- Generate output flag for UE sticky bit -- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted. REG_UE : process (S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE or (Enable_ECC_i = '0') then ECC_UE_i <= '0'; elsif Sl_UE = '1' then ECC_UE_i <= '1'; elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then ECC_UE_i <= '0'; else ECC_UE_i <= ECC_UE_i; end if; end if; end process REG_UE; ECC_UE <= ECC_UE_i; --------------------------------------------------------------------------- end generate ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_ECC_STATUS_REGISTERS -- Purpose: No ECC status or interrupt registers enabled. --------------------------------------------------------------------------- NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate begin ECC_EnableIRQReg <= (others => '0'); ECC_StatusReg <= (others => '0'); Interrupt <= '0'; ECC_UE <= '0'; end generate NO_ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: GEN_ECC_ONOFF -- Purpose: Implement ECC on/off control register. --------------------------------------------------------------------------- GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate begin ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then if (C_ECC_ONOFF_RESET_VALUE = 0) then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; else ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1'; end if; -- ECC on by default at reset (but can be disabled) elsif ECC_OnOffReg_WE = '1' then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH); end if; end if; end process EnableIRQReg; Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH); Enable_ECC <= Enable_ECC_i; end generate GEN_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC_ONOFF -- Purpose: No ECC on/off control register. --------------------------------------------------------------------------- GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate begin Enable_ECC <= '0'; -- ECC ON/OFF register is only enabled when C_ECC = 1. -- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then -- ECC should be disabled. ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; end generate GEN_NO_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: CE_COUNTER -- Purpose: Enable Correctable Error Counter -- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits. -- Parameterized here for future enhancements. --------------------------------------------------------------------------- CE_COUNTER : if C_HAS_CE_COUNTER generate -- One extra bit compare to CE_CounterReg to handle carry bit signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31); begin CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0'; -- TBD (could come from axi_lite) -- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and -- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') -- else '0'; CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') else '0'; CountReg : process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then CE_CounterReg <= (others => '0'); elsif CE_CounterReg_WE = '1' then -- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1); CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31); elsif CE_CounterReg_Inc_i = '1' then CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31); end if; end if; end process CountReg; CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1); end generate CE_COUNTER; -- Note: Hit this generate when C_ECC = 0. -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: NO_CE_COUNTER -- -- Purpose: Default for no CE counter register. -- --------------------------------------------------------------------------- -- -- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate -- begin -- CE_CounterReg <= (others => '0'); -- end generate NO_CE_COUNTER; --------------------------------------------------------------------------- -- Generate: GEN_REG_32_DATA -- Purpose: Generate read register values & signal assignments based on -- 32-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress; when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_32_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_64_DATA -- Purpose: Generate read register values & signal assignments based on -- 64-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_64_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_128_DATA -- Purpose: Generate read register values & signal assignments based on -- 128-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95); when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_128_DATA; --------------------------------------------------------------------------- end architecture implementation;
------------------------------------------------------------------------------- -- lite_ecc_reg.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: lite_ecc_reg.vhd -- -- Description: This module contains the register components for the -- ECC status & control data when enabled. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/17/2011 v1.03a -- ~~~~~~ -- Add ECC support for 128-bit BRAM data width. -- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and -- modify BRAM address registers. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_lite_if; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity lite_ecc_reg is generic ( C_S_AXI_PROTOCOL : string := "AXI4"; -- Used in this module to differentiate timing for error capture C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : INTEGER := 1; -- Enable single port usage of BRAM C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Clock and Reset S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- *** AXI-Lite ECC Register Interface Signals *** -- All synchronized to S_AXI_CTRL_AClk -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- *** Memory Controller Interface Signals *** -- All synchronized to S_AXI_AClk Enable_ECC : out std_logic; -- Indicates if and when ECC is enabled FaultInjectClr : in std_logic; -- Clear for Fault Inject Registers CE_Failing_We : in std_logic; -- WE for CE Failing Registers -- UE_Failing_We : in std_logic; -- WE for CE Failing Registers CE_CounterReg_Inc : in std_logic; -- Increment CE Counter Register Sl_CE : in std_logic; -- Correctable Error Flag Sl_UE : in std_logic; -- Uncorrectable Error Flag BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_En : in std_logic; Active_Wr : in std_logic; -- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- Outputs FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1) ); end entity lite_ecc_reg; ------------------------------------------------------------------------------- architecture implementation of lite_ecc_reg is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Start LMB BRAM v3.00a HDL constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1; constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1; constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1; constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1; constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1; constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0; -- Register accesses -- Register addresses use word address, i.e 2 LSB don't care -- Don't decode MSB, i.e. mirrorring of registers in address space of module constant C_REGADDR_WIDTH : integer := 8; constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00 constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01 constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10 constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11 constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00 constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01 constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10 constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11 constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00 constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00 constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01 constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00 constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01 constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10 constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11 constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00 constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00 constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00 constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00 constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01 constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10 constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11 constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00 -- ECC Status register bit positions constant C_ECC_STATUS_CE : natural := 30; constant C_ECC_STATUS_UE : natural := 31; constant C_ECC_STATUS_WIDTH : natural := 2; constant C_ECC_ENABLE_IRQ_CE : natural := 30; constant C_ECC_ENABLE_IRQ_UE : natural := 31; constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2; constant C_ECC_ON_OFF_WIDTH : natural := 1; -- End LMB BRAM v3.00a HDL constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0'); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal S_AXI_AReset : std_logic; -- Start LMB BRAM v3.00a HDL -- Read and write data to internal registers constant C_DWIDTH : integer := 32; signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegWr : std_logic; signal RegWr_i : std_logic; --signal RegWr_d1 : std_logic; --signal RegWr_d2 : std_logic; -- Fault Inject Register signal FaultInjectData_WE_0 : std_logic := '0'; signal FaultInjectData_WE_1 : std_logic := '0'; signal FaultInjectData_WE_2 : std_logic := '0'; signal FaultInjectData_WE_3 : std_logic := '0'; signal FaultInjectECC_WE : std_logic := '0'; --signal FaultInjectClr : std_logic := '0'; -- Correctable Error First Failing Register signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0'); signal CE_Failing_We_i : std_logic := '0'; -- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- Uncorrectable Error First Failing Register -- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0'); -- signal UE_Failing_We_i : std_logic := '0'; -- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0'); -- ECC Status and Control register signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg_WE : std_logic := '0'; -- ECC On/Off Control register signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0'); signal ECC_OnOffReg_WE : std_logic := '0'; -- Correctable Error Counter signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0'); signal CE_CounterReg_WE : std_logic := '0'; signal CE_CounterReg_Inc_i : std_logic := '0'; -- End LMB BRAM v3.00a HDL signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0'); signal Enable_ECC_i : std_logic := '0'; signal ECC_UE_i : std_logic := '0'; signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin FaultInjectData <= FaultInjectData_i; FaultInjectECC <= FaultInjectECC_i; -- Reserve for future support. -- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn); S_AXI_AReset <= not (S_AXI_AResetn); --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- -- Description: -- This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. -- -- Synchronized to AXI-Lite clock and reset. -- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to -- the AXI clock. -- --------------------------------------------------------------------------- I_AXI_LITE_IF : entity work.axi_lite_if generic map( C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH, C_REGADDR_WIDTH => C_REGADDR_WIDTH, C_DWIDTH => C_DWIDTH ) port map ( -- Reserve for future support. -- LMB_Clk => S_AXI_CTRL_AClk, -- LMB_Rst => S_AXI_CTRL_AReset, LMB_Clk => S_AXI_AClk, LMB_Rst => S_AXI_AReset, S_AXI_AWADDR => AXI_CTRL_AWADDR, S_AXI_AWVALID => AXI_CTRL_AWVALID, S_AXI_AWREADY => AXI_CTRL_AWREADY, S_AXI_WDATA => AXI_CTRL_WDATA, S_AXI_WSTRB => axi_lite_wstrb_int, S_AXI_WVALID => AXI_CTRL_WVALID, S_AXI_WREADY => AXI_CTRL_WREADY, S_AXI_BRESP => AXI_CTRL_BRESP, S_AXI_BVALID => AXI_CTRL_BVALID, S_AXI_BREADY => AXI_CTRL_BREADY, S_AXI_ARADDR => AXI_CTRL_ARADDR, S_AXI_ARVALID => AXI_CTRL_ARVALID, S_AXI_ARREADY => AXI_CTRL_ARREADY, S_AXI_RDATA => AXI_CTRL_RDATA, S_AXI_RRESP => AXI_CTRL_RRESP, S_AXI_RVALID => AXI_CTRL_RVALID, S_AXI_RREADY => AXI_CTRL_RREADY, RegWr => RegWr_i, RegWrData => RegWrData_i, RegAddr => RegAddr_i, RegRdData => RegRdData_i ); -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- -- Save HDL -- If it is decided to go back and use seperate clock inputs -- One for AXI4 and one for AXI4-Lite on this core. -- For now, temporarily comment out and replace the *_i signal -- assignments. RegWr <= RegWr_i; RegWrData <= RegWrData_i; RegAddr <= RegAddr_i; RegRdData_i <= RegRdData; -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- -- -- All registers must be synchronized to the correct clock. -- -- RegWr must be synchronized to the S_AXI_Clk -- -- RegWrData must be synchronized to the S_AXI_Clk -- -- RegAddr must be synchronized to the S_AXI_Clk -- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk -- -- -- --------------------------------------------------------------------------- -- -- SYNC_AXI_CLK: process (S_AXI_AClk) -- begin -- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- RegWr_d1 <= RegWr_i; -- RegWr_d2 <= RegWr_d1; -- RegWrData_d1 <= RegWrData_i; -- RegWrData_d2 <= RegWrData_d1; -- RegAddr_d1 <= RegAddr_i; -- RegAddr_d2 <= RegAddr_d1; -- end if; -- end process SYNC_AXI_CLK; -- -- RegWr <= RegWr_d2; -- RegWrData <= RegWrData_d2; -- RegAddr <= RegAddr_d2; -- -- -- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk) -- begin -- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then -- RegRdData_d1 <= RegRdData; -- RegRdData_d2 <= RegRdData_d1; -- end if; -- end process SYNC_AXI_LITE_CLK; -- -- RegRdData_i <= RegRdData_d2; -- --------------------------------------------------------------------------- axi_lite_wstrb_int <= (others => '1'); --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_SNG -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If single port, only register Port A address. -- -- With CE flag being registered, must account for one more -- pipeline stage in stored BRAM addresss that correlates to -- failing ECC. --------------------------------------------------------------------------- GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate -- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_A_d2 <= BRAM_Addr_A_d1; BRAM_Addr_A_d3 <= BRAM_Addr_A_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_A_d2 <= BRAM_Addr_A_d2; BRAM_Addr_A_d3 <= BRAM_Addr_A_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time. end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline). -- During read operaitons, use 3-deep address pipeline to store address values. FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_SNG; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_DUAL -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If dual port BRAM, register Port A & Port B address. -- -- Account for CE flag register delay, add 3rd BRAM address -- pipeline stage. -- --------------------------------------------------------------------------- GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate -- Port B pipeline stages only used in a dual port mode configuration. signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_B_d1 <= BRAM_Addr_B; BRAM_Addr_B_d2 <= BRAM_Addr_B_d1; BRAM_Addr_B_d3 <= BRAM_Addr_B_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_B_d1 <= BRAM_Addr_B_d1; BRAM_Addr_B_d2 <= BRAM_Addr_B_d2; BRAM_Addr_B_d3 <= BRAM_Addr_B_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin -- Only one active operation at a time. -- Use one deep address pipeline. Determine if Port A or B based on active read or write. FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A). -- During read operations, use 3-deep address pipeline to store address values (and from Port B). FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_DUAL; --------------------------------------------------------------------------- -- Generate: FAULT_INJECT -- Purpose: Implement fault injection registers -- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB) --------------------------------------------------------------------------- FAULT_INJECT : if C_HAS_FAULT_INJECT generate begin -- FaultInjectClr added to top level port list. -- Original LMB BRAM HDL -- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0'; --------------------------------------------------------------------------- -- Generate: GEN_32_FAULT -- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 32-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (25:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_32_FAULT; --------------------------------------------------------------------------- -- Generate: GEN_64_FAULT -- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 64-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (24:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_64_FAULT; -- v1.03a --------------------------------------------------------------------------- -- Generate: GEN_128_FAULT -- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0'; FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 128-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (96 to 127) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (64 to 95) <= RegWrData; elsif FaultInjectData_WE_2 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_3 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_128_FAULT; end generate FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: NO_FAULT_INJECT -- Purpose: Set default outputs when no fault inject capabilities. -- Remove check from C_WRITE_ACCESS (from LMB) --------------------------------------------------------------------------- NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate begin FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end generate NO_FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: CE_FAILING_REGISTERS -- Purpose: Implement Correctable Error First Failing Register --------------------------------------------------------------------------- CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate begin -- TBD (could come from axi_lite) -- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') -- else '0'; CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') else '0'; CE_FailingReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then CE_FailingAddress <= (others => '0'); -- Reserve for future support. -- CE_FailingData <= (others => '0'); elsif CE_Failing_We_i = '1' then --As the AXI Addr Width can now be lesser than 32, the address is getting shifted --Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000 CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0); --CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ; -- Reserve for future support. -- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1); end if; end if; end process CE_FailingReg; -- Note: Remove storage of CE_FFE & CE_FFD registers. -- Here for future support. -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_64; end generate CE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_CE_FAILING_REGISTERS -- Purpose: No Correctable Error Failing registers. --------------------------------------------------------------------------- NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate begin CE_FailingAddress <= (others => '0'); -- CE_FailingData <= (others => '0'); -- CE_FailingECC <= (others => '0'); end generate NO_CE_FAILING_REGISTERS; -- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0 -- This generate clause will never be evaluated. -- Here for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: UE_FAILING_REGISTERS -- -- Purpose: Implement Unorrectable Error First Failing Register -- --------------------------------------------------------------------------- -- -- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate -- begin -- -- -- TBD (could come from axi_lite) -- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- -- else '0'; -- -- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- else '0'; -- -- -- UE_FailingReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingAddress <= FailingAddr_Ld; -- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1); -- end if; -- end if; -- end process UE_FailingReg; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_64; -- -- end generate UE_FAILING_REGISTERS; -- -- -- --------------------------------------------------------------------------- -- -- Generate: NO_UE_FAILING_REGISTERS -- -- Purpose: No Uncorrectable Error Failing registers. -- --------------------------------------------------------------------------- -- -- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate -- begin -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- UE_FailingECC <= (others => '0'); -- end generate NO_UE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: ECC_STATUS_REGISTERS -- Purpose: Enable ECC status and interrupt enable registers. --------------------------------------------------------------------------- ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate begin ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE; ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE; StatusReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_StatusReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then -- CE Interrupt status bit if RegWrData(C_ECC_STATUS_CE) = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1' end if; -- UE Interrupt status bit if RegWrData(C_ECC_STATUS_UE) = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1' end if; else if Sl_CE = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs end if; if Sl_UE = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs end if; end if; end if; end process StatusReg; ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_EnableIRQReg <= (others => '0'); elsif ECC_EnableIRQReg_WE = '1' then -- CE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE); -- UE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE); end if; end if; end process EnableIRQReg; Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or (ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE)); --------------------------------------------------------------------------- -- Generate output flag for UE sticky bit -- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted. REG_UE : process (S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE or (Enable_ECC_i = '0') then ECC_UE_i <= '0'; elsif Sl_UE = '1' then ECC_UE_i <= '1'; elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then ECC_UE_i <= '0'; else ECC_UE_i <= ECC_UE_i; end if; end if; end process REG_UE; ECC_UE <= ECC_UE_i; --------------------------------------------------------------------------- end generate ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_ECC_STATUS_REGISTERS -- Purpose: No ECC status or interrupt registers enabled. --------------------------------------------------------------------------- NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate begin ECC_EnableIRQReg <= (others => '0'); ECC_StatusReg <= (others => '0'); Interrupt <= '0'; ECC_UE <= '0'; end generate NO_ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: GEN_ECC_ONOFF -- Purpose: Implement ECC on/off control register. --------------------------------------------------------------------------- GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate begin ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then if (C_ECC_ONOFF_RESET_VALUE = 0) then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; else ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1'; end if; -- ECC on by default at reset (but can be disabled) elsif ECC_OnOffReg_WE = '1' then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH); end if; end if; end process EnableIRQReg; Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH); Enable_ECC <= Enable_ECC_i; end generate GEN_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC_ONOFF -- Purpose: No ECC on/off control register. --------------------------------------------------------------------------- GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate begin Enable_ECC <= '0'; -- ECC ON/OFF register is only enabled when C_ECC = 1. -- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then -- ECC should be disabled. ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; end generate GEN_NO_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: CE_COUNTER -- Purpose: Enable Correctable Error Counter -- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits. -- Parameterized here for future enhancements. --------------------------------------------------------------------------- CE_COUNTER : if C_HAS_CE_COUNTER generate -- One extra bit compare to CE_CounterReg to handle carry bit signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31); begin CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0'; -- TBD (could come from axi_lite) -- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and -- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') -- else '0'; CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') else '0'; CountReg : process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then CE_CounterReg <= (others => '0'); elsif CE_CounterReg_WE = '1' then -- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1); CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31); elsif CE_CounterReg_Inc_i = '1' then CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31); end if; end if; end process CountReg; CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1); end generate CE_COUNTER; -- Note: Hit this generate when C_ECC = 0. -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: NO_CE_COUNTER -- -- Purpose: Default for no CE counter register. -- --------------------------------------------------------------------------- -- -- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate -- begin -- CE_CounterReg <= (others => '0'); -- end generate NO_CE_COUNTER; --------------------------------------------------------------------------- -- Generate: GEN_REG_32_DATA -- Purpose: Generate read register values & signal assignments based on -- 32-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress; when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_32_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_64_DATA -- Purpose: Generate read register values & signal assignments based on -- 64-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_64_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_128_DATA -- Purpose: Generate read register values & signal assignments based on -- 128-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95); when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_128_DATA; --------------------------------------------------------------------------- end architecture implementation;
------------------------------------------------------------------------------- -- lite_ecc_reg.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: lite_ecc_reg.vhd -- -- Description: This module contains the register components for the -- ECC status & control data when enabled. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/17/2011 v1.03a -- ~~~~~~ -- Add ECC support for 128-bit BRAM data width. -- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and -- modify BRAM address registers. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_lite_if; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity lite_ecc_reg is generic ( C_S_AXI_PROTOCOL : string := "AXI4"; -- Used in this module to differentiate timing for error capture C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : INTEGER := 1; -- Enable single port usage of BRAM C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Clock and Reset S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- *** AXI-Lite ECC Register Interface Signals *** -- All synchronized to S_AXI_CTRL_AClk -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- *** Memory Controller Interface Signals *** -- All synchronized to S_AXI_AClk Enable_ECC : out std_logic; -- Indicates if and when ECC is enabled FaultInjectClr : in std_logic; -- Clear for Fault Inject Registers CE_Failing_We : in std_logic; -- WE for CE Failing Registers -- UE_Failing_We : in std_logic; -- WE for CE Failing Registers CE_CounterReg_Inc : in std_logic; -- Increment CE Counter Register Sl_CE : in std_logic; -- Correctable Error Flag Sl_UE : in std_logic; -- Uncorrectable Error Flag BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_En : in std_logic; Active_Wr : in std_logic; -- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- Outputs FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1) ); end entity lite_ecc_reg; ------------------------------------------------------------------------------- architecture implementation of lite_ecc_reg is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Start LMB BRAM v3.00a HDL constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1; constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1; constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1; constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1; constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1; constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0; -- Register accesses -- Register addresses use word address, i.e 2 LSB don't care -- Don't decode MSB, i.e. mirrorring of registers in address space of module constant C_REGADDR_WIDTH : integer := 8; constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00 constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01 constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10 constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11 constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00 constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01 constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10 constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11 constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00 constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00 constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01 constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00 constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01 constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10 constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11 constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00 constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00 constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00 constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00 constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01 constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10 constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11 constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00 -- ECC Status register bit positions constant C_ECC_STATUS_CE : natural := 30; constant C_ECC_STATUS_UE : natural := 31; constant C_ECC_STATUS_WIDTH : natural := 2; constant C_ECC_ENABLE_IRQ_CE : natural := 30; constant C_ECC_ENABLE_IRQ_UE : natural := 31; constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2; constant C_ECC_ON_OFF_WIDTH : natural := 1; -- End LMB BRAM v3.00a HDL constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0'); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal S_AXI_AReset : std_logic; -- Start LMB BRAM v3.00a HDL -- Read and write data to internal registers constant C_DWIDTH : integer := 32; signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegWr : std_logic; signal RegWr_i : std_logic; --signal RegWr_d1 : std_logic; --signal RegWr_d2 : std_logic; -- Fault Inject Register signal FaultInjectData_WE_0 : std_logic := '0'; signal FaultInjectData_WE_1 : std_logic := '0'; signal FaultInjectData_WE_2 : std_logic := '0'; signal FaultInjectData_WE_3 : std_logic := '0'; signal FaultInjectECC_WE : std_logic := '0'; --signal FaultInjectClr : std_logic := '0'; -- Correctable Error First Failing Register signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0'); signal CE_Failing_We_i : std_logic := '0'; -- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- Uncorrectable Error First Failing Register -- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0'); -- signal UE_Failing_We_i : std_logic := '0'; -- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0'); -- ECC Status and Control register signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg_WE : std_logic := '0'; -- ECC On/Off Control register signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0'); signal ECC_OnOffReg_WE : std_logic := '0'; -- Correctable Error Counter signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0'); signal CE_CounterReg_WE : std_logic := '0'; signal CE_CounterReg_Inc_i : std_logic := '0'; -- End LMB BRAM v3.00a HDL signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0'); signal Enable_ECC_i : std_logic := '0'; signal ECC_UE_i : std_logic := '0'; signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin FaultInjectData <= FaultInjectData_i; FaultInjectECC <= FaultInjectECC_i; -- Reserve for future support. -- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn); S_AXI_AReset <= not (S_AXI_AResetn); --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- -- Description: -- This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. -- -- Synchronized to AXI-Lite clock and reset. -- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to -- the AXI clock. -- --------------------------------------------------------------------------- I_AXI_LITE_IF : entity work.axi_lite_if generic map( C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH, C_REGADDR_WIDTH => C_REGADDR_WIDTH, C_DWIDTH => C_DWIDTH ) port map ( -- Reserve for future support. -- LMB_Clk => S_AXI_CTRL_AClk, -- LMB_Rst => S_AXI_CTRL_AReset, LMB_Clk => S_AXI_AClk, LMB_Rst => S_AXI_AReset, S_AXI_AWADDR => AXI_CTRL_AWADDR, S_AXI_AWVALID => AXI_CTRL_AWVALID, S_AXI_AWREADY => AXI_CTRL_AWREADY, S_AXI_WDATA => AXI_CTRL_WDATA, S_AXI_WSTRB => axi_lite_wstrb_int, S_AXI_WVALID => AXI_CTRL_WVALID, S_AXI_WREADY => AXI_CTRL_WREADY, S_AXI_BRESP => AXI_CTRL_BRESP, S_AXI_BVALID => AXI_CTRL_BVALID, S_AXI_BREADY => AXI_CTRL_BREADY, S_AXI_ARADDR => AXI_CTRL_ARADDR, S_AXI_ARVALID => AXI_CTRL_ARVALID, S_AXI_ARREADY => AXI_CTRL_ARREADY, S_AXI_RDATA => AXI_CTRL_RDATA, S_AXI_RRESP => AXI_CTRL_RRESP, S_AXI_RVALID => AXI_CTRL_RVALID, S_AXI_RREADY => AXI_CTRL_RREADY, RegWr => RegWr_i, RegWrData => RegWrData_i, RegAddr => RegAddr_i, RegRdData => RegRdData_i ); -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- -- Save HDL -- If it is decided to go back and use seperate clock inputs -- One for AXI4 and one for AXI4-Lite on this core. -- For now, temporarily comment out and replace the *_i signal -- assignments. RegWr <= RegWr_i; RegWrData <= RegWrData_i; RegAddr <= RegAddr_i; RegRdData_i <= RegRdData; -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- -- -- All registers must be synchronized to the correct clock. -- -- RegWr must be synchronized to the S_AXI_Clk -- -- RegWrData must be synchronized to the S_AXI_Clk -- -- RegAddr must be synchronized to the S_AXI_Clk -- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk -- -- -- --------------------------------------------------------------------------- -- -- SYNC_AXI_CLK: process (S_AXI_AClk) -- begin -- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- RegWr_d1 <= RegWr_i; -- RegWr_d2 <= RegWr_d1; -- RegWrData_d1 <= RegWrData_i; -- RegWrData_d2 <= RegWrData_d1; -- RegAddr_d1 <= RegAddr_i; -- RegAddr_d2 <= RegAddr_d1; -- end if; -- end process SYNC_AXI_CLK; -- -- RegWr <= RegWr_d2; -- RegWrData <= RegWrData_d2; -- RegAddr <= RegAddr_d2; -- -- -- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk) -- begin -- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then -- RegRdData_d1 <= RegRdData; -- RegRdData_d2 <= RegRdData_d1; -- end if; -- end process SYNC_AXI_LITE_CLK; -- -- RegRdData_i <= RegRdData_d2; -- --------------------------------------------------------------------------- axi_lite_wstrb_int <= (others => '1'); --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_SNG -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If single port, only register Port A address. -- -- With CE flag being registered, must account for one more -- pipeline stage in stored BRAM addresss that correlates to -- failing ECC. --------------------------------------------------------------------------- GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate -- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_A_d2 <= BRAM_Addr_A_d1; BRAM_Addr_A_d3 <= BRAM_Addr_A_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_A_d2 <= BRAM_Addr_A_d2; BRAM_Addr_A_d3 <= BRAM_Addr_A_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time. end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline). -- During read operaitons, use 3-deep address pipeline to store address values. FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_SNG; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_DUAL -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If dual port BRAM, register Port A & Port B address. -- -- Account for CE flag register delay, add 3rd BRAM address -- pipeline stage. -- --------------------------------------------------------------------------- GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate -- Port B pipeline stages only used in a dual port mode configuration. signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_B_d1 <= BRAM_Addr_B; BRAM_Addr_B_d2 <= BRAM_Addr_B_d1; BRAM_Addr_B_d3 <= BRAM_Addr_B_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_B_d1 <= BRAM_Addr_B_d1; BRAM_Addr_B_d2 <= BRAM_Addr_B_d2; BRAM_Addr_B_d3 <= BRAM_Addr_B_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin -- Only one active operation at a time. -- Use one deep address pipeline. Determine if Port A or B based on active read or write. FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A). -- During read operations, use 3-deep address pipeline to store address values (and from Port B). FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_DUAL; --------------------------------------------------------------------------- -- Generate: FAULT_INJECT -- Purpose: Implement fault injection registers -- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB) --------------------------------------------------------------------------- FAULT_INJECT : if C_HAS_FAULT_INJECT generate begin -- FaultInjectClr added to top level port list. -- Original LMB BRAM HDL -- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0'; --------------------------------------------------------------------------- -- Generate: GEN_32_FAULT -- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 32-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (25:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_32_FAULT; --------------------------------------------------------------------------- -- Generate: GEN_64_FAULT -- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 64-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (24:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_64_FAULT; -- v1.03a --------------------------------------------------------------------------- -- Generate: GEN_128_FAULT -- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0'; FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 128-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (96 to 127) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (64 to 95) <= RegWrData; elsif FaultInjectData_WE_2 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_3 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_128_FAULT; end generate FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: NO_FAULT_INJECT -- Purpose: Set default outputs when no fault inject capabilities. -- Remove check from C_WRITE_ACCESS (from LMB) --------------------------------------------------------------------------- NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate begin FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end generate NO_FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: CE_FAILING_REGISTERS -- Purpose: Implement Correctable Error First Failing Register --------------------------------------------------------------------------- CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate begin -- TBD (could come from axi_lite) -- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') -- else '0'; CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') else '0'; CE_FailingReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then CE_FailingAddress <= (others => '0'); -- Reserve for future support. -- CE_FailingData <= (others => '0'); elsif CE_Failing_We_i = '1' then --As the AXI Addr Width can now be lesser than 32, the address is getting shifted --Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000 CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0); --CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ; -- Reserve for future support. -- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1); end if; end if; end process CE_FailingReg; -- Note: Remove storage of CE_FFE & CE_FFD registers. -- Here for future support. -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_64; end generate CE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_CE_FAILING_REGISTERS -- Purpose: No Correctable Error Failing registers. --------------------------------------------------------------------------- NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate begin CE_FailingAddress <= (others => '0'); -- CE_FailingData <= (others => '0'); -- CE_FailingECC <= (others => '0'); end generate NO_CE_FAILING_REGISTERS; -- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0 -- This generate clause will never be evaluated. -- Here for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: UE_FAILING_REGISTERS -- -- Purpose: Implement Unorrectable Error First Failing Register -- --------------------------------------------------------------------------- -- -- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate -- begin -- -- -- TBD (could come from axi_lite) -- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- -- else '0'; -- -- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- else '0'; -- -- -- UE_FailingReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingAddress <= FailingAddr_Ld; -- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1); -- end if; -- end if; -- end process UE_FailingReg; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_64; -- -- end generate UE_FAILING_REGISTERS; -- -- -- --------------------------------------------------------------------------- -- -- Generate: NO_UE_FAILING_REGISTERS -- -- Purpose: No Uncorrectable Error Failing registers. -- --------------------------------------------------------------------------- -- -- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate -- begin -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- UE_FailingECC <= (others => '0'); -- end generate NO_UE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: ECC_STATUS_REGISTERS -- Purpose: Enable ECC status and interrupt enable registers. --------------------------------------------------------------------------- ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate begin ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE; ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE; StatusReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_StatusReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then -- CE Interrupt status bit if RegWrData(C_ECC_STATUS_CE) = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1' end if; -- UE Interrupt status bit if RegWrData(C_ECC_STATUS_UE) = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1' end if; else if Sl_CE = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs end if; if Sl_UE = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs end if; end if; end if; end process StatusReg; ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_EnableIRQReg <= (others => '0'); elsif ECC_EnableIRQReg_WE = '1' then -- CE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE); -- UE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE); end if; end if; end process EnableIRQReg; Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or (ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE)); --------------------------------------------------------------------------- -- Generate output flag for UE sticky bit -- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted. REG_UE : process (S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE or (Enable_ECC_i = '0') then ECC_UE_i <= '0'; elsif Sl_UE = '1' then ECC_UE_i <= '1'; elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then ECC_UE_i <= '0'; else ECC_UE_i <= ECC_UE_i; end if; end if; end process REG_UE; ECC_UE <= ECC_UE_i; --------------------------------------------------------------------------- end generate ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_ECC_STATUS_REGISTERS -- Purpose: No ECC status or interrupt registers enabled. --------------------------------------------------------------------------- NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate begin ECC_EnableIRQReg <= (others => '0'); ECC_StatusReg <= (others => '0'); Interrupt <= '0'; ECC_UE <= '0'; end generate NO_ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: GEN_ECC_ONOFF -- Purpose: Implement ECC on/off control register. --------------------------------------------------------------------------- GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate begin ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then if (C_ECC_ONOFF_RESET_VALUE = 0) then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; else ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1'; end if; -- ECC on by default at reset (but can be disabled) elsif ECC_OnOffReg_WE = '1' then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH); end if; end if; end process EnableIRQReg; Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH); Enable_ECC <= Enable_ECC_i; end generate GEN_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC_ONOFF -- Purpose: No ECC on/off control register. --------------------------------------------------------------------------- GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate begin Enable_ECC <= '0'; -- ECC ON/OFF register is only enabled when C_ECC = 1. -- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then -- ECC should be disabled. ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; end generate GEN_NO_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: CE_COUNTER -- Purpose: Enable Correctable Error Counter -- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits. -- Parameterized here for future enhancements. --------------------------------------------------------------------------- CE_COUNTER : if C_HAS_CE_COUNTER generate -- One extra bit compare to CE_CounterReg to handle carry bit signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31); begin CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0'; -- TBD (could come from axi_lite) -- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and -- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') -- else '0'; CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') else '0'; CountReg : process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then CE_CounterReg <= (others => '0'); elsif CE_CounterReg_WE = '1' then -- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1); CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31); elsif CE_CounterReg_Inc_i = '1' then CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31); end if; end if; end process CountReg; CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1); end generate CE_COUNTER; -- Note: Hit this generate when C_ECC = 0. -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: NO_CE_COUNTER -- -- Purpose: Default for no CE counter register. -- --------------------------------------------------------------------------- -- -- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate -- begin -- CE_CounterReg <= (others => '0'); -- end generate NO_CE_COUNTER; --------------------------------------------------------------------------- -- Generate: GEN_REG_32_DATA -- Purpose: Generate read register values & signal assignments based on -- 32-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress; when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_32_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_64_DATA -- Purpose: Generate read register values & signal assignments based on -- 64-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_64_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_128_DATA -- Purpose: Generate read register values & signal assignments based on -- 128-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95); when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_128_DATA; --------------------------------------------------------------------------- end architecture implementation;
------------------------------------------------------------------------------- -- lite_ecc_reg.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: lite_ecc_reg.vhd -- -- Description: This module contains the register components for the -- ECC status & control data when enabled. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/17/2011 v1.03a -- ~~~~~~ -- Add ECC support for 128-bit BRAM data width. -- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and -- modify BRAM address registers. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_lite_if; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity lite_ecc_reg is generic ( C_S_AXI_PROTOCOL : string := "AXI4"; -- Used in this module to differentiate timing for error capture C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : INTEGER := 1; -- Enable single port usage of BRAM C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Clock and Reset S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- *** AXI-Lite ECC Register Interface Signals *** -- All synchronized to S_AXI_CTRL_AClk -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- *** Memory Controller Interface Signals *** -- All synchronized to S_AXI_AClk Enable_ECC : out std_logic; -- Indicates if and when ECC is enabled FaultInjectClr : in std_logic; -- Clear for Fault Inject Registers CE_Failing_We : in std_logic; -- WE for CE Failing Registers -- UE_Failing_We : in std_logic; -- WE for CE Failing Registers CE_CounterReg_Inc : in std_logic; -- Increment CE Counter Register Sl_CE : in std_logic; -- Correctable Error Flag Sl_UE : in std_logic; -- Uncorrectable Error Flag BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_En : in std_logic; Active_Wr : in std_logic; -- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- Outputs FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1) ); end entity lite_ecc_reg; ------------------------------------------------------------------------------- architecture implementation of lite_ecc_reg is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Start LMB BRAM v3.00a HDL constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1; constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1; constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1; constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1; constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1; constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0; -- Register accesses -- Register addresses use word address, i.e 2 LSB don't care -- Don't decode MSB, i.e. mirrorring of registers in address space of module constant C_REGADDR_WIDTH : integer := 8; constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00 constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01 constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10 constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11 constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00 constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01 constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10 constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11 constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00 constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00 constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01 constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00 constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01 constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10 constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11 constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00 constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00 constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00 constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00 constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01 constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10 constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11 constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00 -- ECC Status register bit positions constant C_ECC_STATUS_CE : natural := 30; constant C_ECC_STATUS_UE : natural := 31; constant C_ECC_STATUS_WIDTH : natural := 2; constant C_ECC_ENABLE_IRQ_CE : natural := 30; constant C_ECC_ENABLE_IRQ_UE : natural := 31; constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2; constant C_ECC_ON_OFF_WIDTH : natural := 1; -- End LMB BRAM v3.00a HDL constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0'); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal S_AXI_AReset : std_logic; -- Start LMB BRAM v3.00a HDL -- Read and write data to internal registers constant C_DWIDTH : integer := 32; signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegWr : std_logic; signal RegWr_i : std_logic; --signal RegWr_d1 : std_logic; --signal RegWr_d2 : std_logic; -- Fault Inject Register signal FaultInjectData_WE_0 : std_logic := '0'; signal FaultInjectData_WE_1 : std_logic := '0'; signal FaultInjectData_WE_2 : std_logic := '0'; signal FaultInjectData_WE_3 : std_logic := '0'; signal FaultInjectECC_WE : std_logic := '0'; --signal FaultInjectClr : std_logic := '0'; -- Correctable Error First Failing Register signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0'); signal CE_Failing_We_i : std_logic := '0'; -- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- Uncorrectable Error First Failing Register -- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0'); -- signal UE_Failing_We_i : std_logic := '0'; -- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0'); -- ECC Status and Control register signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg_WE : std_logic := '0'; -- ECC On/Off Control register signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0'); signal ECC_OnOffReg_WE : std_logic := '0'; -- Correctable Error Counter signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0'); signal CE_CounterReg_WE : std_logic := '0'; signal CE_CounterReg_Inc_i : std_logic := '0'; -- End LMB BRAM v3.00a HDL signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0'); signal Enable_ECC_i : std_logic := '0'; signal ECC_UE_i : std_logic := '0'; signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin FaultInjectData <= FaultInjectData_i; FaultInjectECC <= FaultInjectECC_i; -- Reserve for future support. -- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn); S_AXI_AReset <= not (S_AXI_AResetn); --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- -- Description: -- This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. -- -- Synchronized to AXI-Lite clock and reset. -- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to -- the AXI clock. -- --------------------------------------------------------------------------- I_AXI_LITE_IF : entity work.axi_lite_if generic map( C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH, C_REGADDR_WIDTH => C_REGADDR_WIDTH, C_DWIDTH => C_DWIDTH ) port map ( -- Reserve for future support. -- LMB_Clk => S_AXI_CTRL_AClk, -- LMB_Rst => S_AXI_CTRL_AReset, LMB_Clk => S_AXI_AClk, LMB_Rst => S_AXI_AReset, S_AXI_AWADDR => AXI_CTRL_AWADDR, S_AXI_AWVALID => AXI_CTRL_AWVALID, S_AXI_AWREADY => AXI_CTRL_AWREADY, S_AXI_WDATA => AXI_CTRL_WDATA, S_AXI_WSTRB => axi_lite_wstrb_int, S_AXI_WVALID => AXI_CTRL_WVALID, S_AXI_WREADY => AXI_CTRL_WREADY, S_AXI_BRESP => AXI_CTRL_BRESP, S_AXI_BVALID => AXI_CTRL_BVALID, S_AXI_BREADY => AXI_CTRL_BREADY, S_AXI_ARADDR => AXI_CTRL_ARADDR, S_AXI_ARVALID => AXI_CTRL_ARVALID, S_AXI_ARREADY => AXI_CTRL_ARREADY, S_AXI_RDATA => AXI_CTRL_RDATA, S_AXI_RRESP => AXI_CTRL_RRESP, S_AXI_RVALID => AXI_CTRL_RVALID, S_AXI_RREADY => AXI_CTRL_RREADY, RegWr => RegWr_i, RegWrData => RegWrData_i, RegAddr => RegAddr_i, RegRdData => RegRdData_i ); -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- -- Save HDL -- If it is decided to go back and use seperate clock inputs -- One for AXI4 and one for AXI4-Lite on this core. -- For now, temporarily comment out and replace the *_i signal -- assignments. RegWr <= RegWr_i; RegWrData <= RegWrData_i; RegAddr <= RegAddr_i; RegRdData_i <= RegRdData; -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- -- -- All registers must be synchronized to the correct clock. -- -- RegWr must be synchronized to the S_AXI_Clk -- -- RegWrData must be synchronized to the S_AXI_Clk -- -- RegAddr must be synchronized to the S_AXI_Clk -- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk -- -- -- --------------------------------------------------------------------------- -- -- SYNC_AXI_CLK: process (S_AXI_AClk) -- begin -- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- RegWr_d1 <= RegWr_i; -- RegWr_d2 <= RegWr_d1; -- RegWrData_d1 <= RegWrData_i; -- RegWrData_d2 <= RegWrData_d1; -- RegAddr_d1 <= RegAddr_i; -- RegAddr_d2 <= RegAddr_d1; -- end if; -- end process SYNC_AXI_CLK; -- -- RegWr <= RegWr_d2; -- RegWrData <= RegWrData_d2; -- RegAddr <= RegAddr_d2; -- -- -- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk) -- begin -- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then -- RegRdData_d1 <= RegRdData; -- RegRdData_d2 <= RegRdData_d1; -- end if; -- end process SYNC_AXI_LITE_CLK; -- -- RegRdData_i <= RegRdData_d2; -- --------------------------------------------------------------------------- axi_lite_wstrb_int <= (others => '1'); --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_SNG -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If single port, only register Port A address. -- -- With CE flag being registered, must account for one more -- pipeline stage in stored BRAM addresss that correlates to -- failing ECC. --------------------------------------------------------------------------- GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate -- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_A_d2 <= BRAM_Addr_A_d1; BRAM_Addr_A_d3 <= BRAM_Addr_A_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_A_d2 <= BRAM_Addr_A_d2; BRAM_Addr_A_d3 <= BRAM_Addr_A_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time. end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline). -- During read operaitons, use 3-deep address pipeline to store address values. FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_SNG; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_DUAL -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If dual port BRAM, register Port A & Port B address. -- -- Account for CE flag register delay, add 3rd BRAM address -- pipeline stage. -- --------------------------------------------------------------------------- GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate -- Port B pipeline stages only used in a dual port mode configuration. signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_B_d1 <= BRAM_Addr_B; BRAM_Addr_B_d2 <= BRAM_Addr_B_d1; BRAM_Addr_B_d3 <= BRAM_Addr_B_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_B_d1 <= BRAM_Addr_B_d1; BRAM_Addr_B_d2 <= BRAM_Addr_B_d2; BRAM_Addr_B_d3 <= BRAM_Addr_B_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin -- Only one active operation at a time. -- Use one deep address pipeline. Determine if Port A or B based on active read or write. FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A). -- During read operations, use 3-deep address pipeline to store address values (and from Port B). FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_DUAL; --------------------------------------------------------------------------- -- Generate: FAULT_INJECT -- Purpose: Implement fault injection registers -- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB) --------------------------------------------------------------------------- FAULT_INJECT : if C_HAS_FAULT_INJECT generate begin -- FaultInjectClr added to top level port list. -- Original LMB BRAM HDL -- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0'; --------------------------------------------------------------------------- -- Generate: GEN_32_FAULT -- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 32-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (25:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_32_FAULT; --------------------------------------------------------------------------- -- Generate: GEN_64_FAULT -- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 64-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (24:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_64_FAULT; -- v1.03a --------------------------------------------------------------------------- -- Generate: GEN_128_FAULT -- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0'; FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 128-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (96 to 127) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (64 to 95) <= RegWrData; elsif FaultInjectData_WE_2 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_3 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_128_FAULT; end generate FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: NO_FAULT_INJECT -- Purpose: Set default outputs when no fault inject capabilities. -- Remove check from C_WRITE_ACCESS (from LMB) --------------------------------------------------------------------------- NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate begin FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end generate NO_FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: CE_FAILING_REGISTERS -- Purpose: Implement Correctable Error First Failing Register --------------------------------------------------------------------------- CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate begin -- TBD (could come from axi_lite) -- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') -- else '0'; CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') else '0'; CE_FailingReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then CE_FailingAddress <= (others => '0'); -- Reserve for future support. -- CE_FailingData <= (others => '0'); elsif CE_Failing_We_i = '1' then --As the AXI Addr Width can now be lesser than 32, the address is getting shifted --Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000 CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0); --CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ; -- Reserve for future support. -- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1); end if; end if; end process CE_FailingReg; -- Note: Remove storage of CE_FFE & CE_FFD registers. -- Here for future support. -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_64; end generate CE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_CE_FAILING_REGISTERS -- Purpose: No Correctable Error Failing registers. --------------------------------------------------------------------------- NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate begin CE_FailingAddress <= (others => '0'); -- CE_FailingData <= (others => '0'); -- CE_FailingECC <= (others => '0'); end generate NO_CE_FAILING_REGISTERS; -- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0 -- This generate clause will never be evaluated. -- Here for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: UE_FAILING_REGISTERS -- -- Purpose: Implement Unorrectable Error First Failing Register -- --------------------------------------------------------------------------- -- -- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate -- begin -- -- -- TBD (could come from axi_lite) -- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- -- else '0'; -- -- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- else '0'; -- -- -- UE_FailingReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingAddress <= FailingAddr_Ld; -- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1); -- end if; -- end if; -- end process UE_FailingReg; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_64; -- -- end generate UE_FAILING_REGISTERS; -- -- -- --------------------------------------------------------------------------- -- -- Generate: NO_UE_FAILING_REGISTERS -- -- Purpose: No Uncorrectable Error Failing registers. -- --------------------------------------------------------------------------- -- -- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate -- begin -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- UE_FailingECC <= (others => '0'); -- end generate NO_UE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: ECC_STATUS_REGISTERS -- Purpose: Enable ECC status and interrupt enable registers. --------------------------------------------------------------------------- ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate begin ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE; ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE; StatusReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_StatusReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then -- CE Interrupt status bit if RegWrData(C_ECC_STATUS_CE) = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1' end if; -- UE Interrupt status bit if RegWrData(C_ECC_STATUS_UE) = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1' end if; else if Sl_CE = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs end if; if Sl_UE = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs end if; end if; end if; end process StatusReg; ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_EnableIRQReg <= (others => '0'); elsif ECC_EnableIRQReg_WE = '1' then -- CE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE); -- UE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE); end if; end if; end process EnableIRQReg; Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or (ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE)); --------------------------------------------------------------------------- -- Generate output flag for UE sticky bit -- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted. REG_UE : process (S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE or (Enable_ECC_i = '0') then ECC_UE_i <= '0'; elsif Sl_UE = '1' then ECC_UE_i <= '1'; elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then ECC_UE_i <= '0'; else ECC_UE_i <= ECC_UE_i; end if; end if; end process REG_UE; ECC_UE <= ECC_UE_i; --------------------------------------------------------------------------- end generate ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_ECC_STATUS_REGISTERS -- Purpose: No ECC status or interrupt registers enabled. --------------------------------------------------------------------------- NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate begin ECC_EnableIRQReg <= (others => '0'); ECC_StatusReg <= (others => '0'); Interrupt <= '0'; ECC_UE <= '0'; end generate NO_ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: GEN_ECC_ONOFF -- Purpose: Implement ECC on/off control register. --------------------------------------------------------------------------- GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate begin ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then if (C_ECC_ONOFF_RESET_VALUE = 0) then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; else ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1'; end if; -- ECC on by default at reset (but can be disabled) elsif ECC_OnOffReg_WE = '1' then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH); end if; end if; end process EnableIRQReg; Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH); Enable_ECC <= Enable_ECC_i; end generate GEN_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC_ONOFF -- Purpose: No ECC on/off control register. --------------------------------------------------------------------------- GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate begin Enable_ECC <= '0'; -- ECC ON/OFF register is only enabled when C_ECC = 1. -- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then -- ECC should be disabled. ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; end generate GEN_NO_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: CE_COUNTER -- Purpose: Enable Correctable Error Counter -- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits. -- Parameterized here for future enhancements. --------------------------------------------------------------------------- CE_COUNTER : if C_HAS_CE_COUNTER generate -- One extra bit compare to CE_CounterReg to handle carry bit signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31); begin CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0'; -- TBD (could come from axi_lite) -- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and -- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') -- else '0'; CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') else '0'; CountReg : process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then CE_CounterReg <= (others => '0'); elsif CE_CounterReg_WE = '1' then -- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1); CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31); elsif CE_CounterReg_Inc_i = '1' then CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31); end if; end if; end process CountReg; CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1); end generate CE_COUNTER; -- Note: Hit this generate when C_ECC = 0. -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: NO_CE_COUNTER -- -- Purpose: Default for no CE counter register. -- --------------------------------------------------------------------------- -- -- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate -- begin -- CE_CounterReg <= (others => '0'); -- end generate NO_CE_COUNTER; --------------------------------------------------------------------------- -- Generate: GEN_REG_32_DATA -- Purpose: Generate read register values & signal assignments based on -- 32-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress; when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_32_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_64_DATA -- Purpose: Generate read register values & signal assignments based on -- 64-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_64_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_128_DATA -- Purpose: Generate read register values & signal assignments based on -- 128-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95); when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_128_DATA; --------------------------------------------------------------------------- end architecture implementation;
------------------------------------------------------------------------------- -- lite_ecc_reg.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: lite_ecc_reg.vhd -- -- Description: This module contains the register components for the -- ECC status & control data when enabled. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/17/2011 v1.03a -- ~~~~~~ -- Add ECC support for 128-bit BRAM data width. -- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and -- modify BRAM address registers. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_lite_if; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity lite_ecc_reg is generic ( C_S_AXI_PROTOCOL : string := "AXI4"; -- Used in this module to differentiate timing for error capture C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : INTEGER := 1; -- Enable single port usage of BRAM C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Clock and Reset S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- *** AXI-Lite ECC Register Interface Signals *** -- All synchronized to S_AXI_CTRL_AClk -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- *** Memory Controller Interface Signals *** -- All synchronized to S_AXI_AClk Enable_ECC : out std_logic; -- Indicates if and when ECC is enabled FaultInjectClr : in std_logic; -- Clear for Fault Inject Registers CE_Failing_We : in std_logic; -- WE for CE Failing Registers -- UE_Failing_We : in std_logic; -- WE for CE Failing Registers CE_CounterReg_Inc : in std_logic; -- Increment CE Counter Register Sl_CE : in std_logic; -- Correctable Error Flag Sl_UE : in std_logic; -- Uncorrectable Error Flag BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_En : in std_logic; Active_Wr : in std_logic; -- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- Outputs FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1) ); end entity lite_ecc_reg; ------------------------------------------------------------------------------- architecture implementation of lite_ecc_reg is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Start LMB BRAM v3.00a HDL constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1; constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1; constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1; constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1; constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1; constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0; -- Register accesses -- Register addresses use word address, i.e 2 LSB don't care -- Don't decode MSB, i.e. mirrorring of registers in address space of module constant C_REGADDR_WIDTH : integer := 8; constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00 constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01 constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10 constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11 constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00 constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01 constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10 constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11 constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00 constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00 constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01 constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00 constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01 constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10 constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11 constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00 constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00 constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00 constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00 constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01 constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10 constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11 constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00 -- ECC Status register bit positions constant C_ECC_STATUS_CE : natural := 30; constant C_ECC_STATUS_UE : natural := 31; constant C_ECC_STATUS_WIDTH : natural := 2; constant C_ECC_ENABLE_IRQ_CE : natural := 30; constant C_ECC_ENABLE_IRQ_UE : natural := 31; constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2; constant C_ECC_ON_OFF_WIDTH : natural := 1; -- End LMB BRAM v3.00a HDL constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0'); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal S_AXI_AReset : std_logic; -- Start LMB BRAM v3.00a HDL -- Read and write data to internal registers constant C_DWIDTH : integer := 32; signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegWr : std_logic; signal RegWr_i : std_logic; --signal RegWr_d1 : std_logic; --signal RegWr_d2 : std_logic; -- Fault Inject Register signal FaultInjectData_WE_0 : std_logic := '0'; signal FaultInjectData_WE_1 : std_logic := '0'; signal FaultInjectData_WE_2 : std_logic := '0'; signal FaultInjectData_WE_3 : std_logic := '0'; signal FaultInjectECC_WE : std_logic := '0'; --signal FaultInjectClr : std_logic := '0'; -- Correctable Error First Failing Register signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0'); signal CE_Failing_We_i : std_logic := '0'; -- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- Uncorrectable Error First Failing Register -- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0'); -- signal UE_Failing_We_i : std_logic := '0'; -- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0'); -- ECC Status and Control register signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg_WE : std_logic := '0'; -- ECC On/Off Control register signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0'); signal ECC_OnOffReg_WE : std_logic := '0'; -- Correctable Error Counter signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0'); signal CE_CounterReg_WE : std_logic := '0'; signal CE_CounterReg_Inc_i : std_logic := '0'; -- End LMB BRAM v3.00a HDL signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0'); signal Enable_ECC_i : std_logic := '0'; signal ECC_UE_i : std_logic := '0'; signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin FaultInjectData <= FaultInjectData_i; FaultInjectECC <= FaultInjectECC_i; -- Reserve for future support. -- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn); S_AXI_AReset <= not (S_AXI_AResetn); --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- -- Description: -- This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. -- -- Synchronized to AXI-Lite clock and reset. -- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to -- the AXI clock. -- --------------------------------------------------------------------------- I_AXI_LITE_IF : entity work.axi_lite_if generic map( C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH, C_REGADDR_WIDTH => C_REGADDR_WIDTH, C_DWIDTH => C_DWIDTH ) port map ( -- Reserve for future support. -- LMB_Clk => S_AXI_CTRL_AClk, -- LMB_Rst => S_AXI_CTRL_AReset, LMB_Clk => S_AXI_AClk, LMB_Rst => S_AXI_AReset, S_AXI_AWADDR => AXI_CTRL_AWADDR, S_AXI_AWVALID => AXI_CTRL_AWVALID, S_AXI_AWREADY => AXI_CTRL_AWREADY, S_AXI_WDATA => AXI_CTRL_WDATA, S_AXI_WSTRB => axi_lite_wstrb_int, S_AXI_WVALID => AXI_CTRL_WVALID, S_AXI_WREADY => AXI_CTRL_WREADY, S_AXI_BRESP => AXI_CTRL_BRESP, S_AXI_BVALID => AXI_CTRL_BVALID, S_AXI_BREADY => AXI_CTRL_BREADY, S_AXI_ARADDR => AXI_CTRL_ARADDR, S_AXI_ARVALID => AXI_CTRL_ARVALID, S_AXI_ARREADY => AXI_CTRL_ARREADY, S_AXI_RDATA => AXI_CTRL_RDATA, S_AXI_RRESP => AXI_CTRL_RRESP, S_AXI_RVALID => AXI_CTRL_RVALID, S_AXI_RREADY => AXI_CTRL_RREADY, RegWr => RegWr_i, RegWrData => RegWrData_i, RegAddr => RegAddr_i, RegRdData => RegRdData_i ); -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- -- Save HDL -- If it is decided to go back and use seperate clock inputs -- One for AXI4 and one for AXI4-Lite on this core. -- For now, temporarily comment out and replace the *_i signal -- assignments. RegWr <= RegWr_i; RegWrData <= RegWrData_i; RegAddr <= RegAddr_i; RegRdData_i <= RegRdData; -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- -- -- All registers must be synchronized to the correct clock. -- -- RegWr must be synchronized to the S_AXI_Clk -- -- RegWrData must be synchronized to the S_AXI_Clk -- -- RegAddr must be synchronized to the S_AXI_Clk -- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk -- -- -- --------------------------------------------------------------------------- -- -- SYNC_AXI_CLK: process (S_AXI_AClk) -- begin -- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- RegWr_d1 <= RegWr_i; -- RegWr_d2 <= RegWr_d1; -- RegWrData_d1 <= RegWrData_i; -- RegWrData_d2 <= RegWrData_d1; -- RegAddr_d1 <= RegAddr_i; -- RegAddr_d2 <= RegAddr_d1; -- end if; -- end process SYNC_AXI_CLK; -- -- RegWr <= RegWr_d2; -- RegWrData <= RegWrData_d2; -- RegAddr <= RegAddr_d2; -- -- -- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk) -- begin -- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then -- RegRdData_d1 <= RegRdData; -- RegRdData_d2 <= RegRdData_d1; -- end if; -- end process SYNC_AXI_LITE_CLK; -- -- RegRdData_i <= RegRdData_d2; -- --------------------------------------------------------------------------- axi_lite_wstrb_int <= (others => '1'); --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_SNG -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If single port, only register Port A address. -- -- With CE flag being registered, must account for one more -- pipeline stage in stored BRAM addresss that correlates to -- failing ECC. --------------------------------------------------------------------------- GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate -- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_A_d2 <= BRAM_Addr_A_d1; BRAM_Addr_A_d3 <= BRAM_Addr_A_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_A_d2 <= BRAM_Addr_A_d2; BRAM_Addr_A_d3 <= BRAM_Addr_A_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time. end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline). -- During read operaitons, use 3-deep address pipeline to store address values. FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_SNG; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_DUAL -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If dual port BRAM, register Port A & Port B address. -- -- Account for CE flag register delay, add 3rd BRAM address -- pipeline stage. -- --------------------------------------------------------------------------- GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate -- Port B pipeline stages only used in a dual port mode configuration. signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_B_d1 <= BRAM_Addr_B; BRAM_Addr_B_d2 <= BRAM_Addr_B_d1; BRAM_Addr_B_d3 <= BRAM_Addr_B_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_B_d1 <= BRAM_Addr_B_d1; BRAM_Addr_B_d2 <= BRAM_Addr_B_d2; BRAM_Addr_B_d3 <= BRAM_Addr_B_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin -- Only one active operation at a time. -- Use one deep address pipeline. Determine if Port A or B based on active read or write. FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A). -- During read operations, use 3-deep address pipeline to store address values (and from Port B). FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_DUAL; --------------------------------------------------------------------------- -- Generate: FAULT_INJECT -- Purpose: Implement fault injection registers -- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB) --------------------------------------------------------------------------- FAULT_INJECT : if C_HAS_FAULT_INJECT generate begin -- FaultInjectClr added to top level port list. -- Original LMB BRAM HDL -- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0'; --------------------------------------------------------------------------- -- Generate: GEN_32_FAULT -- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 32-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (25:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_32_FAULT; --------------------------------------------------------------------------- -- Generate: GEN_64_FAULT -- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 64-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (24:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_64_FAULT; -- v1.03a --------------------------------------------------------------------------- -- Generate: GEN_128_FAULT -- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0'; FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 128-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (96 to 127) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (64 to 95) <= RegWrData; elsif FaultInjectData_WE_2 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_3 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_128_FAULT; end generate FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: NO_FAULT_INJECT -- Purpose: Set default outputs when no fault inject capabilities. -- Remove check from C_WRITE_ACCESS (from LMB) --------------------------------------------------------------------------- NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate begin FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end generate NO_FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: CE_FAILING_REGISTERS -- Purpose: Implement Correctable Error First Failing Register --------------------------------------------------------------------------- CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate begin -- TBD (could come from axi_lite) -- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') -- else '0'; CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') else '0'; CE_FailingReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then CE_FailingAddress <= (others => '0'); -- Reserve for future support. -- CE_FailingData <= (others => '0'); elsif CE_Failing_We_i = '1' then --As the AXI Addr Width can now be lesser than 32, the address is getting shifted --Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000 CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0); --CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ; -- Reserve for future support. -- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1); end if; end if; end process CE_FailingReg; -- Note: Remove storage of CE_FFE & CE_FFD registers. -- Here for future support. -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_64; end generate CE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_CE_FAILING_REGISTERS -- Purpose: No Correctable Error Failing registers. --------------------------------------------------------------------------- NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate begin CE_FailingAddress <= (others => '0'); -- CE_FailingData <= (others => '0'); -- CE_FailingECC <= (others => '0'); end generate NO_CE_FAILING_REGISTERS; -- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0 -- This generate clause will never be evaluated. -- Here for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: UE_FAILING_REGISTERS -- -- Purpose: Implement Unorrectable Error First Failing Register -- --------------------------------------------------------------------------- -- -- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate -- begin -- -- -- TBD (could come from axi_lite) -- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- -- else '0'; -- -- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- else '0'; -- -- -- UE_FailingReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingAddress <= FailingAddr_Ld; -- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1); -- end if; -- end if; -- end process UE_FailingReg; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_64; -- -- end generate UE_FAILING_REGISTERS; -- -- -- --------------------------------------------------------------------------- -- -- Generate: NO_UE_FAILING_REGISTERS -- -- Purpose: No Uncorrectable Error Failing registers. -- --------------------------------------------------------------------------- -- -- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate -- begin -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- UE_FailingECC <= (others => '0'); -- end generate NO_UE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: ECC_STATUS_REGISTERS -- Purpose: Enable ECC status and interrupt enable registers. --------------------------------------------------------------------------- ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate begin ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE; ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE; StatusReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_StatusReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then -- CE Interrupt status bit if RegWrData(C_ECC_STATUS_CE) = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1' end if; -- UE Interrupt status bit if RegWrData(C_ECC_STATUS_UE) = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1' end if; else if Sl_CE = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs end if; if Sl_UE = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs end if; end if; end if; end process StatusReg; ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_EnableIRQReg <= (others => '0'); elsif ECC_EnableIRQReg_WE = '1' then -- CE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE); -- UE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE); end if; end if; end process EnableIRQReg; Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or (ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE)); --------------------------------------------------------------------------- -- Generate output flag for UE sticky bit -- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted. REG_UE : process (S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE or (Enable_ECC_i = '0') then ECC_UE_i <= '0'; elsif Sl_UE = '1' then ECC_UE_i <= '1'; elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then ECC_UE_i <= '0'; else ECC_UE_i <= ECC_UE_i; end if; end if; end process REG_UE; ECC_UE <= ECC_UE_i; --------------------------------------------------------------------------- end generate ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_ECC_STATUS_REGISTERS -- Purpose: No ECC status or interrupt registers enabled. --------------------------------------------------------------------------- NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate begin ECC_EnableIRQReg <= (others => '0'); ECC_StatusReg <= (others => '0'); Interrupt <= '0'; ECC_UE <= '0'; end generate NO_ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: GEN_ECC_ONOFF -- Purpose: Implement ECC on/off control register. --------------------------------------------------------------------------- GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate begin ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then if (C_ECC_ONOFF_RESET_VALUE = 0) then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; else ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1'; end if; -- ECC on by default at reset (but can be disabled) elsif ECC_OnOffReg_WE = '1' then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH); end if; end if; end process EnableIRQReg; Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH); Enable_ECC <= Enable_ECC_i; end generate GEN_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC_ONOFF -- Purpose: No ECC on/off control register. --------------------------------------------------------------------------- GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate begin Enable_ECC <= '0'; -- ECC ON/OFF register is only enabled when C_ECC = 1. -- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then -- ECC should be disabled. ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; end generate GEN_NO_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: CE_COUNTER -- Purpose: Enable Correctable Error Counter -- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits. -- Parameterized here for future enhancements. --------------------------------------------------------------------------- CE_COUNTER : if C_HAS_CE_COUNTER generate -- One extra bit compare to CE_CounterReg to handle carry bit signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31); begin CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0'; -- TBD (could come from axi_lite) -- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and -- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') -- else '0'; CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') else '0'; CountReg : process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then CE_CounterReg <= (others => '0'); elsif CE_CounterReg_WE = '1' then -- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1); CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31); elsif CE_CounterReg_Inc_i = '1' then CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31); end if; end if; end process CountReg; CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1); end generate CE_COUNTER; -- Note: Hit this generate when C_ECC = 0. -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: NO_CE_COUNTER -- -- Purpose: Default for no CE counter register. -- --------------------------------------------------------------------------- -- -- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate -- begin -- CE_CounterReg <= (others => '0'); -- end generate NO_CE_COUNTER; --------------------------------------------------------------------------- -- Generate: GEN_REG_32_DATA -- Purpose: Generate read register values & signal assignments based on -- 32-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress; when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_32_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_64_DATA -- Purpose: Generate read register values & signal assignments based on -- 64-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_64_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_128_DATA -- Purpose: Generate read register values & signal assignments based on -- 128-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95); when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_128_DATA; --------------------------------------------------------------------------- end architecture implementation;
library verilog; use verilog.vl_types.all; entity ln_x_controller is generic( RAEDY : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0); \INIT\ : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1); CALC_POW : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0); CALC_SUM : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi1) ); port( start : in vl_logic; clk : in vl_logic; reset : in vl_logic; init : out vl_logic; ldPow : out vl_logic; ldRes : out vl_logic; mul_mux : out vl_logic; add_or_sub : out vl_logic; ready : out vl_logic; rom_addr : out vl_logic_vector(3 downto 0) ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of RAEDY : constant is 2; attribute mti_svvh_generic_type of \INIT\ : constant is 2; attribute mti_svvh_generic_type of CALC_POW : constant is 2; attribute mti_svvh_generic_type of CALC_SUM : constant is 2; end ln_x_controller;
---------------------------------------------------------------------------------- -- Company: LARC - Escola Politecnica - University of Sao Paulo -- Engineer: Pedro Maat C. Massolino -- -- Create Date: 05/12/2012 -- Design Name: Syndrome_Calculator_N_Pipe -- Module Name: Syndrome_Calculator_N_Pipe -- Project Name: McEliece Goppa Decoder -- Target Devices: Any -- Tool versions: Xilinx ISE 13.3 WebPack -- -- Description: -- -- The 1st step in Goppa Code Decoding. -- -- This circuit computes the syndrome from the ciphertext, support elements and -- inverted evaluation of support elements into polynomial g, aka g(L)^(-1). -- This circuit works by computing the syndrome of only the positions where the ciphertext -- has value 1. -- -- This is circuit version with a variable number of computation units and a pipeline. -- A optimized version that loads and analyzes the ciphertext in a pipeline version is -- syndrome_calculator_n_pipe_v2. -- -- The circuits parameters -- -- number_of_units : -- -- The number of units that compute each syndrome at the same time. -- This number must be 1 or greater. -- -- gf_2_m : -- -- The size of the field used in this circuit. This parameter depends of the -- Goppa code used. -- -- length_codeword : -- -- The length of the codeword or in this case the ciphertext. Both the codeword -- and ciphertext has the same size. -- -- size_codeword : -- -- The number of bits necessary to hold the ciphertext/codeword. -- This is ceil(log2(length_codeword)). -- -- length_syndrome : -- -- The size of the syndrome array. This parameter depends of the -- Goppa code used. -- -- size_syndrome : -- -- The number of bits necessary to hold the array syndrome. -- This is ceil(log2(length_syndrome)). -- -- Dependencies: -- VHDL-93 -- IEEE.NUMERIC_STD_ALL; -- -- controller_syndrome_calculator_2_pipe Rev 1.0 -- register_nbits Rev 1.0 -- register_rst_nbits Rev 1.0 -- counter_rst_nbits Rev 1.0 -- counter_decrement_rst_nbits Rev 1.0 -- shift_register_rst_nbits Rev 1.0 -- mult_gf_2_m Rev 1.0 -- adder_gf_2_m Rev 1.0 -- -- Revision: -- Revision 1.0 -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity syndrome_calculator_n_pipe is Generic( -- GOPPA [2048, 1751, 27, 11] -- -- number_of_units : integer := 32; -- gf_2_m : integer range 1 to 20 := 11; -- length_codeword : integer := 2048; -- size_codeword : integer := 11; -- length_syndrome : integer := 54; -- size_syndrome : integer := 6 -- GOPPA [2048, 1498, 50, 11] -- -- number_of_units : integer := 32; -- gf_2_m : integer range 1 to 20 := 11; -- length_codeword : integer := 2048; -- size_codeword : integer := 11; -- length_syndrome : integer := 100; -- size_syndrome : integer := 7 -- QD-GOPPA [2528, 2144, 32, 12] -- -- number_of_units : integer := 32; -- gf_2_m : integer range 1 to 20 := 12; -- length_codeword : integer := 2528; -- size_codeword : integer := 12; -- length_syndrome : integer := 64; -- size_syndrome : integer := 6 -- QD-GOPPA [2816, 2048, 64, 12] -- -- number_of_units : integer := 32; -- gf_2_m : integer range 1 to 20 := 12; -- length_codeword : integer := 2816; -- size_codeword : integer := 12; -- length_syndrome : integer := 128; -- size_syndrome : integer := 7 -- QD-GOPPA [3328, 2560, 64, 12] -- -- number_of_units : integer := 32; -- gf_2_m : integer range 1 to 20 := 12; -- length_codeword : integer := 3200; -- size_codeword : integer := 12; -- length_syndrome : integer := 256; -- size_syndrome : integer := 8 -- QD-GOPPA [7296, 5632, 128, 13] -- number_of_units : integer := 32; gf_2_m : integer range 1 to 20 := 15; length_codeword : integer := 8320; size_codeword : integer := 14; length_syndrome : integer := 256; size_syndrome : integer := 8 ); Port( clk : in STD_LOGIC; rst : in STD_LOGIC; value_h : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0); value_L : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0); value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0); value_codeword : in STD_LOGIC_VECTOR(0 downto 0); syndrome_finalized : out STD_LOGIC; write_enable_new_syndrome : out STD_LOGIC; new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0); address_h : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0); address_L : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0); address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0); address_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0); address_new_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0) ); end syndrome_calculator_n_pipe; architecture Behavioral of syndrome_calculator_n_pipe is component controller_syndrome_calculator_2_pipe Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; almost_units_ready : in STD_LOGIC; empty_units : in STD_LOGIC; limit_ctr_codeword_q : in STD_LOGIC; limit_ctr_syndrome_q : in STD_LOGIC; reg_first_syndrome_q : in STD_LOGIC_VECTOR(0 downto 0); reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0); syndrome_finalized : out STD_LOGIC; write_enable_new_syndrome : out STD_LOGIC; control_units_ce : out STD_LOGIC; control_units_rst : out STD_LOGIC; int_reg_L_ce : out STD_LOGIC; int_square_h : out STD_LOGIC; int_reg_h_ce : out STD_LOGIC; int_reg_h_rst : out STD_LOGIC; int_sel_reg_h : out STD_LOGIC; reg_load_syndrome_ce : out STD_LOGIC; reg_load_syndrome_rst : out STD_LOGIC; reg_new_value_syndrome_ce : out STD_LOGIC; reg_codeword_ce : out STD_LOGIC; reg_first_syndrome_ce : out STD_LOGIC; reg_first_syndrome_rst : out STD_LOGIC; ctr_load_address_syndrome_ce : out STD_LOGIC; ctr_load_address_syndrome_rst : out STD_LOGIC; reg_bus_address_syndrome_ce : out STD_LOGIC; reg_calc_address_syndrome_ce : out STD_LOGIC; reg_store_address_syndrome_ce : out STD_LOGIC; ctr_load_address_codeword_ce : out STD_LOGIC; ctr_load_address_codeword_rst : out STD_LOGIC ); end component; component register_nbits Generic (size : integer); Port ( d : in STD_LOGIC_VECTOR ((size - 1) downto 0); clk : in STD_LOGIC; ce : in STD_LOGIC; q : out STD_LOGIC_VECTOR ((size - 1) downto 0) ); end component; component register_rst_nbits Generic (size : integer); Port ( d : in STD_LOGIC_VECTOR ((size - 1) downto 0); clk : in STD_LOGIC; ce : in STD_LOGIC; rst : in STD_LOGIC; rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0); q : out STD_LOGIC_VECTOR ((size - 1) downto 0) ); end component; component counter_rst_nbits Generic ( size : integer; increment_value : integer ); Port ( clk : in STD_LOGIC; ce : in STD_LOGIC; rst : in STD_LOGIC; rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0); q : out STD_LOGIC_VECTOR ((size - 1) downto 0) ); end component; component counter_decrement_rst_nbits Generic ( size : integer; decrement_value : integer ); Port ( clk : in STD_LOGIC; ce : in STD_LOGIC; rst : in STD_LOGIC; rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0); q : out STD_LOGIC_VECTOR((size - 1) downto 0) ); end component; component shift_register_rst_nbits Generic (size : integer); Port ( data_in : in STD_LOGIC; clk : in STD_LOGIC; ce : in STD_LOGIC; rst : in STD_LOGIC; rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0); q : out STD_LOGIC_VECTOR((size - 1) downto 0); data_out : out STD_LOGIC ); end component; component mult_gf_2_m Generic (gf_2_m : integer range 1 to 20 := 11); Port( a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0); b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0); o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) ); end component; component adder_gf_2_m Generic( gf_2_m : integer := 1; number_of_elements : integer range 2 to integer'high := 2 ); Port( a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0); o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) ); end component; signal reg_L_d : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0); signal reg_L_ce : STD_LOGIC_VECTOR((number_of_units - 1) downto 0); signal reg_L_q : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0); signal reg_h_d :STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0); signal reg_h_ce : STD_LOGIC_VECTOR((number_of_units - 1) downto 0); signal reg_h_rst : STD_LOGIC_VECTOR((number_of_units - 1) downto 0); constant reg_h_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0'); signal reg_h_q : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0); signal sel_reg_h : STD_LOGIC_VECTOR((number_of_units - 1) downto 0); signal square_h : STD_LOGIC_VECTOR((number_of_units - 1) downto 0); signal reg_load_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0); signal reg_load_syndrome_ce : STD_LOGIC; signal reg_load_syndrome_rst : STD_LOGIC; constant reg_load_syndrome_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m)); signal reg_load_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0); signal reg_new_value_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0); signal reg_new_value_syndrome_ce : STD_LOGIC; signal reg_new_value_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0); signal reg_codeword_d : STD_LOGIC_VECTOR(0 downto 0); signal reg_codeword_ce : STD_LOGIC; signal reg_codeword_q : STD_LOGIC_VECTOR(0 downto 0); signal reg_first_syndrome_d : STD_LOGIC_VECTOR(0 downto 0); signal reg_first_syndrome_ce : STD_LOGIC; signal reg_first_syndrome_rst : STD_LOGIC; constant reg_first_syndrome_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "1"; signal reg_first_syndrome_q : STD_LOGIC_VECTOR(0 downto 0); signal mult_a : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0); signal mult_b : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0); signal mult_o : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0); signal adder_a : STD_LOGIC_VECTOR(((number_of_units+1)*gf_2_m - 1) downto 0); signal adder_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0); signal ctr_load_address_syndrome_ce : STD_LOGIC; signal ctr_load_address_syndrome_rst : STD_LOGIC; constant ctr_load_address_syndrome_rst_value : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0) := std_logic_vector(to_unsigned(length_syndrome - 1, size_syndrome)); signal ctr_load_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0); signal reg_bus_address_syndrome_d : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0); signal reg_bus_address_syndrome_ce : STD_LOGIC; signal reg_bus_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0); signal reg_calc_address_syndrome_d : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0); signal reg_calc_address_syndrome_ce : STD_LOGIC; signal reg_calc_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0); signal reg_store_address_syndrome_d : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0); signal reg_store_address_syndrome_ce : STD_LOGIC; signal reg_store_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0); signal ctr_load_address_codeword_ce : STD_LOGIC; signal ctr_load_address_codeword_rst : STD_LOGIC; constant ctr_load_address_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - 1) downto 0) := std_logic_vector(to_unsigned(0, size_codeword)); signal ctr_load_address_codeword_q : STD_LOGIC_VECTOR((size_codeword - 1) downto 0); signal control_units_ce : STD_LOGIC; signal control_units_rst : STD_LOGIC; constant control_units_rst_value0 : STD_LOGIC_VECTOR((number_of_units - 1) downto 0) := (others => '0'); constant control_units_rst_value1 : STD_LOGIC_VECTOR((number_of_units) downto (number_of_units)) := "1"; constant control_units_rst_value : STD_LOGIC_VECTOR((number_of_units) downto 0) := control_units_rst_value1 & control_units_rst_value0; signal control_units_q : STD_LOGIC_VECTOR((number_of_units) downto 0); signal control_units_data_out : STD_LOGIC; signal int_reg_L_ce : STD_LOGIC; signal int_square_h : STD_LOGIC; signal int_reg_h_ce : STD_LOGIC; signal int_reg_h_rst: STD_LOGIC; signal int_sel_reg_h : STD_LOGIC; signal almost_units_ready : STD_LOGIC; signal empty_units : STD_LOGIC; signal limit_ctr_codeword_q : STD_LOGIC; signal limit_ctr_syndrome_q : STD_LOGIC; begin controller : controller_syndrome_calculator_2_pipe Port Map( clk => clk, rst => rst, almost_units_ready => almost_units_ready, empty_units => empty_units, limit_ctr_codeword_q => limit_ctr_codeword_q, limit_ctr_syndrome_q => limit_ctr_syndrome_q, reg_first_syndrome_q => reg_first_syndrome_q, reg_codeword_q => reg_codeword_q, syndrome_finalized => syndrome_finalized, write_enable_new_syndrome => write_enable_new_syndrome, control_units_ce => control_units_ce, control_units_rst => control_units_rst, int_reg_L_ce => int_reg_L_ce, int_square_h => int_square_h, int_reg_h_ce => int_reg_h_ce, int_reg_h_rst => int_reg_h_rst, int_sel_reg_h => int_sel_reg_h, reg_load_syndrome_ce => reg_load_syndrome_ce, reg_load_syndrome_rst => reg_load_syndrome_rst, reg_new_value_syndrome_ce => reg_new_value_syndrome_ce, reg_codeword_ce => reg_codeword_ce, reg_first_syndrome_ce => reg_first_syndrome_ce, reg_first_syndrome_rst => reg_first_syndrome_rst, ctr_load_address_syndrome_ce => ctr_load_address_syndrome_ce, ctr_load_address_syndrome_rst => ctr_load_address_syndrome_rst, reg_bus_address_syndrome_ce => reg_bus_address_syndrome_ce, reg_calc_address_syndrome_ce => reg_calc_address_syndrome_ce, reg_store_address_syndrome_ce => reg_store_address_syndrome_ce, ctr_load_address_codeword_ce => ctr_load_address_codeword_ce, ctr_load_address_codeword_rst => ctr_load_address_codeword_rst ); calculator_units : for I in 0 to (number_of_units - 1) generate reg_L_I : register_nbits Generic Map( size => gf_2_m ) Port Map( d => reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m), clk => clk, ce => reg_L_ce(I), q => reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m) ); reg_h_I : register_rst_nbits Generic Map( size => gf_2_m ) Port Map( d => reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m), clk => clk, ce => reg_h_ce(I), rst => reg_h_rst(I), rst_value => reg_h_rst_value, q => reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m) ); mult_I : mult_gf_2_m Generic Map( gf_2_m => gf_2_m ) Port Map( a => mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m), b => mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m), o => mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m) ); reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= value_L; reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when sel_reg_h(I) = '1' else value_h; mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when square_h(I) = '1' else reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m); mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m); reg_L_ce(I) <= int_reg_L_ce and control_units_q(I); square_h(I) <= int_square_h and control_units_q(I); reg_h_ce(I) <= int_reg_h_ce and (control_units_q(I) or (int_sel_reg_h and (not int_square_h))); reg_h_rst(I) <= int_reg_h_rst and control_units_q(I); sel_reg_h(I) <= int_sel_reg_h; end generate; control_units : shift_register_rst_nbits Generic Map( size => number_of_units+1 ) Port Map( data_in => control_units_data_out, clk => clk, ce => control_units_ce, rst => control_units_rst, rst_value => control_units_rst_value, q => control_units_q, data_out => control_units_data_out ); adder : adder_gf_2_m Generic Map( gf_2_m => gf_2_m, number_of_elements => number_of_units+1 ) Port Map( a => adder_a, o => adder_o ); reg_load_syndrome : register_rst_nbits Generic Map( size => gf_2_m ) Port Map( d => reg_load_syndrome_d, clk => clk, ce => reg_load_syndrome_ce, rst => reg_load_syndrome_rst, rst_value => reg_load_syndrome_rst_value, q => reg_load_syndrome_q ); reg_new_value_syndrome : register_nbits Generic Map( size => gf_2_m ) Port Map( d => reg_new_value_syndrome_d, clk => clk, ce => reg_new_value_syndrome_ce, q => reg_new_value_syndrome_q ); reg_codeword : register_nbits Generic Map( size => 1 ) Port Map( d => reg_codeword_d, clk => clk, ce => reg_codeword_ce, q => reg_codeword_q ); reg_first_syndrome : register_rst_nbits Generic Map( size => 1 ) Port Map( d => reg_first_syndrome_d, clk => clk, ce => reg_first_syndrome_ce, rst => reg_first_syndrome_rst, rst_value => reg_first_syndrome_rst_value, q => reg_first_syndrome_q ); ctr_load_address_syndrome : counter_decrement_rst_nbits Generic Map( size => size_syndrome, decrement_value => 1 ) Port Map( clk => clk, ce => ctr_load_address_syndrome_ce, rst => ctr_load_address_syndrome_rst, rst_value => ctr_load_address_syndrome_rst_value, q => ctr_load_address_syndrome_q ); reg_bus_address_syndrome : register_nbits Generic Map( size => size_syndrome ) Port Map( d => reg_bus_address_syndrome_d, clk => clk, ce => reg_bus_address_syndrome_ce, q => reg_bus_address_syndrome_q ); reg_calc_address_syndrome : register_nbits Generic Map( size => size_syndrome ) Port Map( d => reg_calc_address_syndrome_d, clk => clk, ce => reg_calc_address_syndrome_ce, q => reg_calc_address_syndrome_q ); reg_store_address_syndrome : register_nbits Generic Map( size => size_syndrome ) Port Map( d => reg_store_address_syndrome_d, clk => clk, ce => reg_store_address_syndrome_ce, q => reg_store_address_syndrome_q ); ctr_load_address_codeword : counter_rst_nbits Generic Map( size => size_codeword, increment_value => 1 ) Port Map( clk => clk, ce => ctr_load_address_codeword_ce, rst => ctr_load_address_codeword_rst, rst_value => ctr_load_address_codeword_rst_value, q => ctr_load_address_codeword_q ); adder_a <= reg_h_q & reg_load_syndrome_q; reg_load_syndrome_d <= value_syndrome; reg_codeword_d <= value_codeword; reg_first_syndrome_d <= "0"; reg_new_value_syndrome_d <= adder_o; new_value_syndrome <= reg_new_value_syndrome_q; reg_bus_address_syndrome_d <= ctr_load_address_syndrome_q; reg_calc_address_syndrome_d <= reg_bus_address_syndrome_q; reg_store_address_syndrome_d <= reg_calc_address_syndrome_q; address_h <= ctr_load_address_codeword_q; address_L <= ctr_load_address_codeword_q; address_codeword <= ctr_load_address_codeword_q; address_syndrome <= ctr_load_address_syndrome_q; address_new_syndrome <= reg_store_address_syndrome_q; almost_units_ready <= control_units_q(number_of_units - 1); empty_units <= control_units_q(0); limit_ctr_codeword_q <= '1' when (ctr_load_address_codeword_q = std_logic_vector(to_unsigned(length_codeword - 1, ctr_load_address_codeword_q'length))) else '0'; limit_ctr_syndrome_q <= '1' when (reg_store_address_syndrome_q = std_logic_vector(to_unsigned(0, ctr_load_address_syndrome_q'length))) else '0'; end Behavioral;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;