content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipeline : natural := 0;
width : natural := 24);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 24,
decode => "000000000000000000001111",
pipeline => 0)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipeline : natural := 0;
width : natural := 24);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 24,
decode => "000000000000000000001111",
pipeline => 0)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipeline : natural := 0;
width : natural := 24);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 24,
decode => "000000000000000000001111",
pipeline => 0)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; |
-------------------------------------------------------------------------------
-- Title : Direct Digital Synthesis
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : DDS with RAM Table, Table can be defined over MM Interface
-- The Phase Incremen can also be set over an extra MM Interface
-------------------------------------------------------------------------------
architecture Rtl of Dds is
-- RAM
subtype entry_t is u_sfixed(0 downto -(wave_table_width_g-1));
type memory_t is array (wave_table_len_g-1 downto 0) of entry_t;
function init_ram
return memory_t is
variable tmp : memory_t := (others => (others => '0'));
begin
if wave_table_len_g = 4096 then
for idx in 0 to wave_table_len_g-1 loop
-- init rom with gWaveTable values
tmp(idx) := to_sfixed(sin_table_c(idx), 0, -(wave_table_width_g-1));
end loop;
end if;
return tmp;
end init_ram;
-- doesn't work with init ram function, quartus generates no memory
signal wave_table : memory_t;-- := init_ram;
--attribute ramstyle : string;
--attribute ramstyle of wave_table : signal is "MLAB";
signal ram_addr : natural range 0 to wave_table'length-1;
signal ram_d : entry_t;
-- phase increment register
signal phase_inc : natural range 0 to 2**phase_bits_g;
-- phase register
signal phase : unsigned(phase_bits_g-1 downto 0);
-- enable register
signal enable : std_ulogic;
-- output signal
signal dds_data : u_sfixed(0 downto -(data_width_g-1));
begin -- architecture rtl
-----------------------------------------------------------------------------
-- RAM
-- write ram
ram_wr : process (csi_clk) is
begin -- process ram_wr
if rising_edge(csi_clk) then -- rising clock edge
if avs_s0_write = '1' then
wave_table(to_integer(unsigned(avs_s0_address))) <=
to_sfixed(avs_s0_writedata(wave_table_width_g-1 downto 0), wave_table(0));
end if;
end if;
end process ram_wr;
-- read ram
ram_rd : process (csi_clk) is
begin -- process ram_rd
if rising_edge(csi_clk) then -- rising clock edge
ram_d <= wave_table(ram_addr);
end if;
end process ram_rd;
-----------------------------------------------------------------------------
-- Avalon MM Slave Port s1
-- phase increment register
phase_inc_reg : process (csi_clk, rsi_reset_n) is
begin -- process phase_inc_reg
if rsi_reset_n = '0' then -- asynchronous reset (active low)
phase_inc <= 0;
enable <= '0';
elsif rising_edge(csi_clk) then -- rising clock edge
if avs_s1_write = '1' then
case avs_s1_address is
when '0' => enable <= avs_s1_writedata(0);
when '1' => phase_inc <= to_integer(unsigned(avs_s1_writedata));
when others => null;
end case;
end if;
end if;
end process phase_inc_reg;
-----------------------------------------------------------------------------
-- Avalon ST source
aso_data <= to_slv(dds_data) when enable = '1' else (others => '0');
aso_valid <= coe_sample_strobe;
-----------------------------------------------------------------------------
-- DDS
-- calculate next phase
phase_calc : process (csi_clk, rsi_reset_n) is
begin -- process phase_cals
if rsi_reset_n = '0' then -- asynchronous reset (active low)
phase <= to_unsigned(0, phase'length);
elsif rising_edge(csi_clk) then -- rising clock edge
if coe_sample_strobe = '1' then
phase <= phase + phase_inc;
end if;
if enable = '0' then
phase <= to_unsigned(0, phase'length);
end if;
end if;
end process phase_calc;
-- calculate wave table address from phase
ram_addr <= to_integer(phase(phase'left downto phase'right + phase_dither_g));
-- resize data read from ram to size of output data
dds_data <= resize(ram_d, dds_data'left, dds_data'right);
-----------------------------------------------------------------------------
end architecture rtl;
|
entity test is
end test;
architecture only of test is
type my_type is array(0 to 3) of integer;
begin -- only
p: process
begin -- process p
assert my_type'left = 0 report "TEST FAILED left = 0" severity failure;
report "TEST PASSED left = 0";
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type my_type is array(0 to 3) of integer;
begin -- only
p: process
begin -- process p
assert my_type'left = 0 report "TEST FAILED left = 0" severity failure;
report "TEST PASSED left = 0";
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type my_type is array(0 to 3) of integer;
begin -- only
p: process
begin -- process p
assert my_type'left = 0 report "TEST FAILED left = 0" severity failure;
report "TEST PASSED left = 0";
wait;
end process p;
end only;
|
library ieee;
use ieee.std_logic_1164.all;
use work.graphics_types_pkg.all;
use work.sprites_pkg.all;
use work.colors_pkg.all;
use work.basic_types_pkg.all;
-- It is worth noting that the sprites engine should not (and does not) access
-- any game-specific constants or code. Therefore, it can be readily reused
-- accross games without any modification. The only game-dependent values are
-- given as generics when the module is instantiated.
entity sprites_engine is
generic (
SPRITES_INITIAL_VALUES: sprites_array_type;
SPRITES_COLLISION_QUERY: sprite_collision_query_type
);
port (
clock: in std_logic;
reset: in std_logic;
raster_position: point_type;
sprites_coordinates: in point_array_type(SPRITES_INITIAL_VALUES'range);
sprites_enabled: in bool_vector(SPRITES_INITIAL_VALUES'range);
sprite_pixel: out palette_color_type;
sprite_pixel_is_valid: out boolean;
sprite_collisions_results: out bool_vector
);
end;
architecture rtl of sprites_engine is
signal sprites: sprites_array_type(SPRITES_INITIAL_VALUES'range);
begin
sprite_collisions_results <= get_sprites_collisions(sprites, SPRITES_COLLISION_QUERY);
update_sprites: process (clock, reset) begin
for i in sprites'range loop
if reset then
sprites(i) <= SPRITES_INITIAL_VALUES(i);
elsif rising_edge(clock) then
sprites(i) <= update_sprite(
sprites(i),
raster_position,
sprites_coordinates(i),
sprites_enabled(i)
);
end if;
end loop;
end process;
generate_output_pixel: process (clock, reset) is
variable pixel_is_valid: boolean := false;
variable pixel_color: palette_color_type;
begin
if reset then
sprite_pixel <= PC_TRANSPARENT;
sprite_pixel_is_valid <= false;
elsif rising_edge(clock) then
sprite_pixel <= PC_TRANSPARENT;
pixel_is_valid := false;
for i in sprites'range loop
-- if sprite_contains_coordinate(sprites(i), raster_position) then
-- only enabled sprites are drawn
if sprites(i).enabled and sprite_contains_coordinate(sprites(i), raster_position) then
pixel_color := get_sprite_pixel(sprites(i), raster_position);
if pixel_color /= PC_TRANSPARENT then
sprite_pixel <= get_sprite_pixel(sprites(i), raster_position);
pixel_is_valid := true;
end if;
end if;
end loop;
sprite_pixel_is_valid <= pixel_is_valid;
end if;
end process;
end;
|
-- file: Clock_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity Clock_tb is
end Clock_tb;
architecture test of Clock_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 20.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(4 downto 1);
-- Status and control signals
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(4 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component Clock_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(4 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(4 downto 1);
-- Status and control signals
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
wait until LOCKED = '1';
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
process (CLK_IN1)
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
if (CLK_IN1'event and CLK_IN1='1') then
timeout_counter <= timeout_counter + '1';
if (timeout_counter = "10000000000000") then
if (LOCKED /= '1') then
simtimeprint;
report "NO LOCK signal" severity failure;
end if;
end if;
end if;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : Clock_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
LOCKED => LOCKED);
-- Freq Check
end test;
|
-- Company:
-- Engineer:
--
-- Create Date: 16:52:41 06/05/2016
-- Design Name:
-- Module Name: mem_control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mem_control is
port(
IR: in std_logic_vector(7 downto 0);
CONT: in std_logic_vector(2 downto 0);
salida_mem_control : out std_logic_vector(24 downto 0)
);
end mem_control;
architecture Behavioral of mem_control is
signal señales_de_control : std_logic_vector(27 downto 0);
begin
señales_de_control <= X"0050100" WHEN IR&CONT = "00000000000" ELSE
X"0004000" WHEN IR&CONT = "00000000001" ELSE
X"0802000" WHEN IR&CONT = "00000000010" ELSE
X"0050100" WHEN IR&CONT = "00000001000" ELSE
X"0004000" WHEN IR&CONT = "00000001001" ELSE
X"0802001" WHEN IR&CONT = "00000001010" ELSE
X"0050100" WHEN IR&CONT = "00000010000" ELSE
X"0004000" WHEN IR&CONT = "00000010001" ELSE
X"0802002" WHEN IR&CONT = "00000010010" ELSE
X"0050100" WHEN IR&CONT = "00000011000" ELSE
X"0004000" WHEN IR&CONT = "00000011001" ELSE
X"0050100" WHEN IR&CONT = "00000011010" ELSE
X"0008000" WHEN IR&CONT = "00000011011" ELSE
X"0802003" WHEN IR&CONT = "00000011100" ELSE
X"0050100" WHEN IR&CONT = "00000100000" ELSE
X"0004000" WHEN IR&CONT = "00000100001" ELSE
X"0801004" WHEN IR&CONT = "00000100010" ELSE
X"0050100" WHEN IR&CONT = "00000101000" ELSE
X"0004000" WHEN IR&CONT = "00000101001" ELSE
X"0801005" WHEN IR&CONT = "00000101010" ELSE
X"0050100" WHEN IR&CONT = "00000110000" ELSE
X"0004000" WHEN IR&CONT = "00000110001" ELSE
X"0801006" WHEN IR&CONT = "00000110010" ELSE
X"0050100" WHEN IR&CONT = "00000111000" ELSE
X"0004000" WHEN IR&CONT = "00000111001" ELSE
X"0050100" WHEN IR&CONT = "00000111010" ELSE
X"0008000" WHEN IR&CONT = "00000111011" ELSE
X"0801007" WHEN IR&CONT = "00000111100" ELSE
X"0050100" WHEN IR&CONT = "00001000000" ELSE
X"0004000" WHEN IR&CONT = "00001000001" ELSE
X"0800808" WHEN IR&CONT = "00001000010" ELSE
X"0050100" WHEN IR&CONT = "00001001000" ELSE
X"0004000" WHEN IR&CONT = "00001001001" ELSE
X"0800809" WHEN IR&CONT = "00001001010" ELSE
X"0050100" WHEN IR&CONT = "00001010000" ELSE
X"0004000" WHEN IR&CONT = "00001010001" ELSE
X"080080A" WHEN IR&CONT = "00001010010" ELSE
X"0050100" WHEN IR&CONT = "00001011000" ELSE
X"0004000" WHEN IR&CONT = "00001011001" ELSE
X"0050100" WHEN IR&CONT = "00001011010" ELSE
X"0008000" WHEN IR&CONT = "00001011011" ELSE
X"080080B" WHEN IR&CONT = "00001011100" ELSE
X"0050100" WHEN IR&CONT = "00010011000" ELSE
X"0004000" WHEN IR&CONT = "00010011001" ELSE
X"0050100" WHEN IR&CONT = "00010011010" ELSE
X"0008000" WHEN IR&CONT = "00010011011" ELSE
X"0010020" WHEN IR&CONT = "00010011100" ELSE
X"0008000" WHEN IR&CONT = "00010011101" ELSE
X"0802003" WHEN IR&CONT = "00010011110" ELSE
X"0050100" WHEN IR&CONT = "00011100000" ELSE
X"0004000" WHEN IR&CONT = "00011100001" ELSE
X"0050100" WHEN IR&CONT = "00011100010" ELSE
X"0008000" WHEN IR&CONT = "00011100011" ELSE
X"0010020" WHEN IR&CONT = "00011100100" ELSE
X"0008010" WHEN IR&CONT = "00011100101" ELSE
X"0800200" WHEN IR&CONT = "00011100110" ELSE
X"0050100" WHEN IR&CONT = "00010111000" ELSE
X"0004000" WHEN IR&CONT = "00010111001" ELSE
X"0050100" WHEN IR&CONT = "00010111010" ELSE
X"0008000" WHEN IR&CONT = "00010111011" ELSE
X"0010020" WHEN IR&CONT = "00010111100" ELSE
X"0008000" WHEN IR&CONT = "00010111101" ELSE
X"0801007" WHEN IR&CONT = "00010111110" ELSE
X"0050100" WHEN IR&CONT = "00011101000" ELSE
X"0004000" WHEN IR&CONT = "00011101001" ELSE
X"0050100" WHEN IR&CONT = "00011101010" ELSE
X"0008000" WHEN IR&CONT = "00011101011" ELSE
X"0010020" WHEN IR&CONT = "00011101100" ELSE
X"0008015" WHEN IR&CONT = "00011101101" ELSE
X"0800200" WHEN IR&CONT = "00011101110" ELSE
X"0050100" WHEN IR&CONT = "00011011000" ELSE
X"0004000" WHEN IR&CONT = "00011011001" ELSE
X"0050100" WHEN IR&CONT = "00011011010" ELSE
X"0008000" WHEN IR&CONT = "00011011011" ELSE
X"0010020" WHEN IR&CONT = "00011011100" ELSE
X"0008000" WHEN IR&CONT = "00011011101" ELSE
X"080080B" WHEN IR&CONT = "00011011110" ELSE
X"0050100" WHEN IR&CONT = "00011110000" ELSE
X"0004000" WHEN IR&CONT = "00011110001" ELSE
X"0050100" WHEN IR&CONT = "00011110010" ELSE
X"0008000" WHEN IR&CONT = "00011110011" ELSE
X"0010020" WHEN IR&CONT = "00011110100" ELSE
X"000801A" WHEN IR&CONT = "00011110101" ELSE
X"0800200" WHEN IR&CONT = "00011110110" ELSE
X"0050100" WHEN IR&CONT = "00100000000" ELSE
X"0004000" WHEN IR&CONT = "00100000001" ELSE
X"0820000" WHEN IR&CONT = "00100000010" ELSE
X"0050100" WHEN IR&CONT = "00100001000" ELSE
X"0004000" WHEN IR&CONT = "00100001001" ELSE
X"0820000" WHEN IR&CONT = "00100001010" ELSE
X"0050100" WHEN IR&CONT = "00100010000" ELSE
X"0004000" WHEN IR&CONT = "00100010001" ELSE
X"0820000" WHEN IR&CONT = "00100010010" ELSE
X"0050100" WHEN IR&CONT = "00100011000" ELSE
X"0004000" WHEN IR&CONT = "00100011001" ELSE
X"0820000" WHEN IR&CONT = "00100011010" ELSE
X"0050100" WHEN IR&CONT = "00100100000" ELSE
X"0004000" WHEN IR&CONT = "00100100001" ELSE
X"0820000" WHEN IR&CONT = "00100100010" ELSE
X"0050100" WHEN IR&CONT = "00100101000" ELSE
X"0004000" WHEN IR&CONT = "00100101001" ELSE
X"0820000" WHEN IR&CONT = "00100101010" ELSE
X"0050100" WHEN IR&CONT = "00100110000" ELSE
X"0004000" WHEN IR&CONT = "00100110001" ELSE
X"0820000" WHEN IR&CONT = "00100110010" ELSE
X"0050100" WHEN IR&CONT = "00100111000" ELSE
X"0004000" WHEN IR&CONT = "00100111001" ELSE
X"0820000" WHEN IR&CONT = "00100111010" ELSE
X"0050100" WHEN IR&CONT = "00101000000" ELSE
X"0004000" WHEN IR&CONT = "00101000001" ELSE
X"0820000" WHEN IR&CONT = "00101000010" ELSE
X"0050100" WHEN IR&CONT = "00101001000" ELSE
X"0004000" WHEN IR&CONT = "00101001001" ELSE
X"0820000" WHEN IR&CONT = "00101001010" ELSE
X"0050100" WHEN IR&CONT = "00101010000" ELSE
X"0004000" WHEN IR&CONT = "00101010001" ELSE
X"0820000" WHEN IR&CONT = "00101010010" ELSE
X"0050100" WHEN IR&CONT = "00101011000" ELSE
X"0004000" WHEN IR&CONT = "00101011001" ELSE
X"0820000" WHEN IR&CONT = "00101011010" ELSE
X"0050100" WHEN IR&CONT = "00101100000" ELSE
X"0004000" WHEN IR&CONT = "00101100001" ELSE
X"0820000" WHEN IR&CONT = "00101100010" ELSE
X"0050100" WHEN IR&CONT = "00101101000" ELSE
X"0004000" WHEN IR&CONT = "00101101001" ELSE
X"0820000" WHEN IR&CONT = "00101101010" ELSE
X"0050100" WHEN IR&CONT = "00101110000" ELSE
X"0004000" WHEN IR&CONT = "00101110001" ELSE
X"0820000" WHEN IR&CONT = "00101110010" ELSE
X"0050100" WHEN IR&CONT = "00101111000" ELSE
X"0004000" WHEN IR&CONT = "00101111001" ELSE
X"0820000" WHEN IR&CONT = "00101111010" ELSE
X"0050100" WHEN IR&CONT = "00110000000" ELSE
X"0004000" WHEN IR&CONT = "00110000001" ELSE
X"0882000" WHEN IR&CONT = "00110000010" ELSE
X"0050100" WHEN IR&CONT = "00110001000" ELSE
X"0004000" WHEN IR&CONT = "00110001001" ELSE
X"0882001" WHEN IR&CONT = "00110001010" ELSE
X"0050100" WHEN IR&CONT = "00110010000" ELSE
X"0004000" WHEN IR&CONT = "00110010001" ELSE
X"0882002" WHEN IR&CONT = "00110010010" ELSE
X"0050100" WHEN IR&CONT = "00110011000" ELSE
X"0004000" WHEN IR&CONT = "00110011001" ELSE
X"0050100" WHEN IR&CONT = "00110011010" ELSE
X"0008000" WHEN IR&CONT = "00110011011" ELSE
X"0882003" WHEN IR&CONT = "00110011100" ELSE
X"0050100" WHEN IR&CONT = "00110100000" ELSE
X"0004000" WHEN IR&CONT = "00110100001" ELSE
X"0881004" WHEN IR&CONT = "00110100010" ELSE
X"0050100" WHEN IR&CONT = "00110101000" ELSE
X"0004000" WHEN IR&CONT = "00110101001" ELSE
X"0881005" WHEN IR&CONT = "00110101010" ELSE
X"0050100" WHEN IR&CONT = "00110110000" ELSE
X"0004000" WHEN IR&CONT = "00110110001" ELSE
X"0881006" WHEN IR&CONT = "00110110010" ELSE
X"0050100" WHEN IR&CONT = "00110111000" ELSE
X"0004000" WHEN IR&CONT = "00110111001" ELSE
X"0050100" WHEN IR&CONT = "00110111010" ELSE
X"0008000" WHEN IR&CONT = "00110111011" ELSE
X"0881007" WHEN IR&CONT = "00110111100" ELSE
X"0050100" WHEN IR&CONT = "00111000000" ELSE
X"0004000" WHEN IR&CONT = "00111000001" ELSE
X"0880808" WHEN IR&CONT = "00111000010" ELSE
X"0050100" WHEN IR&CONT = "00111001000" ELSE
X"0004000" WHEN IR&CONT = "00111001001" ELSE
X"0880809" WHEN IR&CONT = "00111001010" ELSE
X"0050100" WHEN IR&CONT = "00111010000" ELSE
X"0004000" WHEN IR&CONT = "00111010001" ELSE
X"088080A" WHEN IR&CONT = "00111010010" ELSE
X"0050100" WHEN IR&CONT = "00111011000" ELSE
X"0004000" WHEN IR&CONT = "00111011001" ELSE
X"0050100" WHEN IR&CONT = "00111011010" ELSE
X"0008000" WHEN IR&CONT = "00111011011" ELSE
X"088080B" WHEN IR&CONT = "00111011100" ELSE
X"0050100" WHEN IR&CONT = "01000000000" ELSE
X"0004000" WHEN IR&CONT = "01000000001" ELSE
X"0902000" WHEN IR&CONT = "01000000010" ELSE
X"0050100" WHEN IR&CONT = "01000001000" ELSE
X"0004000" WHEN IR&CONT = "01000001001" ELSE
X"0902001" WHEN IR&CONT = "01000001010" ELSE
X"0050100" WHEN IR&CONT = "01000010000" ELSE
X"0004000" WHEN IR&CONT = "01000010001" ELSE
X"0902002" WHEN IR&CONT = "01000010010" ELSE
X"0050100" WHEN IR&CONT = "01000011000" ELSE
X"0004000" WHEN IR&CONT = "01000011001" ELSE
X"0050100" WHEN IR&CONT = "01000011010" ELSE
X"0008000" WHEN IR&CONT = "01000011011" ELSE
X"0902003" WHEN IR&CONT = "01000011100" ELSE
X"0050100" WHEN IR&CONT = "01000100000" ELSE
X"0004000" WHEN IR&CONT = "01000100001" ELSE
X"0901004" WHEN IR&CONT = "01000100010" ELSE
X"0050100" WHEN IR&CONT = "01000101000" ELSE
X"0004000" WHEN IR&CONT = "01000101001" ELSE
X"0901005" WHEN IR&CONT = "01000101010" ELSE
X"0050100" WHEN IR&CONT = "01000110000" ELSE
X"0004000" WHEN IR&CONT = "01000110001" ELSE
X"0901006" WHEN IR&CONT = "01000110010" ELSE
X"0050100" WHEN IR&CONT = "01000111000" ELSE
X"0004000" WHEN IR&CONT = "01000111001" ELSE
X"0050100" WHEN IR&CONT = "01000111010" ELSE
X"0008000" WHEN IR&CONT = "01000111011" ELSE
X"0901007" WHEN IR&CONT = "01000111100" ELSE
X"0050100" WHEN IR&CONT = "01001000000" ELSE
X"0004000" WHEN IR&CONT = "01001000001" ELSE
X"0900808" WHEN IR&CONT = "01001000010" ELSE
X"0050100" WHEN IR&CONT = "01001001000" ELSE
X"0004000" WHEN IR&CONT = "01001001001" ELSE
X"0900809" WHEN IR&CONT = "01001001010" ELSE
X"0050100" WHEN IR&CONT = "01001010000" ELSE
X"0004000" WHEN IR&CONT = "01001010001" ELSE
X"090080A" WHEN IR&CONT = "01001010010" ELSE
X"0050100" WHEN IR&CONT = "01001011000" ELSE
X"0004000" WHEN IR&CONT = "01001011001" ELSE
X"0050100" WHEN IR&CONT = "01001011010" ELSE
X"0008000" WHEN IR&CONT = "01001011011" ELSE
X"090080B" WHEN IR&CONT = "01001011100" ELSE
X"0050100" WHEN IR&CONT = "01010000000" ELSE
X"0004000" WHEN IR&CONT = "01010000001" ELSE
X"0902000" WHEN IR&CONT = "01010000010" ELSE
X"0050100" WHEN IR&CONT = "01010001000" ELSE
X"0004000" WHEN IR&CONT = "01010001001" ELSE
X"0902001" WHEN IR&CONT = "01010001010" ELSE
X"0050100" WHEN IR&CONT = "01010010000" ELSE
X"0004000" WHEN IR&CONT = "01010010001" ELSE
X"0902002" WHEN IR&CONT = "01010010010" ELSE
X"0050100" WHEN IR&CONT = "01010011000" ELSE
X"0004000" WHEN IR&CONT = "01010011001" ELSE
X"0050100" WHEN IR&CONT = "01010011010" ELSE
X"0008000" WHEN IR&CONT = "01010011011" ELSE
X"0902003" WHEN IR&CONT = "01010011100" ELSE
X"0050100" WHEN IR&CONT = "01010100000" ELSE
X"0004000" WHEN IR&CONT = "01010100001" ELSE
X"0901004" WHEN IR&CONT = "01010100010" ELSE
X"0050100" WHEN IR&CONT = "01010101000" ELSE
X"0004000" WHEN IR&CONT = "01010101001" ELSE
X"0901005" WHEN IR&CONT = "01010101010" ELSE
X"0050100" WHEN IR&CONT = "01010110000" ELSE
X"0004000" WHEN IR&CONT = "01010110001" ELSE
X"0901006" WHEN IR&CONT = "01010110010" ELSE
X"0050100" WHEN IR&CONT = "01010111000" ELSE
X"0004000" WHEN IR&CONT = "01010111001" ELSE
X"0050100" WHEN IR&CONT = "01010111010" ELSE
X"0008000" WHEN IR&CONT = "01010111011" ELSE
X"0901007" WHEN IR&CONT = "01010111100" ELSE
X"0050100" WHEN IR&CONT = "01011000000" ELSE
X"0004000" WHEN IR&CONT = "01011000001" ELSE
X"0900808" WHEN IR&CONT = "01011000010" ELSE
X"0050100" WHEN IR&CONT = "01011001000" ELSE
X"0004000" WHEN IR&CONT = "01011001001" ELSE
X"0900809" WHEN IR&CONT = "01011001010" ELSE
X"0050100" WHEN IR&CONT = "01011010000" ELSE
X"0004000" WHEN IR&CONT = "01011010001" ELSE
X"090080A" WHEN IR&CONT = "01011010010" ELSE
X"0050100" WHEN IR&CONT = "01011011000" ELSE
X"0004000" WHEN IR&CONT = "01011011001" ELSE
X"0050100" WHEN IR&CONT = "01011011010" ELSE
X"0008000" WHEN IR&CONT = "01011011011" ELSE
X"090080B" WHEN IR&CONT = "01011011100" ELSE
X"0050100" WHEN IR&CONT = "01100000000" ELSE
X"0004000" WHEN IR&CONT = "01100000001" ELSE
X"0A02000" WHEN IR&CONT = "01100000010" ELSE
X"0050100" WHEN IR&CONT = "01100001000" ELSE
X"0004000" WHEN IR&CONT = "01100001001" ELSE
X"0A02001" WHEN IR&CONT = "01100001010" ELSE
X"0050100" WHEN IR&CONT = "01100010000" ELSE
X"0004000" WHEN IR&CONT = "01100010001" ELSE
X"0A02002" WHEN IR&CONT = "01100010010" ELSE
X"0050100" WHEN IR&CONT = "01100011000" ELSE
X"0004000" WHEN IR&CONT = "01100011001" ELSE
X"0050100" WHEN IR&CONT = "01100011010" ELSE
X"0008000" WHEN IR&CONT = "01100011011" ELSE
X"0A02003" WHEN IR&CONT = "01100011100" ELSE
X"0050100" WHEN IR&CONT = "01100100000" ELSE
X"0004000" WHEN IR&CONT = "01100100001" ELSE
X"0A01004" WHEN IR&CONT = "01100100010" ELSE
X"0050100" WHEN IR&CONT = "01100101000" ELSE
X"0004000" WHEN IR&CONT = "01100101001" ELSE
X"0A01005" WHEN IR&CONT = "01100101010" ELSE
X"0050100" WHEN IR&CONT = "01100110000" ELSE
X"0004000" WHEN IR&CONT = "01100110001" ELSE
X"0A01006" WHEN IR&CONT = "01100110010" ELSE
X"0050100" WHEN IR&CONT = "01100111000" ELSE
X"0004000" WHEN IR&CONT = "01100111001" ELSE
X"0050100" WHEN IR&CONT = "01100111010" ELSE
X"0008000" WHEN IR&CONT = "01100111011" ELSE
X"0A01007" WHEN IR&CONT = "01100111100" ELSE
X"0050100" WHEN IR&CONT = "01101000000" ELSE
X"0004000" WHEN IR&CONT = "01101000001" ELSE
X"0A00808" WHEN IR&CONT = "01101000010" ELSE
X"0050100" WHEN IR&CONT = "01101001000" ELSE
X"0004000" WHEN IR&CONT = "01101001001" ELSE
X"0A00809" WHEN IR&CONT = "01101001010" ELSE
X"0050100" WHEN IR&CONT = "01101010000" ELSE
X"0004000" WHEN IR&CONT = "01101010001" ELSE
X"0A0080A" WHEN IR&CONT = "01101010010" ELSE
X"0050100" WHEN IR&CONT = "01101011000" ELSE
X"0004000" WHEN IR&CONT = "01101011001" ELSE
X"0050100" WHEN IR&CONT = "01101011010" ELSE
X"0008000" WHEN IR&CONT = "01101011011" ELSE
X"0A0080B" WHEN IR&CONT = "01101011100" ELSE
X"0050100" WHEN IR&CONT = "01110000000" ELSE
X"0004000" WHEN IR&CONT = "01110000001" ELSE
X"0A82000" WHEN IR&CONT = "01110000010" ELSE
X"0050100" WHEN IR&CONT = "01110001000" ELSE
X"0004000" WHEN IR&CONT = "01110001001" ELSE
X"0A82001" WHEN IR&CONT = "01110001010" ELSE
X"0050100" WHEN IR&CONT = "01110010000" ELSE
X"0004000" WHEN IR&CONT = "01110010001" ELSE
X"0A82002" WHEN IR&CONT = "01110010010" ELSE
X"0050100" WHEN IR&CONT = "01110011000" ELSE
X"0004000" WHEN IR&CONT = "01110011001" ELSE
X"0050100" WHEN IR&CONT = "01110011010" ELSE
X"0008000" WHEN IR&CONT = "01110011011" ELSE
X"0A82003" WHEN IR&CONT = "01110011100" ELSE
X"0050100" WHEN IR&CONT = "01110100000" ELSE
X"0004000" WHEN IR&CONT = "01110100001" ELSE
X"0A81004" WHEN IR&CONT = "01110100010" ELSE
X"0050100" WHEN IR&CONT = "01110101000" ELSE
X"0004000" WHEN IR&CONT = "01110101001" ELSE
X"0A81005" WHEN IR&CONT = "01110101010" ELSE
X"0050100" WHEN IR&CONT = "01110110000" ELSE
X"0004000" WHEN IR&CONT = "01110110001" ELSE
X"0A81006" WHEN IR&CONT = "01110110010" ELSE
X"0050100" WHEN IR&CONT = "01110111000" ELSE
X"0004000" WHEN IR&CONT = "01110111001" ELSE
X"0050100" WHEN IR&CONT = "01110111010" ELSE
X"0008000" WHEN IR&CONT = "01110111011" ELSE
X"0A81007" WHEN IR&CONT = "01110111100" ELSE
X"0050100" WHEN IR&CONT = "01111000000" ELSE
X"0004000" WHEN IR&CONT = "01111000001" ELSE
X"0A80808" WHEN IR&CONT = "01111000010" ELSE
X"0050100" WHEN IR&CONT = "01111001000" ELSE
X"0004000" WHEN IR&CONT = "01111001001" ELSE
X"0A80809" WHEN IR&CONT = "01111001010" ELSE
X"0050100" WHEN IR&CONT = "01111010000" ELSE
X"0004000" WHEN IR&CONT = "01111010001" ELSE
X"0A8080A" WHEN IR&CONT = "01111010010" ELSE
X"0050100" WHEN IR&CONT = "01111011000" ELSE
X"0004000" WHEN IR&CONT = "01111011001" ELSE
X"0050100" WHEN IR&CONT = "01111011010" ELSE
X"0008000" WHEN IR&CONT = "01111011011" ELSE
X"0A8080B" WHEN IR&CONT = "01111011100" ELSE
X"0050100" WHEN IR&CONT = "10000000000" ELSE
X"0004000" WHEN IR&CONT = "10000000001" ELSE
X"0B02040" WHEN IR&CONT = "10000000010" ELSE
X"0050100" WHEN IR&CONT = "10000001000" ELSE
X"0004000" WHEN IR&CONT = "10000001001" ELSE
X"0B02041" WHEN IR&CONT = "10000001010" ELSE
X"0050100" WHEN IR&CONT = "10000010000" ELSE
X"0004000" WHEN IR&CONT = "10000010001" ELSE
X"0B02042" WHEN IR&CONT = "10000010010" ELSE
X"0050100" WHEN IR&CONT = "10000011000" ELSE
X"0004000" WHEN IR&CONT = "10000011001" ELSE
X"0050100" WHEN IR&CONT = "10000011010" ELSE
X"0008000" WHEN IR&CONT = "10000011011" ELSE
X"0B02043" WHEN IR&CONT = "10000011100" ELSE
X"0050100" WHEN IR&CONT = "10000100000" ELSE
X"0004000" WHEN IR&CONT = "10000100001" ELSE
X"0B01044" WHEN IR&CONT = "10000100010" ELSE
X"0050100" WHEN IR&CONT = "10000101000" ELSE
X"0004000" WHEN IR&CONT = "10000101001" ELSE
X"0B01045" WHEN IR&CONT = "10000101010" ELSE
X"0050100" WHEN IR&CONT = "10000110000" ELSE
X"0004000" WHEN IR&CONT = "10000110001" ELSE
X"0B01046" WHEN IR&CONT = "10000110010" ELSE
X"0050100" WHEN IR&CONT = "10000111000" ELSE
X"0004000" WHEN IR&CONT = "10000111001" ELSE
X"0050100" WHEN IR&CONT = "10000111010" ELSE
X"0008000" WHEN IR&CONT = "10000111011" ELSE
X"0B01047" WHEN IR&CONT = "10000111100" ELSE
X"0050100" WHEN IR&CONT = "10001000000" ELSE
X"0004000" WHEN IR&CONT = "10001000001" ELSE
X"0B00848" WHEN IR&CONT = "10001000010" ELSE
X"0050100" WHEN IR&CONT = "10001001000" ELSE
X"0004000" WHEN IR&CONT = "10001001001" ELSE
X"0B00849" WHEN IR&CONT = "10001001010" ELSE
X"0050100" WHEN IR&CONT = "10001010000" ELSE
X"0004000" WHEN IR&CONT = "10001010001" ELSE
X"0B0084A" WHEN IR&CONT = "10001010010" ELSE
X"0050100" WHEN IR&CONT = "10001011000" ELSE
X"0004000" WHEN IR&CONT = "10001011001" ELSE
X"0050100" WHEN IR&CONT = "10001011010" ELSE
X"0008000" WHEN IR&CONT = "10001011011" ELSE
X"0B0084B" WHEN IR&CONT = "10001011100" ELSE
X"0050100" WHEN IR&CONT = "10010000000" ELSE
X"0004000" WHEN IR&CONT = "10010000001" ELSE
X"0B82040" WHEN IR&CONT = "10010000010" ELSE
X"0050100" WHEN IR&CONT = "10010001000" ELSE
X"0004000" WHEN IR&CONT = "10010001001" ELSE
X"0B81045" WHEN IR&CONT = "10010001010" ELSE
X"0050100" WHEN IR&CONT = "10010010000" ELSE
X"0004000" WHEN IR&CONT = "10010010001" ELSE
X"0B8084A" WHEN IR&CONT = "10010010010" ELSE
X"0050100" WHEN IR&CONT = "10010100000" ELSE
X"0004000" WHEN IR&CONT = "10010100001" ELSE
X"0C02040" WHEN IR&CONT = "10010100010" ELSE
X"0050100" WHEN IR&CONT = "10010101000" ELSE
X"0004000" WHEN IR&CONT = "10010101001" ELSE
X"0C01045" WHEN IR&CONT = "10010101010" ELSE
X"0050100" WHEN IR&CONT = "10010110000" ELSE
X"0004000" WHEN IR&CONT = "10010110001" ELSE
X"0C0084A" WHEN IR&CONT = "10010110010" ELSE
X"0050100" WHEN IR&CONT = "10011000000" ELSE
X"0004000" WHEN IR&CONT = "10011000001" ELSE
X"0C82040" WHEN IR&CONT = "10011000010" ELSE
X"0050100" WHEN IR&CONT = "10011001000" ELSE
X"0004000" WHEN IR&CONT = "10011001001" ELSE
X"0C81045" WHEN IR&CONT = "10011001010" ELSE
X"0050100" WHEN IR&CONT = "10011010000" ELSE
X"0004000" WHEN IR&CONT = "10011010001" ELSE
X"0C8084A" WHEN IR&CONT = "10011010010" ELSE
X"0050100" WHEN IR&CONT = "10011111000" ELSE
X"0804000" WHEN IR&CONT = "10011111001" ELSE
X"0050100" WHEN IR&CONT = "11001000000" ELSE
X"0004000" WHEN IR&CONT = "11001000001" ELSE
X"0D02000" WHEN IR&CONT = "11001000010" ELSE
X"0050100" WHEN IR&CONT = "11001001000" ELSE
X"0004000" WHEN IR&CONT = "11001001001" ELSE
X"0D01004" WHEN IR&CONT = "11001001010" ELSE
X"0050100" WHEN IR&CONT = "11001010000" ELSE
X"0004000" WHEN IR&CONT = "11001010001" ELSE
X"0D00808" WHEN IR&CONT = "11001010010" ELSE
X"0050100" WHEN IR&CONT = "11001100000" ELSE
X"0004000" WHEN IR&CONT = "11001100001" ELSE
X"0D82000" WHEN IR&CONT = "11001100010" ELSE
X"0050100" WHEN IR&CONT = "11001101000" ELSE
X"0004000" WHEN IR&CONT = "11001101001" ELSE
X"0D81004" WHEN IR&CONT = "11001101010" ELSE
X"0050100" WHEN IR&CONT = "11001110000" ELSE
X"0004000" WHEN IR&CONT = "11001110001" ELSE
X"0D80808" WHEN IR&CONT = "11001110010" ELSE
X"0050100" WHEN IR&CONT = "10100000000" ELSE
X"0004000" WHEN IR&CONT = "10100000001" ELSE
X"0900400" WHEN IR&CONT = "10100000010" ELSE
X"0050100" WHEN IR&CONT = "10100001000" ELSE
X"0004000" WHEN IR&CONT = "10100001001" ELSE
X"0900401" WHEN IR&CONT = "10100001010" ELSE
X"0050100" WHEN IR&CONT = "10100010000" ELSE
X"0004000" WHEN IR&CONT = "10100010001" ELSE
X"0900402" WHEN IR&CONT = "10100010010" ELSE
X"0050100" WHEN IR&CONT = "10100011000" ELSE
X"0004000" WHEN IR&CONT = "10100011001" ELSE
X"0050100" WHEN IR&CONT = "10100011010" ELSE
X"0008000" WHEN IR&CONT = "10100011011" ELSE
X"0900403" WHEN IR&CONT = "10100011100" ELSE
X"0050100" WHEN IR&CONT = "10100100000" ELSE
X"0004000" WHEN IR&CONT = "10100100001" ELSE
X"0900404" WHEN IR&CONT = "10100100010" ELSE
X"0050100" WHEN IR&CONT = "10100101000" ELSE
X"0004000" WHEN IR&CONT = "10100101001" ELSE
X"0900405" WHEN IR&CONT = "10100101010" ELSE
X"0050100" WHEN IR&CONT = "10100110000" ELSE
X"0004000" WHEN IR&CONT = "10100110001" ELSE
X"0900406" WHEN IR&CONT = "10100110010" ELSE
X"0050100" WHEN IR&CONT = "10100111000" ELSE
X"0004000" WHEN IR&CONT = "10100111001" ELSE
X"0050100" WHEN IR&CONT = "10100111010" ELSE
X"0008000" WHEN IR&CONT = "10100111011" ELSE
X"0900407" WHEN IR&CONT = "10100111100" ELSE
X"0050100" WHEN IR&CONT = "10101000000" ELSE
X"0004000" WHEN IR&CONT = "10101000001" ELSE
X"0900408" WHEN IR&CONT = "10101000010" ELSE
X"0050100" WHEN IR&CONT = "10101001000" ELSE
X"0004000" WHEN IR&CONT = "10101001001" ELSE
X"0900409" WHEN IR&CONT = "10101001010" ELSE
X"0050100" WHEN IR&CONT = "10101010000" ELSE
X"0004000" WHEN IR&CONT = "10101010001" ELSE
X"090040A" WHEN IR&CONT = "10101010010" ELSE
X"0050100" WHEN IR&CONT = "10101011000" ELSE
X"0004000" WHEN IR&CONT = "10101011001" ELSE
X"0050100" WHEN IR&CONT = "10101011010" ELSE
X"0008000" WHEN IR&CONT = "10101011011" ELSE
X"090040B" WHEN IR&CONT = "10101011100" ELSE
X"0050100" WHEN IR&CONT = "10110000000" ELSE
X"0004000" WHEN IR&CONT = "10110000001" ELSE
X"0050100" WHEN IR&CONT = "10110000010" ELSE
X"0008000" WHEN IR&CONT = "10110000011" ELSE
X"0840040" WHEN IR&CONT = "10110000100" ELSE
X"0050100" WHEN IR&CONT = "10110001000" ELSE
X"0004000" WHEN IR&CONT = "10110001001" ELSE
X"0050100" WHEN IR&CONT = "10110001010" ELSE
X"0008000" WHEN IR&CONT = "10110001011" ELSE
X"0840040" WHEN IR&CONT = "10110001100" ELSE
X"0050100" WHEN IR&CONT = "10110010000" ELSE
X"0004000" WHEN IR&CONT = "10110010001" ELSE
X"0050100" WHEN IR&CONT = "10110010010" ELSE
X"0008000" WHEN IR&CONT = "10110010011" ELSE
X"0840040" WHEN IR&CONT = "10110010100" ELSE
X"0050100" WHEN IR&CONT = "10110011000" ELSE
X"0004000" WHEN IR&CONT = "10110011001" ELSE
X"0050100" WHEN IR&CONT = "10110011010" ELSE
X"0008000" WHEN IR&CONT = "10110011011" ELSE
X"0840040" WHEN IR&CONT = "10110011100" ELSE
X"0050100" WHEN IR&CONT = "10110100000" ELSE
X"0004000" WHEN IR&CONT = "10110100001" ELSE
X"0050100" WHEN IR&CONT = "10110100010" ELSE
X"0008000" WHEN IR&CONT = "10110100011" ELSE
X"0840040" WHEN IR&CONT = "10110100100" ELSE
X"0050100" WHEN IR&CONT = "10110101000" ELSE
X"0004000" WHEN IR&CONT = "10110101001" ELSE
X"0050100" WHEN IR&CONT = "10110101010" ELSE
X"0008000" WHEN IR&CONT = "10110101011" ELSE
X"0840040" WHEN IR&CONT = "10110101100" ELSE
X"0050100" WHEN IR&CONT = "10110110000" ELSE
X"0004000" WHEN IR&CONT = "10110110001" ELSE
X"0050100" WHEN IR&CONT = "10110110010" ELSE
X"0008000" WHEN IR&CONT = "10110110011" ELSE
X"0840040" WHEN IR&CONT = "10110110100" ELSE
X"0050100" WHEN IR&CONT = "10110111000" ELSE
X"0004000" WHEN IR&CONT = "10110111001" ELSE
X"0050100" WHEN IR&CONT = "10110111010" ELSE
X"0008000" WHEN IR&CONT = "10110111011" ELSE
X"0840040" WHEN IR&CONT = "10110111100" ELSE
X"0050100" WHEN IR&CONT = "10111000000" ELSE
X"0004000" WHEN IR&CONT = "10111000001" ELSE
X"0050100" WHEN IR&CONT = "10111000010" ELSE
X"0008000" WHEN IR&CONT = "10111000011" ELSE
X"0840040" WHEN IR&CONT = "10111000100" ELSE
X"0050100" WHEN IR&CONT = "10111001000" ELSE
X"0004000" WHEN IR&CONT = "10111001001" ELSE
X"0050100" WHEN IR&CONT = "10111001010" ELSE
X"0008000" WHEN IR&CONT = "10111001011" ELSE
X"0840040" WHEN IR&CONT = "10111001100" ELSE
X"0050100" WHEN IR&CONT = "10111010000" ELSE
X"0004000" WHEN IR&CONT = "10111010001" ELSE
X"0050100" WHEN IR&CONT = "10111010010" ELSE
X"0008000" WHEN IR&CONT = "10111010011" ELSE
X"0840040" WHEN IR&CONT = "10111010100" ELSE
X"0050100" WHEN IR&CONT = "10111011000" ELSE
X"0004000" WHEN IR&CONT = "10111011001" ELSE
X"0050100" WHEN IR&CONT = "10111011010" ELSE
X"0008000" WHEN IR&CONT = "10111011011" ELSE
X"0840040" WHEN IR&CONT = "10111011100" ELSE
X"0050100" WHEN IR&CONT = "10111100000" ELSE
X"0004000" WHEN IR&CONT = "10111100001" ELSE
X"0050100" WHEN IR&CONT = "10111100010" ELSE
X"0008000" WHEN IR&CONT = "10111100011" ELSE
X"0840040" WHEN IR&CONT = "10111100100" ELSE
X"0050100" WHEN IR&CONT = "10111101000" ELSE
X"0004000" WHEN IR&CONT = "10111101001" ELSE
X"0050100" WHEN IR&CONT = "10111101010" ELSE
X"0008000" WHEN IR&CONT = "10111101011" ELSE
X"0840040" WHEN IR&CONT = "10111101100" ELSE
X"0050100" WHEN IR&CONT = "10111110000" ELSE
X"0004000" WHEN IR&CONT = "10111110001" ELSE
X"0050100" WHEN IR&CONT = "10111110010" ELSE
X"0008000" WHEN IR&CONT = "10111110011" ELSE
X"0840040" WHEN IR&CONT = "10111110100" ELSE
X"0050100" WHEN IR&CONT = "10111111000" ELSE
X"0004000" WHEN IR&CONT = "10111111001" ELSE
X"0050100" WHEN IR&CONT = "10111111010" ELSE
X"0008000" WHEN IR&CONT = "10111111011" ELSE
X"0840040" WHEN IR&CONT = "10111111100" ELSE
X"0050100" WHEN IR&CONT = "11000000000" ELSE
X"0004000" WHEN IR&CONT = "11000000001" ELSE
X"0050100" WHEN IR&CONT = "11000000010" ELSE
X"0008000" WHEN IR&CONT = "11000000011" ELSE
X"0840000" WHEN IR&CONT = "11000000100" ELSE
X"0050100" WHEN IR&CONT = "11000001000" ELSE
X"0004000" WHEN IR&CONT = "11000001001" ELSE
X"0050100" WHEN IR&CONT = "11000001010" ELSE
X"0008000" WHEN IR&CONT = "11000001011" ELSE
X"0840000" WHEN IR&CONT = "11000001100" ELSE
X"0050100" WHEN IR&CONT = "11000010000" ELSE
X"0004000" WHEN IR&CONT = "11000010001" ELSE
X"0050100" WHEN IR&CONT = "11000010010" ELSE
X"0008000" WHEN IR&CONT = "11000010011" ELSE
X"0840000" WHEN IR&CONT = "11000010100" ELSE
X"0050100" WHEN IR&CONT = "11010000000" ELSE
X"0004000" WHEN IR&CONT = "11010000001" ELSE
X"0008010" WHEN IR&CONT = "11010000010" ELSE
X"0010020" WHEN IR&CONT = "11010000011" ELSE
X"0008000" WHEN IR&CONT = "11010000100" ELSE
X"0802003" WHEN IR&CONT = "11010000101" ELSE
X"0050100" WHEN IR&CONT = "11010001000" ELSE
X"0004000" WHEN IR&CONT = "11010001001" ELSE
X"0008015" WHEN IR&CONT = "11010001010" ELSE
X"0010020" WHEN IR&CONT = "11010001011" ELSE
X"0008000" WHEN IR&CONT = "11010001100" ELSE
X"0802003" WHEN IR&CONT = "11010001101" ELSE
X"0050100" WHEN IR&CONT = "11010010000" ELSE
X"0004000" WHEN IR&CONT = "11010010001" ELSE
X"000801A" WHEN IR&CONT = "11010010010" ELSE
X"0010020" WHEN IR&CONT = "11010010011" ELSE
X"0008000" WHEN IR&CONT = "11010010100" ELSE
X"0802003" WHEN IR&CONT = "11010010101" ELSE
X"0050100" WHEN IR&CONT = "11010100000" ELSE
X"0004000" WHEN IR&CONT = "11010100001" ELSE
X"0008010" WHEN IR&CONT = "11010100010" ELSE
X"0010020" WHEN IR&CONT = "11010100011" ELSE
X"0008000" WHEN IR&CONT = "11010100100" ELSE
X"0801007" WHEN IR&CONT = "11010100101" ELSE
X"0050100" WHEN IR&CONT = "11010101000" ELSE
X"0004000" WHEN IR&CONT = "11010101001" ELSE
X"0008015" WHEN IR&CONT = "11010101010" ELSE
X"0010020" WHEN IR&CONT = "11010101011" ELSE
X"0008000" WHEN IR&CONT = "11010101100" ELSE
X"0801007" WHEN IR&CONT = "11010101101" ELSE
X"0050100" WHEN IR&CONT = "11010110000" ELSE
X"0004000" WHEN IR&CONT = "11010110001" ELSE
X"000801A" WHEN IR&CONT = "11010110010" ELSE
X"0010020" WHEN IR&CONT = "11010110011" ELSE
X"0008000" WHEN IR&CONT = "11010110100" ELSE
X"0801007" WHEN IR&CONT = "11010110101" ELSE
X"0050100" WHEN IR&CONT = "11011000000" ELSE
X"0004000" WHEN IR&CONT = "11011000001" ELSE
X"0008010" WHEN IR&CONT = "11011000010" ELSE
X"0010020" WHEN IR&CONT = "11011000011" ELSE
X"0008000" WHEN IR&CONT = "11011000100" ELSE
X"080080B" WHEN IR&CONT = "11011000101" ELSE
X"0050100" WHEN IR&CONT = "11011001000" ELSE
X"0004000" WHEN IR&CONT = "11011001001" ELSE
X"0008010" WHEN IR&CONT = "11011001010" ELSE
X"0010020" WHEN IR&CONT = "11011001011" ELSE
X"0008000" WHEN IR&CONT = "11011001100" ELSE
X"080080B" WHEN IR&CONT = "11011001101" ELSE
X"0050100" WHEN IR&CONT = "11011010000" ELSE
X"0004000" WHEN IR&CONT = "11011010001" ELSE
X"0008010" WHEN IR&CONT = "11011010010" ELSE
X"0010020" WHEN IR&CONT = "11011010011" ELSE
X"0008000" WHEN IR&CONT = "11011010100" ELSE
X"080080B" WHEN IR&CONT = "11011010101" ELSE
X"0050100" WHEN IR&CONT = "11100000000" ELSE
X"0004000" WHEN IR&CONT = "11100000001" ELSE
X"0008010" WHEN IR&CONT = "11100000010" ELSE
X"0010020" WHEN IR&CONT = "11100000011" ELSE
X"0008010" WHEN IR&CONT = "11100000100" ELSE
X"0800200" WHEN IR&CONT = "11100000101" ELSE
X"0050100" WHEN IR&CONT = "11100001000" ELSE
X"0004000" WHEN IR&CONT = "11100001001" ELSE
X"0008010" WHEN IR&CONT = "11100001010" ELSE
X"0010020" WHEN IR&CONT = "11100001011" ELSE
X"0008015" WHEN IR&CONT = "11100001100" ELSE
X"0800200" WHEN IR&CONT = "11100001101" ELSE
X"0050100" WHEN IR&CONT = "11100010000" ELSE
X"0004000" WHEN IR&CONT = "11100010001" ELSE
X"0008010" WHEN IR&CONT = "11100010010" ELSE
X"0010020" WHEN IR&CONT = "11100010011" ELSE
X"000801A" WHEN IR&CONT = "11100010100" ELSE
X"0800200" WHEN IR&CONT = "11100010101" ELSE
X"0050100" WHEN IR&CONT = "11100100000" ELSE
X"0004000" WHEN IR&CONT = "11100100001" ELSE
X"0008015" WHEN IR&CONT = "11100100010" ELSE
X"0010020" WHEN IR&CONT = "11100100011" ELSE
X"0008010" WHEN IR&CONT = "11100100100" ELSE
X"0800200" WHEN IR&CONT = "11100100101" ELSE
X"0050100" WHEN IR&CONT = "11100101000" ELSE
X"0004000" WHEN IR&CONT = "11100101001" ELSE
X"0008015" WHEN IR&CONT = "11100101010" ELSE
X"0010020" WHEN IR&CONT = "11100101011" ELSE
X"0008015" WHEN IR&CONT = "11100101100" ELSE
X"0800200" WHEN IR&CONT = "11100101101" ELSE
X"0050100" WHEN IR&CONT = "11100110000" ELSE
X"0004000" WHEN IR&CONT = "11100110001" ELSE
X"0008015" WHEN IR&CONT = "11100110010" ELSE
X"0010020" WHEN IR&CONT = "11100110011" ELSE
X"000801A" WHEN IR&CONT = "11100110100" ELSE
X"0800200" WHEN IR&CONT = "11100110101" ELSE
X"0050100" WHEN IR&CONT = "11101000000" ELSE
X"0004000" WHEN IR&CONT = "11101000001" ELSE
X"000801A" WHEN IR&CONT = "11101000010" ELSE
X"0010020" WHEN IR&CONT = "11101000011" ELSE
X"0008010" WHEN IR&CONT = "11101000100" ELSE
X"0800200" WHEN IR&CONT = "11101000101" ELSE
X"0050100" WHEN IR&CONT = "11101001000" ELSE
X"0004000" WHEN IR&CONT = "11101001001" ELSE
X"000801A" WHEN IR&CONT = "11101001010" ELSE
X"0010020" WHEN IR&CONT = "11101001011" ELSE
X"0008015" WHEN IR&CONT = "11101001100" ELSE
X"0800200" WHEN IR&CONT = "11101001101" ELSE
X"0050100" WHEN IR&CONT = "11101010000" ELSE
X"0004000" WHEN IR&CONT = "11101010001" ELSE
X"000801A" WHEN IR&CONT = "11101010010" ELSE
X"0010020" WHEN IR&CONT = "11101010011" ELSE
X"000801A" WHEN IR&CONT = "11101010100" ELSE
X"0800200" WHEN IR&CONT = "11101010101" ELSE
X"0050100" WHEN IR&CONT = "11110000000" ELSE
X"0004000" WHEN IR&CONT = "11110000001" ELSE
X"0050100" WHEN IR&CONT = "11110000010" ELSE
X"0008000" WHEN IR&CONT = "11110000011" ELSE
X"1000000" WHEN IR&CONT = "11110000100" ELSE
X"0840040" WHEN IR&CONT = "11110000101" ELSE
X"0050100" WHEN IR&CONT = "11110001000" ELSE
X"0004000" WHEN IR&CONT = "11110001001" ELSE
X"0050100" WHEN IR&CONT = "11110001010" ELSE
X"0008000" WHEN IR&CONT = "11110001011" ELSE
X"1000000" WHEN IR&CONT = "11110001100" ELSE
X"0840040" WHEN IR&CONT = "11110001101" ELSE
X"0050100" WHEN IR&CONT = "11110010000" ELSE
X"0004000" WHEN IR&CONT = "11110010001" ELSE
X"0050100" WHEN IR&CONT = "11110010010" ELSE
X"0008000" WHEN IR&CONT = "11110010011" ELSE
X"1000000" WHEN IR&CONT = "11110010100" ELSE
X"0840040" WHEN IR&CONT = "11110010101" ELSE
X"0050100" WHEN IR&CONT = "11110011000" ELSE
X"0004000" WHEN IR&CONT = "11110011001" ELSE
X"0050100" WHEN IR&CONT = "11110011010" ELSE
X"0008000" WHEN IR&CONT = "11110011011" ELSE
X"1000000" WHEN IR&CONT = "11110011100" ELSE
X"0840040" WHEN IR&CONT = "11110011101" ELSE
X"0050100" WHEN IR&CONT = "11110100000" ELSE
X"0004000" WHEN IR&CONT = "11110100001" ELSE
X"0050100" WHEN IR&CONT = "11110100010" ELSE
X"0008000" WHEN IR&CONT = "11110100011" ELSE
X"1000000" WHEN IR&CONT = "11110100100" ELSE
X"0840040" WHEN IR&CONT = "11110100101" ELSE
X"0050100" WHEN IR&CONT = "11110101000" ELSE
X"0004000" WHEN IR&CONT = "11110101001" ELSE
X"0050100" WHEN IR&CONT = "11110101010" ELSE
X"0008000" WHEN IR&CONT = "11110101011" ELSE
X"1000000" WHEN IR&CONT = "11110101100" ELSE
X"0840040" WHEN IR&CONT = "11110101101" ELSE
X"0050100" WHEN IR&CONT = "11110110000" ELSE
X"0004000" WHEN IR&CONT = "11110110001" ELSE
X"0050100" WHEN IR&CONT = "11110110010" ELSE
X"0008000" WHEN IR&CONT = "11110110011" ELSE
X"1000000" WHEN IR&CONT = "11110110100" ELSE
X"0840040" WHEN IR&CONT = "11110110101" ELSE
X"0050100" WHEN IR&CONT = "11110111000" ELSE
X"0004000" WHEN IR&CONT = "11110111001" ELSE
X"0050100" WHEN IR&CONT = "11110111010" ELSE
X"0008000" WHEN IR&CONT = "11110111011" ELSE
X"1000000" WHEN IR&CONT = "11110111100" ELSE
X"0840040" WHEN IR&CONT = "11110111101" ELSE
X"0050100" WHEN IR&CONT = "11111000000" ELSE
X"0004000" WHEN IR&CONT = "11111000001" ELSE
X"0050100" WHEN IR&CONT = "11111000010" ELSE
X"0008000" WHEN IR&CONT = "11111000011" ELSE
X"1000000" WHEN IR&CONT = "11111000100" ELSE
X"0840040" WHEN IR&CONT = "11111000101" ELSE
X"0050100" WHEN IR&CONT = "11111001000" ELSE
X"0004000" WHEN IR&CONT = "11111001001" ELSE
X"0050100" WHEN IR&CONT = "11111001010" ELSE
X"0008000" WHEN IR&CONT = "11111001011" ELSE
X"1000000" WHEN IR&CONT = "11111001100" ELSE
X"0840040" WHEN IR&CONT = "11111001101" ELSE
X"0050100" WHEN IR&CONT = "11111010000" ELSE
X"0004000" WHEN IR&CONT = "11111010001" ELSE
X"0050100" WHEN IR&CONT = "11111010010" ELSE
X"0008000" WHEN IR&CONT = "11111010011" ELSE
X"1000000" WHEN IR&CONT = "11111010100" ELSE
X"0840040" WHEN IR&CONT = "11111010101" ELSE
X"0050100" WHEN IR&CONT = "11111011000" ELSE
X"0004000" WHEN IR&CONT = "11111011001" ELSE
X"0050100" WHEN IR&CONT = "11111011010" ELSE
X"0008000" WHEN IR&CONT = "11111011011" ELSE
X"1000000" WHEN IR&CONT = "11111011100" ELSE
X"0840040" WHEN IR&CONT = "11111011101" ELSE
X"0050100" WHEN IR&CONT = "11111100000" ELSE
X"0004000" WHEN IR&CONT = "11111100001" ELSE
X"0050100" WHEN IR&CONT = "11111100010" ELSE
X"0008000" WHEN IR&CONT = "11111100011" ELSE
X"1000000" WHEN IR&CONT = "11111100100" ELSE
X"0840040" WHEN IR&CONT = "11111100101" ELSE
X"0050100" WHEN IR&CONT = "11111101000" ELSE
X"0004000" WHEN IR&CONT = "11111101001" ELSE
X"0050100" WHEN IR&CONT = "11111101010" ELSE
X"0008000" WHEN IR&CONT = "11111101011" ELSE
X"1000000" WHEN IR&CONT = "11111101100" ELSE
X"0840040" WHEN IR&CONT = "11111101101" ELSE
X"0050100" WHEN IR&CONT = "11111110000" ELSE
X"0004000" WHEN IR&CONT = "11111110001" ELSE
X"0050100" WHEN IR&CONT = "11111110010" ELSE
X"0008000" WHEN IR&CONT = "11111110011" ELSE
X"1000000" WHEN IR&CONT = "11111110100" ELSE
X"0840040" WHEN IR&CONT = "11111110101" ELSE
X"0050100" WHEN IR&CONT = "11111111000" ELSE
X"0004000" WHEN IR&CONT = "11111111001" ELSE
X"0050100" WHEN IR&CONT = "11111111010" ELSE
X"0008000" WHEN IR&CONT = "11111111011" ELSE
X"1000000" WHEN IR&CONT = "11111111100" ELSE
X"0840040" WHEN IR&CONT = "11111111101" ELSE
X"0050100" WHEN IR&CONT = "10011110000" ELSE
X"0004000" WHEN IR&CONT = "10011110001" ELSE
X"0840080" WHEN IR&CONT = "10011110010" ELSE
X"0004000";
salida_mem_control <= señales_de_control(24 downto 0);
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.gencomp.all;
entity leon4_net is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
hclken : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqi_hrdrst: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(63 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
dbgo_ducnt : out std_ulogic);
end ;
architecture rtl of leon4_net is
signal disasen : std_ulogic;
component leon4_ut90nhbd
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 1 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 1 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk: in std_ulogic;
gclk: in std_ulogic;
hclken: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(127 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbi_testen: in std_ulogic;
ahbi_testrst: in std_ulogic;
ahbi_scanen: in std_ulogic;
ahbi_testoen: in std_ulogic;
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(127 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(127 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
disasen : in std_ulogic);
end component;
signal ahbi_hgrant: std_logic_vector(0 to NAHBMST-1);
signal ahbi_hready: std_ulogic;
signal ahbi_hresp: std_logic_vector(1 downto 0);
signal ahbi_hrdata: std_logic_vector(127 downto 0);
signal ahbi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbi_testen: std_ulogic;
signal ahbi_testrst: std_ulogic;
signal ahbi_scanen: std_ulogic;
signal ahbi_testoen: std_ulogic;
signal ahbo_hbusreq: std_ulogic;
signal ahbo_hlock: std_ulogic;
signal ahbo_htrans: std_logic_vector(1 downto 0);
signal ahbo_haddr: std_logic_vector(31 downto 0);
signal ahbo_hwrite: std_ulogic;
signal ahbo_hsize: std_logic_vector(2 downto 0);
signal ahbo_hburst: std_logic_vector(2 downto 0);
signal ahbo_hprot: std_logic_vector(3 downto 0);
signal ahbo_hwdata: std_logic_vector(127 downto 0);
signal ahbo_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbsi_hsel: std_logic_vector(0 to NAHBSLV-1);
signal ahbsi_haddr: std_logic_vector(31 downto 0);
signal ahbsi_hwrite: std_ulogic;
signal ahbsi_htrans: std_logic_vector(1 downto 0);
signal ahbsi_hsize: std_logic_vector(2 downto 0);
signal ahbsi_hburst: std_logic_vector(2 downto 0);
signal ahbsi_hwdata: std_logic_vector(127 downto 0);
signal ahbsi_hprot: std_logic_vector(3 downto 0);
signal ahbsi_hready: std_ulogic;
signal ahbsi_hmaster: std_logic_vector(3 downto 0);
signal ahbsi_hmastlock: std_ulogic;
signal ahbsi_hmbsel: std_logic_vector(0 to NAHBAMR-1);
signal ahbsi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
constant hconfig: ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON4, 0, 0, 0),
others => zero32);
begin
disasen <= '1' when disas /= 0 else '0';
-- Plug&Play information
ahbox.hconfig <= hconfig;
ahbox.hindex <= hindex;
ut09 : if fabtech = ut90 generate
wrp: leon4_ut90nhbd
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize, smp => smp)
port map(
clk => clk,
gclk => gclk,
hclken => hclken,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbi_testen => ahbi_testen,
ahbi_testrst => ahbi_testrst,
ahbi_scanen => ahbi_scanen,
ahbi_testoen => ahbi_testoen,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqi_rstvec => irqi_rstvec,
irqi_iact => irqi_iact,
irqi_index => irqi_index,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
irqo_fpen => irqo_fpen,
irqo_idle => irqo_idle,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer(30 downto 0),
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
dbgo_fcnt => dbgo_fcnt,
dbgo_optype => dbgo_optype,
dbgo_bpmiss => dbgo_bpmiss,
dbgo_istat_cmiss => dbgo_istat_cmiss,
dbgo_istat_tmiss => dbgo_istat_tmiss,
dbgo_istat_chold => dbgo_istat_chold,
dbgo_istat_mhold => dbgo_istat_mhold,
dbgo_dstat_cmiss => dbgo_dstat_cmiss,
dbgo_dstat_tmiss => dbgo_dstat_tmiss,
dbgo_dstat_chold => dbgo_dstat_chold,
dbgo_dstat_mhold => dbgo_dstat_mhold,
dbgo_wbhold => dbgo_wbhold,
dbgo_su => dbgo_su,
disasen => disasen);
dbgo_ducnt <= '1';
end generate;
ahbi_hgrant(0) <= ahbix.hgrant(hindex);
ahbi_hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi_hready <= ahbix.hready;
ahbi_hresp <= ahbix.hresp;
ahbi_hrdata(127 mod AHBDW downto 0) <= ahbix.hrdata(127 mod AHBDW downto 0);
ahbi_hirq <= ahbix.hirq;
ahbi_testen <= ahbix.testen;
ahbi_testrst <= ahbix.testrst;
ahbi_scanen <= ahbix.scanen;
ahbi_testoen <= ahbix.testoen;
ahbox.hbusreq <= ahbo_hbusreq;
ahbox.hlock <= ahbo_hlock;
ahbox.htrans <= ahbo_htrans;
ahbox.haddr <= ahbo_haddr;
ahbox.hwrite <= ahbo_hwrite;
ahbox.hsize <= ahbo_hsize(2 downto 0);
ahbox.hburst <= "00" & ahbo_hburst(0);
ahbox.hprot <= ahbo_hprot;
ahbox.hwdata(127 mod AHBDW downto 0) <= ahbo_hwdata(127 mod AHBDW downto 0);
ahbox.hirq <= (others => '0'); --ahbo_hirq;
ahbsi_hsel <= ahbsix.hsel;
ahbsi_haddr <= ahbsix.haddr;
ahbsi_hwrite <= ahbsix.hwrite;
ahbsi_htrans <= ahbsix.htrans;
ahbsi_hsize <= ahbsix.hsize;
ahbsi_hburst <= ahbsix.hburst;
ahbsi_hwdata(127 mod AHBDW downto 0) <= ahbsix.hwdata(127 mod AHBDW downto 0);
ahbsi_hprot <= ahbsix.hprot;
ahbsi_hready <= ahbsix.hready;
ahbsi_hmaster <= ahbsix.hmaster;
ahbsi_hmastlock <= ahbsix.hmastlock;
ahbsi_hmbsel <= ahbsix.hmbsel;
ahbsi_hirq <= ahbsix.hirq;
-- pragma translate_off
assert NAHBSLV=16
report "LEON4FT netlist: Only NAHBSLV=16 supported by wrapper"
severity Failure;
-- pragma translate_on
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jc8LEfyzhB6MqNSbhlWuoMUFNYcybITivORMfB8rzl4OkHj0KaI8+xV+sqd+1SaETTyIozxnr9sw
Km8USG6axg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
e2glk2VzurZE73FjU9GxoFY8HVJy3A5KWf9ojsn3WHmQPwsWSCHzx/z0K4Z4C5EhIBc0YA+Px/Vs
9ZzqYqXeJZcbYR9DwEl2iFv4k3ZVDCfXfVdoOdInD07q3ji16cXuFbU36aEughYk9FyuzsFnvLzO
3eJRcKx9tyRTAy84Itg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
sGLPLHipVjTL26IUHSADhjydFNIITmr3F6TKs2hIYEmCIirlVMXj+FD4MlMzlCkl49pAm6Ce/hbh
NHUZrJGWk4EBiv4mT6yws4zdwXwiglH47LRzXpqmwy3byWUrOhCNgZwHDAK/7WIlLePQu1bfgnYs
z+28gMIxLoOdTVUkmzqeGliz127jUgVHeaDQuRQMG06Spc5hiR1hpG0qQJqECKt37e1wg4xla0sL
wImVQ763NgdU6xYkjH6TbcGuyB5lwowlA0koNEHBJCWgFeXNv4D+8s0zmDfUrGkxjHomSep6akea
PemJx2MPv5svdsWFZoOV4pZwhjzM4CkoZdeHcA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
T7Lz1+5AT058Kx95H43nryI2Ho00JIFHkUdt/YwNLu+Pb7rPXgmxND7abttOfbuDn0E9UvyuPQOL
RovwzsRTvitzL4knMlppkGzDzkJrreKNi2ze7EqNMC+UTgNK3cdiI/LF+1/RdCPnMbMqp3vv+DQm
JRPuqjEuyDs//JtALp8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
JMw/5G+LHV8rF90nVLGDHIXkf0FjKIISJK9ovLg3twB5BphjTn59rHLpRHyjEjL3IQsOTSkx3ZvR
VC89ktrPJiRNeM+nwE/e2Fyn/wazkfcGUhJF2ZUIySXsyCC39DXyKl0jKuBB5unOryt9FppBLjRo
BPTpcR8RuIzeiGQsCO7hupEXjn6dmKgJCsQ2ZVo9K6JjxQLjxMNtsArRv/yRaFQhRiyjl/x+XlUa
KTQdP/Y4Sih2RfOMSOMoRi0EndJz4jmYt1mkX4n4psjKPJY8V++XQ/unk9GtDDaz8O+4THcnML4Y
uqqss95MLeokZvgVRySMHhPaTjfi3noLDpNMYQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 61648)
`protect data_block
qc9xgk8ux08LJ/qPe39FWHtjRfE1EQHVav6JwVL81bxD7Ip/LnhRG9fhcyHycrpQ6mEEzgGIqbRW
H8ClL87DzzzCd1KGh79aA6tQBVg77hGiBrEg1JpqhLgCtaYm6z30s6spRJwjzp2FO+sCBSxjQNmt
2hpNVWC95OeREWaudMuzG1PG1x1GGNTJTwqsTmmGdV7bFn2iopQyGJHw1TiF8FQDf2jEIgFZEJqL
3RQMwIN5FyAlf8BXujRiiPeTcrlW488bhegnyf0mRh274z4TQuk1ks8gAw3eULDyVbYTNqKmobgD
2YjuulsF8uUlePa5MgNE3hLGgp3Gef2tV9MhbP5i3T7D8ggj0vVcfNihOW+mV0ipa07hh526WKD4
g7vjFDJYvRccFgvlN4fgl7YUiHnbG5uK27br9Uml8PGw5ZO5gnHOcU8uS6O9JkJcpKm4z7+bML6Y
0UlWtq+8P75mYP36Av8SQjQc4lvoDwxND89Zv/ZW7ldIJzFfEhKAOl80J9wKJcWv3PREwg5I9XEo
ZNp2Lhkr2fAa9QPGpNCKYbHLlaT9qTxiStpSg+rDTBV43aOF80a/gVelHeuCV7iaTv6C/3sdh3p5
xynTf3dyWBA+VZ1mOHDIEp4lNLU2o9e4TIKtq/UQny8U1aI3iQrF+XOTAV4PsbBCqxF+mIL+zQ4l
R4a8ML8dwg2YRoPdPnocc4sYts6CXsGc5JaEniHnt6xcY1NJtfqittGtKmv4A1EdmZrKtA125zWg
WSVsldhdaUokWkk6fM43j5fw6/OiNZ30gZjZ2rcXqA/iLl6VUVqXwFjICtyrjaVy0jwtZo8SlcOe
oIt9vcSHGGGyDnDjaZNuCsSd5AwMD7LcH4bvhqMSlp7SKEcCA2HxhGIBXaDnYXg+GbEP5sVPiLMo
PB/tdZLiE5wVNl7H/TlvjmSOqK42TfbLyiNB5VObuXPBDLvrR6ynCGqeSlXno6nMX2xbsUH85R3Q
IHzcdllWSAUgMqpjpvnFURAkoEyDKXGfRhP2iyI8+ww3E/O9njomNIY2Qugb5sYJvmTBWzHzGT66
L9OmpwN+VCZl8Z+Cnxjvo47RgjmSpObvoTBN7iYzAA8Yn5MH8SHYBZ8PTT4h0wQ/jn3eE2TvvFqG
HxnImV69/TDNyXtg47omOyCE+X0xYM83wdztcEtQ0fvZiyqYN/pSc+NT6NWn+iTCyrTX9YHQS7Fk
IcIA6ckum6RlQw75tf9IZNjohe/a+gYg8TMBP3Ratj6uuiUwzH29Mg7TpOFytwXVyocUw0cRWKaj
X93RaXy/5kdqpiYFvRZI5PmpF5/kK7f9YbQiKrH1pZ8IHIjaVaTGzYn8njk+/xFs/Wjpi4vQYoKi
BcAXGEUswIqXTl3v5BYjJL+zNWtat3MoEHLzsPTS0U49BxKG1SvtnzmkHK63V9FWENCenwQldIIS
C0YlGExqdlumhC5omUnaOt4jh3eWtxVJlQIvn1qBQS7KIY4FjfwcnSx7sW4wls2Sc9DcUULQQxaM
8fpyzO2XCFAfiiSojRpsVJrfufRDsCN0QmICjs69Ga3pFljD02/nBPbz8jxiRmDbWCAC1KRHtRgl
7IO5Uj7uSiYrhQMwOnyYEHFKFa2kXqP0OyU7fpfNG6KlkVpdLUtvJJIFeSVmmT13cgjj2IgFaTB6
DLgB8Ilw11oIk8mIoq3TwnjNe5PxVIgdQsANzXoJ7BN5jSJkooR1V+bqkDStm8KLVGcZ4uvKCFej
yDEBsJqoYH9KnIGH7Kt5RusBE8aSMChDXdvD4TSNTFRqBJxfGzqUEwFhs4cZ9Xr61EXxjyw1AEn7
uvaDzUmVprdLVOwNQF6yaS1EByQiZDrkQScwtXCmJlqcUVGBBlS8kVJ4Oo6fsKlKNo6J+IVUjSaX
2ch2tmQzTVS8PHOkPAPqTF9C6yj066bgBvPuhCmMuUoKUnD7F73YHZk9OYEsauH3zkrhKDpfp5yY
ofXv8wdJu0o+EwKgvt7c/9xYkY+/DRif0YHMF9yrQuF5xQ+tomyXZXIdcoDu+3CSNpNQ4cHE2l4l
XR3iJbBWpeET3b9E3j8j+r3EhWJhdJDA4fz/vu71sv/CV4u5yzFX3QrT6pO3ogj+qUFWSFdVpcuV
cukqPy7mZz+fSsXvzMXfG9wtNpNoAf9mFCVUv+wU3EHQJdfz529E02GmJpx5XHibog+5abof9t9n
ZfeYpvpyLpa++RlJN+MdEeOqebuWjbyGaO/tBvWHGb0oMaljBx8Nm1SHaJjcsNuColzw0Xc2P66G
MuKxcJXcUdOk/kII5OmDVmBiHwU9kBeBZ6HtSUy6sfvE/Qurd9rWJuzT5jm+T082MEooR40FUAV2
QRbmZMGy59yYUweXuuagtEWuwGARgXITJGYAHaP5qmP3MeApiyEGaPkYoQUuVG7KiBelgkmEtFJP
C4q7fphP+yoxxjyiQKnmriLZRxkjRWbo6Xh90dlaZWQlqQUeQ6aUWITepwHdIHP96c4XDX9yJ5s+
Dy96iqzfXdmS2lxvW/AzVUvacXxzZHmrlROqyqmIvnByCop9gFcD7rkuUUE/GLbRzvL3DaI4jzSt
v8P6JQxxgLPPF9ErEV7XG75mdRkL13rUdSnZsHsZoV0/BAY9PhM6A3U8maN9GB3JQDwuRBk/7tW2
VBNr7nzC3dO6vArRKnrxEyAvCz2vv+QMyh/lOFwpYXOXApHBKVaGt3JTx8Z2RMKvo2hyz89XKOjc
SoPlo3W5Q0UkHSZ3NNh6I/RfgFUx1A1BoVCrdUFbNevxWgutdtuvLAiel3+ESr6mStrR86xnimjp
/HZLEpCEst48+HAbQ0K8pdUku98RlJMcSGmMf705uhGV8P+RNI6l+e7tY7/7eyTzXXEn8bmmSuJT
JneICRB/bH7ViD01ahg4nz+phJFuQzqIplDuU7/+Fii4sr9jKz7n6riAFDHLxkGZv3Mv/8Rm3Av0
/G4fNakEyQGfgQJrb6MHrbrmpCUWj8C42myPke5quJ7LF+l77rhfGVEPZjhQ2besVj4FfN+EI0VA
41kJT2OLFT5ZomE2bva0fv5l0kODRcdKTxOY4RL4V+nDz2EkpT5d8blASFdn0sa3Qj+xTJ/MHmvP
4PE5grzuZnprQpNsEhhi1j6puZlDbMMnX03WNY6gOhITbl8zx+B+kFPLk3jvceeZgL3xg7vz4opv
30OD8uUWwvJJeZ3KfoPnLqx8moO6W7pBKFnRiEiSx5sShF+DOCNY3ijsrrJ0YU2j+QJ0eq1+zjSN
5RmEo5Px6HPlPcE/Gt6KqnlTBePEwH05OIYjLQLYwdDm1gyYBqIhr/PZcdq7RvZB2cxHRoyIpXsj
GCFjewWAPYIEGTeh4VJXTxKnxJO/PpakPK6tILfo4RneJfpoUJsBxBVm2JWSHe4q4mnYUxx4GwUI
8us7+YqiuJw2mzHg2eB77Y7vPUInE+GhORwyq1m86HmUH+nwQ7yrNn/BaUcslZ1vPy9ePAG0tb0U
necFGer4+JOLOt+4i97MOHRof9ahA1F2TEqv1W/k8WGXL/VdDdEGOkHdJHdphBKzNHQzyV5AAxTx
xWHUgvR6RbNoIRf/GnwfBKKAdhsKjnjOaL4sbYgAGoBSoRz3XQ3wnNfCI220R4gbP9qUJIUMXFC+
WmA86bhNmjnoQsoU1pZ4yL6mq9oLM/rYtcuoMB/03KLQj0GXpB4Q0GcquJWGuEJ+i2GQ+OtMESr4
5Sczxl65PoT7WZFaXN/WLjUw3vmDakfwmqVtnF6I1fJr6L57JDBig/QYT93NcLOrMGHWHWXqjHcC
P19VgODxCngVFMlgNK6rOPlVSBDlbAX6/uke2gxNXSaOjmDY5v3p38DJs5MUaGEARYuwCO/VvFps
lzE7Pv7EJVoG/47cTV1LrOfQRj1Lu3VEHEo5/OAmoT6W81IxxAU7L4lEUBE/IaqHqLweeYNhwft1
msSCWtzkPh/6uA75EcqacJCgGgUfx5DUp5I0kFFkxOEHWYp9Z4doQ1o7wyXDwY5FMjF3porIZTxc
vSqmId1IHTBIxMGBbIM0YcWfrlrIr8y8qRHUQc7lkP4kisYyUfbvoTV4O3MJzzEGzzyTdyLfjDvi
jukqXoZv3yW7aqliL9Cc3YzR6KTXFYxzS+EluXvCFjBCdXkZuhBSJmTNT0FPqznN1rV152vHc70j
w3uMSGcHRoLn9a1PXBngz9Tiv0iso9qBKde0xWgyE0XptyivecgZDxqChiN2dAQeuWOWBRNH1Tlf
tglvbjh1nbmDSLqCc/TPjD2ViKd8NbKOCL3vAuZeNlKXdSf/ECYiuGdVdAAX5doGD9brCY+tHCXn
ny9P+nBa46K+9sMsXlaxkPoPutqcYxJ4r8wFdnXJOX0la6MFbxALOagO2vdKgXFkqeoItDYD2H15
NeGAkDqjwW8mI/0W7eGKMBL7FzV/8u8KnAyr4KN2D6utnMh8m9bHxR6sMVW5FgYcmhgbW5XLNSNY
goxiu4gnZ1ezCr0Eo+R3DNiIXGP4qfjRnOMn1e+/ALXnkNBHGciV86Huy8fr5cc2nmzOAbOwJuFu
ixXDJ4I8PFYkgDXpkmzGWa8DscFo/Hb7gJWvVIH7Bmv5HlOuyZudIHemEIazF9dw8FZWEyQg0jY+
3qU7pRZN/jwDcCzp2M4+gzrTgtE9XLIwbUo3ja12HTOX2z4FYWq6TrqNPvtszQbqPBBb12rZEGln
kv3oZQKiYGnxkgh1EidRP/sD5whasfR8wt7oiQ9UsQUw8pdJzF/tsYwrOxpJeZkM52sRR/GCuUhp
UYO2XNI2tDaqhgPNDDycTEj7/ofQBhxn1ZvCQwjKeFSUvrqpqbyP4nrDovd4Wt7j5zbprfKayOmf
o6/U6Zhy6B703AQyIMju19DJG9wX35m9HQs/PKSzET8CGDTymlyT/l23YyQ528FJrFnFWa8F9NFY
HT8ADI6yZFFrqY+qzLP+izVM6sCPKYmcxMdrnRIByS/xlezt7FZdj2uRDJZil54H8LfvHW8lq7+v
iGoX2tRG7sfNQQU/fXrBNlNvIVnlDfSc0vKRyA1zxzaL+HYf9LSzEOKXeVTjxgii0/rGshdKqPxR
oB/KCA23VeG41zmZnupNHmaOT7G8ziycplPTE2w3lhq0h8CMtKIW8Zp6fIiKaVIVVdyX3McLnu5S
2mXr3JfZf3kWWMMhBG5ahwcJ54IHs9G4zV8bgP22SzkIpP7478/8z6bIY59ckL//0kUc8FrgU7Ws
4uLtIA/MEFB0ao/0yvI0tce9cK1EeBfnAbw7kaKnLhhk+oa6f9pyMWVwxLgrYSe69rrM/63ujVV4
Bs0DhSzyGpOjDolH0ri49NunWz8P7HQrER2NFQ9dut9rAHeZfz4ypxxr//22dbZkmNds2mLEz2f5
OyP0O6w0iM3vZfTacTj/CyzC+Hh0tXJWY++0i73nRgyYkWYayQ9WBW7+EaxZABzjY8nj8YBdgSdK
Nw5InR2cmqjiv81BjOtkjklPlbkpM2OhQFi8PqqwP1/mC0YjTCy3+pc17wCHo2mkfvJitb1MaW1V
H9s5UeucfNEQHO8UcVd+EXomhuDsiRWBEM2GyBrz9x6y3TczYsfHPoZxiKUNvM7MHaIgnXviKJ/A
ZscaRJ/5qLWxCChxtsb66OmFVk6DGfvU8+Wax3rZbvTirFKyGHSFmVBpSYSKLV6nL+qcQXToJ0ZF
udLoPCBJ0BiVMgsSPgzfAgKqOQtpj1Y2/nTRl+/AJAkQWTD/k3f+q7DD/XAn6T+V2QL/dundRP7F
3gzz0XFNkP0r7m1U0KD49YeXh3O9Y4Rd6CkwKMJfwE64hI2ZFiLacxJimznZKCmr9qeNNRKmTwWd
w0e4DGyZ0+qZUMU+dynkhBNH/shqBGckfAWcQp8OG9GHcZ+ZcZhVF5Ns8HqfIgxiNPamY7/eskQ2
6pdN+6AMbUZxs/xjlHHrG4VhLGUpOTnXBDvhOpXlGLt17kt6ANqTD1vuongxnUqHZQDzFrC1BCh6
Bb2BkHTiHvpr1tWL3FmHMvFUaPZS0LLIlhdjV5O8hAjQTMdRGzLZBVZ9lIcxd9s0qH4TEl93P06u
adGzJHqkH9d0duwodUwmR3172wLBEQSjqBZLRTbLS5u2+4BPXh4epv7SGKVvNmGtZ0K2XdMLNsy9
bhEgkuy3oNQoJExFCVlRMaS3fdQpHQyOdTg+nr5cR0fthkeDJvmmvRDggpi+njHztzUMQGe2r2e2
p0Qo7KN9S3Be+1jquEX6oU4msM6ucWijKYdN9e0bTBtYop8txrlX2/GXvjeucIL9IM/+uRMag72u
PRCH3K28pqU6ASakpfFwG0LKVQqZw93WFquO/R0n/tjZ4j239yCZjCu+zipa6Sa/wwVt0v5MpHif
ImSaN3NBAP+rczAAsRKkt3MRDS+KPY1mrcBXJl4Z3fyPqYjaIty/8Xbk7AaWhjaedlr3im88I5b8
zvHTBOguzktpBM8dLhjCEFPF4xFflve8B8XZkfRSUeMDCrz8pBmPujCWuI19yjX2hhuY7cJn6aBi
EHkRjtQibFOXB1TJ9mrFuqd/8L5KgNSseB9TnlAN/yamRh4KbTHe4+aEV7UIJfHvtFqXQ7NrW0PP
Pi5iT3SK4O44cXmBWkn0qR9tUPESUqCSMzaRjHFb+YJWGXC+9jwYRbYH940d/Lwb53ZsSeioKMs+
jG06vaAW8Dfv75JjphTp3YPnp1MADTTHcvLDDkTKGn0Br1vLWx9NkDJFGREHKrOwYZ4YOONQI2KS
xWkWO+u9uv3nlejGvtl/0D6JytpP9yJGqNgZfhcoR7bJoCr0hgXViViY77M0L6EVRMCKjiHX+y6v
PR9/DvQkHo7g1atfMWqED5M0/GG78EQ6ItXtTMJS+51/fL3SXnkqrHPeLIU35Czly80IJYLlF5vT
vBMdhpBeg1bpwpdoPiLYJoL1W/IOhcLNvuDAZxGU+hTX3aU+sEEoiOdD6AgERtZrFXR0P4jY2RPX
lH9Gv2ZB35cLlZIXjAsgE60MRvqvD8o8EhNoFt+2yAeBhJTxeUT4LNjTOR+QNdGbaOPSzLn8lndM
VZyZhHuGS1qFN+cPW+AvAND29iaB8EvfwTh5OcAlYyp9CQoqi8vAZiKcYtSzxfLSCVP/9eUJ4bfh
JsGrN6iDwYNzh8lXGPXIY58mW7Gdw5l9SxMZU4aMioZEW02apBFtzD4rk0+2MiJs8zsXRrozgDbL
lBvRjTuavnlRcGQZ8O1mfSEa/CGgZUGqERIt3v3LVLTE3f6A5EFfm6Oy4kFookgGlhZI6hWHAzJR
ma0v3brqV+5xaiMI7FWXVbTrW3FYZ3QARs0TkKH5m/9ZsaeNrSjddJTnBSNG+IecscYxnzsvpOwQ
UpwapIZZ52CPgZMRjAonsFTsBEVqEpsa2NSQKL4UV/EFWOjiNBtKNBFZpiOLw0YDMSevN9KyhNiM
h6zhAmWnMkSl4DZu12pi5GxKMxPhf7YnRTUobtOXpeuI0tvfAizVnSZ+rrcawI5GkqRI2QAZt/kK
H7wA22Hr6WIAvieQDA4lkddRJw/AUNqMrhJoA8nm7Ng6z1h1ElRRqbnt2oArsNqXGht5/y7jW9la
ssmWur0ZG5PjGfvOWhmlPDHsb68dX+WYQBUjop4inAJ7rkCdBGHfjOfPu0R4JquNZ0f4uJmdgU8H
JS3yTWsLR3r+ncupMOZ1zC3DXAWgbUmefux9hYlB+VSAe1smH6FWfsVEEzA/tUQ4k2R12U8ualz8
KmLh7AZUj5RVxfMYK0WtUgc7ZBC0J7O4CoBXbZIaljcpf1/wIgP3WSSxlqP5FvoGlupAIP9Le3Yw
LqHIlybFX8sQr5bwmKCqc4vD4AtyQPPv1HPSB//V2RoXCj98FmkQUubgdQ7da0OyURzTz5j89qok
UuXqy6/ydyq4/IVsh+V/DwDfFwOsncrUxlXlHVQ2FuQSDSwAJsxJwaH3uIxGpL3xaqgDFTTkSKAw
zkVQiPFi1cwCiYoF+vO4PrQEmWIKifiPiiLHjBSQpIEpaWvgpiKAPcs0V4xtUPZ2joCKe1UYtrWM
j+Bllm2Lc6kulwLUNVh9Z8ko0cCS2HjqSfozaLv+lPJFhFhqja12qavptqAyARAcnukjOF+P6eNN
jR5+KH823zO+E/DE32rcrVrjx7xTb/S8whdspXK1afgCgLG4jd9G/K7us2FB8fBc62iOqfgG9fVC
HYknA5EFVHcboAXSXnIgEkJo8UnZBw4a6YSia3iZKHRvJxBmI3vFWnpG1jNYutFNscTDBPjFCvzM
HFbJlhnCqm7I1dxXiQjwhsM4FHOayqD22S0P8tfdwx5aEgLyFJtAWWfkJeOGMc9h612NGLZq+pP9
NOJtYeApTwRa6mWACGrpFg8SCQwOH1g5zEDgjsFqY2P1vgkRqSusN0QugMjpZ0vVTkplECnYGXbm
5rJ6rjEtzCODb/JdOykfi22xBJCBxOuGsTMe9lfCYxh+bXv1bNUHSZgxJeXfvJAaZocj11Fttqma
qCYN9F6JPdVNPpTyIJLewblwapsGLuSJNlpLdTbrlFr3NNiEWBV7rSJcqetqJnCQ0ZHpwFt2e4we
c/Zqowh655VjqbQtypgVy2iPbWU84c81rmfM6ECYHBCzWKCZ4MV5FBPc4SeejxEVuj9GAtWnpbW6
gGnztkgfl+vT8AnnJjgRKPXxEAR0/m7pKEjubJlgUnm/vMzznCBOVGzW2gnEbg/yRBklYuljqzgz
lxcvyy8kmLmIbKAi0vVyPan8hjL0xrfw8G5at9vHKLDv7SE0npkfvOWzkUsiy2wlgo0YrQaLmsLc
/zX7DI31xazNBTVihViomHspcOShBA3PHXDXGLMf6qQ0jJATNVQwsUpW/OXppOvjfjPHAK2uePna
opo/yqDnMpzx3itgMUlzdu+AtK4Eh40b4hQKrhBLeyJbNDCZIZE3sZ1RSZg+W7daeOTycJIbp+T4
cda2Oq/w0fslEFJcFoTkku7yoQPz1tDWn0F/EwfZfCbWmp5cFvmBEfyyNR6+XJRR82gU1+mLa1tM
mpb406ezUvSTckr3WyiaxdtXOZgAyLDa9axQZS58A+aKqEyQgw7hDE0Lu7j3Fst6EFdMGNA48aHq
PmEOGSIlLUd19OQBr3lSNWzmatkn1RN16qGQ3dq3jvgDQ217LOGB0BQwuX+PewshqgZRPpcAPOZX
n0FBTNnpBmQMXvY4vhreLE1ovHbl2ETPej1qQpUX1svEIkB6qLX4EfcDC7a9K956AMAZK29gveOj
f1yTGzlUV2JZXo0Cr3xGL+JHB6JRwWYTwD7rFJ6/RbfK0LX0npLxQKUtMBvHBCzOktpfHHxkcvWZ
zkwMXh0PUcOQdWjctSVK9kwDTrE1+r7PlMWQqRG0a5gYL/oYeWfqYxL0wlvlvCpI29V+s6SNaSTX
vl+W31VbqQlruroumTHlqV85Zqg+feP/bMQVftsfqkDHQp/CDIsHBANY19P2lwAys2v+QTt7Xfl6
Nno8RnN1MAJzcxg0/uuDBPr3wgf62NuSL/toNCGyAYmlOttDG7t7/qC6SIEHEHCd+F+qtorI3LTM
uVHa3XQoFf7fsuGjgxXoalaqeVmDzN/XEJRWSRctS0AZbBNjqPc2Swc9shH2pQhm6uCcaS82zIoR
XLhW/OuMMBo1axdUbmNveP755Gww1oEUApKv7E13+ZNU4xb7uzvK2Ho2P5apmX6C4/n9VW3Y81+P
o8EhiGXaNtytOiVstVy/kwLkjUBTmaQELcseHS/VIJThJ0oANxflXQH/YbdOQXbvmEScUHQt52n3
kq+U9w++jEGdQh7MiEn3DFmPGOIchOLnwWDm15jbkNNnVLoS/AQhaqB8WOi3FCuyl0FYFR6RlYVB
oIUBtBi9cYmFDAzdoANPAOdG3etYUtMwappfwL1iSCiSkot0X1jfL8nAe7hSSe0VdYETphO/dSwq
EH7jVb7mQYmfSxPDs/YeK3G+xzdCNfru5MWB6BgVTLWj0kTkjrDOEtKNT2k0cRqfPeSmxq5t+Hcj
fwts8uZ6m2/E3SOpTnZXQJc8ydPO0KcJ7TO4uysz1SdkvJhjOxz3RytlFlOgp4xMYa9eVMM38r/L
VAylT3KQkPWaLELi7Lx0bww/pWjhVJuixIsQnI5NNhn0oL+XIWdLpcBGd3l9j0SZACCkAgD7yDDC
NLW21/qu4OjRPtvUBEPIG+Kpfch9/hT3LuKbTM9p32vtQpecneVbWDvQvN/9/D7N9jqD0FxCbq/x
1ErAHLw9wd4bdqoTCO5RemuKnvS8I++LjJDc3XHAQ/YNTzxa0la7YDpX+zph49L9iJGqJfmEJRC1
2h5TUUJv1ZHl24Y4w7XbFx55uaWWTL/xH+xlvF7iO1b/lO0lpPJydT24mpwDODGoD1a9QhmzLbGT
9yMf9Lv4dHAiFSAHoP2g3tEbAFKmLUDdjzLLJwMlZC9zrXs5Zrrbi4YkU6rk9RcHDskz76l4r9ie
YqgbI5iO8WMBhQCE9zRhsriQ+M0VjOcHchXx+1FfUhJRgbcjKjurwYlyChWebXiBvazn630xz6vy
K0+57SfZ7pAYWzesOxXFyfcbGtWZfRmP2se6ZDfTzV5jlgt+DWX9/ydrcBHV5+EV2a5eb0CVB89D
IS/FIyQg+tr7vOgwp0HhKf0mcVEQ7Ycd1xzaR4ohgWgz8i1tbO46E1e0zDGjos5DSjR5yQerrwfe
pwP4c3nAqKwt1QURhkmhJlJ9Qtd9eFbqnkou+DD3Q+rSruLn/CnROAU7MBNjs4VXHoeKOUDbHkkw
P9fI6EvMeKXPIEXo5XadIgcJmbFbhTqspOskXvoSlMybDVHm5Se3bXZkXsMEUEpsHVJ53I8ft+u+
0Go8iSQgrpiE/5Voi8XeLVAj288CL5J72txuP1/uxx3HMxnmhk488LiXetyHsxYWOB0ojssAqQSa
6SvS6P7zV2O/bB6YHGLaXvtikx5QF91TKNrb1oWiDYmvNjdwWnfHraHdBStn/anhxjH/3GiSNDTi
coS9gSGI7zCebdlVDDxuxVf8qxr0uLB4XWAX04kiAsGOuC8+wcF/+WkNNPQ5/W6jtP44EjQQrkj/
5/mBoP4KqTUh2kZ7tif+BF6tW8cm7grLVeKbrTvWnjGREONBKybmuowKR5nHRpfOF8sQaOxNmXiS
YPsmL2BXaO/5AsoVI+VY418d3iTDY5sRNS8Oi58IGj/8hK7m335oM6nlRZvk8BTohLtJfpXSk28M
chh+M9SLRvXy8C2kw8jTj41Q2Z0/089+d6N6YIHWEIVAznCOT1Vg3di9fIXApMGxTWGh1iYKuVcu
j1MpxQ5uCBowLCtsD9J+dXheRoYpWp4rjSgnG8L82GfB68rZQPgG75JvdiZHzcv0O3TAIlPHMhhB
PUS0zrIDGBkeKO+JuBSJcNcTLxquxlFdQd+0IWhSCGUVe6qmLs7d7Pqo4pZFHci5S80+b7lwot1u
GSmBC5Bsgcc88t5urjAOQJqwBIuG+fCa2LF6CoesEYCSPCpASGa1JyDPnZc+rbmCO613KAgFKEJs
mnvwrykWANwtQeVqDcP0BAbRx2oKVeR7DAMMXveH/IkuOuROl2NuVwjXF3kusRWJ+f/55OAexgRc
hvTUmF21JDc65YpnMx0nHOFuYRH9AQmpJSzTgWLTTEoYAbLQ3eV5rvISC0C0QtDj+i/yxo72qLUb
DWePjyUEFzMw6L+0AZrJifuM+ONeoewFc4KTO0dOvO7YOHcOA91XqsZUz55Pp9S3W0wZeQ8m/+Eg
YH2u8wfJmv4IZ4poYjeIkuXuAEMyR+j5MIMMVJjhi7cq2rC6WtyJQL/MvG0bGGLCXaRkRlYN2LTE
cADxUA4lDmkahKBg4OVCWCb2F9K7EnT1qB74BeMlmQiiXHu6+nI7E6dDsNwtTAGmzJtfCn611o7s
iz4XcqReuN5areabVj3Iex9O58xbzacf3Bcit2+H2+MWeZTyePvHT8kCNf/CtWeL1/8AwRs9w4EA
NXwAQVPxzAuRm3WQ8lM1QmlkT33UxVIAHvJk5cpTuLwfBfLbE4RUeOIV56HWyQEsroNeVrdSmoCP
yscytkjwRhTEzDx/QnBP8xbgzeB7+eJTBypRO0Xid26DOvQrWtn8jroJp1l7Luv5BZMjx8/t1BYY
lZzcxxbN0zWxv0eBAp3fmK6+zkePL1afAKD3SSklhWhjUrEYHbdFPsYVBfMMtUsenvhkhUUDSSIr
kj8BiURvANtlCORdgTI6oHkR5E7dQd2YHw4rXi8sENtTr3sp/vezk0I0GZARyquD8xnYQ78SaiHT
eXvCU56c3Ta+e/jocDQ4nWqG+kXLbRAzb/P633cUijNoYtumK7X3DA8udamyP7JpwlHsBQP+WUJV
xqBH9OjJx7N/NWIyYAxkHwB7dSxlHtZibxAtZjS2ehXKcF4Gz1bJoPJoq9yyg/thQalE2NMUX2DY
Hk9QWz0lcsDQbH28kxEgDh5TYxeq6a9G7bsUq3GR3+NnjC69N8z72on/5m/h6UNw4M035lH5n41L
5BUUSJc+6QljERavCcR1kEOrF+E5Cz91E/IyoY8Oa5l6QcXcpgkaIe+Yiqd2y9oL4HDrZI/Jp9fz
CqU2HzFIU7lqYBZAvSbh7aakmFDHMTugMI4A5RW+W+RmvN1xGI0tH0kpPlvK68eneGW4onr1iDkH
egFNsX2ge4SYRD/x/1TCb9xKAWjonyu/KgCWzZJoisJuS6/ZvRX5g445QHdmpUV8RYo/7ZJV9KRl
6pBh3Fe7wjYl/ybsVLf711V+WJ0SbGvga7OVIIspU2CeQ2ZXNF+we5B2hF9UNWwnwWLxL+qCd7Ll
Kfu1SWUjTYlAmvBQ34JeqHaAyKESAD/dbeFvQo8bEDntDNxLbWIyfU/euM3qqRmvjCPxt4QOKMdS
VeVomN6cw9KXVogUyfUdiuqnLDYjzT6XtUaoZWJ5fJ7bG74W0LhbC0BAjFRw4WUBA+9j2K5Cm4Us
k8pEKcc8DDu3JjK7CkBFUZ01vrM7UF6zxWQ0BKtyJPuC7DYZHmrSr1z7/dYrz98vHsmLXAkNNUjW
0EU5eHNZuBoZ/WfB3NdaCboNwV84Dsy3YrrpzToKq9ohhdgfjHQpP9YvfbMZbZxNCySQ4zk9pzM8
5dehG2pn88fo9jwYnuHfP+yDPflWiaANp+wunlD6HV4+Hd2ZXJ1eY7UFNmsQeZKX6UwJR4jhtM4l
GwZCaD/uciZEaWltH91URg16VTWZnJtOmezWGMA85Crum2Eyvfga9y8/rW8OMTujkBKZakOMbnk6
LiVieNFZ0hnuv8PE87UglWWRjiOmYrIw8jboIIi//e17odbuVi229JX849Sb76BfEg/R4jO+2vu0
/mjit89q7/5f3Zrlm5ckkEl7ZepZHSV+B+sPc38UmtqkR3hsU5pMSVDi9RPfVhyr43X8fy9/BaH7
iTQSaQFTCOd/T9zszN6zVpuQz103fORcU4fsD2+NIvz5C1UrxhRmjlkbiMlyItPZWBlUz7lke8fF
KjaQa7HavjNZfhbWqytcSdEnLJB9ZE6V68bHCIOm3SakFwDW4f2D4lYzolW97VeiiSOSHHFf7Zcu
FI1NzdB0LNB6OimGVeRaddvhlAUlfI5JJ/muqV6azGEVikhp5mufRxfnEVLM2+IMKnZyw3BkkhaE
dsae19s+3ThORQVJk3ui+WGoYS8eqrjo/e1pr1tCZ2EvnaFThnslW8ZthoCUCrY4H4V2L950RrHP
pQWTLW53PQbuDVkCE32KOELDsTnuYVzw1aJkdKXahZJaO4lVhai4HAlOeFhwZ05lxNjyZlLaLyX6
bF3i5SHu6P6Dm8gFcWOnMP8mDAWg0GuDRfYjVBINRq5y2H+9seK8nqbrhzPSe7tZVT3N2sfQWzia
He8IlshTWfNBtsAjeh9exkz94hlrPfnZs76Wpe49NEQ8VqBiVyY0hQAp+FCuGADz2ROU353mXNll
8ZArv/9k6qJAKf/rjEIeET594OT7S/rv6foXWiw75MlsDaoZYCWvcwWpL1NmT4SSVkaIEwXktaVa
2h8qHrDA3L292Z6LxCAG3EjWWW9YjwxmV570S1oFxUQjZM8g2OqugZIiyjfOi8BnE79QNWNM9LaZ
UFtYbdf1xwIVfg4aJC8t0PDDMZoNIpRk4INxkD0x2q7reYFglOsssql/Pwyk1xMwqHmZWPyT6j0H
Tppx+4rjQ0Vd0X+pexqbVV1drs/gNTZ8HZcacrqNTWvv8TQ3PTiovmxZ8e6qg2iY5LAYDMi9mH+v
+fizsef/yQaOASLpVAE/an828JiCYVtn5Vy6xwaFHZ2ESMBztZ/S2WBcnBMmJOU+gRG7IWtT1w/w
ixfXrF8LhB5GhN15RB5IVfMVUBDYYL2GcUDKsGQ2IVXxL7tBGmlnRlt+RQdRV8VEMDO+9O9qyh4I
S7auf8PuiEABcdVNwe328rJdGStlCL2xsr4c97wCh87oTFR8r6JXBBzzw5ZSFg8NV5xPOu/0OUDL
oIMofSaVIkTBUN6ii7Hz6IXQEFrFZscAWDn0Cx5VnAMSEcFSND+vgIwIk3s/JFAMq91eH5jQetXO
W0Ydrbd24Etuxoi6Jee6ydNLVhJ3qpNAWQRRRf/O0s4M6KrLKbCOiCn1698wvQymg4Eo+8JuOYct
pXfKlTIdtjM4r9NpuIgyXOIEoEGWowWgegs8bk/3bcV+5bgey6Ah+453zm5zGAmaOFRE9ZhbZwhm
QGcoZuBnFtU9LaAn8n5pk4zpDEnaN6QFh7jQVObzyyCE4EclFRyCaUfaZCgnps87e8uWL2xuoQnc
qvFiPhNOaX9AVHzd1l2jzR0Cs9UXardT0AofEiEjPeQ2EYei47AJFamM4PFwxY8LB6IYdsMFzhmC
SGuJ0KcKdDb9aoGu4zsALeGLvnbMB7qnJcUt7VZUHS2DuhAiIm1mg9HjMO0Hfq4Ya/HMNvDawc/x
C2aOK1o3iU1hTaulJeEmxdKRWqmHiiIoCD08Pu1zkD5qY3P9J5agogB0068tJivp2nJem+F/lnKA
R+6uRdZRQuaBwwV4TLJIeEnzFmsNklcrecpI6oXvshzGoTqhksxtUOcTWMQ18VUFBIP9+l3izbDa
HPxE7tt9XM3hk1LH5+nm3YRqrU3Adu7cTU/hos3tWITs/al3n5wRN8vLCPUNeYsX5sbcLI8g5Y6j
979lQ8uv0vcIkvcdnmBT6xECpgXBtifulmIaPHBSVpLuNl+Wz7oHbOrbehabQHlaYhzM0cgC1Kb0
YasC6iLoxSc5GpIU/gH5l1XtT35hSpfw7o97JlvJg26caaylnzobUOUnJhblGH3i0j4FcRLX5tlU
5UMupDdlqqinWlNcNYE4mETi/7R7dQBzJElED+LDNi6WJttUrDMSWfUnMufVubGQ3V+lqLQW6umC
/P0WMz+tBwJjjCG5xIvUr3B8ibVHLmARTVMa0WjtCqHaSRdKzcNoLpWNBHUqOjSLRKchEwdsfq3x
jVJTxx4OjtGdg1vFWRVJW+R0hy5E1w8naYoEDIT5TbkM8V+mg/uKYuEaKuZsXnYRv582MAPrvk74
VsYpXHhD2hcs1t1jFaHziqpblX53mMDj7S6H444vEA+9wwrca0Bpt9nqNYm5F6el0k4Fo5whkJ5E
oEjRNtL8c3h+Vx6fO3oA8dGqsnm6MDwiVdKCn0QfceZqLfmvnMcgBo50Evxoe06h3vbU0r6i4Yyh
1JYgjD1gyV/9pJ9oNNENWjj0jG+RUMtar2sHAsHKxUlHIIKDOkwi3ltLZVjabRx8Ee7ipT89YYCU
g+NsL6bui9V9gwhYT10FwfL+nE9EFvUcB1wvjucqnDLiY+0Da1JHLihFHf9kQdhasjHIjYpchm7I
JbSkHUFAHalT77vGiqeS4fTsum2sWwzzYDYQ9KmYkKdmn/awUHo4nSD4gMXV7+TTuAUZ2GGdKaGy
Bnj2IJ85mxk3GOo/0B15b2p+vZYKuv424w+PJtCX9cI2ncVveKaS3ZXObp2rRmH7ptuQBSh3ITsC
ZQ6t3peZGjWzjCPRTpwbJ25fenYMn/UbeS6cAutkvCb7eK+Bx8en5At8NlpJYs/JFf+Fvjeo4OtU
n2UOrn8QxgH+2I+GCgh9urs3/R6jbWN14lmb6/Kn9QxDPqi1RxPceduq0pgP6IuKTHQaBBiZzics
bJsU+5W7fgRVj8gqiRyfFo1K9iEIrBqQT25NmaPU1WocijRVIQo/M4W9yJBA1UYG0OxOvtCh6qfR
oynOIcdEq14Di3pCO1SveK5PsWk78Xn22TH3eilcj/7ZPkRYSN3teA2oRgNrhvj0lMkQZNabgl2U
dTgM3Ou21HiYJ3QvKgKuIwMVtWpHeyjOx1iQPzo0Q76QNwQmBp9bBSLHhbQvAQCwRZr35Kw0gc9d
e/XgvFLeIn/drYCIROzK0G2TGAGSgplYeoshcGasF2y4VaCtyLdbMMIrvkgPB1368K9dfUDzu94y
qw//Nu730Dy28sM0srAB6LRbWkAj7pULMg8jjivvC+biZbZ9aD8CoulDy+zUVy/3r2dbtQd5SZRn
OmKUzxp5uDfSQZe6pJfnoNkl/WhhLohM31a0ci8EtzwRia9SauQYP9ILFqRH6Hw9Vo210qZqRXLC
N26roGl8xs0VkaL4sJ7wFXq4//8fMgC1DOKHgI0fHy6esks7dBzVpFCPDk5Fx6AODv1JZ9/btHHU
2pYHF1003elylhwFVQATTg0Jtf/2wMHFPJdRwKApAdvzxzHWg+OywGvFgzSpiuONVxEmEUyzgzyr
lRm9bvwnvnOwA1rDC+4XMd/0DZEzrHLe4oplGTqgGMA4LRYPC1YgH1QYbTj/hOB/+AlUPfcH1xHE
SYrBErV4adxyIABPuL66Z7GmLdzVQ5T1DVA7FvRiLL3lk5QpJCqLEiVyGOr1bd+ufULFIrZy7WzL
eoCpAnJjJzHRRvd65Xb0kEsEd2VbRv8KPeigiRbVuXufq+6h7BMT3+zqdtu/AwukPoMCT5deFkG0
lqwC0JfGEaaWksy7nkVw2t9W40MwsGzW6jxNdR3CxLjuiXW1HfaFTpfrM1L0hnZ/pMB3q/tpH+0I
iTV0WGnVv2rs+xqc87FnTtzI9evjLXzUeMdMXREpgoLxwKubqVgOwunulOpc8cHenFDcGCYb5wHy
eMJiU5/tjo4TRm8XGn7KbKLFpJhSyRSZKSRlJjC+1DTIo0eZMR4Jd+K+L35zNXzhFpE4HcIlOJ1T
YuevJ5KrPyjRpkcnK4cF0cLWcFPBZZhvEAR69aeBtWeouM13VAxFPfHVOZ9IGbrRSQZOnLZZwtR7
G+vWbWU5Cdu3kNGUXMw57fWXHJi9VsTfJsJBHs8KzucasuPgOzQNnvkZbkyhO3l6cqUKgzl96VAM
VAT8/DLKpkC0C00EftwZwiWoDJeM4qCz3c+u7L3xLfubuKT7FrllYwuCnNrx387tacs5QQeW8GAX
867RrAr3oeeKhpS39IN5wB0/C1mczyU0uG9sVXNHZQLPpLItZ0Ke2pNRfZ5GSL4aAwKynNEjKIAO
dR3dR6TwuDWG2uAIQAjlWdDeHweDfyIgoQHMZVLpdx5+ZIeS28N6MxXoQAbcJ1VT8prKretOho0m
i48WhQM3WoEDejLpQ018stQS1D9CTNNtQB0zyBrm72mLKjbEIdGFl/V2Bs0vvcBSwGMoJZcE2uZh
ZakZYqXUpvj7RNt2631L9dtFvOssCzbmVuJcZH3GtcTOlvvZbVLdbBgWaax5yY/YUPxJQhpg9fw2
19xg90lLqwPDmJBIEnwjQgaCsgNs2Z/Vh7Fq4GXPFEM4vWARzVxXd+Clcrj6B23AuSFNJ10SR6DQ
DDjQjDsbRtHDeTy3miFxVrjVXa6tnKLH9zcNvZ65pK3dP0u2YppBJcjHbPr0lz9TogTcY9wywENC
6tXvQLa2t2E4TNLiNArH8O9eIUbBFaW5OMNKjuo1PZ0u7h2deuJsIaKov06f9pCJFtpMcwzRWI1h
LvMcSMMXyoHPBwC18PMydeZK6pZp6QLUbLKwxD8HsTcoDWAqPV03pvf8kUmieEMXjKl+nJxJAb/r
8mFY9EEuzKQfYeIDuwBzog88ASEWymLNJPU9wBY5Elyv9r3P+n9nRTNunphQRA7aYi6+SlvxEL2w
lJl7VlV9+zP1kFhBoT3uQg4XEy7NdTtfIz0fr223fBVMrhoXAfylHO7wGnGRKtKDvr92xMlkV7JI
PDF1RhF12SqZaV8Us9UJQNCSDPHrvqBs3QoHruRGNHhuj4NGbz7kcZdtxYfv0tzYNyDN3s50K6X/
tELbkvdsBLkGl2c+3eOMMXym4OQ/DMKvYmu3A185qvNhPhq3i5kkxYm3yNVlkQzSGD/gyL5UZTA8
yD5EuZOv5sThzwkKvSqGo55HC9/WpYmjwk9YzARC8aktvbK5QZINmCKMJLA7yIsDSKyqR80bGNcb
OE5PWo8xQ9933ZmmDcLI9cfoDLKH/XAYo01+CVuE2lNgRuVT/X00I1WRXJ00Ms8KQ6c5R2bk/PIA
5NPpwPj2QiuOGYIc+F3SVuAQ2TyeKzF8MOYkTiVK3R2T0pffaLXDHy4uA0VRh2QsJqNICyTvGTUQ
9lLfRGsWxVopc6RQCnFfNQ7pYW1CQg+PYt3gH/1Rt2+SgJbkkpSfnliBrnKEgQIbwMBMhqNHIEMW
wOjO8v1CMk1K4AVdTYTJmJBiTgsi76XA/kYQzmPRPxV0cwL8fm64ZEXO1OYGQVtfSNJBvM3Wj8hs
5v43KwDeXJ7B43j6eJHG+A/n90rsnrqLMTeJ0r/58IWDL/F2pDeoqArCtwVEig4QQ1v8gjteW9XD
Cz0DJ4DTTEbLxn2oGFow+GIXnGXmIEogEqs1PHhRghivWe8J4U7QOu8yMTYt18/OMWEcZbZ6Tgno
zR7WkCK+kvJ/n+m51NYPRjG3pXascPdllgv1ai1mrO0ZY88VWPsmzMOsOu07HSpFvD7Ta3LeUDgB
f1VvRo576qZo4HhS3bOpvgfJS5mryu390KFXVbX5MypnqoqFiG10KzPPR+0rMexdnCE3qEckf/3y
UJ9zTjQsz1HMi6a4V2TWEPwAuYvz3bxfbuK0zTaBXRlgjx/9rEapeWoLQmNwyNku66/MdpDfjZ7G
64pyYcXgI47TZt8GO3Y/X0a2SOXr8cDlOFp1TTQpfA/hsH8ASXd/tUFe4668VMVPYU9lt4FY8XZ7
wV++oG4Z9DPRoSo2a49peFz+JTxXnyQX5sRrXAdC6fOs3znQm4MuvKpJ6JSSLW42r3IihMFjERhw
YbogZrMZOZgujZceAAypI0f0BD9ZHbaqmtEGpdBjIgk6ObjTbJj9Xdi6UQo9kVMm8p7lcfa/y/S0
jX6xOAOfmKjxuDj4XgxIQ988lXomqynqmj/U/CLFYyT2mhUwE2GS24/PJESIR2qw1ljp6vyD6HhR
tf6KyTTCoq+cklPvlqDyewfKesuMpb/7ljL0Ox0OBvnMrAzlMVIk3MTR4HTATh4L5A97gTq0aF89
qUbDAUuSx1DXFR+xvgJEBnVxYG2ZbQcn5352WsyKZZHAJoOlH63cmYlrr/DXnXZ8Xvsjr7iEILAr
jW9ZqlBAXPKSFmnsFFVkdovNGEg8TiDbmAmBngZ6kICW3AosRJyhnjh1HM5RRQGPEwJ9U2GHHQRo
WATkuwDt/BCI4JusC4jlqMCWlPb7kVTXJZl7vFssJGmfPSc8swp7vwv/mAmBSrOY/i1DJxz5gXiw
C1EodBvl+lYmOnbovXc59I/Jizy2+LN+i51mNtJi8oUaoq1EQhOnct28ATTiJW4K1UGyM2ffv+d9
s4vb6RTTF8005nVuHd9sNacXCubRzbllTrTCyT19OT1/gLfX2HxMLbAuK3+nOupxUlpMcf8DzaH7
NdGb/q0aEzz/QvXFct0w6eJmnCETR7HE3CVyLI1wcGYLeazCQskdvdUgP2RxDAZJyod2jh41YVPm
pKYq0CLExxuAQSl+9o26GYJLIwSOhHlTVhnircbu+ny99t7V6MpstSSskpkvsMkd8/Bsxc0jUuqw
0NTolbXiPNTpngSX34j98nND2zDttrZCI+eDtmbQnhPwndgxIYj5dAbJB1TehuIPa5N+Bjc7flDJ
nZWgycdrlFCL9Mm2HpQ9CKiJI5hjU1rmtPVvKgbu+ezpoVgIAv7hI1D7ZylPZU8WHRlaeemuM7a5
jJ3L+qF9va4QyWc2JhBjQSDSlLr33z4eVgZXn4NausuJFwlLUgjf2IpIFSzcQcqDy5cw9QTSpMyN
wOiuh43jsMBp3lPxp6Dmt/Kr7Xlc2TSjorzoamGlRuBWtg1Lp1C7LSuLQw5z8U5TD7MI0wTi5ElV
uyZjNmcbyH5EAZqb+yxoq44ks/pBUgUtP+TzwtjsO8DEKxBQF87Gg4mec2VTTkqJDCXcEAsHDVj8
GnBkgTU2zD0UkdkhySB/ueP/W+ADUJtrrIiFBUlmMgo3dkqXDtYaKHalsg8jodDD8t5t37oEl0fA
Li5ba1UDPFaaZol1lcHQuftjM7F1rPxZN0J26EDQH8QyFjgRKMWPtdr83Q+MlNQHCNlFlM9Mpede
qg+Yc9GumnI5v0U+VnlmyClibf7H67RjLgmjh7ege8aW5Z7Pl/+WTAtkT2Li6LtAYuLD68wHJK/B
I/HCvAoLJC7XBFb3PRVoENaJcIeBacjzp4W/e8T7AbeAv0VNEBfUUBLF9wwwgrI4aEosmdHzfKWD
c8ww/3VAFh+BUKtIxF6rQlDVMt4zqKPk2UnWcBIT2R38/hn5U76yzPv12ws2zxfC1CB8NlSlVyiv
cGRat4Itj7cxkd1hMIWKMokHUEar/X4hxK5rw4v0s7QGr3HlYWxD6Ts/FSl1GrXVY/8YQRHlP8+s
ezxllrBaO4Mf2K7fWEzxuFmC0t2MPl38WwFKYUhPDHdPkVIzTGCtlJB2kdoFSbhissw2OlXNgCxM
KJv2wj02b4HjSpqU+A6jFMEdETaoivoBOHttCrscRJTT3TpC1xXQJG7rm6ghvnOJJAndhefbsONN
mg/T+sqqukwGT8Jk2z2sM8q6I4eckQBAiM6FXOiWpLvrPGOkpqnVZUwY8WZ7oxollI/9S5DH+dPF
M0kiUnw9D4tq5mjpPkXJtvlryoyOD3o+A/pWvRdFYmB6oJJKHsRLtIBvzQgTPucf0YYqctgyYxgy
QZu9m0VyHUw8OG/MvpKK6QTiW7uPMr/+d1F9e5LZK0E8NOQ6Y3aN6OGqrH/eqsCW85fLUSrhQNdB
Ij4FtF/AuAWbGOzMtDmhA1ug5WqFRJV+VkebZetcBWYt46gKaiKLKAigVmUryfWGg6XaSeFDhz4H
5VRx4pIX8wvkkOk5y1m9bo7cWvCD+4Hvuiyg518du58bq1f8TJBWU7HX5kCVptVKBeQFyUQO1fi7
PxKVR2Qjg8q5NIMuHvhJsD4BjpaYpdiUaWHXEy6V5oFHfCNz/5097e9PPhn+D28lwIjcf2RI+tXa
RB6XFjiMtQngQith6xb9a8cR4slotTXFOjfn4ukO7q63dHTbdKdkqUzGi3VoUF3xHavbT1D9s4QU
Jz0Vs8aGER+mpwSK+/otPVUnN7aXIVOR8EKovRthMvXthjrgrk+pAGUMfrojMPG2jIBLywbILNFd
CSerqRWGU4F3gELdgJKE5/tSjpzgcnBLsKXxo1GEpIV4Ww/IDudc76JJBtk5jWRAOeE+6OtJI+0m
9r60YtF8b6ZA8w5m7D4fGNek6GTPC1QIOaXNlJ58TqWyhPXeigHGnd1VMOvQ0gUvj2TT67nJh90C
wKcQkNeDReba44s7EgnQGZmuK6W+ApuP+KE2sMssj7NT/J7nGevhgMBbqrH88zz+0d5QCrqTupIY
EUSE+ZGnmZwP+2hYm2htCzJ89rlggAgrk6efLEQUVfiVXYGMpKGhoQk/6TT0XeLWjR8ynjb9TNUS
hOWkBKs+X8EMgaTJqbElb1GHQpMDdKwxcjCDj56oHd0AJtFj18U7hQ0VbSagfGQUGlev5i0YHCqq
fAzYamaIkw1QVzL5/J7ul9sST75J+y8vrl0YkUzZy2/hfsZeDHNlMGr/V1J8p4g+F3XxOc5a4gwe
s5lr0p30H2Us1PpX7pP33olDmF5awKlo17i5xiISYXlqeokn7BnCrFbS4acpu1p42tEgO+vn2M5w
nVJbbUPNnk+ZVyn2lzkTpT2iSrZzLjxRKg5gOcJtTg+k5bm2VuS2xZ/sjI4hbPU8+634IoAWyDKf
x3Tzt0Hjbo3rAc1xtrQGnMxtkCoWTRJ2VvhTRzGKTGnQt6XYsRyXlmkyQITgQ0BdeCWhuXAsGeZa
9PqPjm2nbbsmkvdDqtzGWkk9eq+fDiJnP0ym693U8Ae7Cgr9WgT1+6WuPBXLuf67cxpbZaMiU7Y1
cKK4oFbKJJlO1bOEWMS9H1S+BvXV38jGubXnDDSUplI25vcQmj2/v+gqvHV10Ybsmo4IRrEQuOvr
PElIetgf87Tp8ZLG+p8HKXYj5XPWKWx/DWZBeYvDSQffQkxh5DwCQ21o259XwtJC/NLB9nYbmb/T
XXX4w+2i0Kut/+b+cjZZdMlASejYVSF5mFPD9duCcyQ1Gs1bsrRH8HP4eaV9fu7BzFMmclXD1bJK
7ubmYJ4pQ2k6e9yihE1f9ZHVDwQ5IOAJYOtVLqM7Y+FNERGlkw9v9UiRraxj/xdqy0UCyKajFyJe
LrHMnAED3BgRq8X2CTjdNwC+VCxOpVv+FPLTd7xM2n/js03Z2U7MFANIulkPXgG0fattlsaF+JUs
9kfkKfUrfQXSXa1cPRxWecltqzifL0le0RMxxNLEDMDPu3+g/xT5tJshqgPkz2Q60Rp/5ZWFUC5x
yoEh2ytR1cVzKGH8qi8f6WhVxg1QjoXVRukwC1SzxZYNE4Sohx/lJN6MX4HUP6L9fLVkqq6aOHfb
W3lcVe18KSG7fDAD3GfLIQ4MzeLM+7PaflZiBgsaDo3OwZVePaBtAGPe0qEBljuehqWnlt7EwZqK
IYkCNK++eG9vygjVZE4KFVqhn0l0CpJxDS7+V70Fy0YBGj/V4uQ9eK0j7h8v8TTaSFvdlkfmIRBC
1ozFrgFAXPwj9rfHtJUSe++JX5vxhJWMr5q4fobIENMsJTv9n2FXusMmLx1QxsPjHsDTztQJBhm9
Pd4xtQL7ErwsXpBNl6PvvYQimQhafPMDvHwKItFXNANfEdlgPBWqblW/DtdkjgSGqSvz7ATsW+FS
7GlPOw8fbNtFpp228bR2T2IW+qcEI4y25i+6HRBR1YqVNPu2oioxc2EXZL/r0WEexlHOb7WkOtVc
fWEaGaohM1Qvte8fr8m9w17evss1TxGlDMcGzQ0YCLG+wshFlJOo2Jg7b5g2lOeRcfiQUQO0Y1Hp
V+5hvF6Oi7V4Tgw35HQy4nFAQXP8mlxQaOdLgCShwaMOHMCUI0ovYaH5oB+YIlYg7kxdYIXhKT8Y
669dg0JZV2m4e7gcKwSYi3Qx+GQoVDDawWKNxlAs/SOFYgvhkmf3l3or/mR0Ogc3DNQDIIUzd6th
m63LA8M2zMiI71cbeQFvE4kk48ckkUa85UdQUr67gBDFXn7v5dbJoq3jkHiLizIXtUtS8U32+jKf
FTcesSBDmU1/B6/HdTkZ5owDzQPLHTFWDJhNFRo6oF7aTqM/tV4oQKGc8GQj7AzptjdM3ewOb7lc
+h6Qd25E6Mk9T/EA2CODdgKrqEs8oF8DjGFTjO9hHnAbxICBzgdVyHI44itlXaQZoJtjYMmSniSQ
OaYicGLzRq0fF6OtqkSt8r9aifHHFbY+XAHodSRHV6EnN9vK1Oo9XEf8pOaMUpZqPw1iJ4ODRQEM
bMVjIMwKLKOnUukXtNVPd95JkQA4+v7hhN6cKqd9ToZEDKyF2w8DcE50gKU6C7bue153qQaoaM1V
hhFBvo0utJ09MKUSKL2lyLKpBBL/gTi9iABDMMpU+xu3LUwo7YiEI0BcqKYmhqG1aoJkVtMg85Xr
hDExRMdYFSdMWnY4Ds5ZI9auUCIxeNQfy7lhCSlKr8WWEhRRUlPUKnV0vEMsJuqMKQUu1fg6WuHX
iAvqCSzNjo/Hahc5Cf1zshBbkmEU06fEgqQA04WGyG86Br5PSKbdslJ+IYzu6cQUGY7E77XxG6ph
2euRoNIFVrpwC2ddtVfm6H+JGURQz6TI95jg9+vqlTtlWc4r+6jPI/8b262ueQjI7ZRC2RMXXGEC
MP8iwWsRO0oz3chSPCZzNLq8T4Zsi4QjYHUhFRNqeBn7qjHgSgfRH6CK6BpYiPdX4cRMdWlYQcmP
Efyo8ZUR2dkC8KW6X5cI/kT/t7SBzE3sPG0uvtxveOZSKB/cK34REqLjbAMF3pxd5w7bTbe+oROi
BIzYn+DGhbThap60YSBCO27XrdYWVWurqfN9VffLz3ZsNwSw8hPGmpDe30TR8QYtYoGUhwjI9vnJ
0y6nwcfWd3h+LuT3S7gr+199hV95xMto6twaHgpw6gNNXgz53T0LgT63gSm7TdvpNNUdMCMOS/Dq
oBVY5Ol8wlAL7w7FIEk6RD1N7MlxJa+hoR1W5UvsxZYeGpo0rwV9wc6/WVJa8MdDSymd+ZkqKRWa
S1KRiemlckbF5ekkNtdwVo2ljtCLZFRX/e9plJKFo6UslgoDcUD9xKl7oMQl3zSKxRnppe3mYtW2
tbzflj3GzMpzBEnzAyXj9VRMDZ3RG+jayh0UUD5uZulN+YqanYZ8IMEVg2kqrpkxzG2z38an7nY7
jecDtgBPGUx9MS0WfP8zyVMy5AVQIUv1MJH38IK9T7mxFyRvVv16VC02zc5k2/tI2quYDcGiIbzR
3PioTlNSHZUZb+s9MLTPmrPSwcEUSvlF8sqjOlV0U895Dcgfa7HTcEmM+wFNIatSmFoOz6KXoqI/
zyWNA8piAzddBSPd8orVGZGHJ52DX3kbbk3+9PwDSj5OTuuM8ENJ/DCLKk9B7XI/9aEJjLtmyAV8
yb21MAAeLaGF5pfbF/gHH3oQYMvAoOy5s7G2/TWJbHpdipERtsrO6+6gRJSBeonoUCVmu6JsPB3F
21fV82PTv43L8XBFT7miFxFYW2xvylSO4h/zYkEYsWg6BzFovth9zx6t18XHNKMiCuf/JAIAPdRP
6TH1CzpGWsVbAxW3/rM4ApncS1JGQpN8/YP8tiPEpDLWkh7Ek/h8WoXqcr4ISAnegIBWf91pG3yj
nnjaVBWavWmAyRdSaQHu4rkxxl6SyPIpKYWNE+Nndy4E6qvB+gGXJPjQKoXYrKwSD7eBUhPlxZzI
G0s7s2cKiUoFYrn7BinZGHSfI27JRVdTs/Sh6yQU9V4O6xQGwqKZNG2pNsOhfNJOqJ4LJftNhU0w
Y5uNitGBYhJqlKWF2EgRm+MKdoHe94duWNH/y19MKIR9EmpGRV7qJfXT7b7kj39l8HYU86cE7HwX
lInKWo+i5JXPmJP/NHfsERfTJxIrN5tDr5lZcMuGucg5KoQrStx5kHnyJr1Z1eAtCIl7/9Kx53mD
28BvfDg/l9L2/ZMZCVsf5oVOEdOU68C6QG08wF0bZrfpxJldRUQwxWF/sNR2W9Nznf5qFG51CA4H
99jceeZKzLzTYdIJPHluy+TdKjit0A2DQMMtFniU8v6GPIdtOXeeTiplqWjxQA2w69zf8/JqmL1e
RBE+6GgH6nP9iaUvvtLYWFqtkho/MdQcC0ioaCfpRg+xevLuRxBaqdd1/V4h7hqc78OPW1dORjAD
7U525GZatsDteZPMP1m3JDQ79Wx2hudpSm3NqDhGi8WU9Hz2sQOyeJivfaD2yMHFoRYWbn0xUKs/
yZ/LQo8EhrHCa5JZ8TAG/KcCj15qIoDwTq5vFl/LRtypQ4KIeFVPX1cmOwM6piJVBnj7Tqo2hgwa
c40Dp95XvseqEyqiTktN4QR22B6Gy0r3izcICC28uavCDPjlZ3aOELEeVQi9yOpxKxep8VYda6eM
bYTSYZdtPByfqnDHAxxu8DqmaVLQR0xP8I5vqdjxBxL07yy3lbYDo/vkz/HpIv7F2vxZZy++s0oB
2Zub23spBs+2LwXGEMIGk5TyOn2eQhebocYCGeMWcC1+/uh8I4JnWiEpXzAWpCRhVaSD8Qz1eHBq
LHS6BVnmmDz/Kh1qepUZlguEEhQnQRJ2PG4DWtWu6Z7R9UuT7pIQwSq5p4DGjs4ih536mnaSvm1/
7X9oj5hAuvBrcyk2IRChjyOZp9dPfgDnt54hIQ/nkoGnih3r2PWX9HQGp9+tn8CunVVkaDeBVR3j
q1kD0MUypYgUQTsnUCIgYXZweH/eFW+dzaHZu/ocmQ2vQvsAddQ36V9oJa3BzLYKKDQTarlr96va
RAlWyzsdsyr6rAr9FaRhzu6GO4afBh5CzwUqtPCojN1hFT5fkZSUhdEFqSoiWSbfidfYag5Ipr9c
j2yr8geYE90Xy6lWzXgpS6IEjl8DHxYRZ7qQRG0nQ9remjCa4TvE0m0K9B24MOuzV93XOjY9B/uK
FP7IYpNME5CdOYU1UGXXEQaKJOXmxmJUer8McV3seNNXp72X39YNkOdkbiy8RHo3KdtER8lvrv5h
oX2qsrL3mmP4pav38AddlVLhnvtK5mEWi4k2bbdiLNXjZWM0AmX3zo1XI6yhDGXL0OE5u+lVa3l3
NroLphRV4/2XVJpIJJb/gUUyRZ0Wv7nKKkSiYnwJQtet41bgKUDO4zDab9rEQGTq9J++0G3w+HZ/
nS1u4WuRGha7UhYnCqmcgJS8zOeb/OjijJzUQefG6OVebm1iAp7wPErZns3A6vIzIwu5FDVKvfT0
/HEPeB7ENlRXmEUNd8RucjPOwwK/Sz+PuoCYfRzsTVgg2OPsz7ab8c2UWCeqCoG589EfQoyqKrSQ
tt9nGiHZVHwqs9ZKl3YYT9YfcZfgo5GAeFPh7AiF6VwgS46ThynT/w9XlvzOEj4vZGD+TbHdJneX
wQtubFLjR0pjQJjxeV0+8HU3buYLAowSvVPh04iW4yGA/+HfKBwTX/OHQFgJtY2yVVCWcAUa4zEG
pHDcQcy6D1kIExVRLpNdkH9h40db8avSTex5PuzAMsL9qNkzzsqi1CDXdPQPBhUg5Pwx1Gfu5XOb
o0n8zOT5QoUtp0S/hVlEhEL51BAwRTkTqJIepmmRIIlwoh75kc9Xfsle+sAXD8LdyXyciDNj0uOG
kEV7GYExfh1xXjjyJnpSTzHEXKU2ljJu2Q1NoXRvMOW6nuCQb4wCF0n4IeKvv6HbQd4cd2iYD7xe
kak4BM6nQx9do+Ajpnq9CQ4zEKxtkO/fcl/Iamoo2zXJ2u7LpTgN6V5yD8GlA8vCvHLCTS89T6iM
4MZ3LSbdJZs/p8QrYEmUODTt5ppe0CPJV69eDsdYjrot29SteLnbQAd06VL/MvtK+jM98PyzZ0TL
HSJq9ahGPz6M02LDoc+sDBnMJJiRz2lNO9a6QS8ROzoof5b21oG/LCMVIo5HT1H5bHL1vo+Jc9Q0
DlkeMl82usJEZPgrBBQ11QyQmoDVA0GKTlIS0Z78hzTYebXIG5/g6yy4LoJwnEw9VtI/HiPNat4s
ewtI591E6ZRFJ0Mw7KWBwdBcrv4WY/ZMvETt9d8xzgfRnHgJpvRszbYhbj58pwH5sCn+0u1GcZ1w
U/bGIxQEQnedpSlbwM0ZMcoEakrNo6xyVHFaHnqY+73dvRl/VXhqOzM5+ewWXxDeHYG0aqBvwDlc
C+zfCJ/o8EHEcoVF3oZryCNNRZ9znaItaIPfWqsytT88d5rdy4c3Dc836GR2EF5z+obtkYy/loif
Nn5F0h6VkZ8O0Bnxcg2ssDVofFDry95aJj7OVtP1lIpJR60U1XkkO7HYEvsFOIamobOmxbvyHEgi
fURPJnu//rWp/6nT+iY6hok7Ds1SyvBs73+nGA5Q0H2mrnj9Cj6UsnLzOq9NfJT0i7Y8os0NcAIc
E1KIJnJr3rAaUTW7ibo0vga3wvai1qHdBUTJGe5gJBYpBVLNW8pFtn6uWqOGz+4aoq1EhBDTr1yi
NO76mD31mvNaa8LylDlnIAsruFIqRX+aOMa+e0n3vvkSq0kSd1kzAIWHNX2Fse0i3QLgz8Q1qcnN
PzQVQxaQAvKx/kDSVl3REu2iizr3hVShbnVfwH8yZPyHXXXVmRGQhSKd2hhh4V68fXIrvD9sSiYO
JWxGhtmA240lKkFwe5uYqi2nVZpmsJ0ICYqsUy2qcvJrahs0HVdkC2x7+tHkdA17rUjmT4yesPmq
ga0maF7PIJxwKooW255b5/U7UXL95AJ3m6pRmrIi9Y1Dry0zyqEjhRUavdhq+rQNMR2kbVRS86lB
bnjP88UKF1DTPzVCfVMHqMzxX82hwj3Ku+imDTd2T3g7GvagNVATtJogTodomAWJKw67pEgkIQMa
fWIS50MX0BKxSKU9WFLtNU36QlNYF8jD8vt9EiW7t9W+LrBVVwATmnukI1VABxdx1Jf3E5HxUeV5
9Gv7Hs6yt2ZQrb9FYOXDNtOCPD/m9uoEjRnVoiOjw+BS647rVAdteFDW84q7wltH1w8CsW3ugDg8
RNTEpM0HVgf/Cfyl9b9vvY+Xt8Ug45Zuxe9LQiTlNALHWZ84+NIgsBgozscUjv1ML7uv2mZT/Svd
WYBOfgWEbe8r7yoPphjw23o+DThZ25ZyVfOuM+HD21iefeQaNDvnu4QQn08/UDNXytpoLK0lsA9Z
uVQD0H1M7CkFlFh0p6ZWGV8ITFifw97nzPWclEsDEKYfIOS+WFuv1RBuxaHcWIGBJElNXvWuD+k/
JuuYPbRdH+MgtJy2j0E6X/uufQr9kfNDRszoYzr0kWgojmLwRdUW1FCj3tkkJ/ToqayNMmTxndSq
KnuzWhPVkmUNDRL+t2Kbm8/rWjwFo8E+5kYZqz5AVfZfDzjIK7diqtDlUiorVZ0+GIIdZYUIuKRO
E6ySHh3W5L8m5TVTE/+3xUUY5JiJ9LhXrCJYtU4kb6YwPFxZ4bULvexft50rbvQKSGfvzbpedOLE
WHvVxodanU8e7IeXkqfIu7EDWU7bIrgfb79dV181QIyzTo97JI3sg39IU/X5eVK4N0QIBqB+t2bh
aAKo6xp2hAq8mAts8wUfHHIpsgQdECZuOTVMj8vXdu+lb9lbfagp9kdgm4pWcsRrNC7V4TN5f0e1
gdBcwqm3MC/WV9W+77cdY0vJLEuaWvdeLGnIhAZZBOdS3mxy6lx+9wu0IAnFF5NnUkRzck6S1oRx
kUPq2p+LQjLyL8kTF/VVoVgLNRmVp8Wf2coFo+ibdwQhRfmNkCuBHKcJ2qbI1wJ4X2reOK0ro2ar
UUt+ThMweISbosvdEwz+7V4fNjwogloPBfYZZj6TphLs+jmoT4S+3qL9/9xmZDTHpB2eK30oHZKq
dL8A0MPC5IH8PlZ/tQ6zxDKw0kqvI6z79msqX/gs0ninSuD3dN4lvbOltrq+XYibDyYBlq92qKkh
tAWyMvZdAHqsGTtt9qHbm7licb/UVzTdZ8JA+7FTWA19tTnh/EgsTHCzKD7YvDALQLOYimiPfk+B
8ZLaYjsc2HO7TCkpQZH8ThS2WQe9cian/4pfI8tH7iNllJvNwYifcNvjyzu16VQ9/RzZUc8UVREl
+7PMTW7DNoCBYtK3miIM9mrqX5AeJX+gG+P49kbgV+FunGPtkZnpxG1dMXt0mGGRZY3yh880pCv/
1kieHgLTdPFJuoTECBb80NGtFMPa6N0LLL+ObFNuPK/jkuZWEdh3ermseIXgEPZVrUGj40Jx1+WE
FujnS4RAYur7J9zlbNqkMVq6Ygd3sPX2hy11Nj8pXLPI8WT2/jOBqelyC5TW3MMV8rnM9Dgu+SoP
AsTADAiAng2oaj0gJWkWoNVZNrjTLP7jBczHdaYOPZVyc1QTXfU/n6Dcl939cMuPgFjqYkbeA564
pyxx5hm/hlUI/LCqkobnkkTrzH7LxBR/5eKnUDHBkPtvMdY19yi+V2LmgKGKndCCLCxvK4aPA8AM
91k02xp4hCHQfek6dPzeuLdbZUJCm8yEhEckDLXLUC1sJgso8Ufffdayeun2ftAZrUIn2nmzKqbe
e3Iimu8oMzJf0EOWSFAvD13Ma6P2sKQn9OSjmgnGhBEp3qyzGqm0N8FkgPMGgUXUAOtiiWN+6S9Y
Z9rOs6BVb6joUIO/1dp3HWGz6yZEyfoTIHmWB6b5VM+PBm87YZowES8wapsj9PHNW7rmOCI3sf+9
PECMROCbytCSLlzfC/JZ3AQ/atFfW2+SIKSlbBgjZnVz2jo5Me98BiXglG5knOtR3MTYGPpNgqxo
M5dc7oh7gZWY1uRuaBm1VIxmJW6q4jzG5bTIjP6xTU+2qynUypZBxuDAHDcZtIw4aVEe8356CEq5
warr4QXEaMhz23/Tb1aZCawInuG3UWkRUDY/L3sitNcge1da0yoyn2D4xS9ubrXYQ0vdKT4hFH8D
PUbu4p7Tu65on1mG26CcPW3f897c5yHvrkiqPqoY7TvoTohXFaQPBxxea4s7VmwGxbs0DtzpCmt4
83qaKCGnSHuwUmB4thf+omfK/jTz63YACrb0+82vUFtlhkyu9aqA4gycXGaZhoYMYp0ahkEmBdSx
2q3i5t4nZmyf/s0BpFFd2rm3tNiQ8F6opXprdNlLosKZF2W5OaDNFI2fG7DYHT/NnhLjrU6wdPD2
Em9Bhqs+sMjMz9aKJyvIqxzm6nGUAoUyxRnK/6+es8/jtvi8I0NQzb/WzYFbvI6Mp0fiv6eExIaW
a3bOGeyRxhs+qG0z0gW45wDhWJwDZcUn71h5PjogdfEvvWRur3OBRrchG8UKGuwASymvuZL61hTf
Fx4qfKJZPXsKJhzSSZjtrobwUGAypp0B2XJumnZcdb2dLP7LPk+xcKLp066BLNaiWiUujLZo1YPm
nbMF55L5Cm5qOAagdo1PSXD1nURs8qr65wDSj+8DLq5Q6QA4e7OBaR2oh0oi93Drldxw4qOTd6Rv
iYuRl9R+SAY4uyUORPYPC0XLJOI2P79+lgt8k+FeTn8KI1PerbbzGm+t1SbCAmc4lXq+du83d97F
aKwNrXRIpWSYs8R/2XVkPBs/gB64zIMe5yeOK49w1Qgcy5hw2qpdI0yFL3Hd3F9N8fx3U424WTmc
HPkygNK+9tkB8cVPLGGDrF/BhKwImzBaXuNTJU5cIF1aJWRY4TkKS5XUK+x/akk9r+xcsMUJG1QU
vGebWpTxQm50DxAdYCiFhhYsL5LIpIfVAzMq1RyBg+xgh52wS2NuGkyebJSrw63Sb/qsQ8+AZFRR
yszkAWHnieOFQAqRJm+gu6aQMSqfZP7EjTog87kgo2fdSoeqDYY1kGICDal9Z8peXPKAbQous04W
YIRqe/iZvw0wW+ZfpLc7GN4jZyy3lAbOzkCIeaf7mlWP65q6MRqSxqtJPXkvwohoS7YMpoPfnsCg
hYw1y8EkPF6Xfc3YxhtvuQ7Ww22Pnf3jocJapelojIGftn52+2/Vees+uB29G9BoLZOraCQttyVX
/tfiDQ84Xu4hXETdUOmHQvORFD6i6VaS+o+9F6XqG79qy518X7z9kncj5pmoeWphcb4s0Vp67It4
6mvdlAxwiYaCXTl6w5uBSbZa9JI1Pw/bBpkrLLHYgfWTPqoJKtY0sr6Q1UtuJSxzrBLnsfI9ZrsI
eL4VgUFPEXsOK4/UVSCtrl1Ijg0vfIXhglFShKyx8xNyKclSGjatrGSf7odJUmJ+YqFtL3V/rdPM
aMch83M2LMu2XvVxpyTwSt7lqkCHZz4UDSbbizzwoCo4eTG/Vf7q/EylvBRzN5za0MLD3vkEpzgn
i8q7xErDDbbS+reX6WzHwHeLTlRQ30k2oSA8xYELTuRObqAcC4YtapSt79S/NYHD/OTZ20azFr78
RkY0o2LJ3D6cpNP47RuTx3UMRX1C12Dp2TK//icUg1sEmnYlPKvx0RRzPFieoD46Y2JAqCVEcN+5
rKjGfLQpbhuM3dw7Wwknog2Y8QuV98cl3nYYa1iGNgewoKKT7giyC3gVXl92n//U0ZJHUxTBLHg0
SEE7xB7IAoyRK36S33FFJWb9XCaFukswlwW2svcfO/QxXmuCgd00QhOGBFl31J23h0NCtnjqMp+l
RwUoYo5g56MRZmhWjuO0OqdYixrY3tb9UrCvg1lJVbl1wPx3kegYfT3H4ZgkgX/qQcgknhcPrW0K
FypfDCBE1gF2FO/OQopvyKerpKkCliCVVDEBS0AV/ysmsL2SA9iXFSy5jN2qwjHDMn/raiI/eMSA
HdK1+L90GWvsq/+tgCO9/EJtJIyhUse6IbgnHjsh/bf6BcM8Xkdv/aJYy91oYYOTUuxbMqByvynY
vrJ9kv6IjGZZQ5lXnn+OEhNE7fZnPeQ/OCihBpSSSCU5ubHl/7Kq2wPClwnssyjYgidBGciOsK01
BaLRg2wPUy2pHNwoXzJyMmoz19CCshqsd0w97sq9TsgHFPsdk0WULVWLCU2CjTHP0010Qp11WCkJ
1avx1Iu0iq2JgLpDc/lAgVEIDQ1Gb1y/JGUHeNnKcFf6dJBQVFGp1UsWp3Gq+hgKXjU4RwY+/UFq
H1esmjwXObo69QxmGn7j+dl4AXB3xQfTwsfgWEgWUe+6Ohzn8eWeiR9QZo48r5cRSQ688743l7Ak
MJsbU7M+asMyCUxvQjz1kVYLLoXxiqLkDqZP8BoFK9O0SW5wur9imYOAIbcXnzEDQkGnpXa8Ikef
HEdbOV6DJu7COvkp9Wqcx2vIXGhzB5FDkCRuw2K89LR8hDM2vFxOx14B9m9J0FJx98bMiuddoLUi
u1wQtXkBGqGXAagb8FMId3Ndh4xoLuDkhpb0PGrJ8HKutNKsSN/R9s1aZlkXe6M30FlufwSOaD2p
bWal7bdheoQI33DEecEYtoeYS1fBZxjGv0UcvDsUX62l0mhqW4wIs8PwCN/IVOD3mIGjvsCnEck4
d237Ngx11SfiqwsMBM0Q3WxPZsrs48DQ8aRSGd4jCgMqFgmFs47RDNFxocQvgyn4msxAaXlpd5H9
8BVCc2n6yV6VXnL/0u9v/aKW6Ybf6xG5vmM0ixENXzBigIA7ytWuwSkYy+Inw10p8NkXBwugdFFw
t6bd6zoXklNLcqf7D9bRE9hFAvjVU2AR2BTjN4z6zYwxGYQ5cMxyQsUOqMkALAZSWw2tO5kJ1hG0
SBOUEfUkaL7/AFayWZ/ffGJHijSU1PJUpObyWZT+DZZ9ZZX0HabaKLHTuGNBNPwQ9l1OHWYyrcee
kS9zIW+xAnmEqSLRTFX+znTiIy+2dab48cS8ijV76DTmpTbqraZfjTOVMkEVX3XLzksrBLQRd0Qy
hV2R0yZYk4Qb71lqXhTHKIpM/YCc8DVF74zCEFtpp+hb0zVhnL93ZrjMBa/YZWIclGoOo07fyUuW
MTxVXZscZhh73lJG9jG/t1FpmtnOe0cZzRCfg1MD2UwSk8Ur6i4DGVzV3oqQDCwWEB8hn7M21O/Z
/A1lSaLmcrOrWAI0mG6+djdVbunbEBqfyuG8Jd3jCtIPxdyfGEUwXxpQ7NtEV/5ZciW1WHbwHngp
SF3ixMJLmMRY0hxY4Wkt4p6NSjrcg31I6wzizA16WUC+C9B9+Je2sAiCNbAFAs0rndw+pN0S2H7S
xZ65oThUg4faaaRy+Lx3SLK5N2hrzdjdd6vaVhE7+unjC1rpXMT9G4l1vFaXxl/iB/AFQCMnyDq2
Ejb0ILUh0M4U4n3ETozyyRwYw0q9cTrcB+K7njnqjInW0qWOXhNHBHcWr5rErnlCYVQpdwYsW1HU
uVVNVzlUqGcUdJBa5nAlntmhDYA21UgEuXrZ67+FJNstfwmp7ludAZUmNEgiFlu5t7heBOUOwEuh
gtTSka7Qvnmn3PMf2C5zq7fMJxI+mGLTYw+f8LuYAjR+mrqyvY+aEZ4mWP35p2PKpdP6XcabsiPp
p2uun9XPK6SzM4iJqLbIvBOXMF6PgdPg5Iu5LSDEyUnO/GLRovRwckl98qu8qf/yL7JcSkbavpcW
pUSe0saagMQVmnxWqiH74NpccvZ4mT+P6KMGCOoEHZqh9JvE9SKyD1WhaV/uugsUPR8UMQxaCnCz
9bwj1jp+6PTpYOfqnN0QVUZxra40BqmNrSXHTYWPKHZd+gpfifqiwHZgamjiQQcL40jA3T+u6VQ1
5VpQ+r6PHDBe5XO0/ndlkf7KmumYvIawpj2ROQmKsTEs+TtvYFEfjN4AN6JNIS6LWVKcPamchfcT
JEJgb7ra380aRlEV4Yj1rDH7iiQ24A+0R+q+7mNz2ir+YA8/DDIwoflAS6KG240T0a6Biyo4oCAl
EfmI9Ojd6/iZMfIKi/sObYR4ZocU6L+vUfFMPjn4l/QCD2mWb5xf+DlKxLUGi1O09UrrSGklR3IZ
7HPqSMPDmY8KoyPBFgjsbTo3b2Fl5gAcZolcbVeDILrsSs/CzJZmMJ9RkQzkrxqEIUe+cQzvQD/s
1lbzeCdnP3Bb5P2ZdalKRCZ/fCDoYxQADOP2PKKniI7sL2HSO07fx1IbAUhl89u2tsggxzpXh+R6
cNaETzPJaRTsIKo3ersYK/nWgCFFISbSE2e6yAJLRapw648Qmcqd8M/7OE/WtSVmHkPGHWpM8jVE
Q9vpMmwZpmndTDCBa6tufewWEUZtfn8ZXzBwzX995P0nouyCtT6eQ4YONwObelIlb6/81gx+CUmd
vLjCXDArco9WfrLxb0Uj9w6kARyGMpYQQDPX9oY2b0Hthfed79/P3XVm3XTnRDqnXNsRUl42U1/q
dSsMnYPicgPhsL8kgPSF0rcVfbguiWmCQdWFRt9BD/c4g5fa6MXzDs08xZsBlybptOccDqRs5Xc0
gCDEykLd+9mOPbjSoxPtWToihYiCowblOqNENAFdrjU6PMFwWZJbxtsJgJYFG8zbN2nFWadJr1Jd
mkNgUaoZetApJGojVMbH/f+I2PO2+DnEGJzH6lrJJY6W08LcaeiIQM5EUykOE56eI0DnPhvcKU/A
f9lG9zh/N8+j8L9y37fDvWToLreKdVpc/z5WY32iPHnCLca1SwWfaoPX30C8Ryt8ionY6FVWrqaw
+3rDGEP34J62W4F4H+W54gI6cDj25z0d3V/20/UDgjP2ISyQGwnbiuaynZkO9TKXzvbm/9zU6Pp/
A+MRShlV8UqSZaEf4KGz3PXi9ykAGshDavJ0nMkZPqa4j9BIOX/LBtj4qEAZ05vcN/2ED0siTQyl
zw41CzmMtmv7AcN6Fy3r4XMx8WSuJI6fTiRYIdCLLLJvj5e9LJTFFi37zZsTcSBWaKeY2hxzIm5c
NapY7XLiKozffKezX4GDVo9WxrDKUiWi9b3u6T21W32HnSj4BRNdJpmpo8G6iwKGoCzqnI5xuZJc
cQl03v7Jv/ri293zhmNjqA7MNoGElc7u6ThOLfWgGtaNV/2Ish/o+tlVSYnaQKBrwjs16m5URJkL
X0cdW3OdixgHmsjMeai4S7PrJgOXsMct/3M3+GSjUnJQbr+YO49QP9K6QPkvaop6VZgpADL2maQW
dCOjhytzvF/ZSt/46Cv43Q/JphqhPZOdKX0gp7aUPZMAD4wU3K/iuvQKP7/dCJCBevvyVa9qAH/3
AzYA/RRaWaT9GGPb9R/GvUxmMqK4LkZuzAJCdBkHsvhGsKLE7Bul/kZYAXojO5ykTcDKydLxhm6m
QORgU9nozVYkZIURl+4mt8BKSNWqmFfTWdGUkSyzIOj1LsheTk5jjTm1sodbZ5DsDxmLZrN/JMAG
Z19cwMx4xG1Q9mnO4MEoJbO/45JT6RZx/CDBwITA1A6OeOSBQSLmfSni7KTScPzQqCN/uNGuQHSy
sDVWAgMSZF0VPwmRlC4xDStgC7k+MJ7xtMm3iexuZnZq9CvQFKxUyOfqs1vCLvzBbQo77Fw0ZSbn
8y8IYexE+TgwyiKl24gn/W/RH4hIhztXaj6IhzNZ0RJMqL+0eS0X0KRLqWtEWBWoHmv5l3IFJIJs
fKmIEgJKrtt+3kmBrdB5RzSgaFTejFhx6sHl/oIcCL6mBHBwQR3WFCgNS7gbaKUa00EyW3CfcXRb
xaQejObF4IyM5v4r5w392SCmZSt6KejV2W7ZO7z/YT3UmLXsm9Fypdp6D+cyLZDSkv7PKeUmVapS
9sgTIu/cwh2M+D+3U1hVPVVePqzp4q5BDpXeIq+9766FZN4VoBqycSZfqJ1C5Iq325djhRjdRMAU
9Q4WAY1L9ACH2+Rqci/fts1lWNrKMa0L/X/NKPz7ZwPPNfXSjYzASSYArWvpxQO+YdzNX4Vp6/k1
w49f2RCzmnDHL6ae7pjzWXLvoTtvNIjxhkCA82bc+vbrxsDlQ3+8b2rajDU12TMVMD1z0GK3bdnB
VHBi250CYgBkYMMFhrUcsjkln+yLJDUg0YRu2NWYPx5wGKRvKUZf7+0+WZa7oKZNNSBO2IVZdkmu
xArBeuUXWLH7RLn6YeXEFSoocXFqByT6N7zarIHIJ+i8P86ad3ukg9nDPPpQ9evpjzJFJ3xdu2v0
DrDH/rDS5YwLYrp4YXcpXFdAR9whRx4feErAK0QUdULi8AeUidJTa5o0qs82AB6OFYgIXtyq1/jQ
tThDp0shw1txt21t56C+LUQ95yWO8nTJzCUs9aQayjmDzMAxiE+71q8V32Fg3b5dP6X0XKnWxb2E
z9LsJSYA/eMf3ya31z9Z/GX0I/ErbB8KnQuiRrp7WEG48+9FsnCctdLEsRzvk8GRiTAyMXXZw3fg
5uy5rnKzw3p0QCMOsxNwr9P228z6C0n4QQSuXCkiwgWxzxDQ1WOc0uzlMwBXQ9CgYpUGwzuSgH7n
pRKtMsdVLRIQdhIHc48L/pH9dbn3B7MqTIVgoTn8uRqr0UOKRlA+uaicenLTAMtbsOU2vKqdnRup
2NTHPwqactTVTOCLdUb0LAt+wRfTwdgNxLplv7RIcZLR/XHjvSbMXuWFbRvF5n4EPbpG837UNpRJ
FkFCPmMMYI/mmiBbz4K9mm+ZRvdJTs2rsBPlXGY3iwI+BtfzuI/xyoF45qyyaiLuqdoBzP1ddT+N
W85B48kyDAwIitTxz5epulXlNRxnMLvf5Gu9ZqTFryDXIbie/9aMBBtmVSNXJmk4SAjEBgBZ4lFZ
S/Q5G/wzm/5c3gn/5d/Or+irg+UfpKIEI9w0zWBdzI6IVw0gTp0rqtS1ETc8yk7gMOe/oDFedqfK
LryJyL0rpZIez4HPN8wsirnb6xv6/HD8v/VQFjfZWIpLwTO1qOs+mx04nOpFhj4LsXjzpmEKS3R2
LJBdFWBcDIq/kpqOnxCm2TfWSRk+4oHrIXawBIzm6k/evThiKJ7DptM1Y9G5fssSCFOx3qViJh6b
q3zhVzB4KC2I40kMzOztLTToqziJYRjLXG4B7imv9q3Q7svgcTU5GsVatng/AlOTvIuVmXcSgEUH
LgrKpB0YpU0LX1EbsEyvSF3RmWpqmzpARRYMqpmy2m4s/O3GUKjsHzmLdQeYQR7UrN3IRc/+ZUwW
2U2RBBNthVxVxDXGkok/iIsg9Xt101W3tHPYGLB5P95/Gyh0Btd5mQ/g8B5+hcdkICFeVYMwfnd0
EN0vnPvXR9M5f+CemVE+j8ibEFJreyp0eGbOJEaa56+9v7mSXiOQ8teoZvKnkA+QWXrJhxmsjpBq
qIYUYgxu4tkr4E+3AMFh+9CkfaaOl2hu4Yzaz/NUCdG42JdL5++F1JIe/5xK0UJ+udyZfCsgApwE
NzEXnkR8LPujaxO0cvr9fn1SzM53Us+2UWFdzJxHBDwKjh+b+nACh3pXBDPYgx7KvTGm90rcloqD
UO+/NlzZ1LyJzaiMosBE+W7p5obBNmWtY2EhrCH9lEpmfRroesKMxl4KV3ibO4Xp349VeVZ38u35
gPcJx7IykOVGAxZjgtUKfUZqR+/iE9HentmLtc3I0OCwCbAUpk0Z9FRRJwZ4dpQ4r2YUpVnuSIK3
Jt3t6kbuPj62J/0zVGt0m2B/TJoHBbcVw6yMIFwQuhiYrUoKqQpHdEKbuHCWS4xtcKsJDS+Isp89
nKyYzSPXgjxIfhN8WBFqNUH9HVCk2zpBLyMIy+/rm0TruIOSpXKKwLz0wGxvxRruyvYXPBgc3sHd
K/45lEY8Y7Yq+xhHasl6//DD6qVUYAFl4XZsFzhXI6qSFZSBFq4jfFju7ZtTS0cUIH5J5nJ24Ga/
EnKqi94i8jd1AiGLrnB6KRgvnlwQXsBrSYFfOQgyjd+WjMREPCdh0Lfh0ANvVlBbUQizkWx7MI1O
b3JaPEi8df8c3gebamOZRXLH5miNUi0X8R5IK7q2cg4y+XkiCLB2a72Eeeko/tkGDU3uhdAB1Ixm
wrg6zgaM3Nxt8+DFaM5qOL5NK7QrPkXxzSXiBvPyZqdZhC8UuoGbPoRX+ZtCsNbfPYcpMkRBnZV4
zuXNlH9aE8M8lmiuEGZdini1kgt35IVPAuAN6hfBqRh/Pq6p7WpjUeZNLCy2UZqaAwzTv1NJK/1T
t+AmCr+ITRssy/T8hTwtKsD3fkZuggkDOu74zfpXsrHAFzEAeWP4I1JoMMU8E1Xn8R9TcHoAPnvM
WzIRN7EbPbBFpQLkCyE5WSHAMPxy4HhrlCz138Y3xN0ZZmYOCb6EnmJoSHlVxYJorwmVtGxVOs+s
YzpuQyyqkH6vU1qQ+BBbRC1Thi5pXFGa/Sf86WL6FIB27QqjdX88HUvjZ+SZMldqbSYeE4onpqOB
e7Ya7JsYOOnLyEPhOZsFlIRSgRRFoBAvTjTU7knDnj2kMA50vJtPDhyBfRzLPKzOIY9ylN51z0o0
J+ud4nIQv31Ses4jg0Gt43vrpyjKPidkT1AZYoWXwZnvSzOxsqR1DafPSkzrtlxcHQM8x5Rj5ZPz
M31hs3UW1CUdf8GokpeiUTtmQQcPHkEZhW/1MgymlLR8pPN9u8A3TzwT4FDzCxQoV8m1fTHWfnWC
I1K3ClyKyedTDmvDPEX+ZnFXSjm9zgtjTHGOe2GLxniv4dsh3t/EpMXAiqnUjkTPtHeRZc6tmnPw
2qJoaOfH7TbAQe7XLRIwu/GG6/0OxesBexSmrlQuk4OWCFSRMA9UPdenAJZnvZtDDOXt9HVQk1da
9Fl/BNeye0bv00Iqzsyx8abQPc/AZxSr5l7GHuKKUFg3xnRY7/H7bwiTPUOPv3oPaZJ9Z+ndrZQa
nupDTj7pRf35uRpFx4VQ7pBuXTfXFHiv3J9d8FBoBcjeB+h8lJY+8Q74W1+CnYvWJEe9ZVlO5tRn
YdCV+wBFqoMatwInmi6FgBY4Hw0yM1ZamD6ri9VL8oAy/HG4zelvsIdxMvRQll3BZQ2+cSb4+QkJ
z5+keHU3jFiHaMjINm56oH8jAdA7T61syyQTNhYf2DnAQIQzzcIznRDSeIoPyVovTOCTLSDAEP3U
9GdYYbM8FjuPDclaNQP576uV7VriXrq/2ltYPixf0IenmUO3+axoBON2weJg1m/33g5EklKEqmGw
K/HspW38aFxQcxfy1frq5pK3hn5pn2xOU63M/GUIbUyUyGHxKrmwbwe8lZgxhNi8HgG1rJ4nxqmn
ZIrRtez7Bkf2th7QK1P0R5uo4q0qxUG7HuOMGOlx5zY3eq/rFUCik4gLaUGO6CqMsc0t2pcj7dEt
Isn3zCUgLqRBjFvndHRnCwtVSuJZ3R1oO8nYBgVq0ru+GNUVIR1YsqtW/hz6HMgImII5h+gfRWqu
X7CEz1wSnZJElTt4FkX1EGNlcgFKJZqnZlWyV9cgaJB0m5+63pZxEQ1FcVMDcZVolJIP8YT8R9TV
UwbOi+inko2XbWA08K/cvTHcZtBgmlHN/rs0+EX8GFzRUcdc9sqO9g4ivMxEj01Izw0wrMUN5VHg
z/YLOLgs/tSUsNfIhuEoj+wtrcw9ZH6Exgp+qXBD7Fw+7H/Q5Zf29bEQAl+xZLAXoNg+spydvmZc
4ciBUhWiDq4fjlpyNaHHKP04PTi5AxFANqOTRSoX/hrtu2ytXvr9c7fICt5PMQ/mopc2MX8XPm/V
6zu8pECXHvbIeHoVV462gNZz0mfaPZ8i1LLg4NfRqwAaa0Epk358nimS3Yj9UO3uY1slupQKy+Me
sb4eADNHsClgovv1Tb0Qe8SNkGKcjRCSK8Vp7Tmdu2ld25Gv1z3sd1oyU7I7Uf0FkHATtFcPaCq/
uWaRr2lqt4JwX3yAOBkbhX5hnNfjZbWIkDNf+nfSk5RB8p/UwOV4YiJwp5y3LXoEH0cAs9LOp3SF
NirCQScYNiWY8Bx89m4UheuNh/NotQum3objIHDLoOz17c98BTwzJj0hw6uEooVewXJK96N0jzvl
K7tOzias6tPH8TVmyA62dYhUXyTwnS2XFf58/D8v+3Dq+H732yjpGjXwXqocuPnsSwUHdWX1fRfx
BnufjwHJTmNI097USlITVhF/yC+FNnGKyfqaYbsU1m3/muAixX6AWxhQey2PiGivSIwqEyBiYelw
u4lmgA7ALDUOl27FO6h7mnLbqIUtvjSk1rSHwLN0oTA37uutGxrkai/EmZIGYHK0+XCZgfahANSY
mKGfk527uQV7uZ2jX1RBehv13yih5dV3vmhHid+yKmkN0wBJtigDb3RfF2UMp5WK1UZI68iP25HJ
xJN9VgJQz/yvihsB0SZxFNZLs3gQ6YcJ02ijjvmrVIDWnFrhcHXTEq2Ar4+8DCRbDVA2J9kHv8cA
8R7AxeSM8RiX0IbEF/FhpdgAOewpiMts8oKkUFey55mskRbTsJh+DakRNcPfIcInQJs3BV/Wfd7C
fd2gHso3M0hE3sNY2qPMoI+vlpJ0sM3kr4dFEjk4F/IbKXgrTpEsTYoqe7QBugB4GPLh95ow9YZ9
is/WZJJDeDpIPn7r681RxvG0Af1tIIQu/J7h8eJHe0TQnrFdOtdqFeNkqBgPdrdJOqVJyJB9eWVS
ghhv8wXWylnnObbLNX2XO+HwnV0i1nvlfKKczdD92UnWp6xwLNywBfDXplq1RpGt2FnuqxvlqM8y
gZBlcKnD6LC/lzYJ8ZWBRnnEb+00PNkVuzxnP/h85zBWxwuWL3S7nJ8AVjYy9qS4B4vqL5a5aHhQ
6fAeF/q6P/+RRJAEPWydjhI8BrYB/Tb3zMhC63P58UREyhANgRgm+8DIZ+OMZwJ7xtERgHmRJwhh
fDoNfYwGpyG685x8nDzPS5HaG1e/Ggr9j/Pu1zu6HqeHz8khko8hbTX/MkwKbLX7uehzEHLE8W2F
JljimqFLkoSdJUkfItqraZvWYPPsLxHaU9msFYB7+brpsMkncpoO/zStLsQaIzfIqHodD3i/0LoM
RLLpaJyX6ygApgcUsslqF4YQFVAUQxAj3/O5aNi58avP1P9US16OujRsj50LTAOqTMOfr1UzG1cP
NKHm22Rnu5KG4ZlqhRWYxlCr6h1/TF2kBB4p5WcLK0L2H8DS30wztvZzwAX+5RxygG0eRMtMXQ8h
P7VuhIPiT8lSos22Hl7V4S7lI4wQiK2+9lgS6/xh24Im3CZWTGwEVV4eIzA8N9LCz6LITM+XnhwH
EGVeu5R/BO3fyivN5XZ4ymhoBngzgvxBTYAdj/eZ802MD/ea5FaQvzlavNbweusQu6IP/iHV4i6I
C5shDzM5huag3Yoxfh/vYkDtOGv5o7NbeKwtXZfN3QLACSLc62M6qCfxc331nwZ3L8TOFYvwkcfr
mvieJ7lWU/n7HU2rH2enXQXYlJn+jQY6rzL+BHQdLggMDjZCNCaZPYiIkBN1kjO7Apny+8A/r/pM
wTHlEQRDKe56+tJNe+xzUvGDEpgMnVG/uX24RE36Aj1kfxIGSWMAxQYPmTVxmwPfvAwE7Q9XfQKS
MGuTMAoDZjqA3MEZo1In/wdba6UYTbCiUbbbRKq8xkbwRR3qbDBk3MDgf7Fr0/wP0/pQLHrahOed
NQ5R9Ma0kh/bUt1PVwD2Ruqm9PN5t5CJrGA170gtXUT+gXwCMdS13+UzD1h6QaNyfc7BtBl1hkg9
cBqw6397PARb3LScN0QmOPe0EYo+5X4KMEG9/DjHIBub7yw56RaWucIvxFm6yDlK/Msq7HWrTu9W
hweQWlURuHLm+rsGuaiRM/ysyEjUEHC+2y52+sM7dX/tfNJkp/3uxK6mazAGEy6lNTHniJZ0wX7C
cXSqtbkiC4sVWV8vUA8jxgHNPyQmWAxst9yWXNsDnGgxkSY+cFGkJVEsfdpbNxGSnC7KUty+a0Yp
TYorJpiLemjf7Nv6y1B9p/OEZHre0whmFGAWdPJM7d+Zu0AELbKuoRMXdq4VgsRWVoycixiFf343
NJDyRKaICcwKHXnSmgGzoxp1XytZxM7V+HoVztn9DXSvWlBF5p9BtpkxFZc//rj2m1wrFFBZCygB
bV6bbR4bPP/dsQXnaMgvgkKViMiwj4SnE9HWOCDTiiRGAEgQDJJBT6ONPmSJPozKKwtwJuBrSfdB
9n+RRGocsIz9/fF7LOrDWPRaxiH5fXfj1YTDrp/6v9w3jto2kDZUO7pd9W2jnJpFP5sifNWhZSPb
FjSCG+wQ6KFMP6/b/6z6vpwYEl88LB/dgBFHeAwulAZbiZcsVTIkpqdeHOZAvE6losmHPlSvVhF4
uin4gcvQ5mFQJlYBp1wGvD/VgJtpgjIsu6gnm3Vb5gtrPePoAjHUNIlNvs5PVehm6hOPrOMYVkqc
9KJGMEOElJDLaOdQThA9g0dheWOKvpt8ESY2oeWSiIsTTgccU5486Rk+/wV9b7ZFDi4KuBl9lZ1g
nZhdhs1MWGSEIVixdzePjx4bTw5NJAe4i8XRThIg8dBN1NdPpWi2ClMncwLlbecGZiF0KY4T5LmB
kcEIzjQa4DEjgaLWqK1CeOlvXTT25GMXtAdgVs5Crs/whniGzYOA0NXE8hgWAG2dPG8WAoAuAbcd
C+t4K8Zc2MSCjGcW5j/q30YS+ioz9zpkxoWZHJPvJaMlXNJV+c7Cy2X2A5zWUI0e0B5oNXZpjX7K
v3EOCnzwsqYhBdHtcrtxQw0bjGvRvhZCwUykVX3HYlGCNoLr5M3tHuhTWInTbe+266protBtLoYF
fG7YXdpY7RlvmZPOOi9r1wAIkChXzJe/gkYyrIb/GHsUTRx503IEDHCezplAqJFV9UK4d7VuCIEi
VKQQAiBNx8RBi7urXBoOAN7GUGMtpHImrbAgJHsF6ZVdDUA55QDLHNuU0hRt9rXubDGKCBHvInmi
LlaXDyE7iKeKjtKS/Xr5DVoKBvSA6vbsHv4d+urrDxbDEwTC29scTLkp2yvX2Fjmz6x+8mZnYaqG
qi7ijaZf+i1B3YOu+knQNfX4c7NUugyTpLdkmx9aEraTW4Pw6yJ49R00NYjOTq2BLo0RHH5M/6nN
5Zj3wpZL7LTia3d3uGLo3tLVfLt+mFPjCPAYPoNXI/wkO8lllfO+S94aKcDQNHybk47vuQbFW1VD
05UhrWkLBXptbMSPXAifXB8XShCF8OEIk4wAb4RIXeiXnfcayzNnvbMc4uspnbQFrw5Jm29TV4SC
bqGO3LHYjS4aealVYPdgR7FqCjE6CvnxHHh92SHAPL2ILUDkCjoGSL1IFzw0Pt3NmCRM73MNaPYz
QcdAWEyCc1va5OFHLgCODjjmonsfJsGgBgrPk/8IYFG3V5pLcatlZffMA7C0gScZn7hPbU0jEldD
Bdqv7dYUEFev/vlein/pyT5CKJxmSby7hkZOPMPKly6B7j47x2FMED2c+7gsaiACkHBW/P243y2y
IhtM5MWYoszwZ6oh40nwytexKKIRUeCoDK6F67ZOEHPrRAcjgI6JXhxoO0b9yBj8734lB+RNcoXV
4L4ViNaQ2UyioFEQO9km+DON975hx5KP8gz2MY/1yXYfRPbq7g1EXN2RJRKZHPSAYSq5alevL6/O
N3LXcr3rP6qD8Okb4G8ZDdaV+e55GlUSSMNzVX/i/bXlg9E2Jib9T5p/fruUZm1i1VDc5Dqh/Ded
hc3w9FBfnc3pCEGVEB3zUPkX/s0eSctqdz09gG7ZzEyuQ0Z9vX3ty85wt3+SUZQR+8dt+QvP14nP
9wCDhh/P28UCwz4Vi1VZ37KuLFPygRt/Pff9Qr0HUBWcUi+KfBYs8zah4EyqbNRspJW7W+wtkOFh
uGjuLMjAqvpUnJurn3++Gw2l5udSmBIcmaA/7dmJvbO+YY+oIy7s6ss31WCH9mo7Q9974Ad2E0bB
X+DDh+o/wN0Pamtzgo2l54x3RSlejIF/j/PCk+3udIpo7SCnQtqacLjzqSm0gZgfcJC8uzVzuAf8
PMk0JYaTMmRALIc7ZT2OLVtaHO36vt0279JB0hkpIhp9VvpuCt9sZp8tRiR49kFhh36otjF7L6n+
dzpXS7V/4Pp3ZdsHJXdcVuQUB57oZTbEDSZ00U5pFi5iBpx/Yg/iUr1SI6JG/iCjfVq1p5CVXo6U
31pcn7YbO2bCM13s1k6RF3WEdFb7yEGIX7I6p852cEIQLHKPuRlS/uVLMLCYM1N8CaWVoM8r1No6
0cz4Usvdpbw+Bp/Eg5KN8GLAUrUST8oxsNX6wMAog8sBw+EAaLdjY9+tz5gI4L6nfY2FMdpT8IUM
05JerWIA36LP7fORk7gLtgZtV2c2AvHl/IneDdfTotV/DoZgU7uTRzpnfRRjkxbFsMcQ195OCZZ5
MRLQtzvaf+3YeACByZ2zetv+fZj4WtK2JmmBBf3I2z7oNMz0Z6ebdMwYhaK2b/AOSAKXRfkyaUGs
th3V0HQDIpuEDsH9k3Hhxc6ny3TvBDawkXfvHyGncB1IKilDteskIau2UdjhrDK01kswQgGCb5PF
4wHjbUULZM7Cub0/OLZw001/78xkC1VN1ajpM496RkJ4Bwl81YSDMxdJizXtp08XVSOCN5H9Nvt4
dMyvcQwXt33mLnbKf6BHIDu9saSDOeqKwVm25V3pTk7IzaSDjTtl+4qh1IaBaggiwz2G2uwGmMtG
FY5dAakhGyKcEfsT7uHZyIlrJKDitKJ5JZyY+4G2+bvtfm0g/lWss1dliSYhSsErAlMy6s1PTvTC
wWixO8FTWaVpWO4szm3jWPhMIZX6xW0o17IvmW7gZikDD7KtSFkRnsevpMQj8ibQdXL0siQFNJhi
DWghtAa8OLsLzyR8ivokCYWcFYXynekiUaOAmp7RAgV3qtaNok2Kxw4uv7EOCwE9FsJb0F/VdmGP
5Ra4XGweahgES2FZQcHTb6OoaZayfAn2A3ubhWVRGol4ItM3SvoSn16QbZVktiPFxN17Ak4ORZVk
LgtI+bOGdde+fEt0vps6xIGtLID758AWTqGrAmFtN5eb4BHFXZlprZ7pwUww436KYyjjHdpCwto+
2PLeXapt+Fn4mqA7wUSpCnegubmafhM10Wa2vvAC4Dai+nV9CpkAhdZV2tIaUyRUV69ZHUYY7t6b
M4jQ6mDCZwQrRumONuNagX8f8tGV2/dbqEz4KiW5/u5aWoioQzM2iRV0fLDcRrQxir3j4sUm6BVQ
ZRoe1xUQuA7Tk7XQ3EGKxsTTNIKABcuLLkmJAA4enhPRW6dx1wu1dBmTxPHHpD07nogdlCocNI6m
/Kl/3HZXskElU8Fq9iAEETpUNLbhVlddPzGlcDO7RWfNAu21yTvB/CGsJC0Sq5CZk9x85PWJoEE3
rsPyfD4T7/dR0/Yq64LJMwX3ps5GmcOeZ2HSfRRdahp6BcB4qeSozx+lg3DHVpOv5ObFDBMEY0iE
VbgMPUJsX8327bpDaDdvim54l0ZaeimSZEBfd3gIiTI3gIpaWSXbYzwtTohx5iQ5TAr87p3yqBcg
pd5wSCHlKoja9nkJM1qVl4k6LfYReCMO4PZdZnryQxoQIcN1o2U7W7Ew4aCYw8ryUghtS+VeI/Z2
OmrXV+m+7Ljwq1PcRWPZaMGnu+GNcU7biUEhInVeubmqDAS4z6rYEZkkYpyK4BZ9JS0SBLhhWbHZ
L+vP7BKH6rwl2usApR5h9nFBU/4fmBikH0k7I7FUEjh5Wt8cs9KWEUqCpw6StT5YMYjPoG6qptdZ
n36bhnYFwWE8p0FcnGVfUg/VZXMEMpQNiV4vswr/P1uRZNDrKLbaG17oIyelb9OiQZMF/7I0xkGw
6PdcE2jm/YX2BPKZ3RJuR6Okac8tI7brV9wq/RDq9DJEg8AbfAW9S3pRUuwYCOSYYlCD954xu2cJ
6uXslS+yJT5boVO+LTVL+UPgcdD/Otg811Eq34R3I5Y0X3BQOwLgk7TrwJ7UvnDuhg3KzZ4v5suC
n6ySnfe3cwLlI5JS+dCogxxTbmEpmr3bGkK5ZV0ww7izKs/BpYDnGTtY6m9rLXSy/CtYzPHCWifP
OEw0n3zNzK9ZNiviqLf4nqx5TowhCYztDH2NZcwrsXICsWJFUVLevI9cxovP7toRoFlhQhNdPwXK
yTmcoKD02SDwEeNSVVInpaCFqENVp0Hd+iv1SDF8tc2iH7BsvRRhbB01Y9FhzJlmdSU3X3rFD9qU
GLv5w+TRgbooKLIlWR/Ttx1GkPt9j3qWmFy7HelCtlwN774TEZ/6VXO/69jWJxRDIZpewScrGHEG
Gz17P+ofWOs1jlsKOL3mkb3vsWjopJpucCj4DX8Ztxcn/5goryjNBSGLHYMU1j0LJj9j/1tY8p/V
W1gzbTvj99W6TbskwoYCV3qrGd5TgRIRkKUj8fHcUpgEXapnWg5GZHxK+pHvhREHXlc8fiJqAM0h
rZkwBAAH9qdY68bAUGGvhXOOk6RSg6RZ5MgGKcObwKyMjGHLBQwyrQtXp6NrImO27jW1+ciZeDRW
Kcp7ALygV6FClqD5SuZO9hKA+KaDvx3AJ3RxPX0y34s2gbixbAffnJyDmEhGW2l1RreyVBWN0xHx
ELYAWZxiXau7elfqRP+UzArUg5V6BBGTcBfqwfaIZT4k+PINAfoMrU42m4h8qJ+ge87Z2Qgt2FZN
LEDNHp3Q6yuzcU/EufxAODY2fWSTIwzWWr5oMKPWrNg9vy39WsDNcL7Hq+gUJ2BkU3/N1rMLkmf8
bd1CudKq3aQaAyISRZHWI50wjxq2V3V0WAj0SsjJzbTrjhD8u6aPDzVzkinlEdlhprTQnwbVjadd
Lf43Au73gJro8FVJqLxfmAzC7bt5o/ib8n2929uzOe09bBv7zCKgKiV7+lywGplKyc3odtSnvF/s
18ZmxFPqXcjMn5ZpJKQW53yhrrUvfCOEXUZiRGCnIXg4CgnkNY40PTdT1QRrClhlJ5fp5BJbbLPq
KD7luLiwXO/M2Fkhjht7CNjq7MdjDPzvivQvOSWvlvfIWBB0njveVfxSGyxVYplqq22sJxDG2Vd5
wpz2ODuETmHgcLAeWL23nYnDqJIjQzIPKGjlHEmt9ma0eKJ7Mtfzg8g8av47rRGFw75ezZUwzvcD
ekwuFcgDEorslvTjUkxEtlhKuBTGROUpxixz4aIM+b8uN4Axombu2fTJViDUNbqxfQiM8uJR6Otb
vremKWSqjRJV9hEHOhkP/uHpJXMdcWAPzrNK9Fd1+Q9Sr5m8FoxlYkSr0fF+bOOf+GQB8+WFDj6q
SO1kUWBZHPfP2opLT2YstEeL5EBZXWU+w6Shj0/nsEyvpoaf8Jni/6KE4Q1XjineRPkB1I2aTYTa
HANiV4rZ+4nr7cNpODUWarAGMOhDeBO43wZENidBeXnPAQZ87XtkUy4vzOkR5rVZGNeYBJHtt4R1
BKCteIayGzrUo/mwW1tOzl/1JSqeitHRtTZW/5ebuQFQyMRBLqUbXm0Iht10FWMVmtBtfnWH+Y77
783V6kh5+eSnpkY9LQDtkzYnm9DTGegBX188yJ2ZLHssCga1yROcg06FzS1KB+rSskNV8jOE4XjQ
GffeRa2vYp3EGtHIUPsd7SVUbD30zrON3pdV9hPMJ+z5ScQ/dS/fDYRwQc+sDZMbzibX2u/qv3e3
9xqASfch0yiMNcKoaMyZWy3+ipGMQVj/+ZoT3sY2Qdt22FTuBcsqfc8bHeeqgaQCsyYyvnoxFuos
lM1IONxqDY1q4BZoBXM+WLWugNx5w2CRx5S1o7QSLxiglNh7wYClvz74Xd6UE+7OqFtY+F4Dozpc
XuDstqZRekTKUqDaDs72IgjZriTrNgYiMd6FfFxhl+VHYCZMug1BPgi+ngUvrFdsOmHqRGWOiqcg
zzmHd0hy0L2LfVaOzmn0vzqEF6ew6d4Ov38jC8PLecPVG5lmTUjOEh/enj9MZPDXIesn9Jyy80JA
ilAmYeQvxgeVOD+JdogKsAQHlXFFXiKmFY9XVPBse1dFFx7ccD8Gk+2qVGMDLFAqwwErjqEPUhFw
fIukUh2xIkq7s/Rav8jQLrL68TVMz6/CDASFPqIdyCQC9LY2zNQmr6P014cf2JCOHjUuT4YMcR8k
Fv2rHe4rJILjaxi5eRZm0MTWUxegCcLU527nF4m5on4gAix7mH7gPvVh1JakVjbPD4YGS2B5mNwi
bdVcg3jT6CZHlTog5wLPSxTRmkuf7Bt0iVCJwAq179AOoRlu2U7tg2nwWmvtIRAVPlw3tHaDbbji
MwL+S5w3eBKlQ5HzRg78BU63cZMU6Jd/8EsTIW1m07vaYVJ9Wf/MzZUudqtXZhWqeXsvg6StYKtI
RqkyUs4g/0BD5IVxQOnZ3oVl3aZO4OWOE3fkD/kjgJxk3bk7pDTHKWgepDc/oyd4rcb+lUx+9kWD
ApKHo2TToAt3sb1GEj9V8okqsE9vfDZ4d9bVCVHbCj6sXbn363PTGYE4Q6knoQWReRzrkiRtR19U
HShm/ywNwR1QcoPAOwENFaKK6rMspjJls5Ogdam+YLcPZ24QeLui5iP9x1EGk2SnFON2vPr4mfjt
0vo7anEPvLHHhySsixA54XyUBv74L8vo1pyxbl2qqzzMzECGLmsrs0kp1Mc1cbJbYLimSfasSd45
zzvdsRG35FrBo4UCZ3EjKL8sFjxN1Pxzffsw9Ce+U6c2AiO0Gt95lDwR47o75n3KuRe8p+N0Vr+c
xgs9eaMLqe+EOqnvnhCam4Bc4/AnYisIBiTXP3zUCVLDxMafjjfC6Tnynfi+NHhXfrtx+UgsHtEi
R0V9MHpENAHqdPIFyRA8BwiGqKk8CXIPh+05g+PH+p2UgiRC2Uvao8ZQFhxTaBGr0egxKX9RKC3n
R8jPms0nS1YnA3Cnz19rZn6RilCRRh0hwVlyy3NG8NPXNIOYQjwvJiX5V5l/cwzB5O++02vJtWyZ
doMt26XgJccWVMKY62d/B6JRWO4tTk4WqWASxcJ8gFCtathLuSsBehVQbea9zzzbn0fVPU3PcK9q
UxQhNJvKXJuM2XbuHCJwpOpL826kQ1OOcvfh39d2a6jEsskLErVHN2+k0KxOLJF+rcYGSEaNTFPC
ACo0rTDk8TaTNBa4E5RRGJsrRa8dOpIeUDch0tuFCn8WFBNzyVm6AxQ33btu1WYThR720hKg2PjF
vnQLw2HTn+oad9nK6g1EtGeC76CuU3+3rBa1U3JhWcHB4t93qtWMV/+UZOo98kt63eTKfs9UNfaU
noeOf8AfAgUzd43QgEhm5dMCBCIN9z6K4ynxLrE/bJQAkEE6xN6cy2d91A5Dltcvtuh7XLnxZ2VJ
LvQfctAHT7iKaTNjgL1UTmfIkH5OFtP/DJzZ8rEwEAOP4758K2JdJry4AW/d4jwmCrh+dVDAa0/I
lMjTF4xEMSAFppWiloSRNDu1rHFd5H/j9hAZ56JCNH0bwxKPsQ5mGwa2bAnWRgu78Ax5BUHWjF4w
P+Jenus9YgyOUJclS904N9lMXJKmC2BQBBs/CIqqy2kI3a8XbkcmqFzNTW21E8RoAnAxkxSwC86t
YrFA/mD3VuXqhH5CIySgn/XBoZAI5zSTNFq123eF7EaY5iQnd5k2/Nad2XeTCUxkbh0KTJqipUK7
EZmOOcGQIw5SuPxruqFd3ZPNQJRIWTvUwbAVMmMI+un4Bdj6zEy3dh/0t6GcS+KQZOYsodt9hg3G
Yr/atzhdtZ0LED/jNhat+SeDjsrP5XVaiWXFsCR9VxADqKNcJmGeFDevqsbbH8vLncIgm2jiRM9/
gi7SJB+DEwaAJx2AOGzI4Ls8yvrTTOidUvgiYE4xgjdCtDQzlDVmhYm0jZPkoebrOPnMy8MysPbP
Cc0OW8bQ13qHCMm/Tt1V4pzMcTP2o8/E+zzZmskKn9Tfotd1PPD8flv3FvLXgK8GIIund7N5th3J
9fPTc3csA63STPSpijaRdt97GKxB1kcPR+ICTCtaHIAUJ6mO9l5ZPw0UY18jmAIxEEV8LFAAuVFn
E6LXqca/rw+KETjHL63fqDg5FlQ8PKmg22uMzyoEFUv19pBlAzNRMAslIj7GDFEhEawSjhtzBDn+
4ZVquGq6k5lpr3v7FQybNBV3I4H7mb9IiXsri6fUHr9Nal5vFAHjc3M/bfAB+sEeLymTjUzcbPJ1
ky0YuXdE3J0iKB1Y1A+dxqFO1NuyN3JxL3s25T1rm/xwypym0qigE2K/gN3bLdN734zjNMXjwivk
XAhR66Ufzy0+44zHd8Ms7v6pJ7kt+ORjpRZSf1kaFPvHg6FIwQFQ5eCV42uk//K7VzC6BInGyM2S
5s6IzZgvWBByAL/CtFkzBOlXJc8YPqf7dHfXWxXXCgR4a7Bd/cqGcWU5V9Gmjcnc9UnbqQMy7TUK
qn21+76uLsF4qeGDLc8HeBDz8MKK+OQGI4lCTUIpF9ccRYhZyeneS7k1JMiWVcLYmXzDj/NkeyNR
t96UDLv+oGkcepy4C/CaOkO2dj6kU7R6q20bGa7o4hQECvGiWfqtm8xXM2pg2g8bAa33N0ACR/Wc
mWEAHbwbgM9gXIUM+YBT//TPiBO8d2maN98MrNIt7kZq0RxeMxbkrNbyUwOEmr4op/fP92UmMewC
YrphvEFVZvqiYiuIkGo1eBg1CYSg+dI0wtOluPEN3NrxvVNIwtfBvyWJAg3b2M5hIhaw2HkR/40e
Ed93PKkt1s8hdIeDhsIsY74eg/Wdd34CTPvwuk+lvNT4nWZ4v6qrnsFmJnBpN2kUswbVcBAX12bb
rc9vv5fsZ9G1Z622PIw/+dAA0QUo3P9gjpmAvJAQvDeyktcfsGGD9ASmqgXDUHjDdBjFuSnq1i0s
N7EHgVagsInRDgIqaZUNK0nTBknqeaxCri3zCJpI8h1t0IkJfjr7rk7pJGz0+5dBjYEV9z//Jino
Iop1lG6IlBXAVOdcR+j1hSJQGQp5UgVWyLrqkHFSRZ3ODElBRu7CFYhvb/hp6oph2/UOieuSHtlK
HgjtlwW00p56Ij+ARNl3P39YFK/7/B1x71tVfqH/Regs6ZnJNIc30gaAfr3SN0D9cSw3ckSwz38L
C1MwafSZMgqcT2xb50sOeHokxUYZL7Uv6GXlKK4tUnY5gsNIFmh+g6Ypxfhw5eIzwv5TfWLrg7Nd
gokvtc/COMM6JGseXV3vp86xWxJ/FyFQAYq4UYtu5mxGHPeRrCP0GDUUFBLRdqFgITLaGtxtiN5l
Q8zJQsQhNgrpFvnUEyUU9uasFkAvsKv8apzh1yt//7vDKtlhisRDcTZM70v7nTzffChZGa0V5M1+
T+6hXzItHh/zlwnUPIFbol71LO8X1obvjIDuGI3M/9gPbIF38+p7Zfiprs2xgPrDfr3JcDKalcre
yWyDgwBw3UKH91qkl9V8wLKFrX2pPeFiS50vkP3cYYMhCPnzlxDefAR0iyVvTgnjG9MofFHH8YQO
KzuIdwlYfyBBkrXM56R3skwApZ2Aipsi+xQDkzLpkO5+MuM0q0XTLxSMTw42rSqckj0a+LE6Ph+L
oq7ZgsmV2SXHlVHw2rUjOUmautIMlItCIP98KEhua01ToBAkn3qJv0TQ5qydmz9g7uvRz2nxQvam
QBRHUfBToai6/IP8NN65k8uNpt+K5PcjHRa6Na9ffce0hKMelozkrsTLf2iXbKqxY8S2MdUYazkw
vw0i3aqfddARJLTPY8R0jAXEEC3A1hQ6wPAMybYSBiIK6vmdXrtu0ga0pBdYruwEnBIgzZYmH3xf
swzNorbbbiOOC0wa7HeQTRk+HAHILXDV24yK5kwj8C4vuAATZF9bRyFCjl/RepYeBlGdVMbqRXvl
N08UhKwf4Kb/v1OzQWCJZyuDJUoe/r69nRHyl42ykB+/oOrxlsb0cIMS5OPK+2uPZsTlZPo9AWHd
nQC8IyEXhPtt4FQlMyfD9Ipd0atEanE+Awa+csOVVdx1Uqku9Xflhv18xQEBt43XLz7XpFLa49SF
asBuw+WFN6+c2HOT7kOH3Lpjo0P6rmezao/SZqnmKhDpdLqWT5jEcQAFtSNpnHCjvOLGr3ExtUyp
NAaB2la2vELh1/epdMiWGcRY6gGcrQsfMl3qc52/IX25J31C/sq0EaqN9HpcMSnP3BMkY2/oJh3m
x+JtNU9TtuJZirNf2+qbzdq0JUcoawPAeATX73iPeRBDB91Z4YAkTdDrEUDmyK/xj+d0Vrgxrg/8
i10QWXzPMVZ0V9yFxicQeGmq7IGUz+y/WorYNk2WTuxrV9WTp9qhYvHtqU/KuLLFGfostXAZpPoQ
yfr21Ap2tA/mTpTwyfINM+AAek+xoOjdirxRmFmkty0QWqUg6T7K/cwASgi5+y3r0PZyVLHE/Jkw
wxXZHRrpw7cP7wT/iS4qV9+Mbxe51t6kGYu5+kic1/GF9TjYvc1Jxh2+f7Dz647dmbEN6R552ZM4
KbT0AQX7FrN6pB/xxLJYXx1RoiNYtK6ZjbogAOv3rWuMiCPzf3LG5pXmFmu6NwSy2OPKWNlAu+Un
0deEWdtAcnT+TxlS5N54xxghZN8/nT7O2bTSlLrgS3mcNadp80VDBwLAufpjM2hzZ8wHChZn8jYJ
lnwlzQLmmHHZJXTp55mIBLUEjnCAGTf9t0u5bSYRrpOQII6gObMt79YzGVMRiHChQpRwjUWMhZbv
ATlHZh4qfgsqgzPBlKMJ6LW2LDGECaiymdK3wY5Tzu8NVL6drtWp3DlKuUnsF+1/ibiThk2Yh/ND
fQtVZbwVf9zmW3clx/BzJYmyhZngAz3pB6EBQQQx7Ke1peXSRjOdFDE72SX9qV8oMvhpkUn5ZRK8
918l9n5LxTRZrqlHxwvaSg+fz+BmkwPjByl8Dou+u2+oE4LhYMGiiEUPzG64KQqD6wlmw58Em7Dl
1AajF6FVYu6i3SW65FLn07/XhC2HeQm9koP0higuFH53xpkpwOyjL7puMgc3HpF2qj9mNCLwrHAR
pc+vCt2LBjTuvMz37WxLT6QfCxRoyyxSqyYhTpoIdVo2U92qBrj+YnbySD/zce0CMiVfUgUWrhbG
iRN1RNtx73bh40vw6w0wxJepBZvNObMAOL4Ld+GZw2Q9u8reLxTv+OxYTIj+RLcG5TfUvGrlF7tr
Iwsntke8F6rG/kaa9hM0hi5d32ARqQYE0rqFUKOM81bNeJ3upDHPaQDr5nxzrBbToGOTxJyg2qxy
NB4VXGNnjc5IdjYo10V4aUJwKUAuLc1inXm4o+9zpUAtl+xpDaqwiOiAopEF5wZadnwsXTDt2EBL
dsQntmzNjZWf3dOzZI9t7Sj7a0/iKTH46pdU/KMVO0QZIssHih1i9dsO2QxQeMp6FFNqNW6QOhOl
9N1MkNxprVVOk1HinugXTi7u/rx2GKieVGuxFYA+67qERtUvEk/vtg+YRtZhDeoIXI919O79SFWQ
QRA7Nqgb3F0wzYy2TdEr+QIXvVxRdLhImJmUz68dEjZhFmt1m3pOSuCJtJXqeNhOKLAxbz3Zrbb2
Y7npyxdjxxbCsJJJgNQ8KKghLtT++O4B2pXtlWra+yNfwLEVX+SM4mpQCqy69pZxq25MJNSilXbS
b+FY/ZwQXDEVkP10QkbhJZudILN1tObwtAbsG66JQhC2TaSKaUQsPGL9N3J94t+0sUOQIkdZUM3I
+WW9WAJJF74Smq+f5EMy4K/8nqjK0uq4TeoBwpexkQaBFcSvib/CvN+gCm5/Mw4ezjhPs16rSar7
asyjKEPf2hXWyhUU0DSZvFazRWSCwA/utSbDyJBWSJ9PpiISFsRfelk2J4o+adM9yt6VzbbskAp7
6qrlCEDWsYDF1J1Byuo1kq3+Zoim5FB9w2QiK241zPRbZ9YgXwkg4OufHxm5PEi5FekjGEEOVYSM
l99jyyWQyEVnOBENnxZSGxUy5u/+D9SX6SUDf7x1MkRu3t9YnWNMjSq6cVn87MoZQcGvKM7uiPn3
e5dh3Z47vmknmAL/fzPMnfIhKtlv6++WCvwiEMnZHwAn9ChFKYJ5hqWBswBAyM/B4PIapJlxzSve
Hfh9XSC65gy6bVs+aAm/5386UfwsckR7ncC+nM2/5zH1HqxTEySRPse1C0hVkskuwqOXUAKxy7c+
i/HFpWv5gfFdis9mDNv9ksquSWauChybBXoFpFJwYc3uMRV508RMWlI/e2vy6Nogeh3fLjncdbzE
8dDl2IdG9AGS8aiYhL9c8UJbgxjL+9h7PDnMMyHyZftE4NjvR5npqMuyq9qI5C9UFpSleZyp4dcb
u+73cTbGxaMS65bSz0jSeznaRSlwdodPu01d0cYOgSrN1gjwi5oGFzWybcCZiXc0ZuLLhVQ1O3zc
mRoHZMQ77KIbFRaWJoo/Ukucodu0OcyhZa0CxkgyjcrZIn2JJfPjNS1L/rLr/w4IS/+xQD7PE0xJ
gOM3AFDuBnkpJBtIolPJp1iG2JhYYQWb31PQWgHCemNiaK+jk+J4SBl2K1lMScsFWipuBOPfzofm
uefYxWUqf9SYk+6Qej/rrNLh8sxgiv5lOMaPKGypAXaL/KubD8ry2IxiMA60DvqAzBsNR3IoO+/R
TPUjHI7xpWq17GwTlLFLfucOpQxrBPj3yqX8O0cVWDnkBZaQU6o8AewhbFIIEQvq3qYXi9HeolbQ
fSDIsxpeecKKG7xjkN7esfu3lOxzwBkG4ti9yWr98BCzGMpyxtKvmFkjBJf+IwAG22nNJFVShKy7
vuM2bvM/3kXICZrAwQplc3gY2vpamlFPgbiIG6UeJs/x1kJP+xtPC/9W4dJsfFjHrUHTHD0G+D5L
JT9whvlp0PHwK7tyhqEyVkP9MRonYmqqlPzQ3MopMhd2T4BWjoBbtDLebIrIccLmIwu8JChui6Nx
BWwlYD0OidEEacHim0NNdBge1nSY86vfO9cUK8MG017r5lYwA1zDYeXsL2Lby86RCmyrWH196f61
/c5Z+MR9F3rLTejkKBqpokucf7Eq7GyZLg/TLiLttiOLid/KmuovDva2eqc6Bm2ibph5RcsviBFE
R+vC02WIURaTkAelpoWQFQlY72oG3qW7+dED/X99Ps7yqwlF8P0DCR34vnRcldt8N9JocQN4VZg0
ZWR4vq1av/7MsGh9NfmxEQQtGjrnMc/qCu/6SkkXS6x05j85jk/1CtWkE2mQnLDCybdRwis364uX
qWMrBAQheuwflFn7VPtQybdKqyBiGAZjSgM524eZQxHFUj/0M8daIUxi1cYIIajJY492hOia5Bll
B0n+n7vbUPGVwbZOFQdyU2DYkfS/wTlHjV5H26PqppyU4eUFcUdoR48rRqlzMpPtbf99xXHBe6rU
l74wO2StKNO4mL6YT/jnu88F5sfvT+hCxyJ1gElehdfYxJFmpgoi0fbYx4+ksFhzOPikxMs2Fy9a
UL2Y7OKD/ze46cecUM7fA9itHJMNqqHiGcmg243P3CGhu8289Aa02T59hgqPPHeP1LHdeRqirp0D
q5KCBXkrbRXkPScc1+jcfoPAvRvorgFlCeilPgZQuWrO0rTiztHoP9KQHDHsG80Ywpumxca4AM2B
EohgvAHf9TTHKX+wTlDd/kFIgGkTngkQIEFqSZ+S6QpWYWEimyWZMf+DRkJQ+kUtp2UfxyGLVeoz
Qrc8vMEDRxvTCQEdoI1I4QBdlYqW6K0XAVrXXakwRjVp8KbljR2ys+rFCWJ8nsYUlarNM/6Don5s
dDSYbFzPFrccNTVD6peJOLcdFcnxBow16vN9/kjRU8e48MehGAohNmCtjOov0m3bK4fOxTvDAvEx
/1dHm+TfCdYXD1gMrIhACshocUXibCQ3OrJsPcCPjFG4CyAGLjnG9jAvzy6quqosA+oiwRospm6x
DIEGAXoOLdZimHFXgfIfTXXf5SZ3XQjS9P34Drwd8HGjri1whWIJ6oyfJLOO1wUFEUlZFpRdE6/U
OinWYwb6BWwpSHdcO1tt/gdJrP7gM9gOSVy2ACReZiElzqf+CkofHAmnZMIkAlUPzmoN4820IXgk
7K2a47fQCYqpZZR1IhysjIV40sE3J1W62kxCDMLLAkTdhvLKA+LL1/Y6sSfau8vCm4ACbCVeBVwH
QthfcS8pxtgao1Ab3fy4jbN+6U2T/HdTY98EC8LHaCq4GXWGsE+Ve3AtzuIo9junCAuyqEkqFcZ0
Seyr3naIzP6L6GX+KMQFWrHXX8lfXSFQDpx/Pl2ECxm9sFcTlQgnHZkKJQyws790bfW6O0RyujKv
9THjWoAQ57Y58CjKRrGf+KGo75mQQhbl3JT5C9ZxNbbaUYGYWQgOaUDsdwpHvNrv4+3HBo7gnrfa
Kpt1Zrgm9KO9zG8fOxoYqcTEILDY0sqtrsTCzOOBTJy+AgMBOlwioWxG4xjuLodbUyWDCLCAogMX
NzBgoFfHgnTEQ2d5XuAewoV44uuTwjdG1qY4BmZhvq+MfF34MafLfqjuGgn8bBhFhkUMl6BUNfeu
mv7Uz6yrd+bKELMO6cZ3DY4LBxE6YWtMX8at8HbW9lu+T8589RS0S0UyvAkVU/E6y/ix6oc3iAoU
WcAq39yQdR7lFXnAVpIKvBHoqeEjmeK4nHrPT8cZb100yq2RykxHm4kHQEqNcLIdFMlqTyUwaFqk
/km4tnFEf9+da+KRDFguy1i/tyI5fv5aA5SEwv3j2JrN+gX4Nqv8zT2dsKbqptmACVD5a/OCzZcx
9pKKFPx7MK2ZHJTxabtcdwmdYpRDgZt6LoNqZUB3wmi7SLtOUOl1YnDmLu9UvruDTz4jZ16NoG7D
qbeJXE99jYZLRQotb+CI7t2Rsa+QI2j8VPhjqGSgsqW7sz/MHseKqwdSXLDeH9CB81wB8BXSZFAQ
9gzzsPS3NokPwyfLJQ/772jKolSxNbUaWoY3ED8m8dAWGQwFOBrVS5xWyu3P3YDGn9ZCMEE3BMvS
6ZY74T7OmJd6t8uLwltuAJmseMbMDNumDFHxCnV0hYP8sWRXyhn3y5r1GFR8E0toIAh24bt9C5mz
r4f0p99GmiSN8HXmdFSiJYx8L4Zyoz+GJzqVRk+vH+44rj76/vk6A/Z0CtYX5BOWuUdO2OtuDkhu
dW0umrA0WmOjLlg7d3XyLXUVimievfpCp+Vfctdly+aHaoGbS59X+32mz4X+K9T3jC9sqRGtIssd
X8S41GEAhYDXVvklnXwDT0rb8HkzrbXvMkFpzoT9IwpR4ptMHji+u6PZ1JQrqGKD9xNc2JcSMpUt
88YXauF5yMIW1svK/v3hB64F5Lu1qf5doJ5BYMwl5r8sFWRj9nTEMo7qMzeUpxtgBtUDiyEGA3ue
zDvCggqtHMYNong2fY6gLS/jFfCzf+hk4DS57lZq9BvFE0F15VSQPUssirg9kv2nKPvXcCqINx2g
05bl+L25QY4yy2cM47usZLbSiDPRAwxx9vX/RAyayidWF+fDmTnVl3G7bLpBw0ytXkulqk4aNsGm
0eeulkcF9xIoGfU+BOkES7edqMO2cDpp8L8d+fcj58cxaOxT+c75m8rhq3kLmvRO15mzxwxayQW8
y7pn2sHSoZNtd2DuaP/mLODxCFEa7UEJpf3Zv2jURfWmeclRrbr0kAIXp5Up3WLva9GI5Amx6qqF
ipY/ajxO8e33KGKC7cy2KJJPBC9WrgqwUP8kuBT6XQYE3T36Hz517NtxEym+xTOxnaT5rEFNEWUa
QfP9xYE9udkQRkxROmeRuX2J0U/IAtQs5uOS2ZzmHFuZvoKBtUH9qtIhVueUl54kI9gNtht79AAn
nYZBWIBVTcMl345X0H/f7qUZHKDjl4Y/NHtHiN3sigZMVpVCQWlaQV6c6yJIQ+ZzbJrlBR4iASSN
oFqQNNHyRZ2DRJHjEGA2N893tYB/7qjkM/R17HANTwME55plVb3f2PoXzHmjFPk9BKtXbI/fAkQ5
dloB0o5MqFkXLyweof+2u0twxiRW26mfOlBRXuFfLr6OFQ17m4DoR1SCCEVV/tAC7YSoqvgctUs0
IDe59LgTh/ajcS6+Kk17a5rOglZufcPkksfJarx7QttpBbL4EYiO4KqS/kZMkj9m5gwwv0eJHZ9Z
4fDaUwcSfwpBWSrtZMPfmTYC6/TTisD9tEZGVAfDS7CLJOqlf7VCdCVbFHo+IwDRsvj9QTQOdqFk
SaFkbUiweYVdsi1mgsNPJrLWIWIIlFyqSg8sntEvrkSHjDrKqEhayEQi8rhpTFcoeNg6JAmbyQ8K
Z0wFC3ViZeYHN2GAxdHB86Q1uYi3Q/AdMkxwQW2CUNTentqgdF/ql87+P4bFZTeqFimU/ac5/3l9
p7xdas5Ymw67S1AQuGAPhxNCNyBnv9caCv93coIrGKs5afqLso9+SPmvlWsonkBtJBt+qBb3NJ9z
8O5QwI64vmkOkw5/r2z855arBq/gE8xb/Nuv9vNjS3AZAv7dJw/EBUII7KIW52Ot9WV776RadFPH
PM0kXZ85PbR+ZPWC7nE8SmWCflUUQvbPBTFXb81HxkWYHixMhCquZ0jb0pSPqWAeRqVw2+MXIXAf
/yoIP2yKMP1RWmgLj/QFc8BXqzeROB/RWziVHJVf+EtduXHb8n6uclUG0aJ5WQV51qpQKHAALzFz
6XkcQt958yQ3YpVM36YHd7iiO6hbCYhDCRBv7dPzOKz7wKxoCOuEs8Rj56xOq0AOxPBGqkZ1q4mB
/uDcu6UL1IVyzp3AzC/TKpUdD1KuehW1b7C7sF9KD9ev1zIHzpB8gswRO+grG9XdC5V2YsK4nGr9
gp2uNZbzxF9h7MKbWKwzKZ5HPROeutbu9wSt/yPx+ZV0/SH03xk0Xx7emoSnN5LjBut0RG+bv6je
/XSzjFCrLicx/7L89orXxe+EcU+fmHl4kU6rqWRJ8OIHNyoDOOIK+7ifsS97gGjKHYFrSndPfPuF
bLX03sLpFQ2k+41HCVMeO9qg/SvMw2+yByAGMHt4WbTHGP0fZ5x4whd46ooBL6zXVSgl640yBWOs
PYl9GXKARQemvzICI7tL0jxpAjHsffbcK7K3taEfOg/cpAxKwsmxXsRIdJYKnSz3Rj0m3+AjlfEt
4XOjJVQ9x989w0z/X3RCMH/EFRLxxsHfnMMq1l4EnCDdaJLiSVQfkm2rlLtFU+hk7Xfkd8mnhwkg
t5+cTSLvSwiBDxOAbD3G/XEeSC/8mtKoLRGZASnJUROXnuGC3S7wYOPUY8ndNm2IXk7NxfSFgMSu
IZfHgg1zOqEa7J9oaDeIHbeP2KqMuOKIBr51430spkcun4MhAO/uJKZCUwxTvWbCxJM/LPSyhFDu
punfcFbTqjAxengvYB3JXUKGBkCaPJTA05lOaGPD/nibbJKf8GL26EeF/0g4Moq4iJhSNEPCyAtq
d/G4rG1njBSGIt3YIK9Aso9XMsueQkJWaYrbuAte8LJO+D7Tr0OOuQU142E2Tjox6evbvJ7xwibX
JVC/hIx1kvK8X6c11aiHKaPx2QWVYbHNGZNoHosuCO6AklILmgldtJzg4omfIyWIVpRweb8K817u
AcjIQHsc4IiTRvQur/HG+AFLap3FHyzuEGf7QCNGl8jwMjbepZl25uoijefW0/7trVzZpVZ3Mnoq
xC+r+40AIhD34DubaPiHSFG5JXUw+Lnm5iaSc1t7yU2aDyiVMxWx3tk3ibHp+MIuMaFFhePOIov0
3Y7tkouss6UO3AgNzlMPcFPoW7kQrUe4wBxZw+naa901ByRRl4OQ/Fuxtf9Jpl8YOH0aNNUiTXj6
LSkFWePGoT3Lx7yKqGDBF6WF8Q/ScaBbFMkA9tplwhwUeTTxnT2yxS/IDH90PSqrGQINH81aEDBb
MA+HmroOhnZsn5SDnO8mzR9w/isvT6gF+SUp5tvx633DnmqZZDJr73V1mXkcJ93+Nc39YsL7/z49
6cnyeRCgV2f6LX5khOpAIFjyBjd1cb/3LXiOIBV8IZIFaXh5LkcF/yl5iJ1nSm+EZzSs8A06GUrh
CegxDmB8SABe7yIMpT6CMibyJhVlEOEuWJb2Xrassju8rmdVAwVH16D3Ga94yuXr3rBleqYmP5OO
D9L9F4uPr5M63lUsWPSFmpPYUTK1WYlP7CIaDWArZQ6U7WCtyPcZ+sz3i/kReus88dhSPoSVhuWZ
0mzcCMa/DcFPbCG1ufFUeuh7Ru9kyK3wj12h5/qJZOpOCueSy9UTjr/tN6U+NcMqifm5cVRwbfMw
fHZsaxJrsilmYkhwRvNa2jun2042lY+mYCSaA0nIr96wroMZgij528btpidSBYBmw5zmqR9Um2OW
DEy1YSHvi6Bq5r00rEdizxLrIvZomxMwhh7oESPwshvL6iZY4NLw1juxpVxoDYuWlBYTG01nxsqT
y1DhhhSPjLp24VqaUb82UpoWlvPdA1VjKeh0ovh1VuDI3PrNdYWY9WSGLB+yn7i/tdklyc+lTzMg
QaniENqloKfxtupAiuKFbQAkSnIfWxYqUvxAZdbmH/QUafmNZizmxV2HnfjDJ/IVwfoyobLlc4XE
rVjI1AkUCg6+zR/UwZFlAzcNKdzt8CV8K3PQ2CJndzlbs5Le4aXtPvCSzCmXTBB4g0kkKZ/NKZZw
iafbxvZyBHJUy0Wdlehe7thv/c0Z0Fx8TJbYtTTWNcFlpFUD/sSebK+Wm5aNbwT2Z3e5vIrzGmlw
8URgCehw3UUuFsebFeMrmS79DRq0krYWMZeyDsG4MPOTDWIT6/IYDovjvJPhofKBgdhImiiWjxkL
gih8F+KAxehrUuXk+T36CyhPyP7fVdiBXw9kCTL6zxyuR6jfLKfi9kipYh0qL2WRLAnpTrke+oml
H1N4RZXEjpRjeCjeAm6LtHnAnkwAGj8QGZXDxNFQFCXFeY2mijt4IQ1oTg5oQy9CRbHwDmLwb3Uj
3nO5syIWA/8VYo5Zig8Z5GrshdBivcs5lrVTFMDo8yoHh5F5TzgjiKpV/8qxywsXT8r54KuvuJIa
Vg8zWjadB2D7yClfdnDl546FnI1nUqlNdRha3M6dPZc6rLaA9hVFbUmj7LfLS5aELsxL6GQ8vqev
NT0Sytz59h0Uee8BIfP40+XC/wkGO+bCyoP5E/VW1fiw9D6jzMQGdXnF/OSNst6gad0pe5+gdqbU
2PP5FRBEm+97hem/DTXmguPVOIOzg2BBBg7rajt7HXlIwqxzKBnnlmCHJEoM+AasckFNrsqjSeVs
hmScyWg66itv82Z9MpcIMwWIbQnp4Ff/i3pkx1dVCCBAkaWT5ugpv9+tEVP+xVG7NbtSWsPAh8Tj
uWV/UGYgS4mNEgJEWATLCXFujAOG5x9y2K4Yk1hcZxjamMl7wxIFXwlOC2+FIup8/ur1oevlwg5s
u1EQ1GjHaRdUjchS+irzk7IwdnG/OFX++73rydG78E82M3HmrNig44K1SUB9P/lkf7jEnwrIeyOq
tKY9NazpyiIHgjYMR4qKpIV+Z+p3Y6Z4CslT8x1uLHPZJFTbScYw8C+kFnC7brHEh+sfEJiCxRns
72T4RgRuc+KEMV2s1kJB+8YaRIpJ5ZmnAEZY97KLGEVr9LeNl2szT9JxppwOWGawhVzGZ+jGI9EA
Ubr6V3Len3lr84ZRrZdD4FdR4SIG/kNyFqvaVwJQXKfShNm2WU60ZbgBJD1CXePywlKzJQqRTkBQ
Ui8g+4DRutlXuIXsAfV7Rej3jqZxm2CiGim41llqRsANLd1IQsmVdSLxx7SxVatNp3jNUYZ0Ojhc
nmjFs0NUdh8s43uZ+SGGi6VSXHkqrYXGw302K4aIfRtirKGShZQ9TpFa2B2rAHWaunCpGJ2bq3gV
SUPICRkq34nK4UUKWiwNxavM1LHI1MHzsV61x0oGkAs5vQO0Bykpww+X1B0Mc8Z8JqiMIL/3AGC8
MVIIztlUPmobrgW0j9S4bdyOpC4JtlUHCevXeK3q7jDHKEinR2dkeShqtR1SzoJyHAg8YTaeVM6J
Vt0SgphGNe5USzuo7KTPswbxnM4qqrLBj0pXtK6SGKIbkP50VtPeEM1O3L4h+kgLAzujoRSlvUas
+NnLTxVig2LzFtx0oqf01NHjKhoikfaqJ3ksTsI2oCGVbrmyskpVEiBcGoZh/lEN1eQlBxAJxNn2
J9bo045Yoph2FRy6a8oa5QuT45ns4CRZsxwOHlPw/4O+qZjRSN3Jx/V6B41t5q/y+vJoaHKkgqlr
Hej7SXUwitRaOTxi0NLj4Rdw2sBfsTNv653v0dd9hYY4VugGgEqorJUZ+qzzzFia5Z8GgOLTrnBF
rAzQe8TnnI0kj64Mpdrw0SIa8HzDu7u9Gvgo908FD3Gp8y64Zh/rKz9JclzucvlR3DzlHTRx3zcv
/I81tc7C18V1Sb3MMZOKB658dCC8cW5zfeTbDVrMwGT/OIZ2Eu7u7zKYJm+j3+C+smNiasGh+lpG
2OEFnyaMnenqZ73CG9n4VbZTYbLU8qaZ1p8H2zapOpuhkHcTwePRR3We8VhtAxArDn1XOwyFVWGc
SOnrMZHEU7ktjoFUdwdvkCC8wjaK93mhL5+ze+f8KiSIdCpvEfh833tGoA5uorAcFlvklKiuzh9U
i2Dgya72do/V0bvjD5ohAd4DbSVfL0ArlHB+BhPiurBjeAUfnSUIGMkUB0zK38yuSvbVsmCaZGuV
Bepm8/CTnddF6r9aspzUbo56cRxcKgfw/i9srhw7wK+fK5rMwqirQ3njplF8U8q2KKxd2Pa44cOv
eAF0UMU+uEUuxS54zSD9euCiwkLN2pqDvA5KdQFILIBhv8cmYOQB1ojgx32XQsFtYxlqOVyYj/1z
rzHF4hvBv25ZR6UaOYtOHy8ypOfDTf70dd0S5YGDS/kDjNX8rdnt9KLuj9bFSWerQCMfXIpepTbk
CzZjd7BtSIg59VHKX2o1U9AgqkKp2j7WXiSw+NSQ/n07rMhnJMPZZ1lWhd+q3U24BjSLYR5ptqMc
NQ/SfQg5/S3XKb0onVH9vGrjTIeWdq062bcfGERFpITe+MbbC2A9ykECOavoEbUNQpjzMtLwrQ5x
bFzuOXmdiA7Pn1CUf3UDuc4XOf2sCQrd+egS4FyQIINQmRNKTOpD+S8oqmNoz/majeeOZnvuAECO
l4nB8n6mWu/bBDR1Qs9ioRilJWwkQPTOdBobxXGlCHPaUe4/jclXWzeZ1xErtn5N4reNEd45BES1
f1WoleQb3gvWZmaZF5T8hpVyIDGloeqlR+fi7wg5yF6oEO6kbXAg4Tp5CQTGoPKB350AGyBKMUGr
yJNJ6IXdrtfnSedWB6ybpRK5x9aNo3WJVhEveO61HV2ZJzkJrQ7Pf/X4PDX9zOVlRjZZuQ819TVM
aPAoWEOyFAcgwBskSSEsnjsm5NsNdhSAKS1WTjeBlewYqPQRD3URLjPO27ItAA1WcRr8eaJ3NQFl
9UZXiwhAszuIa/8ryUjMtGZepbw2MlqFCOQSUg5JPJF15KGSDsD8lCBWmzo3efeOs5XjlPU62j8f
DVLCZfU2WPUAtumKQkrwmJShOtAWlDEtB21Og+og0pYQlP2nLr7ZLp3SayDBfUikisaKnZt4H5zx
rsMWn32x4Ro2CzAOXu34s4NhH+SG0Or4yg+NitC+ybmLvA4tX8MxGacHtEGxcAZ9t31canyqoggW
MIFuTlNxQTStRsLMhV0nTOC7Wa1yKGiL0Wjyy8PmBT33sBGGGv5jZ3fUWeJv4V03eFtkL297Fvi7
WVEI+1tiKR3XuyxVOHyYBnAGfxaeAH+W08xutp31GQYNY3YdBh/sBpCG3w73ereU0+/pprccOLt+
RTWI0S7olIEfWk9Gq1QbvPFeDk4OayZ8ad51p+ijw72L5zryDtppvL4orwFhOOPDGxM3tDYsbqf3
XmIMX5yJ2TNCEEpCkuvQSxtukfAbTdrCz8O+g5MJCFwXH0qFrjvsZyCB0/w1Y07PjNmcrEFpcpi7
hsl3KlYCQe0MbIZgv13Dl52aW9w+XLYV8zVpItMgrCMXbx0ZtAlZEEENrIyU5nB+SbI+xbFDPOtb
+YPRJyuXE+DFqt6xD/c+k9toyQKOclIKLMCtbsV/VAf5GvKYfaHK0idiHohVBD1ct7y4G3eq6b2x
D/L64meGKgkUqiClOzTbKTJWhp66yYLSU6jNKMVoTQTsM6dvRbnKxwi1VocMB76kbJ5XG7ttps11
zI34mj0xvWcfWMQFJ2BAtCRAyDjrF9t6GRVY8yL2m3Z5HQ7rvdLB4LxCfvZ9rrbiJmMzewRduA1V
3tN7jIB8B6ZUz7QHw+tSazWGFRYWp2JuThWDTrM6pSOO6ANJpGnFeMi7t5dlMQNhKjBFiZBtk4/f
iK50xP2sDJ8ArSVXQKIwoD/oZI8miyuSyvoBSJCi7Pir/2/DewxvjOAYxE3ZdJ0kx90CelV2dW0V
w4wawyc4h9SD6hMAtauLXt0yW7dH5w+VXWxkojPLXHDEAE0retEYniBLH8j7F28+jj9GK9pIRrOv
PZnAyVjKrFg/PEfRjNtAx0GxcpS09aTXV1TnuXhfx0LA1nAafc6paXXH0RKf0yjiuriCc0avUsgv
fCxgVAiOWKZbwndpd+cGbbjFeAo9jrAQGJBtg8YllgPb7pEMPwAP06/vE71QFR5ujNtFE/00blHE
uHZt8b7xVlOIlu5gwUeVhyCB2vpH7tVp7hvk3ewV8tWCE/LdJabzNhhHn3AAuTMV3K8ve90RkPmo
BmXrqJ1Oo4w1HzGtVST+xhJ2FRcWQGs36HoRpRZZ6JB1a5l5Kjo/AK4yjG1TtQs5i8cbq/IT3+Dx
0BvMZKDlBrdtSeSPR7SRzfAOnWlzcyopTphAQbkBi/rKea9kbeE9HmbO87/7QoNdJZp4CmpL8uNN
5QqSSgtDEDq7T4ux/7hfSUCMg6M9RHGDJ5oY5U4B+uCRlnNxTMrBuKZ6FMrs1fRGWhzRhxdMbJNS
kUyaNNgzqrX4nbp8gzjY1i0BDybjW3dBMJIzJRS0/r8aR9+Wex9vPWtKZHYxC/bjPATc8I083puw
vv2wcpScL+OQJ6SeFaBKdrjvR5KmzzSD7iBGvkN3clbR+XqaWcWp28AisecTZLh4xeMTl2J/PE+3
5jS2rrB4jGKllNw8hiuTlAoBJ7UErVkjEDYZ+lUTr66sH3ZJkzk0YuxxVGTcr83m/vnGdhA8NqF/
eRJiJKbQBYocYTGbjG03ENRiJ+Einb+PGa3arevgOtC1oG434RgGZYmAZcdv3JxMu4KbMX1rQEP2
lzs7bdIa2oJMRxFAdI5WRcIXhVZqTwzV9akqrUyeAOluBqgFa9Yj9MT3dcxH1ZvmA6RIs245p8C6
VWfqd18vCMblUHgyOnzTrq4N1CLqiy8AzD6cKA/ybF/mrm27ZCZsiPNGccEpj/PIHYWPIobG89Ua
OYC26ti831rlEIv11L8cVv1D5i/knJWS4yZ3lxAT7VvDfHTqz6mm3CBe2xavM6vPTOPWp22K2CyO
e9YS/7Pg3qIOhAtC4UcXvU1j4KwHHn6TSjti0Sdk4lfn00eO6n7V2D9shH0+laBN4S+QRUBeJHQp
GgNIqgiZg2JSCTKTGfym7+1gVNHS6hEeSZRUF/l79aTzTEi64SrQZsLl10e462O5ZVtWibgQM9v8
tU4k9QWM7V9XcO+MkLrK4hfdJXLyWB14cobe9Wpm6oeqRChchd5AY3Mu3/ObD1Qel+ItqLbqCjV6
keoBSW96347O/t6aY0EnzPIrWFAf8BBcAKMjTkapBaepKX1UWqFasq3o2NiqLCocyZYHCPVVUisD
9/aE4HyEOd3C63qtkuJqMfIGy4po/K9iOGaJkKGYzLOD5kvWrINj5QT2dFtyzbB8HNb4cniAXIAy
vM0FNiM26JYl5Y07FoIW4PIlJ1AmzgsmgO/mZjWZQ1qTCBN5dQx16wR81NQqdhAewNxNFJFqpcje
X51p4jpl0m3EQO/uljAHk5EKGNGGXJh7sK0JIBylSs5VjPmaxrR48CE0EgrxVrBu4H6V7IgE3s1U
jODqnLQS8bFY4FW3NztBiBqTjSs28OPWTGwH1mGVG7SadxWhjRmQK5pSOpImCB2mMAVt1441IFPz
qPysP7PIhts+9OeLUIgcFWLmIh0u4sO+335e8RYeW7Onvq/+UIfyf+nXzGzhzHsC47ZMnTL0L5XS
nyf8XLQnvLxN3zTxEz39jnNvLGFaTyAf2j8DDWPJp+rrJusaFcsoQTVRRzc9feOmLKhkc4uN4kUv
Zams2ftxpqrVpuhVi31OXwqVcShkGoSpQhOO4ASjwBrNxqzs6dZP+FZB6fgZFFGHAerp0u335GBP
8O2hZDLjANLhlFVEt6vKoVAMbwQ4xs/1vjAvR5WREhWFnlcOHn6n00LaZXfozShoN/YP11XvCxOh
Ck3ckCyCxRj8NgN3Zm9wuUpDtDhq0FT15kCxskINo7rkWugL0u3ElTKGHQoFVttwRNDxrMxLrXEV
WrlevMIs8r8+aACKdU3Hjg8hwO22nOZFhkhWH95KRYW/5evcI+8+Zhl6KuXu85/xfYo9WH9RZ/Kt
tgRa7g1uQmbgjbCSpMTiU0LBNk3cqx/OMaHc19hUMtajhCYVgwUZ5W0X+JY0E/pwkMFyunNPzOxB
U2NmVtByWefcp4mtY7n9KvdKVybvOZ1fhE6b8qkOH7fUTBGsc5IDD3AVNOnMya4Al1BOij4Ec8ql
Zt4jj8LXm/RGYAVra30S7dQxpF568nN3kbjeJ9s02OUC3rAgQ4czrKc/ju9pAUO1092bummrUtgn
4yRH2BZH66QCRalb2lEuwWE7FNMYkPc3bk9yb2JsbopcuqMAGjl3q0cgUUdFy0lVgjOw2js3iiyd
PguPX9UygmkaUww1IYTBGXz4RufePJT0b2rgpgtIO4hUIKn/ICBF9l4Oq7cYXbcA0wgn6PurjmXy
092ruo3a2+lTKr8WSWz70SmV64AN4nwxGQ9eZQMoBx6hqIa3Y4h2X2FIwA5ZVJ1NX3RMN+9g2AYB
pvwUHoSxNniWsJNR1ne10ldtId1CV3EkFDsn9On0l/kW/kxCpbnQ5yrueYoIvV4xRD4lz6WJTJZj
FtEB/IftFCTo+SpA44lXwaDp+GdjjTD8vVb185ACtWCdERb7L10na/+8ltOX4AqVie3RjeiWxw3J
dAmFlRkvZvrSxuADQ6jYc0G+Ec+ViL3FaZMPGGQ4mGdgrysKHJELjmK2Ww6iVPWqB8U8fVcdw+EJ
80UwdvstEVnEOkYymT7n8bmYms01MZDvtnoXq/JyIT/FPCTfIHTXyS2ryJCO8v83D+iChIhTP81+
paAerJ8N9MFBihHchQawa4mSZ3XGFi+koMcL3M1ps31CPAEEWHhyw/LXywMwFhCwyr3YQPdgA4it
YHIn4f2fb8krHrivmJzQXp5SYQgfisAhAPNvKlO6YdexvFIVPjJ+jBM5GfGF5Mz/og0KiXuACR7C
YrudeoWSIQTAY+iublVq5fWmWJ4h7tYFfzxMtzge0E37x0iOer0WpccmqYltzUJdcx6oo0f4vy6h
WJeED9sMxZb+cL22NazLLIVqS3Rqy3ZVWNeAWxqOYvidSfsrP0YI7gjmE6gDakc1pc1LskCG/iqZ
51MIuyh9VzCWD44W/cXg4MdWqrfLYvqe9PvbXzsUooiAldH94EwLaTlzOsvAbdTED7hm6pCvkEd3
DP+6MAHD8GHUEI3sDyZi4APeVxloVpQbdDTXTmkT+KW72PQHFOB/X/UCCgMly8umBA/JSLx3oiZO
ytgYy+b6ax5Ws3+2ldV8rFwy6Ey7F1H6SuXOeeUmY/cSmJ+KOVHxufmrG6dp/HqvCO6vDhEaeqp8
QR4RH0pddZFRSM1eq2JtnVrSOuqEXWPH9X6wYrBI+UWMgoHrAKQn2oW0SfqMxGsStPsd7fg5LQe3
bDV4oHxcytLaDda+7kNcunCWIvA4wnP+EdrGgxY6az3aNvkQkuFvhBbLyC19BMBbprBUhErJFez6
n05xgtlQ2T3ss8iaZ3iDTRgt2wkebpxnOCbIWi5eCViJM5r1mb5RlNRWddZMgZdR5IfwMeSwyanf
nnAr52M8qGTFf3rpQJ1S9bUR0nuGpLORm+N2rF38Igi2SQRGrwMRCMJ7vfq5MZ9D0rpG3hHcD84l
p2mbJleB/xZv21hJvNOpPW0jkclaZSytSkItdDuRQ6X2y3UqgY+IXAb5HGrBKLAqEr48ySvFLPde
kZ0twwoizlugK01shXZGb8gUWnO9v5zxpww3RZy7X6Fam7JwWEkQqiJUZtV1OK93Za096p0eyo6f
KYJM6UYqCyLE9hJLHhCBCLChwI4WpLlZYFiMpZ1zMnVDll4CHQ8knXk8a61s1IV/Fhyj5KyHufoF
2/kzawUknCapKCMfcdX+dk/DeTkQA6BrxUdGSI2YUArJO3VAulav3DyWCohkjq2ZsfGbYdfdiH+B
tmDsINtPOmz9fUYKmrkiKbw5c64E8h783Ak8rnG7uxu6c/b07Ir/C8tU+pXVZnwmRMeUlnSp3wNV
ASRDK6BJcaymFeqeDEtuNainCvFrdnxqlu4Bg4Urw6v7QQsxEU+DZp1trstoccg7Pbojl+h0xHqo
9PkG59DZHOUXa4eKYsk+S2lAn7rQa1S90xam3Sa/zv3e0GOWYQh7ygQ9OlUnFT7peO38MaxZ7bAe
uHuPOg8Zjps8fKvhpSjx97XtAJzloDDuTAkZRFIrQxUs5I6DrfVtHPvFLVvv3V0V3aUfxcFqKfTs
xIesQfnPjWORLSHNgr+WN/o6g3OXZHj4B/SiHbF/ZCKa7S1iJoAfEjknuXJ5ukMrKljBhN5I5lSh
2FyUZI967yExF5xbv7YA7tKmDSj/UVokt2uFwT6Z6OAFBuMDr6RH955GwnhxIFEET9VeMNuOiB5A
oZX1mC0FFpRsv+vlHLZZB6FZ7okqWAMrudBVHk3QbveRzMHoCRlXmpJST0Dnv82cV/RLGfV/Nz9r
qmZwS3y4X6fPOfejEyLxcJ4Pomt7UZyMPTSDj2U49OamZc8Kde4SEEc8PSv0IuyG40ggjBBMt/1x
tAGUI5kkfrtxMgV9FGB2WzU7hWF34FrmStUJ0mnBK/szuF5aAGXkmFm80jNAr7W1WjzeQtVDiGvV
h6/9lxJ82mEW9+GUXZ1b7CD43IwBq2eQKy5sPNOEkFTGIDQsTZ/nqtKiX5wx1+TZBgf2HK5sxVGm
FtTtKKIV4BB86CWhz69c/bKTgdV/t1Y6pAGZPKruHVkOII34/I5frn2XFRhYDyMr5Xh8xawboLg+
c6Lhy7WXg6jGEHJ1uM9DUEn8ZhGdJmto+8MIUuYxV9lesB4rD0UB3ADKIvrX/X3RheVWO4jpn1SD
y3pGjUouDiTD2iaZDHZRQjHZl4fYAyk1+eIeZgHZFbRcG2uQa5+WvW2dSEFtu4SQZbVqXNuye6Xp
C7IJu83xCj+Q7dM5RJkANlvin+KWneFdVJYSUa4GPB2iXoF/5FIOJMAiuvtR2sEoQi0wpbjaB0Gu
IC34mp30PVdaIkGNbEoyTmqas6uFNgTECT3X4CRuJ6gC6mr1mZFeYOIZgAz6oKZ1j1EADobkgtoP
8r5JnhcMKwiQ88NY4NcYfR9avs4LE5D0fD0T1bEtjfLnKteEKG2/9PSY34g2imDSZYpIIos/5puO
EIqWN9jmAf+W6mCHoqCHWdtOHgW/u4oCT8HpA2R4MSq12cwqbDz1/q8YvjpyuDyPl//UlTskKav3
MTcLPaiYPiB4NFiT5U4bbCR5L5FkK00AupUVqyBgcrY3j83xcpHewNKaLJw4VWOVG809lF2wRzMS
iy/lYrwgiQFCmZD9q5Mc19vaUykLFppkYX4VqsR4DyTZwV3dRG3AdTBmcaOX4M4+EtgBBVJcwu1Y
R/c7KT0dUct1jb+Cvvha2cKj3ng29iO8PXVLEhW5EUJ5v7kchTdQ9yWbfF6gXhwBLKyjfnM42qD1
cgQCdbMU0CR2auW5dZ2ZSvi+wz/MKJj58UIpYVq8AFPs+x/P5QtOy6IeDmEtZm4/khRGSBMdsymi
CFVXS7eDDVikYU+X7jOtdNgFXzwEUtS4D7DcrSMOfJ4zkd7R0T/cXjRqknhtdbZ0d6KCxccg0/Wv
b+tilAfTyM9K+WB2AsjS8m0x74+9j1dj5SxY2AtO37ZdtQiupcCheUVH9y/HQ3JvbmUKwzeIMb9A
lehiQvdN8yd5ZSwuoyxR9QCSIHrvr97ABJ93BKQ0OdTKFUJw6ei4tYom8E7RtjUNPExgAGmMA3ng
9usD+aMjI/B4fmoNUBK5h+o1eqvfW692FbjO8ooXCEPCt326vy+YCq6W3AjupCI0F8ztMVR1fYlZ
vtG1vPEwPUOBx16SLu2jsl118eIf12Gn3kg4aEIzNeyjOChVd8Od37Ng5yHJIPcYsM+PLqsuF5m6
qGdgsSmtiwgO3/Q2MgDGZP0OFauV5yS4j8cJV9flCs4WCFKZI9YkAWc2Fu75s2DcZYIYvfv/oRtJ
a+FJmqBBiJXqmF85Oc3HUptgjxlqRbBgHV/SKUlsmx4eqxuoYsjou3z6m0KKgEQOaG5QOInj3zmk
HHMNeB690Lbw2iRAIF/DlSaGilQsWzKsjJtgj7Z8WwwkAzMR8leBowYM6gBpUdrBI7T+QorAmJnu
C27/Kh5DJAoFghRFkBOktWDX3GayyUE1ZoZ9327WzeCAok7lDaxf/0n2xpUuYOZqMo9i+LYx/xlH
tyRzeIooPpRrK3dYBErm9REg8LudiL0Xh8bIkMGZH6CNjjfRTOZ7o9QNoIGzyeva05m3FZMMq13I
R4KnfA0KfpB/sVFI+zpQY8gdgl19ma8lD0fUUFQ8vGMSHGmtfQR0jvBmbbmwyYxYL9BmNTNpf6mV
9JOX+g5NuoOBhAr20tPpxQ1n30o1Lv/QzCliHi+CvGJIqj0Ca6Dt/KB6qh1cs8WCWoDbpqcqLHtP
9m+m7w6QBuO5vMO6pj7rGqPD7QKWOTvk9CD8c7GoQl3NmYpsd01JXohaQjSqppcMkJX7a9pi5lVt
psFPY/dO/5FHyOB9Uz9JtGFQufyBo+ZhrV3O/IyGKAvJBY2xXTQUgKLW32kvPynjYa2uLphJE++L
mLSL6ZqO78SfPYv9E/icIlbwBY2N+9N9H5meJWimpopR+wQ3f0b6dR0dtezUXxQRbVy2XLUh/ACv
Tyz2fnaSkBJc0DoV+OOYQsVXg6miIiZzgIO7MRw1485KLhUuG3pMOCDaqdGGAKaadPO19HoaSoIP
COcya3SakL4+oUDrFjToL5tAHfsHGxBdYV51TC/6ax38/FpU/VVTuLnx2ESGxxnX36GKqiK7w42c
SmqjHHU8VhT2OJvYvAmlkNy+hFGlUKl14+HZLC8WyujnCk2urpq5XOhOdgkE7gaZED+FMXQjF6/n
dGu4HLCplxaL6lsFHX9vYPKDZF8vTL7HnlXWTMQg44rah1RmYbikAYM0m3hO6doi9R7LspXKpe40
ajSaWWv+ZZBb/OE30xGmAzEAeXm/iYRk5ZGsq9U1VpTojM9n9mvld+7/MM3z94XEKJ5IQJgRJxEC
yohzeMO4GIgqPf+buUy/KdVlcTh/iYF7cRUdks2iScEjGu+XGKrYSi7qCDaMt7IMOeD1w69OAxyr
enC5L4ckXVZHApRd6aWFY7BZwnDkl5FQ2MvfmfqnEkAZEyO1/1d4KM8DN7a8UQrM0+r4aNTWm36E
S/EyafNU/deBJPtiWLPXmAXluWQwSSujSjye4LjGvc4eEmDY/+738ZkqRThOPEJSPJMRSIR1/Mfl
ucBtxY/1Itlqiy1wXurkPVV1CgFSBLEKqKHGsKEIEGrNki/NbvgnpHrne7OOlJvq2bv9ZBxY6KcH
fxo3C5TYf6E3ZzYYrBo9/E/9hUPf+QTE0nSXVWt+UgJ4c3XD3RUtLalZMS/OTEtJ9nmtRWQ9TynM
iJ47F7eIMANUsc+BN5NqOGkVj9Fc3TCBv+AoArI+7N1lHiUyV02z3c6hZj8ZNCxeVsmU4WfutsAy
ivhhpFQwG07Mwa7/RLOjotV45Yps5+fVrLCzsB63uLB0jvLXWAXAyav0fWOocDzFddMAKURwNFUa
Pqf+J/13yosLw+2jxf5IB/1cQNumLjaSrwVy1KOCXiKxSCJnfFVLAkThtlsG0DUDkuTfMvgaH2gF
Rmg6HyPXOh79APngQybUOQVjv/9rcPHMYzczNFjqvCX3wY4gv30u4TCOssCWQ6D6Jakxe7as5/MQ
+Sqp196to/Ky22hb752H0ChNVTWpxNogN8eXU6WPxUuCL4Y2mf2PoE5FLc3/8pgM1zmSPSO3Mdfu
9Q7GSu2NSmNIHrExRzfplgTUBQFcrEOEiFoxXC1sH7KKIhIIphk3D2msbn4p2itM0z4lrkHDOP/6
6V2eHbN38PVQVitKIesVZ56uMhMZ9jjLdnLjxkFI8/TnS57+0XFdeTB4IAG4mk4umTeqfQpWJuMz
JP9Qz6T/vXe1OLDH9dFd9r3V5KboChBFiUnvYxQutNI19rEi/hJboawZ6w/wY7/vF3FPy43O+LYa
3MdTxwLbv55V+qnniWRJ3bJ58DGgwHFbsY1gMAYnp4XFdrBfDWJeB90pH01FQZP3YkvA2UdtxTUQ
sBPmNmWO+AwZDtiaJyCb2239rbYxmTcllp7htOFxGiFyc1p0x6nM1KPQA2PdgWBlvhfrZCXooNTc
EvasGmcfwwGqT2/2jNygL4iM7CZLDeoZmYUSjRZlVUtI5knasbaLAdrPIopJTCTaXrdQtZP36h8r
9xhRE6xahsPpQ8EbSzQSzC9Bzu5KjnK12z+/laIer9MaGqgvea5fxLUWBYXxYMn4LRqejJP9Z833
kjQuwFo8vom5vBreUa6Xz6bAaPFJspmRzOYSDIQRe4Kmp8IHczOUr2qthDoqcFML2+Cai4dhymFQ
tRLnzdp9pS2DHEYZ4WevbCiptxeHGEL4c1T5gk4zLqsuGn357jkjmOYwrWP1M7RR3GRrQRoAaZy/
kVcbYYpN8kscEDwvYIKsVrZy4TawQ4R8tXC05zdHviHcLAqbNj8f98XV94a1APCn4cdBcLqwb7K0
VuUNDjHZnZty3Pz3/r4ybYWAWHFwVfPnUn+7+IQEHGAmiil3E0z5gAII0HknlnikWxkFnJL/oOpa
l+LuHi4ij2Pwzfj3GleY8aEfV8KhPSJFzbVulwVQnvr4o1sebDFZOAAyr5NmGNr7jwtWD2us1/W1
/fBxJG2wfy9cjwWZY3MbWW+UxMheicHmRjlCkMw0h5PLdspi07k0J2tUox7X11HyCbrFY8UJay9I
D73qK5Pqn7pE6WSDqXkUwrNxSCoGCDQ/TXZ2pRGQmc084O2rdhJbrjyodiKiGt879uzJoYqRJvPv
8yb0vw4nPczOewJOQYMTrcC+Zrzhm60m4tcD7HaMn/UHskRiEx4u+Gqo0zfgjL5rRdIgu9iCegOs
BWxs9uarClNw6yF0iHHkQYMCUvo/MLKrERgo2GxIgiVIcwFjbX26xvrlveWB5fiuO24qwvAYWtJR
i8ALivUCBuYpJGdoRdkKqt+FqvWROZmUWMRgjUNsp4w9+JomPZtTF0V9xk9RNBP2+JQfdKgXTFI2
1qedwcn7xF9Dcr6CGKiOn1UuC44mI+yoo1e3jpS+NH+Hxgn8dAvhMj40DhX1aQ5zUvkEhIES5WTz
C4iuvg/AiZTrYEGzW/8+Xw+M2ip4EzBrDcDHpcxvr8YIDi3AIMUYldjiMUv0kp8WjUwi7RF+fCaD
LU8vlFnOSXI1NG7u/0hNo2whJPeeRtUU25YlQ3VXZTby36LBiOMv/xQjIq0spurKYO361r9g9i0j
D/0OcqU1mhoCVijThkkV3HmcMty4pp9FOQHzAx8GM3dyh9Fprr4hTZZ58b40EfVI3KnHt5O6M3Wo
dzFjwGfXuhVvKUpHpfzmek1BsHqPADtY9wrDls3kdVBoYZ551P2F3BGMacHPPr8IUkp91tvyRODG
iVY1bN1bzb+pr1ZDoGSS/8+OYm0eUJ1AlieBUUElX65dYMZM6JdevbCJz5oift9vT9w7+MbWYptp
y8Gn6LXncx8yaoBgqSzMLpawTQadXnwXXjkA/idIrn8RasXsejx6JNLhmJDDJ/E6eS1eGB02ts2N
Xf7G/Px/XmtQEsTTdKa7KwduysBZ1IH/nABEk2mWejZB3qgvrcPlrT9m0EEPH8fqZB4XLJxb9MNd
v9zkja/sJf2T+91xdPbRUoRsol0Ng35Z8PYpAXg88UGm60S0yDlYwnd4vDCdO7DKmmi4BwmnZRrj
P7+lBi8a2m6B3oIFZQMD1rTcDsYjdZm6DrzPWWVBvjtJd6bppHGwBwas6AAJREbH9+Zwjd62Md9+
opz19FQefF88TwJFEjHU2xvKhBKz3csUedyNNrVSn2ltEBd0i3evASeHvPXxd61p0X9lQMOt0GFU
hkPGRsGCm9nGn8odP98XD5elodPTlF82jhFJLWmqrirnsU/C1Fi20AGYg8GyUckYSvEYrFoS3noJ
Nz9vzproOjUP02S/+1zbfvqQXP2XvbFMVxXjmQiOO6b38WW2TPVkcPyCl76m/dy1+Tz1+zDELdHV
jyZ0QuVRmtgf0nozvIE3d6cEuQZ37RlVPqLOVyHtcfiC0arfq+Nz8hprQF8FkVBYWE3WRr6W/ovy
cDc2KFbL/vQd/GKn6ZWrNt7jiYNZ+Kx6ITPapHzOb8UN05noB4zJ8rLiyy0hiodZjUxJ47LcpHBa
TH4LAjUisDxdqXWiMweQUxh+wiloidwfA1wrL4HZ5ZD9JFH38cowIkclPFLFNjQUv+o3SRZNQg+l
MO9e09/0qOR5qMRKd4V5ZXOYtJ7tXKfA5iprXRmsU7sbw+cx3Myt4CMmSpTTb98kohP/92bgyQWI
56WVST8wABk+SleLMGixmJ3U53rXPv/xkYVQAnGM23k1l/wUwewzNlxPfhx4uJNyhAublrGvd2HQ
3evw9KWsi0I6JaYjA4gUvj3+rJlGLW6ssSRCRegXzMLPpHzSYNG5j4aR6QKTq/k6Cj0xWQ35UmzY
RfpmOQj0YHIfKDnJnAafp+IecIsWm+sWwJzsL7hhOSDnCuwl9nPSR8uh3Mqu+Z7dphQpCH0kFqcK
jTT9u3+JtI1GCqPTsgcq5eFTsu8C4PIbP/7xRDJvvKoc9uZHDAX7qIbTPVxraXg7kysT4snhIu2/
gTJa75bG4K2KFAJjfYCNRMLzoDxUZI7mPkiALV0RokunXlOmD4opoSQXaRGrzO64mRcQhoks69qw
/JiOiiCG7HJi+Y+a/7d68TTPBFwDznYjOtbBBk6NOOFeGpoooiHbCqhFqaK54AwYB2W4fpnYyZ9f
50Mr0oheVA6P3dpaeogUQnI0TjdBOW8wnX5F/AGyAc0SCwucXduefMZ/PTUzd00TgNiN4TcgpSHF
98Ngj8QpFg9RRdsEc8o2L5JAniPXFxghzwf7YlD5ZDKFi+ppr1+D2InvIKTCfxI9gBa4MgBpUZIO
CLSRaZoYPnvpNG4lXBpKmgSxpZVCRCNjpGbuMDHp1D5nTtcCxVVfcCwXFXOyXEcf9D0opJR4jtAr
sIySWA9qiLVFmHk0bmRfqq0Nd0qzNb5uB8Yl9rQhQDe0EHolrtvfI/vrKuf3wVWUJ+8xoKAKuDql
WGuC6IK02OYYAIx2Ggw4xHsR5op4eIlQliBsTJvM+T80PHbdVXKeyon/79gJbtaIOu7bBVTSksW3
B/2kJKuEDdF9jgL5dDDIbpovxCkZYBBUoMKxwOQMcCrIzgN5373SdM/2Dy/KfG64jc/cGP4SImq+
3NWBtfQnExwg2xSqAwQF5H5KN1JTI0GwhyLpn8K2Dzm8Y3zOacuW0mPtXvs8oTA/fQl0W6Fm7yGr
8jtja6kM9imiG0pYP3Bdr6r4DAWXJ3Vjc+6EvYdwfnK9ei5AkeJy2z7/xRLu4eqp7P1Jp8XXlCh3
cxtor4f3CP39d09N+TStEQGHKSlB7fZ5uWt74w0ZVg88gwemLloXL5cyEmoC8UNNS6ciEctSTlgr
dfe5D2KNynkPYSR6BBHvk+C/aRevqew9WSSDzlYBE8pBc5RivZrIm0jqm1WEqBGsTQMtcEDfMS9r
iMyr/bf52NKF7ZWMXmdfwE37GpOihZpvvbZU6lejKeZfC08Q2Wm+SuLiKhZgoYTOR6pj9v0XJ2Lw
lKXx2EJ4rbtb0th/eXYz8P1k8uYs6zpgxtFT1iJQG/InkER6lFwgMdZbivUibB9KRwbtIQUadpLg
lryB34IGePZGq8zyaw1meXsEx6oqwic9qPylfp8WoHa3mf3jGXNcrfP3vMdGZWn4+Or4i+rFkOGJ
A7yG1QS0NZgtKcRP8urzSA7wJeK2IdczzR2AF/pjUMNFM+tvXxuC3gVXcfy2SJv3uSo72BQP2obt
7qKhDJ1WXLxFE30/HD4Z8i2lKf7z6jk4nv4Zqj7PPCwNQNp0mnhl3lGSKwxOeseqx1VPnq+I7ndv
hAxf17BacFFaKJXfdEOM0q8qVbJ6ClAlwSylvr79WxOmpq7JbgXoeXjCOngP920VdKGa49ozZ5CJ
xoiCi+PnWe45DpIqL2ruxDiW/AdsTk1wTXXc5rJh+kRZNRZLXnM3LHxBB2hpGPjT31y4yXpvWB7X
A9qap3kLfPyXMIOx0wsHYhZq+PI8pYIFeZ/57lncQYbH4kZKFP0Ltl5sdXFcVbxNpZHk9lzg+12S
7qIq/XyTb54WYJIyGjlYV+lTy+MvtdU/wHgpQ0SocrlYAajloib4pxNRCjJ7InvN+bScEKW0UCA8
qLsjg3ZxZKmAxb3d2+Zl1uq3/BEeMTEXLxJu1P2Z6shW6XhBSfjsbgxKJTdn7Khw4sx7UkSqTKWV
mPYqSX07BaMnTietRrBxaecPyN8j5tIVk0jq3BNFMkOB7wNcEp0ZkL0yaT1QXeqHT6ZRs1QwTw7N
MLp/vikOanj9oeu4m56szNNfNjy75pxJ7J+4M73qSJEmgtXAYTlsPGt02vMG+/eq/BYMJpY39Asv
O3sWB2qGIj2X8dooauSTghWQ+C3GG7O2VSeRNyiyzXZSU67rPRh74g4SInXbdr/1VY/yp7tnwVdL
Z/0i3/z24kjBtvkD/Mn4y4ckVLDgjuxHpbHkcKRiLoTHpeUGWv0zNk7gNS8jGDtEbrU4XBzgtuHL
k5jYbYGvsufo1xwqRSnXeV7SDz5fBX+ErAtseC6E0LVNszQxkFF3gFdpOiCG7mgJgTks5Zm6ORor
pbXOH0vkKAPsQAyStvySNnGJGJmaCloASmdKVzxMW+3sTECyrFJMdVLrOMESO40FIa20bZhqxHG3
sUM4Ci99JUKqNDU+izhTe6Ma3VdrqdEW5G1EhHIhiCmgHmxvOLP5Jjckw0U3oddN0i9F4bucJsBv
sxFwuBkp8k4oMTG0NsDBdK1Sqkcz8/SYHQM9PcPKJDaimB819EGUPgpY/Y8q+5JxUrl/YJamso/k
bf1iCfLSDVb0+8x8jzlLO/CkCnk529DxbfVUPWG5LTXFHfNFBgfJAEnoSubf7X3YbFGpuysGQRV7
hg6uvgCfSxDUEFMdwiNdag8GH+N/vgV8fnGHM91vEZxTJp2+h86WnACzMag+hQ2oDYXaR572PtrY
gcpE8s4+R79PUVhqUFxEye/NcTn4hbppfgkCClukI+XPf2q+zoBEf2zGzL5DlIMkuPldcyacj5Xq
BrDn1O015KuT76+giFC5Be0GVn3r/9b6X+zeS9Fs/un4zJaMbdpkY2Qkq9N2Ez99X1EFL6P2JsRh
PFKGQX9JSoknQNehdEfC/NlIuglQUjNxiIccvR+0in6XYRpfkA2N5JG9NQe21e2icwGGSoeNxHzw
u9W2CqSIhhXtrRxsHjn5MwANPG6WQV6kb5tXE2o3iUC/NZDT5rKpugYnwTQviO75ggi+NU+gKEjq
JwUNBYqWLDwkV5l4Qy+RnNktQRhKT2F6dye9I7o5kBCxyyrawCT8WppXcZ83kuU7PEyc8O1fl9B5
8F0ElXwrDAWbwfwpzKcz+X9U3VxM5K8ayuz0NNwNU1VkkXWlNbFOJHsi6OBVgtj4mNNKj+XiaRQv
D01X94VtF3yjDdxi32PfKmUqC+vPkotNRmPbHfDgO1JdpKwRgp7gO08AXekwTT8CDYBjgdIP6xXR
PVLwVbERvuYj5dT/EorlOZ0E3X0FpLrLzngXv2uhecNq/A39OCWJ8o2kVhExerq4Ix3cr+iIFHGf
rd+a+0Dq76wMyonKMoyGj2ZYxViQ7enxhAc+sPLXXwBiCVMZc5s6mKr8fQb7I/yTWlPFR/6Hrbhe
mJz8BFAkHYNqFUk6Y73C8w5/bXxCe+M+KPgirt5EunIFzRij09RHWDOcKDZeQLLVScZsbP2yrP3a
KUzoXDB24zTmONpcm/6OeFhMrSx0IEdbuRLsZOCJpmWi/R8DpiNZuvE6vUK/HLo9b5eZ8Y+/nWh3
GniMPLDE3bFyOnvHrN+JtGh+1dDAZd6Ez5xIjmDVOpr8EXMOXPJggSpuq4wE/aLz3nGgTWWX3fYf
yZbZCY0YS0D7b+mUz46k21HfmMcuw55kZS1pwiijPkerCtLgO+AyZF2/uKV53isfZlIj3i+zq737
I1hZJV3Aju+mQVzVVcA8gKVgAbWTAcQyLhefMdkqKtK92oEVNza3FlJsRJu9iyddvidQk8l33CUV
5oQ/Ml3tgouEO2X3MCLEzEtzz55eiKD7ecwRGJ9FzXaxVPg2wOdWNDA/813KM34cxtHTJm0Uc1wP
//6vbhLvyvdSkTtYy69DdK6UDZ5InIy5KD005UHxCiM5Vu/rfBQgEk8y7Et8+1DqEPzv5JC2pPlq
Pg/8GfEmmiVz0nbaqFv1K4IsxeRGBf0iNxjQsLEki+64uosB6zY0EMNK4VZRC2iAhq/g4jSN4KJx
yT1FtpE2BSRh4sbQ3OXQXnWA0nFBSb0SHl/95KXPNf2x/mNC0FYwXww82BLSbzJ1d70Grx5+TWLU
5CmZBpvkHs1G1p2hCYsQNRXED8qde6/NRwsTCpzfATK0VXyWGW8gvuf337htMnhZW2u4otuUkc3K
udCQRG3fKcBlipWAyCEtaV9UjfXZNdBvFwICu8z7lvg9632jBNfZO7U9obu41AGoe2BufI1BcVe1
Vv54gHtAK1aqesmTrtTMyFqrxxMbiRaHxIG9/3PQrFkCTTy0rip5wQ2g09wVoWcd1pyciYJZmEjS
0vsPAnQB2rxW0/W2GN1psG27j8l4zimMRMY2XEsyjQ+8t2Cokc1JJQvpUa4LWpEVZYAYSWpAmBvP
N7Vab+Lo6wdjje/flJHDRRedF2wSLRuEiKvbhPVli8P3loJ/eGQA536KkYtP04D8z7jLHmTax8IH
DIz7VgisK0wdR5aqtt2S2KqV17VgZ+hLlHgk+D/D2trsS1rA2NzdVCEn1JnBNd9gbyW5sZW55NKn
UB7kcpiFZ0miGFYwlQ3gRMiTCIOydE1K9YsOv/zsuqbvU7Bl0AwBdd3M2yFy0hed3v3dNgj5LBlB
zPFNhGmVMggKe6A2/ad9m+mgATE+dG+obXKtm1ajHG0n0YxUoNiHmLGftYGy3mpTVflapOkjSOiM
6yL6ntJUFwD4mYxhLr+Xvg/rwiFznzSU98gk+QxzfoqWXYbm96UEtuTTfNVR8gTiV3tvG8pQ3psX
x1PguFTSQXOWc2BRUn/gM5YuUjLW7v0G/Ag8K2kCehAjCHfXLMUmLRxt5cPf5JP76vNTGmbNVsKq
wouUwbfNydLsd8UIf0DKwtQ8CALX9fxQ9wWm2bZWgJ7itT3xwpsYsBQG4ezuFSSqVfao/auD/aZI
nlWUCcQfOqMYxHZR+Z7noPA7fH7BPTNCL+Q/EPHBYcdO3YHHsZEvcMg0rLVfeBBcsS6BeaD6NJwB
8NcBj1tqIL/JALv//zrrC/zT2EF5xDW8wmra8AJOSSqjFjPVh07dF4Y0JNkNPAut4d9E6olrnBHn
5uVAytns18K/vTLEfjWkUXLtUK9xYFE3jmsGL6O1gQ2NcQ0A1bq7Cjrqjx0k/Cg5nfQtFD//VJaa
gZrC6GZMY5kk6xRHydYWP4X1ONYXSMO+esZizShHptKKBqgiEg55iw3UwfwTdhJ+dy15CACTWnEI
dYu7cBVrE5Rbt/mTFHLBULR5yVbrKmIT2wpTJpm9Usj1TseXjIQvmd7RAogswCyuewQo5tS10wmt
5WbkjB4z7iRUhzg0Zr7K0MSObhWDiAx8ja8JeO/mp0zI3gSsFAy5a/hRtZAVKw1rtsbzdOeNCmPu
ycMpsRkfwpkxMQaoOAOslLQQBFSL8EMafepXqH68ewlqGk+p1sYllnPCDlvgg0vKlFcmvPv9VZD/
BlhGfASuvHOLty0BFawUNHBvET9tYkssBzbVDy/nDBkV/BHmE4+9g8D4eOGJtKxM7FE3GZBxI6OU
LLgGv8KjX8fbN8rEwPPQInUb6h3WP1UV81Zlz0CJOG66rFwYx+8fJcFkAparHAnPJ3m/DVNt2sCi
Nz3xfnB4OikI1BdmZAn3a1zObwI2z7ws9PmVhuUqrbXtV0Hhehl2Tz3xPWZx1pjKBmecdTekJ8R8
mbxdbCO0uHje3awuruZScPwjfYN4eIGJlt0XKO7oabFDPDePKA8T1DApJ4n7zO6FDv2Bm/wUgytz
5z/FYWb8d/58nKK2+H/ZbbHrOyuDAGzPm1MvmoWym9mUyIiJmMuAYQPl5klAuhmgIKnVUjjoiO1E
qxLZRS8oEii4q5oSCTjQ3KY22Au1TOwbcY8fDnff/B300WEwMfWevRzOMVgDmQHdWnZsPAmx+1ON
8OJsETkYAUaj7Jqsez1rng2j24hUTcxj/8JT7lBhZVFo8a+RQ/d+qw7jtbyhonGGzgB5575Ys/4m
g/rzvy4eYHrQ40mNYn3drPJw44qLwiSmwldKgBVZzGRWHUHxWiWK9kwF6cF9SirWXL+GT7u4WYs+
OpmYo6h8+JKtV4Geha8BwDvPHKdfT+bzq6LJJktN3HUpMDuddD9FFFjyjgGEkHu+AvISMajsoaf/
JUNoFrrB18t9WD6OWIu2ZEAlL9zJBd267U0C+DjVNOJQUw/GDmeyH6nH99uW/O/QQV7QhjuAa0zw
/mNHDOeRtUnvx6eX70C2+cat19yGD3FmaGhfmnKHj6/f3LI/niWkldYr+NSKhQnsrNXYbE8OpL6w
bPN2Vd7uXPK3T6PzVmNmCT7a8KOaLQ46HEtSU3DvoP1BLkYQekxl9fsQUWKrCi83JiUuDxvTmlVI
BlGqdFsKuONiwvqc7LPlmQAcQr42qYIhK5AwqqxxRhu7AjKX2X7YtR5HPB7SpCg0pa8W6EpavbTu
vb6AS5donLUa5yKCooX8QsizDlZ0IJwPsfuxOe5I7tOVhTlefehenGezFk+Gz1GJsBncaVHJtAfZ
G5UEKvF7ybZoCOYbt1a9iDCE/RmrwqZ0LrTistaLM9pehuOU7KXNYIboZdbtLrY1kMFZOY4lU+If
P0wLXsQIHKIOrHR4VgCvM2Wa+OfCqR4Km64UCsfuw+vPoR9hVnq3GQTrBe5/DmlgdMVo+am9f/Oy
3e6uMfkOsRPQ1RFAg//ZtaplkF6R6+kec7ntesVQi3lsO77BuWPdfsdRAyaws3iQPOSZpAT4J+eg
kV2YipxIalnF8NU/BGzXL5RY+shIbIfiPLYEY3KiLMuDE6fpK/zKh0d6xFYqRDm7FhAXkaXIbmr7
7FcQTEuE3PPGB7QKO8uqKaKWlUN8yQcq5zlYguP9V4bduPaun/kXjAPeL9WKgqvlAoVyVTyb/Gqu
7vAnvWJF7A2T1mjcTq4T2Jre3Do1dYubHYjzlFSrXMqiG28wqwHYBVdLoyG0r4Qmv7tQX03hblis
+HmxXIC7kgDXY5GjdYGj0jnE3EKfifQAXjQ+a9ApmA==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jc8LEfyzhB6MqNSbhlWuoMUFNYcybITivORMfB8rzl4OkHj0KaI8+xV+sqd+1SaETTyIozxnr9sw
Km8USG6axg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
e2glk2VzurZE73FjU9GxoFY8HVJy3A5KWf9ojsn3WHmQPwsWSCHzx/z0K4Z4C5EhIBc0YA+Px/Vs
9ZzqYqXeJZcbYR9DwEl2iFv4k3ZVDCfXfVdoOdInD07q3ji16cXuFbU36aEughYk9FyuzsFnvLzO
3eJRcKx9tyRTAy84Itg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
sGLPLHipVjTL26IUHSADhjydFNIITmr3F6TKs2hIYEmCIirlVMXj+FD4MlMzlCkl49pAm6Ce/hbh
NHUZrJGWk4EBiv4mT6yws4zdwXwiglH47LRzXpqmwy3byWUrOhCNgZwHDAK/7WIlLePQu1bfgnYs
z+28gMIxLoOdTVUkmzqeGliz127jUgVHeaDQuRQMG06Spc5hiR1hpG0qQJqECKt37e1wg4xla0sL
wImVQ763NgdU6xYkjH6TbcGuyB5lwowlA0koNEHBJCWgFeXNv4D+8s0zmDfUrGkxjHomSep6akea
PemJx2MPv5svdsWFZoOV4pZwhjzM4CkoZdeHcA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
T7Lz1+5AT058Kx95H43nryI2Ho00JIFHkUdt/YwNLu+Pb7rPXgmxND7abttOfbuDn0E9UvyuPQOL
RovwzsRTvitzL4knMlppkGzDzkJrreKNi2ze7EqNMC+UTgNK3cdiI/LF+1/RdCPnMbMqp3vv+DQm
JRPuqjEuyDs//JtALp8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
JMw/5G+LHV8rF90nVLGDHIXkf0FjKIISJK9ovLg3twB5BphjTn59rHLpRHyjEjL3IQsOTSkx3ZvR
VC89ktrPJiRNeM+nwE/e2Fyn/wazkfcGUhJF2ZUIySXsyCC39DXyKl0jKuBB5unOryt9FppBLjRo
BPTpcR8RuIzeiGQsCO7hupEXjn6dmKgJCsQ2ZVo9K6JjxQLjxMNtsArRv/yRaFQhRiyjl/x+XlUa
KTQdP/Y4Sih2RfOMSOMoRi0EndJz4jmYt1mkX4n4psjKPJY8V++XQ/unk9GtDDaz8O+4THcnML4Y
uqqss95MLeokZvgVRySMHhPaTjfi3noLDpNMYQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 61648)
`protect data_block
qc9xgk8ux08LJ/qPe39FWHtjRfE1EQHVav6JwVL81bxD7Ip/LnhRG9fhcyHycrpQ6mEEzgGIqbRW
H8ClL87DzzzCd1KGh79aA6tQBVg77hGiBrEg1JpqhLgCtaYm6z30s6spRJwjzp2FO+sCBSxjQNmt
2hpNVWC95OeREWaudMuzG1PG1x1GGNTJTwqsTmmGdV7bFn2iopQyGJHw1TiF8FQDf2jEIgFZEJqL
3RQMwIN5FyAlf8BXujRiiPeTcrlW488bhegnyf0mRh274z4TQuk1ks8gAw3eULDyVbYTNqKmobgD
2YjuulsF8uUlePa5MgNE3hLGgp3Gef2tV9MhbP5i3T7D8ggj0vVcfNihOW+mV0ipa07hh526WKD4
g7vjFDJYvRccFgvlN4fgl7YUiHnbG5uK27br9Uml8PGw5ZO5gnHOcU8uS6O9JkJcpKm4z7+bML6Y
0UlWtq+8P75mYP36Av8SQjQc4lvoDwxND89Zv/ZW7ldIJzFfEhKAOl80J9wKJcWv3PREwg5I9XEo
ZNp2Lhkr2fAa9QPGpNCKYbHLlaT9qTxiStpSg+rDTBV43aOF80a/gVelHeuCV7iaTv6C/3sdh3p5
xynTf3dyWBA+VZ1mOHDIEp4lNLU2o9e4TIKtq/UQny8U1aI3iQrF+XOTAV4PsbBCqxF+mIL+zQ4l
R4a8ML8dwg2YRoPdPnocc4sYts6CXsGc5JaEniHnt6xcY1NJtfqittGtKmv4A1EdmZrKtA125zWg
WSVsldhdaUokWkk6fM43j5fw6/OiNZ30gZjZ2rcXqA/iLl6VUVqXwFjICtyrjaVy0jwtZo8SlcOe
oIt9vcSHGGGyDnDjaZNuCsSd5AwMD7LcH4bvhqMSlp7SKEcCA2HxhGIBXaDnYXg+GbEP5sVPiLMo
PB/tdZLiE5wVNl7H/TlvjmSOqK42TfbLyiNB5VObuXPBDLvrR6ynCGqeSlXno6nMX2xbsUH85R3Q
IHzcdllWSAUgMqpjpvnFURAkoEyDKXGfRhP2iyI8+ww3E/O9njomNIY2Qugb5sYJvmTBWzHzGT66
L9OmpwN+VCZl8Z+Cnxjvo47RgjmSpObvoTBN7iYzAA8Yn5MH8SHYBZ8PTT4h0wQ/jn3eE2TvvFqG
HxnImV69/TDNyXtg47omOyCE+X0xYM83wdztcEtQ0fvZiyqYN/pSc+NT6NWn+iTCyrTX9YHQS7Fk
IcIA6ckum6RlQw75tf9IZNjohe/a+gYg8TMBP3Ratj6uuiUwzH29Mg7TpOFytwXVyocUw0cRWKaj
X93RaXy/5kdqpiYFvRZI5PmpF5/kK7f9YbQiKrH1pZ8IHIjaVaTGzYn8njk+/xFs/Wjpi4vQYoKi
BcAXGEUswIqXTl3v5BYjJL+zNWtat3MoEHLzsPTS0U49BxKG1SvtnzmkHK63V9FWENCenwQldIIS
C0YlGExqdlumhC5omUnaOt4jh3eWtxVJlQIvn1qBQS7KIY4FjfwcnSx7sW4wls2Sc9DcUULQQxaM
8fpyzO2XCFAfiiSojRpsVJrfufRDsCN0QmICjs69Ga3pFljD02/nBPbz8jxiRmDbWCAC1KRHtRgl
7IO5Uj7uSiYrhQMwOnyYEHFKFa2kXqP0OyU7fpfNG6KlkVpdLUtvJJIFeSVmmT13cgjj2IgFaTB6
DLgB8Ilw11oIk8mIoq3TwnjNe5PxVIgdQsANzXoJ7BN5jSJkooR1V+bqkDStm8KLVGcZ4uvKCFej
yDEBsJqoYH9KnIGH7Kt5RusBE8aSMChDXdvD4TSNTFRqBJxfGzqUEwFhs4cZ9Xr61EXxjyw1AEn7
uvaDzUmVprdLVOwNQF6yaS1EByQiZDrkQScwtXCmJlqcUVGBBlS8kVJ4Oo6fsKlKNo6J+IVUjSaX
2ch2tmQzTVS8PHOkPAPqTF9C6yj066bgBvPuhCmMuUoKUnD7F73YHZk9OYEsauH3zkrhKDpfp5yY
ofXv8wdJu0o+EwKgvt7c/9xYkY+/DRif0YHMF9yrQuF5xQ+tomyXZXIdcoDu+3CSNpNQ4cHE2l4l
XR3iJbBWpeET3b9E3j8j+r3EhWJhdJDA4fz/vu71sv/CV4u5yzFX3QrT6pO3ogj+qUFWSFdVpcuV
cukqPy7mZz+fSsXvzMXfG9wtNpNoAf9mFCVUv+wU3EHQJdfz529E02GmJpx5XHibog+5abof9t9n
ZfeYpvpyLpa++RlJN+MdEeOqebuWjbyGaO/tBvWHGb0oMaljBx8Nm1SHaJjcsNuColzw0Xc2P66G
MuKxcJXcUdOk/kII5OmDVmBiHwU9kBeBZ6HtSUy6sfvE/Qurd9rWJuzT5jm+T082MEooR40FUAV2
QRbmZMGy59yYUweXuuagtEWuwGARgXITJGYAHaP5qmP3MeApiyEGaPkYoQUuVG7KiBelgkmEtFJP
C4q7fphP+yoxxjyiQKnmriLZRxkjRWbo6Xh90dlaZWQlqQUeQ6aUWITepwHdIHP96c4XDX9yJ5s+
Dy96iqzfXdmS2lxvW/AzVUvacXxzZHmrlROqyqmIvnByCop9gFcD7rkuUUE/GLbRzvL3DaI4jzSt
v8P6JQxxgLPPF9ErEV7XG75mdRkL13rUdSnZsHsZoV0/BAY9PhM6A3U8maN9GB3JQDwuRBk/7tW2
VBNr7nzC3dO6vArRKnrxEyAvCz2vv+QMyh/lOFwpYXOXApHBKVaGt3JTx8Z2RMKvo2hyz89XKOjc
SoPlo3W5Q0UkHSZ3NNh6I/RfgFUx1A1BoVCrdUFbNevxWgutdtuvLAiel3+ESr6mStrR86xnimjp
/HZLEpCEst48+HAbQ0K8pdUku98RlJMcSGmMf705uhGV8P+RNI6l+e7tY7/7eyTzXXEn8bmmSuJT
JneICRB/bH7ViD01ahg4nz+phJFuQzqIplDuU7/+Fii4sr9jKz7n6riAFDHLxkGZv3Mv/8Rm3Av0
/G4fNakEyQGfgQJrb6MHrbrmpCUWj8C42myPke5quJ7LF+l77rhfGVEPZjhQ2besVj4FfN+EI0VA
41kJT2OLFT5ZomE2bva0fv5l0kODRcdKTxOY4RL4V+nDz2EkpT5d8blASFdn0sa3Qj+xTJ/MHmvP
4PE5grzuZnprQpNsEhhi1j6puZlDbMMnX03WNY6gOhITbl8zx+B+kFPLk3jvceeZgL3xg7vz4opv
30OD8uUWwvJJeZ3KfoPnLqx8moO6W7pBKFnRiEiSx5sShF+DOCNY3ijsrrJ0YU2j+QJ0eq1+zjSN
5RmEo5Px6HPlPcE/Gt6KqnlTBePEwH05OIYjLQLYwdDm1gyYBqIhr/PZcdq7RvZB2cxHRoyIpXsj
GCFjewWAPYIEGTeh4VJXTxKnxJO/PpakPK6tILfo4RneJfpoUJsBxBVm2JWSHe4q4mnYUxx4GwUI
8us7+YqiuJw2mzHg2eB77Y7vPUInE+GhORwyq1m86HmUH+nwQ7yrNn/BaUcslZ1vPy9ePAG0tb0U
necFGer4+JOLOt+4i97MOHRof9ahA1F2TEqv1W/k8WGXL/VdDdEGOkHdJHdphBKzNHQzyV5AAxTx
xWHUgvR6RbNoIRf/GnwfBKKAdhsKjnjOaL4sbYgAGoBSoRz3XQ3wnNfCI220R4gbP9qUJIUMXFC+
WmA86bhNmjnoQsoU1pZ4yL6mq9oLM/rYtcuoMB/03KLQj0GXpB4Q0GcquJWGuEJ+i2GQ+OtMESr4
5Sczxl65PoT7WZFaXN/WLjUw3vmDakfwmqVtnF6I1fJr6L57JDBig/QYT93NcLOrMGHWHWXqjHcC
P19VgODxCngVFMlgNK6rOPlVSBDlbAX6/uke2gxNXSaOjmDY5v3p38DJs5MUaGEARYuwCO/VvFps
lzE7Pv7EJVoG/47cTV1LrOfQRj1Lu3VEHEo5/OAmoT6W81IxxAU7L4lEUBE/IaqHqLweeYNhwft1
msSCWtzkPh/6uA75EcqacJCgGgUfx5DUp5I0kFFkxOEHWYp9Z4doQ1o7wyXDwY5FMjF3porIZTxc
vSqmId1IHTBIxMGBbIM0YcWfrlrIr8y8qRHUQc7lkP4kisYyUfbvoTV4O3MJzzEGzzyTdyLfjDvi
jukqXoZv3yW7aqliL9Cc3YzR6KTXFYxzS+EluXvCFjBCdXkZuhBSJmTNT0FPqznN1rV152vHc70j
w3uMSGcHRoLn9a1PXBngz9Tiv0iso9qBKde0xWgyE0XptyivecgZDxqChiN2dAQeuWOWBRNH1Tlf
tglvbjh1nbmDSLqCc/TPjD2ViKd8NbKOCL3vAuZeNlKXdSf/ECYiuGdVdAAX5doGD9brCY+tHCXn
ny9P+nBa46K+9sMsXlaxkPoPutqcYxJ4r8wFdnXJOX0la6MFbxALOagO2vdKgXFkqeoItDYD2H15
NeGAkDqjwW8mI/0W7eGKMBL7FzV/8u8KnAyr4KN2D6utnMh8m9bHxR6sMVW5FgYcmhgbW5XLNSNY
goxiu4gnZ1ezCr0Eo+R3DNiIXGP4qfjRnOMn1e+/ALXnkNBHGciV86Huy8fr5cc2nmzOAbOwJuFu
ixXDJ4I8PFYkgDXpkmzGWa8DscFo/Hb7gJWvVIH7Bmv5HlOuyZudIHemEIazF9dw8FZWEyQg0jY+
3qU7pRZN/jwDcCzp2M4+gzrTgtE9XLIwbUo3ja12HTOX2z4FYWq6TrqNPvtszQbqPBBb12rZEGln
kv3oZQKiYGnxkgh1EidRP/sD5whasfR8wt7oiQ9UsQUw8pdJzF/tsYwrOxpJeZkM52sRR/GCuUhp
UYO2XNI2tDaqhgPNDDycTEj7/ofQBhxn1ZvCQwjKeFSUvrqpqbyP4nrDovd4Wt7j5zbprfKayOmf
o6/U6Zhy6B703AQyIMju19DJG9wX35m9HQs/PKSzET8CGDTymlyT/l23YyQ528FJrFnFWa8F9NFY
HT8ADI6yZFFrqY+qzLP+izVM6sCPKYmcxMdrnRIByS/xlezt7FZdj2uRDJZil54H8LfvHW8lq7+v
iGoX2tRG7sfNQQU/fXrBNlNvIVnlDfSc0vKRyA1zxzaL+HYf9LSzEOKXeVTjxgii0/rGshdKqPxR
oB/KCA23VeG41zmZnupNHmaOT7G8ziycplPTE2w3lhq0h8CMtKIW8Zp6fIiKaVIVVdyX3McLnu5S
2mXr3JfZf3kWWMMhBG5ahwcJ54IHs9G4zV8bgP22SzkIpP7478/8z6bIY59ckL//0kUc8FrgU7Ws
4uLtIA/MEFB0ao/0yvI0tce9cK1EeBfnAbw7kaKnLhhk+oa6f9pyMWVwxLgrYSe69rrM/63ujVV4
Bs0DhSzyGpOjDolH0ri49NunWz8P7HQrER2NFQ9dut9rAHeZfz4ypxxr//22dbZkmNds2mLEz2f5
OyP0O6w0iM3vZfTacTj/CyzC+Hh0tXJWY++0i73nRgyYkWYayQ9WBW7+EaxZABzjY8nj8YBdgSdK
Nw5InR2cmqjiv81BjOtkjklPlbkpM2OhQFi8PqqwP1/mC0YjTCy3+pc17wCHo2mkfvJitb1MaW1V
H9s5UeucfNEQHO8UcVd+EXomhuDsiRWBEM2GyBrz9x6y3TczYsfHPoZxiKUNvM7MHaIgnXviKJ/A
ZscaRJ/5qLWxCChxtsb66OmFVk6DGfvU8+Wax3rZbvTirFKyGHSFmVBpSYSKLV6nL+qcQXToJ0ZF
udLoPCBJ0BiVMgsSPgzfAgKqOQtpj1Y2/nTRl+/AJAkQWTD/k3f+q7DD/XAn6T+V2QL/dundRP7F
3gzz0XFNkP0r7m1U0KD49YeXh3O9Y4Rd6CkwKMJfwE64hI2ZFiLacxJimznZKCmr9qeNNRKmTwWd
w0e4DGyZ0+qZUMU+dynkhBNH/shqBGckfAWcQp8OG9GHcZ+ZcZhVF5Ns8HqfIgxiNPamY7/eskQ2
6pdN+6AMbUZxs/xjlHHrG4VhLGUpOTnXBDvhOpXlGLt17kt6ANqTD1vuongxnUqHZQDzFrC1BCh6
Bb2BkHTiHvpr1tWL3FmHMvFUaPZS0LLIlhdjV5O8hAjQTMdRGzLZBVZ9lIcxd9s0qH4TEl93P06u
adGzJHqkH9d0duwodUwmR3172wLBEQSjqBZLRTbLS5u2+4BPXh4epv7SGKVvNmGtZ0K2XdMLNsy9
bhEgkuy3oNQoJExFCVlRMaS3fdQpHQyOdTg+nr5cR0fthkeDJvmmvRDggpi+njHztzUMQGe2r2e2
p0Qo7KN9S3Be+1jquEX6oU4msM6ucWijKYdN9e0bTBtYop8txrlX2/GXvjeucIL9IM/+uRMag72u
PRCH3K28pqU6ASakpfFwG0LKVQqZw93WFquO/R0n/tjZ4j239yCZjCu+zipa6Sa/wwVt0v5MpHif
ImSaN3NBAP+rczAAsRKkt3MRDS+KPY1mrcBXJl4Z3fyPqYjaIty/8Xbk7AaWhjaedlr3im88I5b8
zvHTBOguzktpBM8dLhjCEFPF4xFflve8B8XZkfRSUeMDCrz8pBmPujCWuI19yjX2hhuY7cJn6aBi
EHkRjtQibFOXB1TJ9mrFuqd/8L5KgNSseB9TnlAN/yamRh4KbTHe4+aEV7UIJfHvtFqXQ7NrW0PP
Pi5iT3SK4O44cXmBWkn0qR9tUPESUqCSMzaRjHFb+YJWGXC+9jwYRbYH940d/Lwb53ZsSeioKMs+
jG06vaAW8Dfv75JjphTp3YPnp1MADTTHcvLDDkTKGn0Br1vLWx9NkDJFGREHKrOwYZ4YOONQI2KS
xWkWO+u9uv3nlejGvtl/0D6JytpP9yJGqNgZfhcoR7bJoCr0hgXViViY77M0L6EVRMCKjiHX+y6v
PR9/DvQkHo7g1atfMWqED5M0/GG78EQ6ItXtTMJS+51/fL3SXnkqrHPeLIU35Czly80IJYLlF5vT
vBMdhpBeg1bpwpdoPiLYJoL1W/IOhcLNvuDAZxGU+hTX3aU+sEEoiOdD6AgERtZrFXR0P4jY2RPX
lH9Gv2ZB35cLlZIXjAsgE60MRvqvD8o8EhNoFt+2yAeBhJTxeUT4LNjTOR+QNdGbaOPSzLn8lndM
VZyZhHuGS1qFN+cPW+AvAND29iaB8EvfwTh5OcAlYyp9CQoqi8vAZiKcYtSzxfLSCVP/9eUJ4bfh
JsGrN6iDwYNzh8lXGPXIY58mW7Gdw5l9SxMZU4aMioZEW02apBFtzD4rk0+2MiJs8zsXRrozgDbL
lBvRjTuavnlRcGQZ8O1mfSEa/CGgZUGqERIt3v3LVLTE3f6A5EFfm6Oy4kFookgGlhZI6hWHAzJR
ma0v3brqV+5xaiMI7FWXVbTrW3FYZ3QARs0TkKH5m/9ZsaeNrSjddJTnBSNG+IecscYxnzsvpOwQ
UpwapIZZ52CPgZMRjAonsFTsBEVqEpsa2NSQKL4UV/EFWOjiNBtKNBFZpiOLw0YDMSevN9KyhNiM
h6zhAmWnMkSl4DZu12pi5GxKMxPhf7YnRTUobtOXpeuI0tvfAizVnSZ+rrcawI5GkqRI2QAZt/kK
H7wA22Hr6WIAvieQDA4lkddRJw/AUNqMrhJoA8nm7Ng6z1h1ElRRqbnt2oArsNqXGht5/y7jW9la
ssmWur0ZG5PjGfvOWhmlPDHsb68dX+WYQBUjop4inAJ7rkCdBGHfjOfPu0R4JquNZ0f4uJmdgU8H
JS3yTWsLR3r+ncupMOZ1zC3DXAWgbUmefux9hYlB+VSAe1smH6FWfsVEEzA/tUQ4k2R12U8ualz8
KmLh7AZUj5RVxfMYK0WtUgc7ZBC0J7O4CoBXbZIaljcpf1/wIgP3WSSxlqP5FvoGlupAIP9Le3Yw
LqHIlybFX8sQr5bwmKCqc4vD4AtyQPPv1HPSB//V2RoXCj98FmkQUubgdQ7da0OyURzTz5j89qok
UuXqy6/ydyq4/IVsh+V/DwDfFwOsncrUxlXlHVQ2FuQSDSwAJsxJwaH3uIxGpL3xaqgDFTTkSKAw
zkVQiPFi1cwCiYoF+vO4PrQEmWIKifiPiiLHjBSQpIEpaWvgpiKAPcs0V4xtUPZ2joCKe1UYtrWM
j+Bllm2Lc6kulwLUNVh9Z8ko0cCS2HjqSfozaLv+lPJFhFhqja12qavptqAyARAcnukjOF+P6eNN
jR5+KH823zO+E/DE32rcrVrjx7xTb/S8whdspXK1afgCgLG4jd9G/K7us2FB8fBc62iOqfgG9fVC
HYknA5EFVHcboAXSXnIgEkJo8UnZBw4a6YSia3iZKHRvJxBmI3vFWnpG1jNYutFNscTDBPjFCvzM
HFbJlhnCqm7I1dxXiQjwhsM4FHOayqD22S0P8tfdwx5aEgLyFJtAWWfkJeOGMc9h612NGLZq+pP9
NOJtYeApTwRa6mWACGrpFg8SCQwOH1g5zEDgjsFqY2P1vgkRqSusN0QugMjpZ0vVTkplECnYGXbm
5rJ6rjEtzCODb/JdOykfi22xBJCBxOuGsTMe9lfCYxh+bXv1bNUHSZgxJeXfvJAaZocj11Fttqma
qCYN9F6JPdVNPpTyIJLewblwapsGLuSJNlpLdTbrlFr3NNiEWBV7rSJcqetqJnCQ0ZHpwFt2e4we
c/Zqowh655VjqbQtypgVy2iPbWU84c81rmfM6ECYHBCzWKCZ4MV5FBPc4SeejxEVuj9GAtWnpbW6
gGnztkgfl+vT8AnnJjgRKPXxEAR0/m7pKEjubJlgUnm/vMzznCBOVGzW2gnEbg/yRBklYuljqzgz
lxcvyy8kmLmIbKAi0vVyPan8hjL0xrfw8G5at9vHKLDv7SE0npkfvOWzkUsiy2wlgo0YrQaLmsLc
/zX7DI31xazNBTVihViomHspcOShBA3PHXDXGLMf6qQ0jJATNVQwsUpW/OXppOvjfjPHAK2uePna
opo/yqDnMpzx3itgMUlzdu+AtK4Eh40b4hQKrhBLeyJbNDCZIZE3sZ1RSZg+W7daeOTycJIbp+T4
cda2Oq/w0fslEFJcFoTkku7yoQPz1tDWn0F/EwfZfCbWmp5cFvmBEfyyNR6+XJRR82gU1+mLa1tM
mpb406ezUvSTckr3WyiaxdtXOZgAyLDa9axQZS58A+aKqEyQgw7hDE0Lu7j3Fst6EFdMGNA48aHq
PmEOGSIlLUd19OQBr3lSNWzmatkn1RN16qGQ3dq3jvgDQ217LOGB0BQwuX+PewshqgZRPpcAPOZX
n0FBTNnpBmQMXvY4vhreLE1ovHbl2ETPej1qQpUX1svEIkB6qLX4EfcDC7a9K956AMAZK29gveOj
f1yTGzlUV2JZXo0Cr3xGL+JHB6JRwWYTwD7rFJ6/RbfK0LX0npLxQKUtMBvHBCzOktpfHHxkcvWZ
zkwMXh0PUcOQdWjctSVK9kwDTrE1+r7PlMWQqRG0a5gYL/oYeWfqYxL0wlvlvCpI29V+s6SNaSTX
vl+W31VbqQlruroumTHlqV85Zqg+feP/bMQVftsfqkDHQp/CDIsHBANY19P2lwAys2v+QTt7Xfl6
Nno8RnN1MAJzcxg0/uuDBPr3wgf62NuSL/toNCGyAYmlOttDG7t7/qC6SIEHEHCd+F+qtorI3LTM
uVHa3XQoFf7fsuGjgxXoalaqeVmDzN/XEJRWSRctS0AZbBNjqPc2Swc9shH2pQhm6uCcaS82zIoR
XLhW/OuMMBo1axdUbmNveP755Gww1oEUApKv7E13+ZNU4xb7uzvK2Ho2P5apmX6C4/n9VW3Y81+P
o8EhiGXaNtytOiVstVy/kwLkjUBTmaQELcseHS/VIJThJ0oANxflXQH/YbdOQXbvmEScUHQt52n3
kq+U9w++jEGdQh7MiEn3DFmPGOIchOLnwWDm15jbkNNnVLoS/AQhaqB8WOi3FCuyl0FYFR6RlYVB
oIUBtBi9cYmFDAzdoANPAOdG3etYUtMwappfwL1iSCiSkot0X1jfL8nAe7hSSe0VdYETphO/dSwq
EH7jVb7mQYmfSxPDs/YeK3G+xzdCNfru5MWB6BgVTLWj0kTkjrDOEtKNT2k0cRqfPeSmxq5t+Hcj
fwts8uZ6m2/E3SOpTnZXQJc8ydPO0KcJ7TO4uysz1SdkvJhjOxz3RytlFlOgp4xMYa9eVMM38r/L
VAylT3KQkPWaLELi7Lx0bww/pWjhVJuixIsQnI5NNhn0oL+XIWdLpcBGd3l9j0SZACCkAgD7yDDC
NLW21/qu4OjRPtvUBEPIG+Kpfch9/hT3LuKbTM9p32vtQpecneVbWDvQvN/9/D7N9jqD0FxCbq/x
1ErAHLw9wd4bdqoTCO5RemuKnvS8I++LjJDc3XHAQ/YNTzxa0la7YDpX+zph49L9iJGqJfmEJRC1
2h5TUUJv1ZHl24Y4w7XbFx55uaWWTL/xH+xlvF7iO1b/lO0lpPJydT24mpwDODGoD1a9QhmzLbGT
9yMf9Lv4dHAiFSAHoP2g3tEbAFKmLUDdjzLLJwMlZC9zrXs5Zrrbi4YkU6rk9RcHDskz76l4r9ie
YqgbI5iO8WMBhQCE9zRhsriQ+M0VjOcHchXx+1FfUhJRgbcjKjurwYlyChWebXiBvazn630xz6vy
K0+57SfZ7pAYWzesOxXFyfcbGtWZfRmP2se6ZDfTzV5jlgt+DWX9/ydrcBHV5+EV2a5eb0CVB89D
IS/FIyQg+tr7vOgwp0HhKf0mcVEQ7Ycd1xzaR4ohgWgz8i1tbO46E1e0zDGjos5DSjR5yQerrwfe
pwP4c3nAqKwt1QURhkmhJlJ9Qtd9eFbqnkou+DD3Q+rSruLn/CnROAU7MBNjs4VXHoeKOUDbHkkw
P9fI6EvMeKXPIEXo5XadIgcJmbFbhTqspOskXvoSlMybDVHm5Se3bXZkXsMEUEpsHVJ53I8ft+u+
0Go8iSQgrpiE/5Voi8XeLVAj288CL5J72txuP1/uxx3HMxnmhk488LiXetyHsxYWOB0ojssAqQSa
6SvS6P7zV2O/bB6YHGLaXvtikx5QF91TKNrb1oWiDYmvNjdwWnfHraHdBStn/anhxjH/3GiSNDTi
coS9gSGI7zCebdlVDDxuxVf8qxr0uLB4XWAX04kiAsGOuC8+wcF/+WkNNPQ5/W6jtP44EjQQrkj/
5/mBoP4KqTUh2kZ7tif+BF6tW8cm7grLVeKbrTvWnjGREONBKybmuowKR5nHRpfOF8sQaOxNmXiS
YPsmL2BXaO/5AsoVI+VY418d3iTDY5sRNS8Oi58IGj/8hK7m335oM6nlRZvk8BTohLtJfpXSk28M
chh+M9SLRvXy8C2kw8jTj41Q2Z0/089+d6N6YIHWEIVAznCOT1Vg3di9fIXApMGxTWGh1iYKuVcu
j1MpxQ5uCBowLCtsD9J+dXheRoYpWp4rjSgnG8L82GfB68rZQPgG75JvdiZHzcv0O3TAIlPHMhhB
PUS0zrIDGBkeKO+JuBSJcNcTLxquxlFdQd+0IWhSCGUVe6qmLs7d7Pqo4pZFHci5S80+b7lwot1u
GSmBC5Bsgcc88t5urjAOQJqwBIuG+fCa2LF6CoesEYCSPCpASGa1JyDPnZc+rbmCO613KAgFKEJs
mnvwrykWANwtQeVqDcP0BAbRx2oKVeR7DAMMXveH/IkuOuROl2NuVwjXF3kusRWJ+f/55OAexgRc
hvTUmF21JDc65YpnMx0nHOFuYRH9AQmpJSzTgWLTTEoYAbLQ3eV5rvISC0C0QtDj+i/yxo72qLUb
DWePjyUEFzMw6L+0AZrJifuM+ONeoewFc4KTO0dOvO7YOHcOA91XqsZUz55Pp9S3W0wZeQ8m/+Eg
YH2u8wfJmv4IZ4poYjeIkuXuAEMyR+j5MIMMVJjhi7cq2rC6WtyJQL/MvG0bGGLCXaRkRlYN2LTE
cADxUA4lDmkahKBg4OVCWCb2F9K7EnT1qB74BeMlmQiiXHu6+nI7E6dDsNwtTAGmzJtfCn611o7s
iz4XcqReuN5areabVj3Iex9O58xbzacf3Bcit2+H2+MWeZTyePvHT8kCNf/CtWeL1/8AwRs9w4EA
NXwAQVPxzAuRm3WQ8lM1QmlkT33UxVIAHvJk5cpTuLwfBfLbE4RUeOIV56HWyQEsroNeVrdSmoCP
yscytkjwRhTEzDx/QnBP8xbgzeB7+eJTBypRO0Xid26DOvQrWtn8jroJp1l7Luv5BZMjx8/t1BYY
lZzcxxbN0zWxv0eBAp3fmK6+zkePL1afAKD3SSklhWhjUrEYHbdFPsYVBfMMtUsenvhkhUUDSSIr
kj8BiURvANtlCORdgTI6oHkR5E7dQd2YHw4rXi8sENtTr3sp/vezk0I0GZARyquD8xnYQ78SaiHT
eXvCU56c3Ta+e/jocDQ4nWqG+kXLbRAzb/P633cUijNoYtumK7X3DA8udamyP7JpwlHsBQP+WUJV
xqBH9OjJx7N/NWIyYAxkHwB7dSxlHtZibxAtZjS2ehXKcF4Gz1bJoPJoq9yyg/thQalE2NMUX2DY
Hk9QWz0lcsDQbH28kxEgDh5TYxeq6a9G7bsUq3GR3+NnjC69N8z72on/5m/h6UNw4M035lH5n41L
5BUUSJc+6QljERavCcR1kEOrF+E5Cz91E/IyoY8Oa5l6QcXcpgkaIe+Yiqd2y9oL4HDrZI/Jp9fz
CqU2HzFIU7lqYBZAvSbh7aakmFDHMTugMI4A5RW+W+RmvN1xGI0tH0kpPlvK68eneGW4onr1iDkH
egFNsX2ge4SYRD/x/1TCb9xKAWjonyu/KgCWzZJoisJuS6/ZvRX5g445QHdmpUV8RYo/7ZJV9KRl
6pBh3Fe7wjYl/ybsVLf711V+WJ0SbGvga7OVIIspU2CeQ2ZXNF+we5B2hF9UNWwnwWLxL+qCd7Ll
Kfu1SWUjTYlAmvBQ34JeqHaAyKESAD/dbeFvQo8bEDntDNxLbWIyfU/euM3qqRmvjCPxt4QOKMdS
VeVomN6cw9KXVogUyfUdiuqnLDYjzT6XtUaoZWJ5fJ7bG74W0LhbC0BAjFRw4WUBA+9j2K5Cm4Us
k8pEKcc8DDu3JjK7CkBFUZ01vrM7UF6zxWQ0BKtyJPuC7DYZHmrSr1z7/dYrz98vHsmLXAkNNUjW
0EU5eHNZuBoZ/WfB3NdaCboNwV84Dsy3YrrpzToKq9ohhdgfjHQpP9YvfbMZbZxNCySQ4zk9pzM8
5dehG2pn88fo9jwYnuHfP+yDPflWiaANp+wunlD6HV4+Hd2ZXJ1eY7UFNmsQeZKX6UwJR4jhtM4l
GwZCaD/uciZEaWltH91URg16VTWZnJtOmezWGMA85Crum2Eyvfga9y8/rW8OMTujkBKZakOMbnk6
LiVieNFZ0hnuv8PE87UglWWRjiOmYrIw8jboIIi//e17odbuVi229JX849Sb76BfEg/R4jO+2vu0
/mjit89q7/5f3Zrlm5ckkEl7ZepZHSV+B+sPc38UmtqkR3hsU5pMSVDi9RPfVhyr43X8fy9/BaH7
iTQSaQFTCOd/T9zszN6zVpuQz103fORcU4fsD2+NIvz5C1UrxhRmjlkbiMlyItPZWBlUz7lke8fF
KjaQa7HavjNZfhbWqytcSdEnLJB9ZE6V68bHCIOm3SakFwDW4f2D4lYzolW97VeiiSOSHHFf7Zcu
FI1NzdB0LNB6OimGVeRaddvhlAUlfI5JJ/muqV6azGEVikhp5mufRxfnEVLM2+IMKnZyw3BkkhaE
dsae19s+3ThORQVJk3ui+WGoYS8eqrjo/e1pr1tCZ2EvnaFThnslW8ZthoCUCrY4H4V2L950RrHP
pQWTLW53PQbuDVkCE32KOELDsTnuYVzw1aJkdKXahZJaO4lVhai4HAlOeFhwZ05lxNjyZlLaLyX6
bF3i5SHu6P6Dm8gFcWOnMP8mDAWg0GuDRfYjVBINRq5y2H+9seK8nqbrhzPSe7tZVT3N2sfQWzia
He8IlshTWfNBtsAjeh9exkz94hlrPfnZs76Wpe49NEQ8VqBiVyY0hQAp+FCuGADz2ROU353mXNll
8ZArv/9k6qJAKf/rjEIeET594OT7S/rv6foXWiw75MlsDaoZYCWvcwWpL1NmT4SSVkaIEwXktaVa
2h8qHrDA3L292Z6LxCAG3EjWWW9YjwxmV570S1oFxUQjZM8g2OqugZIiyjfOi8BnE79QNWNM9LaZ
UFtYbdf1xwIVfg4aJC8t0PDDMZoNIpRk4INxkD0x2q7reYFglOsssql/Pwyk1xMwqHmZWPyT6j0H
Tppx+4rjQ0Vd0X+pexqbVV1drs/gNTZ8HZcacrqNTWvv8TQ3PTiovmxZ8e6qg2iY5LAYDMi9mH+v
+fizsef/yQaOASLpVAE/an828JiCYVtn5Vy6xwaFHZ2ESMBztZ/S2WBcnBMmJOU+gRG7IWtT1w/w
ixfXrF8LhB5GhN15RB5IVfMVUBDYYL2GcUDKsGQ2IVXxL7tBGmlnRlt+RQdRV8VEMDO+9O9qyh4I
S7auf8PuiEABcdVNwe328rJdGStlCL2xsr4c97wCh87oTFR8r6JXBBzzw5ZSFg8NV5xPOu/0OUDL
oIMofSaVIkTBUN6ii7Hz6IXQEFrFZscAWDn0Cx5VnAMSEcFSND+vgIwIk3s/JFAMq91eH5jQetXO
W0Ydrbd24Etuxoi6Jee6ydNLVhJ3qpNAWQRRRf/O0s4M6KrLKbCOiCn1698wvQymg4Eo+8JuOYct
pXfKlTIdtjM4r9NpuIgyXOIEoEGWowWgegs8bk/3bcV+5bgey6Ah+453zm5zGAmaOFRE9ZhbZwhm
QGcoZuBnFtU9LaAn8n5pk4zpDEnaN6QFh7jQVObzyyCE4EclFRyCaUfaZCgnps87e8uWL2xuoQnc
qvFiPhNOaX9AVHzd1l2jzR0Cs9UXardT0AofEiEjPeQ2EYei47AJFamM4PFwxY8LB6IYdsMFzhmC
SGuJ0KcKdDb9aoGu4zsALeGLvnbMB7qnJcUt7VZUHS2DuhAiIm1mg9HjMO0Hfq4Ya/HMNvDawc/x
C2aOK1o3iU1hTaulJeEmxdKRWqmHiiIoCD08Pu1zkD5qY3P9J5agogB0068tJivp2nJem+F/lnKA
R+6uRdZRQuaBwwV4TLJIeEnzFmsNklcrecpI6oXvshzGoTqhksxtUOcTWMQ18VUFBIP9+l3izbDa
HPxE7tt9XM3hk1LH5+nm3YRqrU3Adu7cTU/hos3tWITs/al3n5wRN8vLCPUNeYsX5sbcLI8g5Y6j
979lQ8uv0vcIkvcdnmBT6xECpgXBtifulmIaPHBSVpLuNl+Wz7oHbOrbehabQHlaYhzM0cgC1Kb0
YasC6iLoxSc5GpIU/gH5l1XtT35hSpfw7o97JlvJg26caaylnzobUOUnJhblGH3i0j4FcRLX5tlU
5UMupDdlqqinWlNcNYE4mETi/7R7dQBzJElED+LDNi6WJttUrDMSWfUnMufVubGQ3V+lqLQW6umC
/P0WMz+tBwJjjCG5xIvUr3B8ibVHLmARTVMa0WjtCqHaSRdKzcNoLpWNBHUqOjSLRKchEwdsfq3x
jVJTxx4OjtGdg1vFWRVJW+R0hy5E1w8naYoEDIT5TbkM8V+mg/uKYuEaKuZsXnYRv582MAPrvk74
VsYpXHhD2hcs1t1jFaHziqpblX53mMDj7S6H444vEA+9wwrca0Bpt9nqNYm5F6el0k4Fo5whkJ5E
oEjRNtL8c3h+Vx6fO3oA8dGqsnm6MDwiVdKCn0QfceZqLfmvnMcgBo50Evxoe06h3vbU0r6i4Yyh
1JYgjD1gyV/9pJ9oNNENWjj0jG+RUMtar2sHAsHKxUlHIIKDOkwi3ltLZVjabRx8Ee7ipT89YYCU
g+NsL6bui9V9gwhYT10FwfL+nE9EFvUcB1wvjucqnDLiY+0Da1JHLihFHf9kQdhasjHIjYpchm7I
JbSkHUFAHalT77vGiqeS4fTsum2sWwzzYDYQ9KmYkKdmn/awUHo4nSD4gMXV7+TTuAUZ2GGdKaGy
Bnj2IJ85mxk3GOo/0B15b2p+vZYKuv424w+PJtCX9cI2ncVveKaS3ZXObp2rRmH7ptuQBSh3ITsC
ZQ6t3peZGjWzjCPRTpwbJ25fenYMn/UbeS6cAutkvCb7eK+Bx8en5At8NlpJYs/JFf+Fvjeo4OtU
n2UOrn8QxgH+2I+GCgh9urs3/R6jbWN14lmb6/Kn9QxDPqi1RxPceduq0pgP6IuKTHQaBBiZzics
bJsU+5W7fgRVj8gqiRyfFo1K9iEIrBqQT25NmaPU1WocijRVIQo/M4W9yJBA1UYG0OxOvtCh6qfR
oynOIcdEq14Di3pCO1SveK5PsWk78Xn22TH3eilcj/7ZPkRYSN3teA2oRgNrhvj0lMkQZNabgl2U
dTgM3Ou21HiYJ3QvKgKuIwMVtWpHeyjOx1iQPzo0Q76QNwQmBp9bBSLHhbQvAQCwRZr35Kw0gc9d
e/XgvFLeIn/drYCIROzK0G2TGAGSgplYeoshcGasF2y4VaCtyLdbMMIrvkgPB1368K9dfUDzu94y
qw//Nu730Dy28sM0srAB6LRbWkAj7pULMg8jjivvC+biZbZ9aD8CoulDy+zUVy/3r2dbtQd5SZRn
OmKUzxp5uDfSQZe6pJfnoNkl/WhhLohM31a0ci8EtzwRia9SauQYP9ILFqRH6Hw9Vo210qZqRXLC
N26roGl8xs0VkaL4sJ7wFXq4//8fMgC1DOKHgI0fHy6esks7dBzVpFCPDk5Fx6AODv1JZ9/btHHU
2pYHF1003elylhwFVQATTg0Jtf/2wMHFPJdRwKApAdvzxzHWg+OywGvFgzSpiuONVxEmEUyzgzyr
lRm9bvwnvnOwA1rDC+4XMd/0DZEzrHLe4oplGTqgGMA4LRYPC1YgH1QYbTj/hOB/+AlUPfcH1xHE
SYrBErV4adxyIABPuL66Z7GmLdzVQ5T1DVA7FvRiLL3lk5QpJCqLEiVyGOr1bd+ufULFIrZy7WzL
eoCpAnJjJzHRRvd65Xb0kEsEd2VbRv8KPeigiRbVuXufq+6h7BMT3+zqdtu/AwukPoMCT5deFkG0
lqwC0JfGEaaWksy7nkVw2t9W40MwsGzW6jxNdR3CxLjuiXW1HfaFTpfrM1L0hnZ/pMB3q/tpH+0I
iTV0WGnVv2rs+xqc87FnTtzI9evjLXzUeMdMXREpgoLxwKubqVgOwunulOpc8cHenFDcGCYb5wHy
eMJiU5/tjo4TRm8XGn7KbKLFpJhSyRSZKSRlJjC+1DTIo0eZMR4Jd+K+L35zNXzhFpE4HcIlOJ1T
YuevJ5KrPyjRpkcnK4cF0cLWcFPBZZhvEAR69aeBtWeouM13VAxFPfHVOZ9IGbrRSQZOnLZZwtR7
G+vWbWU5Cdu3kNGUXMw57fWXHJi9VsTfJsJBHs8KzucasuPgOzQNnvkZbkyhO3l6cqUKgzl96VAM
VAT8/DLKpkC0C00EftwZwiWoDJeM4qCz3c+u7L3xLfubuKT7FrllYwuCnNrx387tacs5QQeW8GAX
867RrAr3oeeKhpS39IN5wB0/C1mczyU0uG9sVXNHZQLPpLItZ0Ke2pNRfZ5GSL4aAwKynNEjKIAO
dR3dR6TwuDWG2uAIQAjlWdDeHweDfyIgoQHMZVLpdx5+ZIeS28N6MxXoQAbcJ1VT8prKretOho0m
i48WhQM3WoEDejLpQ018stQS1D9CTNNtQB0zyBrm72mLKjbEIdGFl/V2Bs0vvcBSwGMoJZcE2uZh
ZakZYqXUpvj7RNt2631L9dtFvOssCzbmVuJcZH3GtcTOlvvZbVLdbBgWaax5yY/YUPxJQhpg9fw2
19xg90lLqwPDmJBIEnwjQgaCsgNs2Z/Vh7Fq4GXPFEM4vWARzVxXd+Clcrj6B23AuSFNJ10SR6DQ
DDjQjDsbRtHDeTy3miFxVrjVXa6tnKLH9zcNvZ65pK3dP0u2YppBJcjHbPr0lz9TogTcY9wywENC
6tXvQLa2t2E4TNLiNArH8O9eIUbBFaW5OMNKjuo1PZ0u7h2deuJsIaKov06f9pCJFtpMcwzRWI1h
LvMcSMMXyoHPBwC18PMydeZK6pZp6QLUbLKwxD8HsTcoDWAqPV03pvf8kUmieEMXjKl+nJxJAb/r
8mFY9EEuzKQfYeIDuwBzog88ASEWymLNJPU9wBY5Elyv9r3P+n9nRTNunphQRA7aYi6+SlvxEL2w
lJl7VlV9+zP1kFhBoT3uQg4XEy7NdTtfIz0fr223fBVMrhoXAfylHO7wGnGRKtKDvr92xMlkV7JI
PDF1RhF12SqZaV8Us9UJQNCSDPHrvqBs3QoHruRGNHhuj4NGbz7kcZdtxYfv0tzYNyDN3s50K6X/
tELbkvdsBLkGl2c+3eOMMXym4OQ/DMKvYmu3A185qvNhPhq3i5kkxYm3yNVlkQzSGD/gyL5UZTA8
yD5EuZOv5sThzwkKvSqGo55HC9/WpYmjwk9YzARC8aktvbK5QZINmCKMJLA7yIsDSKyqR80bGNcb
OE5PWo8xQ9933ZmmDcLI9cfoDLKH/XAYo01+CVuE2lNgRuVT/X00I1WRXJ00Ms8KQ6c5R2bk/PIA
5NPpwPj2QiuOGYIc+F3SVuAQ2TyeKzF8MOYkTiVK3R2T0pffaLXDHy4uA0VRh2QsJqNICyTvGTUQ
9lLfRGsWxVopc6RQCnFfNQ7pYW1CQg+PYt3gH/1Rt2+SgJbkkpSfnliBrnKEgQIbwMBMhqNHIEMW
wOjO8v1CMk1K4AVdTYTJmJBiTgsi76XA/kYQzmPRPxV0cwL8fm64ZEXO1OYGQVtfSNJBvM3Wj8hs
5v43KwDeXJ7B43j6eJHG+A/n90rsnrqLMTeJ0r/58IWDL/F2pDeoqArCtwVEig4QQ1v8gjteW9XD
Cz0DJ4DTTEbLxn2oGFow+GIXnGXmIEogEqs1PHhRghivWe8J4U7QOu8yMTYt18/OMWEcZbZ6Tgno
zR7WkCK+kvJ/n+m51NYPRjG3pXascPdllgv1ai1mrO0ZY88VWPsmzMOsOu07HSpFvD7Ta3LeUDgB
f1VvRo576qZo4HhS3bOpvgfJS5mryu390KFXVbX5MypnqoqFiG10KzPPR+0rMexdnCE3qEckf/3y
UJ9zTjQsz1HMi6a4V2TWEPwAuYvz3bxfbuK0zTaBXRlgjx/9rEapeWoLQmNwyNku66/MdpDfjZ7G
64pyYcXgI47TZt8GO3Y/X0a2SOXr8cDlOFp1TTQpfA/hsH8ASXd/tUFe4668VMVPYU9lt4FY8XZ7
wV++oG4Z9DPRoSo2a49peFz+JTxXnyQX5sRrXAdC6fOs3znQm4MuvKpJ6JSSLW42r3IihMFjERhw
YbogZrMZOZgujZceAAypI0f0BD9ZHbaqmtEGpdBjIgk6ObjTbJj9Xdi6UQo9kVMm8p7lcfa/y/S0
jX6xOAOfmKjxuDj4XgxIQ988lXomqynqmj/U/CLFYyT2mhUwE2GS24/PJESIR2qw1ljp6vyD6HhR
tf6KyTTCoq+cklPvlqDyewfKesuMpb/7ljL0Ox0OBvnMrAzlMVIk3MTR4HTATh4L5A97gTq0aF89
qUbDAUuSx1DXFR+xvgJEBnVxYG2ZbQcn5352WsyKZZHAJoOlH63cmYlrr/DXnXZ8Xvsjr7iEILAr
jW9ZqlBAXPKSFmnsFFVkdovNGEg8TiDbmAmBngZ6kICW3AosRJyhnjh1HM5RRQGPEwJ9U2GHHQRo
WATkuwDt/BCI4JusC4jlqMCWlPb7kVTXJZl7vFssJGmfPSc8swp7vwv/mAmBSrOY/i1DJxz5gXiw
C1EodBvl+lYmOnbovXc59I/Jizy2+LN+i51mNtJi8oUaoq1EQhOnct28ATTiJW4K1UGyM2ffv+d9
s4vb6RTTF8005nVuHd9sNacXCubRzbllTrTCyT19OT1/gLfX2HxMLbAuK3+nOupxUlpMcf8DzaH7
NdGb/q0aEzz/QvXFct0w6eJmnCETR7HE3CVyLI1wcGYLeazCQskdvdUgP2RxDAZJyod2jh41YVPm
pKYq0CLExxuAQSl+9o26GYJLIwSOhHlTVhnircbu+ny99t7V6MpstSSskpkvsMkd8/Bsxc0jUuqw
0NTolbXiPNTpngSX34j98nND2zDttrZCI+eDtmbQnhPwndgxIYj5dAbJB1TehuIPa5N+Bjc7flDJ
nZWgycdrlFCL9Mm2HpQ9CKiJI5hjU1rmtPVvKgbu+ezpoVgIAv7hI1D7ZylPZU8WHRlaeemuM7a5
jJ3L+qF9va4QyWc2JhBjQSDSlLr33z4eVgZXn4NausuJFwlLUgjf2IpIFSzcQcqDy5cw9QTSpMyN
wOiuh43jsMBp3lPxp6Dmt/Kr7Xlc2TSjorzoamGlRuBWtg1Lp1C7LSuLQw5z8U5TD7MI0wTi5ElV
uyZjNmcbyH5EAZqb+yxoq44ks/pBUgUtP+TzwtjsO8DEKxBQF87Gg4mec2VTTkqJDCXcEAsHDVj8
GnBkgTU2zD0UkdkhySB/ueP/W+ADUJtrrIiFBUlmMgo3dkqXDtYaKHalsg8jodDD8t5t37oEl0fA
Li5ba1UDPFaaZol1lcHQuftjM7F1rPxZN0J26EDQH8QyFjgRKMWPtdr83Q+MlNQHCNlFlM9Mpede
qg+Yc9GumnI5v0U+VnlmyClibf7H67RjLgmjh7ege8aW5Z7Pl/+WTAtkT2Li6LtAYuLD68wHJK/B
I/HCvAoLJC7XBFb3PRVoENaJcIeBacjzp4W/e8T7AbeAv0VNEBfUUBLF9wwwgrI4aEosmdHzfKWD
c8ww/3VAFh+BUKtIxF6rQlDVMt4zqKPk2UnWcBIT2R38/hn5U76yzPv12ws2zxfC1CB8NlSlVyiv
cGRat4Itj7cxkd1hMIWKMokHUEar/X4hxK5rw4v0s7QGr3HlYWxD6Ts/FSl1GrXVY/8YQRHlP8+s
ezxllrBaO4Mf2K7fWEzxuFmC0t2MPl38WwFKYUhPDHdPkVIzTGCtlJB2kdoFSbhissw2OlXNgCxM
KJv2wj02b4HjSpqU+A6jFMEdETaoivoBOHttCrscRJTT3TpC1xXQJG7rm6ghvnOJJAndhefbsONN
mg/T+sqqukwGT8Jk2z2sM8q6I4eckQBAiM6FXOiWpLvrPGOkpqnVZUwY8WZ7oxollI/9S5DH+dPF
M0kiUnw9D4tq5mjpPkXJtvlryoyOD3o+A/pWvRdFYmB6oJJKHsRLtIBvzQgTPucf0YYqctgyYxgy
QZu9m0VyHUw8OG/MvpKK6QTiW7uPMr/+d1F9e5LZK0E8NOQ6Y3aN6OGqrH/eqsCW85fLUSrhQNdB
Ij4FtF/AuAWbGOzMtDmhA1ug5WqFRJV+VkebZetcBWYt46gKaiKLKAigVmUryfWGg6XaSeFDhz4H
5VRx4pIX8wvkkOk5y1m9bo7cWvCD+4Hvuiyg518du58bq1f8TJBWU7HX5kCVptVKBeQFyUQO1fi7
PxKVR2Qjg8q5NIMuHvhJsD4BjpaYpdiUaWHXEy6V5oFHfCNz/5097e9PPhn+D28lwIjcf2RI+tXa
RB6XFjiMtQngQith6xb9a8cR4slotTXFOjfn4ukO7q63dHTbdKdkqUzGi3VoUF3xHavbT1D9s4QU
Jz0Vs8aGER+mpwSK+/otPVUnN7aXIVOR8EKovRthMvXthjrgrk+pAGUMfrojMPG2jIBLywbILNFd
CSerqRWGU4F3gELdgJKE5/tSjpzgcnBLsKXxo1GEpIV4Ww/IDudc76JJBtk5jWRAOeE+6OtJI+0m
9r60YtF8b6ZA8w5m7D4fGNek6GTPC1QIOaXNlJ58TqWyhPXeigHGnd1VMOvQ0gUvj2TT67nJh90C
wKcQkNeDReba44s7EgnQGZmuK6W+ApuP+KE2sMssj7NT/J7nGevhgMBbqrH88zz+0d5QCrqTupIY
EUSE+ZGnmZwP+2hYm2htCzJ89rlggAgrk6efLEQUVfiVXYGMpKGhoQk/6TT0XeLWjR8ynjb9TNUS
hOWkBKs+X8EMgaTJqbElb1GHQpMDdKwxcjCDj56oHd0AJtFj18U7hQ0VbSagfGQUGlev5i0YHCqq
fAzYamaIkw1QVzL5/J7ul9sST75J+y8vrl0YkUzZy2/hfsZeDHNlMGr/V1J8p4g+F3XxOc5a4gwe
s5lr0p30H2Us1PpX7pP33olDmF5awKlo17i5xiISYXlqeokn7BnCrFbS4acpu1p42tEgO+vn2M5w
nVJbbUPNnk+ZVyn2lzkTpT2iSrZzLjxRKg5gOcJtTg+k5bm2VuS2xZ/sjI4hbPU8+634IoAWyDKf
x3Tzt0Hjbo3rAc1xtrQGnMxtkCoWTRJ2VvhTRzGKTGnQt6XYsRyXlmkyQITgQ0BdeCWhuXAsGeZa
9PqPjm2nbbsmkvdDqtzGWkk9eq+fDiJnP0ym693U8Ae7Cgr9WgT1+6WuPBXLuf67cxpbZaMiU7Y1
cKK4oFbKJJlO1bOEWMS9H1S+BvXV38jGubXnDDSUplI25vcQmj2/v+gqvHV10Ybsmo4IRrEQuOvr
PElIetgf87Tp8ZLG+p8HKXYj5XPWKWx/DWZBeYvDSQffQkxh5DwCQ21o259XwtJC/NLB9nYbmb/T
XXX4w+2i0Kut/+b+cjZZdMlASejYVSF5mFPD9duCcyQ1Gs1bsrRH8HP4eaV9fu7BzFMmclXD1bJK
7ubmYJ4pQ2k6e9yihE1f9ZHVDwQ5IOAJYOtVLqM7Y+FNERGlkw9v9UiRraxj/xdqy0UCyKajFyJe
LrHMnAED3BgRq8X2CTjdNwC+VCxOpVv+FPLTd7xM2n/js03Z2U7MFANIulkPXgG0fattlsaF+JUs
9kfkKfUrfQXSXa1cPRxWecltqzifL0le0RMxxNLEDMDPu3+g/xT5tJshqgPkz2Q60Rp/5ZWFUC5x
yoEh2ytR1cVzKGH8qi8f6WhVxg1QjoXVRukwC1SzxZYNE4Sohx/lJN6MX4HUP6L9fLVkqq6aOHfb
W3lcVe18KSG7fDAD3GfLIQ4MzeLM+7PaflZiBgsaDo3OwZVePaBtAGPe0qEBljuehqWnlt7EwZqK
IYkCNK++eG9vygjVZE4KFVqhn0l0CpJxDS7+V70Fy0YBGj/V4uQ9eK0j7h8v8TTaSFvdlkfmIRBC
1ozFrgFAXPwj9rfHtJUSe++JX5vxhJWMr5q4fobIENMsJTv9n2FXusMmLx1QxsPjHsDTztQJBhm9
Pd4xtQL7ErwsXpBNl6PvvYQimQhafPMDvHwKItFXNANfEdlgPBWqblW/DtdkjgSGqSvz7ATsW+FS
7GlPOw8fbNtFpp228bR2T2IW+qcEI4y25i+6HRBR1YqVNPu2oioxc2EXZL/r0WEexlHOb7WkOtVc
fWEaGaohM1Qvte8fr8m9w17evss1TxGlDMcGzQ0YCLG+wshFlJOo2Jg7b5g2lOeRcfiQUQO0Y1Hp
V+5hvF6Oi7V4Tgw35HQy4nFAQXP8mlxQaOdLgCShwaMOHMCUI0ovYaH5oB+YIlYg7kxdYIXhKT8Y
669dg0JZV2m4e7gcKwSYi3Qx+GQoVDDawWKNxlAs/SOFYgvhkmf3l3or/mR0Ogc3DNQDIIUzd6th
m63LA8M2zMiI71cbeQFvE4kk48ckkUa85UdQUr67gBDFXn7v5dbJoq3jkHiLizIXtUtS8U32+jKf
FTcesSBDmU1/B6/HdTkZ5owDzQPLHTFWDJhNFRo6oF7aTqM/tV4oQKGc8GQj7AzptjdM3ewOb7lc
+h6Qd25E6Mk9T/EA2CODdgKrqEs8oF8DjGFTjO9hHnAbxICBzgdVyHI44itlXaQZoJtjYMmSniSQ
OaYicGLzRq0fF6OtqkSt8r9aifHHFbY+XAHodSRHV6EnN9vK1Oo9XEf8pOaMUpZqPw1iJ4ODRQEM
bMVjIMwKLKOnUukXtNVPd95JkQA4+v7hhN6cKqd9ToZEDKyF2w8DcE50gKU6C7bue153qQaoaM1V
hhFBvo0utJ09MKUSKL2lyLKpBBL/gTi9iABDMMpU+xu3LUwo7YiEI0BcqKYmhqG1aoJkVtMg85Xr
hDExRMdYFSdMWnY4Ds5ZI9auUCIxeNQfy7lhCSlKr8WWEhRRUlPUKnV0vEMsJuqMKQUu1fg6WuHX
iAvqCSzNjo/Hahc5Cf1zshBbkmEU06fEgqQA04WGyG86Br5PSKbdslJ+IYzu6cQUGY7E77XxG6ph
2euRoNIFVrpwC2ddtVfm6H+JGURQz6TI95jg9+vqlTtlWc4r+6jPI/8b262ueQjI7ZRC2RMXXGEC
MP8iwWsRO0oz3chSPCZzNLq8T4Zsi4QjYHUhFRNqeBn7qjHgSgfRH6CK6BpYiPdX4cRMdWlYQcmP
Efyo8ZUR2dkC8KW6X5cI/kT/t7SBzE3sPG0uvtxveOZSKB/cK34REqLjbAMF3pxd5w7bTbe+oROi
BIzYn+DGhbThap60YSBCO27XrdYWVWurqfN9VffLz3ZsNwSw8hPGmpDe30TR8QYtYoGUhwjI9vnJ
0y6nwcfWd3h+LuT3S7gr+199hV95xMto6twaHgpw6gNNXgz53T0LgT63gSm7TdvpNNUdMCMOS/Dq
oBVY5Ol8wlAL7w7FIEk6RD1N7MlxJa+hoR1W5UvsxZYeGpo0rwV9wc6/WVJa8MdDSymd+ZkqKRWa
S1KRiemlckbF5ekkNtdwVo2ljtCLZFRX/e9plJKFo6UslgoDcUD9xKl7oMQl3zSKxRnppe3mYtW2
tbzflj3GzMpzBEnzAyXj9VRMDZ3RG+jayh0UUD5uZulN+YqanYZ8IMEVg2kqrpkxzG2z38an7nY7
jecDtgBPGUx9MS0WfP8zyVMy5AVQIUv1MJH38IK9T7mxFyRvVv16VC02zc5k2/tI2quYDcGiIbzR
3PioTlNSHZUZb+s9MLTPmrPSwcEUSvlF8sqjOlV0U895Dcgfa7HTcEmM+wFNIatSmFoOz6KXoqI/
zyWNA8piAzddBSPd8orVGZGHJ52DX3kbbk3+9PwDSj5OTuuM8ENJ/DCLKk9B7XI/9aEJjLtmyAV8
yb21MAAeLaGF5pfbF/gHH3oQYMvAoOy5s7G2/TWJbHpdipERtsrO6+6gRJSBeonoUCVmu6JsPB3F
21fV82PTv43L8XBFT7miFxFYW2xvylSO4h/zYkEYsWg6BzFovth9zx6t18XHNKMiCuf/JAIAPdRP
6TH1CzpGWsVbAxW3/rM4ApncS1JGQpN8/YP8tiPEpDLWkh7Ek/h8WoXqcr4ISAnegIBWf91pG3yj
nnjaVBWavWmAyRdSaQHu4rkxxl6SyPIpKYWNE+Nndy4E6qvB+gGXJPjQKoXYrKwSD7eBUhPlxZzI
G0s7s2cKiUoFYrn7BinZGHSfI27JRVdTs/Sh6yQU9V4O6xQGwqKZNG2pNsOhfNJOqJ4LJftNhU0w
Y5uNitGBYhJqlKWF2EgRm+MKdoHe94duWNH/y19MKIR9EmpGRV7qJfXT7b7kj39l8HYU86cE7HwX
lInKWo+i5JXPmJP/NHfsERfTJxIrN5tDr5lZcMuGucg5KoQrStx5kHnyJr1Z1eAtCIl7/9Kx53mD
28BvfDg/l9L2/ZMZCVsf5oVOEdOU68C6QG08wF0bZrfpxJldRUQwxWF/sNR2W9Nznf5qFG51CA4H
99jceeZKzLzTYdIJPHluy+TdKjit0A2DQMMtFniU8v6GPIdtOXeeTiplqWjxQA2w69zf8/JqmL1e
RBE+6GgH6nP9iaUvvtLYWFqtkho/MdQcC0ioaCfpRg+xevLuRxBaqdd1/V4h7hqc78OPW1dORjAD
7U525GZatsDteZPMP1m3JDQ79Wx2hudpSm3NqDhGi8WU9Hz2sQOyeJivfaD2yMHFoRYWbn0xUKs/
yZ/LQo8EhrHCa5JZ8TAG/KcCj15qIoDwTq5vFl/LRtypQ4KIeFVPX1cmOwM6piJVBnj7Tqo2hgwa
c40Dp95XvseqEyqiTktN4QR22B6Gy0r3izcICC28uavCDPjlZ3aOELEeVQi9yOpxKxep8VYda6eM
bYTSYZdtPByfqnDHAxxu8DqmaVLQR0xP8I5vqdjxBxL07yy3lbYDo/vkz/HpIv7F2vxZZy++s0oB
2Zub23spBs+2LwXGEMIGk5TyOn2eQhebocYCGeMWcC1+/uh8I4JnWiEpXzAWpCRhVaSD8Qz1eHBq
LHS6BVnmmDz/Kh1qepUZlguEEhQnQRJ2PG4DWtWu6Z7R9UuT7pIQwSq5p4DGjs4ih536mnaSvm1/
7X9oj5hAuvBrcyk2IRChjyOZp9dPfgDnt54hIQ/nkoGnih3r2PWX9HQGp9+tn8CunVVkaDeBVR3j
q1kD0MUypYgUQTsnUCIgYXZweH/eFW+dzaHZu/ocmQ2vQvsAddQ36V9oJa3BzLYKKDQTarlr96va
RAlWyzsdsyr6rAr9FaRhzu6GO4afBh5CzwUqtPCojN1hFT5fkZSUhdEFqSoiWSbfidfYag5Ipr9c
j2yr8geYE90Xy6lWzXgpS6IEjl8DHxYRZ7qQRG0nQ9remjCa4TvE0m0K9B24MOuzV93XOjY9B/uK
FP7IYpNME5CdOYU1UGXXEQaKJOXmxmJUer8McV3seNNXp72X39YNkOdkbiy8RHo3KdtER8lvrv5h
oX2qsrL3mmP4pav38AddlVLhnvtK5mEWi4k2bbdiLNXjZWM0AmX3zo1XI6yhDGXL0OE5u+lVa3l3
NroLphRV4/2XVJpIJJb/gUUyRZ0Wv7nKKkSiYnwJQtet41bgKUDO4zDab9rEQGTq9J++0G3w+HZ/
nS1u4WuRGha7UhYnCqmcgJS8zOeb/OjijJzUQefG6OVebm1iAp7wPErZns3A6vIzIwu5FDVKvfT0
/HEPeB7ENlRXmEUNd8RucjPOwwK/Sz+PuoCYfRzsTVgg2OPsz7ab8c2UWCeqCoG589EfQoyqKrSQ
tt9nGiHZVHwqs9ZKl3YYT9YfcZfgo5GAeFPh7AiF6VwgS46ThynT/w9XlvzOEj4vZGD+TbHdJneX
wQtubFLjR0pjQJjxeV0+8HU3buYLAowSvVPh04iW4yGA/+HfKBwTX/OHQFgJtY2yVVCWcAUa4zEG
pHDcQcy6D1kIExVRLpNdkH9h40db8avSTex5PuzAMsL9qNkzzsqi1CDXdPQPBhUg5Pwx1Gfu5XOb
o0n8zOT5QoUtp0S/hVlEhEL51BAwRTkTqJIepmmRIIlwoh75kc9Xfsle+sAXD8LdyXyciDNj0uOG
kEV7GYExfh1xXjjyJnpSTzHEXKU2ljJu2Q1NoXRvMOW6nuCQb4wCF0n4IeKvv6HbQd4cd2iYD7xe
kak4BM6nQx9do+Ajpnq9CQ4zEKxtkO/fcl/Iamoo2zXJ2u7LpTgN6V5yD8GlA8vCvHLCTS89T6iM
4MZ3LSbdJZs/p8QrYEmUODTt5ppe0CPJV69eDsdYjrot29SteLnbQAd06VL/MvtK+jM98PyzZ0TL
HSJq9ahGPz6M02LDoc+sDBnMJJiRz2lNO9a6QS8ROzoof5b21oG/LCMVIo5HT1H5bHL1vo+Jc9Q0
DlkeMl82usJEZPgrBBQ11QyQmoDVA0GKTlIS0Z78hzTYebXIG5/g6yy4LoJwnEw9VtI/HiPNat4s
ewtI591E6ZRFJ0Mw7KWBwdBcrv4WY/ZMvETt9d8xzgfRnHgJpvRszbYhbj58pwH5sCn+0u1GcZ1w
U/bGIxQEQnedpSlbwM0ZMcoEakrNo6xyVHFaHnqY+73dvRl/VXhqOzM5+ewWXxDeHYG0aqBvwDlc
C+zfCJ/o8EHEcoVF3oZryCNNRZ9znaItaIPfWqsytT88d5rdy4c3Dc836GR2EF5z+obtkYy/loif
Nn5F0h6VkZ8O0Bnxcg2ssDVofFDry95aJj7OVtP1lIpJR60U1XkkO7HYEvsFOIamobOmxbvyHEgi
fURPJnu//rWp/6nT+iY6hok7Ds1SyvBs73+nGA5Q0H2mrnj9Cj6UsnLzOq9NfJT0i7Y8os0NcAIc
E1KIJnJr3rAaUTW7ibo0vga3wvai1qHdBUTJGe5gJBYpBVLNW8pFtn6uWqOGz+4aoq1EhBDTr1yi
NO76mD31mvNaa8LylDlnIAsruFIqRX+aOMa+e0n3vvkSq0kSd1kzAIWHNX2Fse0i3QLgz8Q1qcnN
PzQVQxaQAvKx/kDSVl3REu2iizr3hVShbnVfwH8yZPyHXXXVmRGQhSKd2hhh4V68fXIrvD9sSiYO
JWxGhtmA240lKkFwe5uYqi2nVZpmsJ0ICYqsUy2qcvJrahs0HVdkC2x7+tHkdA17rUjmT4yesPmq
ga0maF7PIJxwKooW255b5/U7UXL95AJ3m6pRmrIi9Y1Dry0zyqEjhRUavdhq+rQNMR2kbVRS86lB
bnjP88UKF1DTPzVCfVMHqMzxX82hwj3Ku+imDTd2T3g7GvagNVATtJogTodomAWJKw67pEgkIQMa
fWIS50MX0BKxSKU9WFLtNU36QlNYF8jD8vt9EiW7t9W+LrBVVwATmnukI1VABxdx1Jf3E5HxUeV5
9Gv7Hs6yt2ZQrb9FYOXDNtOCPD/m9uoEjRnVoiOjw+BS647rVAdteFDW84q7wltH1w8CsW3ugDg8
RNTEpM0HVgf/Cfyl9b9vvY+Xt8Ug45Zuxe9LQiTlNALHWZ84+NIgsBgozscUjv1ML7uv2mZT/Svd
WYBOfgWEbe8r7yoPphjw23o+DThZ25ZyVfOuM+HD21iefeQaNDvnu4QQn08/UDNXytpoLK0lsA9Z
uVQD0H1M7CkFlFh0p6ZWGV8ITFifw97nzPWclEsDEKYfIOS+WFuv1RBuxaHcWIGBJElNXvWuD+k/
JuuYPbRdH+MgtJy2j0E6X/uufQr9kfNDRszoYzr0kWgojmLwRdUW1FCj3tkkJ/ToqayNMmTxndSq
KnuzWhPVkmUNDRL+t2Kbm8/rWjwFo8E+5kYZqz5AVfZfDzjIK7diqtDlUiorVZ0+GIIdZYUIuKRO
E6ySHh3W5L8m5TVTE/+3xUUY5JiJ9LhXrCJYtU4kb6YwPFxZ4bULvexft50rbvQKSGfvzbpedOLE
WHvVxodanU8e7IeXkqfIu7EDWU7bIrgfb79dV181QIyzTo97JI3sg39IU/X5eVK4N0QIBqB+t2bh
aAKo6xp2hAq8mAts8wUfHHIpsgQdECZuOTVMj8vXdu+lb9lbfagp9kdgm4pWcsRrNC7V4TN5f0e1
gdBcwqm3MC/WV9W+77cdY0vJLEuaWvdeLGnIhAZZBOdS3mxy6lx+9wu0IAnFF5NnUkRzck6S1oRx
kUPq2p+LQjLyL8kTF/VVoVgLNRmVp8Wf2coFo+ibdwQhRfmNkCuBHKcJ2qbI1wJ4X2reOK0ro2ar
UUt+ThMweISbosvdEwz+7V4fNjwogloPBfYZZj6TphLs+jmoT4S+3qL9/9xmZDTHpB2eK30oHZKq
dL8A0MPC5IH8PlZ/tQ6zxDKw0kqvI6z79msqX/gs0ninSuD3dN4lvbOltrq+XYibDyYBlq92qKkh
tAWyMvZdAHqsGTtt9qHbm7licb/UVzTdZ8JA+7FTWA19tTnh/EgsTHCzKD7YvDALQLOYimiPfk+B
8ZLaYjsc2HO7TCkpQZH8ThS2WQe9cian/4pfI8tH7iNllJvNwYifcNvjyzu16VQ9/RzZUc8UVREl
+7PMTW7DNoCBYtK3miIM9mrqX5AeJX+gG+P49kbgV+FunGPtkZnpxG1dMXt0mGGRZY3yh880pCv/
1kieHgLTdPFJuoTECBb80NGtFMPa6N0LLL+ObFNuPK/jkuZWEdh3ermseIXgEPZVrUGj40Jx1+WE
FujnS4RAYur7J9zlbNqkMVq6Ygd3sPX2hy11Nj8pXLPI8WT2/jOBqelyC5TW3MMV8rnM9Dgu+SoP
AsTADAiAng2oaj0gJWkWoNVZNrjTLP7jBczHdaYOPZVyc1QTXfU/n6Dcl939cMuPgFjqYkbeA564
pyxx5hm/hlUI/LCqkobnkkTrzH7LxBR/5eKnUDHBkPtvMdY19yi+V2LmgKGKndCCLCxvK4aPA8AM
91k02xp4hCHQfek6dPzeuLdbZUJCm8yEhEckDLXLUC1sJgso8Ufffdayeun2ftAZrUIn2nmzKqbe
e3Iimu8oMzJf0EOWSFAvD13Ma6P2sKQn9OSjmgnGhBEp3qyzGqm0N8FkgPMGgUXUAOtiiWN+6S9Y
Z9rOs6BVb6joUIO/1dp3HWGz6yZEyfoTIHmWB6b5VM+PBm87YZowES8wapsj9PHNW7rmOCI3sf+9
PECMROCbytCSLlzfC/JZ3AQ/atFfW2+SIKSlbBgjZnVz2jo5Me98BiXglG5knOtR3MTYGPpNgqxo
M5dc7oh7gZWY1uRuaBm1VIxmJW6q4jzG5bTIjP6xTU+2qynUypZBxuDAHDcZtIw4aVEe8356CEq5
warr4QXEaMhz23/Tb1aZCawInuG3UWkRUDY/L3sitNcge1da0yoyn2D4xS9ubrXYQ0vdKT4hFH8D
PUbu4p7Tu65on1mG26CcPW3f897c5yHvrkiqPqoY7TvoTohXFaQPBxxea4s7VmwGxbs0DtzpCmt4
83qaKCGnSHuwUmB4thf+omfK/jTz63YACrb0+82vUFtlhkyu9aqA4gycXGaZhoYMYp0ahkEmBdSx
2q3i5t4nZmyf/s0BpFFd2rm3tNiQ8F6opXprdNlLosKZF2W5OaDNFI2fG7DYHT/NnhLjrU6wdPD2
Em9Bhqs+sMjMz9aKJyvIqxzm6nGUAoUyxRnK/6+es8/jtvi8I0NQzb/WzYFbvI6Mp0fiv6eExIaW
a3bOGeyRxhs+qG0z0gW45wDhWJwDZcUn71h5PjogdfEvvWRur3OBRrchG8UKGuwASymvuZL61hTf
Fx4qfKJZPXsKJhzSSZjtrobwUGAypp0B2XJumnZcdb2dLP7LPk+xcKLp066BLNaiWiUujLZo1YPm
nbMF55L5Cm5qOAagdo1PSXD1nURs8qr65wDSj+8DLq5Q6QA4e7OBaR2oh0oi93Drldxw4qOTd6Rv
iYuRl9R+SAY4uyUORPYPC0XLJOI2P79+lgt8k+FeTn8KI1PerbbzGm+t1SbCAmc4lXq+du83d97F
aKwNrXRIpWSYs8R/2XVkPBs/gB64zIMe5yeOK49w1Qgcy5hw2qpdI0yFL3Hd3F9N8fx3U424WTmc
HPkygNK+9tkB8cVPLGGDrF/BhKwImzBaXuNTJU5cIF1aJWRY4TkKS5XUK+x/akk9r+xcsMUJG1QU
vGebWpTxQm50DxAdYCiFhhYsL5LIpIfVAzMq1RyBg+xgh52wS2NuGkyebJSrw63Sb/qsQ8+AZFRR
yszkAWHnieOFQAqRJm+gu6aQMSqfZP7EjTog87kgo2fdSoeqDYY1kGICDal9Z8peXPKAbQous04W
YIRqe/iZvw0wW+ZfpLc7GN4jZyy3lAbOzkCIeaf7mlWP65q6MRqSxqtJPXkvwohoS7YMpoPfnsCg
hYw1y8EkPF6Xfc3YxhtvuQ7Ww22Pnf3jocJapelojIGftn52+2/Vees+uB29G9BoLZOraCQttyVX
/tfiDQ84Xu4hXETdUOmHQvORFD6i6VaS+o+9F6XqG79qy518X7z9kncj5pmoeWphcb4s0Vp67It4
6mvdlAxwiYaCXTl6w5uBSbZa9JI1Pw/bBpkrLLHYgfWTPqoJKtY0sr6Q1UtuJSxzrBLnsfI9ZrsI
eL4VgUFPEXsOK4/UVSCtrl1Ijg0vfIXhglFShKyx8xNyKclSGjatrGSf7odJUmJ+YqFtL3V/rdPM
aMch83M2LMu2XvVxpyTwSt7lqkCHZz4UDSbbizzwoCo4eTG/Vf7q/EylvBRzN5za0MLD3vkEpzgn
i8q7xErDDbbS+reX6WzHwHeLTlRQ30k2oSA8xYELTuRObqAcC4YtapSt79S/NYHD/OTZ20azFr78
RkY0o2LJ3D6cpNP47RuTx3UMRX1C12Dp2TK//icUg1sEmnYlPKvx0RRzPFieoD46Y2JAqCVEcN+5
rKjGfLQpbhuM3dw7Wwknog2Y8QuV98cl3nYYa1iGNgewoKKT7giyC3gVXl92n//U0ZJHUxTBLHg0
SEE7xB7IAoyRK36S33FFJWb9XCaFukswlwW2svcfO/QxXmuCgd00QhOGBFl31J23h0NCtnjqMp+l
RwUoYo5g56MRZmhWjuO0OqdYixrY3tb9UrCvg1lJVbl1wPx3kegYfT3H4ZgkgX/qQcgknhcPrW0K
FypfDCBE1gF2FO/OQopvyKerpKkCliCVVDEBS0AV/ysmsL2SA9iXFSy5jN2qwjHDMn/raiI/eMSA
HdK1+L90GWvsq/+tgCO9/EJtJIyhUse6IbgnHjsh/bf6BcM8Xkdv/aJYy91oYYOTUuxbMqByvynY
vrJ9kv6IjGZZQ5lXnn+OEhNE7fZnPeQ/OCihBpSSSCU5ubHl/7Kq2wPClwnssyjYgidBGciOsK01
BaLRg2wPUy2pHNwoXzJyMmoz19CCshqsd0w97sq9TsgHFPsdk0WULVWLCU2CjTHP0010Qp11WCkJ
1avx1Iu0iq2JgLpDc/lAgVEIDQ1Gb1y/JGUHeNnKcFf6dJBQVFGp1UsWp3Gq+hgKXjU4RwY+/UFq
H1esmjwXObo69QxmGn7j+dl4AXB3xQfTwsfgWEgWUe+6Ohzn8eWeiR9QZo48r5cRSQ688743l7Ak
MJsbU7M+asMyCUxvQjz1kVYLLoXxiqLkDqZP8BoFK9O0SW5wur9imYOAIbcXnzEDQkGnpXa8Ikef
HEdbOV6DJu7COvkp9Wqcx2vIXGhzB5FDkCRuw2K89LR8hDM2vFxOx14B9m9J0FJx98bMiuddoLUi
u1wQtXkBGqGXAagb8FMId3Ndh4xoLuDkhpb0PGrJ8HKutNKsSN/R9s1aZlkXe6M30FlufwSOaD2p
bWal7bdheoQI33DEecEYtoeYS1fBZxjGv0UcvDsUX62l0mhqW4wIs8PwCN/IVOD3mIGjvsCnEck4
d237Ngx11SfiqwsMBM0Q3WxPZsrs48DQ8aRSGd4jCgMqFgmFs47RDNFxocQvgyn4msxAaXlpd5H9
8BVCc2n6yV6VXnL/0u9v/aKW6Ybf6xG5vmM0ixENXzBigIA7ytWuwSkYy+Inw10p8NkXBwugdFFw
t6bd6zoXklNLcqf7D9bRE9hFAvjVU2AR2BTjN4z6zYwxGYQ5cMxyQsUOqMkALAZSWw2tO5kJ1hG0
SBOUEfUkaL7/AFayWZ/ffGJHijSU1PJUpObyWZT+DZZ9ZZX0HabaKLHTuGNBNPwQ9l1OHWYyrcee
kS9zIW+xAnmEqSLRTFX+znTiIy+2dab48cS8ijV76DTmpTbqraZfjTOVMkEVX3XLzksrBLQRd0Qy
hV2R0yZYk4Qb71lqXhTHKIpM/YCc8DVF74zCEFtpp+hb0zVhnL93ZrjMBa/YZWIclGoOo07fyUuW
MTxVXZscZhh73lJG9jG/t1FpmtnOe0cZzRCfg1MD2UwSk8Ur6i4DGVzV3oqQDCwWEB8hn7M21O/Z
/A1lSaLmcrOrWAI0mG6+djdVbunbEBqfyuG8Jd3jCtIPxdyfGEUwXxpQ7NtEV/5ZciW1WHbwHngp
SF3ixMJLmMRY0hxY4Wkt4p6NSjrcg31I6wzizA16WUC+C9B9+Je2sAiCNbAFAs0rndw+pN0S2H7S
xZ65oThUg4faaaRy+Lx3SLK5N2hrzdjdd6vaVhE7+unjC1rpXMT9G4l1vFaXxl/iB/AFQCMnyDq2
Ejb0ILUh0M4U4n3ETozyyRwYw0q9cTrcB+K7njnqjInW0qWOXhNHBHcWr5rErnlCYVQpdwYsW1HU
uVVNVzlUqGcUdJBa5nAlntmhDYA21UgEuXrZ67+FJNstfwmp7ludAZUmNEgiFlu5t7heBOUOwEuh
gtTSka7Qvnmn3PMf2C5zq7fMJxI+mGLTYw+f8LuYAjR+mrqyvY+aEZ4mWP35p2PKpdP6XcabsiPp
p2uun9XPK6SzM4iJqLbIvBOXMF6PgdPg5Iu5LSDEyUnO/GLRovRwckl98qu8qf/yL7JcSkbavpcW
pUSe0saagMQVmnxWqiH74NpccvZ4mT+P6KMGCOoEHZqh9JvE9SKyD1WhaV/uugsUPR8UMQxaCnCz
9bwj1jp+6PTpYOfqnN0QVUZxra40BqmNrSXHTYWPKHZd+gpfifqiwHZgamjiQQcL40jA3T+u6VQ1
5VpQ+r6PHDBe5XO0/ndlkf7KmumYvIawpj2ROQmKsTEs+TtvYFEfjN4AN6JNIS6LWVKcPamchfcT
JEJgb7ra380aRlEV4Yj1rDH7iiQ24A+0R+q+7mNz2ir+YA8/DDIwoflAS6KG240T0a6Biyo4oCAl
EfmI9Ojd6/iZMfIKi/sObYR4ZocU6L+vUfFMPjn4l/QCD2mWb5xf+DlKxLUGi1O09UrrSGklR3IZ
7HPqSMPDmY8KoyPBFgjsbTo3b2Fl5gAcZolcbVeDILrsSs/CzJZmMJ9RkQzkrxqEIUe+cQzvQD/s
1lbzeCdnP3Bb5P2ZdalKRCZ/fCDoYxQADOP2PKKniI7sL2HSO07fx1IbAUhl89u2tsggxzpXh+R6
cNaETzPJaRTsIKo3ersYK/nWgCFFISbSE2e6yAJLRapw648Qmcqd8M/7OE/WtSVmHkPGHWpM8jVE
Q9vpMmwZpmndTDCBa6tufewWEUZtfn8ZXzBwzX995P0nouyCtT6eQ4YONwObelIlb6/81gx+CUmd
vLjCXDArco9WfrLxb0Uj9w6kARyGMpYQQDPX9oY2b0Hthfed79/P3XVm3XTnRDqnXNsRUl42U1/q
dSsMnYPicgPhsL8kgPSF0rcVfbguiWmCQdWFRt9BD/c4g5fa6MXzDs08xZsBlybptOccDqRs5Xc0
gCDEykLd+9mOPbjSoxPtWToihYiCowblOqNENAFdrjU6PMFwWZJbxtsJgJYFG8zbN2nFWadJr1Jd
mkNgUaoZetApJGojVMbH/f+I2PO2+DnEGJzH6lrJJY6W08LcaeiIQM5EUykOE56eI0DnPhvcKU/A
f9lG9zh/N8+j8L9y37fDvWToLreKdVpc/z5WY32iPHnCLca1SwWfaoPX30C8Ryt8ionY6FVWrqaw
+3rDGEP34J62W4F4H+W54gI6cDj25z0d3V/20/UDgjP2ISyQGwnbiuaynZkO9TKXzvbm/9zU6Pp/
A+MRShlV8UqSZaEf4KGz3PXi9ykAGshDavJ0nMkZPqa4j9BIOX/LBtj4qEAZ05vcN/2ED0siTQyl
zw41CzmMtmv7AcN6Fy3r4XMx8WSuJI6fTiRYIdCLLLJvj5e9LJTFFi37zZsTcSBWaKeY2hxzIm5c
NapY7XLiKozffKezX4GDVo9WxrDKUiWi9b3u6T21W32HnSj4BRNdJpmpo8G6iwKGoCzqnI5xuZJc
cQl03v7Jv/ri293zhmNjqA7MNoGElc7u6ThOLfWgGtaNV/2Ish/o+tlVSYnaQKBrwjs16m5URJkL
X0cdW3OdixgHmsjMeai4S7PrJgOXsMct/3M3+GSjUnJQbr+YO49QP9K6QPkvaop6VZgpADL2maQW
dCOjhytzvF/ZSt/46Cv43Q/JphqhPZOdKX0gp7aUPZMAD4wU3K/iuvQKP7/dCJCBevvyVa9qAH/3
AzYA/RRaWaT9GGPb9R/GvUxmMqK4LkZuzAJCdBkHsvhGsKLE7Bul/kZYAXojO5ykTcDKydLxhm6m
QORgU9nozVYkZIURl+4mt8BKSNWqmFfTWdGUkSyzIOj1LsheTk5jjTm1sodbZ5DsDxmLZrN/JMAG
Z19cwMx4xG1Q9mnO4MEoJbO/45JT6RZx/CDBwITA1A6OeOSBQSLmfSni7KTScPzQqCN/uNGuQHSy
sDVWAgMSZF0VPwmRlC4xDStgC7k+MJ7xtMm3iexuZnZq9CvQFKxUyOfqs1vCLvzBbQo77Fw0ZSbn
8y8IYexE+TgwyiKl24gn/W/RH4hIhztXaj6IhzNZ0RJMqL+0eS0X0KRLqWtEWBWoHmv5l3IFJIJs
fKmIEgJKrtt+3kmBrdB5RzSgaFTejFhx6sHl/oIcCL6mBHBwQR3WFCgNS7gbaKUa00EyW3CfcXRb
xaQejObF4IyM5v4r5w392SCmZSt6KejV2W7ZO7z/YT3UmLXsm9Fypdp6D+cyLZDSkv7PKeUmVapS
9sgTIu/cwh2M+D+3U1hVPVVePqzp4q5BDpXeIq+9766FZN4VoBqycSZfqJ1C5Iq325djhRjdRMAU
9Q4WAY1L9ACH2+Rqci/fts1lWNrKMa0L/X/NKPz7ZwPPNfXSjYzASSYArWvpxQO+YdzNX4Vp6/k1
w49f2RCzmnDHL6ae7pjzWXLvoTtvNIjxhkCA82bc+vbrxsDlQ3+8b2rajDU12TMVMD1z0GK3bdnB
VHBi250CYgBkYMMFhrUcsjkln+yLJDUg0YRu2NWYPx5wGKRvKUZf7+0+WZa7oKZNNSBO2IVZdkmu
xArBeuUXWLH7RLn6YeXEFSoocXFqByT6N7zarIHIJ+i8P86ad3ukg9nDPPpQ9evpjzJFJ3xdu2v0
DrDH/rDS5YwLYrp4YXcpXFdAR9whRx4feErAK0QUdULi8AeUidJTa5o0qs82AB6OFYgIXtyq1/jQ
tThDp0shw1txt21t56C+LUQ95yWO8nTJzCUs9aQayjmDzMAxiE+71q8V32Fg3b5dP6X0XKnWxb2E
z9LsJSYA/eMf3ya31z9Z/GX0I/ErbB8KnQuiRrp7WEG48+9FsnCctdLEsRzvk8GRiTAyMXXZw3fg
5uy5rnKzw3p0QCMOsxNwr9P228z6C0n4QQSuXCkiwgWxzxDQ1WOc0uzlMwBXQ9CgYpUGwzuSgH7n
pRKtMsdVLRIQdhIHc48L/pH9dbn3B7MqTIVgoTn8uRqr0UOKRlA+uaicenLTAMtbsOU2vKqdnRup
2NTHPwqactTVTOCLdUb0LAt+wRfTwdgNxLplv7RIcZLR/XHjvSbMXuWFbRvF5n4EPbpG837UNpRJ
FkFCPmMMYI/mmiBbz4K9mm+ZRvdJTs2rsBPlXGY3iwI+BtfzuI/xyoF45qyyaiLuqdoBzP1ddT+N
W85B48kyDAwIitTxz5epulXlNRxnMLvf5Gu9ZqTFryDXIbie/9aMBBtmVSNXJmk4SAjEBgBZ4lFZ
S/Q5G/wzm/5c3gn/5d/Or+irg+UfpKIEI9w0zWBdzI6IVw0gTp0rqtS1ETc8yk7gMOe/oDFedqfK
LryJyL0rpZIez4HPN8wsirnb6xv6/HD8v/VQFjfZWIpLwTO1qOs+mx04nOpFhj4LsXjzpmEKS3R2
LJBdFWBcDIq/kpqOnxCm2TfWSRk+4oHrIXawBIzm6k/evThiKJ7DptM1Y9G5fssSCFOx3qViJh6b
q3zhVzB4KC2I40kMzOztLTToqziJYRjLXG4B7imv9q3Q7svgcTU5GsVatng/AlOTvIuVmXcSgEUH
LgrKpB0YpU0LX1EbsEyvSF3RmWpqmzpARRYMqpmy2m4s/O3GUKjsHzmLdQeYQR7UrN3IRc/+ZUwW
2U2RBBNthVxVxDXGkok/iIsg9Xt101W3tHPYGLB5P95/Gyh0Btd5mQ/g8B5+hcdkICFeVYMwfnd0
EN0vnPvXR9M5f+CemVE+j8ibEFJreyp0eGbOJEaa56+9v7mSXiOQ8teoZvKnkA+QWXrJhxmsjpBq
qIYUYgxu4tkr4E+3AMFh+9CkfaaOl2hu4Yzaz/NUCdG42JdL5++F1JIe/5xK0UJ+udyZfCsgApwE
NzEXnkR8LPujaxO0cvr9fn1SzM53Us+2UWFdzJxHBDwKjh+b+nACh3pXBDPYgx7KvTGm90rcloqD
UO+/NlzZ1LyJzaiMosBE+W7p5obBNmWtY2EhrCH9lEpmfRroesKMxl4KV3ibO4Xp349VeVZ38u35
gPcJx7IykOVGAxZjgtUKfUZqR+/iE9HentmLtc3I0OCwCbAUpk0Z9FRRJwZ4dpQ4r2YUpVnuSIK3
Jt3t6kbuPj62J/0zVGt0m2B/TJoHBbcVw6yMIFwQuhiYrUoKqQpHdEKbuHCWS4xtcKsJDS+Isp89
nKyYzSPXgjxIfhN8WBFqNUH9HVCk2zpBLyMIy+/rm0TruIOSpXKKwLz0wGxvxRruyvYXPBgc3sHd
K/45lEY8Y7Yq+xhHasl6//DD6qVUYAFl4XZsFzhXI6qSFZSBFq4jfFju7ZtTS0cUIH5J5nJ24Ga/
EnKqi94i8jd1AiGLrnB6KRgvnlwQXsBrSYFfOQgyjd+WjMREPCdh0Lfh0ANvVlBbUQizkWx7MI1O
b3JaPEi8df8c3gebamOZRXLH5miNUi0X8R5IK7q2cg4y+XkiCLB2a72Eeeko/tkGDU3uhdAB1Ixm
wrg6zgaM3Nxt8+DFaM5qOL5NK7QrPkXxzSXiBvPyZqdZhC8UuoGbPoRX+ZtCsNbfPYcpMkRBnZV4
zuXNlH9aE8M8lmiuEGZdini1kgt35IVPAuAN6hfBqRh/Pq6p7WpjUeZNLCy2UZqaAwzTv1NJK/1T
t+AmCr+ITRssy/T8hTwtKsD3fkZuggkDOu74zfpXsrHAFzEAeWP4I1JoMMU8E1Xn8R9TcHoAPnvM
WzIRN7EbPbBFpQLkCyE5WSHAMPxy4HhrlCz138Y3xN0ZZmYOCb6EnmJoSHlVxYJorwmVtGxVOs+s
YzpuQyyqkH6vU1qQ+BBbRC1Thi5pXFGa/Sf86WL6FIB27QqjdX88HUvjZ+SZMldqbSYeE4onpqOB
e7Ya7JsYOOnLyEPhOZsFlIRSgRRFoBAvTjTU7knDnj2kMA50vJtPDhyBfRzLPKzOIY9ylN51z0o0
J+ud4nIQv31Ses4jg0Gt43vrpyjKPidkT1AZYoWXwZnvSzOxsqR1DafPSkzrtlxcHQM8x5Rj5ZPz
M31hs3UW1CUdf8GokpeiUTtmQQcPHkEZhW/1MgymlLR8pPN9u8A3TzwT4FDzCxQoV8m1fTHWfnWC
I1K3ClyKyedTDmvDPEX+ZnFXSjm9zgtjTHGOe2GLxniv4dsh3t/EpMXAiqnUjkTPtHeRZc6tmnPw
2qJoaOfH7TbAQe7XLRIwu/GG6/0OxesBexSmrlQuk4OWCFSRMA9UPdenAJZnvZtDDOXt9HVQk1da
9Fl/BNeye0bv00Iqzsyx8abQPc/AZxSr5l7GHuKKUFg3xnRY7/H7bwiTPUOPv3oPaZJ9Z+ndrZQa
nupDTj7pRf35uRpFx4VQ7pBuXTfXFHiv3J9d8FBoBcjeB+h8lJY+8Q74W1+CnYvWJEe9ZVlO5tRn
YdCV+wBFqoMatwInmi6FgBY4Hw0yM1ZamD6ri9VL8oAy/HG4zelvsIdxMvRQll3BZQ2+cSb4+QkJ
z5+keHU3jFiHaMjINm56oH8jAdA7T61syyQTNhYf2DnAQIQzzcIznRDSeIoPyVovTOCTLSDAEP3U
9GdYYbM8FjuPDclaNQP576uV7VriXrq/2ltYPixf0IenmUO3+axoBON2weJg1m/33g5EklKEqmGw
K/HspW38aFxQcxfy1frq5pK3hn5pn2xOU63M/GUIbUyUyGHxKrmwbwe8lZgxhNi8HgG1rJ4nxqmn
ZIrRtez7Bkf2th7QK1P0R5uo4q0qxUG7HuOMGOlx5zY3eq/rFUCik4gLaUGO6CqMsc0t2pcj7dEt
Isn3zCUgLqRBjFvndHRnCwtVSuJZ3R1oO8nYBgVq0ru+GNUVIR1YsqtW/hz6HMgImII5h+gfRWqu
X7CEz1wSnZJElTt4FkX1EGNlcgFKJZqnZlWyV9cgaJB0m5+63pZxEQ1FcVMDcZVolJIP8YT8R9TV
UwbOi+inko2XbWA08K/cvTHcZtBgmlHN/rs0+EX8GFzRUcdc9sqO9g4ivMxEj01Izw0wrMUN5VHg
z/YLOLgs/tSUsNfIhuEoj+wtrcw9ZH6Exgp+qXBD7Fw+7H/Q5Zf29bEQAl+xZLAXoNg+spydvmZc
4ciBUhWiDq4fjlpyNaHHKP04PTi5AxFANqOTRSoX/hrtu2ytXvr9c7fICt5PMQ/mopc2MX8XPm/V
6zu8pECXHvbIeHoVV462gNZz0mfaPZ8i1LLg4NfRqwAaa0Epk358nimS3Yj9UO3uY1slupQKy+Me
sb4eADNHsClgovv1Tb0Qe8SNkGKcjRCSK8Vp7Tmdu2ld25Gv1z3sd1oyU7I7Uf0FkHATtFcPaCq/
uWaRr2lqt4JwX3yAOBkbhX5hnNfjZbWIkDNf+nfSk5RB8p/UwOV4YiJwp5y3LXoEH0cAs9LOp3SF
NirCQScYNiWY8Bx89m4UheuNh/NotQum3objIHDLoOz17c98BTwzJj0hw6uEooVewXJK96N0jzvl
K7tOzias6tPH8TVmyA62dYhUXyTwnS2XFf58/D8v+3Dq+H732yjpGjXwXqocuPnsSwUHdWX1fRfx
BnufjwHJTmNI097USlITVhF/yC+FNnGKyfqaYbsU1m3/muAixX6AWxhQey2PiGivSIwqEyBiYelw
u4lmgA7ALDUOl27FO6h7mnLbqIUtvjSk1rSHwLN0oTA37uutGxrkai/EmZIGYHK0+XCZgfahANSY
mKGfk527uQV7uZ2jX1RBehv13yih5dV3vmhHid+yKmkN0wBJtigDb3RfF2UMp5WK1UZI68iP25HJ
xJN9VgJQz/yvihsB0SZxFNZLs3gQ6YcJ02ijjvmrVIDWnFrhcHXTEq2Ar4+8DCRbDVA2J9kHv8cA
8R7AxeSM8RiX0IbEF/FhpdgAOewpiMts8oKkUFey55mskRbTsJh+DakRNcPfIcInQJs3BV/Wfd7C
fd2gHso3M0hE3sNY2qPMoI+vlpJ0sM3kr4dFEjk4F/IbKXgrTpEsTYoqe7QBugB4GPLh95ow9YZ9
is/WZJJDeDpIPn7r681RxvG0Af1tIIQu/J7h8eJHe0TQnrFdOtdqFeNkqBgPdrdJOqVJyJB9eWVS
ghhv8wXWylnnObbLNX2XO+HwnV0i1nvlfKKczdD92UnWp6xwLNywBfDXplq1RpGt2FnuqxvlqM8y
gZBlcKnD6LC/lzYJ8ZWBRnnEb+00PNkVuzxnP/h85zBWxwuWL3S7nJ8AVjYy9qS4B4vqL5a5aHhQ
6fAeF/q6P/+RRJAEPWydjhI8BrYB/Tb3zMhC63P58UREyhANgRgm+8DIZ+OMZwJ7xtERgHmRJwhh
fDoNfYwGpyG685x8nDzPS5HaG1e/Ggr9j/Pu1zu6HqeHz8khko8hbTX/MkwKbLX7uehzEHLE8W2F
JljimqFLkoSdJUkfItqraZvWYPPsLxHaU9msFYB7+brpsMkncpoO/zStLsQaIzfIqHodD3i/0LoM
RLLpaJyX6ygApgcUsslqF4YQFVAUQxAj3/O5aNi58avP1P9US16OujRsj50LTAOqTMOfr1UzG1cP
NKHm22Rnu5KG4ZlqhRWYxlCr6h1/TF2kBB4p5WcLK0L2H8DS30wztvZzwAX+5RxygG0eRMtMXQ8h
P7VuhIPiT8lSos22Hl7V4S7lI4wQiK2+9lgS6/xh24Im3CZWTGwEVV4eIzA8N9LCz6LITM+XnhwH
EGVeu5R/BO3fyivN5XZ4ymhoBngzgvxBTYAdj/eZ802MD/ea5FaQvzlavNbweusQu6IP/iHV4i6I
C5shDzM5huag3Yoxfh/vYkDtOGv5o7NbeKwtXZfN3QLACSLc62M6qCfxc331nwZ3L8TOFYvwkcfr
mvieJ7lWU/n7HU2rH2enXQXYlJn+jQY6rzL+BHQdLggMDjZCNCaZPYiIkBN1kjO7Apny+8A/r/pM
wTHlEQRDKe56+tJNe+xzUvGDEpgMnVG/uX24RE36Aj1kfxIGSWMAxQYPmTVxmwPfvAwE7Q9XfQKS
MGuTMAoDZjqA3MEZo1In/wdba6UYTbCiUbbbRKq8xkbwRR3qbDBk3MDgf7Fr0/wP0/pQLHrahOed
NQ5R9Ma0kh/bUt1PVwD2Ruqm9PN5t5CJrGA170gtXUT+gXwCMdS13+UzD1h6QaNyfc7BtBl1hkg9
cBqw6397PARb3LScN0QmOPe0EYo+5X4KMEG9/DjHIBub7yw56RaWucIvxFm6yDlK/Msq7HWrTu9W
hweQWlURuHLm+rsGuaiRM/ysyEjUEHC+2y52+sM7dX/tfNJkp/3uxK6mazAGEy6lNTHniJZ0wX7C
cXSqtbkiC4sVWV8vUA8jxgHNPyQmWAxst9yWXNsDnGgxkSY+cFGkJVEsfdpbNxGSnC7KUty+a0Yp
TYorJpiLemjf7Nv6y1B9p/OEZHre0whmFGAWdPJM7d+Zu0AELbKuoRMXdq4VgsRWVoycixiFf343
NJDyRKaICcwKHXnSmgGzoxp1XytZxM7V+HoVztn9DXSvWlBF5p9BtpkxFZc//rj2m1wrFFBZCygB
bV6bbR4bPP/dsQXnaMgvgkKViMiwj4SnE9HWOCDTiiRGAEgQDJJBT6ONPmSJPozKKwtwJuBrSfdB
9n+RRGocsIz9/fF7LOrDWPRaxiH5fXfj1YTDrp/6v9w3jto2kDZUO7pd9W2jnJpFP5sifNWhZSPb
FjSCG+wQ6KFMP6/b/6z6vpwYEl88LB/dgBFHeAwulAZbiZcsVTIkpqdeHOZAvE6losmHPlSvVhF4
uin4gcvQ5mFQJlYBp1wGvD/VgJtpgjIsu6gnm3Vb5gtrPePoAjHUNIlNvs5PVehm6hOPrOMYVkqc
9KJGMEOElJDLaOdQThA9g0dheWOKvpt8ESY2oeWSiIsTTgccU5486Rk+/wV9b7ZFDi4KuBl9lZ1g
nZhdhs1MWGSEIVixdzePjx4bTw5NJAe4i8XRThIg8dBN1NdPpWi2ClMncwLlbecGZiF0KY4T5LmB
kcEIzjQa4DEjgaLWqK1CeOlvXTT25GMXtAdgVs5Crs/whniGzYOA0NXE8hgWAG2dPG8WAoAuAbcd
C+t4K8Zc2MSCjGcW5j/q30YS+ioz9zpkxoWZHJPvJaMlXNJV+c7Cy2X2A5zWUI0e0B5oNXZpjX7K
v3EOCnzwsqYhBdHtcrtxQw0bjGvRvhZCwUykVX3HYlGCNoLr5M3tHuhTWInTbe+266protBtLoYF
fG7YXdpY7RlvmZPOOi9r1wAIkChXzJe/gkYyrIb/GHsUTRx503IEDHCezplAqJFV9UK4d7VuCIEi
VKQQAiBNx8RBi7urXBoOAN7GUGMtpHImrbAgJHsF6ZVdDUA55QDLHNuU0hRt9rXubDGKCBHvInmi
LlaXDyE7iKeKjtKS/Xr5DVoKBvSA6vbsHv4d+urrDxbDEwTC29scTLkp2yvX2Fjmz6x+8mZnYaqG
qi7ijaZf+i1B3YOu+knQNfX4c7NUugyTpLdkmx9aEraTW4Pw6yJ49R00NYjOTq2BLo0RHH5M/6nN
5Zj3wpZL7LTia3d3uGLo3tLVfLt+mFPjCPAYPoNXI/wkO8lllfO+S94aKcDQNHybk47vuQbFW1VD
05UhrWkLBXptbMSPXAifXB8XShCF8OEIk4wAb4RIXeiXnfcayzNnvbMc4uspnbQFrw5Jm29TV4SC
bqGO3LHYjS4aealVYPdgR7FqCjE6CvnxHHh92SHAPL2ILUDkCjoGSL1IFzw0Pt3NmCRM73MNaPYz
QcdAWEyCc1va5OFHLgCODjjmonsfJsGgBgrPk/8IYFG3V5pLcatlZffMA7C0gScZn7hPbU0jEldD
Bdqv7dYUEFev/vlein/pyT5CKJxmSby7hkZOPMPKly6B7j47x2FMED2c+7gsaiACkHBW/P243y2y
IhtM5MWYoszwZ6oh40nwytexKKIRUeCoDK6F67ZOEHPrRAcjgI6JXhxoO0b9yBj8734lB+RNcoXV
4L4ViNaQ2UyioFEQO9km+DON975hx5KP8gz2MY/1yXYfRPbq7g1EXN2RJRKZHPSAYSq5alevL6/O
N3LXcr3rP6qD8Okb4G8ZDdaV+e55GlUSSMNzVX/i/bXlg9E2Jib9T5p/fruUZm1i1VDc5Dqh/Ded
hc3w9FBfnc3pCEGVEB3zUPkX/s0eSctqdz09gG7ZzEyuQ0Z9vX3ty85wt3+SUZQR+8dt+QvP14nP
9wCDhh/P28UCwz4Vi1VZ37KuLFPygRt/Pff9Qr0HUBWcUi+KfBYs8zah4EyqbNRspJW7W+wtkOFh
uGjuLMjAqvpUnJurn3++Gw2l5udSmBIcmaA/7dmJvbO+YY+oIy7s6ss31WCH9mo7Q9974Ad2E0bB
X+DDh+o/wN0Pamtzgo2l54x3RSlejIF/j/PCk+3udIpo7SCnQtqacLjzqSm0gZgfcJC8uzVzuAf8
PMk0JYaTMmRALIc7ZT2OLVtaHO36vt0279JB0hkpIhp9VvpuCt9sZp8tRiR49kFhh36otjF7L6n+
dzpXS7V/4Pp3ZdsHJXdcVuQUB57oZTbEDSZ00U5pFi5iBpx/Yg/iUr1SI6JG/iCjfVq1p5CVXo6U
31pcn7YbO2bCM13s1k6RF3WEdFb7yEGIX7I6p852cEIQLHKPuRlS/uVLMLCYM1N8CaWVoM8r1No6
0cz4Usvdpbw+Bp/Eg5KN8GLAUrUST8oxsNX6wMAog8sBw+EAaLdjY9+tz5gI4L6nfY2FMdpT8IUM
05JerWIA36LP7fORk7gLtgZtV2c2AvHl/IneDdfTotV/DoZgU7uTRzpnfRRjkxbFsMcQ195OCZZ5
MRLQtzvaf+3YeACByZ2zetv+fZj4WtK2JmmBBf3I2z7oNMz0Z6ebdMwYhaK2b/AOSAKXRfkyaUGs
th3V0HQDIpuEDsH9k3Hhxc6ny3TvBDawkXfvHyGncB1IKilDteskIau2UdjhrDK01kswQgGCb5PF
4wHjbUULZM7Cub0/OLZw001/78xkC1VN1ajpM496RkJ4Bwl81YSDMxdJizXtp08XVSOCN5H9Nvt4
dMyvcQwXt33mLnbKf6BHIDu9saSDOeqKwVm25V3pTk7IzaSDjTtl+4qh1IaBaggiwz2G2uwGmMtG
FY5dAakhGyKcEfsT7uHZyIlrJKDitKJ5JZyY+4G2+bvtfm0g/lWss1dliSYhSsErAlMy6s1PTvTC
wWixO8FTWaVpWO4szm3jWPhMIZX6xW0o17IvmW7gZikDD7KtSFkRnsevpMQj8ibQdXL0siQFNJhi
DWghtAa8OLsLzyR8ivokCYWcFYXynekiUaOAmp7RAgV3qtaNok2Kxw4uv7EOCwE9FsJb0F/VdmGP
5Ra4XGweahgES2FZQcHTb6OoaZayfAn2A3ubhWVRGol4ItM3SvoSn16QbZVktiPFxN17Ak4ORZVk
LgtI+bOGdde+fEt0vps6xIGtLID758AWTqGrAmFtN5eb4BHFXZlprZ7pwUww436KYyjjHdpCwto+
2PLeXapt+Fn4mqA7wUSpCnegubmafhM10Wa2vvAC4Dai+nV9CpkAhdZV2tIaUyRUV69ZHUYY7t6b
M4jQ6mDCZwQrRumONuNagX8f8tGV2/dbqEz4KiW5/u5aWoioQzM2iRV0fLDcRrQxir3j4sUm6BVQ
ZRoe1xUQuA7Tk7XQ3EGKxsTTNIKABcuLLkmJAA4enhPRW6dx1wu1dBmTxPHHpD07nogdlCocNI6m
/Kl/3HZXskElU8Fq9iAEETpUNLbhVlddPzGlcDO7RWfNAu21yTvB/CGsJC0Sq5CZk9x85PWJoEE3
rsPyfD4T7/dR0/Yq64LJMwX3ps5GmcOeZ2HSfRRdahp6BcB4qeSozx+lg3DHVpOv5ObFDBMEY0iE
VbgMPUJsX8327bpDaDdvim54l0ZaeimSZEBfd3gIiTI3gIpaWSXbYzwtTohx5iQ5TAr87p3yqBcg
pd5wSCHlKoja9nkJM1qVl4k6LfYReCMO4PZdZnryQxoQIcN1o2U7W7Ew4aCYw8ryUghtS+VeI/Z2
OmrXV+m+7Ljwq1PcRWPZaMGnu+GNcU7biUEhInVeubmqDAS4z6rYEZkkYpyK4BZ9JS0SBLhhWbHZ
L+vP7BKH6rwl2usApR5h9nFBU/4fmBikH0k7I7FUEjh5Wt8cs9KWEUqCpw6StT5YMYjPoG6qptdZ
n36bhnYFwWE8p0FcnGVfUg/VZXMEMpQNiV4vswr/P1uRZNDrKLbaG17oIyelb9OiQZMF/7I0xkGw
6PdcE2jm/YX2BPKZ3RJuR6Okac8tI7brV9wq/RDq9DJEg8AbfAW9S3pRUuwYCOSYYlCD954xu2cJ
6uXslS+yJT5boVO+LTVL+UPgcdD/Otg811Eq34R3I5Y0X3BQOwLgk7TrwJ7UvnDuhg3KzZ4v5suC
n6ySnfe3cwLlI5JS+dCogxxTbmEpmr3bGkK5ZV0ww7izKs/BpYDnGTtY6m9rLXSy/CtYzPHCWifP
OEw0n3zNzK9ZNiviqLf4nqx5TowhCYztDH2NZcwrsXICsWJFUVLevI9cxovP7toRoFlhQhNdPwXK
yTmcoKD02SDwEeNSVVInpaCFqENVp0Hd+iv1SDF8tc2iH7BsvRRhbB01Y9FhzJlmdSU3X3rFD9qU
GLv5w+TRgbooKLIlWR/Ttx1GkPt9j3qWmFy7HelCtlwN774TEZ/6VXO/69jWJxRDIZpewScrGHEG
Gz17P+ofWOs1jlsKOL3mkb3vsWjopJpucCj4DX8Ztxcn/5goryjNBSGLHYMU1j0LJj9j/1tY8p/V
W1gzbTvj99W6TbskwoYCV3qrGd5TgRIRkKUj8fHcUpgEXapnWg5GZHxK+pHvhREHXlc8fiJqAM0h
rZkwBAAH9qdY68bAUGGvhXOOk6RSg6RZ5MgGKcObwKyMjGHLBQwyrQtXp6NrImO27jW1+ciZeDRW
Kcp7ALygV6FClqD5SuZO9hKA+KaDvx3AJ3RxPX0y34s2gbixbAffnJyDmEhGW2l1RreyVBWN0xHx
ELYAWZxiXau7elfqRP+UzArUg5V6BBGTcBfqwfaIZT4k+PINAfoMrU42m4h8qJ+ge87Z2Qgt2FZN
LEDNHp3Q6yuzcU/EufxAODY2fWSTIwzWWr5oMKPWrNg9vy39WsDNcL7Hq+gUJ2BkU3/N1rMLkmf8
bd1CudKq3aQaAyISRZHWI50wjxq2V3V0WAj0SsjJzbTrjhD8u6aPDzVzkinlEdlhprTQnwbVjadd
Lf43Au73gJro8FVJqLxfmAzC7bt5o/ib8n2929uzOe09bBv7zCKgKiV7+lywGplKyc3odtSnvF/s
18ZmxFPqXcjMn5ZpJKQW53yhrrUvfCOEXUZiRGCnIXg4CgnkNY40PTdT1QRrClhlJ5fp5BJbbLPq
KD7luLiwXO/M2Fkhjht7CNjq7MdjDPzvivQvOSWvlvfIWBB0njveVfxSGyxVYplqq22sJxDG2Vd5
wpz2ODuETmHgcLAeWL23nYnDqJIjQzIPKGjlHEmt9ma0eKJ7Mtfzg8g8av47rRGFw75ezZUwzvcD
ekwuFcgDEorslvTjUkxEtlhKuBTGROUpxixz4aIM+b8uN4Axombu2fTJViDUNbqxfQiM8uJR6Otb
vremKWSqjRJV9hEHOhkP/uHpJXMdcWAPzrNK9Fd1+Q9Sr5m8FoxlYkSr0fF+bOOf+GQB8+WFDj6q
SO1kUWBZHPfP2opLT2YstEeL5EBZXWU+w6Shj0/nsEyvpoaf8Jni/6KE4Q1XjineRPkB1I2aTYTa
HANiV4rZ+4nr7cNpODUWarAGMOhDeBO43wZENidBeXnPAQZ87XtkUy4vzOkR5rVZGNeYBJHtt4R1
BKCteIayGzrUo/mwW1tOzl/1JSqeitHRtTZW/5ebuQFQyMRBLqUbXm0Iht10FWMVmtBtfnWH+Y77
783V6kh5+eSnpkY9LQDtkzYnm9DTGegBX188yJ2ZLHssCga1yROcg06FzS1KB+rSskNV8jOE4XjQ
GffeRa2vYp3EGtHIUPsd7SVUbD30zrON3pdV9hPMJ+z5ScQ/dS/fDYRwQc+sDZMbzibX2u/qv3e3
9xqASfch0yiMNcKoaMyZWy3+ipGMQVj/+ZoT3sY2Qdt22FTuBcsqfc8bHeeqgaQCsyYyvnoxFuos
lM1IONxqDY1q4BZoBXM+WLWugNx5w2CRx5S1o7QSLxiglNh7wYClvz74Xd6UE+7OqFtY+F4Dozpc
XuDstqZRekTKUqDaDs72IgjZriTrNgYiMd6FfFxhl+VHYCZMug1BPgi+ngUvrFdsOmHqRGWOiqcg
zzmHd0hy0L2LfVaOzmn0vzqEF6ew6d4Ov38jC8PLecPVG5lmTUjOEh/enj9MZPDXIesn9Jyy80JA
ilAmYeQvxgeVOD+JdogKsAQHlXFFXiKmFY9XVPBse1dFFx7ccD8Gk+2qVGMDLFAqwwErjqEPUhFw
fIukUh2xIkq7s/Rav8jQLrL68TVMz6/CDASFPqIdyCQC9LY2zNQmr6P014cf2JCOHjUuT4YMcR8k
Fv2rHe4rJILjaxi5eRZm0MTWUxegCcLU527nF4m5on4gAix7mH7gPvVh1JakVjbPD4YGS2B5mNwi
bdVcg3jT6CZHlTog5wLPSxTRmkuf7Bt0iVCJwAq179AOoRlu2U7tg2nwWmvtIRAVPlw3tHaDbbji
MwL+S5w3eBKlQ5HzRg78BU63cZMU6Jd/8EsTIW1m07vaYVJ9Wf/MzZUudqtXZhWqeXsvg6StYKtI
RqkyUs4g/0BD5IVxQOnZ3oVl3aZO4OWOE3fkD/kjgJxk3bk7pDTHKWgepDc/oyd4rcb+lUx+9kWD
ApKHo2TToAt3sb1GEj9V8okqsE9vfDZ4d9bVCVHbCj6sXbn363PTGYE4Q6knoQWReRzrkiRtR19U
HShm/ywNwR1QcoPAOwENFaKK6rMspjJls5Ogdam+YLcPZ24QeLui5iP9x1EGk2SnFON2vPr4mfjt
0vo7anEPvLHHhySsixA54XyUBv74L8vo1pyxbl2qqzzMzECGLmsrs0kp1Mc1cbJbYLimSfasSd45
zzvdsRG35FrBo4UCZ3EjKL8sFjxN1Pxzffsw9Ce+U6c2AiO0Gt95lDwR47o75n3KuRe8p+N0Vr+c
xgs9eaMLqe+EOqnvnhCam4Bc4/AnYisIBiTXP3zUCVLDxMafjjfC6Tnynfi+NHhXfrtx+UgsHtEi
R0V9MHpENAHqdPIFyRA8BwiGqKk8CXIPh+05g+PH+p2UgiRC2Uvao8ZQFhxTaBGr0egxKX9RKC3n
R8jPms0nS1YnA3Cnz19rZn6RilCRRh0hwVlyy3NG8NPXNIOYQjwvJiX5V5l/cwzB5O++02vJtWyZ
doMt26XgJccWVMKY62d/B6JRWO4tTk4WqWASxcJ8gFCtathLuSsBehVQbea9zzzbn0fVPU3PcK9q
UxQhNJvKXJuM2XbuHCJwpOpL826kQ1OOcvfh39d2a6jEsskLErVHN2+k0KxOLJF+rcYGSEaNTFPC
ACo0rTDk8TaTNBa4E5RRGJsrRa8dOpIeUDch0tuFCn8WFBNzyVm6AxQ33btu1WYThR720hKg2PjF
vnQLw2HTn+oad9nK6g1EtGeC76CuU3+3rBa1U3JhWcHB4t93qtWMV/+UZOo98kt63eTKfs9UNfaU
noeOf8AfAgUzd43QgEhm5dMCBCIN9z6K4ynxLrE/bJQAkEE6xN6cy2d91A5Dltcvtuh7XLnxZ2VJ
LvQfctAHT7iKaTNjgL1UTmfIkH5OFtP/DJzZ8rEwEAOP4758K2JdJry4AW/d4jwmCrh+dVDAa0/I
lMjTF4xEMSAFppWiloSRNDu1rHFd5H/j9hAZ56JCNH0bwxKPsQ5mGwa2bAnWRgu78Ax5BUHWjF4w
P+Jenus9YgyOUJclS904N9lMXJKmC2BQBBs/CIqqy2kI3a8XbkcmqFzNTW21E8RoAnAxkxSwC86t
YrFA/mD3VuXqhH5CIySgn/XBoZAI5zSTNFq123eF7EaY5iQnd5k2/Nad2XeTCUxkbh0KTJqipUK7
EZmOOcGQIw5SuPxruqFd3ZPNQJRIWTvUwbAVMmMI+un4Bdj6zEy3dh/0t6GcS+KQZOYsodt9hg3G
Yr/atzhdtZ0LED/jNhat+SeDjsrP5XVaiWXFsCR9VxADqKNcJmGeFDevqsbbH8vLncIgm2jiRM9/
gi7SJB+DEwaAJx2AOGzI4Ls8yvrTTOidUvgiYE4xgjdCtDQzlDVmhYm0jZPkoebrOPnMy8MysPbP
Cc0OW8bQ13qHCMm/Tt1V4pzMcTP2o8/E+zzZmskKn9Tfotd1PPD8flv3FvLXgK8GIIund7N5th3J
9fPTc3csA63STPSpijaRdt97GKxB1kcPR+ICTCtaHIAUJ6mO9l5ZPw0UY18jmAIxEEV8LFAAuVFn
E6LXqca/rw+KETjHL63fqDg5FlQ8PKmg22uMzyoEFUv19pBlAzNRMAslIj7GDFEhEawSjhtzBDn+
4ZVquGq6k5lpr3v7FQybNBV3I4H7mb9IiXsri6fUHr9Nal5vFAHjc3M/bfAB+sEeLymTjUzcbPJ1
ky0YuXdE3J0iKB1Y1A+dxqFO1NuyN3JxL3s25T1rm/xwypym0qigE2K/gN3bLdN734zjNMXjwivk
XAhR66Ufzy0+44zHd8Ms7v6pJ7kt+ORjpRZSf1kaFPvHg6FIwQFQ5eCV42uk//K7VzC6BInGyM2S
5s6IzZgvWBByAL/CtFkzBOlXJc8YPqf7dHfXWxXXCgR4a7Bd/cqGcWU5V9Gmjcnc9UnbqQMy7TUK
qn21+76uLsF4qeGDLc8HeBDz8MKK+OQGI4lCTUIpF9ccRYhZyeneS7k1JMiWVcLYmXzDj/NkeyNR
t96UDLv+oGkcepy4C/CaOkO2dj6kU7R6q20bGa7o4hQECvGiWfqtm8xXM2pg2g8bAa33N0ACR/Wc
mWEAHbwbgM9gXIUM+YBT//TPiBO8d2maN98MrNIt7kZq0RxeMxbkrNbyUwOEmr4op/fP92UmMewC
YrphvEFVZvqiYiuIkGo1eBg1CYSg+dI0wtOluPEN3NrxvVNIwtfBvyWJAg3b2M5hIhaw2HkR/40e
Ed93PKkt1s8hdIeDhsIsY74eg/Wdd34CTPvwuk+lvNT4nWZ4v6qrnsFmJnBpN2kUswbVcBAX12bb
rc9vv5fsZ9G1Z622PIw/+dAA0QUo3P9gjpmAvJAQvDeyktcfsGGD9ASmqgXDUHjDdBjFuSnq1i0s
N7EHgVagsInRDgIqaZUNK0nTBknqeaxCri3zCJpI8h1t0IkJfjr7rk7pJGz0+5dBjYEV9z//Jino
Iop1lG6IlBXAVOdcR+j1hSJQGQp5UgVWyLrqkHFSRZ3ODElBRu7CFYhvb/hp6oph2/UOieuSHtlK
HgjtlwW00p56Ij+ARNl3P39YFK/7/B1x71tVfqH/Regs6ZnJNIc30gaAfr3SN0D9cSw3ckSwz38L
C1MwafSZMgqcT2xb50sOeHokxUYZL7Uv6GXlKK4tUnY5gsNIFmh+g6Ypxfhw5eIzwv5TfWLrg7Nd
gokvtc/COMM6JGseXV3vp86xWxJ/FyFQAYq4UYtu5mxGHPeRrCP0GDUUFBLRdqFgITLaGtxtiN5l
Q8zJQsQhNgrpFvnUEyUU9uasFkAvsKv8apzh1yt//7vDKtlhisRDcTZM70v7nTzffChZGa0V5M1+
T+6hXzItHh/zlwnUPIFbol71LO8X1obvjIDuGI3M/9gPbIF38+p7Zfiprs2xgPrDfr3JcDKalcre
yWyDgwBw3UKH91qkl9V8wLKFrX2pPeFiS50vkP3cYYMhCPnzlxDefAR0iyVvTgnjG9MofFHH8YQO
KzuIdwlYfyBBkrXM56R3skwApZ2Aipsi+xQDkzLpkO5+MuM0q0XTLxSMTw42rSqckj0a+LE6Ph+L
oq7ZgsmV2SXHlVHw2rUjOUmautIMlItCIP98KEhua01ToBAkn3qJv0TQ5qydmz9g7uvRz2nxQvam
QBRHUfBToai6/IP8NN65k8uNpt+K5PcjHRa6Na9ffce0hKMelozkrsTLf2iXbKqxY8S2MdUYazkw
vw0i3aqfddARJLTPY8R0jAXEEC3A1hQ6wPAMybYSBiIK6vmdXrtu0ga0pBdYruwEnBIgzZYmH3xf
swzNorbbbiOOC0wa7HeQTRk+HAHILXDV24yK5kwj8C4vuAATZF9bRyFCjl/RepYeBlGdVMbqRXvl
N08UhKwf4Kb/v1OzQWCJZyuDJUoe/r69nRHyl42ykB+/oOrxlsb0cIMS5OPK+2uPZsTlZPo9AWHd
nQC8IyEXhPtt4FQlMyfD9Ipd0atEanE+Awa+csOVVdx1Uqku9Xflhv18xQEBt43XLz7XpFLa49SF
asBuw+WFN6+c2HOT7kOH3Lpjo0P6rmezao/SZqnmKhDpdLqWT5jEcQAFtSNpnHCjvOLGr3ExtUyp
NAaB2la2vELh1/epdMiWGcRY6gGcrQsfMl3qc52/IX25J31C/sq0EaqN9HpcMSnP3BMkY2/oJh3m
x+JtNU9TtuJZirNf2+qbzdq0JUcoawPAeATX73iPeRBDB91Z4YAkTdDrEUDmyK/xj+d0Vrgxrg/8
i10QWXzPMVZ0V9yFxicQeGmq7IGUz+y/WorYNk2WTuxrV9WTp9qhYvHtqU/KuLLFGfostXAZpPoQ
yfr21Ap2tA/mTpTwyfINM+AAek+xoOjdirxRmFmkty0QWqUg6T7K/cwASgi5+y3r0PZyVLHE/Jkw
wxXZHRrpw7cP7wT/iS4qV9+Mbxe51t6kGYu5+kic1/GF9TjYvc1Jxh2+f7Dz647dmbEN6R552ZM4
KbT0AQX7FrN6pB/xxLJYXx1RoiNYtK6ZjbogAOv3rWuMiCPzf3LG5pXmFmu6NwSy2OPKWNlAu+Un
0deEWdtAcnT+TxlS5N54xxghZN8/nT7O2bTSlLrgS3mcNadp80VDBwLAufpjM2hzZ8wHChZn8jYJ
lnwlzQLmmHHZJXTp55mIBLUEjnCAGTf9t0u5bSYRrpOQII6gObMt79YzGVMRiHChQpRwjUWMhZbv
ATlHZh4qfgsqgzPBlKMJ6LW2LDGECaiymdK3wY5Tzu8NVL6drtWp3DlKuUnsF+1/ibiThk2Yh/ND
fQtVZbwVf9zmW3clx/BzJYmyhZngAz3pB6EBQQQx7Ke1peXSRjOdFDE72SX9qV8oMvhpkUn5ZRK8
918l9n5LxTRZrqlHxwvaSg+fz+BmkwPjByl8Dou+u2+oE4LhYMGiiEUPzG64KQqD6wlmw58Em7Dl
1AajF6FVYu6i3SW65FLn07/XhC2HeQm9koP0higuFH53xpkpwOyjL7puMgc3HpF2qj9mNCLwrHAR
pc+vCt2LBjTuvMz37WxLT6QfCxRoyyxSqyYhTpoIdVo2U92qBrj+YnbySD/zce0CMiVfUgUWrhbG
iRN1RNtx73bh40vw6w0wxJepBZvNObMAOL4Ld+GZw2Q9u8reLxTv+OxYTIj+RLcG5TfUvGrlF7tr
Iwsntke8F6rG/kaa9hM0hi5d32ARqQYE0rqFUKOM81bNeJ3upDHPaQDr5nxzrBbToGOTxJyg2qxy
NB4VXGNnjc5IdjYo10V4aUJwKUAuLc1inXm4o+9zpUAtl+xpDaqwiOiAopEF5wZadnwsXTDt2EBL
dsQntmzNjZWf3dOzZI9t7Sj7a0/iKTH46pdU/KMVO0QZIssHih1i9dsO2QxQeMp6FFNqNW6QOhOl
9N1MkNxprVVOk1HinugXTi7u/rx2GKieVGuxFYA+67qERtUvEk/vtg+YRtZhDeoIXI919O79SFWQ
QRA7Nqgb3F0wzYy2TdEr+QIXvVxRdLhImJmUz68dEjZhFmt1m3pOSuCJtJXqeNhOKLAxbz3Zrbb2
Y7npyxdjxxbCsJJJgNQ8KKghLtT++O4B2pXtlWra+yNfwLEVX+SM4mpQCqy69pZxq25MJNSilXbS
b+FY/ZwQXDEVkP10QkbhJZudILN1tObwtAbsG66JQhC2TaSKaUQsPGL9N3J94t+0sUOQIkdZUM3I
+WW9WAJJF74Smq+f5EMy4K/8nqjK0uq4TeoBwpexkQaBFcSvib/CvN+gCm5/Mw4ezjhPs16rSar7
asyjKEPf2hXWyhUU0DSZvFazRWSCwA/utSbDyJBWSJ9PpiISFsRfelk2J4o+adM9yt6VzbbskAp7
6qrlCEDWsYDF1J1Byuo1kq3+Zoim5FB9w2QiK241zPRbZ9YgXwkg4OufHxm5PEi5FekjGEEOVYSM
l99jyyWQyEVnOBENnxZSGxUy5u/+D9SX6SUDf7x1MkRu3t9YnWNMjSq6cVn87MoZQcGvKM7uiPn3
e5dh3Z47vmknmAL/fzPMnfIhKtlv6++WCvwiEMnZHwAn9ChFKYJ5hqWBswBAyM/B4PIapJlxzSve
Hfh9XSC65gy6bVs+aAm/5386UfwsckR7ncC+nM2/5zH1HqxTEySRPse1C0hVkskuwqOXUAKxy7c+
i/HFpWv5gfFdis9mDNv9ksquSWauChybBXoFpFJwYc3uMRV508RMWlI/e2vy6Nogeh3fLjncdbzE
8dDl2IdG9AGS8aiYhL9c8UJbgxjL+9h7PDnMMyHyZftE4NjvR5npqMuyq9qI5C9UFpSleZyp4dcb
u+73cTbGxaMS65bSz0jSeznaRSlwdodPu01d0cYOgSrN1gjwi5oGFzWybcCZiXc0ZuLLhVQ1O3zc
mRoHZMQ77KIbFRaWJoo/Ukucodu0OcyhZa0CxkgyjcrZIn2JJfPjNS1L/rLr/w4IS/+xQD7PE0xJ
gOM3AFDuBnkpJBtIolPJp1iG2JhYYQWb31PQWgHCemNiaK+jk+J4SBl2K1lMScsFWipuBOPfzofm
uefYxWUqf9SYk+6Qej/rrNLh8sxgiv5lOMaPKGypAXaL/KubD8ry2IxiMA60DvqAzBsNR3IoO+/R
TPUjHI7xpWq17GwTlLFLfucOpQxrBPj3yqX8O0cVWDnkBZaQU6o8AewhbFIIEQvq3qYXi9HeolbQ
fSDIsxpeecKKG7xjkN7esfu3lOxzwBkG4ti9yWr98BCzGMpyxtKvmFkjBJf+IwAG22nNJFVShKy7
vuM2bvM/3kXICZrAwQplc3gY2vpamlFPgbiIG6UeJs/x1kJP+xtPC/9W4dJsfFjHrUHTHD0G+D5L
JT9whvlp0PHwK7tyhqEyVkP9MRonYmqqlPzQ3MopMhd2T4BWjoBbtDLebIrIccLmIwu8JChui6Nx
BWwlYD0OidEEacHim0NNdBge1nSY86vfO9cUK8MG017r5lYwA1zDYeXsL2Lby86RCmyrWH196f61
/c5Z+MR9F3rLTejkKBqpokucf7Eq7GyZLg/TLiLttiOLid/KmuovDva2eqc6Bm2ibph5RcsviBFE
R+vC02WIURaTkAelpoWQFQlY72oG3qW7+dED/X99Ps7yqwlF8P0DCR34vnRcldt8N9JocQN4VZg0
ZWR4vq1av/7MsGh9NfmxEQQtGjrnMc/qCu/6SkkXS6x05j85jk/1CtWkE2mQnLDCybdRwis364uX
qWMrBAQheuwflFn7VPtQybdKqyBiGAZjSgM524eZQxHFUj/0M8daIUxi1cYIIajJY492hOia5Bll
B0n+n7vbUPGVwbZOFQdyU2DYkfS/wTlHjV5H26PqppyU4eUFcUdoR48rRqlzMpPtbf99xXHBe6rU
l74wO2StKNO4mL6YT/jnu88F5sfvT+hCxyJ1gElehdfYxJFmpgoi0fbYx4+ksFhzOPikxMs2Fy9a
UL2Y7OKD/ze46cecUM7fA9itHJMNqqHiGcmg243P3CGhu8289Aa02T59hgqPPHeP1LHdeRqirp0D
q5KCBXkrbRXkPScc1+jcfoPAvRvorgFlCeilPgZQuWrO0rTiztHoP9KQHDHsG80Ywpumxca4AM2B
EohgvAHf9TTHKX+wTlDd/kFIgGkTngkQIEFqSZ+S6QpWYWEimyWZMf+DRkJQ+kUtp2UfxyGLVeoz
Qrc8vMEDRxvTCQEdoI1I4QBdlYqW6K0XAVrXXakwRjVp8KbljR2ys+rFCWJ8nsYUlarNM/6Don5s
dDSYbFzPFrccNTVD6peJOLcdFcnxBow16vN9/kjRU8e48MehGAohNmCtjOov0m3bK4fOxTvDAvEx
/1dHm+TfCdYXD1gMrIhACshocUXibCQ3OrJsPcCPjFG4CyAGLjnG9jAvzy6quqosA+oiwRospm6x
DIEGAXoOLdZimHFXgfIfTXXf5SZ3XQjS9P34Drwd8HGjri1whWIJ6oyfJLOO1wUFEUlZFpRdE6/U
OinWYwb6BWwpSHdcO1tt/gdJrP7gM9gOSVy2ACReZiElzqf+CkofHAmnZMIkAlUPzmoN4820IXgk
7K2a47fQCYqpZZR1IhysjIV40sE3J1W62kxCDMLLAkTdhvLKA+LL1/Y6sSfau8vCm4ACbCVeBVwH
QthfcS8pxtgao1Ab3fy4jbN+6U2T/HdTY98EC8LHaCq4GXWGsE+Ve3AtzuIo9junCAuyqEkqFcZ0
Seyr3naIzP6L6GX+KMQFWrHXX8lfXSFQDpx/Pl2ECxm9sFcTlQgnHZkKJQyws790bfW6O0RyujKv
9THjWoAQ57Y58CjKRrGf+KGo75mQQhbl3JT5C9ZxNbbaUYGYWQgOaUDsdwpHvNrv4+3HBo7gnrfa
Kpt1Zrgm9KO9zG8fOxoYqcTEILDY0sqtrsTCzOOBTJy+AgMBOlwioWxG4xjuLodbUyWDCLCAogMX
NzBgoFfHgnTEQ2d5XuAewoV44uuTwjdG1qY4BmZhvq+MfF34MafLfqjuGgn8bBhFhkUMl6BUNfeu
mv7Uz6yrd+bKELMO6cZ3DY4LBxE6YWtMX8at8HbW9lu+T8589RS0S0UyvAkVU/E6y/ix6oc3iAoU
WcAq39yQdR7lFXnAVpIKvBHoqeEjmeK4nHrPT8cZb100yq2RykxHm4kHQEqNcLIdFMlqTyUwaFqk
/km4tnFEf9+da+KRDFguy1i/tyI5fv5aA5SEwv3j2JrN+gX4Nqv8zT2dsKbqptmACVD5a/OCzZcx
9pKKFPx7MK2ZHJTxabtcdwmdYpRDgZt6LoNqZUB3wmi7SLtOUOl1YnDmLu9UvruDTz4jZ16NoG7D
qbeJXE99jYZLRQotb+CI7t2Rsa+QI2j8VPhjqGSgsqW7sz/MHseKqwdSXLDeH9CB81wB8BXSZFAQ
9gzzsPS3NokPwyfLJQ/772jKolSxNbUaWoY3ED8m8dAWGQwFOBrVS5xWyu3P3YDGn9ZCMEE3BMvS
6ZY74T7OmJd6t8uLwltuAJmseMbMDNumDFHxCnV0hYP8sWRXyhn3y5r1GFR8E0toIAh24bt9C5mz
r4f0p99GmiSN8HXmdFSiJYx8L4Zyoz+GJzqVRk+vH+44rj76/vk6A/Z0CtYX5BOWuUdO2OtuDkhu
dW0umrA0WmOjLlg7d3XyLXUVimievfpCp+Vfctdly+aHaoGbS59X+32mz4X+K9T3jC9sqRGtIssd
X8S41GEAhYDXVvklnXwDT0rb8HkzrbXvMkFpzoT9IwpR4ptMHji+u6PZ1JQrqGKD9xNc2JcSMpUt
88YXauF5yMIW1svK/v3hB64F5Lu1qf5doJ5BYMwl5r8sFWRj9nTEMo7qMzeUpxtgBtUDiyEGA3ue
zDvCggqtHMYNong2fY6gLS/jFfCzf+hk4DS57lZq9BvFE0F15VSQPUssirg9kv2nKPvXcCqINx2g
05bl+L25QY4yy2cM47usZLbSiDPRAwxx9vX/RAyayidWF+fDmTnVl3G7bLpBw0ytXkulqk4aNsGm
0eeulkcF9xIoGfU+BOkES7edqMO2cDpp8L8d+fcj58cxaOxT+c75m8rhq3kLmvRO15mzxwxayQW8
y7pn2sHSoZNtd2DuaP/mLODxCFEa7UEJpf3Zv2jURfWmeclRrbr0kAIXp5Up3WLva9GI5Amx6qqF
ipY/ajxO8e33KGKC7cy2KJJPBC9WrgqwUP8kuBT6XQYE3T36Hz517NtxEym+xTOxnaT5rEFNEWUa
QfP9xYE9udkQRkxROmeRuX2J0U/IAtQs5uOS2ZzmHFuZvoKBtUH9qtIhVueUl54kI9gNtht79AAn
nYZBWIBVTcMl345X0H/f7qUZHKDjl4Y/NHtHiN3sigZMVpVCQWlaQV6c6yJIQ+ZzbJrlBR4iASSN
oFqQNNHyRZ2DRJHjEGA2N893tYB/7qjkM/R17HANTwME55plVb3f2PoXzHmjFPk9BKtXbI/fAkQ5
dloB0o5MqFkXLyweof+2u0twxiRW26mfOlBRXuFfLr6OFQ17m4DoR1SCCEVV/tAC7YSoqvgctUs0
IDe59LgTh/ajcS6+Kk17a5rOglZufcPkksfJarx7QttpBbL4EYiO4KqS/kZMkj9m5gwwv0eJHZ9Z
4fDaUwcSfwpBWSrtZMPfmTYC6/TTisD9tEZGVAfDS7CLJOqlf7VCdCVbFHo+IwDRsvj9QTQOdqFk
SaFkbUiweYVdsi1mgsNPJrLWIWIIlFyqSg8sntEvrkSHjDrKqEhayEQi8rhpTFcoeNg6JAmbyQ8K
Z0wFC3ViZeYHN2GAxdHB86Q1uYi3Q/AdMkxwQW2CUNTentqgdF/ql87+P4bFZTeqFimU/ac5/3l9
p7xdas5Ymw67S1AQuGAPhxNCNyBnv9caCv93coIrGKs5afqLso9+SPmvlWsonkBtJBt+qBb3NJ9z
8O5QwI64vmkOkw5/r2z855arBq/gE8xb/Nuv9vNjS3AZAv7dJw/EBUII7KIW52Ot9WV776RadFPH
PM0kXZ85PbR+ZPWC7nE8SmWCflUUQvbPBTFXb81HxkWYHixMhCquZ0jb0pSPqWAeRqVw2+MXIXAf
/yoIP2yKMP1RWmgLj/QFc8BXqzeROB/RWziVHJVf+EtduXHb8n6uclUG0aJ5WQV51qpQKHAALzFz
6XkcQt958yQ3YpVM36YHd7iiO6hbCYhDCRBv7dPzOKz7wKxoCOuEs8Rj56xOq0AOxPBGqkZ1q4mB
/uDcu6UL1IVyzp3AzC/TKpUdD1KuehW1b7C7sF9KD9ev1zIHzpB8gswRO+grG9XdC5V2YsK4nGr9
gp2uNZbzxF9h7MKbWKwzKZ5HPROeutbu9wSt/yPx+ZV0/SH03xk0Xx7emoSnN5LjBut0RG+bv6je
/XSzjFCrLicx/7L89orXxe+EcU+fmHl4kU6rqWRJ8OIHNyoDOOIK+7ifsS97gGjKHYFrSndPfPuF
bLX03sLpFQ2k+41HCVMeO9qg/SvMw2+yByAGMHt4WbTHGP0fZ5x4whd46ooBL6zXVSgl640yBWOs
PYl9GXKARQemvzICI7tL0jxpAjHsffbcK7K3taEfOg/cpAxKwsmxXsRIdJYKnSz3Rj0m3+AjlfEt
4XOjJVQ9x989w0z/X3RCMH/EFRLxxsHfnMMq1l4EnCDdaJLiSVQfkm2rlLtFU+hk7Xfkd8mnhwkg
t5+cTSLvSwiBDxOAbD3G/XEeSC/8mtKoLRGZASnJUROXnuGC3S7wYOPUY8ndNm2IXk7NxfSFgMSu
IZfHgg1zOqEa7J9oaDeIHbeP2KqMuOKIBr51430spkcun4MhAO/uJKZCUwxTvWbCxJM/LPSyhFDu
punfcFbTqjAxengvYB3JXUKGBkCaPJTA05lOaGPD/nibbJKf8GL26EeF/0g4Moq4iJhSNEPCyAtq
d/G4rG1njBSGIt3YIK9Aso9XMsueQkJWaYrbuAte8LJO+D7Tr0OOuQU142E2Tjox6evbvJ7xwibX
JVC/hIx1kvK8X6c11aiHKaPx2QWVYbHNGZNoHosuCO6AklILmgldtJzg4omfIyWIVpRweb8K817u
AcjIQHsc4IiTRvQur/HG+AFLap3FHyzuEGf7QCNGl8jwMjbepZl25uoijefW0/7trVzZpVZ3Mnoq
xC+r+40AIhD34DubaPiHSFG5JXUw+Lnm5iaSc1t7yU2aDyiVMxWx3tk3ibHp+MIuMaFFhePOIov0
3Y7tkouss6UO3AgNzlMPcFPoW7kQrUe4wBxZw+naa901ByRRl4OQ/Fuxtf9Jpl8YOH0aNNUiTXj6
LSkFWePGoT3Lx7yKqGDBF6WF8Q/ScaBbFMkA9tplwhwUeTTxnT2yxS/IDH90PSqrGQINH81aEDBb
MA+HmroOhnZsn5SDnO8mzR9w/isvT6gF+SUp5tvx633DnmqZZDJr73V1mXkcJ93+Nc39YsL7/z49
6cnyeRCgV2f6LX5khOpAIFjyBjd1cb/3LXiOIBV8IZIFaXh5LkcF/yl5iJ1nSm+EZzSs8A06GUrh
CegxDmB8SABe7yIMpT6CMibyJhVlEOEuWJb2Xrassju8rmdVAwVH16D3Ga94yuXr3rBleqYmP5OO
D9L9F4uPr5M63lUsWPSFmpPYUTK1WYlP7CIaDWArZQ6U7WCtyPcZ+sz3i/kReus88dhSPoSVhuWZ
0mzcCMa/DcFPbCG1ufFUeuh7Ru9kyK3wj12h5/qJZOpOCueSy9UTjr/tN6U+NcMqifm5cVRwbfMw
fHZsaxJrsilmYkhwRvNa2jun2042lY+mYCSaA0nIr96wroMZgij528btpidSBYBmw5zmqR9Um2OW
DEy1YSHvi6Bq5r00rEdizxLrIvZomxMwhh7oESPwshvL6iZY4NLw1juxpVxoDYuWlBYTG01nxsqT
y1DhhhSPjLp24VqaUb82UpoWlvPdA1VjKeh0ovh1VuDI3PrNdYWY9WSGLB+yn7i/tdklyc+lTzMg
QaniENqloKfxtupAiuKFbQAkSnIfWxYqUvxAZdbmH/QUafmNZizmxV2HnfjDJ/IVwfoyobLlc4XE
rVjI1AkUCg6+zR/UwZFlAzcNKdzt8CV8K3PQ2CJndzlbs5Le4aXtPvCSzCmXTBB4g0kkKZ/NKZZw
iafbxvZyBHJUy0Wdlehe7thv/c0Z0Fx8TJbYtTTWNcFlpFUD/sSebK+Wm5aNbwT2Z3e5vIrzGmlw
8URgCehw3UUuFsebFeMrmS79DRq0krYWMZeyDsG4MPOTDWIT6/IYDovjvJPhofKBgdhImiiWjxkL
gih8F+KAxehrUuXk+T36CyhPyP7fVdiBXw9kCTL6zxyuR6jfLKfi9kipYh0qL2WRLAnpTrke+oml
H1N4RZXEjpRjeCjeAm6LtHnAnkwAGj8QGZXDxNFQFCXFeY2mijt4IQ1oTg5oQy9CRbHwDmLwb3Uj
3nO5syIWA/8VYo5Zig8Z5GrshdBivcs5lrVTFMDo8yoHh5F5TzgjiKpV/8qxywsXT8r54KuvuJIa
Vg8zWjadB2D7yClfdnDl546FnI1nUqlNdRha3M6dPZc6rLaA9hVFbUmj7LfLS5aELsxL6GQ8vqev
NT0Sytz59h0Uee8BIfP40+XC/wkGO+bCyoP5E/VW1fiw9D6jzMQGdXnF/OSNst6gad0pe5+gdqbU
2PP5FRBEm+97hem/DTXmguPVOIOzg2BBBg7rajt7HXlIwqxzKBnnlmCHJEoM+AasckFNrsqjSeVs
hmScyWg66itv82Z9MpcIMwWIbQnp4Ff/i3pkx1dVCCBAkaWT5ugpv9+tEVP+xVG7NbtSWsPAh8Tj
uWV/UGYgS4mNEgJEWATLCXFujAOG5x9y2K4Yk1hcZxjamMl7wxIFXwlOC2+FIup8/ur1oevlwg5s
u1EQ1GjHaRdUjchS+irzk7IwdnG/OFX++73rydG78E82M3HmrNig44K1SUB9P/lkf7jEnwrIeyOq
tKY9NazpyiIHgjYMR4qKpIV+Z+p3Y6Z4CslT8x1uLHPZJFTbScYw8C+kFnC7brHEh+sfEJiCxRns
72T4RgRuc+KEMV2s1kJB+8YaRIpJ5ZmnAEZY97KLGEVr9LeNl2szT9JxppwOWGawhVzGZ+jGI9EA
Ubr6V3Len3lr84ZRrZdD4FdR4SIG/kNyFqvaVwJQXKfShNm2WU60ZbgBJD1CXePywlKzJQqRTkBQ
Ui8g+4DRutlXuIXsAfV7Rej3jqZxm2CiGim41llqRsANLd1IQsmVdSLxx7SxVatNp3jNUYZ0Ojhc
nmjFs0NUdh8s43uZ+SGGi6VSXHkqrYXGw302K4aIfRtirKGShZQ9TpFa2B2rAHWaunCpGJ2bq3gV
SUPICRkq34nK4UUKWiwNxavM1LHI1MHzsV61x0oGkAs5vQO0Bykpww+X1B0Mc8Z8JqiMIL/3AGC8
MVIIztlUPmobrgW0j9S4bdyOpC4JtlUHCevXeK3q7jDHKEinR2dkeShqtR1SzoJyHAg8YTaeVM6J
Vt0SgphGNe5USzuo7KTPswbxnM4qqrLBj0pXtK6SGKIbkP50VtPeEM1O3L4h+kgLAzujoRSlvUas
+NnLTxVig2LzFtx0oqf01NHjKhoikfaqJ3ksTsI2oCGVbrmyskpVEiBcGoZh/lEN1eQlBxAJxNn2
J9bo045Yoph2FRy6a8oa5QuT45ns4CRZsxwOHlPw/4O+qZjRSN3Jx/V6B41t5q/y+vJoaHKkgqlr
Hej7SXUwitRaOTxi0NLj4Rdw2sBfsTNv653v0dd9hYY4VugGgEqorJUZ+qzzzFia5Z8GgOLTrnBF
rAzQe8TnnI0kj64Mpdrw0SIa8HzDu7u9Gvgo908FD3Gp8y64Zh/rKz9JclzucvlR3DzlHTRx3zcv
/I81tc7C18V1Sb3MMZOKB658dCC8cW5zfeTbDVrMwGT/OIZ2Eu7u7zKYJm+j3+C+smNiasGh+lpG
2OEFnyaMnenqZ73CG9n4VbZTYbLU8qaZ1p8H2zapOpuhkHcTwePRR3We8VhtAxArDn1XOwyFVWGc
SOnrMZHEU7ktjoFUdwdvkCC8wjaK93mhL5+ze+f8KiSIdCpvEfh833tGoA5uorAcFlvklKiuzh9U
i2Dgya72do/V0bvjD5ohAd4DbSVfL0ArlHB+BhPiurBjeAUfnSUIGMkUB0zK38yuSvbVsmCaZGuV
Bepm8/CTnddF6r9aspzUbo56cRxcKgfw/i9srhw7wK+fK5rMwqirQ3njplF8U8q2KKxd2Pa44cOv
eAF0UMU+uEUuxS54zSD9euCiwkLN2pqDvA5KdQFILIBhv8cmYOQB1ojgx32XQsFtYxlqOVyYj/1z
rzHF4hvBv25ZR6UaOYtOHy8ypOfDTf70dd0S5YGDS/kDjNX8rdnt9KLuj9bFSWerQCMfXIpepTbk
CzZjd7BtSIg59VHKX2o1U9AgqkKp2j7WXiSw+NSQ/n07rMhnJMPZZ1lWhd+q3U24BjSLYR5ptqMc
NQ/SfQg5/S3XKb0onVH9vGrjTIeWdq062bcfGERFpITe+MbbC2A9ykECOavoEbUNQpjzMtLwrQ5x
bFzuOXmdiA7Pn1CUf3UDuc4XOf2sCQrd+egS4FyQIINQmRNKTOpD+S8oqmNoz/majeeOZnvuAECO
l4nB8n6mWu/bBDR1Qs9ioRilJWwkQPTOdBobxXGlCHPaUe4/jclXWzeZ1xErtn5N4reNEd45BES1
f1WoleQb3gvWZmaZF5T8hpVyIDGloeqlR+fi7wg5yF6oEO6kbXAg4Tp5CQTGoPKB350AGyBKMUGr
yJNJ6IXdrtfnSedWB6ybpRK5x9aNo3WJVhEveO61HV2ZJzkJrQ7Pf/X4PDX9zOVlRjZZuQ819TVM
aPAoWEOyFAcgwBskSSEsnjsm5NsNdhSAKS1WTjeBlewYqPQRD3URLjPO27ItAA1WcRr8eaJ3NQFl
9UZXiwhAszuIa/8ryUjMtGZepbw2MlqFCOQSUg5JPJF15KGSDsD8lCBWmzo3efeOs5XjlPU62j8f
DVLCZfU2WPUAtumKQkrwmJShOtAWlDEtB21Og+og0pYQlP2nLr7ZLp3SayDBfUikisaKnZt4H5zx
rsMWn32x4Ro2CzAOXu34s4NhH+SG0Or4yg+NitC+ybmLvA4tX8MxGacHtEGxcAZ9t31canyqoggW
MIFuTlNxQTStRsLMhV0nTOC7Wa1yKGiL0Wjyy8PmBT33sBGGGv5jZ3fUWeJv4V03eFtkL297Fvi7
WVEI+1tiKR3XuyxVOHyYBnAGfxaeAH+W08xutp31GQYNY3YdBh/sBpCG3w73ereU0+/pprccOLt+
RTWI0S7olIEfWk9Gq1QbvPFeDk4OayZ8ad51p+ijw72L5zryDtppvL4orwFhOOPDGxM3tDYsbqf3
XmIMX5yJ2TNCEEpCkuvQSxtukfAbTdrCz8O+g5MJCFwXH0qFrjvsZyCB0/w1Y07PjNmcrEFpcpi7
hsl3KlYCQe0MbIZgv13Dl52aW9w+XLYV8zVpItMgrCMXbx0ZtAlZEEENrIyU5nB+SbI+xbFDPOtb
+YPRJyuXE+DFqt6xD/c+k9toyQKOclIKLMCtbsV/VAf5GvKYfaHK0idiHohVBD1ct7y4G3eq6b2x
D/L64meGKgkUqiClOzTbKTJWhp66yYLSU6jNKMVoTQTsM6dvRbnKxwi1VocMB76kbJ5XG7ttps11
zI34mj0xvWcfWMQFJ2BAtCRAyDjrF9t6GRVY8yL2m3Z5HQ7rvdLB4LxCfvZ9rrbiJmMzewRduA1V
3tN7jIB8B6ZUz7QHw+tSazWGFRYWp2JuThWDTrM6pSOO6ANJpGnFeMi7t5dlMQNhKjBFiZBtk4/f
iK50xP2sDJ8ArSVXQKIwoD/oZI8miyuSyvoBSJCi7Pir/2/DewxvjOAYxE3ZdJ0kx90CelV2dW0V
w4wawyc4h9SD6hMAtauLXt0yW7dH5w+VXWxkojPLXHDEAE0retEYniBLH8j7F28+jj9GK9pIRrOv
PZnAyVjKrFg/PEfRjNtAx0GxcpS09aTXV1TnuXhfx0LA1nAafc6paXXH0RKf0yjiuriCc0avUsgv
fCxgVAiOWKZbwndpd+cGbbjFeAo9jrAQGJBtg8YllgPb7pEMPwAP06/vE71QFR5ujNtFE/00blHE
uHZt8b7xVlOIlu5gwUeVhyCB2vpH7tVp7hvk3ewV8tWCE/LdJabzNhhHn3AAuTMV3K8ve90RkPmo
BmXrqJ1Oo4w1HzGtVST+xhJ2FRcWQGs36HoRpRZZ6JB1a5l5Kjo/AK4yjG1TtQs5i8cbq/IT3+Dx
0BvMZKDlBrdtSeSPR7SRzfAOnWlzcyopTphAQbkBi/rKea9kbeE9HmbO87/7QoNdJZp4CmpL8uNN
5QqSSgtDEDq7T4ux/7hfSUCMg6M9RHGDJ5oY5U4B+uCRlnNxTMrBuKZ6FMrs1fRGWhzRhxdMbJNS
kUyaNNgzqrX4nbp8gzjY1i0BDybjW3dBMJIzJRS0/r8aR9+Wex9vPWtKZHYxC/bjPATc8I083puw
vv2wcpScL+OQJ6SeFaBKdrjvR5KmzzSD7iBGvkN3clbR+XqaWcWp28AisecTZLh4xeMTl2J/PE+3
5jS2rrB4jGKllNw8hiuTlAoBJ7UErVkjEDYZ+lUTr66sH3ZJkzk0YuxxVGTcr83m/vnGdhA8NqF/
eRJiJKbQBYocYTGbjG03ENRiJ+Einb+PGa3arevgOtC1oG434RgGZYmAZcdv3JxMu4KbMX1rQEP2
lzs7bdIa2oJMRxFAdI5WRcIXhVZqTwzV9akqrUyeAOluBqgFa9Yj9MT3dcxH1ZvmA6RIs245p8C6
VWfqd18vCMblUHgyOnzTrq4N1CLqiy8AzD6cKA/ybF/mrm27ZCZsiPNGccEpj/PIHYWPIobG89Ua
OYC26ti831rlEIv11L8cVv1D5i/knJWS4yZ3lxAT7VvDfHTqz6mm3CBe2xavM6vPTOPWp22K2CyO
e9YS/7Pg3qIOhAtC4UcXvU1j4KwHHn6TSjti0Sdk4lfn00eO6n7V2D9shH0+laBN4S+QRUBeJHQp
GgNIqgiZg2JSCTKTGfym7+1gVNHS6hEeSZRUF/l79aTzTEi64SrQZsLl10e462O5ZVtWibgQM9v8
tU4k9QWM7V9XcO+MkLrK4hfdJXLyWB14cobe9Wpm6oeqRChchd5AY3Mu3/ObD1Qel+ItqLbqCjV6
keoBSW96347O/t6aY0EnzPIrWFAf8BBcAKMjTkapBaepKX1UWqFasq3o2NiqLCocyZYHCPVVUisD
9/aE4HyEOd3C63qtkuJqMfIGy4po/K9iOGaJkKGYzLOD5kvWrINj5QT2dFtyzbB8HNb4cniAXIAy
vM0FNiM26JYl5Y07FoIW4PIlJ1AmzgsmgO/mZjWZQ1qTCBN5dQx16wR81NQqdhAewNxNFJFqpcje
X51p4jpl0m3EQO/uljAHk5EKGNGGXJh7sK0JIBylSs5VjPmaxrR48CE0EgrxVrBu4H6V7IgE3s1U
jODqnLQS8bFY4FW3NztBiBqTjSs28OPWTGwH1mGVG7SadxWhjRmQK5pSOpImCB2mMAVt1441IFPz
qPysP7PIhts+9OeLUIgcFWLmIh0u4sO+335e8RYeW7Onvq/+UIfyf+nXzGzhzHsC47ZMnTL0L5XS
nyf8XLQnvLxN3zTxEz39jnNvLGFaTyAf2j8DDWPJp+rrJusaFcsoQTVRRzc9feOmLKhkc4uN4kUv
Zams2ftxpqrVpuhVi31OXwqVcShkGoSpQhOO4ASjwBrNxqzs6dZP+FZB6fgZFFGHAerp0u335GBP
8O2hZDLjANLhlFVEt6vKoVAMbwQ4xs/1vjAvR5WREhWFnlcOHn6n00LaZXfozShoN/YP11XvCxOh
Ck3ckCyCxRj8NgN3Zm9wuUpDtDhq0FT15kCxskINo7rkWugL0u3ElTKGHQoFVttwRNDxrMxLrXEV
WrlevMIs8r8+aACKdU3Hjg8hwO22nOZFhkhWH95KRYW/5evcI+8+Zhl6KuXu85/xfYo9WH9RZ/Kt
tgRa7g1uQmbgjbCSpMTiU0LBNk3cqx/OMaHc19hUMtajhCYVgwUZ5W0X+JY0E/pwkMFyunNPzOxB
U2NmVtByWefcp4mtY7n9KvdKVybvOZ1fhE6b8qkOH7fUTBGsc5IDD3AVNOnMya4Al1BOij4Ec8ql
Zt4jj8LXm/RGYAVra30S7dQxpF568nN3kbjeJ9s02OUC3rAgQ4czrKc/ju9pAUO1092bummrUtgn
4yRH2BZH66QCRalb2lEuwWE7FNMYkPc3bk9yb2JsbopcuqMAGjl3q0cgUUdFy0lVgjOw2js3iiyd
PguPX9UygmkaUww1IYTBGXz4RufePJT0b2rgpgtIO4hUIKn/ICBF9l4Oq7cYXbcA0wgn6PurjmXy
092ruo3a2+lTKr8WSWz70SmV64AN4nwxGQ9eZQMoBx6hqIa3Y4h2X2FIwA5ZVJ1NX3RMN+9g2AYB
pvwUHoSxNniWsJNR1ne10ldtId1CV3EkFDsn9On0l/kW/kxCpbnQ5yrueYoIvV4xRD4lz6WJTJZj
FtEB/IftFCTo+SpA44lXwaDp+GdjjTD8vVb185ACtWCdERb7L10na/+8ltOX4AqVie3RjeiWxw3J
dAmFlRkvZvrSxuADQ6jYc0G+Ec+ViL3FaZMPGGQ4mGdgrysKHJELjmK2Ww6iVPWqB8U8fVcdw+EJ
80UwdvstEVnEOkYymT7n8bmYms01MZDvtnoXq/JyIT/FPCTfIHTXyS2ryJCO8v83D+iChIhTP81+
paAerJ8N9MFBihHchQawa4mSZ3XGFi+koMcL3M1ps31CPAEEWHhyw/LXywMwFhCwyr3YQPdgA4it
YHIn4f2fb8krHrivmJzQXp5SYQgfisAhAPNvKlO6YdexvFIVPjJ+jBM5GfGF5Mz/og0KiXuACR7C
YrudeoWSIQTAY+iublVq5fWmWJ4h7tYFfzxMtzge0E37x0iOer0WpccmqYltzUJdcx6oo0f4vy6h
WJeED9sMxZb+cL22NazLLIVqS3Rqy3ZVWNeAWxqOYvidSfsrP0YI7gjmE6gDakc1pc1LskCG/iqZ
51MIuyh9VzCWD44W/cXg4MdWqrfLYvqe9PvbXzsUooiAldH94EwLaTlzOsvAbdTED7hm6pCvkEd3
DP+6MAHD8GHUEI3sDyZi4APeVxloVpQbdDTXTmkT+KW72PQHFOB/X/UCCgMly8umBA/JSLx3oiZO
ytgYy+b6ax5Ws3+2ldV8rFwy6Ey7F1H6SuXOeeUmY/cSmJ+KOVHxufmrG6dp/HqvCO6vDhEaeqp8
QR4RH0pddZFRSM1eq2JtnVrSOuqEXWPH9X6wYrBI+UWMgoHrAKQn2oW0SfqMxGsStPsd7fg5LQe3
bDV4oHxcytLaDda+7kNcunCWIvA4wnP+EdrGgxY6az3aNvkQkuFvhBbLyC19BMBbprBUhErJFez6
n05xgtlQ2T3ss8iaZ3iDTRgt2wkebpxnOCbIWi5eCViJM5r1mb5RlNRWddZMgZdR5IfwMeSwyanf
nnAr52M8qGTFf3rpQJ1S9bUR0nuGpLORm+N2rF38Igi2SQRGrwMRCMJ7vfq5MZ9D0rpG3hHcD84l
p2mbJleB/xZv21hJvNOpPW0jkclaZSytSkItdDuRQ6X2y3UqgY+IXAb5HGrBKLAqEr48ySvFLPde
kZ0twwoizlugK01shXZGb8gUWnO9v5zxpww3RZy7X6Fam7JwWEkQqiJUZtV1OK93Za096p0eyo6f
KYJM6UYqCyLE9hJLHhCBCLChwI4WpLlZYFiMpZ1zMnVDll4CHQ8knXk8a61s1IV/Fhyj5KyHufoF
2/kzawUknCapKCMfcdX+dk/DeTkQA6BrxUdGSI2YUArJO3VAulav3DyWCohkjq2ZsfGbYdfdiH+B
tmDsINtPOmz9fUYKmrkiKbw5c64E8h783Ak8rnG7uxu6c/b07Ir/C8tU+pXVZnwmRMeUlnSp3wNV
ASRDK6BJcaymFeqeDEtuNainCvFrdnxqlu4Bg4Urw6v7QQsxEU+DZp1trstoccg7Pbojl+h0xHqo
9PkG59DZHOUXa4eKYsk+S2lAn7rQa1S90xam3Sa/zv3e0GOWYQh7ygQ9OlUnFT7peO38MaxZ7bAe
uHuPOg8Zjps8fKvhpSjx97XtAJzloDDuTAkZRFIrQxUs5I6DrfVtHPvFLVvv3V0V3aUfxcFqKfTs
xIesQfnPjWORLSHNgr+WN/o6g3OXZHj4B/SiHbF/ZCKa7S1iJoAfEjknuXJ5ukMrKljBhN5I5lSh
2FyUZI967yExF5xbv7YA7tKmDSj/UVokt2uFwT6Z6OAFBuMDr6RH955GwnhxIFEET9VeMNuOiB5A
oZX1mC0FFpRsv+vlHLZZB6FZ7okqWAMrudBVHk3QbveRzMHoCRlXmpJST0Dnv82cV/RLGfV/Nz9r
qmZwS3y4X6fPOfejEyLxcJ4Pomt7UZyMPTSDj2U49OamZc8Kde4SEEc8PSv0IuyG40ggjBBMt/1x
tAGUI5kkfrtxMgV9FGB2WzU7hWF34FrmStUJ0mnBK/szuF5aAGXkmFm80jNAr7W1WjzeQtVDiGvV
h6/9lxJ82mEW9+GUXZ1b7CD43IwBq2eQKy5sPNOEkFTGIDQsTZ/nqtKiX5wx1+TZBgf2HK5sxVGm
FtTtKKIV4BB86CWhz69c/bKTgdV/t1Y6pAGZPKruHVkOII34/I5frn2XFRhYDyMr5Xh8xawboLg+
c6Lhy7WXg6jGEHJ1uM9DUEn8ZhGdJmto+8MIUuYxV9lesB4rD0UB3ADKIvrX/X3RheVWO4jpn1SD
y3pGjUouDiTD2iaZDHZRQjHZl4fYAyk1+eIeZgHZFbRcG2uQa5+WvW2dSEFtu4SQZbVqXNuye6Xp
C7IJu83xCj+Q7dM5RJkANlvin+KWneFdVJYSUa4GPB2iXoF/5FIOJMAiuvtR2sEoQi0wpbjaB0Gu
IC34mp30PVdaIkGNbEoyTmqas6uFNgTECT3X4CRuJ6gC6mr1mZFeYOIZgAz6oKZ1j1EADobkgtoP
8r5JnhcMKwiQ88NY4NcYfR9avs4LE5D0fD0T1bEtjfLnKteEKG2/9PSY34g2imDSZYpIIos/5puO
EIqWN9jmAf+W6mCHoqCHWdtOHgW/u4oCT8HpA2R4MSq12cwqbDz1/q8YvjpyuDyPl//UlTskKav3
MTcLPaiYPiB4NFiT5U4bbCR5L5FkK00AupUVqyBgcrY3j83xcpHewNKaLJw4VWOVG809lF2wRzMS
iy/lYrwgiQFCmZD9q5Mc19vaUykLFppkYX4VqsR4DyTZwV3dRG3AdTBmcaOX4M4+EtgBBVJcwu1Y
R/c7KT0dUct1jb+Cvvha2cKj3ng29iO8PXVLEhW5EUJ5v7kchTdQ9yWbfF6gXhwBLKyjfnM42qD1
cgQCdbMU0CR2auW5dZ2ZSvi+wz/MKJj58UIpYVq8AFPs+x/P5QtOy6IeDmEtZm4/khRGSBMdsymi
CFVXS7eDDVikYU+X7jOtdNgFXzwEUtS4D7DcrSMOfJ4zkd7R0T/cXjRqknhtdbZ0d6KCxccg0/Wv
b+tilAfTyM9K+WB2AsjS8m0x74+9j1dj5SxY2AtO37ZdtQiupcCheUVH9y/HQ3JvbmUKwzeIMb9A
lehiQvdN8yd5ZSwuoyxR9QCSIHrvr97ABJ93BKQ0OdTKFUJw6ei4tYom8E7RtjUNPExgAGmMA3ng
9usD+aMjI/B4fmoNUBK5h+o1eqvfW692FbjO8ooXCEPCt326vy+YCq6W3AjupCI0F8ztMVR1fYlZ
vtG1vPEwPUOBx16SLu2jsl118eIf12Gn3kg4aEIzNeyjOChVd8Od37Ng5yHJIPcYsM+PLqsuF5m6
qGdgsSmtiwgO3/Q2MgDGZP0OFauV5yS4j8cJV9flCs4WCFKZI9YkAWc2Fu75s2DcZYIYvfv/oRtJ
a+FJmqBBiJXqmF85Oc3HUptgjxlqRbBgHV/SKUlsmx4eqxuoYsjou3z6m0KKgEQOaG5QOInj3zmk
HHMNeB690Lbw2iRAIF/DlSaGilQsWzKsjJtgj7Z8WwwkAzMR8leBowYM6gBpUdrBI7T+QorAmJnu
C27/Kh5DJAoFghRFkBOktWDX3GayyUE1ZoZ9327WzeCAok7lDaxf/0n2xpUuYOZqMo9i+LYx/xlH
tyRzeIooPpRrK3dYBErm9REg8LudiL0Xh8bIkMGZH6CNjjfRTOZ7o9QNoIGzyeva05m3FZMMq13I
R4KnfA0KfpB/sVFI+zpQY8gdgl19ma8lD0fUUFQ8vGMSHGmtfQR0jvBmbbmwyYxYL9BmNTNpf6mV
9JOX+g5NuoOBhAr20tPpxQ1n30o1Lv/QzCliHi+CvGJIqj0Ca6Dt/KB6qh1cs8WCWoDbpqcqLHtP
9m+m7w6QBuO5vMO6pj7rGqPD7QKWOTvk9CD8c7GoQl3NmYpsd01JXohaQjSqppcMkJX7a9pi5lVt
psFPY/dO/5FHyOB9Uz9JtGFQufyBo+ZhrV3O/IyGKAvJBY2xXTQUgKLW32kvPynjYa2uLphJE++L
mLSL6ZqO78SfPYv9E/icIlbwBY2N+9N9H5meJWimpopR+wQ3f0b6dR0dtezUXxQRbVy2XLUh/ACv
Tyz2fnaSkBJc0DoV+OOYQsVXg6miIiZzgIO7MRw1485KLhUuG3pMOCDaqdGGAKaadPO19HoaSoIP
COcya3SakL4+oUDrFjToL5tAHfsHGxBdYV51TC/6ax38/FpU/VVTuLnx2ESGxxnX36GKqiK7w42c
SmqjHHU8VhT2OJvYvAmlkNy+hFGlUKl14+HZLC8WyujnCk2urpq5XOhOdgkE7gaZED+FMXQjF6/n
dGu4HLCplxaL6lsFHX9vYPKDZF8vTL7HnlXWTMQg44rah1RmYbikAYM0m3hO6doi9R7LspXKpe40
ajSaWWv+ZZBb/OE30xGmAzEAeXm/iYRk5ZGsq9U1VpTojM9n9mvld+7/MM3z94XEKJ5IQJgRJxEC
yohzeMO4GIgqPf+buUy/KdVlcTh/iYF7cRUdks2iScEjGu+XGKrYSi7qCDaMt7IMOeD1w69OAxyr
enC5L4ckXVZHApRd6aWFY7BZwnDkl5FQ2MvfmfqnEkAZEyO1/1d4KM8DN7a8UQrM0+r4aNTWm36E
S/EyafNU/deBJPtiWLPXmAXluWQwSSujSjye4LjGvc4eEmDY/+738ZkqRThOPEJSPJMRSIR1/Mfl
ucBtxY/1Itlqiy1wXurkPVV1CgFSBLEKqKHGsKEIEGrNki/NbvgnpHrne7OOlJvq2bv9ZBxY6KcH
fxo3C5TYf6E3ZzYYrBo9/E/9hUPf+QTE0nSXVWt+UgJ4c3XD3RUtLalZMS/OTEtJ9nmtRWQ9TynM
iJ47F7eIMANUsc+BN5NqOGkVj9Fc3TCBv+AoArI+7N1lHiUyV02z3c6hZj8ZNCxeVsmU4WfutsAy
ivhhpFQwG07Mwa7/RLOjotV45Yps5+fVrLCzsB63uLB0jvLXWAXAyav0fWOocDzFddMAKURwNFUa
Pqf+J/13yosLw+2jxf5IB/1cQNumLjaSrwVy1KOCXiKxSCJnfFVLAkThtlsG0DUDkuTfMvgaH2gF
Rmg6HyPXOh79APngQybUOQVjv/9rcPHMYzczNFjqvCX3wY4gv30u4TCOssCWQ6D6Jakxe7as5/MQ
+Sqp196to/Ky22hb752H0ChNVTWpxNogN8eXU6WPxUuCL4Y2mf2PoE5FLc3/8pgM1zmSPSO3Mdfu
9Q7GSu2NSmNIHrExRzfplgTUBQFcrEOEiFoxXC1sH7KKIhIIphk3D2msbn4p2itM0z4lrkHDOP/6
6V2eHbN38PVQVitKIesVZ56uMhMZ9jjLdnLjxkFI8/TnS57+0XFdeTB4IAG4mk4umTeqfQpWJuMz
JP9Qz6T/vXe1OLDH9dFd9r3V5KboChBFiUnvYxQutNI19rEi/hJboawZ6w/wY7/vF3FPy43O+LYa
3MdTxwLbv55V+qnniWRJ3bJ58DGgwHFbsY1gMAYnp4XFdrBfDWJeB90pH01FQZP3YkvA2UdtxTUQ
sBPmNmWO+AwZDtiaJyCb2239rbYxmTcllp7htOFxGiFyc1p0x6nM1KPQA2PdgWBlvhfrZCXooNTc
EvasGmcfwwGqT2/2jNygL4iM7CZLDeoZmYUSjRZlVUtI5knasbaLAdrPIopJTCTaXrdQtZP36h8r
9xhRE6xahsPpQ8EbSzQSzC9Bzu5KjnK12z+/laIer9MaGqgvea5fxLUWBYXxYMn4LRqejJP9Z833
kjQuwFo8vom5vBreUa6Xz6bAaPFJspmRzOYSDIQRe4Kmp8IHczOUr2qthDoqcFML2+Cai4dhymFQ
tRLnzdp9pS2DHEYZ4WevbCiptxeHGEL4c1T5gk4zLqsuGn357jkjmOYwrWP1M7RR3GRrQRoAaZy/
kVcbYYpN8kscEDwvYIKsVrZy4TawQ4R8tXC05zdHviHcLAqbNj8f98XV94a1APCn4cdBcLqwb7K0
VuUNDjHZnZty3Pz3/r4ybYWAWHFwVfPnUn+7+IQEHGAmiil3E0z5gAII0HknlnikWxkFnJL/oOpa
l+LuHi4ij2Pwzfj3GleY8aEfV8KhPSJFzbVulwVQnvr4o1sebDFZOAAyr5NmGNr7jwtWD2us1/W1
/fBxJG2wfy9cjwWZY3MbWW+UxMheicHmRjlCkMw0h5PLdspi07k0J2tUox7X11HyCbrFY8UJay9I
D73qK5Pqn7pE6WSDqXkUwrNxSCoGCDQ/TXZ2pRGQmc084O2rdhJbrjyodiKiGt879uzJoYqRJvPv
8yb0vw4nPczOewJOQYMTrcC+Zrzhm60m4tcD7HaMn/UHskRiEx4u+Gqo0zfgjL5rRdIgu9iCegOs
BWxs9uarClNw6yF0iHHkQYMCUvo/MLKrERgo2GxIgiVIcwFjbX26xvrlveWB5fiuO24qwvAYWtJR
i8ALivUCBuYpJGdoRdkKqt+FqvWROZmUWMRgjUNsp4w9+JomPZtTF0V9xk9RNBP2+JQfdKgXTFI2
1qedwcn7xF9Dcr6CGKiOn1UuC44mI+yoo1e3jpS+NH+Hxgn8dAvhMj40DhX1aQ5zUvkEhIES5WTz
C4iuvg/AiZTrYEGzW/8+Xw+M2ip4EzBrDcDHpcxvr8YIDi3AIMUYldjiMUv0kp8WjUwi7RF+fCaD
LU8vlFnOSXI1NG7u/0hNo2whJPeeRtUU25YlQ3VXZTby36LBiOMv/xQjIq0spurKYO361r9g9i0j
D/0OcqU1mhoCVijThkkV3HmcMty4pp9FOQHzAx8GM3dyh9Fprr4hTZZ58b40EfVI3KnHt5O6M3Wo
dzFjwGfXuhVvKUpHpfzmek1BsHqPADtY9wrDls3kdVBoYZ551P2F3BGMacHPPr8IUkp91tvyRODG
iVY1bN1bzb+pr1ZDoGSS/8+OYm0eUJ1AlieBUUElX65dYMZM6JdevbCJz5oift9vT9w7+MbWYptp
y8Gn6LXncx8yaoBgqSzMLpawTQadXnwXXjkA/idIrn8RasXsejx6JNLhmJDDJ/E6eS1eGB02ts2N
Xf7G/Px/XmtQEsTTdKa7KwduysBZ1IH/nABEk2mWejZB3qgvrcPlrT9m0EEPH8fqZB4XLJxb9MNd
v9zkja/sJf2T+91xdPbRUoRsol0Ng35Z8PYpAXg88UGm60S0yDlYwnd4vDCdO7DKmmi4BwmnZRrj
P7+lBi8a2m6B3oIFZQMD1rTcDsYjdZm6DrzPWWVBvjtJd6bppHGwBwas6AAJREbH9+Zwjd62Md9+
opz19FQefF88TwJFEjHU2xvKhBKz3csUedyNNrVSn2ltEBd0i3evASeHvPXxd61p0X9lQMOt0GFU
hkPGRsGCm9nGn8odP98XD5elodPTlF82jhFJLWmqrirnsU/C1Fi20AGYg8GyUckYSvEYrFoS3noJ
Nz9vzproOjUP02S/+1zbfvqQXP2XvbFMVxXjmQiOO6b38WW2TPVkcPyCl76m/dy1+Tz1+zDELdHV
jyZ0QuVRmtgf0nozvIE3d6cEuQZ37RlVPqLOVyHtcfiC0arfq+Nz8hprQF8FkVBYWE3WRr6W/ovy
cDc2KFbL/vQd/GKn6ZWrNt7jiYNZ+Kx6ITPapHzOb8UN05noB4zJ8rLiyy0hiodZjUxJ47LcpHBa
TH4LAjUisDxdqXWiMweQUxh+wiloidwfA1wrL4HZ5ZD9JFH38cowIkclPFLFNjQUv+o3SRZNQg+l
MO9e09/0qOR5qMRKd4V5ZXOYtJ7tXKfA5iprXRmsU7sbw+cx3Myt4CMmSpTTb98kohP/92bgyQWI
56WVST8wABk+SleLMGixmJ3U53rXPv/xkYVQAnGM23k1l/wUwewzNlxPfhx4uJNyhAublrGvd2HQ
3evw9KWsi0I6JaYjA4gUvj3+rJlGLW6ssSRCRegXzMLPpHzSYNG5j4aR6QKTq/k6Cj0xWQ35UmzY
RfpmOQj0YHIfKDnJnAafp+IecIsWm+sWwJzsL7hhOSDnCuwl9nPSR8uh3Mqu+Z7dphQpCH0kFqcK
jTT9u3+JtI1GCqPTsgcq5eFTsu8C4PIbP/7xRDJvvKoc9uZHDAX7qIbTPVxraXg7kysT4snhIu2/
gTJa75bG4K2KFAJjfYCNRMLzoDxUZI7mPkiALV0RokunXlOmD4opoSQXaRGrzO64mRcQhoks69qw
/JiOiiCG7HJi+Y+a/7d68TTPBFwDznYjOtbBBk6NOOFeGpoooiHbCqhFqaK54AwYB2W4fpnYyZ9f
50Mr0oheVA6P3dpaeogUQnI0TjdBOW8wnX5F/AGyAc0SCwucXduefMZ/PTUzd00TgNiN4TcgpSHF
98Ngj8QpFg9RRdsEc8o2L5JAniPXFxghzwf7YlD5ZDKFi+ppr1+D2InvIKTCfxI9gBa4MgBpUZIO
CLSRaZoYPnvpNG4lXBpKmgSxpZVCRCNjpGbuMDHp1D5nTtcCxVVfcCwXFXOyXEcf9D0opJR4jtAr
sIySWA9qiLVFmHk0bmRfqq0Nd0qzNb5uB8Yl9rQhQDe0EHolrtvfI/vrKuf3wVWUJ+8xoKAKuDql
WGuC6IK02OYYAIx2Ggw4xHsR5op4eIlQliBsTJvM+T80PHbdVXKeyon/79gJbtaIOu7bBVTSksW3
B/2kJKuEDdF9jgL5dDDIbpovxCkZYBBUoMKxwOQMcCrIzgN5373SdM/2Dy/KfG64jc/cGP4SImq+
3NWBtfQnExwg2xSqAwQF5H5KN1JTI0GwhyLpn8K2Dzm8Y3zOacuW0mPtXvs8oTA/fQl0W6Fm7yGr
8jtja6kM9imiG0pYP3Bdr6r4DAWXJ3Vjc+6EvYdwfnK9ei5AkeJy2z7/xRLu4eqp7P1Jp8XXlCh3
cxtor4f3CP39d09N+TStEQGHKSlB7fZ5uWt74w0ZVg88gwemLloXL5cyEmoC8UNNS6ciEctSTlgr
dfe5D2KNynkPYSR6BBHvk+C/aRevqew9WSSDzlYBE8pBc5RivZrIm0jqm1WEqBGsTQMtcEDfMS9r
iMyr/bf52NKF7ZWMXmdfwE37GpOihZpvvbZU6lejKeZfC08Q2Wm+SuLiKhZgoYTOR6pj9v0XJ2Lw
lKXx2EJ4rbtb0th/eXYz8P1k8uYs6zpgxtFT1iJQG/InkER6lFwgMdZbivUibB9KRwbtIQUadpLg
lryB34IGePZGq8zyaw1meXsEx6oqwic9qPylfp8WoHa3mf3jGXNcrfP3vMdGZWn4+Or4i+rFkOGJ
A7yG1QS0NZgtKcRP8urzSA7wJeK2IdczzR2AF/pjUMNFM+tvXxuC3gVXcfy2SJv3uSo72BQP2obt
7qKhDJ1WXLxFE30/HD4Z8i2lKf7z6jk4nv4Zqj7PPCwNQNp0mnhl3lGSKwxOeseqx1VPnq+I7ndv
hAxf17BacFFaKJXfdEOM0q8qVbJ6ClAlwSylvr79WxOmpq7JbgXoeXjCOngP920VdKGa49ozZ5CJ
xoiCi+PnWe45DpIqL2ruxDiW/AdsTk1wTXXc5rJh+kRZNRZLXnM3LHxBB2hpGPjT31y4yXpvWB7X
A9qap3kLfPyXMIOx0wsHYhZq+PI8pYIFeZ/57lncQYbH4kZKFP0Ltl5sdXFcVbxNpZHk9lzg+12S
7qIq/XyTb54WYJIyGjlYV+lTy+MvtdU/wHgpQ0SocrlYAajloib4pxNRCjJ7InvN+bScEKW0UCA8
qLsjg3ZxZKmAxb3d2+Zl1uq3/BEeMTEXLxJu1P2Z6shW6XhBSfjsbgxKJTdn7Khw4sx7UkSqTKWV
mPYqSX07BaMnTietRrBxaecPyN8j5tIVk0jq3BNFMkOB7wNcEp0ZkL0yaT1QXeqHT6ZRs1QwTw7N
MLp/vikOanj9oeu4m56szNNfNjy75pxJ7J+4M73qSJEmgtXAYTlsPGt02vMG+/eq/BYMJpY39Asv
O3sWB2qGIj2X8dooauSTghWQ+C3GG7O2VSeRNyiyzXZSU67rPRh74g4SInXbdr/1VY/yp7tnwVdL
Z/0i3/z24kjBtvkD/Mn4y4ckVLDgjuxHpbHkcKRiLoTHpeUGWv0zNk7gNS8jGDtEbrU4XBzgtuHL
k5jYbYGvsufo1xwqRSnXeV7SDz5fBX+ErAtseC6E0LVNszQxkFF3gFdpOiCG7mgJgTks5Zm6ORor
pbXOH0vkKAPsQAyStvySNnGJGJmaCloASmdKVzxMW+3sTECyrFJMdVLrOMESO40FIa20bZhqxHG3
sUM4Ci99JUKqNDU+izhTe6Ma3VdrqdEW5G1EhHIhiCmgHmxvOLP5Jjckw0U3oddN0i9F4bucJsBv
sxFwuBkp8k4oMTG0NsDBdK1Sqkcz8/SYHQM9PcPKJDaimB819EGUPgpY/Y8q+5JxUrl/YJamso/k
bf1iCfLSDVb0+8x8jzlLO/CkCnk529DxbfVUPWG5LTXFHfNFBgfJAEnoSubf7X3YbFGpuysGQRV7
hg6uvgCfSxDUEFMdwiNdag8GH+N/vgV8fnGHM91vEZxTJp2+h86WnACzMag+hQ2oDYXaR572PtrY
gcpE8s4+R79PUVhqUFxEye/NcTn4hbppfgkCClukI+XPf2q+zoBEf2zGzL5DlIMkuPldcyacj5Xq
BrDn1O015KuT76+giFC5Be0GVn3r/9b6X+zeS9Fs/un4zJaMbdpkY2Qkq9N2Ez99X1EFL6P2JsRh
PFKGQX9JSoknQNehdEfC/NlIuglQUjNxiIccvR+0in6XYRpfkA2N5JG9NQe21e2icwGGSoeNxHzw
u9W2CqSIhhXtrRxsHjn5MwANPG6WQV6kb5tXE2o3iUC/NZDT5rKpugYnwTQviO75ggi+NU+gKEjq
JwUNBYqWLDwkV5l4Qy+RnNktQRhKT2F6dye9I7o5kBCxyyrawCT8WppXcZ83kuU7PEyc8O1fl9B5
8F0ElXwrDAWbwfwpzKcz+X9U3VxM5K8ayuz0NNwNU1VkkXWlNbFOJHsi6OBVgtj4mNNKj+XiaRQv
D01X94VtF3yjDdxi32PfKmUqC+vPkotNRmPbHfDgO1JdpKwRgp7gO08AXekwTT8CDYBjgdIP6xXR
PVLwVbERvuYj5dT/EorlOZ0E3X0FpLrLzngXv2uhecNq/A39OCWJ8o2kVhExerq4Ix3cr+iIFHGf
rd+a+0Dq76wMyonKMoyGj2ZYxViQ7enxhAc+sPLXXwBiCVMZc5s6mKr8fQb7I/yTWlPFR/6Hrbhe
mJz8BFAkHYNqFUk6Y73C8w5/bXxCe+M+KPgirt5EunIFzRij09RHWDOcKDZeQLLVScZsbP2yrP3a
KUzoXDB24zTmONpcm/6OeFhMrSx0IEdbuRLsZOCJpmWi/R8DpiNZuvE6vUK/HLo9b5eZ8Y+/nWh3
GniMPLDE3bFyOnvHrN+JtGh+1dDAZd6Ez5xIjmDVOpr8EXMOXPJggSpuq4wE/aLz3nGgTWWX3fYf
yZbZCY0YS0D7b+mUz46k21HfmMcuw55kZS1pwiijPkerCtLgO+AyZF2/uKV53isfZlIj3i+zq737
I1hZJV3Aju+mQVzVVcA8gKVgAbWTAcQyLhefMdkqKtK92oEVNza3FlJsRJu9iyddvidQk8l33CUV
5oQ/Ml3tgouEO2X3MCLEzEtzz55eiKD7ecwRGJ9FzXaxVPg2wOdWNDA/813KM34cxtHTJm0Uc1wP
//6vbhLvyvdSkTtYy69DdK6UDZ5InIy5KD005UHxCiM5Vu/rfBQgEk8y7Et8+1DqEPzv5JC2pPlq
Pg/8GfEmmiVz0nbaqFv1K4IsxeRGBf0iNxjQsLEki+64uosB6zY0EMNK4VZRC2iAhq/g4jSN4KJx
yT1FtpE2BSRh4sbQ3OXQXnWA0nFBSb0SHl/95KXPNf2x/mNC0FYwXww82BLSbzJ1d70Grx5+TWLU
5CmZBpvkHs1G1p2hCYsQNRXED8qde6/NRwsTCpzfATK0VXyWGW8gvuf337htMnhZW2u4otuUkc3K
udCQRG3fKcBlipWAyCEtaV9UjfXZNdBvFwICu8z7lvg9632jBNfZO7U9obu41AGoe2BufI1BcVe1
Vv54gHtAK1aqesmTrtTMyFqrxxMbiRaHxIG9/3PQrFkCTTy0rip5wQ2g09wVoWcd1pyciYJZmEjS
0vsPAnQB2rxW0/W2GN1psG27j8l4zimMRMY2XEsyjQ+8t2Cokc1JJQvpUa4LWpEVZYAYSWpAmBvP
N7Vab+Lo6wdjje/flJHDRRedF2wSLRuEiKvbhPVli8P3loJ/eGQA536KkYtP04D8z7jLHmTax8IH
DIz7VgisK0wdR5aqtt2S2KqV17VgZ+hLlHgk+D/D2trsS1rA2NzdVCEn1JnBNd9gbyW5sZW55NKn
UB7kcpiFZ0miGFYwlQ3gRMiTCIOydE1K9YsOv/zsuqbvU7Bl0AwBdd3M2yFy0hed3v3dNgj5LBlB
zPFNhGmVMggKe6A2/ad9m+mgATE+dG+obXKtm1ajHG0n0YxUoNiHmLGftYGy3mpTVflapOkjSOiM
6yL6ntJUFwD4mYxhLr+Xvg/rwiFznzSU98gk+QxzfoqWXYbm96UEtuTTfNVR8gTiV3tvG8pQ3psX
x1PguFTSQXOWc2BRUn/gM5YuUjLW7v0G/Ag8K2kCehAjCHfXLMUmLRxt5cPf5JP76vNTGmbNVsKq
wouUwbfNydLsd8UIf0DKwtQ8CALX9fxQ9wWm2bZWgJ7itT3xwpsYsBQG4ezuFSSqVfao/auD/aZI
nlWUCcQfOqMYxHZR+Z7noPA7fH7BPTNCL+Q/EPHBYcdO3YHHsZEvcMg0rLVfeBBcsS6BeaD6NJwB
8NcBj1tqIL/JALv//zrrC/zT2EF5xDW8wmra8AJOSSqjFjPVh07dF4Y0JNkNPAut4d9E6olrnBHn
5uVAytns18K/vTLEfjWkUXLtUK9xYFE3jmsGL6O1gQ2NcQ0A1bq7Cjrqjx0k/Cg5nfQtFD//VJaa
gZrC6GZMY5kk6xRHydYWP4X1ONYXSMO+esZizShHptKKBqgiEg55iw3UwfwTdhJ+dy15CACTWnEI
dYu7cBVrE5Rbt/mTFHLBULR5yVbrKmIT2wpTJpm9Usj1TseXjIQvmd7RAogswCyuewQo5tS10wmt
5WbkjB4z7iRUhzg0Zr7K0MSObhWDiAx8ja8JeO/mp0zI3gSsFAy5a/hRtZAVKw1rtsbzdOeNCmPu
ycMpsRkfwpkxMQaoOAOslLQQBFSL8EMafepXqH68ewlqGk+p1sYllnPCDlvgg0vKlFcmvPv9VZD/
BlhGfASuvHOLty0BFawUNHBvET9tYkssBzbVDy/nDBkV/BHmE4+9g8D4eOGJtKxM7FE3GZBxI6OU
LLgGv8KjX8fbN8rEwPPQInUb6h3WP1UV81Zlz0CJOG66rFwYx+8fJcFkAparHAnPJ3m/DVNt2sCi
Nz3xfnB4OikI1BdmZAn3a1zObwI2z7ws9PmVhuUqrbXtV0Hhehl2Tz3xPWZx1pjKBmecdTekJ8R8
mbxdbCO0uHje3awuruZScPwjfYN4eIGJlt0XKO7oabFDPDePKA8T1DApJ4n7zO6FDv2Bm/wUgytz
5z/FYWb8d/58nKK2+H/ZbbHrOyuDAGzPm1MvmoWym9mUyIiJmMuAYQPl5klAuhmgIKnVUjjoiO1E
qxLZRS8oEii4q5oSCTjQ3KY22Au1TOwbcY8fDnff/B300WEwMfWevRzOMVgDmQHdWnZsPAmx+1ON
8OJsETkYAUaj7Jqsez1rng2j24hUTcxj/8JT7lBhZVFo8a+RQ/d+qw7jtbyhonGGzgB5575Ys/4m
g/rzvy4eYHrQ40mNYn3drPJw44qLwiSmwldKgBVZzGRWHUHxWiWK9kwF6cF9SirWXL+GT7u4WYs+
OpmYo6h8+JKtV4Geha8BwDvPHKdfT+bzq6LJJktN3HUpMDuddD9FFFjyjgGEkHu+AvISMajsoaf/
JUNoFrrB18t9WD6OWIu2ZEAlL9zJBd267U0C+DjVNOJQUw/GDmeyH6nH99uW/O/QQV7QhjuAa0zw
/mNHDOeRtUnvx6eX70C2+cat19yGD3FmaGhfmnKHj6/f3LI/niWkldYr+NSKhQnsrNXYbE8OpL6w
bPN2Vd7uXPK3T6PzVmNmCT7a8KOaLQ46HEtSU3DvoP1BLkYQekxl9fsQUWKrCi83JiUuDxvTmlVI
BlGqdFsKuONiwvqc7LPlmQAcQr42qYIhK5AwqqxxRhu7AjKX2X7YtR5HPB7SpCg0pa8W6EpavbTu
vb6AS5donLUa5yKCooX8QsizDlZ0IJwPsfuxOe5I7tOVhTlefehenGezFk+Gz1GJsBncaVHJtAfZ
G5UEKvF7ybZoCOYbt1a9iDCE/RmrwqZ0LrTistaLM9pehuOU7KXNYIboZdbtLrY1kMFZOY4lU+If
P0wLXsQIHKIOrHR4VgCvM2Wa+OfCqR4Km64UCsfuw+vPoR9hVnq3GQTrBe5/DmlgdMVo+am9f/Oy
3e6uMfkOsRPQ1RFAg//ZtaplkF6R6+kec7ntesVQi3lsO77BuWPdfsdRAyaws3iQPOSZpAT4J+eg
kV2YipxIalnF8NU/BGzXL5RY+shIbIfiPLYEY3KiLMuDE6fpK/zKh0d6xFYqRDm7FhAXkaXIbmr7
7FcQTEuE3PPGB7QKO8uqKaKWlUN8yQcq5zlYguP9V4bduPaun/kXjAPeL9WKgqvlAoVyVTyb/Gqu
7vAnvWJF7A2T1mjcTq4T2Jre3Do1dYubHYjzlFSrXMqiG28wqwHYBVdLoyG0r4Qmv7tQX03hblis
+HmxXIC7kgDXY5GjdYGj0jnE3EKfifQAXjQ+a9ApmA==
`protect end_protected
|
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 06/23/2008
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module CAMELLIA256
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity camellia256_tb is
end camellia256_tb;
ARCHITECTURE behavior of camellia256_tb is
-- Component Declaration for the Unit Under Test (UUT)
component CAMELLIA256 is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (0 to 127);
input_en : in STD_LOGIC;
key : in STD_LOGIC_VECTOR (0 to 255);
key_len : in STD_LOGIC_VECTOR (0 to 1);
enc_dec : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (0 to 127);
output_rdy : out STD_LOGIC
);
end component;
--Inputs
signal reset : STD_LOGIC;
signal clk : STD_LOGIC;
signal input : STD_LOGIC_VECTOR(0 to 127) := (others=>'0');
signal input_en : STD_LOGIC := '0';
signal key : STD_LOGIC_VECTOR(0 to 255) := (others=>'0');
signal key_len : STD_LOGIC_VECTOR(0 to 1) := "00";
signal enc_dec : STD_LOGIC;
--Output
signal output : STD_LOGIC_VECTOR(0 to 127);
signal output_rdy : STD_LOGIC;
-- Time constants
constant ClockPeriod : TIME := 5 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: CAMELLIA256
port map(
reset => reset,
clk => clk,
input => input,
input_en => input_en,
key => key,
key_len => key_len,
enc_dec => enc_dec,
output => output,
output_rdy => output_rdy
);
ck : process
begin
clk <= '0';
wait for ClockPeriod / 2;
clk <= '1';
wait for ClockPeriod / 2;
end process;
process
begin
reset <= '1';
wait for ClockPeriod*2; --falling clock edge
reset <= '0';
wait until clk = '1';
input <= X"0123456789ABCDEFFEDCBA9876543210";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "00";
enc_dec <= '0';
input_en <= '1';
wait until clk = '1';
input <= X"67673138549669730857065648EABE43";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "00";
enc_dec <= '1';
wait until clk = '1';
input <= X"0123456789ABCDEFFEDCBA9876543210";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "10";
enc_dec <= '0';
wait until clk = '1';
input <= X"B4993401B3E996F84EE5CEE7D79B09B9";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "10";
enc_dec <= '1';
wait until clk = '1';
input <= X"0123456789ABCDEFFEDCBA9876543210";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "11";
enc_dec <= '0';
wait until clk = '1';
input <= X"9ACC237DFF16D76C20EF7C919E3A7509";
key <= X"0123456789ABCDEFFEDCBA9876543210" &
X"00112233445566778899AABBCCDDEEFF";
key_len <= "11";
enc_dec <= '1';
wait until clk = '1';
input_en <= '0';
wait;
end process;
end;
|
-- Copyright (c) 2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Xilinx dual-port BRAM model with handshaking
-- Project :
-------------------------------------------------------------------------------
-- File : xilinx_do_blockram.vhdl
-- Author : Aleksi Tervo
-- Company : Tampere University
-- Created : 2017-06-01
-- Last update: 2017-06-01
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Parametric-width byte strobe memory with handshaking
-- which infers BRAM on (at least) Xilinx Series 7 FPGAs
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-06-01 1.0 tervoa Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
entity xilinx_dp_blockram is generic (
addrw_g : integer := 10;
dataw_g : integer := 32);
port (
clk : in std_logic;
rstx : in std_logic;
-- PORT A -------------------------------------------------------
-- Access channel
a_avalid_in : in std_logic;
a_aready_out : out std_logic;
a_aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
a_awren_in : in std_logic;
a_astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
a_adata_in : in std_logic_vector(dataw_g-1 downto 0);
-- Read channel
a_rvalid_out : out std_logic;
a_rready_in : in std_logic;
a_rdata_out : out std_logic_vector(dataw_g-1 downto 0);
-- PORT B -------------------------------------------------------
-- Access channel
b_avalid_in : in std_logic;
b_aready_out : out std_logic;
b_aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
b_awren_in : in std_logic;
b_astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
b_adata_in : in std_logic_vector(dataw_g-1 downto 0);
-- Read channel
b_rvalid_out : out std_logic;
b_rready_in : in std_logic;
b_rdata_out : out std_logic_vector(dataw_g-1 downto 0)
);
end xilinx_dp_blockram;
architecture rtl of xilinx_dp_blockram is
constant dataw_padded_c : integer := ((dataw_g+7)/8)*8;
constant astrb_width_c : integer := (dataw_g+7)/8;
constant adata_padding_c : std_logic_vector(dataw_padded_c-dataw_g-1 downto 0)
:= (others => '0');
signal a_addr, b_addr : unsigned(addrw_g-1 downto 0);
signal a_wdata, b_wdata : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_ram_rdata_r, b_ram_rdata_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_enable, b_enable : std_logic;
signal a_strb, b_strb : std_logic_vector(astrb_width_c-1 downto 0);
signal a_adata, b_adata : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_aready_r, b_aready_r : std_logic;
signal a_live_read, b_live_read : std_logic;
signal a_live_read_r, b_live_read_r : std_logic;
signal a_rdata_r, b_rdata_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_rdata_valid_r, b_rdata_valid_r : std_logic;
signal a_rvalid, b_rvalid : std_logic;
type ram_type is array (2**addrw_g-1 downto 0) of std_logic_vector
(dataw_padded_c-1 downto 0);
shared variable RAM_ARR : ram_type;
begin
control_comb_a : process(a_aaddr_in, a_avalid_in, a_aready_r, a_awren_in,
a_astrb_in, a_live_read_r, a_rdata_valid_r)
begin
if a_avalid_in = '1' and a_aready_r = '1' then
a_enable <= '1';
if a_awren_in = '1' then
a_strb <= a_astrb_in;
a_live_read <= '0';
else
a_strb <= (others => '0');
a_live_read <= '1';
end if;
else
a_strb <= (others => '0');
a_enable <= '0';
a_live_read <= '0';
end if;
a_addr <= unsigned(a_aaddr_in);
a_rvalid <= a_live_read_r or a_rdata_valid_r;
end process;
control_comb_b : process(b_aaddr_in, b_avalid_in, b_aready_r, b_awren_in,
b_astrb_in, b_live_read_r, b_rdata_valid_r)
begin
if b_avalid_in = '1' and b_aready_r = '1' then
b_enable <= '1';
if b_awren_in = '1' then
b_strb <= b_astrb_in;
b_live_read <= '0';
else
b_strb <= (others => '0');
b_live_read <= '1';
end if;
else
b_strb <= (others => '0');
b_enable <= '0';
b_live_read <= '0';
end if;
b_addr <= unsigned(b_aaddr_in);
b_rvalid <= b_live_read_r or b_rdata_valid_r;
end process;
control_sync_a : process(clk, rstx)
begin
if rstx = '0' then
a_live_read_r <= '0';
a_aready_r <= '0';
a_rdata_valid_r <= '0';
a_rdata_r <= (others => '0');
elsif rising_edge(clk) then
if a_rvalid = '1' and a_rready_in = '1' then
a_rdata_valid_r <= '0';
end if;
if a_rvalid = '1' and a_rready_in = '0' then
a_aready_r <= '0';
else
a_aready_r <= '1';
end if;
a_live_read_r <= a_live_read or a_live_read_r;
if a_live_read_r = '1' and (a_rready_in = '1' or a_rdata_valid_r = '0') then
a_live_read_r <= a_live_read;
if a_rready_in = '0' or a_rdata_valid_r = '1' then
a_rdata_valid_r <= '1';
a_rdata_r <= a_ram_rdata_r;
end if;
end if;
end if;
end process;
control_sync_b : process(clk, rstx)
begin
if rstx = '0' then
b_live_read_r <= '0';
b_aready_r <= '0';
b_rdata_valid_r <= '0';
b_rdata_r <= (others => '0');
elsif rising_edge(clk) then
if b_rvalid = '1' and b_rready_in = '1' then
b_rdata_valid_r <= '0';
end if;
if b_rvalid = '1' and b_rready_in = '0' then
b_aready_r <= '0';
else
b_aready_r <= '1';
end if;
b_live_read_r <= b_live_read or b_live_read_r;
if b_live_read_r = '1' and (b_rready_in = '1' or b_rdata_valid_r = '0') then
b_live_read_r <= b_live_read;
if b_rready_in = '0' or b_rdata_valid_r = '1' then
b_rdata_valid_r <= '1';
b_rdata_r <= b_ram_rdata_r;
end if;
end if;
end if;
end process;
a_wdata <= adata_padding_c & a_adata_in;
b_wdata <= adata_padding_c & b_adata_in;
RAM_A : process(clk)
begin
if rising_edge(clk) then
if a_enable = '1' then
for i in 0 to astrb_width_c-1 loop
if a_strb(i) = '1' then
RAM_ARR(to_integer(a_addr))((i+1)*8-1 downto i*8)
:= a_wdata((i+1)*8-1 downto i*8);
end if;
end loop;
a_ram_rdata_r <= RAM_ARR(to_integer(a_addr));
end if;
end if;
end process;
RAM_B : process(clk)
begin
if rising_edge(clk) then
if b_enable = '1' then
for i in 0 to astrb_width_c-1 loop
if b_strb(i) = '1' then
RAM_ARR(to_integer(b_addr))((i+1)*8-1 downto i*8)
:= b_wdata((i+1)*8-1 downto i*8);
end if;
end loop;
b_ram_rdata_r <= RAM_ARR(to_integer(b_addr));
end if;
end if;
end process;
a_rdata_out <= a_ram_rdata_r(a_rdata_out'range) when a_rdata_valid_r = '0'
else a_rdata_r(a_rdata_out'range);
b_rdata_out <= b_ram_rdata_r(b_rdata_out'range) when b_rdata_valid_r = '0'
else b_rdata_r(b_rdata_out'range);
a_aready_out <= a_aready_r;
a_rvalid_out <= a_rvalid;
b_aready_out <= b_aready_r;
b_rvalid_out <= b_rvalid;
end architecture rtl; |
-- Copyright (c) 2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Xilinx dual-port BRAM model with handshaking
-- Project :
-------------------------------------------------------------------------------
-- File : xilinx_do_blockram.vhdl
-- Author : Aleksi Tervo
-- Company : Tampere University
-- Created : 2017-06-01
-- Last update: 2017-06-01
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Parametric-width byte strobe memory with handshaking
-- which infers BRAM on (at least) Xilinx Series 7 FPGAs
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-06-01 1.0 tervoa Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
entity xilinx_dp_blockram is generic (
addrw_g : integer := 10;
dataw_g : integer := 32);
port (
clk : in std_logic;
rstx : in std_logic;
-- PORT A -------------------------------------------------------
-- Access channel
a_avalid_in : in std_logic;
a_aready_out : out std_logic;
a_aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
a_awren_in : in std_logic;
a_astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
a_adata_in : in std_logic_vector(dataw_g-1 downto 0);
-- Read channel
a_rvalid_out : out std_logic;
a_rready_in : in std_logic;
a_rdata_out : out std_logic_vector(dataw_g-1 downto 0);
-- PORT B -------------------------------------------------------
-- Access channel
b_avalid_in : in std_logic;
b_aready_out : out std_logic;
b_aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
b_awren_in : in std_logic;
b_astrb_in : in std_logic_vector((dataw_g+7)/8-1 downto 0);
b_adata_in : in std_logic_vector(dataw_g-1 downto 0);
-- Read channel
b_rvalid_out : out std_logic;
b_rready_in : in std_logic;
b_rdata_out : out std_logic_vector(dataw_g-1 downto 0)
);
end xilinx_dp_blockram;
architecture rtl of xilinx_dp_blockram is
constant dataw_padded_c : integer := ((dataw_g+7)/8)*8;
constant astrb_width_c : integer := (dataw_g+7)/8;
constant adata_padding_c : std_logic_vector(dataw_padded_c-dataw_g-1 downto 0)
:= (others => '0');
signal a_addr, b_addr : unsigned(addrw_g-1 downto 0);
signal a_wdata, b_wdata : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_ram_rdata_r, b_ram_rdata_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_enable, b_enable : std_logic;
signal a_strb, b_strb : std_logic_vector(astrb_width_c-1 downto 0);
signal a_adata, b_adata : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_aready_r, b_aready_r : std_logic;
signal a_live_read, b_live_read : std_logic;
signal a_live_read_r, b_live_read_r : std_logic;
signal a_rdata_r, b_rdata_r : std_logic_vector(dataw_padded_c-1 downto 0);
signal a_rdata_valid_r, b_rdata_valid_r : std_logic;
signal a_rvalid, b_rvalid : std_logic;
type ram_type is array (2**addrw_g-1 downto 0) of std_logic_vector
(dataw_padded_c-1 downto 0);
shared variable RAM_ARR : ram_type;
begin
control_comb_a : process(a_aaddr_in, a_avalid_in, a_aready_r, a_awren_in,
a_astrb_in, a_live_read_r, a_rdata_valid_r)
begin
if a_avalid_in = '1' and a_aready_r = '1' then
a_enable <= '1';
if a_awren_in = '1' then
a_strb <= a_astrb_in;
a_live_read <= '0';
else
a_strb <= (others => '0');
a_live_read <= '1';
end if;
else
a_strb <= (others => '0');
a_enable <= '0';
a_live_read <= '0';
end if;
a_addr <= unsigned(a_aaddr_in);
a_rvalid <= a_live_read_r or a_rdata_valid_r;
end process;
control_comb_b : process(b_aaddr_in, b_avalid_in, b_aready_r, b_awren_in,
b_astrb_in, b_live_read_r, b_rdata_valid_r)
begin
if b_avalid_in = '1' and b_aready_r = '1' then
b_enable <= '1';
if b_awren_in = '1' then
b_strb <= b_astrb_in;
b_live_read <= '0';
else
b_strb <= (others => '0');
b_live_read <= '1';
end if;
else
b_strb <= (others => '0');
b_enable <= '0';
b_live_read <= '0';
end if;
b_addr <= unsigned(b_aaddr_in);
b_rvalid <= b_live_read_r or b_rdata_valid_r;
end process;
control_sync_a : process(clk, rstx)
begin
if rstx = '0' then
a_live_read_r <= '0';
a_aready_r <= '0';
a_rdata_valid_r <= '0';
a_rdata_r <= (others => '0');
elsif rising_edge(clk) then
if a_rvalid = '1' and a_rready_in = '1' then
a_rdata_valid_r <= '0';
end if;
if a_rvalid = '1' and a_rready_in = '0' then
a_aready_r <= '0';
else
a_aready_r <= '1';
end if;
a_live_read_r <= a_live_read or a_live_read_r;
if a_live_read_r = '1' and (a_rready_in = '1' or a_rdata_valid_r = '0') then
a_live_read_r <= a_live_read;
if a_rready_in = '0' or a_rdata_valid_r = '1' then
a_rdata_valid_r <= '1';
a_rdata_r <= a_ram_rdata_r;
end if;
end if;
end if;
end process;
control_sync_b : process(clk, rstx)
begin
if rstx = '0' then
b_live_read_r <= '0';
b_aready_r <= '0';
b_rdata_valid_r <= '0';
b_rdata_r <= (others => '0');
elsif rising_edge(clk) then
if b_rvalid = '1' and b_rready_in = '1' then
b_rdata_valid_r <= '0';
end if;
if b_rvalid = '1' and b_rready_in = '0' then
b_aready_r <= '0';
else
b_aready_r <= '1';
end if;
b_live_read_r <= b_live_read or b_live_read_r;
if b_live_read_r = '1' and (b_rready_in = '1' or b_rdata_valid_r = '0') then
b_live_read_r <= b_live_read;
if b_rready_in = '0' or b_rdata_valid_r = '1' then
b_rdata_valid_r <= '1';
b_rdata_r <= b_ram_rdata_r;
end if;
end if;
end if;
end process;
a_wdata <= adata_padding_c & a_adata_in;
b_wdata <= adata_padding_c & b_adata_in;
RAM_A : process(clk)
begin
if rising_edge(clk) then
if a_enable = '1' then
for i in 0 to astrb_width_c-1 loop
if a_strb(i) = '1' then
RAM_ARR(to_integer(a_addr))((i+1)*8-1 downto i*8)
:= a_wdata((i+1)*8-1 downto i*8);
end if;
end loop;
a_ram_rdata_r <= RAM_ARR(to_integer(a_addr));
end if;
end if;
end process;
RAM_B : process(clk)
begin
if rising_edge(clk) then
if b_enable = '1' then
for i in 0 to astrb_width_c-1 loop
if b_strb(i) = '1' then
RAM_ARR(to_integer(b_addr))((i+1)*8-1 downto i*8)
:= b_wdata((i+1)*8-1 downto i*8);
end if;
end loop;
b_ram_rdata_r <= RAM_ARR(to_integer(b_addr));
end if;
end if;
end process;
a_rdata_out <= a_ram_rdata_r(a_rdata_out'range) when a_rdata_valid_r = '0'
else a_rdata_r(a_rdata_out'range);
b_rdata_out <= b_ram_rdata_r(b_rdata_out'range) when b_rdata_valid_r = '0'
else b_rdata_r(b_rdata_out'range);
a_aready_out <= a_aready_r;
a_rvalid_out <= a_rvalid;
b_aready_out <= b_aready_r;
b_rvalid_out <= b_rvalid;
end architecture rtl; |
-- File: gray_counter_4.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_4 is
port (
gray_count: out unsigned(3 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_4;
architecture MyHDL of gray_counter_4 is
signal even: std_logic;
signal gray: unsigned(3 downto 0);
begin
GRAY_COUNTER_4_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(3 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((4 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 4-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_4_SEQ;
gray_count <= gray;
end architecture MyHDL;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clk200Hz_tb IS
END clk200Hz_tb;
ARCHITECTURE behavior OF clk200Hz_tb IS
COMPONENT clk200Hz
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal entrada : std_logic := '0';
signal reset : std_logic := '0';
-- Salidas
signal salida : std_logic;
constant entrada_t : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: clk200Hz PORT MAP (
entrada => entrada,
reset => reset,
salida => salida
);
-- Definición del reloj.
entrada_process :process
begin
entrada <= '0';
wait for entrada_t / 2;
entrada <= '1';
wait for entrada_t / 2;
end process;
-- Procesamiento de estímulos.
estimulos: process
begin
reset <= '1'; -- Condiciones iniciales.
wait for 100 ns;
reset <= '0'; -- ¡A trabajar!
wait;
end process;
END; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clk200Hz_tb IS
END clk200Hz_tb;
ARCHITECTURE behavior OF clk200Hz_tb IS
COMPONENT clk200Hz
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal entrada : std_logic := '0';
signal reset : std_logic := '0';
-- Salidas
signal salida : std_logic;
constant entrada_t : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: clk200Hz PORT MAP (
entrada => entrada,
reset => reset,
salida => salida
);
-- Definición del reloj.
entrada_process :process
begin
entrada <= '0';
wait for entrada_t / 2;
entrada <= '1';
wait for entrada_t / 2;
end process;
-- Procesamiento de estímulos.
estimulos: process
begin
reset <= '1'; -- Condiciones iniciales.
wait for 100 ns;
reset <= '0'; -- ¡A trabajar!
wait;
end process;
END; |
----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : gprf.vhd
-- Design name : gprf
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The general purpose register infers memory blocks to implement
-- the register file. All outputs are registered, possibly by using
-- registered memory elements.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity gprf is port
(
gprf_o : out gprf_out_type;
gprf_i : in gprf_in_type;
ena_i : in std_logic;
clk_i : in std_logic
);
end gprf;
-- This architecture is the default implementation. It
-- consists of three dual port memories. Other
-- architectures can be added while configurations can
-- control the implemented architecture.
architecture arch of gprf is
begin
a : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_a_o,
adr_i => gprf_i.adr_a_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
b : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_b_o,
adr_i => gprf_i.adr_b_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
d : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_d_o,
adr_i => gprf_i.adr_d_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
end arch;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_10.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity reg is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( clock : in std_logic;
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity reg;
-- not in book
architecture gate_level of reg is
begin
end architecture gate_level;
-- end not in book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_10.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity reg is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( clock : in std_logic;
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity reg;
-- not in book
architecture gate_level of reg is
begin
end architecture gate_level;
-- end not in book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_10.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity reg is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( clock : in std_logic;
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity reg;
-- not in book
architecture gate_level of reg is
begin
end architecture gate_level;
-- end not in book
|
-------------------------------------------------------------------[01.11.2014]
-- Encoder
-------------------------------------------------------------------------------
-- V1.0 03.08.2014 Initial release
-- V2.0 01.11.2014 Added AUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder is
port (
CLK : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
C : in STD_LOGIC_VECTOR (1 downto 0);
VDE : in STD_LOGIC; -- Video Data Enable (VDE)
ADE : in STD_LOGIC; -- Audio/auxiliary Data Enable (ADE)
AUX : in STD_LOGIC_VECTOR (3 downto 0);
ENCODED : out STD_LOGIC_VECTOR (9 downto 0));
end encoder;
architecture rtl of encoder is
signal xored : STD_LOGIC_VECTOR (8 downto 0);
signal xnored : STD_LOGIC_VECTOR (8 downto 0);
signal ones : STD_LOGIC_VECTOR (3 downto 0);
signal data_word : STD_LOGIC_VECTOR (8 downto 0);
signal data_word_inv : STD_LOGIC_VECTOR (8 downto 0);
signal data_word_disparity : STD_LOGIC_VECTOR (3 downto 0);
signal dc_bias : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
begin
-- Work our the two different encodings for the byte
xored(0) <= DATA(0);
xored(1) <= DATA(1) xor xored(0);
xored(2) <= DATA(2) xor xored(1);
xored(3) <= DATA(3) xor xored(2);
xored(4) <= DATA(4) xor xored(3);
xored(5) <= DATA(5) xor xored(4);
xored(6) <= DATA(6) xor xored(5);
xored(7) <= DATA(7) xor xored(6);
xored(8) <= '1';
xnored(0) <= DATA(0);
xnored(1) <= DATA(1) xnor xnored(0);
xnored(2) <= DATA(2) xnor xnored(1);
xnored(3) <= DATA(3) xnor xnored(2);
xnored(4) <= DATA(4) xnor xnored(3);
xnored(5) <= DATA(5) xnor xnored(4);
xnored(6) <= DATA(6) xnor xnored(5);
xnored(7) <= DATA(7) xnor xnored(6);
xnored(8) <= '0';
-- Count how many ones are set in data
ones <= "0000" + DATA(0) + DATA(1) + DATA(2) + DATA(3) + DATA(4) + DATA(5) + DATA(6) + DATA(7);
-- Decide which encoding to use
process (ones, DATA(0), xnored, xored)
begin
if ones > 4 or (ones = 4 and DATA(0) = '0') then
data_word <= xnored;
data_word_inv <= NOT(xnored);
else
data_word <= xored;
data_word_inv <= NOT(xored);
end if;
end process;
-- Work out the DC bias of the dataword;
data_word_disparity <= "1100" + data_word(0) + data_word(1) + data_word(2) + data_word(3) + data_word(4) + data_word(5) + data_word(6) + data_word(7);
-- Now work out what the output should be
process(CLK)
begin
if (CLK'event and CLK = '1') then
-- Video Data Coding
if VDE = '1' then
if dc_bias = "00000" or data_word_disparity = 0 then
-- dataword has no disparity
if data_word(8) = '1' then
ENCODED <= "01" & data_word(7 downto 0);
dc_bias <= dc_bias + data_word_disparity;
else
ENCODED <= "10" & data_word_inv(7 downto 0);
dc_bias <= dc_bias - data_word_disparity;
end if;
elsif (dc_bias(3) = '0' and data_word_disparity(3) = '0') or
(dc_bias(3) = '1' and data_word_disparity(3) = '1') then
ENCODED <= '1' & data_word(8) & data_word_inv(7 downto 0);
dc_bias <= dc_bias + data_word(8) - data_word_disparity;
else
ENCODED <= '0' & data_word;
dc_bias <= dc_bias - data_word_inv(8) + data_word_disparity;
end if;
-- TERC4 Coding
elsif ADE = '1' then
case AUX is
when "0000" => ENCODED <= "1010011100";
when "0001" => ENCODED <= "1001100011";
when "0010" => ENCODED <= "1011100100";
when "0011" => ENCODED <= "1011100010";
when "0100" => ENCODED <= "0101110001";
when "0101" => ENCODED <= "0100011110";
when "0110" => ENCODED <= "0110001110";
when "0111" => ENCODED <= "0100111100";
when "1000" => ENCODED <= "1011001100";
when "1001" => ENCODED <= "0100111001";
when "1010" => ENCODED <= "0110011100";
when "1011" => ENCODED <= "1011000110";
when "1100" => ENCODED <= "1010001110";
when "1101" => ENCODED <= "1001110001";
when "1110" => ENCODED <= "0101100011";
when others => ENCODED <= "1011000011";
end case;
else
-- In the control periods, all values have and have balanced bit count
case C is
when "00" => ENCODED <= "1101010100";
when "01" => ENCODED <= "0010101011";
when "10" => ENCODED <= "0101010100";
when others => ENCODED <= "1010101011";
end case;
dc_bias <= (others => '0');
end if;
end if;
end process;
end rtl;
--
-- process(CLK)
-- begin
-- if (CLK'event and CLK = '1') then
-- case encoding is
-- when "00" |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb is
port(
--Clock and Reset
clk : in std_logic;
reset_n : in std_logic;
-- USB Conduit interface to DE2 (Export)
USB_DATA : inout std_logic_vector(15 downto 0);
USB_ADDR : out std_logic_vector(1 downto 0);
USB_WR_N : out std_logic := '1';
USB_RD_N : out std_logic := '1';
USB_RST_N : out std_logic := '1';
USB_CS_N : out std_logic := '1';
USB_INT0 : in std_logic; -- Irq 0 DC
USB_INT1 : in std_logic; -- Irq 1 HC
-- Avalon Memory-Mapped-Slave interface Device Controller (DC)
avs_dc_address : in std_logic;
avs_dc_writedata : in std_logic_vector(15 downto 0);
avs_dc_write_n : in std_logic;
avs_dc_read_n : in std_logic;
avs_dc_CS_n : in std_logic;
avs_dc_readdata : out std_logic_vector(15 downto 0);
avs_dc_irq : out std_logic;
-- Avalon Memory-Mapped-Slave interface Host Controller (HC)
-- Probably will not use this interface.
avs_hc_address : in std_logic;
avs_hc_writedata : in std_logic_vector(15 downto 0);
avs_hc_write_n : in std_logic;
avs_hc_read_n : in std_logic;
avs_hc_CS_n : in std_logic;
avs_hc_readdata : out std_logic_vector(15 downto 0);
avs_hc_irq : out std_logic
);
end usb;
architecture connections of usb is
begin
-- Send interrupt from DE2 connection to proper controller
avs_dc_irq <= USB_INT0;
avs_hc_irq <= USB_INT1;
--Two cases possible, using the host controller or the device controller. The github project combines them with when else style assignments
--Device controller signals
USB_DATA <= avs_dc_writedata when avs_dc_write_n = '0' else (others => 'Z'); -- Only does device controller
avs_dc_readdata <= USB_DATA when avs_dc_read_n = '0' else (others => 'Z');
avs_hc_readdata <= USB_DATA when avs_hc_read_n = '0' else (others => 'Z');
USB_CS_N <= '1' when avs_dc_CS_n = '0' and avs_hc_CS_n = '0' else '0';
USB_ADDR(0) <= '1';
USB_ADDR(1) <= avs_dc_address;
USB_RD_N <= avs_dc_read_n; --Just Ignoring the HC controller right now.
USB_WR_N <= avs_dc_write_n;
USB_RST_N <= reset_n;
end architecture connections;
-- If chip_select_n == 1
-- I could probably have processes for chip select for toggling between HC and DC
-- but for now i'm less than interested when I havent gotten DC working
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pwm is
generic(
N: integer := 4
);
port(
clk: in std_logic;
value: in std_logic_vector(N-1 downto 0);
output: out std_logic
);
end pwm;
architecture pwm_arch of pwm is
signal accumulator: std_logic_vector(N-1 downto 0);
signal accum_next: std_logic_vector(N-1 downto 0);
signal pwm_next: std_logic;
begin
process(clk)
begin
if (clk'event and clk = '0') then
accumulator <= accum_next;
output <= pwm_next;
end if;
end process;
accum_next <= accumulator + '1';
pwm_next <= '1' when (accumulator < value) else '0';
end pwm_arch; |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_register is
generic(
C_NUM_REGISTERS : integer := 11 ;
C_INCLUDE_SG : integer := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
--C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqthresh_wren : out std_logic ; --
irqdelay_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; -- CR605888
--
-- Error Control --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_interr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_interr_set : in std_logic ; --
updt_slverr_set : in std_logic ; --
updt_decerr_set : in std_logic ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
error_in : in std_logic ; --
error_out : out std_logic ; --
introut : out std_logic ; --
soft_reset_in : in std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
sg_ctl : out std_logic_vector (7 downto 0) ;
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
buffer_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
buffer_length_wren : out std_logic ; --
bytes_received : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
bytes_received_wren : in std_logic --
); --
end axi_dma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
-- CR603034 moved s2mm back to offset 6
--constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA)
--constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA)
--
--
--constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA)
-- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx
-- SA_ADDRESS_INDEX, -- Source Address Index
-- DA_ADDRESS_INDEX); -- Destination Address Index
constant BUFF_ADDRESS_INDEX : integer := 6;
constant BUFF_ADDRESS_MSB_INDEX : integer := 7;
constant BUFF_LENGTH_INDEX : integer := 10; -- Buffer Length Reg
constant SGCTL_INDEX : integer := 11; -- Buffer Length Reg
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
constant DMA_CONFIG : std_logic_vector(0 downto 0)
:= std_logic_vector(to_unsigned(C_INCLUDE_SG,1));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i_64 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_length_i : std_logic_vector
(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal cmplt : std_logic := '0';
signal error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
-- interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal sg_cache_info : std_logic_vector (7 downto 0);
signal diff_thresh_xor : std_logic_vector (7 downto 0);
signal sig_cur_updated : std_logic;
signal tmp11 : std_logic;
signal tailpntr_updated_d1 : std_logic;
signal tailpntr_updated_d2 : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ;
taildesc_msb <= taildesc_msb_i ;
BUFF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
buffer_address <= buffer_address_i_64 & buffer_address_i ;
end generate BUFF_ADDR_EQL64;
BUFF_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
buffer_address <= buffer_address_i ;
end generate BUFF_ADDR_EQL32;
buffer_length <= buffer_length_i ;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
--diff_thresh_xor <= dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) xor
-- axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT);
--different_thresh <= '0' when diff_thresh_xor = "00000000"
-- else '1';
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register, Bit 3 for Key hole operation
-------------------------------------------------------------------------------
DMACR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED5_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15
downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT)
-- bit 14
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT)
-- bit 13
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT)
-- bit 12
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT)
-- bits 11 downto 3
& ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT);
end if;
end if;
end process DMACR_REGISTER;
DMACR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then
dmacr_i(DMACR_KH_BIT) <= '0';
dmacr_i(CYCLIC_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT);
dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT);
end if;
end if;
end process DMACR_REGISTER1;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If soft reset set in other channel then set
-- reset bit here too
elsif(soft_reset_in = '1')then
dmacr_i(DMACR_RESET_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Tail Pointer Enable fixed at 1 for this release of axi dma
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1';
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error
or error_in = '1' -- S2MM Error
or stop_dma = '1' -- Stop due to error
or soft_reset_i = '1' -- MM2S Soft Reset
or soft_reset_in = '1' -- S2MM Soft Reset
else '0';
DMACR_RUNSTOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or other channel
-- error (i.e. error_in) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
DMASR_IDLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= error;
SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process SG_FTCH_ERROR_PROC;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- CR605888 Disable delay timer if halted or on delay irq set
--dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348
dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348
or dmasr_i(DMASR_DLYIRQ_BIT);
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
error_d1 <= '0';
else
error_d1 <= error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= error and not error_d1;
DMASR_ERRIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& DMA_CONFIG -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-- Generate current descriptor and tail descriptor register for Scatter Gather Mode
GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
MM2S_SGCTL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_cache_info <= "00000011"; --(others => '0');
elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then
sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0);
else
sg_cache_info <= sg_cache_info;
end if;
end if;
end process MM2S_SGCTL;
sg_ctl <= sg_cache_info;
end generate GEN_SG_CTL_REG;
GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
sg_ctl <= "00000011"; --(others => '0');
end generate GEN_SG_NO_CTL_REG;
-- Signals not used for Scatter Gather Mode, only simple mode
buffer_address_i <= (others => '0');
buffer_length_i <= (others => '0');
buffer_length_wren <= '0';
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(CURDESC_RESERVED_BIT5
-- downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(TAILDESC_RESERVED_BIT5
-- downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH - 1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_DESC_REG_FOR_SG;
-- Generate Buffer Address and Length Register for Simple DMA Mode
GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate
begin
-- Signals not used for simple dma mode, only for sg mode
curdesc_lsb_i <= (others => '0');
curdesc_msb_i <= (others => '0');
taildesc_lsb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
tailpntr_updated <= '0';
error_pointer_set <= '0';
-- Buffer Address register. Used for Source Address (SA) if MM2S
-- and used for Destination Address (DA) if S2MM
BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then
buffer_address_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER;
GEN_BUFF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i_64 <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then
buffer_address_i_64 <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER1;
end generate GEN_BUFF_ADDR_EQL64;
-- Buffer Length register. Used for number of bytes to transfer if MM2S
-- and used for size of receive buffer is S2MM
BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_i <= (others => '0');
-- Update with actual bytes received (Only for S2MM channel)
-- elsif(bytes_received_wren = '1')then
-- buffer_length_i <= bytes_received;
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then
buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process BUFFER_LNGTH_REGISTER;
-- Buffer Length Write Enable control. Assertion of wren will
-- begin a transfer if channel is Idle.
BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_wren <= '0';
-- Non-zero length value written
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1'
and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then
buffer_length_wren <= '1';
else
buffer_length_wren <= '0';
end if;
end if;
end process BUFFER_LNGTH_WRITE;
end generate GEN_REG_FOR_SMPL;
end implementation;
|
architecture RTL of FIFO is
subtype read_size is integer range 0 to 9;
-- Violations below
subtype read_size is integer range 0 to 9;
subtype read_size is integer range 0 to 9;
begin
end architecture RTL;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_TB
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ALU_tb_vhd IS
END ALU_tb_vhd;
ARCHITECTURE behavior OF ALU_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR(7 downto 0);
RB : in STD_LOGIC_VECTOR(7 downto 0);
OPCODE : in STD_LOGIC_VECTOR(3 downto 0);
CCR : out STD_LOGIC_VECTOR(3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0));
END COMPONENT;
--Inputs
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
--Outputs
SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0);
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
--Condition Codes
SIGNAL N : STD_LOGIC := '0';
SIGNAL Z : STD_LOGIC := '0';
SIGNAL V : STD_LOGIC := '0';
SIGNAL C : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP( CLK => CLK,
RA => RA,
RB => RB,
OPCODE => OPCODE,
CCR => CCR,
ALU_OUT => ALU_OUT,
LDST_OUT => LDST_OUT);
-- Assign condition code bits
N <= CCR(3); -- N - Negative
Z <= CCR(2); -- Z - Zero
V <= CCR(1); -- V - Overflow
C <= CCR(0); -- C - Carry/Borrow
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Start ALU Test Bench" severity NOTE;
----- Register-Register Arithmetic Tests -----
RA <= "00000101"; -- 5
RB <= "00000011"; -- 3
OPCODE <= "0000"; wait for period;
assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0001"; wait for period;
assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0010"; wait for period;
assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0011"; wait for period;
assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "01100100"; -- 100
RB <= "00110010"; -- 50
OPCODE <= "0000"; wait for period;
assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0001"; wait for period;
assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0010"; wait for period;
assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0011"; wait for period;
assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
----- END Arithmetic Tests -----
----- CCR Tests -----
RA <= "00000000";
RB <= "00000000";
OPCODE <= "0000"; wait for period;
assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "00000001";
RB <= "11111111";
OPCODE <= "0000"; wait for period;
assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "00000000";
RB <= "00000001";
OPCODE <= "0001"; wait for period;
assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "01111111";
RB <= "00000001";
OPCODE <= "0000"; wait for period;
assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "11111111";
RB <= "00000001";
OPCODE <= "0000"; wait for period;
assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
----- END CCR Tests -----
-- Mem Test --
OPCODE <= "1001"; wait for period;
assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= X"16";
OPCODE <= "1010"; wait for period;
assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "1001"; wait for period;
assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
-- END Mem Test --
report "Finish ALU Test Bench" severity NOTE;
wait; -- will wait forever
END PROCESS;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2528.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n04i02528ent IS
END c07s03b05x00p06n04i02528ent;
ARCHITECTURE c07s03b05x00p06n04i02528arch OF c07s03b05x00p06n04i02528ent IS
BEGIN
TESTING: PROCESS
variable V1 : Integer;
BEGIN
V1 := Integer (10.7);
assert NOT( V1 = 11 )
report "***PASSED TEST: c07s03b05x00p06n04i02528"
severity NOTE;
assert ( V1 = 11 )
report "***FAILED TEST: c07s03b05x00p06n04i02528 - The conversion of a floating point value to an integer type rounds to the nearest integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n04i02528arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2528.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n04i02528ent IS
END c07s03b05x00p06n04i02528ent;
ARCHITECTURE c07s03b05x00p06n04i02528arch OF c07s03b05x00p06n04i02528ent IS
BEGIN
TESTING: PROCESS
variable V1 : Integer;
BEGIN
V1 := Integer (10.7);
assert NOT( V1 = 11 )
report "***PASSED TEST: c07s03b05x00p06n04i02528"
severity NOTE;
assert ( V1 = 11 )
report "***FAILED TEST: c07s03b05x00p06n04i02528 - The conversion of a floating point value to an integer type rounds to the nearest integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n04i02528arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2528.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n04i02528ent IS
END c07s03b05x00p06n04i02528ent;
ARCHITECTURE c07s03b05x00p06n04i02528arch OF c07s03b05x00p06n04i02528ent IS
BEGIN
TESTING: PROCESS
variable V1 : Integer;
BEGIN
V1 := Integer (10.7);
assert NOT( V1 = 11 )
report "***PASSED TEST: c07s03b05x00p06n04i02528"
severity NOTE;
assert ( V1 = 11 )
report "***FAILED TEST: c07s03b05x00p06n04i02528 - The conversion of a floating point value to an integer type rounds to the nearest integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n04i02528arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Andrew Powell
--
-- Create Date: 08/02/2016 04:12:55 PM
-- Design Name:
-- Module Name: spi_cntrl_0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity spi_cntrl_0 is
generic (
SAMPLE_WIDTH : integer := 16
);
port (
s_axi_aclk: in std_logic;
s_axi_aresetn : in std_logic;
enable : in std_logic;
ready : out std_logic;
sample_out : out std_logic_vector( SAMPLE_WIDTH-1 downto 0 );
spi_clk_in : in std_logic;
spi_clk_out : out std_logic;
spi_cs : out std_logic := '1';
spi_sdata : in std_logic
);
end spi_cntrl_0;
architecture Behavioral of spi_cntrl_0 is
type cntrl_state_type is ( CNTRL_STATE_IDLE_0, CNTRL_STATE_WAIT_0, CNTRL_STATE_DONE_0 );
signal cntrl_state : cntrl_state_type := CNTRL_STATE_IDLE_0;
type spi_state_type is ( SPI_STATE_IDLE_0, SPI_STATE_SAMPLE_0, SPI_STATE_DONE_0 );
signal spi_state : spi_state_type := SPI_STATE_IDLE_0;
signal spi_start_req : std_logic;
signal spi_start_ack : std_logic;
signal spi_done_req : std_logic;
signal spi_done_ack : std_logic;
signal spi_clk_en : std_logic;
signal sample_0 : std_logic_vector( SAMPLE_WIDTH-1 downto 0 );
begin
-- Control process
process ( s_axi_aclk )
begin
if ( rising_edge( s_axi_aclk ) ) then
if ( s_axi_aresetn = '0' ) then
cntrl_state <= CNTRL_STATE_IDLE_0;
spi_start_req <= '0';
spi_done_ack <= '0';
ready <= '0';
sample_out <= ( others => '0');
else
case cntrl_state is
when CNTRL_STATE_IDLE_0 =>
if ( enable = '1' and spi_start_req = spi_start_ack ) then
spi_start_req <= not( spi_start_req );
cntrl_state <= CNTRL_STATE_WAIT_0;
end if;
when CNTRL_STATE_WAIT_0 =>
if ( spi_done_req /= spi_done_ack ) then
spi_done_ack <= not( spi_done_ack );
sample_out <= sample_0;
ready <= '1';
cntrl_state <= CNTRL_STATE_DONE_0;
end if;
when CNTRL_STATE_DONE_0 =>
if ( enable = '0' ) then
ready <= '0';
cntrl_state <= CNTRL_STATE_IDLE_0;
end if;
when others => null;
end case;
end if;
end if;
end process;
-- SPI process
spi_cs <= not(spi_clk_en);
spi_clk_out <= spi_clk_in and spi_clk_en;
process ( spi_clk_in, s_axi_aresetn )
variable counter_0 : integer range 0 to SAMPLE_WIDTH;
begin
if ( s_axi_aresetn = '0' ) then
spi_state <= SPI_STATE_IDLE_0;
spi_start_ack <= '0';
spi_done_req <= '0';
spi_clk_en <= '0';
sample_0 <= ( others => '0' );
counter_0 := 0;
elsif ( rising_edge( spi_clk_in ) ) then
case spi_state is
when SPI_STATE_IDLE_0 =>
if ( spi_start_req /= spi_start_ack ) then
spi_start_ack <= not( spi_start_ack );
spi_clk_en <= '1';
spi_state <= SPI_STATE_SAMPLE_0;
end if;
when SPI_STATE_SAMPLE_0 =>
if ( counter_0 /= SAMPLE_WIDTH ) then
sample_0( SAMPLE_WIDTH-1 downto 1 ) <= sample_0( SAMPLE_WIDTH-2 downto 0 );
sample_0( 0 ) <= spi_sdata;
counter_0 := counter_0+1;
else
spi_clk_en <= '0';
spi_state <= SPI_STATE_DONE_0;
counter_0 := 0;
end if;
when SPI_STATE_DONE_0 =>
if ( spi_done_req = spi_done_ack ) then
spi_done_req <= not( spi_done_req );
spi_state <= SPI_STATE_IDLE_0;
end if;
when others => null;
end case;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_08 is
-- code from book
procedure uniform ( variable seed1, seed2 : inout positive;
variable x : out real);
-- end code from book
end package inline_08;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_08 is
-- code from book
procedure uniform ( variable seed1, seed2 : inout positive;
variable x : out real);
-- end code from book
end package inline_08;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_08 is
-- code from book
procedure uniform ( variable seed1, seed2 : inout positive;
variable x : out real);
-- end code from book
end package inline_08;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue414 is
end issue414;
architecture behavioral of issue414 is
signal clk : std_logic := '0';
signal addr : std_logic_vector(55 downto 0);
signal wdata : std_logic_vector(31 downto 0);
subtype uword64 is unsigned(63 downto 0);
signal running : boolean := true;
begin
process (clk, running)
begin
if running then
clk <= not clk after 5 ns;
end if;
end process;
process
procedure wr_data(address_in : std_logic_vector; data : std_logic_vector;
do_wait : boolean) is
-- Without this things work!
constant address : std_logic_vector(address_in'length - 1 downto 0) := address_in;
begin
-- Without this I get, for high enough loop counts (1000000+):
-- zsh: segmentation fault nvc -a bug4.vhd -e bug4 -r
if do_wait then
wait until clk = '1';
end if;
end;
procedure wr_data(address : unsigned; data : unsigned;
do_wait : boolean) is
begin
wr_data(std_logic_vector(address), std_logic_vector(data), do_wait);
end;
variable addr : unsigned(55 downto 0) := (others => '0');
variable slvdata : unsigned(31 downto 0) := (others => '0');
begin
-- 1000 is OK
for n in 0 to 4000 loop
wr_data(addr, slvdata, do_wait => true); -- SIGBUS crash
end loop;
for n in 0 to 1000000 loop
wr_data(addr, slvdata, do_wait => false); -- Stack overflow
end loop;
assert false report "Test OK" severity warning;
running <= false;
wait;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:52:18 11/16/2016
-- Design Name:
-- Module Name: bcdadder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bcdadder is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end bcdadder;
architecture Behavioral of bcdadder is
signal raw_sum, adjusted_sum: std_logic_vector(5 downto 0);
begin
raw_sum <= std_logic_vector(unsigned('0' & a & cin) + unsigned('0' & b & cin));
adjusted_sum <= raw_sum when (raw_sum < "010100") else std_logic_vector(unsigned(raw_sum) + "001100");
sum <= adjusted_sum(4 downto 1);
cout <= adjusted_sum(5);
end Behavioral;
|
--/////////////////////////////////////////////////////////////////////////
--// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
--//
--// XILINX CONFIDENTIAL PROPERTY
--// This document contains proprietary information which is
--// protected by copyright. All rights are reserved. This notice
--// refers to original work by Xilinx, Inc. which may be derivitive
--// of other work distributed under license of the authors. In the
--// case of derivitive work, nothing in this notice overrides the
--// original author's license agreeement. Where applicable, the
--// original license agreement is included in it's original
--// unmodified form immediately below this header.
--//
--// Xilinx, Inc.
--// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
--// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
--// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
--// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
--// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
--// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
--// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
--// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
--// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
--// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
--// AND FITNESS FOR A PARTICULAR PURPOSE.
--//
--/////////////////////////////////////////////////////////////////////////
-- This is round_1 of the FFT calculation
-- Step size is 1 so X and X +1 are mixed together
-- X0 with X1, X2 with X3 and etc
-- U is a constant with a bogus value - you will want to change it
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
library bftLib;
use bftLib.bftPackage.all;
entity round_1 is
port (
clk: in std_logic;
x : in xType;
xOut : out xType
);
end entity round_1;
architecture aR1 of round_1 is
constant u : uType :=
(X"0123",
X"4567",
X"89AB",
X"CDEF",
X"0123",
X"4567",
X"89AB",
X"CDEF");
begin
transformLoop: for N in 0 to 7 generate
ct: entity bftLib.coreTransform(aCT)
generic map (DATA_WIDTH=> DATA_WIDTH)
port map (clk => clk, x =>x(2*N), xStep=>x(2*N+1), u=>u(N), xOut=>xOut(2*N), xOutStep =>xOut(2*N+1));
end generate transformLoop;
end architecture aR1;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ganesh Hegde and Alex
--
-- Create Date: 09/01/2015 10:52:25 AM
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port (
UP: in std_logic;
AUTO: in std_logic;
LOAD: in std_logic;
VALUE: in std_logic_vector(3 downto 0);
TICK: in std_logic;
COUNT: out std_logic_vector(3 downto 0);
RESET: in std_logic;
clk: in std_logic
);
end counter;
architecture Behavioral of counter is
signal n_count:unsigned(3 downto 0);
signal p_count:unsigned(3 downto 0);
signal sum: unsigned(3 downto 0);
signal addend: unsigned(3 downto 0);
signal clk_1sec:std_logic;
signal pulse: std_logic;
signal clk_count : unsigned(26 downto 0);
begin
--Clock process
process(clk,RESET)
begin
if(RESET ='1') then
clk_1sec <= '0';
clk_count <= (others => '0');
elsif (clk' event and clk ='1') then
clk_count <= clk_count + 1;
clk_1sec <= std_logic(clk_count(26));
end if;
end process;
--State register
process(pulse,RESET)
begin
if(RESET = '1') then
p_count <= (others =>'0');
elsif(pulse' event and pulse ='1') then
p_count <= n_count;
end if;
end process;
--State reg clock logic
with AUTO select
pulse <= TICK when '0',
clk_1sec when others;
--Next state logic
with LOAD select
n_count <= sum when '0',
unsigned(VALUE) when others;
--UP/DOWN select
with UP select
addend <= "1111" when '0',
"0001" when others;
--Adder
sum <= p_count + addend;
--Output Logic
COUNT <= std_logic_vector(p_count);
end Behavioral;
|
{{define "top"}}-- This file has been automatically generated by goFB and should not be edited by hand
-- Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
-- VHDL support is EXPERIMENTAL ONLY
{{$block := index .Blocks .BlockIndex}}{{$blocks := .Blocks}}{{$specialIO := $block.GetSpecialIO .Blocks}}
-- This file represents the top level file for the IEC61499 network with {{$block.Name}} as the top level block
-- This is the file that you should embed into your vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iec61499_network_top is
port(
--for clock and reset signal
clk : in std_logic;
reset : in std_logic;
{{if $block.BasicFB}}{{if $specialIO.InternalVars}}
--special emitted internal vars for I/O
{{range $index, $var := $specialIO.InternalVars}}{{$var.Name}} : {{if $var.IsTOPIO_IN}}in{{else}}out{{end}} {{getVhdlType $var.Type}}; --type was {{$var.Type}}
{{end}}{{end}}{{else if $block.CompositeFB}}{{if $specialIO.InternalVars}}
--special emitted internal variables for child I/O
{{range $index, $var := $specialIO.InternalVars}}{{$var.Name}} : {{if $var.IsTOPIO_IN}}in{{else}}out{{end}} {{getVhdlType $var.Type}}; --type was {{$var.Type}}
{{end}}{{end}}{{end}}
--signals in case external components want to measure time
debug_enable: out std_logic;
debug_sync: out std_logic;
debug_done: out std_logic
);
end entity;
architecture rtl of iec61499_network_top is
-- Build an enumerated type for the state machine
type state_type is (STATE_sync, STATE_wait_sync_done, STATE_run, STATE_wait_run_done);
-- Register to hold the current state
signal state : state_type := STATE_sync;
signal enable : std_logic := '0';
signal sync : std_logic := '0';
signal done : std_logic := '0';
begin
--port map for top level block
top_block: entity work.{{$block.Name}} port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
{{if $block.BasicFB}}{{if $specialIO.InternalVars}}
--special emitted internal vars for I/O
{{range $index, $var := $specialIO.InternalVars}}{{$var.Name}} => {{$var.Name}}, --going {{if $var.IsTOPIO_IN}}in{{else}}out{{end}}
{{end}}{{end}}{{else if $block.CompositeFB}}{{if $specialIO.InternalVars}}
--special emitted internal variables for child I/O
{{range $index, $var := $specialIO.InternalVars}}{{$var.Name}} => {{$var.Name}}, --going {{if $var.IsTOPIO_IN}}in{{else}}out{{end}}
{{end}}{{end}}{{end}}
done => done
);
process (clk, reset)
begin
if reset = '1' then
state <= STATE_sync;
elsif (rising_edge(clk)) then
--default values
state <= state;
enable <= '0';
sync <= '0';
case state is
when STATE_sync =>
sync <= '1';
state <= STATE_wait_sync_done;
when STATE_wait_sync_done => --TODO sync_done signal
state <= STATE_run;
when STATE_run =>
enable <= '1';
state <= STATE_wait_run_done;
when STATE_wait_run_done =>
if done='1' then
state <= STATE_sync;
end if;
end case;
end if;
end process;
debug_done <= done;
debug_enable <= enable;
debug_sync <= sync;
end rtl;
{{end}}
|
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0 is
port(
clk_clk_clk : in vl_logic;
clocks_c0_clk : in vl_logic;
cpu_reset_n_reset_bridge_in_reset_reset: in vl_logic;
sdram_reset_reset_bridge_in_reset_reset: in vl_logic;
cpu_data_master_address: in vl_logic_vector(28 downto 0);
cpu_data_master_waitrequest: out vl_logic;
cpu_data_master_byteenable: in vl_logic_vector(3 downto 0);
cpu_data_master_read: in vl_logic;
cpu_data_master_readdata: out vl_logic_vector(31 downto 0);
cpu_data_master_write: in vl_logic;
cpu_data_master_writedata: in vl_logic_vector(31 downto 0);
cpu_data_master_debugaccess: in vl_logic;
cpu_instruction_master_address: in vl_logic_vector(28 downto 0);
cpu_instruction_master_waitrequest: out vl_logic;
cpu_instruction_master_read: in vl_logic;
cpu_instruction_master_readdata: out vl_logic_vector(31 downto 0);
clock_crossing_io_s0_address: out vl_logic_vector(21 downto 0);
clock_crossing_io_s0_write: out vl_logic;
clock_crossing_io_s0_read: out vl_logic;
clock_crossing_io_s0_readdata: in vl_logic_vector(31 downto 0);
clock_crossing_io_s0_writedata: out vl_logic_vector(31 downto 0);
clock_crossing_io_s0_burstcount: out vl_logic_vector(0 downto 0);
clock_crossing_io_s0_byteenable: out vl_logic_vector(3 downto 0);
clock_crossing_io_s0_readdatavalid: in vl_logic;
clock_crossing_io_s0_waitrequest: in vl_logic;
clock_crossing_io_s0_debugaccess: out vl_logic;
clocks_pll_slave_address: out vl_logic_vector(1 downto 0);
clocks_pll_slave_write: out vl_logic;
clocks_pll_slave_read: out vl_logic;
clocks_pll_slave_readdata: in vl_logic_vector(31 downto 0);
clocks_pll_slave_writedata: out vl_logic_vector(31 downto 0);
cpu_jtag_debug_module_address: out vl_logic_vector(8 downto 0);
cpu_jtag_debug_module_write: out vl_logic;
cpu_jtag_debug_module_read: out vl_logic;
cpu_jtag_debug_module_readdata: in vl_logic_vector(31 downto 0);
cpu_jtag_debug_module_writedata: out vl_logic_vector(31 downto 0);
cpu_jtag_debug_module_byteenable: out vl_logic_vector(3 downto 0);
cpu_jtag_debug_module_waitrequest: in vl_logic;
cpu_jtag_debug_module_debugaccess: out vl_logic;
jtag_uart_avalon_jtag_slave_address: out vl_logic_vector(0 downto 0);
jtag_uart_avalon_jtag_slave_write: out vl_logic;
jtag_uart_avalon_jtag_slave_read: out vl_logic;
jtag_uart_avalon_jtag_slave_readdata: in vl_logic_vector(31 downto 0);
jtag_uart_avalon_jtag_slave_writedata: out vl_logic_vector(31 downto 0);
jtag_uart_avalon_jtag_slave_waitrequest: in vl_logic;
jtag_uart_avalon_jtag_slave_chipselect: out vl_logic;
keycode_s1_address: out vl_logic_vector(1 downto 0);
keycode_s1_write: out vl_logic;
keycode_s1_readdata: in vl_logic_vector(31 downto 0);
keycode_s1_writedata: out vl_logic_vector(31 downto 0);
keycode_s1_chipselect: out vl_logic;
sdram_s1_address: out vl_logic_vector(24 downto 0);
sdram_s1_write : out vl_logic;
sdram_s1_read : out vl_logic;
sdram_s1_readdata: in vl_logic_vector(31 downto 0);
sdram_s1_writedata: out vl_logic_vector(31 downto 0);
sdram_s1_byteenable: out vl_logic_vector(3 downto 0);
sdram_s1_readdatavalid: in vl_logic;
sdram_s1_waitrequest: in vl_logic;
sdram_s1_chipselect: out vl_logic
);
end usb_system_mm_interconnect_0;
|
----------------------------------------------------------------------------------
-- Company:
-- EngINeer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: KbdTxData
-- Target Devices:
-- Tool versions: XilINx ISE 14.4
-- Description:
-- http://www.computer-engINeerINg.org/ps2protocol/
--
-- 1) BrINg the Clock lINe low for at least 100 microseconds.
-- 2) BrINg the Data lINe low.
-- 3) Release the Clock lINe.
-- 4) Wait for the device to brINg the Clock lINe low.
-- 5) Set/reset the Data lINe to Tx_en the first data bit
-- 6) Wait for the device to brINg Clock high.
-- 7) Wait for the device to brINg Clock low.
-- 8) Repeat steps 5-7 for the other seven data bits and the parity bit
-- 9) Release the Data lINe.
-- 10) Wait for the device to brINg Data low.
-- 11) Wait for the device to brINg Clock low.
-- 12) Wait for the device to release Data and Clock
-- DepENDencies:
--
-- RevISion:
-- RevISion 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity KbdTxData IS
Port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
Tx_en : IN STD_LOGIC;
kbd_dataf : IN STD_LOGIC;
kbd_clkf : IN STD_LOGIC;
Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
busy : OUT STD_LOGIC;
T_Data : OUT STD_LOGIC; --WHEN T=0, IO = OUT; WHEN T=1, IO = IN;
T_Clk : OUT STD_LOGIC; --WHEN T=0, IO = OUT; WHEN T=1, IO = IN;
KbdData : OUT STD_LOGIC;
KbdClk : OUT STD_LOGIC
);
END KbdTxData;
ARCHITECTURE Behavioral OF KbdTxData IS
TYPE state_type IS (reset,INit, clkLow,
startSEND,startbit,
bitshIFt,bitsEND,
parity,tempo_parity,
stopbit,akn,
DevRelease,ENDFSM);
SIGNAL state, next_state: state_type ;
SIGNAL cnt : std_logic_vector(12 DOWNTO 0):=(OTHERS=>'0');
SIGNAL startCount : std_logic:='0';
SIGNAL ENDCount : std_logic:='0';
SIGNAL shIFt : std_logic:='0';
SIGNAL ENDshIFt : std_logic:='0';
SIGNAL shIFtcnt : std_logic_vector(2 DOWNTO 0):=(OTHERS=>'0');
SIGNAL dataReg : std_logic_vector(7 DOWNTO 0):=(OTHERS=>'0');
SIGNAL INt_busy : std_logic;
SIGNAL INt_T_Clk : std_logic;
SIGNAL INt_T_Data : std_logic;
SIGNAL INt_KbdData : std_logic;
SIGNAL INt_KbdClk : std_logic;
BEGIN
Sequential: PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
state <= INit;
ELSIF (clk='1' and clk'Event) THEN
state <= next_state;
END IF;
END PROCESS;
-- Counter
PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
cnt <= (OTHERS=>'0');
ENDCount <= '0';
ELSIF (clk = '1' and clk'Event) THEN
ENDCount <= '0';
cnt <= (OTHERS=>'0');
IF(startCount = '1') THEN
cnt <= cnt+'1';
IF (cnt = X"1388") THEN -- 100 us
cnt <= (OTHERS=>'0');
ENDCount <= '1';
END IF;
END IF;
END IF;
END PROCESS;
Dataproc:PROCESS(clk,rst)
BEGIN
IF (rst = '1') THEN
dataReg <= X"FF";
shIFtcnt <= "000";
ENDshIFt <= '0';
ELSIF (clk = '1' and clk'Event) THEN
IF (state = INit) THEN
dataReg <= data;
shIFtcnt <= "000";
ENDshIFt <= '0';
ELSIF (shIFtcnt = "111") THEN
shIFtcnt <= "000";
ENDshIFt <= '1';
ELSIF (shIFt = '1') THEN
ENDshIFt <= '0';
shIFtcnt <= shIFtcnt + '1';
dataReg <= dataReg(0) & dataReg(7 DOWNTO 1);
END IF;
END IF;
END PROCESS;
CntrlFSM : PROCESS (state, kbd_clkf, kbd_dataf,ENDCount,Tx_en,ENDshIFt)
BEGIN
CASE state IS
WHEN reset =>
INt_busy <= '0';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
next_state <= clkLow;
WHEN INit =>
INt_busy <= '0';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
IF (Tx_en = '1') THEN
next_state <= clkLow;
ELSIF (Tx_en='0') THEN
next_state <= INit;
END IF;
WHEN clkLow =>
INt_busy <= '1';
INt_T_Clk <= '0';
INt_T_Data <= '1';
shIFt <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '0';
IF (ENDCount = '1') THEN
startCount <= '0';
next_state <= startSEND;
ELSE
startCount <= '1';
next_state <= clkLow;
END IF;
WHEN startSEND =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '0';
startCount <= '0';
IF (kbd_clkf = '1') THEN
next_state <= startbit;
ELSE
next_state <= startSEND;
END IF;
WHEN startbit =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '0';
startCount <= '0';
IF (kbd_clkf = '0') THEN
next_state <= bitshIFt;
ELSE
next_state <= startbit;
END IF;
WHEN bitshIFt =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= dataReg(0);
startCount <='0';
IF (kbd_clkf = '1') THEN
next_state <= bitsEND;
ELSE
next_state <= bitshIFt;
END IF;
WHEN bitsEND =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
INt_KbdClk <= '1';
INt_KbdData <= dataReg(0);
startCount <= '0';
IF (kbd_clkf = '1') THEN
shIFt <= '0';
next_state <= bitsEND;
ELSIF (ENDshIFt = '1') THEN
shIFt <= '0';
next_state <= parity;
ELSE
shIFt <= '1';
next_state <= bitshIFt;
END IF;
WHEN parity =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= not(DataReg(7) xor DataReg(6) xor DataReg(5) xor DataReg(4) xor DataReg(3) xor DataReg(2) xor DataReg(1) xor DataReg(0));
startCount <= '0';
IF (kbd_clkf = '1') THEN
next_state <= tempo_parity;
ELSE
next_state <= parity;
END IF;
WHEN tempo_parity =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= not(DataReg(7) xor DataReg(6) xor DataReg(5) xor DataReg(4) xor DataReg(3) xor DataReg(2) xor DataReg(1) xor DataReg(0));
startCount <= '0';
IF (kbd_clkf = '0') THEN
next_state <= stopbit;
ELSE
next_state <= tempo_parity;
END IF;
WHEN stopbit =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '1';
startCount <= '0';
IF kbd_clkf = '1' THEN
next_state <= akn;
ELSE
next_state <= stopbit;
END IF;
WHEN Akn =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '1';
startCount <= '0';
IF (kbd_dataf = '0') THEN
next_state <= DevRelease;
ELSE
next_state <= Akn;
END IF;
WHEN DevRelease =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
IF (kbd_dataf = '1') THEN
next_state <= ENDFSM;
ELSE
next_state <= DevRelease;
END IF;
WHEN ENDFSM =>
INt_busy <= '0';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
next_state <= INit;
END case;
END PROCESS;
OUTput: PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
busy <= '0';
T_Clk <= '1';
T_Data <= '1';
KbdData <= '1';
KbdClk <= '1';
ELSIF (clk='1' and clk'Event) THEN
busy <= INt_busy;
T_Clk <= INt_T_Clk;
T_Data <= INt_T_Data;
KbdData <= INt_KbdData;
KbdClk <= INt_KbdClk;
END IF;
END PROCESS;
END Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- EngINeer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: KbdTxData
-- Target Devices:
-- Tool versions: XilINx ISE 14.4
-- Description:
-- http://www.computer-engINeerINg.org/ps2protocol/
--
-- 1) BrINg the Clock lINe low for at least 100 microseconds.
-- 2) BrINg the Data lINe low.
-- 3) Release the Clock lINe.
-- 4) Wait for the device to brINg the Clock lINe low.
-- 5) Set/reset the Data lINe to Tx_en the first data bit
-- 6) Wait for the device to brINg Clock high.
-- 7) Wait for the device to brINg Clock low.
-- 8) Repeat steps 5-7 for the other seven data bits and the parity bit
-- 9) Release the Data lINe.
-- 10) Wait for the device to brINg Data low.
-- 11) Wait for the device to brINg Clock low.
-- 12) Wait for the device to release Data and Clock
-- DepENDencies:
--
-- RevISion:
-- RevISion 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity KbdTxData IS
Port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
Tx_en : IN STD_LOGIC;
kbd_dataf : IN STD_LOGIC;
kbd_clkf : IN STD_LOGIC;
Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
busy : OUT STD_LOGIC;
T_Data : OUT STD_LOGIC; --WHEN T=0, IO = OUT; WHEN T=1, IO = IN;
T_Clk : OUT STD_LOGIC; --WHEN T=0, IO = OUT; WHEN T=1, IO = IN;
KbdData : OUT STD_LOGIC;
KbdClk : OUT STD_LOGIC
);
END KbdTxData;
ARCHITECTURE Behavioral OF KbdTxData IS
TYPE state_type IS (reset,INit, clkLow,
startSEND,startbit,
bitshIFt,bitsEND,
parity,tempo_parity,
stopbit,akn,
DevRelease,ENDFSM);
SIGNAL state, next_state: state_type ;
SIGNAL cnt : std_logic_vector(12 DOWNTO 0):=(OTHERS=>'0');
SIGNAL startCount : std_logic:='0';
SIGNAL ENDCount : std_logic:='0';
SIGNAL shIFt : std_logic:='0';
SIGNAL ENDshIFt : std_logic:='0';
SIGNAL shIFtcnt : std_logic_vector(2 DOWNTO 0):=(OTHERS=>'0');
SIGNAL dataReg : std_logic_vector(7 DOWNTO 0):=(OTHERS=>'0');
SIGNAL INt_busy : std_logic;
SIGNAL INt_T_Clk : std_logic;
SIGNAL INt_T_Data : std_logic;
SIGNAL INt_KbdData : std_logic;
SIGNAL INt_KbdClk : std_logic;
BEGIN
Sequential: PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
state <= INit;
ELSIF (clk='1' and clk'Event) THEN
state <= next_state;
END IF;
END PROCESS;
-- Counter
PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
cnt <= (OTHERS=>'0');
ENDCount <= '0';
ELSIF (clk = '1' and clk'Event) THEN
ENDCount <= '0';
cnt <= (OTHERS=>'0');
IF(startCount = '1') THEN
cnt <= cnt+'1';
IF (cnt = X"1388") THEN -- 100 us
cnt <= (OTHERS=>'0');
ENDCount <= '1';
END IF;
END IF;
END IF;
END PROCESS;
Dataproc:PROCESS(clk,rst)
BEGIN
IF (rst = '1') THEN
dataReg <= X"FF";
shIFtcnt <= "000";
ENDshIFt <= '0';
ELSIF (clk = '1' and clk'Event) THEN
IF (state = INit) THEN
dataReg <= data;
shIFtcnt <= "000";
ENDshIFt <= '0';
ELSIF (shIFtcnt = "111") THEN
shIFtcnt <= "000";
ENDshIFt <= '1';
ELSIF (shIFt = '1') THEN
ENDshIFt <= '0';
shIFtcnt <= shIFtcnt + '1';
dataReg <= dataReg(0) & dataReg(7 DOWNTO 1);
END IF;
END IF;
END PROCESS;
CntrlFSM : PROCESS (state, kbd_clkf, kbd_dataf,ENDCount,Tx_en,ENDshIFt)
BEGIN
CASE state IS
WHEN reset =>
INt_busy <= '0';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
next_state <= clkLow;
WHEN INit =>
INt_busy <= '0';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
IF (Tx_en = '1') THEN
next_state <= clkLow;
ELSIF (Tx_en='0') THEN
next_state <= INit;
END IF;
WHEN clkLow =>
INt_busy <= '1';
INt_T_Clk <= '0';
INt_T_Data <= '1';
shIFt <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '0';
IF (ENDCount = '1') THEN
startCount <= '0';
next_state <= startSEND;
ELSE
startCount <= '1';
next_state <= clkLow;
END IF;
WHEN startSEND =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '0';
startCount <= '0';
IF (kbd_clkf = '1') THEN
next_state <= startbit;
ELSE
next_state <= startSEND;
END IF;
WHEN startbit =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '0';
startCount <= '0';
IF (kbd_clkf = '0') THEN
next_state <= bitshIFt;
ELSE
next_state <= startbit;
END IF;
WHEN bitshIFt =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= dataReg(0);
startCount <='0';
IF (kbd_clkf = '1') THEN
next_state <= bitsEND;
ELSE
next_state <= bitshIFt;
END IF;
WHEN bitsEND =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
INt_KbdClk <= '1';
INt_KbdData <= dataReg(0);
startCount <= '0';
IF (kbd_clkf = '1') THEN
shIFt <= '0';
next_state <= bitsEND;
ELSIF (ENDshIFt = '1') THEN
shIFt <= '0';
next_state <= parity;
ELSE
shIFt <= '1';
next_state <= bitshIFt;
END IF;
WHEN parity =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= not(DataReg(7) xor DataReg(6) xor DataReg(5) xor DataReg(4) xor DataReg(3) xor DataReg(2) xor DataReg(1) xor DataReg(0));
startCount <= '0';
IF (kbd_clkf = '1') THEN
next_state <= tempo_parity;
ELSE
next_state <= parity;
END IF;
WHEN tempo_parity =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= not(DataReg(7) xor DataReg(6) xor DataReg(5) xor DataReg(4) xor DataReg(3) xor DataReg(2) xor DataReg(1) xor DataReg(0));
startCount <= '0';
IF (kbd_clkf = '0') THEN
next_state <= stopbit;
ELSE
next_state <= tempo_parity;
END IF;
WHEN stopbit =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '0';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '1';
startCount <= '0';
IF kbd_clkf = '1' THEN
next_state <= akn;
ELSE
next_state <= stopbit;
END IF;
WHEN Akn =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
INt_KbdClk <= '1';
INt_KbdData <= '1';
startCount <= '0';
IF (kbd_dataf = '0') THEN
next_state <= DevRelease;
ELSE
next_state <= Akn;
END IF;
WHEN DevRelease =>
INt_busy <= '1';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
IF (kbd_dataf = '1') THEN
next_state <= ENDFSM;
ELSE
next_state <= DevRelease;
END IF;
WHEN ENDFSM =>
INt_busy <= '0';
INt_T_Clk <= '1';
INt_T_Data <= '1';
shIFt <= '0';
startCount <= '0';
INt_KbdData <= '1';
INt_KbdClk <= '1';
next_state <= INit;
END case;
END PROCESS;
OUTput: PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
busy <= '0';
T_Clk <= '1';
T_Data <= '1';
KbdData <= '1';
KbdClk <= '1';
ELSIF (clk='1' and clk'Event) THEN
busy <= INt_busy;
T_Clk <= INt_T_Clk;
T_Data <= INt_T_Data;
KbdData <= INt_KbdData;
KbdClk <= INt_KbdClk;
END IF;
END PROCESS;
END Behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_1_block.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF1_1_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_3_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_3_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_4_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_4_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_3_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_4_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_4_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_3_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block IS
-- Signals
SIGNAL twdlXdin_3_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdlXdin_3_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdlXdin_4_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdlXdin_4_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_3_re_tmp : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_3_im_tmp : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_4_re_tmp : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_4_im_tmp : signed(16 DOWNTO 0); -- sfix17_En13
BEGIN
twdlXdin_3_re_signed <= signed(twdlXdin_3_re);
twdlXdin_3_im_signed <= signed(twdlXdin_3_im);
twdlXdin_4_re_signed <= signed(twdlXdin_4_re);
twdlXdin_4_im_signed <= signed(twdlXdin_4_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_3_re_signed,
twdlXdin_3_im_signed, twdlXdin_4_re_signed, twdlXdin_4_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(17 DOWNTO 0);
VARIABLE add_cast_0 : signed(17 DOWNTO 0);
VARIABLE sub_cast : signed(17 DOWNTO 0);
VARIABLE sub_cast_0 : signed(17 DOWNTO 0);
VARIABLE add_cast_1 : signed(17 DOWNTO 0);
VARIABLE add_cast_2 : signed(17 DOWNTO 0);
VARIABLE sub_cast_1 : signed(17 DOWNTO 0);
VARIABLE sub_cast_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_3_re_signed, 18);
add_cast_0 := resize(twdlXdin_4_re_signed, 18);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_3_re_signed, 18);
sub_cast_0 := resize(twdlXdin_4_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_3_im_signed, 18);
add_cast_2 := resize(twdlXdin_4_im_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_3_im_signed, 18);
sub_cast_2 := resize(twdlXdin_4_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
dout_3_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(16 DOWNTO 0);
dout_3_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(16 DOWNTO 0);
dout_4_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(16 DOWNTO 0);
dout_4_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(16 DOWNTO 0);
dout_3_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_3_re <= std_logic_vector(dout_3_re_tmp);
dout_3_im <= std_logic_vector(dout_3_im_tmp);
dout_4_re <= std_logic_vector(dout_4_re_tmp);
dout_4_im <= std_logic_vector(dout_4_im_tmp);
END rtl;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock1_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock1_e-rtl-a.vhd,v 1.1 2004/04/06 10:44:22 wig Exp $
-- $Date: 2004/04/06 10:44:22 $
-- $Log: ioblock1_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:44:22 wig
-- Adding result/padio
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Revision: 1.17 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock1_e
--
architecture rtl of ioblock1_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioc_r_io --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_io
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(4 downto 0);
en : in std_ulogic_vector(4 downto 0);
p_di : in std_ulogic;
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity ioc_r_io
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BUS_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioc_disp_2
ioc_disp_2: ioc_r_io
port map (
di => di2(0), -- io data
do(0) => disp2(0), -- io data
do(1) => display_ls_min(0), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(0), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(0), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(0), -- Display storage buffer 1 ms_min
en(0) => disp2_en(0), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_12, -- data in from pad
p_do => pad_do_12, -- data out to pad
p_en => pad_en_12, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_2
-- Generated Instance Port Map for ioc_disp_3
ioc_disp_3: ioc_r_io
port map (
di => di2(1), -- io data
do(0) => disp2(1), -- io data
do(1) => display_ls_min(1), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(1), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(1), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(1), -- Display storage buffer 1 ms_min
en(0) => disp2_en(1), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_13, -- data in from pad
p_do => pad_do_13, -- data out to pad
p_en => pad_en_13, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_3
-- Generated Instance Port Map for ioc_disp_4
ioc_disp_4: ioc_r_io
port map (
di => di2(3), -- io data
do(0) => disp2(3), -- io data
do(1) => display_ls_min(2), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(2), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(2), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(2), -- Display storage buffer 1 ms_min
en(0) => disp2_en(3), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_14, -- data in from pad
p_do => pad_do_14, -- data out to pad
p_en => pad_en_14, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_4
-- Generated Instance Port Map for ioc_disp_5
ioc_disp_5: ioc_r_io
port map (
di => di2(4), -- io data
do(0) => disp2(4), -- io data
do(1) => display_ls_min(3), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(3), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(3), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(3), -- Display storage buffer 1 ms_min
en(0) => disp2_en(4), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_15, -- data in from pad
p_do => pad_do_15, -- data out to pad
p_en => pad_en_15, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_5
-- Generated Instance Port Map for ioc_disp_6
ioc_disp_6: ioc_r_io
port map (
di => di2(5), -- io data
do(0) => disp2(5), -- io data
do(1) => display_ls_min(4), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(4), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(4), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(4), -- Display storage buffer 1 ms_min
en(0) => disp2_en(5), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_16, -- data in from pad
p_do => pad_do_16, -- data out to pad
p_en => pad_en_16, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_6
-- Generated Instance Port Map for ioc_disp_7
ioc_disp_7: ioc_r_io
port map (
di => di2(6), -- io data
do(0) => disp2(6), -- io data
do(1) => display_ls_min(5), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(5), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(5), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(5), -- Display storage buffer 1 ms_min
en(0) => disp2_en(6), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_17, -- data in from pad
p_do => pad_do_17, -- data out to pad
p_en => pad_en_17, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_7
-- Generated Instance Port Map for ioc_disp_8
ioc_disp_8: ioc_r_io
port map (
di => di2(7), -- io data
do(0) => disp2(7), -- io data
do(1) => display_ls_min(6), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(6), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(6), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(6), -- Display storage buffer 1 ms_min
en(0) => disp2_en(7), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_18, -- data in from pad
p_do => pad_do_18, -- data out to pad
p_en => pad_en_18, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_8
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 14:41:49 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_system_ila_0_0_stub.vhdl
-- Design : zqynq_lab_1_design_system_ila_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "bd_1a88,Vivado 2017.2.1";
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
port (
clock_50MHz: in std_logic;
clock_25MHz: out std_logic;
clock_1MHz: out std_logic;
clock_500KHz: out std_logic;
clock_115200Hz: out std_logic
);
end clk_div;
architecture b of clk_div is
-- clock 25
signal clock_25MHz_int: std_logic := '0';
-- others
signal count_1MHz: std_logic_vector(4 downto 0);
signal clock_1MHz_int: std_logic := '0';
signal count_500KHz: std_logic_vector(5 downto 0);
signal clock_500KHz_int: std_logic := '0';
signal count_115200Hz: std_logic_vector(7 downto 0);
signal clock_115200Hz_int: std_logic;
begin
-- 25MHz, devide by 2
process
begin
wait until clock_50MHz'event and clock_50MHz = '1';
clock_25MHz <= clock_25MHz_int;
clock_25MHz_int <= not clock_25MHz_int;
end process;
-- 1MHz, devide by 50
process
begin
wait until clock_50MHz'event and clock_50MHz = '1';
if count_1MHz /= 25 then
count_1MHz <= count_1MHz + 1;
else
count_1MHz <= "00000";
clock_1MHz_int <= not clock_1MHz_int;
end if;
clock_1MHz <= clock_1MHz_int;
end process;
-- 500KHz, devide by 100
process
begin
wait until clock_50MHz'event and clock_50MHz = '1';
if count_500KHz /= 50 then
count_500KHz <= count_500KHz + 1;
else
count_500KHz <= "000000";
clock_500KHz_int <= not clock_500KHz_int;
end if;
clock_500KHz <= clock_500KHz_int;
end process;
-- 115200Hz, divide by 434
process
begin
wait until clock_50MHz'event and clock_50MHz = '1';
if count_115200Hz /= 216 then
count_115200Hz <= count_115200Hz + 1;
else
count_115200Hz <= "00000000";
clock_115200Hz_int <= not clock_115200Hz_int;
end if;
clock_115200Hz <= clock_115200Hz_int;
end process;
end b;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2254.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02254ent IS
END c07s02b06x00p01n01i02254ent;
ARCHITECTURE c07s02b06x00p01n01i02254arch OF c07s02b06x00p01n01i02254ent IS
BEGIN
TESTING: PROCESS
variable I : INTEGER;
BEGIN
I := 1 / 0; -- should yield divide-by-zero error
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02254 - Integer can not divided by zero."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02254arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2254.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02254ent IS
END c07s02b06x00p01n01i02254ent;
ARCHITECTURE c07s02b06x00p01n01i02254arch OF c07s02b06x00p01n01i02254ent IS
BEGIN
TESTING: PROCESS
variable I : INTEGER;
BEGIN
I := 1 / 0; -- should yield divide-by-zero error
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02254 - Integer can not divided by zero."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02254arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2254.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02254ent IS
END c07s02b06x00p01n01i02254ent;
ARCHITECTURE c07s02b06x00p01n01i02254arch OF c07s02b06x00p01n01i02254ent IS
BEGIN
TESTING: PROCESS
variable I : INTEGER;
BEGIN
I := 1 / 0; -- should yield divide-by-zero error
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02254 - Integer can not divided by zero."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02254arch;
|
--================================================================================================================================
-- Copyright (c) 2020 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the Apache License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO
-- THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--================================================================================================================================
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.support_pkg.all;
library bitvis_vip_gmii;
context bitvis_vip_gmii.vvc_context;
architecture GMII of hvvc_to_vvc_bridge is
begin
p_executor : process
constant c_data_words_width : natural := hvvc_to_bridge.data_words(hvvc_to_bridge.data_words'low)'length;
variable v_byte_endianness : t_byte_endianness;
variable v_cmd_idx : integer;
variable v_gmii_received_data : bitvis_vip_gmii.vvc_cmd_pkg.t_vvc_result;
variable v_dut_data_width : positive;
variable v_num_transfers : integer;
variable v_num_data_bytes : positive;
variable v_data_bytes : t_byte_array(0 to GC_MAX_NUM_WORDS*c_data_words_width/8-1);
variable v_channel : t_channel := NA;
variable v_dut_if_field_pos_is_first : boolean;
variable v_dut_if_field_pos_is_last : boolean;
variable v_disabled_msg_id_int_wait : boolean;
variable v_disabled_msg_id_exe_wait : boolean;
--UVVM: temporary fix for HVVC, remove 2 lines below in v3.0
variable v_disabled_msg_id_int : boolean;
variable v_disabled_msg_id_exe : boolean;
-- Disables a previously enabled msg_id in the VVC's shared config
impure function disable_gmii_vvc_msg_id(
constant channel : t_channel;
constant instance_idx : integer;
constant msg_id : t_msg_id
) return boolean is
variable v_disable_id : boolean := false;
begin
if shared_gmii_vvc_config(channel, instance_idx).msg_id_panel(msg_id) = ENABLED then
shared_gmii_vvc_config(channel, instance_idx).msg_id_panel(msg_id) := DISABLED;
v_disable_id := true;
end if;
return v_disable_id;
end function;
begin
if GC_WORD_ENDIANNESS = LOWER_WORD_LEFT or GC_WORD_ENDIANNESS = LOWER_BYTE_LEFT then
v_byte_endianness := LOWER_BYTE_LEFT;
else
v_byte_endianness := LOWER_BYTE_RIGHT;
end if;
loop
-- Await cmd from the HVVC
wait until hvvc_to_bridge.trigger = true;
-- Check the field position in the packet
v_dut_if_field_pos_is_first := hvvc_to_bridge.dut_if_field_pos = FIRST or hvvc_to_bridge.dut_if_field_pos = FIRST_AND_LAST;
v_dut_if_field_pos_is_last := hvvc_to_bridge.dut_if_field_pos = LAST or hvvc_to_bridge.dut_if_field_pos = FIRST_AND_LAST;
if hvvc_to_bridge.operation = TRANSMIT then
v_channel := TX;
elsif hvvc_to_bridge.operation = RECEIVE then
v_channel := RX;
end if;
if v_dut_if_field_pos_is_first then
log(ID_NEW_HVVC_CMD_SEQ, "VVC is busy while executing an HVVC command", "GMII_VVC," & to_string(GC_INSTANCE_IDX), shared_gmii_vvc_config(v_channel, GC_INSTANCE_IDX).msg_id_panel);
-- Disable the interpreter and executor waiting logs during the HVVC command
v_disabled_msg_id_int_wait := disable_gmii_vvc_msg_id(v_channel, GC_INSTANCE_IDX, ID_CMD_INTERPRETER_WAIT);
v_disabled_msg_id_exe_wait := disable_gmii_vvc_msg_id(v_channel, GC_INSTANCE_IDX, ID_CMD_EXECUTOR_WAIT);
--UVVM: temporary fix for HVVC, remove 2 lines below in v3.0
v_disabled_msg_id_int := disable_gmii_vvc_msg_id(v_channel, GC_INSTANCE_IDX, ID_CMD_INTERPRETER);
v_disabled_msg_id_exe := disable_gmii_vvc_msg_id(v_channel, GC_INSTANCE_IDX, ID_CMD_EXECUTOR);
end if;
-- Get the next DUT data width from the config
get_data_width_config(GC_DUT_IF_FIELD_CONFIG, hvvc_to_bridge, v_dut_data_width);
-- Calculate number of transfers
v_num_transfers := (hvvc_to_bridge.num_data_words*c_data_words_width)/v_dut_data_width;
-- Extra transfer if data bits remainder
if ((hvvc_to_bridge.num_data_words*c_data_words_width) rem v_dut_data_width) /= 0 then
v_num_transfers := v_num_transfers+1;
end if;
-- Calculate number of bytes for this operation
v_num_data_bytes := hvvc_to_bridge.num_data_words*c_data_words_width/8;
-- Execute command
case hvvc_to_bridge.operation is
when TRANSMIT =>
--UVVM: temporary fix for HVVC, remove line below in v3.0
shared_gmii_vvc_config(TX, GC_INSTANCE_IDX).parent_msg_id_panel := hvvc_to_bridge.msg_id_panel;
-- Convert from t_slv_array to t_byte_array
v_data_bytes(0 to v_num_data_bytes-1) := convert_slv_array_to_byte_array(hvvc_to_bridge.data_words(0 to hvvc_to_bridge.num_data_words-1), v_byte_endianness);
gmii_write(GMII_VVCT, GC_INSTANCE_IDX, TX, v_data_bytes(0 to v_num_data_bytes-1), "HVVC: Write data via GMII.", GC_SCOPE, hvvc_to_bridge.msg_id_panel);
-- Enable the executor waiting log after receiving its last command
if v_disabled_msg_id_exe_wait and v_dut_if_field_pos_is_last then
shared_gmii_vvc_config(TX, GC_INSTANCE_IDX).msg_id_panel(ID_CMD_EXECUTOR_WAIT) := ENABLED;
end if;
v_cmd_idx := get_last_received_cmd_idx(GMII_VVCT, GC_INSTANCE_IDX, TX, GC_SCOPE);
await_completion(GMII_VVCT, GC_INSTANCE_IDX, TX, v_cmd_idx, (GC_MAX_NUM_WORDS+v_num_transfers)*GC_PHY_MAX_ACCESS_TIME, "HVVC: Wait for write to finish.", GC_SCOPE, hvvc_to_bridge.msg_id_panel);
when RECEIVE =>
--UVVM: temporary fix for HVVC, remove line below in v3.0
shared_gmii_vvc_config(RX, GC_INSTANCE_IDX).parent_msg_id_panel := hvvc_to_bridge.msg_id_panel;
gmii_read(GMII_VVCT, GC_INSTANCE_IDX, RX, v_num_data_bytes, "HVVC: Read data via GMII.", GC_SCOPE, hvvc_to_bridge.msg_id_panel);
-- Enable the executor waiting log after receiving its last command
if v_disabled_msg_id_exe_wait and v_dut_if_field_pos_is_last then
shared_gmii_vvc_config(RX, GC_INSTANCE_IDX).msg_id_panel(ID_CMD_EXECUTOR_WAIT) := ENABLED;
end if;
v_cmd_idx := get_last_received_cmd_idx(GMII_VVCT, GC_INSTANCE_IDX, RX, GC_SCOPE);
await_completion(GMII_VVCT, GC_INSTANCE_IDX, RX, v_cmd_idx, (GC_MAX_NUM_WORDS+v_num_transfers)*GC_PHY_MAX_ACCESS_TIME, "HVVC: Wait for read to finish.", GC_SCOPE, hvvc_to_bridge.msg_id_panel);
fetch_result(GMII_VVCT, GC_INSTANCE_IDX, RX, v_cmd_idx, v_gmii_received_data, "HVVC: Fetching received data.", TB_ERROR, GC_SCOPE, hvvc_to_bridge.msg_id_panel);
-- Convert from t_byte_array back to t_slv_array
bridge_to_hvvc.data_words(0 to hvvc_to_bridge.num_data_words-1) <= convert_byte_array_to_slv_array(v_gmii_received_data.data_array(0 to v_num_data_bytes-1), c_data_words_width/8, v_byte_endianness);
when others =>
alert(TB_ERROR, "Unsupported operation");
end case;
-- Enable the interpreter waiting log after receiving its last command
if v_disabled_msg_id_int_wait and v_dut_if_field_pos_is_last then
shared_gmii_vvc_config(v_channel, GC_INSTANCE_IDX).msg_id_panel(ID_CMD_INTERPRETER_WAIT) := ENABLED;
end if;
--UVVM: temporary fix for HVVC, remove 4 lines below in v3.0
if v_dut_if_field_pos_is_last then
shared_gmii_vvc_config(v_channel, GC_INSTANCE_IDX).msg_id_panel(ID_CMD_INTERPRETER) := ENABLED when v_disabled_msg_id_int;
shared_gmii_vvc_config(v_channel, GC_INSTANCE_IDX).msg_id_panel(ID_CMD_EXECUTOR) := ENABLED when v_disabled_msg_id_exe;
end if;
gen_pulse(bridge_to_hvvc.trigger, 0 ns, "Pulsing bridge_to_hvvc trigger", GC_SCOPE, ID_NEVER);
end loop;
end process;
end architecture GMII; |
-------------------------------------------------------------------------------
-- Demonstration using two SpW interfaces
---
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.hdlc_pkg.all;
use work.bus_pkg.all;
use work.reset_pkg.all;
use work.reset_gen_pkg.all;
use work.reg_file_pkg.all;
use work.fifo_sync_pkg.all;
use work.utils_pkg.all;
use work.uart_pkg.all;
use work.spw_node_pkg.all;
entity toplevel is
generic (RESET_IMPL : reset_type := sync);
port(
so : out std_logic_vector(1 downto 0);
do : out std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
di : in std_logic_vector(1 downto 0);
rsrx : in std_logic;
rstx : out std_logic;
led : out std_logic_vector(7 downto 0);
sw : in std_logic_vector(7 downto 0);
clk : in std_logic
);
end toplevel;
architecture Behavioral of toplevel is
signal reset : std_logic;
signal bus_to_master : busmaster_in_type := (data => (others => '0'));
signal master_to_bus : busmaster_out_type := (addr => (others => '0'), data => (others => '0'), re => '0', we => '0');
signal reg_to_master : busdevice_out_type := (data => (others => '0'));
signal spw0_to_master : busdevice_out_type := (data => (others => '0'));
signal spw1_to_master : busdevice_out_type := (data => (others => '0'));
signal reg_out : std_logic_vector(15 downto 0);
signal reg_in : std_logic_vector(15 downto 0);
begin
-----------------------------------------------------------------------------
-- Reset generator
-----------------------------------------------------------------------------
reset_gen_inst : entity work.reset_gen
port map (
reset => reset,
clk => clk);
-----------------------------------------------------------------------------
-- HDLC Busmaster with UART
-----------------------------------------------------------------------------
hdlc_busmaster_with_support : entity work.hdlc_busmaster_with_support
generic map (
DIV_RX => 40,
DIV_TX => 200,
RESET_IMPL => RESET_IMPL)
port map (
rx => rsrx,
tx => rstx,
bus_o => master_to_bus,
bus_i => bus_to_master,
reset => reset,
clk => clk);
-----------------------------------------------------------------------------
-- LOA Bus
-- here we collect the data-outputs of the devices
-----------------------------------------------------------------------------
bus_to_master.data <= reg_to_master.data or
spw0_to_master.data or
spw1_to_master.data;
-----------------------------------------------------------------------------
-- Input & output periphery register
-----------------------------------------------------------------------------
reg_inst : entity work.peripheral_register
generic map(
BASE_ADDRESS => 16#0000#,
RESET_IMPL => RESET_IMPL)
port map(
dout_p => reg_out,
din_p => reg_in,
bus_o => reg_to_master,
bus_i => master_to_bus,
reset => reset,
clk => clk);
-----------------------------------------------------------------------------
-- IOs interconnect to LEDs and Switches
-----------------------------------------------------------------------------
reg_in <= x"00" & sw;
led(7 downto 0) <= reg_out(7 downto 0);
-----------------------------------------------------------------------------
-- SPW 0 Interface
-----------------------------------------------------------------------------
spw_node_0 : entity work.spw_node
generic map (
BASE_ADDRESS => 16#0010#,
RESET_IMPL => RESET_IMPL)
port map (
do_p => do(0),
so_p => so(0),
di_p => di(0),
si_p => si(0),
bus_o => spw0_to_master,
bus_i => master_to_bus,
reset => reset,
clk => clk);
-----------------------------------------------------------------------------
-- SPW 1 Interface
-----------------------------------------------------------------------------
spw_node_1 : entity work.spw_node
generic map (
BASE_ADDRESS => 16#0020#,
RESET_IMPL => RESET_IMPL)
port map (
do_p => do(1),
so_p => so(1),
di_p => di(1),
si_p => si(1),
bus_o => spw1_to_master,
bus_i => master_to_bus,
reset => reset,
clk => clk);
end Behavioral;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 15-02-2016
-- Module Name: mux_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mux_t is
end entity mux_t;
architecture arch_mux_t of mux_t is
component mux is
port (sel : in std_logic_vector(1 downto 0);
i : in std_logic_vector(3 downto 0);
o : out std_logic);
end component mux;
signal i : std_logic_vector(3 downto 0);
signal sel : std_logic_vector(1 downto 0);
signal o : std_logic;
for all:mux use entity work.mux(beh_arch_mux);
begin
m : mux port map (sel, i, o);
i <= "1101";
sel <= "00", "10" after 100 ns;
end architecture arch_mux_t;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY dcfifo_32in_32out_8kb_cnt IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END dcfifo_32in_32out_8kb_cnt;
ARCHITECTURE dcfifo_32in_32out_8kb_cnt_arch OF dcfifo_32in_32out_8kb_cnt IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dcfifo_32in_32out_8kb_cnt_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dcfifo_32in_32out_8kb_cnt_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dcfifo_32in_32out_8kb_cnt_arch : ARCHITECTURE IS "dcfifo_32in_32out_8kb_cnt,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dcfifo_32in_32out_8kb_cnt_arch: ARCHITECTURE IS "dcfifo_32in_32out_8kb_cnt,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=8,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=1,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=253,C_PROG_FULL_THRESH_NEGATE_VAL=252,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=1,C_RD_DEPTH=256,C_RD_FREQ=1,C_RD_PNTR_WIDTH=8,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=8,C_WR_DEPTH=256,C_WR_FREQ=1,C_WR_PNTR_WIDTH=8,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 8,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 1,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 253,
C_PROG_FULL_THRESH_NEGATE_VAL => 252,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 1,
C_RD_DEPTH => 256,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 8,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 8,
C_WR_DEPTH => 256,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 8,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
rd_data_count => rd_data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END dcfifo_32in_32out_8kb_cnt_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY dcfifo_32in_32out_8kb_cnt IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END dcfifo_32in_32out_8kb_cnt;
ARCHITECTURE dcfifo_32in_32out_8kb_cnt_arch OF dcfifo_32in_32out_8kb_cnt IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dcfifo_32in_32out_8kb_cnt_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dcfifo_32in_32out_8kb_cnt_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dcfifo_32in_32out_8kb_cnt_arch : ARCHITECTURE IS "dcfifo_32in_32out_8kb_cnt,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dcfifo_32in_32out_8kb_cnt_arch: ARCHITECTURE IS "dcfifo_32in_32out_8kb_cnt,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=8,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=1,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=253,C_PROG_FULL_THRESH_NEGATE_VAL=252,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=1,C_RD_DEPTH=256,C_RD_FREQ=1,C_RD_PNTR_WIDTH=8,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=8,C_WR_DEPTH=256,C_WR_FREQ=1,C_WR_PNTR_WIDTH=8,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 8,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 1,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 253,
C_PROG_FULL_THRESH_NEGATE_VAL => 252,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 1,
C_RD_DEPTH => 256,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 8,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 8,
C_WR_DEPTH => 256,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 8,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
rd_data_count => rd_data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END dcfifo_32in_32out_8kb_cnt_arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNIYBMGPQQ is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "000000000000000000001111";
width : positive := 24);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNIYBMGPQQ is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 24,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNIYBMGPQQ is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "000000000000000000001111";
width : positive := 24);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNIYBMGPQQ is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 24,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNIYBMGPQQ is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "000000000000000000001111";
width : positive := 24);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNIYBMGPQQ is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 24,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNIYBMGPQQ is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "000000000000000000001111";
width : positive := 24);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNIYBMGPQQ is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 24,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lcdctl is
Port ( clk,reset : in STD_LOGIC;
vramaddr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ud : out STD_LOGIC;
rl : out STD_LOGIC;
enab : out STD_LOGIC;
vsync : out STD_LOGIC;
hsync : out STD_LOGIC;
ck : out STD_LOGIC;
r : out std_logic_vector(5 downto 0);
g : out std_logic_vector(5 downto 0);
b : out std_logic_vector(5 downto 0)
);
end lcdctl;
architecture Behavioral of lcdctl is
signal clk_fast : std_logic := '0';
signal ired : std_logic_vector(5 downto 0) := "000000";
signal igreen : std_logic_vector(5 downto 0) := "000000";
signal iblue : std_logic_vector(5 downto 0) := "000000";
signal fg_r : std_logic_vector(5 downto 0) := "000000";
signal fg_g : std_logic_vector(5 downto 0) := "000000";
signal fg_b : std_logic_vector(5 downto 0) := "000000";
signal bg_r : std_logic_vector(5 downto 0) := "000000";
signal bg_g : std_logic_vector(5 downto 0) := "000000";
signal bg_b : std_logic_vector(5 downto 0) := "000000";
signal lcdvsync : STD_LOGIC;
signal lcdhsync : STD_LOGIC;
signal char_addr: std_logic_vector(6 downto 0);
signal char_attr: std_logic_vector(7 downto 0) := x"42";
signal attr_not_char: std_logic := '1';
signal rom_addr: std_logic_vector(10 downto 0);
signal row_addr: std_logic_vector(3 downto 0);
signal bit_addr: std_logic_vector(2 downto 0);
signal font_word: std_logic_vector(7 downto 0);
signal font_bit: std_logic;
signal video_on: std_logic;
signal dout: std_logic_vector(7 downto 0) := "01100010";
signal addr_read: std_logic_vector(12 downto 0);
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal ipixel_x, ipixel_y: std_logic_vector(9 downto 0);
begin
ud <= '1';
rl <= '1';
enab <= '0';
ck <= clk_fast;
r <= ired;
g <= igreen;
b <= iblue;
hsync<=lcdhsync;
vsync<=lcdvsync;
sync0: entity work.vga_sync
port map(
clock=>clk_fast,
reset=>reset,
hsync=>lcdhsync, vsync=>lcdvsync,
video_on=>video_on,
pixel_tick=>open,
pixel_x=>pixel_x, pixel_y=>pixel_y
);
-- instantiate frame buffer
-- frame_buffer_unit: entity work.blk_mem_gen_v7_3
-- port map (
-- clka => clk,
-- wea => (others => '0'),
-- addra => (others => '0'),
-- dina => (others => '0'),
-- clkb => clk,
-- addrb => addr_read,
-- doutb => dout
-- );
vramaddr <= "111" & addr_read;
dout <= vramdata;
-- instantiate font ROM
font_unit: entity work.font_rom
port map(
clock => clk_fast,
addr => rom_addr,
data => font_word
);
-- tile RAM read
-- addr_read <= ((pixel_y(9 downto 4) & "000000") + ("00" & pixel_y(9 downto 4) & "0000") + ("00000" & pixel_x(9 downto 3))) & attr_not_char;
addr_read <= ((pixel_y(9 downto 4) * "000101") + ("00000" & pixel_x(9 downto 3))) & attr_not_char;
-- addr_read <= pixel_y(8 downto 4) & pixel_x(9 downto 3) & attr_not_char; -- ok but stride=256 instead of 80*2=160
process(clk,clk_fast,video_on)
begin
if rising_edge(clk) then
if video_on='0' then
attr_not_char <= '0';
clk_fast <= '0';
else
if clk_fast='0' then
char_attr <= dout(7 downto 0);
attr_not_char <= '1';
else
char_addr <= dout(6 downto 0);
attr_not_char <= '0';
end if;
end if;
clk_fast <= not clk_fast;
end if;
end process;
fg_r <= (others => '1') when char_attr(0)='1' else (others => '0');
fg_g <= (others => '1') when char_attr(1)='1' else (others => '0');
fg_b <= (others => '1') when char_attr(2)='1' else (others => '0');
bg_r <= (others => '1') when char_attr(3)='1' else (others => '0');
bg_g <= (others => '1') when char_attr(4)='1' else (others => '0');
bg_b <= (others => '1') when char_attr(5)='1' else (others => '0');
-- font ROM interface
row_addr <= pixel_y(3 downto 0);
rom_addr <= char_addr & row_addr;
-- bit_addr <= std_logic_vector(unsigned(pixel_x(2 downto 0)) - 1);
bit_addr <= std_logic_vector(unsigned(pixel_x(2 downto 0))-2);
font_bit <= font_word(to_integer(unsigned(not bit_addr)));
-- rgb multiplexing
process(font_bit,video_on,fg_r,fg_g,fg_b,bg_r,bg_g,bg_b)
begin
if video_on='0' then
ired <= (others => '0');
igreen <= (others => '0');
iblue <= (others => '0');
elsif font_bit = '1' then
ired <= fg_r;
igreen <= fg_g;
iblue <= fg_b;
-- ired <= (others => '1');
-- igreen <= (others => '1');
-- iblue <= (others => '1');
else
ired <= bg_r;
igreen <= bg_g;
iblue <= bg_b;
-- ired <= (others => '0');
-- igreen <= (others => '0');
-- iblue <= (others => '0');
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MODULOPRINCIPAL is
Port ( rst : in STD_LOGIC;
CLK : in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0));
end MODULOPRINCIPAL;
architecture Behavioral of MODULOPRINCIPAL is
COMPONENT PC
PORT(
rst : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
CLK : IN std_logic;
DataOut : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT Sumador32bits
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT InstructionMemory
PORT(
Address : IN std_logic_vector(5 downto 0);
rst : IN std_logic;
Instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT OMUXT
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm : IN std_logic_vector(31 downto 0);
i : IN std_logic;
oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
rd : IN std_logic_vector(5 downto 0);
DWR : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
WE : IN std_logic;
Crs1 : OUT std_logic_vector(31 downto 0);
Crs2 : OUT std_logic_vector(31 downto 0);
Crd : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT SEU
PORT(
imm13 : IN std_logic_vector(12 downto 0);
SEUimm : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
C : IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT CU
PORT(
OP : IN std_logic_vector(1 downto 0);
OP2 : IN std_logic_vector(2 downto 0);
Cond : IN std_logic_vector(3 downto 0);
icc : IN std_logic_vector(3 downto 0);
OP3 : IN std_logic_vector(5 downto 0);
WE : OUT std_logic;
RFDEST : OUT std_logic;
RFSOURCE : OUT std_logic_vector(1 downto 0);
WRENMEM : OUT std_logic;
--RDENMEM : OUT std_logic;
PCSOURCE : OUT std_logic_vector(1 downto 0);
ALUOP : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
COMPONENT PSRModifier
PORT(
ALUOP : IN std_logic_vector(5 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Oper1 : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
NZVC : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT PSR
PORT(
NZVC : IN std_logic_vector(3 downto 0);
nCWP : IN std_logic;
CLK : IN std_logic;
rst : IN std_logic;
icc : OUT std_logic_vector(3 downto 0);
CWP : OUT std_logic;
C : OUT std_logic
);
END COMPONENT;
COMPONENT WindowsManager
PORT(
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
op : IN std_logic_vector(1 downto 0);
op3 : IN std_logic_vector(5 downto 0);
CWP : IN std_logic;
nRs1 : OUT std_logic_vector(5 downto 0);
nRs2 : OUT std_logic_vector(5 downto 0);
nRd : OUT std_logic_vector(5 downto 0);
nCWP : OUT std_logic
);
END COMPONENT;
COMPONENT DataMemory
PORT(
Crd : IN std_logic_vector(31 downto 0);
Address : IN std_logic_vector(31 downto 0);
WRENMEM : IN std_logic;
--RDENMEM : IN std_logic;
DATATOMEM : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT MUX_PCSOURCE
PORT(
PCdisp30 : IN std_logic_vector(31 downto 0);
PCSEUdisp22 : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
PC : IN std_logic_vector(31 downto 0);
PCSOURCE : IN std_logic_vector(1 downto 0);
nPC : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT MUX_RFDEST
PORT(
RD : IN std_logic_vector(5 downto 0);
RFDEST : IN std_logic;
nRD : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
COMPONENT MUX_RFSOURCE
PORT(
RFSOURCE : IN std_logic_vector(1 downto 0);
DATATOMEM : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
PC : IN std_logic_vector(31 downto 0);
DATATOREG : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT SEUdisp22
PORT(
disp22 : IN std_logic_vector(21 downto 0);
SEUdisp22 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT SEUdisp30
PORT(
disp30 : IN std_logic_vector(29 downto 0);
SEUdisp30 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
signal B0:std_logic_vector(31 downto 0);--Result: conecta al sumador32bits con el PC(entrada) de MUXPCSOURCE
signal B1:std_logic_vector(31 downto 0);--DataOut(nPC): conecta al nPC con el DataIn de PC
signal B2:std_logic_vector(31 downto 0);--DataOut(PC): conecta al PC con el address del IM, con el Oper1 de sumador32bitsdisp22 y con el Oper2 de sumador32bitsdisp30
signal B3:std_logic_vector(31 downto 0);--Instruction: conecta al IM con el CU(OP(31-30),OP3(24-19),Cond(28-25)),WindowManager(rs1(18-14),rs2(4-0),rd(29-25)),
--SEU(12-0),OMUXT(13), SEUdisp22(21-0) y sumador32bitsdisp30(29-0)
signal B4:std_logic_vector(5 downto 0); --ALUOP: conecta a CU y a la ALU
signal B5:std_logic_vector(31 downto 0);--ALURESULT: conecta a la ALU con el Address del DataMemory, con el ALURESULT de MUXRFSOURCE y con el ALURESULT de MUXPCSOURCE, es la salida del Modulo Principal
signal B6:std_logic_vector(31 downto 0);--Crs1: conecta al RF con Oper1 de la ALU
signal B7:std_logic_vector(31 downto 0);--Crs2: conecta al RF con OMUXT
signal B8:std_logic_vector(31 downto 0);--SEUimm: conecta a SEU con OMUXT
signal B9:std_logic_vector(31 downto 0);--Oper2: conecta a OMUXT con el Oper2 de la ALU
signal B10: std_logic; --Carry: conecta al PSR y a la ALU
signal B11: std_logic_vector(3 downto 0);--NZVC: conecta al PSRModifier con el PSR
signal B12: std_logic_vector(17 downto 0);--InstructionWM: conecta al Windows Manager con el RegisterFile(rs1(17-12),rs2(11-6)) y MUXRFDEST(RD(5-0))
signal B13: std_logic;--CWP: conecta al PSR con el WindowsManager
signal B14: std_logic;--nCWP: conecta al WindowsManager con el PSR
signal B15: std_logic_vector(5 downto 0);--rd(nRD): conecta al MUXRFDEST con el rd del Register File
signal B16: std_logic_vector(31 downto 0);--SEUdisp22(entrada): conecta al SEUdisp22(Modulo) con el Oper2 de sumador32bitsdisp22
signal B17: std_logic_vector(31 downto 0);--Result: conecta al sumador32bitsdisp30 con el PCdisp30 de MUXPCSOURCE
signal B18: std_logic_vector(31 downto 0);--Result: conecta al sumador32bitsdisp22 con el PCSEUdisp22 del MUXPCSOURCE
signal B19: std_logic;--RFDEST: conecta a la UC con el RFDEST DE MUXRFDEST
signal B20: std_logic_vector(1 downto 0);--RFSOURCE: conecta a la UC con el RFSOURCE de MUXRFSOURCE
signal B21: std_logic;--WRENMEM conecta a la UC con el WRENMEM del DataMemory;
signal B22: std_logic_vector(31 downto 0);----SEUdisp30(entrada): conecta al SEUdisp30(Modulo) con el Oper2 de sumador32bitsdisp30
signal B23: std_logic;--WE: conecta a la UC con el WE del Register File
signal B24: std_logic_vector(31 downto 0);--Crd: conecta al Register File con el Crd del DataMemory
signal B25: std_logic_vector(31 downto 0);--DATATOMEM: conecta al DataMemory con el DATATOMEM del MUXRFSOURCE
signal B26: std_logic_vector(31 downto 0);--DATATOREG: conecta al MUXRFSOURCE con el DWR del Register File
signal B27: std_logic_vector(3 downto 0); --icc: Conecta al PSR con el icc de la UC
signal B28: std_logic_vector(1 downto 0);--PCSOURCE: conecta a la UC con el PCSOURCE DE MUXPCSOURCE
signal B29: std_logic_vector(31 downto 0);--nPC(Salida): Conecta al MUXPCSOURCE con el nPC(Modulo)
begin
Inst_PC: PC PORT MAP(
rst => rst,
dataIn => B1,
CLK => CLK,
DataOut => B2
);
Inst_Sumador32bitsdisp30: Sumador32bits PORT MAP(
Oper1 => B22,
Oper2 => B2,
Result => B17
);
Inst_Sumador32bitsdisp22: Sumador32bits PORT MAP(
Oper1 => B2,
Oper2 => B16,
Result => B18
);
Inst_Sumador32bits: Sumador32bits PORT MAP(
Oper1 => "00000000000000000000000000000001",
Oper2 => B1,
Result => B0
);
Inst_nPC: PC PORT MAP(
rst => rst,
CLK => CLK,
DataIn => B29,
DataOut => B1
);
Inst_InstructionMemory: InstructionMemory PORT MAP(
Address => B2(5 downto 0),
rst => rst,
Instruction =>B3
);
Inst_OMUXT: OMUXT PORT MAP(
Crs2 => B7,
SEUimm => B8,
i => B3(13),
oper2 => B9
);
Inst_RF: RF PORT MAP(
rs1 => B12(17 downto 12),
rs2 => B12(11 downto 6),
rd => B15,
DWR => B26,
rst => rst,
WE => B23,
Crs1 => B6,
Crs2 => B7,
Crd => B24
);
Inst_SEU: SEU PORT MAP(
imm13 => B3(12 downto 0),
SEUimm => B8
);
Inst_SEUdisp22: SEUdisp22 PORT MAP(
disp22 => B3(21 downto 0),
SEUdisp22 => B16
);
Inst_SEUdisp30: SEUdisp30 PORT MAP(
disp30 => B3(29 downto 0),
SEUdisp30 => B22
);
Inst_ALU: ALU PORT MAP(
Oper1 => B6,
Oper2 => B9,
ALUOP => B4,
C => B10,
ALURESULT => B5
);
Inst_CU: CU PORT MAP(
OP => B3(31 downto 30),
OP2 => B3(24 downto 22),
Cond => B3(28 downto 25),
icc => B27,
OP3 => B3(24 downto 19) ,
WE => B23,
RFDEST => B19,
RFSOURCE => B20,
WRENMEM => B21,
--RDENMEM => B22,
PCSOURCE => B28,
ALUOP => B4
);
Inst_PSRModifier: PSRModifier PORT MAP(
ALUOP => B4,
Oper2 => B9,
Oper1 => B6,
ALURESULT => B5,
NZVC => B11
);
Inst_PSR: PSR PORT MAP(
NZVC => B11,
nCWP => B14,
CLK => CLK,
rst => rst,
icc => B27,
CWP => B13,
C => B10
);
Inst_WindowsManager: WindowsManager PORT MAP(
rs1 => B3(18 downto 14),
rs2 => B3(4 downto 0),
rd => B3(29 downto 25),
op => B3(31 downto 30),
op3 =>B3(24 downto 19) ,
CWP => B13,
nRs1 => B12(17 downto 12),
nRs2 => B12(11 downto 6),
nRd => B12(5 downto 0),
nCWP => B14
);
Inst_DataMemory: DataMemory PORT MAP(
Crd => B24,
Address => B5,
WRENMEM => B21,
--RDENMEM => B22,
DATATOMEM => B25
);
Inst_MUX_PCSOURCE: MUX_PCSOURCE PORT MAP(
PCdisp30 => B17,
PCSEUdisp22 => B18,
ALURESULT => B5,
PC => B0,
PCSOURCE => B28,
nPC => B29
);
Inst_MUX_RFDEST: MUX_RFDEST PORT MAP(
RD => B12(5 downto 0),
RFDEST => B19,
nRD => B15
);
Inst_MUX_RFSOURCE: MUX_RFSOURCE PORT MAP(
RFSOURCE => B20,
DATATOMEM => B25,
ALURESULT => B5,
PC => B2,
DATATOREG => B26
);
ALURESULT<=B5;
end Behavioral;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: target
-- File: target.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: LEON target configuration package
------------------------------------------------------------------------------
-- 29.01.02 Configuration of DDM. LA
-- 13.03.02 MDCT added. APB masters incremented by 1 in AHB configuration, and
-- mdct address added in APB configuration.
library IEEE;
use IEEE.std_logic_1164.all;
package target is
type targettechs is (gen, virtex, atc35, atc25, fs90, umc18);
-- synthesis configuration
type syn_config_type is record
targettech : targettechs;
infer_ram : boolean; -- infer cache ram automatically
infer_regf : boolean; -- infer regfile automatically
infer_rom : boolean; -- infer boot prom automatically
infer_pads : boolean; -- infer pads automatically
infer_mult : boolean; -- infer multiplier automatically
gatedclk : boolean; -- select clocking strategy
rftype : integer; -- regfile implementation option
end record;
-- processor configuration
type multypes is (none, iterative, m32x8, m16x16, m32x16, m32x32);
type divtypes is (none, radix2);
type iu_config_type is record
nwindows : integer; -- # register windows (2 - 32)
multiplier : multypes; -- multiplier type
divider : divtypes; -- divider type
mac : boolean; -- multiply/accumulate
fpuen : integer range 0 to 1; -- FPU enable (integer due to synopsys limitations....sigh!)
cpen : boolean; -- co-processor enable
fastjump : boolean; -- enable fast jump address generation
icchold : boolean; -- enable fast branch logic
lddelay : integer range 1 to 2; -- # load delay cycles (1-2)
fastdecode : boolean; -- optimise instruction decoding (FPGA only)
watchpoints : integer range 0 to 4; -- # hardware watchpoints (0-4)
impl : integer range 0 to 15; -- IU implementation ID
version : integer range 0 to 15; -- IU version ID
end record;
-- FPU configuration
type fputype is (none, meiko, fpc); -- FPU type
type fpu_config_type is record
fpu : fputype; -- FPU type
fregs : integer; -- 32 for internal meiko, 0 for external FPC
version : integer range 0 to 7; -- FPU version ID
end record;
-- co-processor configuration
type cptype is (none, cpc); -- CP type
type cp_config_type is record
cp : cptype; -- Co-processor type
version : integer range 0 to 7; -- CP version ID
-- add your CP-specific configuration options here!!
end record;
-- cache configuration
type cache_config_type is record
icachesize : integer; -- size of I-cache in Kbytes
ilinesize : integer; -- # words per I-cache line
dcachesize : integer; -- size of D-cache in Kbytes
dlinesize : integer; -- # words per D-cache line
end record;
-- memory controller configuration
type mctrl_config_type is record
bus8en : boolean; -- enable 8-bit bus operation
bus16en : boolean; -- enable 16-bit bus operation
rawaddr : boolean; -- enable unlatched address option
end record;
type boottype is (memory, prom, dual);
type boot_config_type is record
boot : boottype; -- select boot source
ramrws : integer range 0 to 3; -- ram read waitstates
ramwws : integer range 0 to 3; -- ram write waitstates
sysclk : integer; -- cpu clock
baud : positive; -- UART baud rate
extbaud : boolean; -- use external baud rate setting
pabits : positive; -- internal boot-prom address bits
end record;
-- PCI configuration
type pcitype is (none, insilicon, esa, ahbtst); -- PCI core type
type pci_config_type is record
pcicore : pcitype; -- PCI core type
ahbmasters : integer; -- number of ahb master interfaces
ahbslaves : integer; -- number of ahb slave interfaces
arbiter : boolean; -- enable PCI arbiter
fixpri : boolean; -- use fixed arbitration priority
prilevels : integer; -- number of priority levels in arbiter
pcimasters : integer; -- number of PCI masters to be handled by arbiter
vendorid : integer; -- PCI vendor ID
deviceid : integer; -- PCI device ID
subsysid : integer; -- PCI subsystem ID
revisionid : integer; -- PCI revision ID
classcode : integer; -- PCI class code
pmepads : boolean; -- enable power down pads
p66pad : boolean; -- enable PCI66 pad
end record;
-- debug configuration
type debug_config_type is record
enable : boolean; -- enable debug port
uart : boolean; -- enable fast uart data to console
iureg : boolean; -- enable tracing of iu register writes
fpureg : boolean; -- enable tracing of fpu register writes
nohalt : boolean; -- dont halt on error
pclow : integer; -- set to 2 for synthesis, 0 for debug
end record;
-- AMBA configuration types
constant AHB_MST_MAX : integer := 5; -- maximum AHB masters
constant AHB_SLV_MAX : integer := 7; -- maximum AHB slaves
constant AHB_SLV_ADDR_MSB : integer := 4; -- MSB address bits to decode slaves
constant AHB_CACHE_MAX : integer := 4; -- maximum cacheability ranges
constant AHB_CACHE_ADDR_MSB : integer := 3; -- MSB address bits to decode cacheability
subtype ahb_range_addr_type is std_logic_vector(AHB_SLV_ADDR_MSB-1 downto 0);
subtype ahb_cache_addr_type is std_logic_vector(AHB_CACHE_ADDR_MSB-1 downto 0);
type ahb_slv_config_type is record
firstaddr : ahb_range_addr_type;
lastaddr : ahb_range_addr_type;
index : integer range 0 to AHB_SLV_MAX-1;
split : boolean;
enable : boolean;
end record;
type ahb_slv_config_vector is array (Natural Range <> ) of ahb_slv_config_type;
constant ahb_slv_config_void : ahb_slv_config_type :=
((others => '0'), (others => '0'), 0, false, false);
type ahb_cache_config_type is record
firstaddr : ahb_cache_addr_type;
lastaddr : ahb_cache_addr_type;
end record;
type ahb_cache_config_vector is array (Natural Range <> ) of ahb_cache_config_type;
constant ahb_cache_config_void : ahb_cache_config_type :=
((others => '0'), (others => '0'));
type ahb_config_type is record
masters : integer range 1 to AHB_MST_MAX;
defmst : integer range 0 to AHB_MST_MAX-1;
split : boolean; -- add support for SPLIT reponse
slvtable : ahb_slv_config_vector(0 to AHB_SLV_MAX-1);
cachetable : ahb_cache_config_vector(0 to AHB_CACHE_MAX-1);
end record;
constant APB_SLV_MAX : integer := 16; -- maximum APB slaves
constant APB_SLV_ADDR_BITS : integer := 10; -- address bits to decode APB slaves
subtype apb_range_addr_type is std_logic_vector(APB_SLV_ADDR_BITS-1 downto 0);
type apb_slv_config_type is record
firstaddr : apb_range_addr_type;
lastaddr : apb_range_addr_type;
index : integer;
enable : boolean;
end record;
type apb_slv_config_vector is array (Natural Range <> ) of apb_slv_config_type;
constant apb_slv_config_void : apb_slv_config_type :=
((others => '0'), (others => '0'), 0, false);
type apb_config_type is record
table : apb_slv_config_vector(0 to APB_SLV_MAX-1);
end record;
type irq_filter_type is (lvl0, lvl1, edge0, edge1);
type irq_filter_vec is array (0 to 31) of irq_filter_type;
type irq2type is record
enable : boolean; -- enable chained interrupt controller
channels : integer; -- number of additional interrupts (1 - 32)
filter : irq_filter_vec; -- irq filter definitions
end record;
type peri_config_type is record
cfgreg : boolean; -- enable LEON configuration register
ahbstat : boolean; -- enable AHB status register
wprot : boolean; -- enable RAM write-protection unit
wdog : boolean; -- enable watchdog
irq2cfg : irq2type; -- chained interrupt controller config
end record;
-- complete configuration record type
type config_type is record
synthesis : syn_config_type;
iu : iu_config_type;
fpu : fpu_config_type;
cp : cp_config_type;
cache : cache_config_type;
ahb : ahb_config_type;
apb : apb_config_type;
mctrl : mctrl_config_type;
boot : boot_config_type;
debug : debug_config_type;
pci : pci_config_type;
peri : peri_config_type;
end record;
----------------------------------------------------------------------------
-- Synthesis configurations
----------------------------------------------------------------------------
constant syn_atc25 : syn_config_type := (
targettech => atc25, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_atc35 : syn_config_type := (
targettech => atc35, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_gen : syn_config_type := (
targettech => gen, infer_pads => true,
infer_ram => true, infer_regf => true, infer_rom => true,
infer_mult => true, gatedclk => false, rftype => 1);
constant syn_virtex : syn_config_type := (
targettech => virtex, infer_pads => true,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => true, gatedclk => false, rftype => 1);
constant syn_virtex_blockprom : syn_config_type := (
targettech => virtex, infer_pads => true,
infer_ram => false, infer_regf => false, infer_rom => false,
infer_mult => true, gatedclk => false, rftype => 1);
constant syn_systel_asic : syn_config_type := (
targettech => atc25, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_fs90 : syn_config_type := (
targettech => fs90, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_umc18 : syn_config_type := (
targettech => umc18, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
-- infer_multgates => false,
infer_mult => false, gatedclk => false, rftype => 1);
----------------------------------------------------------------------------
-- IU configurations
----------------------------------------------------------------------------
constant iu_std : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 0, impl => 0, version => 0);
constant iu_std_mac : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 0, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 0, impl => 0, version => 0);
constant iu_fpu : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 1, cpen => false, fastjump => false, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga : iu_config_type := (
nwindows => 8, multiplier => none, divider => none, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8 : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8_fpu : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 1, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8_mac : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8_small : iu_config_type := (
nwindows => 8, multiplier => iterative, divider => radix2, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_atc25 : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 0, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 2, impl => 0, version => 0);
constant iu_atc25_fpu : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 1, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 2, impl => 0, version => 0);
----------------------------------------------------------------------------
-- FPU configurations
----------------------------------------------------------------------------
constant fpu_none : fpu_config_type := (fpu => none, fregs => 0, version => 0);
constant fpu_meiko: fpu_config_type := (fpu => meiko, fregs => 32, version => 0);
constant fpu_fpc : fpu_config_type := (fpu => fpc, fregs => 0, version => 0);
----------------------------------------------------------------------------
-- CP configurations
----------------------------------------------------------------------------
constant cp_none : cp_config_type := (cp => none, version => 0);
constant cp_cpc : cp_config_type := (cp => cpc, version => 0);
----------------------------------------------------------------------------
-- cache configurations
----------------------------------------------------------------------------
constant cache_1k1k : cache_config_type := (
icachesize => 1, ilinesize => 4, dcachesize => 1, dlinesize => 4);
constant cache_2k1k : cache_config_type := (
icachesize => 2, ilinesize => 4, dcachesize => 1, dlinesize => 4);
constant cache_2k2k : cache_config_type := (
icachesize => 2, ilinesize => 4, dcachesize => 2, dlinesize => 4);
constant cache_2kl8_2kl4 : cache_config_type := (
icachesize => 2, ilinesize => 8, dcachesize => 2, dlinesize => 4);
constant cache_4k2k : cache_config_type := (
icachesize => 4, ilinesize => 8, dcachesize => 2, dlinesize => 4);
constant cache_1k4k : cache_config_type := (
icachesize => 1, ilinesize => 4, dcachesize => 4, dlinesize => 4);
constant cache_4k4k : cache_config_type := (
icachesize => 4, ilinesize => 4, dcachesize => 4, dlinesize => 4);
constant cache_8k8k : cache_config_type := (
icachesize => 8, ilinesize => 8, dcachesize => 8, dlinesize => 4);
----------------------------------------------------------------------------
-- Memory controller configurations
----------------------------------------------------------------------------
constant mctrl_std : mctrl_config_type := (
bus8en => true, bus16en => true, rawaddr => false);
constant mctrl_mem32 : mctrl_config_type := (
bus8en => false, bus16en => false, rawaddr => false);
constant mctrl_mem16 : mctrl_config_type := (
bus8en => false, bus16en => true, rawaddr => false);
----------------------------------------------------------------------------
-- boot configurations
----------------------------------------------------------------------------
constant boot_mem_25M : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 24576000, baud => 38400, extbaud => false,
pabits => 8); -- 21.02.02 Booting system with 25 MHZ LA
constant boot_mem_33M : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 33333333, baud => 38400, extbaud => false,
pabits => 8); -- 15.02.02 Booting system with 33.3 MHZ LA
constant boot_mem : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 1000000, baud => 19200, extbaud => false,
pabits => 8);
constant boot_pmon : boot_config_type := (boot => prom, ramrws => 0,
ramwws => 0, sysclk => 24576000, baud => 38400, extbaud=> false,
pabits => 8);
constant boot_rdbmon : boot_config_type := (boot => prom, ramrws => 0,
ramwws => 0, sysclk => 24576000, baud => 38400, extbaud=> false,
pabits => 11);
constant boot_prom_xess16 : boot_config_type := (boot => prom, ramrws => 0,
ramwws => 0, sysclk => 25000000, baud => 38400, extbaud=> false,
pabits => 8);
----------------------------------------------------------------------------
-- PCI configurations
----------------------------------------------------------------------------
-- NOTE: 0x16E3 is ESA vendor ID - do NOT use without authorisation!!
-- NOTE: 0x1438 is ATMEL vendor ID - do NOT use without authorisation!!
constant pci_none : pci_config_type := (
pcicore => none, ahbmasters => 0, ahbslaves => 0,
arbiter => false, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_test : pci_config_type := (
pcicore => ahbtst, ahbmasters => 2, ahbslaves => 1,
arbiter => false, fixpri => true, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_insilicon : pci_config_type := (
pcicore => insilicon, ahbmasters => 2, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_esaif : pci_config_type := (
pcicore => esa, ahbmasters => 1, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_ahb_test : pci_config_type := (
pcicore => ahbtst, ahbmasters => 0, ahbslaves => 1,
arbiter => false, fixpri => true, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_atc25 : pci_config_type := (
pcicore => ahbtst, ahbmasters => 2, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
-- In-Silicon PCI core in ATMEL configuration
constant pci_atmel : pci_config_type := (
pcicore => insilicon, ahbmasters => 2, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#1438#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
----------------------------------------------------------------------------
-- Peripherals configurations
----------------------------------------------------------------------------
constant irq2none : irq2type := ( enable => false, channels => 32,
filter => (others => lvl0));
constant irq2chan4 : irq2type := ( enable => true, channels => 4,
filter => (lvl0, lvl1, edge0, edge1, others => lvl0));
constant peri_std : peri_config_type := (
cfgreg => true, ahbstat => true, wprot => true, wdog => true,
irq2cfg => irq2none);
constant peri_fpga : peri_config_type := (
cfgreg => true, ahbstat => false, wprot => false, wdog => false,
irq2cfg => irq2none);
constant peri_irq2 : peri_config_type := (
cfgreg => true, ahbstat => false, wprot => false, wdog => false,
irq2cfg => irq2chan4);
----------------------------------------------------------------------------
-- Debug configurations
----------------------------------------------------------------------------
constant debug_none : debug_config_type := ( enable => false, uart => false,
iureg => false, fpureg => false, nohalt => false, pclow => 2);
constant debug_disas : debug_config_type := ( enable => true, uart => false,
iureg => false, fpureg => false, nohalt => false, pclow => 2);
constant debug_msp : debug_config_type := ( enable => true, uart => false,
iureg => false, fpureg => false, nohalt => true, pclow => 2);
constant debug_uart : debug_config_type := ( enable => true, uart => true,
iureg => false, fpureg => false, nohalt => false, pclow => 0);
constant debug_fpu : debug_config_type := ( enable => true, uart => true,
iureg => false, fpureg => true, nohalt => false, pclow => 2);
constant debug_all : debug_config_type := ( enable => true, uart => true,
iureg => true, fpureg => true, nohalt => false, pclow => 0);
----------------------------------------------------------------------------
-- Amba AHB configurations
----------------------------------------------------------------------------
-- standard slave config
constant ahbslvcfg_std : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 256 MB 0x8- 0x8
others => ahb_slv_config_void);
-- AHB test slave config
constant ahbslvcfg_test : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 128 MB 0x8- 0x8
("1010", "1010", 2, true, true), -- AHB test module 0xA- 0xA
("1100", "1111", 3, false, true), -- PCI initiator 0xC- 0xF
others => ahb_slv_config_void);
-- PCI slave config
constant ahbslvcfg_pci : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 128 MB 0x8- 0x8
("1010", "1111", 2, false, true), -- PCI initiator 0xA- 0xF
others => ahb_slv_config_void);
-- standard cacheability config
constant ahbcachecfg_std : ahb_cache_config_vector(0 to AHB_CACHE_MAX-1) := (
-- first last function HADDR[31:29]
("000", "000"), -- PROM area 0x0- 0x0
("010", "011"), -- RAM area 0x2- 0x3
others => ahb_cache_config_void);
-- standard config record
constant ahb_std : ahb_config_type := (
masters => 3, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_std, cachetable => ahbcachecfg_std);
-- FPGA config record
constant ahb_fpga : ahb_config_type := (
masters => 3, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_std, cachetable => ahbcachecfg_std);
-- Phoenix PCI core config record (uses two AHB master instefaces)
constant ahb_insilicon_pci : ahb_config_type := (
masters => 5, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_pci, cachetable => ahbcachecfg_std);
-- ESTEC PCI core config record (uses one AHB master insteface)
constant ahb_esa_pci : ahb_config_type := (
masters => 4, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_pci, cachetable => ahbcachecfg_std);
-- AHB test config
constant ahb_test : ahb_config_type := (
masters => 5, defmst => 0, split => true, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_test, cachetable => ahbcachecfg_std);
----------------------------------------------------------------------------
-- Amba APB configurations
----------------------------------------------------------------------------
-- standard config
constant apbslvcfg_std : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "0000000000", "0000001000", 0, true), -- memory controller, 0x00 - 0x08
( "0000001100", "0000010000", 1, true), -- AHB status reg., 0x0C - 0x10
( "0000010100", "0000011000", 2, true), -- cache controller, 0x14 - 0x18
( "0000011100", "0000100000", 3, true), -- write protection, 0x1C - 0x20
( "0000100100", "0000100100", 4, true), -- config register, 0x24 - 0x24
( "0001000000", "0001101100", 5, true), -- timers, 0x40 - 0x6C
( "0001110000", "0001111100", 6, true), -- uart1, 0x70 - 0x7C
( "0010000000", "0010001100", 7, true), -- uart2, 0x80 - 0x8C
( "0010010000", "0010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "0010100000", "0010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "0100000000", "0111111100", 10, false), -- PCI configuration 0x100 - 0x1FC
( "1000000000", "1000011000", 11, true), -- ddm 0x200 - 0x218
( "1100000000", "1100011000", 12, true), -- mdct 0x300 - 0x318
others => apb_slv_config_void);
-- standard config with secondary interrupt controller
constant apbslvcfg_irq2 : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "0000000000", "0000001000", 0, true), -- memory controller, 0x00 - 0x08
( "0000001100", "0000010000", 1, true), -- AHB status reg., 0x0C - 0x10
( "0000010100", "0000011000", 2, true), -- cache controller, 0x14 - 0x18
( "0000011100", "0000100000", 3, true), -- write protection, 0x1C - 0x20
( "0000100100", "0000100100", 4, true), -- config register, 0x24 - 0x24
( "0001000000", "0001101100", 5, true), -- timers, 0x40 - 0x6C
( "0001110000", "0001111100", 6, true), -- uart1, 0x70 - 0x7C
( "0010000000", "0010001100", 7, true), -- uart2, 0x80 - 0x8C
( "0010010000", "0010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "0010100000", "0010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "0010110000", "0010111100", 10, true), -- 2nd interrupt ctrl 0xB0 - 0xBC
( "1000000000", "1000011000", 11, true), -- ddm 0x200 - 0x218
( "1100000000", "1100011000", 12, true), -- mdct 0x300 - 0x318
others => apb_slv_config_void);
-- PCI config
constant apbslvcfg_pci : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "0000000000", "0000001000", 0, true), -- memory controller, 0x00 - 0x08
( "0000001100", "0000010000", 1, true), -- AHB status reg., 0x0C - 0x10
( "0000010100", "0000011000", 2, true), -- cache controller, 0x14 - 0x18
( "0000011100", "0000100000", 3, true), -- write protection, 0x1C - 0x20
( "0000100100", "0000100100", 4, true), -- config register, 0x24 - 0x24
( "0001000000", "0001101100", 5, true), -- timers, 0x40 - 0x6C
( "0001110000", "0001111100", 6, true), -- uart1, 0x70 - 0x7C
( "0010000000", "0010001100", 7, true), -- uart2, 0x80 - 0x8C
( "0010010000", "0010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "0010100000", "0010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "0100000000", "0111111100", 10, true), -- PCI configuration 0x100- 0x1FC
( "1000000000", "1011111100", 11, true), -- PCI arbiter 0x200- 0x2FC
others => apb_slv_config_void);
constant apb_std : apb_config_type := (table => apbslvcfg_std);
constant apb_irq2 : apb_config_type := (table => apbslvcfg_irq2);
constant apb_pci : apb_config_type := (table => apbslvcfg_pci);
----------------------------------------------------------------------------
-- Pre-defined LEON configurations
----------------------------------------------------------------------------
-- VIRTEX, 2 + 2 Kbyte cache, fpu
constant virtex_2k2k_25M_fpu : config_type := (
synthesis => syn_virtex, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_25M, debug => debug_all, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 4 + 4 Kbyte cache, mul/div, fpu, 25M
constant fpga_4k4k_v8_fpu_33M : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_4k4k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_33M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache 25 MHz
constant fpga_2k2k_25M : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_25M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache 25 MHz
constant fpga_2k2k_fpu_bprom_25M : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_meiko, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache 33.3 MHz
constant fpga_2k2k_33M : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_33M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache
constant fpga_2k2k : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_uart, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, mul/div
constant fpga_2k2k_v8 : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, secondary irq controller (test only)
constant fpga_2k2k_irq2 : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_irq2, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_irq2);
-- Any FPGA, 2 + 2 Kbyte cache, inferred boot-prom
constant fpga_2k2k_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, inferred boot-prom, mul/div
constant fpga_2k2k_v8_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 4 + 4 Kbyte cache, mul/div, fpu
constant fpga_4k4k_v8_fpu : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_4k4k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_25M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 4 + 4 Kbyte cache, inferred boot-prom, mul/div, fpu
constant fpga_4k4k_v8_fpu_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_4k4k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, inferred boot-prom, mul/div, MAC
constant fpga_2k2k_v8_mac_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_mac, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- VIRTEX, 2 + 2 Kbyte cache, hard boot-prom
constant virtex_2k2k_blockprom : config_type := (
synthesis => syn_virtex_blockprom, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- VIRTEX, 2 + 1 Kbyte cache, hard boot-prom with rdbmon
constant virtex_2k1k_rdbmon : config_type := (
synthesis => syn_virtex_blockprom, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k1k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_rdbmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- VIRTEX, 2 + 2 Kbyte cache, hard boot-prom, mul/div
constant virtex_2k2k_v8_fpu_blockprom : config_type := (
synthesis => syn_virtex_blockprom, iu => iu_fpga_v8, fpu => fpu_meiko, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- synthesis targetting ATC25 asic lib
constant gen_atc25 : config_type := (
synthesis => syn_atc25, iu => iu_atc25, fpu => fpu_none, cp => cp_none,
cache => cache_8k8k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting ATC25 asic lib, serial Meiko FPU
constant gen_atc25_meiko : config_type := (
synthesis => syn_atc25, iu => iu_atc25_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_8k8k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting ATC25 asic lib, parallel FPU
constant gen_atc25_fpc : config_type := (
synthesis => syn_atc25, iu => iu_atc25_fpu, fpu => fpu_fpc, cp => cp_none,
cache => cache_8k8k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting ATC25 asic lib + Insilicon PCI core
constant gen_atc25_insilicon_pci : config_type := (
synthesis => syn_atc25, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_4k4k, ahb => ahb_insilicon_pci, apb => apb_pci,
mctrl => mctrl_std, boot => boot_mem, debug => debug_disas, pci => pci_atmel,
peri => peri_std);
-- simulatiom with Insilicon PCI core
constant gen_insilicon_pci : config_type := (
synthesis => syn_gen, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_insilicon_pci, apb => apb_pci,
mctrl => mctrl_std, boot => boot_mem, debug => debug_disas, pci => pci_atmel,
peri => peri_std);
-- synthesis targetting ATC35 asic lib, synopsys
constant gen_atc35 : config_type := (
synthesis => syn_atc35, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_4k4k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- Systel FPGA configuration
constant systel_fpga : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_1k1k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- Systel ASIC configuration
constant systel_asic : config_type := (
synthesis => syn_systel_asic, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_1k1k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting UMC FS90A/B asic lib
constant gen_fs90 : config_type := (
synthesis => syn_fs90, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting UMC18 asic lib, synopsys + AMBIT
constant gen_umc18 : config_type := (
synthesis => syn_umc18, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_4k4k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
end;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutexattr_destroy_2.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutexattr_t * mutexattr = (hthread_mutexattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutexattr_init( mutexattr );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutexattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEXATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = hthread_mutexattr_destroy( mutexattr );
when STATE_4 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_mutexattr_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEXATTR_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
when STATE_6 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
library IEEE;
use IEEE.std_logic_1164.all;
package pkg3 is
component com5 is
--
end component com5;
end package pkg3;
|
package pkg_6502_opcodes is
type t_opcode_array is array(0 to 255) of string(1 to 13);
constant opcode_array : t_opcode_array := (
"BRK ", "ORA ($nn,X) ", "HLT* ", "ASO*($nn,X) ",
"BOT*$nn ", "ORA $nn ", "ASL $nn ", "ASO*$nn ",
"PHP ", "ORA # ", "ASL A ", "ORA*# ",
"BOT*$nnnnn ", "ORA $nnnn ", "ASL $nnnn ", "ASO*$nnnn ",
"BPL rel ", "ORA ($nn),Y ", "HLT* ", "ASO*($nn),Y ",
"BOT*$nn,X ", "ORA $nn,X ", "ASL $nn,X ", "ASO*$nn,X ",
"CLC ", "ORA $nnnn,Y ", "NOP* ", "ASO*$nnnn,Y ",
"BOT*$nnnn,X ", "ORA $nnnn,X ", "ASL $nnnn,X ", "ASO*$nnnn,X ",
"JSR $nnnn ", "AND ($nn,X) ", "HLT* ", "RLA*($nn,X) ",
"BIT $nn ", "AND $nn ", "ROL $nn ", "RLA*$nn ",
"PLP ", "AND # ", "ROL A ", "AND*# ",
"BIT $nnnn ", "AND $nnnn ", "ROL $nnnn ", "RLA*$nnnn ",
"BMI rel ", "AND ($nn),Y ", "HLT* ", "RLA*($nn),Y ",
"BIT*$nn,X ", "AND $nn,X ", "ROL $nn,X ", "RLA*$nn,X ",
"SEC ", "AND $nnnn,Y ", "NOP* ", "RLA*$nnnn,Y ",
"BIT*$nnnn,X ", "AND $nnnn,X ", "ROL $nnnn,X ", "RLA*$nnnn,X ",
"RTI ", "EOR ($nn,X) ", "HLT* ", "LSE*($nn,X) ",
"RDM* ", "EOR $nn ", "LSR $nn ", "LSE*$nn ",
"PHA ", "EOR # ", "LSR A ", "EOR*# ",
"JMP $nnnn ", "EOR $nnnn ", "LSR $nnnn ", "LSE*$nnnn ",
"BVC rel ", "EOR ($nn),Y ", "HLT* ", "LSE*($nn),Y ",
"RDM* ", "EOR $nn,X ", "LSR $nn,X ", "LSE*$nn,X ",
"CLI ", "EOR $nnnn,Y ", "NOP* ", "LSE*$nnnn,Y ",
"JMP*$nnnn ", "EOR $nnnn,X ", "LSR $nnnn,X ", "LSE*$nnnn,X ",
"RTS ", "ADC ($nn,X) ", "HLT* ", "RRA*($nn,X) ",
"RDM* ", "ADC $nn ", "ROR $nn ", "RRA*$nn ",
"PLA ", "ADC # ", "ROR A ", "ADC*# ",
"JMP ($nnnn) ", "ADC $nnnn ", "ROR $nnnn ", "RRA*$nnnn ",
"BVS rel ", "ADC ($nn),Y ", "HLT* ", "RRA*($nn),Y ",
"RDM* ", "ADC $nn,X ", "ROR $nn,X ", "RRA*$nn,X ",
"SEI ", "ADC $nnnn,Y ", "NOP* ", "RRA*$nnnn,Y ",
"JMP*($nnnn,X)", "ADC $nnnn,X ", "ROR $nnnn,X ", "RRA*$nnnn,X ",
"SKB* ", "STA ($nn,X) ", "SKB* ", "AXS*($nn,X) ",
"STY $nn ", "STA $nn ", "STX $nn ", "AXS*$nn ",
"DEY ", "SKB* ", "TXA ", "???* ",
"STY $nnnn ", "STA $nnnn ", "STX $nnnn ", "AXS*$nnnn ",
"BCC ", "STA ($nn),Y ", "HLT* ", "AXS*($nn),Y ",
"STY $nn,X ", "STA $nn,X ", "STX $nn,Y ", "AXS*$nn,Y ",
"TYA ", "STA $nnnn,Y ", "TXS ", "AXS*$nnnn,Y ",
"STY*$nnnn,X ", "STA $nnnn,X ", "STX*$nnnn,Y ", "AXS*$nnnn,Y ",
"LDY # ", "LDA ($nn,X) ", "LDX # ", "LAX*($nn,X) ",
"LDY $nn ", "LDA $nn ", "LDX $nn ", "LAX*$nn ",
"TAY ", "LDA # ", "TAX ", "LAX*# ",
"LDY $nnnn ", "LDA $nnnn ", "LDX $nnnn ", "LAX*$nnnn ",
"BCS ", "LDA ($nn),Y ", "HLT* ", "LAX*($nn),Y ",
"LDY $nn,X ", "LDA $nn,X ", "LDX $nn,Y ", "LAX*$nn,Y ",
"CLV ", "LDA $nnnn,Y ", "TSX ", "LAX*$nnnn,Y ",
"LDY $nnnn,X ", "LDA $nnnn,X ", "LDX $nnnn,Y ", "LAX*$nnnn,Y ",
"CPY # ", "CMP ($nn,X) ", "SKB* ", "DCM*($nn,X) ",
"CPY $nn ", "CMP $nn ", "DEC $nn ", "DCM*$nn ",
"INY ", "CMP # ", "DEX ", "SAX*# (used!)",
"CPY $nnnn ", "CMP $nnnn ", "DEC $nnnn ", "DCM*$nnnn ",
"BNE ", "CMP ($nn),Y ", "HLT* ", "DCM*($nn),Y ",
"RDM* ", "CMP $nn,X ", "DEC $nn,X ", "DCM*$nn,X ",
"CLD ", "CMP $nnnn,Y ", "NOP* ", "DCM*$nnnn,Y ",
"RDM*$nnnn,X ", "CMP $nnnn,X ", "DEC $nnnn,X ", "DCM*$nnnn,X ",
"CPX # ", "SBC ($nn,X) ", "SKB* ", "INS*($nn,X) ",
"CPX $nn ", "SBC $nn ", "INC $nn ", "INS*$nn ",
"INX ", "SBC # ", "NOP ", "SBC*# ",
"CPX $nnnn ", "SBC $nnnn ", "INC $nnnn ", "INS*$nnnn ",
"BEQ ", "SBC ($nn),Y ", "HLT* ", "INS*($nn),Y ",
"RDM* ", "SBC $nn,X ", "INC $nn,X ", "INS*$nn,X ",
"SED ", "SBC $nnnn,Y ", "NOP* ", "INS*$nnnn,Y ",
"RDM*$nnnn,X ", "SBC $nnnn,X ", "INC $nnnn,X ", "INS*$nnnn,X " );
type t_oper_array is array(0 to 7) of string(1 to 4);
constant c_shift_oper_array : t_oper_array := (
"ASL ", "ROL ", "LSR ", "ROR ", "NOP ", "TST ", "DEC ", "INC " );
constant c_alu_oper_array : t_oper_array := (
"OR ", "AND ", "XOR ", "ADD ", "NOP ", "TST ", "CMP ", "SUB " );
end;
|
package pkg_6502_opcodes is
type t_opcode_array is array(0 to 255) of string(1 to 13);
constant opcode_array : t_opcode_array := (
"BRK ", "ORA ($nn,X) ", "HLT* ", "ASO*($nn,X) ",
"BOT*$nn ", "ORA $nn ", "ASL $nn ", "ASO*$nn ",
"PHP ", "ORA # ", "ASL A ", "ORA*# ",
"BOT*$nnnnn ", "ORA $nnnn ", "ASL $nnnn ", "ASO*$nnnn ",
"BPL rel ", "ORA ($nn),Y ", "HLT* ", "ASO*($nn),Y ",
"BOT*$nn,X ", "ORA $nn,X ", "ASL $nn,X ", "ASO*$nn,X ",
"CLC ", "ORA $nnnn,Y ", "NOP* ", "ASO*$nnnn,Y ",
"BOT*$nnnn,X ", "ORA $nnnn,X ", "ASL $nnnn,X ", "ASO*$nnnn,X ",
"JSR $nnnn ", "AND ($nn,X) ", "HLT* ", "RLA*($nn,X) ",
"BIT $nn ", "AND $nn ", "ROL $nn ", "RLA*$nn ",
"PLP ", "AND # ", "ROL A ", "AND*# ",
"BIT $nnnn ", "AND $nnnn ", "ROL $nnnn ", "RLA*$nnnn ",
"BMI rel ", "AND ($nn),Y ", "HLT* ", "RLA*($nn),Y ",
"BIT*$nn,X ", "AND $nn,X ", "ROL $nn,X ", "RLA*$nn,X ",
"SEC ", "AND $nnnn,Y ", "NOP* ", "RLA*$nnnn,Y ",
"BIT*$nnnn,X ", "AND $nnnn,X ", "ROL $nnnn,X ", "RLA*$nnnn,X ",
"RTI ", "EOR ($nn,X) ", "HLT* ", "LSE*($nn,X) ",
"RDM* ", "EOR $nn ", "LSR $nn ", "LSE*$nn ",
"PHA ", "EOR # ", "LSR A ", "EOR*# ",
"JMP $nnnn ", "EOR $nnnn ", "LSR $nnnn ", "LSE*$nnnn ",
"BVC rel ", "EOR ($nn),Y ", "HLT* ", "LSE*($nn),Y ",
"RDM* ", "EOR $nn,X ", "LSR $nn,X ", "LSE*$nn,X ",
"CLI ", "EOR $nnnn,Y ", "NOP* ", "LSE*$nnnn,Y ",
"JMP*$nnnn ", "EOR $nnnn,X ", "LSR $nnnn,X ", "LSE*$nnnn,X ",
"RTS ", "ADC ($nn,X) ", "HLT* ", "RRA*($nn,X) ",
"RDM* ", "ADC $nn ", "ROR $nn ", "RRA*$nn ",
"PLA ", "ADC # ", "ROR A ", "ADC*# ",
"JMP ($nnnn) ", "ADC $nnnn ", "ROR $nnnn ", "RRA*$nnnn ",
"BVS rel ", "ADC ($nn),Y ", "HLT* ", "RRA*($nn),Y ",
"RDM* ", "ADC $nn,X ", "ROR $nn,X ", "RRA*$nn,X ",
"SEI ", "ADC $nnnn,Y ", "NOP* ", "RRA*$nnnn,Y ",
"JMP*($nnnn,X)", "ADC $nnnn,X ", "ROR $nnnn,X ", "RRA*$nnnn,X ",
"SKB* ", "STA ($nn,X) ", "SKB* ", "AXS*($nn,X) ",
"STY $nn ", "STA $nn ", "STX $nn ", "AXS*$nn ",
"DEY ", "SKB* ", "TXA ", "???* ",
"STY $nnnn ", "STA $nnnn ", "STX $nnnn ", "AXS*$nnnn ",
"BCC ", "STA ($nn),Y ", "HLT* ", "AXS*($nn),Y ",
"STY $nn,X ", "STA $nn,X ", "STX $nn,Y ", "AXS*$nn,Y ",
"TYA ", "STA $nnnn,Y ", "TXS ", "AXS*$nnnn,Y ",
"STY*$nnnn,X ", "STA $nnnn,X ", "STX*$nnnn,Y ", "AXS*$nnnn,Y ",
"LDY # ", "LDA ($nn,X) ", "LDX # ", "LAX*($nn,X) ",
"LDY $nn ", "LDA $nn ", "LDX $nn ", "LAX*$nn ",
"TAY ", "LDA # ", "TAX ", "LAX*# ",
"LDY $nnnn ", "LDA $nnnn ", "LDX $nnnn ", "LAX*$nnnn ",
"BCS ", "LDA ($nn),Y ", "HLT* ", "LAX*($nn),Y ",
"LDY $nn,X ", "LDA $nn,X ", "LDX $nn,Y ", "LAX*$nn,Y ",
"CLV ", "LDA $nnnn,Y ", "TSX ", "LAX*$nnnn,Y ",
"LDY $nnnn,X ", "LDA $nnnn,X ", "LDX $nnnn,Y ", "LAX*$nnnn,Y ",
"CPY # ", "CMP ($nn,X) ", "SKB* ", "DCM*($nn,X) ",
"CPY $nn ", "CMP $nn ", "DEC $nn ", "DCM*$nn ",
"INY ", "CMP # ", "DEX ", "SAX*# (used!)",
"CPY $nnnn ", "CMP $nnnn ", "DEC $nnnn ", "DCM*$nnnn ",
"BNE ", "CMP ($nn),Y ", "HLT* ", "DCM*($nn),Y ",
"RDM* ", "CMP $nn,X ", "DEC $nn,X ", "DCM*$nn,X ",
"CLD ", "CMP $nnnn,Y ", "NOP* ", "DCM*$nnnn,Y ",
"RDM*$nnnn,X ", "CMP $nnnn,X ", "DEC $nnnn,X ", "DCM*$nnnn,X ",
"CPX # ", "SBC ($nn,X) ", "SKB* ", "INS*($nn,X) ",
"CPX $nn ", "SBC $nn ", "INC $nn ", "INS*$nn ",
"INX ", "SBC # ", "NOP ", "SBC*# ",
"CPX $nnnn ", "SBC $nnnn ", "INC $nnnn ", "INS*$nnnn ",
"BEQ ", "SBC ($nn),Y ", "HLT* ", "INS*($nn),Y ",
"RDM* ", "SBC $nn,X ", "INC $nn,X ", "INS*$nn,X ",
"SED ", "SBC $nnnn,Y ", "NOP* ", "INS*$nnnn,Y ",
"RDM*$nnnn,X ", "SBC $nnnn,X ", "INC $nnnn,X ", "INS*$nnnn,X " );
type t_oper_array is array(0 to 7) of string(1 to 4);
constant c_shift_oper_array : t_oper_array := (
"ASL ", "ROL ", "LSR ", "ROR ", "NOP ", "TST ", "DEC ", "INC " );
constant c_alu_oper_array : t_oper_array := (
"OR ", "AND ", "XOR ", "ADD ", "NOP ", "TST ", "CMP ", "SUB " );
end;
|
-- ledblinker.vhd
--
-- Created on: 12 May 2017
-- Author: Fabian Meyer
--
-- LED blinker with configurable frequency.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ledblinker is
generic(RSTDEF: std_logic := '1');
port (rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
freq: in std_logic_vector(2 downto 0); -- blinking frequency, 000 = stop, 111 = fast
led: out std_logic); -- LED status, active high
end entity ledblinker;
architecture behavioral of ledblinker is
-- define length of counter
constant CNTLEN: natural := 26;
-- counter that is incremented on each clk
signal cnt: std_logic_vector(CNTLEN-1 downto 0) := (others => '0');
-- counter plus zero bit (freq = 0)
signal cnt_tmp: std_logic_vector(CNTLEN downto 0) := (others => '0');
begin
process(rst, clk)
begin
if rst = RSTDEF then
cnt <= (others => '0');
elsif rising_edge(clk) then
-- increment cnt, carry bit defines LED status
cnt <= cnt + 1;
end if;
end process;
-- always keep a leading 0 for freq = 0
cnt_tmp <= '0' & cnt;
-- led status is defined by carry bit
-- position of carry bit is defined by freq
led <= cnt_tmp(CNTLEN - CONV_INTEGER(freq));
end architecture behavioral;
|
use WORK.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.debugtools.all;
entity iomapper is
port (Clk : in std_logic;
cpuclock : in std_logic;
pixelclk : in std_logic;
uartclock : in std_logic;
clock50mhz : in std_logic;
phi0 : in std_logic;
reset : in std_logic;
reset_out : out std_logic;
irq : out std_logic;
nmi : out std_logic;
restore_nmi : out std_logic;
cpu_hypervisor_mode : in std_logic;
address : in std_logic_vector(19 downto 0);
r : in std_logic;
w : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
sd_data_o : out std_logic_vector(7 downto 0);
sector_buffer_mapped : out std_logic;
key_scancode : in unsigned(15 downto 0);
key_scancode_toggle : in std_logic;
reg_isr_out : out unsigned(7 downto 0);
imask_ta_out : out std_logic;
led : out std_logic := '0';
motor : out std_logic := '0';
ps2data : in std_logic;
ps2clock : in std_logic;
pixel_stream_in : in unsigned (7 downto 0);
pixel_y : in unsigned (11 downto 0);
pixel_valid : in std_logic;
pixel_newframe : in std_logic;
pixel_newraster : in std_logic;
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio : inout std_logic;
eth_mdc : out std_logic;
eth_reset : out std_logic;
eth_rxd : in unsigned(1 downto 0);
eth_txd : out unsigned(1 downto 0);
eth_txen : out std_logic;
eth_rxdv : in std_logic;
eth_rxer : in std_logic;
eth_interrupt : in std_logic;
----------------------------------------------------------------------
-- Flash RAM for holding config
----------------------------------------------------------------------
QspiSCK : out std_logic;
QspiDB : inout std_logic_vector(3 downto 0);
QspiCSn : out std_logic;
-------------------------------------------------------------------------
-- Lines for the SDcard interface itself
-------------------------------------------------------------------------
cs_bo : out std_logic;
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic;
---------------------------------------------------------------------------
-- Lines for other devices that we handle here
---------------------------------------------------------------------------
aclMISO : in std_logic;
aclMOSI : out std_logic;
aclSS : out std_logic;
aclSCK : out std_logic;
aclInt1 : in std_logic;
aclInt2 : in std_logic;
micData : in std_logic;
micClk : out std_logic;
micLRSel : out std_logic;
ampPWM : out std_logic;
ampSD : out std_logic;
tmpSDA : out std_logic;
tmpSCL : out std_logic;
tmpInt : in std_logic;
tmpCT : in std_logic;
sw : in std_logic_vector(15 downto 0);
btn : in std_logic_vector(4 downto 0);
seg_led : out unsigned(31 downto 0);
viciii_iomode : in std_logic_vector(1 downto 0);
colourram_at_dc00 : in std_logic;
---------------------------------------------------------------------------
-- IO port to far call stack
---------------------------------------------------------------------------
farcallstack_we : in std_logic;
farcallstack_addr : in std_logic_vector(8 downto 0);
farcallstack_din : in std_logic_vector(63 downto 0);
farcallstack_dout : out std_logic_vector(63 downto 0)
);
end iomapper;
architecture behavioral of iomapper is
component kickstart is
port (
Clk : in std_logic;
address : in std_logic_vector(13 downto 0);
we : in std_logic;
cs : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0));
end component;
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in unsigned(4 downto 0); -- address lines
di : in unsigned(7 downto 0); -- data in (to chip)
do : out unsigned(7 downto 0); -- data out (from chip)
pot_x : in unsigned(7 downto 0); -- paddle input-X
pot_y : in unsigned(7 downto 0); -- paddle input-Y
audio_data : out unsigned(17 downto 0)
);
end component;
component ethernet is
port (
clock : in std_logic;
clock50mhz : in std_logic;
reset : in std_logic;
irq : out std_logic := 'Z';
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio : inout std_logic;
eth_mdc : out std_logic;
eth_reset : out std_logic;
eth_rxd : in unsigned(1 downto 0);
eth_txd : out unsigned(1 downto 0);
eth_txen : out std_logic;
eth_rxdv : in std_logic;
eth_rxer : in std_logic;
eth_interrupt : in std_logic;
-- Signals from the VIC-IV frame packer to supply the compressed video feed
buffer_moby_toggle : in std_logic := '0';
buffer_address : out unsigned(11 downto 0);
buffer_rdata : in unsigned(7 downto 0);
---------------------------------------------------------------------------
-- keyboard event capture via ethernet
---------------------------------------------------------------------------
eth_keycode_toggle : out std_logic;
eth_keycode : out unsigned(15 downto 0);
fastio_addr : in unsigned(19 downto 0);
fastio_write : in std_logic;
fastio_read : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0)
);
end component;
component sdcardio is
port (
clock : in std_logic;
pixelclk : in std_logic;
reset : in std_logic;
---------------------------------------------------------------------------
-- fast IO port (clocked at core clock). 1MB address space
---------------------------------------------------------------------------
fastio_addr : in unsigned(19 downto 0);
fastio_read : in std_logic;
fastio_write : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0);
-- If colour RAM is mapped at $DC00-$DFFF, then don't map sector buffer
colourram_at_dc00 : in std_logic;
viciii_iomode : in std_logic_vector(1 downto 0);
sectorbuffermapped : out std_logic;
sectorbuffermapped2 : out std_logic;
sectorbuffercs : in std_logic;
led : out std_logic := '0';
motor : out std_logic := '0';
-------------------------------------------------------------------------
-- Lines for the SDcard interface itself
-------------------------------------------------------------------------
cs_bo : out std_logic;
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic;
---------------------------------------------------------------------------
-- Lines for other devices that we handle here
---------------------------------------------------------------------------
-- Accelerometer
aclMISO : in std_logic;
aclMOSI : out std_logic;
aclSS : out std_logic;
aclSCK : out std_logic;
aclInt1 : in std_logic;
aclInt2 : in std_logic;
-- Microphone
micData : in std_logic;
micClk : out std_logic;
micLRSel : out std_logic;
-- Audio in from digital SIDs
leftsid_audio : in unsigned(17 downto 0);
rightsid_audio : in unsigned(17 downto 0);
-- Audio output
ampPWM : out std_logic;
ampSD : out std_logic;
-- Temperature sensor
tmpSDA : out std_logic;
tmpSCL : out std_logic;
tmpInt : in std_logic;
tmpCT : in std_logic;
----------------------------------------------------------------------
-- Flash RAM for holding config
----------------------------------------------------------------------
QspiSCK : out std_logic;
QspiDB : inout std_logic_vector(3 downto 0);
QspiCSn : out std_logic;
last_scan_code : in std_logic_vector(12 downto 0);
-------------------------------------------------------------------------
-- And general switch inputs on the FPGA board (good as place as any here)
-------------------------------------------------------------------------
sw : in std_logic_vector(15 downto 0);
btn : in std_logic_vector(4 downto 0)
);
end component;
component cia6526 is
port (
cpuclock : in std_logic;
phi0 : in std_logic;
todclock : in std_logic;
reset : in std_logic;
irq : out std_logic := '1';
reg_isr_out : out unsigned(7 downto 0);
imask_ta_out : out std_logic;
---------------------------------------------------------------------------
-- fast IO port (clocked at core clock). 1MB address space
---------------------------------------------------------------------------
cs : in std_logic;
fastio_address : in unsigned(7 downto 0);
fastio_write : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0);
portaout : out std_logic_vector(7 downto 0);
portain : in std_logic_vector(7 downto 0);
portbout : out std_logic_vector(7 downto 0);
portbin : in std_logic_vector(7 downto 0);
flagin : in std_logic;
pcout : out std_logic;
spout : out std_logic;
spin : in std_logic;
countout : out std_logic;
countin : in std_logic);
end component;
component keymapper is
port (
pixelclk : in std_logic;
last_scan_code : out std_logic_vector(12 downto 0);
nmi : out std_logic := 'Z';
reset : out std_logic := 'Z';
-- PS2 keyboard interface
ps2clock : in std_logic;
ps2data : in std_logic;
-- CIA ports
porta_in : in std_logic_vector(7 downto 0);
portb_in : in std_logic_vector(7 downto 0);
porta_out : out std_logic_vector(7 downto 0);
portb_out : out std_logic_vector(7 downto 0);
---------------------------------------------------------------------------
-- keyboard event capture via ethernet
---------------------------------------------------------------------------
eth_keycode_toggle : in std_logic;
eth_keycode : in unsigned(15 downto 0)
);
end component;
component framepacker is
port (
pixelclock : in std_logic;
ioclock : in std_logic;
hypervisor_mode : in std_logic;
pixel_stream_in : in unsigned (7 downto 0);
pixel_y : in unsigned (11 downto 0);
pixel_valid : in std_logic;
pixel_newframe : in std_logic;
pixel_newraster : in std_logic;
-- Signals for ethernet controller
buffer_moby_toggle : out std_logic := '0';
buffer_address : in unsigned(11 downto 0);
buffer_rdata : out unsigned(7 downto 0);
---------------------------------------------------------------------------
-- fast IO port (clocked at CPU clock).
---------------------------------------------------------------------------
fastio_addr : in unsigned(19 downto 0);
fastio_write : in std_logic;
fastio_read : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0)
);
end component;
component farcallstack IS
PORT (
-- CPU fastio port
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-- CPU parallel push/pop port
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
end component;
signal kickstartcs : std_logic;
signal reset_high : std_logic;
signal clock50hz : std_logic := '1';
constant divisor50hz : integer := 640000; -- 64MHz/50Hz/2;
signal counter50hz : integer := 0;
signal cia1cs : std_logic;
signal cia2cs : std_logic;
signal sectorbuffercs : std_logic;
signal sector_buffer_mapped_read : std_logic;
signal farcallstackcs : std_logic;
signal farcallstack_w : std_logic;
signal farcallstack_wdata : std_logic_vector(63 downto 0);
signal farcallstack_rdata : std_logic_vector(63 downto 0);
signal last_scan_code : std_logic_vector(12 downto 0);
signal cia1porta_out : std_logic_vector(7 downto 0);
signal cia1porta_in : std_logic_vector(7 downto 0);
signal cia1portb_out : std_logic_vector(7 downto 0);
signal cia1portb_in : std_logic_vector(7 downto 0);
signal leftsid_cs : std_logic;
signal leftsid_audio : unsigned(17 downto 0);
signal rightsid_cs : std_logic;
signal rightsid_audio : unsigned(17 downto 0);
signal spare_bits : unsigned(4 downto 0);
signal buffer_moby_toggle : std_logic;
signal buffer_address : unsigned(11 downto 0);
signal buffer_rdata : unsigned(7 downto 0);
signal eth_keycode_toggle : std_logic;
signal eth_keycode : unsigned(15 downto 0);
begin
kickstartrom : kickstart port map (
clk => clk,
address => address(13 downto 0),
we => w,
cs => kickstartcs,
data_i => data_i,
data_o => data_o);
framepacker0: framepacker port map (
ioclock => clk,
pixelclock => pixelclk,
hypervisor_mode => cpu_hypervisor_mode,
pixel_stream_in => pixel_stream_in,
pixel_y => pixel_y,
pixel_valid => pixel_valid,
pixel_newframe => pixel_newframe,
pixel_newraster => pixel_newraster,
buffer_moby_toggle => buffer_moby_toggle,
buffer_address => buffer_address,
buffer_rdata => buffer_rdata,
fastio_addr => unsigned(address(19 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_read => r,
fastio_wdata => unsigned(data_i)
);
cia1: cia6526 port map (
cpuclock => clk,
phi0 => phi0,
todclock => clock50hz,
reset => reset,
irq => irq,
reg_isr_out => reg_isr_out,
imask_ta_out => imask_ta_out,
cs => cia1cs,
fastio_address => unsigned(address(7 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_wdata => unsigned(data_i),
portaout => cia1porta_out,
portbout => cia1portb_out,
portain => cia1porta_in,
portbin => cia1portb_in,
flagin => '1',
spin => '1',
countin => '1'
);
cia2two: cia6526 port map (
cpuclock => clk,
phi0 => phi0,
todclock => clock50hz,
reset => reset,
irq => nmi,
cs => cia2cs,
fastio_address => unsigned(address(7 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_wdata => unsigned(data_i),
-- CIA ports not connected by default
portbin => x"ff",
portain => x"ff",
flagin => '1',
spin => '1',
countin => '1'
);
keymapper0 : keymapper port map (
pixelclk => clk,
nmi => restore_nmi,
reset => reset_out,
ps2clock => ps2clock,
ps2data => ps2data,
last_scan_code => last_scan_code,
-- key_status => seg_led(1 downto 0),
porta_in => cia1porta_out,
portb_in => cia1portb_out,
porta_out => cia1porta_in,
portb_out => cia1portb_in,
-- remote keyboard input via ethernet
-- eth_keycode_toggle => eth_keycode_toggle,
-- eth_keycode => eth_keycode
-- remote
eth_keycode_toggle => key_scancode_toggle,
eth_keycode => key_scancode
);
leftsid: sid6581 port map (
clk_1MHz => phi0,
clk32 => clk,
reset => reset_high,
cs => leftsid_cs,
we => w,
addr => unsigned(address(4 downto 0)),
di => unsigned(data_i),
std_logic_vector(do) => data_o,
pot_x => x"01",
pot_y => x"02",
audio_data => leftsid_audio);
rightsid: sid6581 port map (
clk_1MHz => phi0,
clk32 => clk,
reset => reset_high,
cs => rightsid_cs,
we => w,
addr => unsigned(address(4 downto 0)),
di => unsigned(data_i),
std_logic_vector(do) => data_o,
pot_x => x"03",
pot_y => x"04",
audio_data => rightsid_audio);
ethernet0 : ethernet port map (
clock50mhz => clock50mhz,
clock => clk,
reset => reset,
irq => irq,
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio => eth_mdio,
eth_mdc => eth_mdc,
eth_reset => eth_reset,
eth_rxd => eth_rxd,
eth_txd => eth_txd,
eth_txen => eth_txen,
eth_rxdv => eth_rxdv,
eth_rxer => eth_rxer,
eth_interrupt => eth_interrupt,
buffer_moby_toggle => buffer_moby_toggle,
buffer_address => buffer_address,
buffer_rdata => buffer_rdata,
eth_keycode_toggle => eth_keycode_toggle,
eth_keycode => eth_keycode,
fastio_addr => unsigned(address),
fastio_write => w,
fastio_read => r,
fastio_wdata => unsigned(data_i),
std_logic_vector(fastio_rdata) => data_o
);
sdcard0 : sdcardio port map (
pixelclk => pixelclk,
clock => clk,
reset => reset,
fastio_addr => unsigned(address),
fastio_write => w,
fastio_read => r,
fastio_wdata => unsigned(data_i),
std_logic_vector(fastio_rdata) => data_o,
colourram_at_dc00 => colourram_at_dc00,
viciii_iomode => viciii_iomode,
sectorbuffermapped => sector_buffer_mapped,
sectorbuffermapped2 => sector_buffer_mapped_read,
sectorbuffercs => sectorbuffercs,
led => led,
motor => motor,
sw => sw,
btn => btn,
cs_bo => cs_bo,
sclk_o => sclk_o,
mosi_o => mosi_o,
miso_i => miso_i,
aclMISO => aclMISO,
aclMOSI => aclMOSI,
aclSS => aclSS,
aclSCK => aclSCK,
aclInt1 => aclInt1,
aclInt2 => aclInt2,
micData => micData,
micClk => micClk,
micLRSel => micLRSel,
leftsid_audio => leftsid_audio,
rightsid_audio => rightsid_audio,
ampSD => ampSD,
ampPWM => ampPWM,
tmpSDA => tmpSDA,
tmpSCL => tmpSCL,
tmpInt => tmpInt,
tmpCT => tmpCT,
QspiSCK => QspiSCK,
QspiDB => QspiDB,
QspiCSn => QspiCSn,
last_scan_code => last_scan_code
);
farcallstack0: farcallstack port map (
clka => clk,
ena => farcallstackcs,
wea(0) => w,
addra => address(11 downto 0),
dina => data_i,
douta => data_o,
clkb => cpuclock,
web(0) => farcallstack_w,
addrb => farcallstack_addr,
dinb => farcallstack_wdata,
doutb => farcallstack_rdata
);
process(reset)
begin
reset_high <= not reset;
end process;
process(clk)
begin
if rising_edge(clk) then
-- Generate 50Hz signal for TOD clock
-- (Note that we are a bit conflicted here, as our video mode is PALx4,
-- but at 60Hz. We will make our CIAs take 50Hz like in most PAL countries
-- so that we don't confuse things too much. We will probably add a 50Hz
-- raster interrupt filter to help music and games play at the right rate.)
if counter50hz<divisor50hz then
counter50hz <= counter50hz + 1;
else
clock50hz <= not clock50hz;
counter50hz <= 0;
end if;
seg_led(12) <= eth_keycode_toggle;
seg_led(11) <= last_scan_code(12);
seg_led(10 downto 0) <= unsigned(last_scan_code(10 downto 0));
end if;
end process;
process (r,w,address,cia1portb_in,cia1porta_out,colourram_at_dc00,
sector_buffer_mapped_read)
begin -- process
if (r or w) = '1' then
-- @IO:GS $FFF8000-$FFFBFFF 16KB Kickstart/hypervisor ROM
-- @IO:GS $FFF8000 Hypervisor entry point when $D67F is written
if address(19 downto 14)&"00" = x"F8" then
kickstartcs <= cpu_hypervisor_mode;
else
kickstartcs <='0';
end if;
-- @IO:GS $FFF0000-$FFF0FFF - CPU far call stack (512x8 byte entries)
if address(19 downto 12) = x"F0" then
farcallstackcs <= '1';
else
farcallstackcs <= '0';
end if;
-- sdcard sector buffer: only mapped if no colour ram @ $DC00, and if
-- the sectorbuffer mapping flag is set
sectorbuffercs <= '0';
report "fastio address = $" & to_hstring(address) severity note;
if address(19 downto 16) = x"D"
and address(15 downto 14) = "00"
and address(11 downto 9)&'0' = x"E"
and sector_buffer_mapped_read = '1' and colourram_at_dc00 = '0' then
sectorbuffercs <= '1';
report "selecting SD card sector buffer" severity note;
end if;
-- Also map SD card sector buffer at $FFD6000 - $FFD61FF regardless of
-- VIC-IV IO mode and mapping of colour RAM
if address(19 downto 8) = x"D60" or address(19 downto 8) = x"D61" then
sectorbuffercs <= '1';
end if;
-- Now map the SIDs
-- @IO:C64 $D440-$D47F = left SID
-- @IO:C64 $D400-$D43F = right SID
-- @IO:C64 $D480-$D4FF = repeated images of SIDs
-- Presumably repeated through to $D5FF. But we will repeat to $D4FF only
-- so that we can use $D500-$D5FF for other stuff.
case address(19 downto 8) is
when x"D04" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D14" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D24" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D34" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when others => leftsid_cs <= '0'; rightsid_cs <= '0';
end case;
-- $D500 - $D5FF is not currently used. Probably use some for FPU.
-- $D600 - $D60F is reserved for 6551 serial UART emulation for C65
-- compatibility (6551 actually only has 4 registers).
-- 6551 is not currently implemented, so this is just unmapped for now,
-- except for any read values required to allow the C65 ROM to function.
-- Hypervisor control (only visible from hypervisor mode) $D640 - $D67F
-- The hypervisor is a CPU provided function.
-- SD controller and miscellaneous hardware (microphone, accelerometer etc)
-- uses $D680 - $D6FF
-- CPU uses $FFD{0,1,2,3}700 for DMAgic and other CPU-hosted IO registers.
-- Now map the CIAs.
-- These are a bit fun, because they only get mapped if colour RAM isn't
-- being mapped in $DC00-$DFFF using the C65 2K colour ram register
cia1cs <='0';
cia2cs <='0';
if colourram_at_dc00='0' and sector_buffer_mapped_read='0' then
case address(19 downto 8) is
when x"D0C" => cia1cs <='1';
when x"D1C" => cia1cs <='1';
when x"D2C" => cia1cs <='1';
when x"D3C" => cia1cs <='1';
when x"D0D" => cia2cs <='1';
when x"D1D" => cia2cs <='1';
when x"D2D" => cia2cs <='1';
when x"D3D" => cia2cs <='1';
when others => null;
end case;
end if;
else
cia1cs <= '0';
cia2cs <= '0';
kickstartcs <= '0';
sectorbuffercs <= '0';
leftsid_cs <= '0';
rightsid_cs <= '0';
farcallstackcs <= '0';
end if;
end process;
end behavioral;
|
use WORK.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.debugtools.all;
entity iomapper is
port (Clk : in std_logic;
cpuclock : in std_logic;
pixelclk : in std_logic;
uartclock : in std_logic;
clock50mhz : in std_logic;
phi0 : in std_logic;
reset : in std_logic;
reset_out : out std_logic;
irq : out std_logic;
nmi : out std_logic;
restore_nmi : out std_logic;
cpu_hypervisor_mode : in std_logic;
address : in std_logic_vector(19 downto 0);
r : in std_logic;
w : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
sd_data_o : out std_logic_vector(7 downto 0);
sector_buffer_mapped : out std_logic;
key_scancode : in unsigned(15 downto 0);
key_scancode_toggle : in std_logic;
reg_isr_out : out unsigned(7 downto 0);
imask_ta_out : out std_logic;
led : out std_logic := '0';
motor : out std_logic := '0';
ps2data : in std_logic;
ps2clock : in std_logic;
pixel_stream_in : in unsigned (7 downto 0);
pixel_y : in unsigned (11 downto 0);
pixel_valid : in std_logic;
pixel_newframe : in std_logic;
pixel_newraster : in std_logic;
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio : inout std_logic;
eth_mdc : out std_logic;
eth_reset : out std_logic;
eth_rxd : in unsigned(1 downto 0);
eth_txd : out unsigned(1 downto 0);
eth_txen : out std_logic;
eth_rxdv : in std_logic;
eth_rxer : in std_logic;
eth_interrupt : in std_logic;
----------------------------------------------------------------------
-- Flash RAM for holding config
----------------------------------------------------------------------
QspiSCK : out std_logic;
QspiDB : inout std_logic_vector(3 downto 0);
QspiCSn : out std_logic;
-------------------------------------------------------------------------
-- Lines for the SDcard interface itself
-------------------------------------------------------------------------
cs_bo : out std_logic;
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic;
---------------------------------------------------------------------------
-- Lines for other devices that we handle here
---------------------------------------------------------------------------
aclMISO : in std_logic;
aclMOSI : out std_logic;
aclSS : out std_logic;
aclSCK : out std_logic;
aclInt1 : in std_logic;
aclInt2 : in std_logic;
micData : in std_logic;
micClk : out std_logic;
micLRSel : out std_logic;
ampPWM : out std_logic;
ampSD : out std_logic;
tmpSDA : out std_logic;
tmpSCL : out std_logic;
tmpInt : in std_logic;
tmpCT : in std_logic;
sw : in std_logic_vector(15 downto 0);
btn : in std_logic_vector(4 downto 0);
seg_led : out unsigned(31 downto 0);
viciii_iomode : in std_logic_vector(1 downto 0);
colourram_at_dc00 : in std_logic;
---------------------------------------------------------------------------
-- IO port to far call stack
---------------------------------------------------------------------------
farcallstack_we : in std_logic;
farcallstack_addr : in std_logic_vector(8 downto 0);
farcallstack_din : in std_logic_vector(63 downto 0);
farcallstack_dout : out std_logic_vector(63 downto 0)
);
end iomapper;
architecture behavioral of iomapper is
component kickstart is
port (
Clk : in std_logic;
address : in std_logic_vector(13 downto 0);
we : in std_logic;
cs : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0));
end component;
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in unsigned(4 downto 0); -- address lines
di : in unsigned(7 downto 0); -- data in (to chip)
do : out unsigned(7 downto 0); -- data out (from chip)
pot_x : in unsigned(7 downto 0); -- paddle input-X
pot_y : in unsigned(7 downto 0); -- paddle input-Y
audio_data : out unsigned(17 downto 0)
);
end component;
component ethernet is
port (
clock : in std_logic;
clock50mhz : in std_logic;
reset : in std_logic;
irq : out std_logic := 'Z';
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio : inout std_logic;
eth_mdc : out std_logic;
eth_reset : out std_logic;
eth_rxd : in unsigned(1 downto 0);
eth_txd : out unsigned(1 downto 0);
eth_txen : out std_logic;
eth_rxdv : in std_logic;
eth_rxer : in std_logic;
eth_interrupt : in std_logic;
-- Signals from the VIC-IV frame packer to supply the compressed video feed
buffer_moby_toggle : in std_logic := '0';
buffer_address : out unsigned(11 downto 0);
buffer_rdata : in unsigned(7 downto 0);
---------------------------------------------------------------------------
-- keyboard event capture via ethernet
---------------------------------------------------------------------------
eth_keycode_toggle : out std_logic;
eth_keycode : out unsigned(15 downto 0);
fastio_addr : in unsigned(19 downto 0);
fastio_write : in std_logic;
fastio_read : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0)
);
end component;
component sdcardio is
port (
clock : in std_logic;
pixelclk : in std_logic;
reset : in std_logic;
---------------------------------------------------------------------------
-- fast IO port (clocked at core clock). 1MB address space
---------------------------------------------------------------------------
fastio_addr : in unsigned(19 downto 0);
fastio_read : in std_logic;
fastio_write : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0);
-- If colour RAM is mapped at $DC00-$DFFF, then don't map sector buffer
colourram_at_dc00 : in std_logic;
viciii_iomode : in std_logic_vector(1 downto 0);
sectorbuffermapped : out std_logic;
sectorbuffermapped2 : out std_logic;
sectorbuffercs : in std_logic;
led : out std_logic := '0';
motor : out std_logic := '0';
-------------------------------------------------------------------------
-- Lines for the SDcard interface itself
-------------------------------------------------------------------------
cs_bo : out std_logic;
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic;
---------------------------------------------------------------------------
-- Lines for other devices that we handle here
---------------------------------------------------------------------------
-- Accelerometer
aclMISO : in std_logic;
aclMOSI : out std_logic;
aclSS : out std_logic;
aclSCK : out std_logic;
aclInt1 : in std_logic;
aclInt2 : in std_logic;
-- Microphone
micData : in std_logic;
micClk : out std_logic;
micLRSel : out std_logic;
-- Audio in from digital SIDs
leftsid_audio : in unsigned(17 downto 0);
rightsid_audio : in unsigned(17 downto 0);
-- Audio output
ampPWM : out std_logic;
ampSD : out std_logic;
-- Temperature sensor
tmpSDA : out std_logic;
tmpSCL : out std_logic;
tmpInt : in std_logic;
tmpCT : in std_logic;
----------------------------------------------------------------------
-- Flash RAM for holding config
----------------------------------------------------------------------
QspiSCK : out std_logic;
QspiDB : inout std_logic_vector(3 downto 0);
QspiCSn : out std_logic;
last_scan_code : in std_logic_vector(12 downto 0);
-------------------------------------------------------------------------
-- And general switch inputs on the FPGA board (good as place as any here)
-------------------------------------------------------------------------
sw : in std_logic_vector(15 downto 0);
btn : in std_logic_vector(4 downto 0)
);
end component;
component cia6526 is
port (
cpuclock : in std_logic;
phi0 : in std_logic;
todclock : in std_logic;
reset : in std_logic;
irq : out std_logic := '1';
reg_isr_out : out unsigned(7 downto 0);
imask_ta_out : out std_logic;
---------------------------------------------------------------------------
-- fast IO port (clocked at core clock). 1MB address space
---------------------------------------------------------------------------
cs : in std_logic;
fastio_address : in unsigned(7 downto 0);
fastio_write : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0);
portaout : out std_logic_vector(7 downto 0);
portain : in std_logic_vector(7 downto 0);
portbout : out std_logic_vector(7 downto 0);
portbin : in std_logic_vector(7 downto 0);
flagin : in std_logic;
pcout : out std_logic;
spout : out std_logic;
spin : in std_logic;
countout : out std_logic;
countin : in std_logic);
end component;
component keymapper is
port (
pixelclk : in std_logic;
last_scan_code : out std_logic_vector(12 downto 0);
nmi : out std_logic := 'Z';
reset : out std_logic := 'Z';
-- PS2 keyboard interface
ps2clock : in std_logic;
ps2data : in std_logic;
-- CIA ports
porta_in : in std_logic_vector(7 downto 0);
portb_in : in std_logic_vector(7 downto 0);
porta_out : out std_logic_vector(7 downto 0);
portb_out : out std_logic_vector(7 downto 0);
---------------------------------------------------------------------------
-- keyboard event capture via ethernet
---------------------------------------------------------------------------
eth_keycode_toggle : in std_logic;
eth_keycode : in unsigned(15 downto 0)
);
end component;
component framepacker is
port (
pixelclock : in std_logic;
ioclock : in std_logic;
hypervisor_mode : in std_logic;
pixel_stream_in : in unsigned (7 downto 0);
pixel_y : in unsigned (11 downto 0);
pixel_valid : in std_logic;
pixel_newframe : in std_logic;
pixel_newraster : in std_logic;
-- Signals for ethernet controller
buffer_moby_toggle : out std_logic := '0';
buffer_address : in unsigned(11 downto 0);
buffer_rdata : out unsigned(7 downto 0);
---------------------------------------------------------------------------
-- fast IO port (clocked at CPU clock).
---------------------------------------------------------------------------
fastio_addr : in unsigned(19 downto 0);
fastio_write : in std_logic;
fastio_read : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0)
);
end component;
component farcallstack IS
PORT (
-- CPU fastio port
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-- CPU parallel push/pop port
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
end component;
signal kickstartcs : std_logic;
signal reset_high : std_logic;
signal clock50hz : std_logic := '1';
constant divisor50hz : integer := 640000; -- 64MHz/50Hz/2;
signal counter50hz : integer := 0;
signal cia1cs : std_logic;
signal cia2cs : std_logic;
signal sectorbuffercs : std_logic;
signal sector_buffer_mapped_read : std_logic;
signal farcallstackcs : std_logic;
signal farcallstack_w : std_logic;
signal farcallstack_wdata : std_logic_vector(63 downto 0);
signal farcallstack_rdata : std_logic_vector(63 downto 0);
signal last_scan_code : std_logic_vector(12 downto 0);
signal cia1porta_out : std_logic_vector(7 downto 0);
signal cia1porta_in : std_logic_vector(7 downto 0);
signal cia1portb_out : std_logic_vector(7 downto 0);
signal cia1portb_in : std_logic_vector(7 downto 0);
signal leftsid_cs : std_logic;
signal leftsid_audio : unsigned(17 downto 0);
signal rightsid_cs : std_logic;
signal rightsid_audio : unsigned(17 downto 0);
signal spare_bits : unsigned(4 downto 0);
signal buffer_moby_toggle : std_logic;
signal buffer_address : unsigned(11 downto 0);
signal buffer_rdata : unsigned(7 downto 0);
signal eth_keycode_toggle : std_logic;
signal eth_keycode : unsigned(15 downto 0);
begin
kickstartrom : kickstart port map (
clk => clk,
address => address(13 downto 0),
we => w,
cs => kickstartcs,
data_i => data_i,
data_o => data_o);
framepacker0: framepacker port map (
ioclock => clk,
pixelclock => pixelclk,
hypervisor_mode => cpu_hypervisor_mode,
pixel_stream_in => pixel_stream_in,
pixel_y => pixel_y,
pixel_valid => pixel_valid,
pixel_newframe => pixel_newframe,
pixel_newraster => pixel_newraster,
buffer_moby_toggle => buffer_moby_toggle,
buffer_address => buffer_address,
buffer_rdata => buffer_rdata,
fastio_addr => unsigned(address(19 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_read => r,
fastio_wdata => unsigned(data_i)
);
cia1: cia6526 port map (
cpuclock => clk,
phi0 => phi0,
todclock => clock50hz,
reset => reset,
irq => irq,
reg_isr_out => reg_isr_out,
imask_ta_out => imask_ta_out,
cs => cia1cs,
fastio_address => unsigned(address(7 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_wdata => unsigned(data_i),
portaout => cia1porta_out,
portbout => cia1portb_out,
portain => cia1porta_in,
portbin => cia1portb_in,
flagin => '1',
spin => '1',
countin => '1'
);
cia2two: cia6526 port map (
cpuclock => clk,
phi0 => phi0,
todclock => clock50hz,
reset => reset,
irq => nmi,
cs => cia2cs,
fastio_address => unsigned(address(7 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_wdata => unsigned(data_i),
-- CIA ports not connected by default
portbin => x"ff",
portain => x"ff",
flagin => '1',
spin => '1',
countin => '1'
);
keymapper0 : keymapper port map (
pixelclk => clk,
nmi => restore_nmi,
reset => reset_out,
ps2clock => ps2clock,
ps2data => ps2data,
last_scan_code => last_scan_code,
-- key_status => seg_led(1 downto 0),
porta_in => cia1porta_out,
portb_in => cia1portb_out,
porta_out => cia1porta_in,
portb_out => cia1portb_in,
-- remote keyboard input via ethernet
-- eth_keycode_toggle => eth_keycode_toggle,
-- eth_keycode => eth_keycode
-- remote
eth_keycode_toggle => key_scancode_toggle,
eth_keycode => key_scancode
);
leftsid: sid6581 port map (
clk_1MHz => phi0,
clk32 => clk,
reset => reset_high,
cs => leftsid_cs,
we => w,
addr => unsigned(address(4 downto 0)),
di => unsigned(data_i),
std_logic_vector(do) => data_o,
pot_x => x"01",
pot_y => x"02",
audio_data => leftsid_audio);
rightsid: sid6581 port map (
clk_1MHz => phi0,
clk32 => clk,
reset => reset_high,
cs => rightsid_cs,
we => w,
addr => unsigned(address(4 downto 0)),
di => unsigned(data_i),
std_logic_vector(do) => data_o,
pot_x => x"03",
pot_y => x"04",
audio_data => rightsid_audio);
ethernet0 : ethernet port map (
clock50mhz => clock50mhz,
clock => clk,
reset => reset,
irq => irq,
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio => eth_mdio,
eth_mdc => eth_mdc,
eth_reset => eth_reset,
eth_rxd => eth_rxd,
eth_txd => eth_txd,
eth_txen => eth_txen,
eth_rxdv => eth_rxdv,
eth_rxer => eth_rxer,
eth_interrupt => eth_interrupt,
buffer_moby_toggle => buffer_moby_toggle,
buffer_address => buffer_address,
buffer_rdata => buffer_rdata,
eth_keycode_toggle => eth_keycode_toggle,
eth_keycode => eth_keycode,
fastio_addr => unsigned(address),
fastio_write => w,
fastio_read => r,
fastio_wdata => unsigned(data_i),
std_logic_vector(fastio_rdata) => data_o
);
sdcard0 : sdcardio port map (
pixelclk => pixelclk,
clock => clk,
reset => reset,
fastio_addr => unsigned(address),
fastio_write => w,
fastio_read => r,
fastio_wdata => unsigned(data_i),
std_logic_vector(fastio_rdata) => data_o,
colourram_at_dc00 => colourram_at_dc00,
viciii_iomode => viciii_iomode,
sectorbuffermapped => sector_buffer_mapped,
sectorbuffermapped2 => sector_buffer_mapped_read,
sectorbuffercs => sectorbuffercs,
led => led,
motor => motor,
sw => sw,
btn => btn,
cs_bo => cs_bo,
sclk_o => sclk_o,
mosi_o => mosi_o,
miso_i => miso_i,
aclMISO => aclMISO,
aclMOSI => aclMOSI,
aclSS => aclSS,
aclSCK => aclSCK,
aclInt1 => aclInt1,
aclInt2 => aclInt2,
micData => micData,
micClk => micClk,
micLRSel => micLRSel,
leftsid_audio => leftsid_audio,
rightsid_audio => rightsid_audio,
ampSD => ampSD,
ampPWM => ampPWM,
tmpSDA => tmpSDA,
tmpSCL => tmpSCL,
tmpInt => tmpInt,
tmpCT => tmpCT,
QspiSCK => QspiSCK,
QspiDB => QspiDB,
QspiCSn => QspiCSn,
last_scan_code => last_scan_code
);
farcallstack0: farcallstack port map (
clka => clk,
ena => farcallstackcs,
wea(0) => w,
addra => address(11 downto 0),
dina => data_i,
douta => data_o,
clkb => cpuclock,
web(0) => farcallstack_w,
addrb => farcallstack_addr,
dinb => farcallstack_wdata,
doutb => farcallstack_rdata
);
process(reset)
begin
reset_high <= not reset;
end process;
process(clk)
begin
if rising_edge(clk) then
-- Generate 50Hz signal for TOD clock
-- (Note that we are a bit conflicted here, as our video mode is PALx4,
-- but at 60Hz. We will make our CIAs take 50Hz like in most PAL countries
-- so that we don't confuse things too much. We will probably add a 50Hz
-- raster interrupt filter to help music and games play at the right rate.)
if counter50hz<divisor50hz then
counter50hz <= counter50hz + 1;
else
clock50hz <= not clock50hz;
counter50hz <= 0;
end if;
seg_led(12) <= eth_keycode_toggle;
seg_led(11) <= last_scan_code(12);
seg_led(10 downto 0) <= unsigned(last_scan_code(10 downto 0));
end if;
end process;
process (r,w,address,cia1portb_in,cia1porta_out,colourram_at_dc00,
sector_buffer_mapped_read)
begin -- process
if (r or w) = '1' then
-- @IO:GS $FFF8000-$FFFBFFF 16KB Kickstart/hypervisor ROM
-- @IO:GS $FFF8000 Hypervisor entry point when $D67F is written
if address(19 downto 14)&"00" = x"F8" then
kickstartcs <= cpu_hypervisor_mode;
else
kickstartcs <='0';
end if;
-- @IO:GS $FFF0000-$FFF0FFF - CPU far call stack (512x8 byte entries)
if address(19 downto 12) = x"F0" then
farcallstackcs <= '1';
else
farcallstackcs <= '0';
end if;
-- sdcard sector buffer: only mapped if no colour ram @ $DC00, and if
-- the sectorbuffer mapping flag is set
sectorbuffercs <= '0';
report "fastio address = $" & to_hstring(address) severity note;
if address(19 downto 16) = x"D"
and address(15 downto 14) = "00"
and address(11 downto 9)&'0' = x"E"
and sector_buffer_mapped_read = '1' and colourram_at_dc00 = '0' then
sectorbuffercs <= '1';
report "selecting SD card sector buffer" severity note;
end if;
-- Also map SD card sector buffer at $FFD6000 - $FFD61FF regardless of
-- VIC-IV IO mode and mapping of colour RAM
if address(19 downto 8) = x"D60" or address(19 downto 8) = x"D61" then
sectorbuffercs <= '1';
end if;
-- Now map the SIDs
-- @IO:C64 $D440-$D47F = left SID
-- @IO:C64 $D400-$D43F = right SID
-- @IO:C64 $D480-$D4FF = repeated images of SIDs
-- Presumably repeated through to $D5FF. But we will repeat to $D4FF only
-- so that we can use $D500-$D5FF for other stuff.
case address(19 downto 8) is
when x"D04" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D14" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D24" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D34" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when others => leftsid_cs <= '0'; rightsid_cs <= '0';
end case;
-- $D500 - $D5FF is not currently used. Probably use some for FPU.
-- $D600 - $D60F is reserved for 6551 serial UART emulation for C65
-- compatibility (6551 actually only has 4 registers).
-- 6551 is not currently implemented, so this is just unmapped for now,
-- except for any read values required to allow the C65 ROM to function.
-- Hypervisor control (only visible from hypervisor mode) $D640 - $D67F
-- The hypervisor is a CPU provided function.
-- SD controller and miscellaneous hardware (microphone, accelerometer etc)
-- uses $D680 - $D6FF
-- CPU uses $FFD{0,1,2,3}700 for DMAgic and other CPU-hosted IO registers.
-- Now map the CIAs.
-- These are a bit fun, because they only get mapped if colour RAM isn't
-- being mapped in $DC00-$DFFF using the C65 2K colour ram register
cia1cs <='0';
cia2cs <='0';
if colourram_at_dc00='0' and sector_buffer_mapped_read='0' then
case address(19 downto 8) is
when x"D0C" => cia1cs <='1';
when x"D1C" => cia1cs <='1';
when x"D2C" => cia1cs <='1';
when x"D3C" => cia1cs <='1';
when x"D0D" => cia2cs <='1';
when x"D1D" => cia2cs <='1';
when x"D2D" => cia2cs <='1';
when x"D3D" => cia2cs <='1';
when others => null;
end case;
end if;
else
cia1cs <= '0';
cia2cs <= '0';
kickstartcs <= '0';
sectorbuffercs <= '0';
leftsid_cs <= '0';
rightsid_cs <= '0';
farcallstackcs <= '0';
end if;
end process;
end behavioral;
|
use WORK.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.debugtools.all;
entity iomapper is
port (Clk : in std_logic;
cpuclock : in std_logic;
pixelclk : in std_logic;
uartclock : in std_logic;
clock50mhz : in std_logic;
phi0 : in std_logic;
reset : in std_logic;
reset_out : out std_logic;
irq : out std_logic;
nmi : out std_logic;
restore_nmi : out std_logic;
cpu_hypervisor_mode : in std_logic;
address : in std_logic_vector(19 downto 0);
r : in std_logic;
w : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
sd_data_o : out std_logic_vector(7 downto 0);
sector_buffer_mapped : out std_logic;
key_scancode : in unsigned(15 downto 0);
key_scancode_toggle : in std_logic;
reg_isr_out : out unsigned(7 downto 0);
imask_ta_out : out std_logic;
led : out std_logic := '0';
motor : out std_logic := '0';
ps2data : in std_logic;
ps2clock : in std_logic;
pixel_stream_in : in unsigned (7 downto 0);
pixel_y : in unsigned (11 downto 0);
pixel_valid : in std_logic;
pixel_newframe : in std_logic;
pixel_newraster : in std_logic;
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio : inout std_logic;
eth_mdc : out std_logic;
eth_reset : out std_logic;
eth_rxd : in unsigned(1 downto 0);
eth_txd : out unsigned(1 downto 0);
eth_txen : out std_logic;
eth_rxdv : in std_logic;
eth_rxer : in std_logic;
eth_interrupt : in std_logic;
----------------------------------------------------------------------
-- Flash RAM for holding config
----------------------------------------------------------------------
QspiSCK : out std_logic;
QspiDB : inout std_logic_vector(3 downto 0);
QspiCSn : out std_logic;
-------------------------------------------------------------------------
-- Lines for the SDcard interface itself
-------------------------------------------------------------------------
cs_bo : out std_logic;
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic;
---------------------------------------------------------------------------
-- Lines for other devices that we handle here
---------------------------------------------------------------------------
aclMISO : in std_logic;
aclMOSI : out std_logic;
aclSS : out std_logic;
aclSCK : out std_logic;
aclInt1 : in std_logic;
aclInt2 : in std_logic;
micData : in std_logic;
micClk : out std_logic;
micLRSel : out std_logic;
ampPWM : out std_logic;
ampSD : out std_logic;
tmpSDA : out std_logic;
tmpSCL : out std_logic;
tmpInt : in std_logic;
tmpCT : in std_logic;
sw : in std_logic_vector(15 downto 0);
btn : in std_logic_vector(4 downto 0);
seg_led : out unsigned(31 downto 0);
viciii_iomode : in std_logic_vector(1 downto 0);
colourram_at_dc00 : in std_logic;
---------------------------------------------------------------------------
-- IO port to far call stack
---------------------------------------------------------------------------
farcallstack_we : in std_logic;
farcallstack_addr : in std_logic_vector(8 downto 0);
farcallstack_din : in std_logic_vector(63 downto 0);
farcallstack_dout : out std_logic_vector(63 downto 0)
);
end iomapper;
architecture behavioral of iomapper is
component kickstart is
port (
Clk : in std_logic;
address : in std_logic_vector(13 downto 0);
we : in std_logic;
cs : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0));
end component;
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in unsigned(4 downto 0); -- address lines
di : in unsigned(7 downto 0); -- data in (to chip)
do : out unsigned(7 downto 0); -- data out (from chip)
pot_x : in unsigned(7 downto 0); -- paddle input-X
pot_y : in unsigned(7 downto 0); -- paddle input-Y
audio_data : out unsigned(17 downto 0)
);
end component;
component ethernet is
port (
clock : in std_logic;
clock50mhz : in std_logic;
reset : in std_logic;
irq : out std_logic := 'Z';
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio : inout std_logic;
eth_mdc : out std_logic;
eth_reset : out std_logic;
eth_rxd : in unsigned(1 downto 0);
eth_txd : out unsigned(1 downto 0);
eth_txen : out std_logic;
eth_rxdv : in std_logic;
eth_rxer : in std_logic;
eth_interrupt : in std_logic;
-- Signals from the VIC-IV frame packer to supply the compressed video feed
buffer_moby_toggle : in std_logic := '0';
buffer_address : out unsigned(11 downto 0);
buffer_rdata : in unsigned(7 downto 0);
---------------------------------------------------------------------------
-- keyboard event capture via ethernet
---------------------------------------------------------------------------
eth_keycode_toggle : out std_logic;
eth_keycode : out unsigned(15 downto 0);
fastio_addr : in unsigned(19 downto 0);
fastio_write : in std_logic;
fastio_read : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0)
);
end component;
component sdcardio is
port (
clock : in std_logic;
pixelclk : in std_logic;
reset : in std_logic;
---------------------------------------------------------------------------
-- fast IO port (clocked at core clock). 1MB address space
---------------------------------------------------------------------------
fastio_addr : in unsigned(19 downto 0);
fastio_read : in std_logic;
fastio_write : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0);
-- If colour RAM is mapped at $DC00-$DFFF, then don't map sector buffer
colourram_at_dc00 : in std_logic;
viciii_iomode : in std_logic_vector(1 downto 0);
sectorbuffermapped : out std_logic;
sectorbuffermapped2 : out std_logic;
sectorbuffercs : in std_logic;
led : out std_logic := '0';
motor : out std_logic := '0';
-------------------------------------------------------------------------
-- Lines for the SDcard interface itself
-------------------------------------------------------------------------
cs_bo : out std_logic;
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic;
---------------------------------------------------------------------------
-- Lines for other devices that we handle here
---------------------------------------------------------------------------
-- Accelerometer
aclMISO : in std_logic;
aclMOSI : out std_logic;
aclSS : out std_logic;
aclSCK : out std_logic;
aclInt1 : in std_logic;
aclInt2 : in std_logic;
-- Microphone
micData : in std_logic;
micClk : out std_logic;
micLRSel : out std_logic;
-- Audio in from digital SIDs
leftsid_audio : in unsigned(17 downto 0);
rightsid_audio : in unsigned(17 downto 0);
-- Audio output
ampPWM : out std_logic;
ampSD : out std_logic;
-- Temperature sensor
tmpSDA : out std_logic;
tmpSCL : out std_logic;
tmpInt : in std_logic;
tmpCT : in std_logic;
----------------------------------------------------------------------
-- Flash RAM for holding config
----------------------------------------------------------------------
QspiSCK : out std_logic;
QspiDB : inout std_logic_vector(3 downto 0);
QspiCSn : out std_logic;
last_scan_code : in std_logic_vector(12 downto 0);
-------------------------------------------------------------------------
-- And general switch inputs on the FPGA board (good as place as any here)
-------------------------------------------------------------------------
sw : in std_logic_vector(15 downto 0);
btn : in std_logic_vector(4 downto 0)
);
end component;
component cia6526 is
port (
cpuclock : in std_logic;
phi0 : in std_logic;
todclock : in std_logic;
reset : in std_logic;
irq : out std_logic := '1';
reg_isr_out : out unsigned(7 downto 0);
imask_ta_out : out std_logic;
---------------------------------------------------------------------------
-- fast IO port (clocked at core clock). 1MB address space
---------------------------------------------------------------------------
cs : in std_logic;
fastio_address : in unsigned(7 downto 0);
fastio_write : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0);
portaout : out std_logic_vector(7 downto 0);
portain : in std_logic_vector(7 downto 0);
portbout : out std_logic_vector(7 downto 0);
portbin : in std_logic_vector(7 downto 0);
flagin : in std_logic;
pcout : out std_logic;
spout : out std_logic;
spin : in std_logic;
countout : out std_logic;
countin : in std_logic);
end component;
component keymapper is
port (
pixelclk : in std_logic;
last_scan_code : out std_logic_vector(12 downto 0);
nmi : out std_logic := 'Z';
reset : out std_logic := 'Z';
-- PS2 keyboard interface
ps2clock : in std_logic;
ps2data : in std_logic;
-- CIA ports
porta_in : in std_logic_vector(7 downto 0);
portb_in : in std_logic_vector(7 downto 0);
porta_out : out std_logic_vector(7 downto 0);
portb_out : out std_logic_vector(7 downto 0);
---------------------------------------------------------------------------
-- keyboard event capture via ethernet
---------------------------------------------------------------------------
eth_keycode_toggle : in std_logic;
eth_keycode : in unsigned(15 downto 0)
);
end component;
component framepacker is
port (
pixelclock : in std_logic;
ioclock : in std_logic;
hypervisor_mode : in std_logic;
pixel_stream_in : in unsigned (7 downto 0);
pixel_y : in unsigned (11 downto 0);
pixel_valid : in std_logic;
pixel_newframe : in std_logic;
pixel_newraster : in std_logic;
-- Signals for ethernet controller
buffer_moby_toggle : out std_logic := '0';
buffer_address : in unsigned(11 downto 0);
buffer_rdata : out unsigned(7 downto 0);
---------------------------------------------------------------------------
-- fast IO port (clocked at CPU clock).
---------------------------------------------------------------------------
fastio_addr : in unsigned(19 downto 0);
fastio_write : in std_logic;
fastio_read : in std_logic;
fastio_wdata : in unsigned(7 downto 0);
fastio_rdata : out unsigned(7 downto 0)
);
end component;
component farcallstack IS
PORT (
-- CPU fastio port
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-- CPU parallel push/pop port
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
end component;
signal kickstartcs : std_logic;
signal reset_high : std_logic;
signal clock50hz : std_logic := '1';
constant divisor50hz : integer := 640000; -- 64MHz/50Hz/2;
signal counter50hz : integer := 0;
signal cia1cs : std_logic;
signal cia2cs : std_logic;
signal sectorbuffercs : std_logic;
signal sector_buffer_mapped_read : std_logic;
signal farcallstackcs : std_logic;
signal farcallstack_w : std_logic;
signal farcallstack_wdata : std_logic_vector(63 downto 0);
signal farcallstack_rdata : std_logic_vector(63 downto 0);
signal last_scan_code : std_logic_vector(12 downto 0);
signal cia1porta_out : std_logic_vector(7 downto 0);
signal cia1porta_in : std_logic_vector(7 downto 0);
signal cia1portb_out : std_logic_vector(7 downto 0);
signal cia1portb_in : std_logic_vector(7 downto 0);
signal leftsid_cs : std_logic;
signal leftsid_audio : unsigned(17 downto 0);
signal rightsid_cs : std_logic;
signal rightsid_audio : unsigned(17 downto 0);
signal spare_bits : unsigned(4 downto 0);
signal buffer_moby_toggle : std_logic;
signal buffer_address : unsigned(11 downto 0);
signal buffer_rdata : unsigned(7 downto 0);
signal eth_keycode_toggle : std_logic;
signal eth_keycode : unsigned(15 downto 0);
begin
kickstartrom : kickstart port map (
clk => clk,
address => address(13 downto 0),
we => w,
cs => kickstartcs,
data_i => data_i,
data_o => data_o);
framepacker0: framepacker port map (
ioclock => clk,
pixelclock => pixelclk,
hypervisor_mode => cpu_hypervisor_mode,
pixel_stream_in => pixel_stream_in,
pixel_y => pixel_y,
pixel_valid => pixel_valid,
pixel_newframe => pixel_newframe,
pixel_newraster => pixel_newraster,
buffer_moby_toggle => buffer_moby_toggle,
buffer_address => buffer_address,
buffer_rdata => buffer_rdata,
fastio_addr => unsigned(address(19 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_read => r,
fastio_wdata => unsigned(data_i)
);
cia1: cia6526 port map (
cpuclock => clk,
phi0 => phi0,
todclock => clock50hz,
reset => reset,
irq => irq,
reg_isr_out => reg_isr_out,
imask_ta_out => imask_ta_out,
cs => cia1cs,
fastio_address => unsigned(address(7 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_wdata => unsigned(data_i),
portaout => cia1porta_out,
portbout => cia1portb_out,
portain => cia1porta_in,
portbin => cia1portb_in,
flagin => '1',
spin => '1',
countin => '1'
);
cia2two: cia6526 port map (
cpuclock => clk,
phi0 => phi0,
todclock => clock50hz,
reset => reset,
irq => nmi,
cs => cia2cs,
fastio_address => unsigned(address(7 downto 0)),
fastio_write => w,
std_logic_vector(fastio_rdata) => data_o,
fastio_wdata => unsigned(data_i),
-- CIA ports not connected by default
portbin => x"ff",
portain => x"ff",
flagin => '1',
spin => '1',
countin => '1'
);
keymapper0 : keymapper port map (
pixelclk => clk,
nmi => restore_nmi,
reset => reset_out,
ps2clock => ps2clock,
ps2data => ps2data,
last_scan_code => last_scan_code,
-- key_status => seg_led(1 downto 0),
porta_in => cia1porta_out,
portb_in => cia1portb_out,
porta_out => cia1porta_in,
portb_out => cia1portb_in,
-- remote keyboard input via ethernet
-- eth_keycode_toggle => eth_keycode_toggle,
-- eth_keycode => eth_keycode
-- remote
eth_keycode_toggle => key_scancode_toggle,
eth_keycode => key_scancode
);
leftsid: sid6581 port map (
clk_1MHz => phi0,
clk32 => clk,
reset => reset_high,
cs => leftsid_cs,
we => w,
addr => unsigned(address(4 downto 0)),
di => unsigned(data_i),
std_logic_vector(do) => data_o,
pot_x => x"01",
pot_y => x"02",
audio_data => leftsid_audio);
rightsid: sid6581 port map (
clk_1MHz => phi0,
clk32 => clk,
reset => reset_high,
cs => rightsid_cs,
we => w,
addr => unsigned(address(4 downto 0)),
di => unsigned(data_i),
std_logic_vector(do) => data_o,
pot_x => x"03",
pot_y => x"04",
audio_data => rightsid_audio);
ethernet0 : ethernet port map (
clock50mhz => clock50mhz,
clock => clk,
reset => reset,
irq => irq,
---------------------------------------------------------------------------
-- IO lines to the ethernet controller
---------------------------------------------------------------------------
eth_mdio => eth_mdio,
eth_mdc => eth_mdc,
eth_reset => eth_reset,
eth_rxd => eth_rxd,
eth_txd => eth_txd,
eth_txen => eth_txen,
eth_rxdv => eth_rxdv,
eth_rxer => eth_rxer,
eth_interrupt => eth_interrupt,
buffer_moby_toggle => buffer_moby_toggle,
buffer_address => buffer_address,
buffer_rdata => buffer_rdata,
eth_keycode_toggle => eth_keycode_toggle,
eth_keycode => eth_keycode,
fastio_addr => unsigned(address),
fastio_write => w,
fastio_read => r,
fastio_wdata => unsigned(data_i),
std_logic_vector(fastio_rdata) => data_o
);
sdcard0 : sdcardio port map (
pixelclk => pixelclk,
clock => clk,
reset => reset,
fastio_addr => unsigned(address),
fastio_write => w,
fastio_read => r,
fastio_wdata => unsigned(data_i),
std_logic_vector(fastio_rdata) => data_o,
colourram_at_dc00 => colourram_at_dc00,
viciii_iomode => viciii_iomode,
sectorbuffermapped => sector_buffer_mapped,
sectorbuffermapped2 => sector_buffer_mapped_read,
sectorbuffercs => sectorbuffercs,
led => led,
motor => motor,
sw => sw,
btn => btn,
cs_bo => cs_bo,
sclk_o => sclk_o,
mosi_o => mosi_o,
miso_i => miso_i,
aclMISO => aclMISO,
aclMOSI => aclMOSI,
aclSS => aclSS,
aclSCK => aclSCK,
aclInt1 => aclInt1,
aclInt2 => aclInt2,
micData => micData,
micClk => micClk,
micLRSel => micLRSel,
leftsid_audio => leftsid_audio,
rightsid_audio => rightsid_audio,
ampSD => ampSD,
ampPWM => ampPWM,
tmpSDA => tmpSDA,
tmpSCL => tmpSCL,
tmpInt => tmpInt,
tmpCT => tmpCT,
QspiSCK => QspiSCK,
QspiDB => QspiDB,
QspiCSn => QspiCSn,
last_scan_code => last_scan_code
);
farcallstack0: farcallstack port map (
clka => clk,
ena => farcallstackcs,
wea(0) => w,
addra => address(11 downto 0),
dina => data_i,
douta => data_o,
clkb => cpuclock,
web(0) => farcallstack_w,
addrb => farcallstack_addr,
dinb => farcallstack_wdata,
doutb => farcallstack_rdata
);
process(reset)
begin
reset_high <= not reset;
end process;
process(clk)
begin
if rising_edge(clk) then
-- Generate 50Hz signal for TOD clock
-- (Note that we are a bit conflicted here, as our video mode is PALx4,
-- but at 60Hz. We will make our CIAs take 50Hz like in most PAL countries
-- so that we don't confuse things too much. We will probably add a 50Hz
-- raster interrupt filter to help music and games play at the right rate.)
if counter50hz<divisor50hz then
counter50hz <= counter50hz + 1;
else
clock50hz <= not clock50hz;
counter50hz <= 0;
end if;
seg_led(12) <= eth_keycode_toggle;
seg_led(11) <= last_scan_code(12);
seg_led(10 downto 0) <= unsigned(last_scan_code(10 downto 0));
end if;
end process;
process (r,w,address,cia1portb_in,cia1porta_out,colourram_at_dc00,
sector_buffer_mapped_read)
begin -- process
if (r or w) = '1' then
-- @IO:GS $FFF8000-$FFFBFFF 16KB Kickstart/hypervisor ROM
-- @IO:GS $FFF8000 Hypervisor entry point when $D67F is written
if address(19 downto 14)&"00" = x"F8" then
kickstartcs <= cpu_hypervisor_mode;
else
kickstartcs <='0';
end if;
-- @IO:GS $FFF0000-$FFF0FFF - CPU far call stack (512x8 byte entries)
if address(19 downto 12) = x"F0" then
farcallstackcs <= '1';
else
farcallstackcs <= '0';
end if;
-- sdcard sector buffer: only mapped if no colour ram @ $DC00, and if
-- the sectorbuffer mapping flag is set
sectorbuffercs <= '0';
report "fastio address = $" & to_hstring(address) severity note;
if address(19 downto 16) = x"D"
and address(15 downto 14) = "00"
and address(11 downto 9)&'0' = x"E"
and sector_buffer_mapped_read = '1' and colourram_at_dc00 = '0' then
sectorbuffercs <= '1';
report "selecting SD card sector buffer" severity note;
end if;
-- Also map SD card sector buffer at $FFD6000 - $FFD61FF regardless of
-- VIC-IV IO mode and mapping of colour RAM
if address(19 downto 8) = x"D60" or address(19 downto 8) = x"D61" then
sectorbuffercs <= '1';
end if;
-- Now map the SIDs
-- @IO:C64 $D440-$D47F = left SID
-- @IO:C64 $D400-$D43F = right SID
-- @IO:C64 $D480-$D4FF = repeated images of SIDs
-- Presumably repeated through to $D5FF. But we will repeat to $D4FF only
-- so that we can use $D500-$D5FF for other stuff.
case address(19 downto 8) is
when x"D04" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D14" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D24" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when x"D34" => leftsid_cs <= address(6); rightsid_cs <= not address(6);
when others => leftsid_cs <= '0'; rightsid_cs <= '0';
end case;
-- $D500 - $D5FF is not currently used. Probably use some for FPU.
-- $D600 - $D60F is reserved for 6551 serial UART emulation for C65
-- compatibility (6551 actually only has 4 registers).
-- 6551 is not currently implemented, so this is just unmapped for now,
-- except for any read values required to allow the C65 ROM to function.
-- Hypervisor control (only visible from hypervisor mode) $D640 - $D67F
-- The hypervisor is a CPU provided function.
-- SD controller and miscellaneous hardware (microphone, accelerometer etc)
-- uses $D680 - $D6FF
-- CPU uses $FFD{0,1,2,3}700 for DMAgic and other CPU-hosted IO registers.
-- Now map the CIAs.
-- These are a bit fun, because they only get mapped if colour RAM isn't
-- being mapped in $DC00-$DFFF using the C65 2K colour ram register
cia1cs <='0';
cia2cs <='0';
if colourram_at_dc00='0' and sector_buffer_mapped_read='0' then
case address(19 downto 8) is
when x"D0C" => cia1cs <='1';
when x"D1C" => cia1cs <='1';
when x"D2C" => cia1cs <='1';
when x"D3C" => cia1cs <='1';
when x"D0D" => cia2cs <='1';
when x"D1D" => cia2cs <='1';
when x"D2D" => cia2cs <='1';
when x"D3D" => cia2cs <='1';
when others => null;
end case;
end if;
else
cia1cs <= '0';
cia2cs <= '0';
kickstartcs <= '0';
sectorbuffercs <= '0';
leftsid_cs <= '0';
rightsid_cs <= '0';
farcallstackcs <= '0';
end if;
end process;
end behavioral;
|
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use work.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------------
--FPGA to DMC16207 LCD interface. Takes care of inititation and after that sits
--ready to take commands from the top module to print, clear or row-change.
-------------------------------------------------------------------------------
entity LCD is
Generic ( Frequency : integer); --Needs to know the frequency the curcuit is running at
Port (INPUT : in STD_LOGIC_VECTOR (7 downto 0); --ASCII IN
CLK : in STD_LOGIC; --FPGA Clock (100MHz)
RESET : in STD_LOGIC; --RESET
DATA_BUS : out STD_LOGIC_VECTOR (7 downto 0);--DB 7 downto DB 0
RW : out STD_LOGIC := '0'; --RW signal (unused as of now)
RS : out STD_LOGIC; --RS signal
E : out STD_LOGIC; --E (200Hz)
MODE_SELECT : in STD_LOGIC_VECTOR (1 downto 0); --Select cmd to be done
RDY_CMD : out STD_LOGIC := '0'; --Ready for cmd from top module
DO_CMD : in STD_LOGIC); --Cmd to be done from top module
end LCD;
architecture Behaviour of LCD is
Signal INPUT_2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
Signal clock_div_1, clock_div_2: unsigned (7 downto 0) := (others => '0');
Signal clock_div_3, init_state : unsigned (3 downto 0) := (others => '0');
Signal E_toggle, e_step : STD_LOGIC := '0';
constant Clock_cutoff : integer := Frequency/800;
Signal Clock_div : integer range 0 to Frequency/800 := 0;
begin
-------------------------------------CLOCK DIVIDER----------------------------
--Divides a clock from FREQ to 400Hz
------------------------------------------------------------------------------
clock_divider: process (clk)
begin
if rising_edge(clk) then
if RESET = '1' then
Clock_div <= 0;
E_toggle <= '0';
else
if Clock_div < Clock_cutoff then --Inc the counter
Clock_div <= Clock_div + 1;
else --Happens at a frequency of 800Hz
Clock_div <= 0;
E_toggle <= NOT E_toggle; --As this is the inverse of the previous signal, the E_toggle is at 400Hz
end if;
end if;
end if;
end process;
---------------------------------State and Data changes------------------------
--Happens on high flank as on E low flank the action will be executed. Switches
--between having the E 1 and 0 each high flank of E_toggle, and is as such half
--the frequency of E_toggle (200Hz).
-------------------------------------------------------------------------------
E_process: process (E_toggle)
begin
if rising_edge(E_toggle) then
if e_step = '0' then
---------------------------------------------------Initilazion takes 8 E-cycles
if init_state < 8 then
init_state <= init_state + 1;
e_step <= '1';
case init_state is
when x"4" => --Display OFF
RS <= '0';
RW <= '0';
DATA_BUS <= "00001000";
when x"5" => --Clear Display
RS <= '0';
RW <= '0';
DATA_BUS <= "00000001";
when x"6" => --Entry Mode Set
RS <= '0';
RW <= '0';
DATA_BUS <= "00000110";
when x"7" => --Display ON (Blink and Cursor ON)
RS <= '0';
RW <= '0';
DATA_BUS <= "00001111";
RDY_CMD <= '1';
when others => --Function set command (step 0,1,2,3)
RS <= '0';
RW <= '0';
DATA_BUS <= "00111100";
end case;
-----------------------------------------------------Normal operation selection
elsif DO_CMD = '1' then
e_step <= '1';
RDY_CMD <= '0';
case MODE_SELECT is
when "00" => --CLEAR DISPAY
RS <= '0';
RW <= '0';
DATA_BUS <= "00000001";
when "01" => --Print INPUT on DISPLAY
RS <= '1';
RW <= '0';
DATA_BUS <= INPUT;
if INPUT = "00000000" then --if char is '\0', don't print it
e_step <= '0';
end if;
when "10" => --CHANGE ROW
RS <= '0';
RW <= '0';
DATA_BUS <= "11000000";
when others => --CLEAR DISPLAY
RS <= '0';
RW <= '0';
DATA_BUS <= "00000001";
end case;
else --Because we don't print '\0' we have to reset RDY_CMD here
RDY_CMD <= '1';
end if;
else
e_step <= '0';
RDY_CMD <= '1';
end if;
E <= e_step;
end if;
end process E_process;
end architecture; |
architecture RTL of FIFO is
begin
process
begin
for_label : for index in 4 to 23 loop
end loop;
for_label : for index in 4 to 23 loop
end loop;
for_label : for index in 4 to 23 loop
end loop;
end process;
end;
|
ENTITY insertionsort IS
-- empty
END insertionsort;
ARCHITECTURE verhalten OF insertionsort IS
TYPE string IS array(natural RANGE <>) OF character;
BEGIN
PROCESS
CONSTANT N: natural := 20;
VARIABLE a: string(0 TO N-1) := "P91fQeZB4KvTMcrEfzM4";
VARIABLE b: string(0 TO N-1) := "1449BEKMMPQTZceffrvz";
VARIABLE c: string(0 TO N-1) := "zvrffecZTQPMMKEB9441";
PROCEDURE sort(a: INOUT string; n: positive) IS
VARIABLE key: character;
VARIABLE j: integer;
BEGIN
FOR i IN 1 TO n-1 LOOP
key := a(i);
j := i-1;
WHILE j >= 0 LOOP
IF a(j) <= key THEN
EXIT;
END IF;
a(j+1) := a(j);
j := j - 1;
END LOOP;
a(j+1) := key;
END LOOP;
END PROCEDURE;
BEGIN
sort(a, n);
sort(b, n);
sort(c, n);
WAIT;
END PROCESS;
END verhalten; |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net7
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net7,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net8,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_fetch is
Port( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
PC_OP : in std_logic_vector( 2 downto 0);
JDATA : in std_logic_vector(15 downto 0);
RR : in std_logic_vector(15 downto 0);
RDATA : in std_logic_vector( 7 downto 0);
PC : out std_logic_vector(15 downto 0)
);
end opcode_fetch;
architecture Behavioral of opcode_fetch is
signal LPC : std_logic_vector(15 downto 0);
signal LRET : std_logic_vector( 7 downto 0);
begin
PC <= LPC;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CLR = '1') then LPC <= X"0000";
elsif (CE = '1') then
case PC_OP is
when PC_NEXT => LPC <= LPC + 1; -- next address
when PC_JMP => LPC <= JDATA; -- jump address
when PC_RETL => LRET <= RDATA; -- return address L
LPC <= LPC + 1;
when PC_RETH => LPC <= RDATA & LRET; -- return address H
when PC_JPRR => LPC <= RR;
when PC_WAIT =>
when others => LPC <= X"0008"; -- interrupt
end case;
end if;
end if;
end if;
end process;
end Behavioral;
|
package data_bus_pkg is
type data_bus_device_t is (
DEV_NONE
,DEV_PIO
,DEV_SPI
,DEV_AIC
,DEV_UART0
,DEV_UART1
,DEV_UARTGPS
,DEV_SRAM
,DEV_DDR
,DEV_BL0
,DEV_EMAC
,DEV_I2C
);
type ext_bus_device_t is (
DEV_BL0,
DEV_EMAC,
DEV_I2C,
DEV_DDR
);
type ext_to_int_data_bus_t is array(ext_bus_device_t'left to ext_bus_device_t'right) of data_bus_device_t;
-- arrays for mapping mcu_lib's data bus and irq ports to the internal versions
constant ext_to_int_data : ext_to_int_data_bus_t := (
DEV_BL0 => DEV_BL0,
DEV_EMAC => DEV_EMAC,
DEV_I2C => DEV_I2C,
DEV_DDR => DEV_NONE
);
end data_bus_pkg;
-------------------------------------------------------------------------------
package monitor_pkg is
type timeout_t is record
cnt : integer range 0 to 10;
end record;
type cnt_reg_t is record
a : bit;
cnt : integer range 0 to 10;
end record;
constant CNT_REG_RESET : cnt_reg_t := ('0',0);
end package;
-------------------------------------------------------------------------------
use work.monitor_pkg.all;
entity timeout_cnt is
port(
clk : in bit;
rst : in bit;
timeout : out timeout_t
);
end timeout_cnt;
architecture structure of timeout_cnt is
signal this_c : cnt_reg_t;
signal this_r : cnt_reg_t := CNT_REG_RESET;
begin
counter_r0 : process(clk, rst)
begin
if rst = '1' then
this_r <= CNT_REG_RESET;
elsif clk = '1' and clk'event then
report integer'image(this_c.cnt);
this_c.cnt <= this_c.cnt + 1;
this_r <= this_c;
end if;
end process;
timeout.cnt <= this_r.cnt;
end structure;
-------------------------------------------------------------------------------
use work.monitor_pkg.all;
use work.data_bus_pkg.all;
entity jcore2 is
end;
architecture behaviour of jcore2 is
signal clk : bit := '1';
signal rst : bit := '1';
signal timeout : timeout_t;
begin
timeout_cnt_i: entity work.timeout_cnt
port map(clk => clk, rst => rst,
timeout => timeout);
process is
begin
wait for 1 ns;
assert timeout.cnt = 0;
rst <= '0';
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert timeout.cnt = 1;
wait;
end process;
end;
|
package data_bus_pkg is
type data_bus_device_t is (
DEV_NONE
,DEV_PIO
,DEV_SPI
,DEV_AIC
,DEV_UART0
,DEV_UART1
,DEV_UARTGPS
,DEV_SRAM
,DEV_DDR
,DEV_BL0
,DEV_EMAC
,DEV_I2C
);
type ext_bus_device_t is (
DEV_BL0,
DEV_EMAC,
DEV_I2C,
DEV_DDR
);
type ext_to_int_data_bus_t is array(ext_bus_device_t'left to ext_bus_device_t'right) of data_bus_device_t;
-- arrays for mapping mcu_lib's data bus and irq ports to the internal versions
constant ext_to_int_data : ext_to_int_data_bus_t := (
DEV_BL0 => DEV_BL0,
DEV_EMAC => DEV_EMAC,
DEV_I2C => DEV_I2C,
DEV_DDR => DEV_NONE
);
end data_bus_pkg;
-------------------------------------------------------------------------------
package monitor_pkg is
type timeout_t is record
cnt : integer range 0 to 10;
end record;
type cnt_reg_t is record
a : bit;
cnt : integer range 0 to 10;
end record;
constant CNT_REG_RESET : cnt_reg_t := ('0',0);
end package;
-------------------------------------------------------------------------------
use work.monitor_pkg.all;
entity timeout_cnt is
port(
clk : in bit;
rst : in bit;
timeout : out timeout_t
);
end timeout_cnt;
architecture structure of timeout_cnt is
signal this_c : cnt_reg_t;
signal this_r : cnt_reg_t := CNT_REG_RESET;
begin
counter_r0 : process(clk, rst)
begin
if rst = '1' then
this_r <= CNT_REG_RESET;
elsif clk = '1' and clk'event then
report integer'image(this_c.cnt);
this_c.cnt <= this_c.cnt + 1;
this_r <= this_c;
end if;
end process;
timeout.cnt <= this_r.cnt;
end structure;
-------------------------------------------------------------------------------
use work.monitor_pkg.all;
use work.data_bus_pkg.all;
entity jcore2 is
end;
architecture behaviour of jcore2 is
signal clk : bit := '1';
signal rst : bit := '1';
signal timeout : timeout_t;
begin
timeout_cnt_i: entity work.timeout_cnt
port map(clk => clk, rst => rst,
timeout => timeout);
process is
begin
wait for 1 ns;
assert timeout.cnt = 0;
rst <= '0';
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert timeout.cnt = 1;
wait;
end process;
end;
|
package data_bus_pkg is
type data_bus_device_t is (
DEV_NONE
,DEV_PIO
,DEV_SPI
,DEV_AIC
,DEV_UART0
,DEV_UART1
,DEV_UARTGPS
,DEV_SRAM
,DEV_DDR
,DEV_BL0
,DEV_EMAC
,DEV_I2C
);
type ext_bus_device_t is (
DEV_BL0,
DEV_EMAC,
DEV_I2C,
DEV_DDR
);
type ext_to_int_data_bus_t is array(ext_bus_device_t'left to ext_bus_device_t'right) of data_bus_device_t;
-- arrays for mapping mcu_lib's data bus and irq ports to the internal versions
constant ext_to_int_data : ext_to_int_data_bus_t := (
DEV_BL0 => DEV_BL0,
DEV_EMAC => DEV_EMAC,
DEV_I2C => DEV_I2C,
DEV_DDR => DEV_NONE
);
end data_bus_pkg;
-------------------------------------------------------------------------------
package monitor_pkg is
type timeout_t is record
cnt : integer range 0 to 10;
end record;
type cnt_reg_t is record
a : bit;
cnt : integer range 0 to 10;
end record;
constant CNT_REG_RESET : cnt_reg_t := ('0',0);
end package;
-------------------------------------------------------------------------------
use work.monitor_pkg.all;
entity timeout_cnt is
port(
clk : in bit;
rst : in bit;
timeout : out timeout_t
);
end timeout_cnt;
architecture structure of timeout_cnt is
signal this_c : cnt_reg_t;
signal this_r : cnt_reg_t := CNT_REG_RESET;
begin
counter_r0 : process(clk, rst)
begin
if rst = '1' then
this_r <= CNT_REG_RESET;
elsif clk = '1' and clk'event then
report integer'image(this_c.cnt);
this_c.cnt <= this_c.cnt + 1;
this_r <= this_c;
end if;
end process;
timeout.cnt <= this_r.cnt;
end structure;
-------------------------------------------------------------------------------
use work.monitor_pkg.all;
use work.data_bus_pkg.all;
entity jcore2 is
end;
architecture behaviour of jcore2 is
signal clk : bit := '1';
signal rst : bit := '1';
signal timeout : timeout_t;
begin
timeout_cnt_i: entity work.timeout_cnt
port map(clk => clk, rst => rst,
timeout => timeout);
process is
begin
wait for 1 ns;
assert timeout.cnt = 0;
rst <= '0';
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert timeout.cnt = 1;
wait;
end process;
end;
|
-------------------------------------------------------------------------------
-- Title : rmii_transceiver_tb
-- Author : Gideon Zweijtzer (gideon.zweijtzer@gmail.com)
-------------------------------------------------------------------------------
-- Description: Testbench for rmii transceiver
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity rmii_transceiver_tb is
end entity;
architecture testcase of rmii_transceiver_tb is
signal clock : std_logic := '0'; -- 50 MHz reference clock
signal reset : std_logic;
signal rmii_crs_dv : std_logic;
signal rmii_rxd : std_logic_vector(1 downto 0);
signal rmii_tx_en : std_logic;
signal rmii_txd : std_logic_vector(1 downto 0);
signal eth_rx_data : std_logic_vector(7 downto 0);
signal eth_rx_sof : std_logic;
signal eth_rx_eof : std_logic;
signal eth_rx_valid : std_logic;
signal eth_tx_data : std_logic_vector(7 downto 0);
signal eth_tx_sof : std_logic;
signal eth_tx_eof : std_logic;
signal eth_tx_valid : std_logic;
signal eth_tx_ready : std_logic;
signal ten_meg_mode : std_logic;
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant c_frame_with_crc : t_byte_array := (
X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12", X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11", X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C", X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E", X"0F", X"10", X"11", X"12", X"13"
-- , X"7A", X"D5", X"6B", X"B3"
);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.rmii_transceiver
port map (
clock => clock,
reset => reset,
rmii_crs_dv => rmii_crs_dv,
rmii_rxd => rmii_rxd,
rmii_tx_en => rmii_tx_en,
rmii_txd => rmii_txd,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_sof => eth_tx_sof,
eth_tx_eof => eth_tx_eof,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
ten_meg_mode => ten_meg_mode
);
rmii_crs_dv <= rmii_tx_en;
rmii_rxd <= rmii_txd;
test: process
variable i : natural;
begin
eth_tx_data <= X"00";
eth_tx_sof <= '0';
eth_tx_eof <= '0';
eth_tx_valid <= '0';
ten_meg_mode <= '0';
wait until reset = '0';
wait until clock = '1';
i := 0;
L1: loop
wait until clock = '1';
if eth_tx_valid = '0' or eth_tx_ready = '1' then
if eth_tx_eof = '1' then
eth_tx_valid <= '0';
eth_tx_data <= X"00";
exit L1;
else
eth_tx_data <= c_frame_with_crc(i);
eth_tx_valid <= '1';
if i = c_frame_with_crc'left then
eth_tx_sof <= '1';
else
eth_tx_sof <= '0';
end if;
if i = c_frame_with_crc'right then
eth_tx_eof <= '1';
else
eth_tx_eof <= '0';
end if;
i := i + 1;
end if;
end if;
end loop;
wait;
end process;
end architecture;
|
-- file: nregister.vhd
-------------------------------------
-- n bit register for use in carry save counter
-- Shauna Rae
-- October 4, 1999
library ieee;
use ieee.std_logic_1164.all;
-- component nregister is
-- generic (data_width : positive := 16);
--- port(clock, reset : in std_logic;
-- register_in: in std_logic_vector(data_width-1 downto 0);
-- register_out : out std_logic_vector(data_width-1 downto 0));
-- end component nregister;
--define the entity of nregister
entity nregister is
generic (data_width : positive := 16);
port(clock, reset: in std_logic;
register_in: in std_logic_vector(data_width-1 downto 0);
register_out: out std_logic_vector(data_width-1 downto 0));
end nregister;
architecture basic of nregister is
begin
--define a process that is dependent on reset and a clock
register_behaviour: process(clock, reset) is
begin
if reset = '0' then -- on reset zero the output
register_out <= (others => '0');
--on rising edge of clock set output to input
elsif rising_edge(clock) then
register_out <= register_in;
end if;
end process register_behaviour;
end basic; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity octaver_tb is
end octaver_tb;
architecture Behavioral of octaver_tb is
component octaver is
Port ( x : in STD_LOGIC_VECTOR(31 downto 0);
y : out STD_LOGIC_VECTOR(31 downto 0);
clk_48: in std_logic :='1';
clk_24: in std_logic;
options : in STD_LOGIC_VECTOR(0 to 3);
en : in STD_LOGIC_VECTOR(0 to 3);
addr1_temp0 : out std_logic_vector (31 downto 0);
addr2_temp1 : out std_logic_vector (31 downto 0)
);
end component;
signal x : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000";
signal y : STD_LOGIC_VECTOR(31 downto 0);
signal clk_48: std_logic := '1';
signal clk_24: std_logic;
signal options : STD_LOGIC_VECTOR(0 to 3) := "0000";
signal en : STD_LOGIC_VECTOR(0 to 3) := "0100";
signal addr1_temp0 : std_logic_vector (31 downto 0);
signal addr2_temp1 : std_logic_vector (31 downto 0);
-- signal del_temp2 : std_logic_vector (31 downto 0);
-- signal del_temp_last : std_logic_vector (31 downto 0);
constant clock_period: time := 20 us;
signal rand_num : integer := 0;
begin
uut: octaver
port map(
x => x,
y => y,
clk_48 => clk_48,
clk_24 => clk_24,
options => options,
en => en
--addr1_temp0 => addr1_temp0,
--addr2_temp1 => addr2_temp1
);
clk_process: process
begin
clk_48 <= '1';
wait for clock_period/2;
clk_48 <= '0';
wait for clock_period/2;
end process;
clk2_process: process
begin
clk_24 <= '1';
wait for clock_period;
clk_24 <= '0';
wait for clock_period;
end process;
process
begin
x <= std_logic_vector(signed(x)+1);
wait for clock_period;
end process;
--random_num: process
-- variable seed1, seed2: positive; -- seed values for random generator
-- variable rand: real; -- random real-number value in range 0 to 1.0
-- variable range_of_rand : real := 150000.0; -- the range of random values created will be 0 to +30000.
-- begin
-- uniform(seed1, seed2, rand); -- generate random number
-- rand_num <= integer(rand*range_of_rand); -- rescale to 0..1000, convert integer part
-- x <= std_logic_vector(to_unsigned(rand_num, 32));
-- wait for 0.000020 sec;
-- end process;
end Behavioral;
|
entity sub is
generic ( NUM : integer );
port ( s : in bit );
end entity;
architecture test of sub is
begin
process is
begin
wait for (NUM * 10 ns) + 1 ns;
assert s = '1';
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab17 is
end entity;
architecture test of elab17 is
signal vec : bit_vector(2 downto 0);
begin
gen: for i in 0 to 2 generate
signal s : bit;
begin
sub_i: entity work.sub
generic map ( i )
port map ( vec(i) );
end generate;
process is
begin
vec <= "001";
wait for 10 ns;
vec <= "010";
wait for 10 ns;
vec <= "100";
wait for 10 ns;
wait;
end process;
end architecture;
|
entity sub is
generic ( NUM : integer );
port ( s : in bit );
end entity;
architecture test of sub is
begin
process is
begin
wait for (NUM * 10 ns) + 1 ns;
assert s = '1';
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab17 is
end entity;
architecture test of elab17 is
signal vec : bit_vector(2 downto 0);
begin
gen: for i in 0 to 2 generate
signal s : bit;
begin
sub_i: entity work.sub
generic map ( i )
port map ( vec(i) );
end generate;
process is
begin
vec <= "001";
wait for 10 ns;
vec <= "010";
wait for 10 ns;
vec <= "100";
wait for 10 ns;
wait;
end process;
end architecture;
|
entity sub is
generic ( NUM : integer );
port ( s : in bit );
end entity;
architecture test of sub is
begin
process is
begin
wait for (NUM * 10 ns) + 1 ns;
assert s = '1';
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab17 is
end entity;
architecture test of elab17 is
signal vec : bit_vector(2 downto 0);
begin
gen: for i in 0 to 2 generate
signal s : bit;
begin
sub_i: entity work.sub
generic map ( i )
port map ( vec(i) );
end generate;
process is
begin
vec <= "001";
wait for 10 ns;
vec <= "010";
wait for 10 ns;
vec <= "100";
wait for 10 ns;
wait;
end process;
end architecture;
|
entity sub is
generic ( NUM : integer );
port ( s : in bit );
end entity;
architecture test of sub is
begin
process is
begin
wait for (NUM * 10 ns) + 1 ns;
assert s = '1';
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab17 is
end entity;
architecture test of elab17 is
signal vec : bit_vector(2 downto 0);
begin
gen: for i in 0 to 2 generate
signal s : bit;
begin
sub_i: entity work.sub
generic map ( i )
port map ( vec(i) );
end generate;
process is
begin
vec <= "001";
wait for 10 ns;
vec <= "010";
wait for 10 ns;
vec <= "100";
wait for 10 ns;
wait;
end process;
end architecture;
|
entity sub is
generic ( NUM : integer );
port ( s : in bit );
end entity;
architecture test of sub is
begin
process is
begin
wait for (NUM * 10 ns) + 1 ns;
assert s = '1';
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab17 is
end entity;
architecture test of elab17 is
signal vec : bit_vector(2 downto 0);
begin
gen: for i in 0 to 2 generate
signal s : bit;
begin
sub_i: entity work.sub
generic map ( i )
port map ( vec(i) );
end generate;
process is
begin
vec <= "001";
wait for 10 ns;
vec <= "010";
wait for 10 ns;
vec <= "100";
wait for 10 ns;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
entity circular_queue_tb is
end;
architecture behavioural of circular_queue_tb is
constant queue_depth : integer := 2;
signal ctrl : ctrl_t;
signal enqueue : std_logic := '0';
signal dequeue : std_logic := '0';
signal write_in_data : std_logic_vector(7 downto 0) := (others => '0');
signal read_out_data : std_logic_vector(7 downto 0);
signal empty : std_logic;
signal full : std_logic;
signal contents_count : natural range 0 to queue_depth + 1;
begin
circular_queue_1 : entity work.circular_queue
generic map (
queue_depth => queue_depth,
queue_width => 8
)
port map (
ctrl => ctrl,
enqueue => enqueue,
dequeue => dequeue,
write_in_data => write_in_data,
read_out_data => read_out_data,
empty => empty,
full => full,
contents_count => contents_count);
-- Clock process definitions
clk_process : process
begin
ctrl.clk <= '0';
wait for clk_period/2;
ctrl.clk <= '1';
wait for clk_period/2;
end process;
stim_proc : process
procedure write_item(value : in integer) is
begin
write_in_data <= std_logic_vector(to_unsigned(value, 8));
wait until falling_edge(ctrl.clk);
enqueue <= '1';
wait until falling_edge(ctrl.clk);
enqueue <= '0';
wait until falling_edge(ctrl.clk);
end;
procedure dequeue_item is
begin
dequeue <= '1';
wait until falling_edge(ctrl.clk);
dequeue <= '0';
wait until falling_edge(ctrl.clk);
end;
begin
ctrl.reset_n <= '0';
wait for 1 ms;
-- Check reset values
assert empty = '1' report "empty reset value fail";
assert full = '0' report "full reset value fail";
assert contents_count = 0 report "contents_count reset value fail";
ctrl.reset_n <= '1';
wait for 1 us;
-- Check empty and full when there is no data.
assert empty = '1' report "empty fail after reset deassert";
assert full = '0' report "full fail after reset deassert";
assert contents_count = 0 report "contents_count fail after reset deassert";
-- Now add an item. Check that the queue is neither empty nor full.
-- Also check that read_out_data is showing the same item.
write_item(1);
assert empty = '0' report "empty fail after single item added";
assert full = '0' report "full fail after single item added";
assert read_out_data = write_in_data report "read_out_data is not equal to write_in_data after first item added";
assert contents_count = 1 report "contents_count fail after single item added";
-- Add another item. Check that full is asserted and that read_out_data has
-- not changed this time.
write_item(2);
assert empty = '0' report "empty fail when fifo should be full";
assert full = '1' report "full fail when fifo is full";
assert read_out_data = std_logic_vector(to_unsigned(1, 8));
assert contents_count = 2 report "contents_count fail when fifo is full";
-- Now to check that nothing happens, attempt to write a third value. the
-- first item will be dequeued and we will check that the third value is
-- not beign displayed.
write_item(3);
assert empty = '0' report "empty fail after writing to full queue";
assert full = '1' report "full fail after writing to full queue";
assert contents_count = 2 report "contents_count fail after writing to full queue";
dequeue_item;
assert empty = '0' report "empty fail after dequeueing full queue";
assert full = '0' report "full fail after dequeueing full queue";
assert read_out_data = std_logic_vector(to_unsigned(2, 8));
assert contents_count = 1 report "contents_count fail after dequeueing full queue";
-- Now dequeue the final item. Check that the queue is empty again.
dequeue_item;
assert empty = '1' report "empty fail after emptying the queue";
assert full = '0' report "full fail after emptying the queue";
assert contents_count = 0 report "contents_count fail after emptying the queueue";
-- Check that empty and full do not change when dequeueing an empty queue
dequeue_item;
assert empty = '1' report "empty fail after dequeueing an empty queue";
assert full = '0' report "full fail after dequeueing an empty queue";
assert contents_count = 0 report "contents_count fail after dequeueing and empty queue";
assert false severity failure;
wait;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
--err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out,
--err_valid_in_state_out_state_in_not_change,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
--err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
--err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
--err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic
--err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change
--err_state_out_invalid_state_in_state_out_not_change,
--err_state_out_invalid_not_fault_info,
--err_state_out_invalid_not_health_info,
--err_state_out_invalid_not_fake_credit,
--err_state_out_invalid_not_write_fake_flit,
--err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change: out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--signal read_en_signal: std_logic;
begin
--read_en_signal <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty_out;
-- Functional Checkers (Might cover or be covered by some of the structural checkers)
-- Empty and full cannot be high at the same time!
process (empty_out, full_out)
begin
if (empty_out = '1' and full_out = '1') then
err_empty_full <= '1';
else
err_empty_full <= '0';
end if;
end process;
-- Reading from an empty FIFO is not possible!
process (empty_out, read_en_out)
begin
if (empty_out = '1' and read_en_out = '1') then
err_empty_read_en <= '1';
else
err_empty_read_en <= '0';
end if;
end process;
-- Writing to a full FIFO is not possible!
process (full_out, write_en_out)
begin
if (full_out = '1' and write_en_out = '1') then
err_full_write_en <= '1';
else
err_full_write_en <= '0';
end if;
end process;
-- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)!
process (state_in)
begin
if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Read pointer must always be one-hot!
process (read_pointer_in)
begin
if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then
err_read_pointer_in_onehot <= '1';
else
err_read_pointer_in_onehot <= '0';
end if;
end process;
-- Write pointer must always be one-hot!
process (write_pointer_in)
begin
if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then
err_write_pointer_in_onehot <= '1';
else
err_write_pointer_in_onehot <= '0';
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- Structural Checkers
-- Write pointer and Read pointer checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
-- Checked !
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
-- Updated !
process (valid_in, write_en_out)
begin
if (valid_in = '0' and write_en_out = '1') then
err_not_write_en <= '1';
else
err_not_write_en <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then
err_not_write_en1 <= '1';
else
err_not_write_en1 <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then
err_not_write_en2 <= '1';
else
err_not_write_en2 <= '0';
end if;
end process;
-- Updated !
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then
err_read_en_mismatch1 <= '1';
else
err_read_en_mismatch1 <= '0';
end if;
end process;
-- Newly added checkers for FIFO with packet drop and fault classifier support!
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then
err_fake_credit_read_en_fake_credit_counter_in_increment <= '1';
else
err_fake_credit_read_en_fake_credit_counter_in_increment <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1';
else
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, credit_out)
begin
if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then
err_fake_credit_read_en_credit_out <= '1';
else
err_fake_credit_read_en_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0';
end if;
end process;
--process (fake_credit, read_en_out, credit_out)
--begin
-- if (fake_credit = '1' and read_en_out = '1' and credit_out = '1') then
-- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '1';
-- else
-- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '0';
-- end if;
--end process;
-- Checkers for Packet Dropping FSM of FIFO
--process (valid_in, state_out, state_in)
--begin
-- if (valid_in = '0' and (state_out = Idle or state_out = Header_flit or state_out = Body_flit or state_out = Packet_drop) and state_in /= state_out) then
-- err_valid_in_state_out_state_in_not_change <= '1';
-- else
-- err_valid_in_state_out_state_in_not_change <= '0';
-- end if;
--end process;
-- Idle state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, valid_in, state_in)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, fault_out, valid_in, state_in, state_out)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0';
end if;
end process;
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '0' and fake_credit = '1') then
err_state_out_Idle_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Idle_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, fault_info)
begin
if (state_out = Idle and fault_out = '0' and fault_info = '1') then
err_state_out_Idle_not_fault_out_not_fault_info <= '1';
else
err_state_out_Idle_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '1' and fake_credit = '0') then
err_state_out_Idle_fault_out_fake_credit <= '1';
else
err_state_out_Idle_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, state_in)
begin
if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Idle_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Idle_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, fault_out, fault_info)
begin
if (state_out = Idle and fault_out = '1' and fault_info = '0') then
err_state_out_Idle_fault_out_fault_info <= '1';
else
err_state_out_Idle_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in)
begin
if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Idle_fault_out_faulty_packet_in <= '1';
else
err_state_out_Idle_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Idle and write_fake_flit = '1') then
err_state_out_Idle_not_write_fake_flit <= '1';
else
err_state_out_Idle_not_write_fake_flit <= '0';
end if;
end process;
-- Other properties for Idle state
--------------------------------------------------------------------------------------------------
process (state_out, health_info)
begin
if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then
err_state_out_Idle_not_health_info <= '1';
else
err_state_out_Idle_not_health_info <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Header_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then
-- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Header_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in, state_out)
begin
if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Header_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Header_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Header_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1';
else
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Body_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, health_info)
begin
if (state_out = Body_flit and valid_in = '0' and health_info = '1') then
err_state_out_Body_flit_valid_in_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_health_info <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then
-- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Body_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Body_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Body_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Body_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if (state_out = Body_flit and fake_credit = '1') then
err_state_out_Body_flit_not_fake_credit <= '1';
else
err_state_out_Body_flit_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Tail_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then
-- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1';
else
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1';
else
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Tail_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Tail_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Tail_flit and write_fake_flit = '1') then
err_state_out_Tail_flit_not_write_fake_flit <= '1';
else
err_state_out_Tail_flit_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Packet_drop state
-- faulty_packet_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0';
end if;
end process;
-- faulty_packet_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, fault_info)
begin
if (state_out = Packet_drop and fault_info = '1') then
err_state_out_Packet_drop_not_fault_info <= '1';
else
err_state_out_Packet_drop_not_fault_info <= '0';
end if;
end process;
process (state_out, faulty_packet_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0';
end if;
end process;
--process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
--begin
-- if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
-- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '0';
-- end if;
--end process;
-- Invalid state
--process (state_out, state_in)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and state_in /= state_out) then
-- err_state_out_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
--process (state_out, fault_info)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fault_info = '1') then
-- err_state_out_invalid_not_fault_info <= '1';
-- else
-- err_state_out_invalid_not_fault_info <= '0';
-- end if;
--end process;
--process (state_out, health_info)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and health_info = '1') then
-- err_state_out_invalid_not_health_info <= '1';
-- else
-- err_state_out_invalid_not_health_info <= '0';
-- end if;
--end process;
--process (state_out, fake_credit)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fake_credit = '1') then
-- err_state_out_invalid_not_fake_credit <= '1';
-- else
-- err_state_out_invalid_not_fake_credit <= '0';
-- end if;
--end process;
--process (state_out, write_fake_flit)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and write_fake_flit = '1') then
-- err_state_out_invalid_not_write_fake_flit <= '1';
-- else
-- err_state_out_invalid_not_write_fake_flit <= '0';
-- end if;
--end process;
--process (state_out, faulty_packet_in, faulty_packet_out)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and faulty_packet_in /= faulty_packet_out) then
-- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '1';
-- else
-- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '0';
-- end if;
--end process;
end behavior; |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
--err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out,
--err_valid_in_state_out_state_in_not_change,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
--err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
--err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
--err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic
--err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change
--err_state_out_invalid_state_in_state_out_not_change,
--err_state_out_invalid_not_fault_info,
--err_state_out_invalid_not_health_info,
--err_state_out_invalid_not_fake_credit,
--err_state_out_invalid_not_write_fake_flit,
--err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change: out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--signal read_en_signal: std_logic;
begin
--read_en_signal <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty_out;
-- Functional Checkers (Might cover or be covered by some of the structural checkers)
-- Empty and full cannot be high at the same time!
process (empty_out, full_out)
begin
if (empty_out = '1' and full_out = '1') then
err_empty_full <= '1';
else
err_empty_full <= '0';
end if;
end process;
-- Reading from an empty FIFO is not possible!
process (empty_out, read_en_out)
begin
if (empty_out = '1' and read_en_out = '1') then
err_empty_read_en <= '1';
else
err_empty_read_en <= '0';
end if;
end process;
-- Writing to a full FIFO is not possible!
process (full_out, write_en_out)
begin
if (full_out = '1' and write_en_out = '1') then
err_full_write_en <= '1';
else
err_full_write_en <= '0';
end if;
end process;
-- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)!
process (state_in)
begin
if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Read pointer must always be one-hot!
process (read_pointer_in)
begin
if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then
err_read_pointer_in_onehot <= '1';
else
err_read_pointer_in_onehot <= '0';
end if;
end process;
-- Write pointer must always be one-hot!
process (write_pointer_in)
begin
if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then
err_write_pointer_in_onehot <= '1';
else
err_write_pointer_in_onehot <= '0';
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- Structural Checkers
-- Write pointer and Read pointer checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
-- Checked !
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
-- Updated !
process (valid_in, write_en_out)
begin
if (valid_in = '0' and write_en_out = '1') then
err_not_write_en <= '1';
else
err_not_write_en <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then
err_not_write_en1 <= '1';
else
err_not_write_en1 <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then
err_not_write_en2 <= '1';
else
err_not_write_en2 <= '0';
end if;
end process;
-- Updated !
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then
err_read_en_mismatch1 <= '1';
else
err_read_en_mismatch1 <= '0';
end if;
end process;
-- Newly added checkers for FIFO with packet drop and fault classifier support!
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then
err_fake_credit_read_en_fake_credit_counter_in_increment <= '1';
else
err_fake_credit_read_en_fake_credit_counter_in_increment <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1';
else
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, credit_out)
begin
if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then
err_fake_credit_read_en_credit_out <= '1';
else
err_fake_credit_read_en_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0';
end if;
end process;
--process (fake_credit, read_en_out, credit_out)
--begin
-- if (fake_credit = '1' and read_en_out = '1' and credit_out = '1') then
-- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '1';
-- else
-- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '0';
-- end if;
--end process;
-- Checkers for Packet Dropping FSM of FIFO
--process (valid_in, state_out, state_in)
--begin
-- if (valid_in = '0' and (state_out = Idle or state_out = Header_flit or state_out = Body_flit or state_out = Packet_drop) and state_in /= state_out) then
-- err_valid_in_state_out_state_in_not_change <= '1';
-- else
-- err_valid_in_state_out_state_in_not_change <= '0';
-- end if;
--end process;
-- Idle state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, valid_in, state_in)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, fault_out, valid_in, state_in, state_out)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0';
end if;
end process;
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '0' and fake_credit = '1') then
err_state_out_Idle_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Idle_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, fault_info)
begin
if (state_out = Idle and fault_out = '0' and fault_info = '1') then
err_state_out_Idle_not_fault_out_not_fault_info <= '1';
else
err_state_out_Idle_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '1' and fake_credit = '0') then
err_state_out_Idle_fault_out_fake_credit <= '1';
else
err_state_out_Idle_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, state_in)
begin
if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Idle_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Idle_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, fault_out, fault_info)
begin
if (state_out = Idle and fault_out = '1' and fault_info = '0') then
err_state_out_Idle_fault_out_fault_info <= '1';
else
err_state_out_Idle_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in)
begin
if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Idle_fault_out_faulty_packet_in <= '1';
else
err_state_out_Idle_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Idle and write_fake_flit = '1') then
err_state_out_Idle_not_write_fake_flit <= '1';
else
err_state_out_Idle_not_write_fake_flit <= '0';
end if;
end process;
-- Other properties for Idle state
--------------------------------------------------------------------------------------------------
process (state_out, health_info)
begin
if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then
err_state_out_Idle_not_health_info <= '1';
else
err_state_out_Idle_not_health_info <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Header_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then
-- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Header_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in, state_out)
begin
if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Header_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Header_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Header_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1';
else
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Body_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, health_info)
begin
if (state_out = Body_flit and valid_in = '0' and health_info = '1') then
err_state_out_Body_flit_valid_in_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_health_info <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then
-- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Body_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Body_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Body_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Body_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if (state_out = Body_flit and fake_credit = '1') then
err_state_out_Body_flit_not_fake_credit <= '1';
else
err_state_out_Body_flit_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Tail_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then
-- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1';
else
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1';
else
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Tail_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Tail_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Tail_flit and write_fake_flit = '1') then
err_state_out_Tail_flit_not_write_fake_flit <= '1';
else
err_state_out_Tail_flit_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Packet_drop state
-- faulty_packet_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0';
end if;
end process;
-- faulty_packet_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, fault_info)
begin
if (state_out = Packet_drop and fault_info = '1') then
err_state_out_Packet_drop_not_fault_info <= '1';
else
err_state_out_Packet_drop_not_fault_info <= '0';
end if;
end process;
process (state_out, faulty_packet_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0';
end if;
end process;
--process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
--begin
-- if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
-- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '0';
-- end if;
--end process;
-- Invalid state
--process (state_out, state_in)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and state_in /= state_out) then
-- err_state_out_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
--process (state_out, fault_info)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fault_info = '1') then
-- err_state_out_invalid_not_fault_info <= '1';
-- else
-- err_state_out_invalid_not_fault_info <= '0';
-- end if;
--end process;
--process (state_out, health_info)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and health_info = '1') then
-- err_state_out_invalid_not_health_info <= '1';
-- else
-- err_state_out_invalid_not_health_info <= '0';
-- end if;
--end process;
--process (state_out, fake_credit)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fake_credit = '1') then
-- err_state_out_invalid_not_fake_credit <= '1';
-- else
-- err_state_out_invalid_not_fake_credit <= '0';
-- end if;
--end process;
--process (state_out, write_fake_flit)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and write_fake_flit = '1') then
-- err_state_out_invalid_not_write_fake_flit <= '1';
-- else
-- err_state_out_invalid_not_write_fake_flit <= '0';
-- end if;
--end process;
--process (state_out, faulty_packet_in, faulty_packet_out)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and faulty_packet_in /= faulty_packet_out) then
-- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '1';
-- else
-- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '0';
-- end if;
--end process;
end behavior; |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
--err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out,
--err_valid_in_state_out_state_in_not_change,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
--err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
--err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
--err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic
--err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change
--err_state_out_invalid_state_in_state_out_not_change,
--err_state_out_invalid_not_fault_info,
--err_state_out_invalid_not_health_info,
--err_state_out_invalid_not_fake_credit,
--err_state_out_invalid_not_write_fake_flit,
--err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change: out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--signal read_en_signal: std_logic;
begin
--read_en_signal <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty_out;
-- Functional Checkers (Might cover or be covered by some of the structural checkers)
-- Empty and full cannot be high at the same time!
process (empty_out, full_out)
begin
if (empty_out = '1' and full_out = '1') then
err_empty_full <= '1';
else
err_empty_full <= '0';
end if;
end process;
-- Reading from an empty FIFO is not possible!
process (empty_out, read_en_out)
begin
if (empty_out = '1' and read_en_out = '1') then
err_empty_read_en <= '1';
else
err_empty_read_en <= '0';
end if;
end process;
-- Writing to a full FIFO is not possible!
process (full_out, write_en_out)
begin
if (full_out = '1' and write_en_out = '1') then
err_full_write_en <= '1';
else
err_full_write_en <= '0';
end if;
end process;
-- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)!
process (state_in)
begin
if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Read pointer must always be one-hot!
process (read_pointer_in)
begin
if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then
err_read_pointer_in_onehot <= '1';
else
err_read_pointer_in_onehot <= '0';
end if;
end process;
-- Write pointer must always be one-hot!
process (write_pointer_in)
begin
if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then
err_write_pointer_in_onehot <= '1';
else
err_write_pointer_in_onehot <= '0';
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- Structural Checkers
-- Write pointer and Read pointer checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
-- Checked !
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
-- Updated !
process (valid_in, write_en_out)
begin
if (valid_in = '0' and write_en_out = '1') then
err_not_write_en <= '1';
else
err_not_write_en <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then
err_not_write_en1 <= '1';
else
err_not_write_en1 <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then
err_not_write_en2 <= '1';
else
err_not_write_en2 <= '0';
end if;
end process;
-- Updated !
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then
err_read_en_mismatch1 <= '1';
else
err_read_en_mismatch1 <= '0';
end if;
end process;
-- Newly added checkers for FIFO with packet drop and fault classifier support!
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then
err_fake_credit_read_en_fake_credit_counter_in_increment <= '1';
else
err_fake_credit_read_en_fake_credit_counter_in_increment <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1';
else
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, credit_out)
begin
if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then
err_fake_credit_read_en_credit_out <= '1';
else
err_fake_credit_read_en_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0';
end if;
end process;
--process (fake_credit, read_en_out, credit_out)
--begin
-- if (fake_credit = '1' and read_en_out = '1' and credit_out = '1') then
-- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '1';
-- else
-- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '0';
-- end if;
--end process;
-- Checkers for Packet Dropping FSM of FIFO
--process (valid_in, state_out, state_in)
--begin
-- if (valid_in = '0' and (state_out = Idle or state_out = Header_flit or state_out = Body_flit or state_out = Packet_drop) and state_in /= state_out) then
-- err_valid_in_state_out_state_in_not_change <= '1';
-- else
-- err_valid_in_state_out_state_in_not_change <= '0';
-- end if;
--end process;
-- Idle state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, valid_in, state_in)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, fault_out, valid_in, state_in, state_out)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0';
end if;
end process;
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '0' and fake_credit = '1') then
err_state_out_Idle_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Idle_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, fault_info)
begin
if (state_out = Idle and fault_out = '0' and fault_info = '1') then
err_state_out_Idle_not_fault_out_not_fault_info <= '1';
else
err_state_out_Idle_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '1' and fake_credit = '0') then
err_state_out_Idle_fault_out_fake_credit <= '1';
else
err_state_out_Idle_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, state_in)
begin
if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Idle_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Idle_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, fault_out, fault_info)
begin
if (state_out = Idle and fault_out = '1' and fault_info = '0') then
err_state_out_Idle_fault_out_fault_info <= '1';
else
err_state_out_Idle_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in)
begin
if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Idle_fault_out_faulty_packet_in <= '1';
else
err_state_out_Idle_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Idle and write_fake_flit = '1') then
err_state_out_Idle_not_write_fake_flit <= '1';
else
err_state_out_Idle_not_write_fake_flit <= '0';
end if;
end process;
-- Other properties for Idle state
--------------------------------------------------------------------------------------------------
process (state_out, health_info)
begin
if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then
err_state_out_Idle_not_health_info <= '1';
else
err_state_out_Idle_not_health_info <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Header_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then
-- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Header_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in, state_out)
begin
if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Header_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Header_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Header_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1';
else
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Body_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, health_info)
begin
if (state_out = Body_flit and valid_in = '0' and health_info = '1') then
err_state_out_Body_flit_valid_in_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_health_info <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then
-- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Body_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Body_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Body_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Body_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if (state_out = Body_flit and fake_credit = '1') then
err_state_out_Body_flit_not_fake_credit <= '1';
else
err_state_out_Body_flit_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Tail_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then
-- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1';
else
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1';
else
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Tail_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Tail_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Tail_flit and write_fake_flit = '1') then
err_state_out_Tail_flit_not_write_fake_flit <= '1';
else
err_state_out_Tail_flit_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Packet_drop state
-- faulty_packet_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0';
end if;
end process;
-- faulty_packet_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, fault_info)
begin
if (state_out = Packet_drop and fault_info = '1') then
err_state_out_Packet_drop_not_fault_info <= '1';
else
err_state_out_Packet_drop_not_fault_info <= '0';
end if;
end process;
process (state_out, faulty_packet_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0';
end if;
end process;
--process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
--begin
-- if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
-- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '0';
-- end if;
--end process;
-- Invalid state
--process (state_out, state_in)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and state_in /= state_out) then
-- err_state_out_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
--process (state_out, fault_info)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fault_info = '1') then
-- err_state_out_invalid_not_fault_info <= '1';
-- else
-- err_state_out_invalid_not_fault_info <= '0';
-- end if;
--end process;
--process (state_out, health_info)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and health_info = '1') then
-- err_state_out_invalid_not_health_info <= '1';
-- else
-- err_state_out_invalid_not_health_info <= '0';
-- end if;
--end process;
--process (state_out, fake_credit)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fake_credit = '1') then
-- err_state_out_invalid_not_fake_credit <= '1';
-- else
-- err_state_out_invalid_not_fake_credit <= '0';
-- end if;
--end process;
--process (state_out, write_fake_flit)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and write_fake_flit = '1') then
-- err_state_out_invalid_not_write_fake_flit <= '1';
-- else
-- err_state_out_invalid_not_write_fake_flit <= '0';
-- end if;
--end process;
--process (state_out, faulty_packet_in, faulty_packet_out)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and faulty_packet_in /= faulty_packet_out) then
-- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '1';
-- else
-- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '0';
-- end if;
--end process;
end behavior; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY servo_pwm_contador_clk64kHz_tb IS
END servo_pwm_contador_clk64kHz_tb;
ARCHITECTURE behavior OF servo_pwm_contador_clk64kHz_tb IS
-- Unidad bajo prueba.
COMPONENT servo_pwm_contador_clk64kHz
PORT(
clk : IN std_logic;
reset : IN std_logic;
cnt_up: IN std_logic;
cnt_dn: IN std_logic;
servo : OUT std_logic
);
END COMPONENT;
-- Entradas.
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal cnt_up : std_logic := '0';
signal cnt_dn : std_logic := '0';
-- Salidas.
signal servo : std_logic;
-- Definición del reloj.
constant clk_period : time := 10 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: servo_pwm_contador_clk64kHz PORT MAP (
clk => clk,
reset => reset,
cnt_up => cnt_up,
cnt_dn => cnt_dn,
servo => servo
);
-- Definición del proceso de reloj.
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Procesamiento de estímulos.
proceso_estimulos: process begin
-- Crear condición de reset.
reset <= '1';
wait for 50 ns;
reset <= '0';
-- Esperar poco menos de dos ciclos.
wait for 39 ms;
-- Crear el estímulo.
cnt_up <= '1';
wait for 15 us; -- Tiempo a editar.
--cnt_up <= '0';
wait;
end process;
END; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY servo_pwm_contador_clk64kHz_tb IS
END servo_pwm_contador_clk64kHz_tb;
ARCHITECTURE behavior OF servo_pwm_contador_clk64kHz_tb IS
-- Unidad bajo prueba.
COMPONENT servo_pwm_contador_clk64kHz
PORT(
clk : IN std_logic;
reset : IN std_logic;
cnt_up: IN std_logic;
cnt_dn: IN std_logic;
servo : OUT std_logic
);
END COMPONENT;
-- Entradas.
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal cnt_up : std_logic := '0';
signal cnt_dn : std_logic := '0';
-- Salidas.
signal servo : std_logic;
-- Definición del reloj.
constant clk_period : time := 10 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: servo_pwm_contador_clk64kHz PORT MAP (
clk => clk,
reset => reset,
cnt_up => cnt_up,
cnt_dn => cnt_dn,
servo => servo
);
-- Definición del proceso de reloj.
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Procesamiento de estímulos.
proceso_estimulos: process begin
-- Crear condición de reset.
reset <= '1';
wait for 50 ns;
reset <= '0';
-- Esperar poco menos de dos ciclos.
wait for 39 ms;
-- Crear el estímulo.
cnt_up <= '1';
wait for 15 us; -- Tiempo a editar.
--cnt_up <= '0';
wait;
end process;
END; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity top is
port(
clk : in std_logic;
btn_north_i : in std_logic;
-- LCD Interface
lcd_db_io : inout std_logic_vector(7 downto 0);
lcd_rs_o : out std_logic;
lcd_en_o : out std_logic;
lcd_rw_o : out std_logic;
-- Rotary Knob (ROT)
rot_center_i : in std_logic;
rot_a_i : in std_logic;
rot_b_i : in std_logic;
-- Mechanical Switches
switch_i : in std_logic_vector(3 downto 0)
);
end entity top;
architecture beh of top is
signal rst : std_logic;
signal rst_n_i : std_logic;
signal address : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal lcd_db : std_logic_vector (7 downto 0);
signal lcd_rs : std_logic;
signal lcd_en : std_logic;
signal lcd_rw : std_logic;
signal lcd_wr : std_logic;
signal lcd_out : std_logic_vector(7 downto 0);
signal rightInt : std_logic;
signal leftInt : std_logic;
signal pushInt : std_logic;
begin
deb_rst: entity work.debounce
port map(
clk => clk,
input => btn_north_i,
output => rst,
riseedge => open,
falledge => open
);
rst_n_i <= not rst;
mem_inst: entity work.memory
port map(
address => address,
data => data
);
cpu_core: entity work.core
port map(
clk => clk,
rst => rst_n_i,
address => address,
data => data,
lcd_out => lcd_out,
lcd_wr => lcd_wr,
rightInt => rightInt,
leftInt => leftInt,
pushInt => pushInt,
switch => switch_i
);
inst_rotKey : entity work.rotKey
port map(
clk => clk,
rotA => rot_a_i,
rotB => rot_b_i,
rotPush => rot_center_i,
rotRightEvent => rightInt,
rotLeftEvent => leftInt,
rotPushEvent => pushInt);
i_lcd_core : entity work.lcd_core
port map
(
clk_i => clk,
reset_n_i => rst_n_i,
lcd_cs_i => lcd_wr,
lcd_data_i => lcd_out,
lcd_data_o => lcd_db,
lcd_rs_o => lcd_rs,
lcd_en_o => lcd_en,
lcd_rw_o => lcd_rw
);
lcd_db_io <= lcd_db when (lcd_rw = '0') else (others => 'Z');
lcd_rs_o <= lcd_rs;
lcd_en_o <= lcd_en;
lcd_rw_o <= lcd_rw;
end architecture beh;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_1_block6.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block6
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_8_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_8_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_16_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_16_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_15_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_16_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_16_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_15_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block6;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block6 IS
-- Signals
SIGNAL twdlXdin_8_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_8_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_16_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_16_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_15_re_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_15_im_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_16_re_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_16_im_tmp : signed(17 DOWNTO 0); -- sfix18
BEGIN
twdlXdin_8_re_signed <= signed(twdlXdin_8_re);
twdlXdin_8_im_signed <= signed(twdlXdin_8_im);
twdlXdin_16_re_signed <= signed(twdlXdin_16_re);
twdlXdin_16_im_signed <= signed(twdlXdin_16_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_8_re_signed,
twdlXdin_8_im_signed, twdlXdin_16_re_signed, twdlXdin_16_im_signed,
twdlXdin_1_vld)
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_8_re_signed, 19) + resize(twdlXdin_16_re_signed, 19);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_8_re_signed, 19) - resize(twdlXdin_16_re_signed, 19);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_8_im_signed, 19) + resize(twdlXdin_16_im_signed, 19);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_8_im_signed, 19) - resize(twdlXdin_16_im_signed, 19);
END IF;
dout_15_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(17 DOWNTO 0);
dout_15_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(17 DOWNTO 0);
dout_16_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(17 DOWNTO 0);
dout_16_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(17 DOWNTO 0);
dout_15_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_15_re <= std_logic_vector(dout_15_re_tmp);
dout_15_im <= std_logic_vector(dout_15_im_tmp);
dout_16_re <= std_logic_vector(dout_16_re_tmp);
dout_16_im <= std_logic_vector(dout_16_im_tmp);
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_external_wb8 is
generic(
ADDRBITS: integer := 19;
DATABITS: integer := 8
);
port(
-- signal naming according to Wishbone B4 spec
CLK_I: in std_logic;
STB_I: in std_logic;
WE_I: in std_logic;
ADR_I: in std_logic_vector(ADDRBITS-1 downto 0);
DAT_I: in std_logic_vector(DATABITS-1 downto 0);
DAT_O: out std_logic_vector(DATABITS-1 downto 0);
ACK_O: out std_logic;
-- interface to external SRAM
O_sram_adr: out std_logic_vector(ADDRBITS-1 downto 0);
O_sram_we: out std_logic := '1';
O_sram_ce: out std_logic := '1';
O_sram_oe: out std_logic := '1';
IO_sram_dat: inout std_logic_vector(DATABITS-1 downto 0) := X"00"
);
end sram_external_wb8;
architecture Behavioral of sram_external_wb8 is
begin
sram_external_instance: entity work.sram_external port map(
I_addr => ADR_I,
I_data => DAT_I,
I_en => STB_I,
I_we => (WE_I and STB_I),
O_data => DAT_O,
IO_external_data => IO_sram_dat,
O_external_addr => O_sram_adr(ADDRBITS-1 downto 0),
O_external_ce => O_sram_ce,
O_external_oe => O_sram_oe,
O_external_we => O_sram_we
);
process(CLK_I, STB_I)
variable ack: std_logic := '0';
begin
if rising_edge(CLK_I) then
ack := '0';
if STB_I = '1' then
ack := '1';
end if;
end if;
ACK_O <= ack and STB_I;
end process;
end Behavioral; |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : arg_mem_bank_v6.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.asymmetric_dp_bank_v6;
use axis_accelerator_adapter_v2_1_6.symmetric_dp_bank_v6;
use axis_accelerator_adapter_v2_1_6.dp_bank_sdp_v6;
entity arg_mem_bank_v6 is
generic (
C_FAMILY : string;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_PRINT_INFO : boolean := false;
C_IS_UNIDIR : integer range 0 to 1 := 0;
C_OPORT_AWIDTH : integer;
C_OPORT_DWIDTH : integer;
C_IPORT_AWIDTH : integer;
C_IPORT_DWIDTH : integer);
port (
rst : in std_logic;
oport_clk : in std_logic;
oport_ce : in std_logic;
oport_we : in std_logic;
oport_addr : in std_logic_vector(C_OPORT_AWIDTH-1 downto 0);
oport_din : in std_logic_vector(C_OPORT_DWIDTH-1 downto 0);
oport_dout : out std_logic_vector(C_OPORT_DWIDTH-1 downto 0);
iport_clk : in std_logic;
iport_ce : in std_logic;
iport_we : in std_logic;
iport_addr : in std_logic_vector(C_IPORT_AWIDTH-1 downto 0);
iport_din : in std_logic_vector(C_IPORT_DWIDTH-1 downto 0);
iport_dout : out std_logic_vector(C_IPORT_DWIDTH-1 downto 0));
end arg_mem_bank_v6;
architecture rtl of arg_mem_bank_v6 is
function calc_use_sdp(is_unidir : natural) return integer is
variable use_sdp : integer;
begin
if(C_IS_UNIDIR = 0) then
use_sdp := 0;
else
use_sdp := 0;
if(C_OPORT_DWIDTH = 64 and C_IPORT_DWIDTH <= 64 and C_OPORT_AWIDTH <= 9) then
-- SDP, WR port 64 bits
use_sdp := 1;
elsif(C_IPORT_DWIDTH = 64 and C_OPORT_DWIDTH <= 64 and C_IPORT_AWIDTH <= 9) then
-- SDP, RD port 64 bits
use_sdp := 1;
end if;
end if;
return use_sdp;
end function calc_use_sdp;
constant USE_SDP : integer := calc_use_sdp(C_IS_UNIDIR);
begin
WR_PORT_WIDER_GEN : if (C_IPORT_DWIDTH > C_OPORT_DWIDTH) generate
begin
USE_SDP_GEN : if (use_sdp /= 0) generate
begin
BANK_I : entity axis_accelerator_adapter_v2_1_6.dp_bank_sdp_v6
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_SDP_WIDE => 1,
C_RD_AWIDTH => C_OPORT_AWIDTH,
C_RD_DWIDTH => C_OPORT_DWIDTH,
C_WR_AWIDTH => C_IPORT_AWIDTH,
C_WR_DWIDTH => C_IPORT_DWIDTH)
port map (
rst => rst,
rd_clk => oport_clk,
rd_en => oport_ce,
rd_addr => oport_addr,
dout => oport_dout,
wr_clk => iport_clk,
wr_en => iport_ce,
wr_addr => iport_addr,
din => iport_din);
iport_dout <= (others => '0');
end generate USE_SDP_GEN;
DONT_USE_SDP_GEN : if (use_sdp = 0) generate
begin
-- Port A is always the wider port
BANK_I : entity axis_accelerator_adapter_v2_1_6.asymmetric_dp_bank_v6
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_BANK_AWIDTH_A => C_IPORT_AWIDTH,
C_BANK_DWIDTH_A => C_IPORT_DWIDTH,
C_BANK_AWIDTH_B => C_OPORT_AWIDTH,
C_BANK_DWIDTH_B => C_OPORT_DWIDTH)
port map (
rst => rst,
clk_a => iport_clk,
ce_a => iport_ce,
we_a => iport_we,
addr_a => iport_addr,
din_a => iport_din,
dout_a => iport_dout,
clk_b => oport_clk,
ce_b => oport_ce,
we_b => oport_we,
addr_b => oport_addr,
din_b => oport_din,
dout_b => oport_dout);
end generate DONT_USE_SDP_GEN;
end generate WR_PORT_WIDER_GEN;
---------------------------------------------------------------------------------------
WR_PORT_NARROWER_GEN : if (C_IPORT_DWIDTH < C_OPORT_DWIDTH) generate
begin
USE_SDP_GEN : if (use_sdp /= 0) generate
begin
BANK_I : entity axis_accelerator_adapter_v2_1_6.dp_bank_sdp_v6
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_SDP_WIDE => 0,
C_RD_AWIDTH => C_OPORT_AWIDTH,
C_RD_DWIDTH => C_OPORT_DWIDTH,
C_WR_AWIDTH => C_IPORT_AWIDTH,
C_WR_DWIDTH => C_IPORT_DWIDTH)
port map (
rst => rst,
rd_clk => oport_clk,
rd_en => oport_ce,
rd_addr => oport_addr,
dout => oport_dout,
wr_clk => iport_clk,
wr_en => iport_ce,
wr_addr => iport_addr,
din => iport_din);
iport_dout <= (others => '0');
end generate USE_SDP_GEN;
DONT_USE_SDP_GEN : if (use_sdp = 0) generate
begin
-- Port A is always the wider port
BANK_I : entity axis_accelerator_adapter_v2_1_6.asymmetric_dp_bank_v6
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_BANK_AWIDTH_B => C_IPORT_AWIDTH,
C_BANK_DWIDTH_B => C_IPORT_DWIDTH,
C_BANK_AWIDTH_A => C_OPORT_AWIDTH,
C_BANK_DWIDTH_A => C_OPORT_DWIDTH)
port map (
rst => rst,
clk_b => iport_clk,
ce_b => iport_ce,
we_b => iport_we,
addr_b => iport_addr,
din_b => iport_din,
dout_b => iport_dout,
clk_a => oport_clk,
ce_a => oport_ce,
we_a => oport_we,
addr_a => oport_addr,
din_a => oport_din,
dout_a => oport_dout);
end generate DONT_USE_SDP_GEN;
end generate WR_PORT_NARROWER_GEN;
SAME_WIDTH_GEN : if (C_OPORT_DWIDTH = C_IPORT_DWIDTH) generate
begin
BANK_I : entity axis_accelerator_adapter_v2_1_6.symmetric_dp_bank_v6
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_BANK_AWIDTH => C_OPORT_AWIDTH,
C_BANK_DWIDTH => C_OPORT_DWIDTH)
port map (
rst => rst,
clk_a => oport_clk,
ce_a => oport_ce,
we_a => oport_we,
addr_a => oport_addr,
din_a => oport_din,
dout_a => oport_dout,
clk_b => iport_clk,
ce_b => iport_ce,
we_b => iport_we,
addr_b => iport_addr,
din_b => iport_din,
dout_b => iport_dout);
end generate SAME_WIDTH_GEN;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: net
-- File: net.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package with component and type declarations for network cores
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package net is
type eth_in_type is record
gtx_clk : std_ulogic;
rmii_clk : std_ulogic;
tx_clk : std_ulogic;
tx_clk_90 : std_ulogic;
tx_dv : std_ulogic;
rx_clk : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
rx_en : std_ulogic;
mdio_i : std_ulogic;
mdint : std_ulogic;
phyrstaddr : std_logic_vector(4 downto 0);
edcladdr : std_logic_vector(3 downto 0);
edclsepahb : std_ulogic;
edcldisable: std_ulogic;
end record;
constant eth_in_none : eth_in_type :=
('0', '0', '0', '0', '0', '0', (others => '0'), '0', '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0');
type eth_out_type is record
reset : std_ulogic;
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
tx_clk : std_ulogic;
mdc : std_ulogic;
mdio_o : std_ulogic;
mdio_oe : std_ulogic;
gbit : std_ulogic;
speed : std_ulogic;
end record;
constant eth_out_none : eth_out_type :=
('0', (others => '0'), '0', '0', '0', '0', '0', '1', '0', '0');
type eth_sgmii_in_type is record
clkp : std_ulogic;
clkn : std_ulogic;
rxp : std_ulogic;
rxn : std_ulogic;
mdio_i : std_ulogic;
mdint : std_ulogic;
end record;
type eth_sgmii_out_type is record
reset : std_ulogic;
txp : std_ulogic;
txn : std_ulogic;
mdc : std_ulogic;
mdio_o : std_ulogic;
mdio_oe : std_ulogic;
end record;
component eth_arb
generic(
fullduplex : integer := 0;
mdiomaster : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
ethi : in eth_in_type;
etho : out eth_out_type;
methi : in eth_out_type;
metho : out eth_in_type;
dethi : in eth_out_type;
detho : out eth_in_type
);
end component;
component greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greth_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greth_gbit_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greth_gbit is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component grethm
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component rgmii is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
tech : integer := 0;
gmii : integer := 0;
debugmem : integer := 0;
abits : integer := 8;
no_clk_mux : integer := 0;
pirq : integer := 0;
use90degtxclk : integer := 0
);
port (
rstn : in std_ulogic;
gmiii : out eth_in_type;
gmiio : in eth_out_type;
rgmiii : in eth_in_type;
rgmiio : out eth_out_type ;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component sgmii is
generic (
fabtech : integer := 0;
phy_addr : integer := 0;
mode : integer := 0 -- unused
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
ser_rx_p : in std_logic;
ser_tx_p : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
tx_clk : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
rx_clk : out std_logic;
-- optional MDIO interface to PCS
mdc : in std_logic;
mdio_o : in std_logic := '0';
mdio_oe : in std_logic := '1';
mdio_i : out std_logic
);
end component ;
component comma_detect is
port (
clk : in std_logic;
rstn : in std_logic;
indata : in std_logic_vector(9 downto 0);
bitslip : out std_logic
);
end component;
component elastic_buffer is
port (
wr_clk : in std_logic;
wr_rst : in std_logic;
wr_data : in std_logic_vector(9 downto 0);
rd_clk : in std_logic;
rd_rst : in std_logic;
rd_data : out std_logic_vector(9 downto 0)
) ;
end component ;
end;
|
-- -*- vhdl -*-
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pyvivado_utils.all;
entity CombMinimumNonZeroRemainder is
generic (
WIDTH: integer;
N_INPUTS: integer;
INPUT_ADDRESS_WIDTH: integer := 0
);
port (
i_data: in std_logic_vector(N_INPUTS*WIDTH-1 downto 0);
i_addresses: in std_logic_vector(N_INPUTS*INPUT_ADDRESS_WIDTH-1 downto 0);
o_data: out std_logic_vector(WIDTH-1 downto 0);
o_address: out std_logic_vector(
INPUT_ADDRESS_WIDTH+logceil(N_INPUTS)-1 downto 0)
);
end CombMinimumNonZeroRemainder;
architecture arch of CombMinimumNonZeroRemainder is
constant ZEROS: positive := 2 ** (logceil(N_INPUTS+1)-1);
constant NONZEROS: positive := N_INPUTS - ZEROS;
constant INTERMED_ADDRESS_WIDTH: positive :=
INPUT_ADDRESS_WIDTH + logceil(ZEROS);
signal zero_i_data: std_logic_vector(ZEROS*WIDTH-1 downto 0);
signal zero_i_addresses: std_logic_vector(
ZEROS*INPUT_ADDRESS_WIDTH-1 downto 0);
signal nonzero_i_data: std_logic_vector(NONZEROS*WIDTH-1 downto 0);
signal nonzero_i_addresses: std_logic_vector(
NONZEROS*INPUT_ADDRESS_WIDTH-1 downto 0);
signal zero_o_data: std_logic_vector(WIDTH-1 downto 0);
signal zero_o_address: std_logic_vector(
INTERMED_ADDRESS_WIDTH-1 downto 0);
signal nonzero_o_data: std_logic_vector(WIDTH-1 downto 0);
signal nonzero_o_address: std_logic_vector(
INPUT_ADDRESS_WIDTH+logceil(NONZEROS)-1 downto 0);
signal padded_nonzero_o_address: std_logic_vector(
INTERMED_ADDRESS_WIDTH-1 downto 0);
signal two_i_data: std_logic_vector(2*WIDTH-1 downto 0);
signal two_i_addresses: std_logic_vector(
2*(INPUT_ADDRESS_WIDTH+logceil(ZEROS))-1 downto 0);
component CombMinimumGeneric is
generic (
WIDTH: integer;
N_INPUTS: integer;
INPUT_ADDRESS_WIDTH: integer := 0
);
port (
i_data: in std_logic_vector(N_INPUTS*WIDTH-1 downto 0);
i_addresses: in std_logic_vector(N_INPUTS*INPUT_ADDRESS_WIDTH-1 downto 0);
o_data: out std_logic_vector(WIDTH-1 downto 0);
o_address: out std_logic_vector(INPUT_ADDRESS_WIDTH+logceil(N_INPUTS)-1 downto 0)
);
end component;
begin
zero_i_data <= i_data(ZEROS*WIDTH-1 downto 0);
nonzero_i_data <= i_data(N_INPUTS*WIDTH-1 downto ZEROS*WIDTH);
zero_i_addresses <= i_addresses(ZEROS*INPUT_ADDRESS_WIDTH-1 downto 0);
nonzero_i_addresses <= i_addresses(N_INPUTS*INPUT_ADDRESS_WIDTH-1 downto
ZEROS*INPUT_ADDRESS_WIDTH);
process(nonzero_o_address)
begin
padded_nonzero_o_address <= (others => '0');
padded_nonzero_o_address(
INPUT_ADDRESS_WIDTH+logceil(NONZEROS)-1 downto 0) <= nonzero_o_address;
end process;
zero: entity work.CombMinimumZeroRemainder
generic map(
N_INPUTS => ZEROS,
WIDTH => WIDTH,
INPUT_ADDRESS_WIDTH => INPUT_ADDRESS_WIDTH
)
port map(
i_data => zero_i_data,
i_addresses => zero_i_addresses,
o_data => zero_o_data,
o_address => zero_o_address
);
general: CombMinimumGeneric
generic map(
N_INPUTS => NONZEROS,
WIDTH => WIDTH,
INPUT_ADDRESS_WIDTH => INPUT_ADDRESS_WIDTH
)
port map(
i_data => nonzero_i_data,
i_addresses => nonzero_i_addresses,
o_data => nonzero_o_data,
o_address => nonzero_o_address
);
two_i_data(WIDTH-1 downto 0) <= zero_o_data;
two_i_data(2*WIDTH-1 downto WIDTH) <= nonzero_o_data;
two_i_addresses(INTERMED_ADDRESS_WIDTH-1 downto 0) <= zero_o_address;
two_i_addresses(2*INTERMED_ADDRESS_WIDTH-1 downto INTERMED_ADDRESS_WIDTH) <=
padded_nonzero_o_address;
combine_two: entity work.CombMinimumTwo
generic map(
WIDTH => WIDTH,
INPUT_ADDRESS_WIDTH => INPUT_ADDRESS_WIDTH + logceil(ZEROS)
)
port map(
i_data => two_i_data,
i_addresses => two_i_addresses,
o_data => o_data,
o_address => o_address
);
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.all;
use work.defs.all;
entity go is
port(adc_p : in unsigned7;
adc_n : in unsigned7;
adc_clk_p : out std_logic;
adc_clk_n : out std_logic;
adc_reclk_p : in std_logic;
adc_reclk_n : in std_logic;
adc_sen : out std_logic := '0';
adc_sdata : out std_logic := '0';
adc_sclk : out std_logic := '0';
adc_reset : out std_logic := '1';
audio_scki, audio_lrck, audio_data, audio_bck : out std_logic;
audio_pd_inv, audio_demp : out std_logic;
usb_d : inout unsigned8;
usb_c : inout unsigned8;
flash_cs_inv, flash_sclk, flash_si : out std_logic;
flash_so : in std_logic;
cpu_ssirx : out std_logic;
cpu_ssitx : in std_logic;
cpu_ssiclk : in std_logic;
cpu_ssifss : in std_logic;
header_16 : out std_logic;
spartan_m0 : in std_logic;
spartan_m1 : in std_logic;
led : out unsigned8;
clkin125 : in std_logic;
clkin125_en : out std_logic);
end go;
architecture go of go is
signal xx, yy : four_mf_signed;
signal xx_mf, yy_mf : mf_signed;
signal xx_buf, yy_buf : signed36;
signal xx_buf_last, yy_buf_last, xx_mf_last, yy_mf_last : std_logic;
signal packet : unsigned(31 downto 0);
-- Generated clock for delivery to ADC.
signal adc_clk : std_logic;
signal adc_clk_neg : std_logic;
signal adc_clk_250 : std_logic;
signal adc_clk_neg_250 : std_logic;
signal adc_clk_200 : std_logic;
signal adc_clk_neg_200 : std_logic;
signal adc_clk_fb : std_logic;
-- Received clk from ADC.
signal adc_reclk_b : std_logic;
signal adc_reclk : std_logic;
signal adc_reclk_diff : std_logic;
-- Regenerated reclk.
signal clk_main : std_logic;
signal clk_main_neg : std_logic;
signal clku_main : std_logic;
signal clku_main_neg : std_logic;
signal clk_main_fb : std_logic;
signal clkin125_b : std_logic;
signal clk_50m : std_logic;
signal clku_50m : std_logic;
signal adc_ddr : unsigned7;
signal adc_data, adc_data_c, adc_data_b : signed14;
attribute keep of adc_data_c : signal is "true";
signal phase : unsigned18;
signal phase_strobe, phase_last : std_logic;
signal ir_data : signed18;
signal ir_strobe : std_logic;
signal ir_last : std_logic;
signal usb_xmit, usb_last : std_logic;
signal usb_xmit_length : integer range 0 to 5;
signal usb_xmit_overrun : std_logic;
signal usb_nRXFb, usb_nTXEb : std_logic := '1';
signal usb_nRXF, usb_nTXE : std_logic := '1';
signal xmit_SIWU : std_logic;
attribute keep of usb_nRXFb, usb_nTXEb : signal is "true";
signal low_data : signed32;
signal low_strobe : std_logic;
signal low_last : std_logic;
signal out_data : signed32;
signal out_last : std_logic;
-- The configuration loaded via the CPU.
constant config_bytes : integer := 28;
signal config : unsigned(config_bytes * 8 - 1 downto 0);
signal conf_strobe, conf_strobe2, conf_strobe3, conf_strobe_fast :
unsigned(config_bytes - 1 downto 0);
alias to_usb_data : unsigned8 is config(7 downto 0);
alias adc_control : unsigned8 is config(15 downto 8);
-- Control for data in to USB host.
alias xmit_control : unsigned8 is config(23 downto 16);
-- Channel to select from time-multiplexed data.
alias xmit_channel : unsigned2 is xmit_control(1 downto 0);
-- Data source.
alias xmit_source : unsigned3 is xmit_control(4 downto 2);
-- Strobe SIWU to push data through to host.
alias xmit_low_latency : std_logic is xmit_control(7);
-- Ignore the TX handshake and shovel data at 12.5 MB/s.
alias xmit_turbo : std_logic is xmit_control(6);
alias flash_control : unsigned8 is config(31 downto 24);
alias clock_select : std_logic is flash_control(7);
alias burst_start : std_logic is flash_control(6);
alias bandpass_freq : unsigned8 is config(39 downto 32);
alias bandpass_gain : unsigned8 is config(47 downto 40);
signal bandpass_strobe : std_logic := '0';
signal bandpass_r, bandpass_i : signed15;
alias sampler_rate : unsigned8 is config(55 downto 48);
alias sampler_decay : unsigned16 is config(71 downto 56);
signal sampler_data : signed15;
signal sampler_strobe : std_logic;
alias pll_decay : unsigned8 is config(79 downto 72);
alias audio_channel : unsigned8 is config(87 downto 80);
signal usb_byte_in : unsigned8;
signal usb_byte_in_strobe, usb_byte_in_strobe2 : std_logic;
signal burst_data : signed15;
signal burst_strobe : std_logic;
signal led_off : unsigned8 := x"fe";
signal usbd_out : unsigned8;
signal usb_oe_n : std_logic;
attribute S : string;
attribute S of usb_c : signal is "yes";
attribute S of led : signal is "yes";
attribute pullup : string;
attribute pullup of spartan_m0, spartan_m1 : signal is "TRUE";
alias clk_main_locked : std_logic is led_off(1);
alias adc_clk_locked : std_logic is led_off(2);
-- spi conf stuff.
constant spi_data_bytes : integer := 44;
signal spi_data : unsigned(spi_data_bytes * 8 - 1 downto 0) :=
(others => '0');
signal spi_data_ack : unsigned(spi_data_bytes - 1 downto 0) :=
(others => '0');
signal usb_read_ok : std_logic := '1';
alias spied_flash : unsigned8 is spi_data(31 downto 24);
alias spied_pll_freq : unsigned(31 downto 0) is spi_data(287 downto 256);
alias spied_pll_error : unsigned(31 downto 0) is spi_data(319 downto 288);
alias spied_pll_level : unsigned(31 downto 0) is spi_data(351 downto 320);
alias spied_pll_strobe : std_logic is spi_data_ack(43);
signal pll_phasor : unsigned18;
signal cpu_ssifss2, cpu_ssitx2, cpu_ssiclk2 : std_logic := '1';
signal cpu_ssifss3, cpu_ssitx3, cpu_ssiclk3 : std_logic := '1';
attribute keep of cpu_ssifss2, cpu_ssitx2, cpu_ssiclk2 : signal is "true";
signal xy_strobe, xy_last : std_logic;
signal xy_data : unsigned(30 downto 0);
constant X40 : unsigned(39 downto 0) := (others => 'X');
begin
usb_d <= usbd_out when usb_oe_n = '0' else "ZZZZZZZZ";
usb_c(7 downto 5) <= "ZZZ";
usb_c(0) <= 'Z'; -- nRXF.
usb_c(1) <= 'Z'; -- nTXE.
-- SIWU can be strobed either by the USBIO unit, or manually.
usb_c(4) <= xmit_SIWU and not (xmit_low_latency and xmit_turbo);
clkin125_en <= '1';
audio_pd_inv <= '1';
audio_demp <= '0';
adc_sen <= adc_control(0);
adc_sdata <= adc_control(1);
adc_sclk <= adc_control(2);
adc_reset <= adc_control(3);
flash_si <= flash_control(0);
flash_cs_inv <= flash_control(1);
flash_sclk <= flash_control(2);
led_control: for i in 0 to 7 generate
led(i) <= '0' when led_off(i) = '0' else 'Z';
end generate;
led_off(5) <= not usb_xmit_overrun or xmit_turbo;
led_off(6) <= spartan_m0;
led_off(7) <= not spartan_m1;
spi : entity spiconf
generic map(
config_bytes, spi_data_bytes,
x"55642576" & x"0067d567" & x"005ed289" &
X40 & x"00" & x"0b" & x"0000" & x"ff" & x"0000"
& x"0f" & x"98" & x"09" & x"00")
port map(cpu_ssifss3, cpu_ssitx3, cpu_ssirx, cpu_ssiclk3,
cpu_ssifss, cpu_ssitx,
spi_data, spi_data_ack, config, conf_strobe, clk_50m);
-- Byte zero is usb data to spi. Byte 3 is flash data to spi.
spi_data(23 downto 8) <= config(23 downto 8);
spi_data(87 downto 32) <= config(87 downto 32);
spi_data(223 downto 128) <= config(223 downto 128);
process
begin
wait until rising_edge(clk_50m);
spied_flash(0) <= flash_so;
if usb_byte_in_strobe = '1' then
spi_data(7 downto 0) <= usb_byte_in;
elsif spi_data_ack(0) = '1' and usb_byte_in_strobe2 = '0' then
spi_data(7 downto 0) <= x"00";
end if;
if usb_byte_in_strobe = '0' and spi_data(7 downto 0) = x"00" then
usb_read_ok <= '1';
else
usb_read_ok <= '0';
end if;
usb_byte_in_strobe2 <= usb_byte_in_strobe;
conf_strobe2 <= conf_strobe;
end process;
process
begin
wait until rising_edge(clk_main);
conf_strobe3 <= conf_strobe2;
conf_strobe_fast <= conf_strobe2 and not conf_strobe3;
end process;
blinky : entity blinkoflow port map(adc_data_b, led_off(4), open, clk_main);
dc0: entity downconvert port map (
adc_data_b, config(159 downto 152), xx(0), yy(0),
config(151 downto 128), clk_main);
dc1: entity downconvert port map (
adc_data_b, config(191 downto 184), xx(1), yy(1),
config(183 downto 160), clk_main);
dcpll : entity downconvertpll
port map(adc_data_b, config(215 downto 192), config(223 downto 216),
pll_decay(3 downto 0),
conf_strobe_fast(26), xx(2), yy(2), pll_phasor,
spied_pll_freq, spied_pll_error, spied_pll_level, spied_pll_strobe,
clk_main);
xfilter: entity multifilter port map(xx, xx_mf, xx_mf_last, clk_main);
yfilter: entity multifilter port map(yy, yy_mf, yy_mf_last, clk_main);
xcheby: entity quadcheby port map(
xx_mf, xx_buf, xx_mf_last, xx_buf_last, clk_main);
ycheby: entity quadcheby port map(
yy_mf, yy_buf, yy_mf_last, yy_buf_last, clk_main);
ph: entity phasedetect
port map(xx_buf, yy_buf, xx_buf_last,
phase, phase_strobe, phase_last, pll_phasor, clk_main);
irf: entity irfir
generic map (acc_width => 36, out_width => 18)
port map(phase, phase_last, ir_data, ir_strobe, ir_last, clk_main);
lf: entity lowfir
generic map (acc_width => 37, out_width => 32)
port map(ir_data, ir_last, low_data, low_strobe, low_last, clk_main);
demph: entity quaddemph generic map (32, 40, 32, 1)
port map (low_data, low_strobe, low_last,
out_data, out_last, clk_main);
au: entity audio generic map (bits_per_sample => 32)
port map (out_data, out_data, audio_channel(1 downto 0), out_last,
audio_scki, audio_lrck, audio_data, audio_bck, clk_main);
bp : entity bandpass port map (
adc_data_b, bandpass_freq, bandpass_gain,
bandpass_r, bandpass_i, bandpass_strobe, clk_main);
brst : entity burst port map (
adc_data_b, burst_start, burst_data, burst_strobe, clk_main);
smplr : entity sampler port map (
adc_data_b, sampler_decay, sampler_rate, sampler_data, sampler_strobe,
clk_main);
cpuclock : entity clockgen port map (
header_16, spi_data(121 downto 112), clk_main, clk_main_neg, clk_50m);
process
begin
wait until rising_edge(clk_main);
adc_data_c <= adc_data xor "10" & x"000";
adc_data_b <= adc_data_c;
packet <= (others => 'X');
case xmit_source is
when "000" =>
packet(17 downto 0) <= unsigned(ir_data);
packet(22 downto 18) <= "00000";
packet(23) <= usb_xmit_overrun;
usb_xmit <= usb_xmit xor ir_strobe;
usb_last <= ir_last;
usb_xmit_length <= 3;
when "001" =>
packet(14 downto 0) <= unsigned(sampler_data);
packet(15) <= usb_xmit_overrun;
usb_xmit <= usb_xmit xor sampler_strobe;
usb_last <= '1';
usb_xmit_length <= 2;
when "010" =>
packet(30 downto 0) <= xy_data;
packet(31) <= usb_xmit_overrun;
usb_xmit <= usb_xmit xor xy_strobe;
usb_last <= xy_last;
usb_xmit_length <= 4;
when "011" =>
packet(17 downto 0) <= phase;
packet(22 downto 18) <= "00000";
packet(23) <= usb_xmit_overrun;
usb_xmit <= usb_xmit xor phase_strobe;
usb_last <= phase_last;
usb_xmit_length <= 3;
when "100" =>
packet(14 downto 0) <= unsigned(bandpass_r);
packet(15) <= '0';
packet(30 downto 16) <= unsigned(bandpass_i);
packet(31) <= usb_xmit_overrun;
usb_xmit_length <= 4;
usb_xmit <= usb_xmit xor bandpass_strobe;
usb_last <= '1';
when "101" =>
packet(14 downto 0) <= unsigned(burst_data);
packet(15) <= usb_xmit_overrun;
usb_xmit_length <= 2;
usb_xmit <= burst_strobe;
usb_last <= '1';
when "110" =>
packet(7 downto 0) <= to_usb_data;
usb_xmit <= usb_xmit xor conf_strobe_fast(0);
usb_last <= '1';
usb_xmit_length <= 1;
when others =>
usb_xmit_length <= 0;
usb_last <= '1';
usb_xmit <= usb_xmit xor ir_strobe;
end case;
end process;
usb: entity usbio
generic map(4)
port map(usbd_in => usb_d, usbd_out => usbd_out, usb_oe_n => usb_oe_n,
usb_nRXF => usb_nRXF, usb_nTXE => usb_nTXE,
usb_nRD => usb_c(2), usb_nWR => usb_c(3),
usb_SIWU => xmit_SIWU, read_ok => usb_read_ok,
byte_in => usb_byte_in, byte_in_strobe => usb_byte_in_strobe,
tx_overrun => usb_xmit_overrun,
packet => packet,
xmit => usb_xmit, last => usb_last,
xmit_channel => xmit_channel, xmit_length => usb_xmit_length,
low_latency => xmit_low_latency, turbo => xmit_turbo,
clk => clk_50m);
process
begin
wait until rising_edge(clk_main_neg);
usb_nRXFb <= usb_c(0);
usb_nTXEb <= usb_c(1);
end process;
process
begin
wait until falling_edge(clk_50m);
usb_nRXF <= usb_nRXFb;
usb_nTXE <= usb_nTXEb;
end process;
process
begin
wait until rising_edge(clk_main);
cpu_ssifss2 <= cpu_ssifss;
cpu_ssitx2 <= cpu_ssitx;
cpu_ssiclk2 <= cpu_ssiclk;
cpu_ssifss3 <= cpu_ssifss2;
cpu_ssitx3 <= cpu_ssitx2;
cpu_ssiclk3 <= cpu_ssiclk2;
if xx_buf_last /= yy_buf_last then
led_off(3) <= '0';
end if;
end process;
-- Every 20 cycles pick up a multifilter output. phase_strobe is a
-- convenient strobe for that.
process
begin
wait until rising_edge(clk_main);
if phase_strobe = '1' then
case pll_decay(5 downto 4) is
when "00" =>
xy_data(30 downto 0) <= unsigned(xx_buf(35 downto 5));
when "01" =>
xy_data(30 downto 0) <= unsigned(yy_buf(35 downto 5));
when others =>
xy_data(14 downto 0) <= unsigned(xx_buf(35 downto 21));
xy_data(15) <= '0';
xy_data(30 downto 16) <= unsigned(yy_buf(35 downto 21));
end case;
xy_last <= xx_buf_last;
end if;
xy_strobe <= phase_strobe;
end process;
-- DDR input from ADC.
adc_input: for i in 0 to 6 generate
adc_in: ibufds generic map (diff_term => true)
port map (I => adc_n(i), IB => adc_p(i), O => adc_ddr(i));
adc_ddr_expand: IDDR2
generic map (ddr_alignment => "C0")
port map (C0 => clk_main, C1 => clk_main_neg,
CE => '1',
D => adc_ddr(i),
Q0 => adc_data(i*2+1), Q1 => adc_data(i*2));
end generate;
-- Clk input from ADC. The ADC drives the data as even on P-falling followed
-- by odd on P-rising.
adc_reclk_in: IBUFGDS
generic map (diff_term => true)
port map(I => adc_reclk_n, IB => adc_reclk_p, O => adc_reclk_b);
-- Are these needed? Do we need to tie them together?
adc_reclk_buf: BUFIO2
port map(I => adc_reclk_b, DIVCLK => adc_reclk,
IOCLK => open, SERDESSTROBE => open);
adc_reclkfb: BUFIO2FB port map(I => clk_main_neg, O => clk_main_fb);
-- Pseudo differential drive of clock to ADC.
adc_clk_ddr_p : oddr2
port map (D0 => '1', D1 => '0', C0 => adc_clk, C1 => adc_clk_neg,
Q => adc_clk_p);
adc_clk_ddr_n : oddr2
port map (D0 => '0', D1 => '1', C0 => adc_clk, C1 => adc_clk_neg,
Q => adc_clk_n);
-- Regenerate the clock from the ADC.
-- We run the PLL oscillator at 1000MHz, i.e., 4 times the input clock.
clk_main_pll : PLL_BASE
generic map(
CLK_FEEDBACK => "CLKOUT0",
DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 1,
CLKOUT0_DIVIDE => 4,
CLKOUT1_DIVIDE => 4, CLKOUT1_PHASE => 180.0,
CLKOUT2_DIVIDE => 20, CLKOUT2_PHASE => 36.0,
CLKIN_PERIOD => 4.0)
port map(
-- Output clocks
CLKFBIN => clk_main_fb,
CLKOUT0 => clku_main_neg, CLKOUT1 => clku_main, CLKOUT2 => clku_50m,
RST => '0', LOCKED => clk_main_locked,
CLKIN => adc_reclk);
clk_main_bufg : BUFG port map(I => clku_main, O => clk_main);
clk_main_neg_bufg : BUFG port map(I => clku_main_neg, O => clk_main_neg);
clk_50m_bufg : BUFG port map(I => clku_50m, O => clk_50m);
clkin125_bufg : bufg port map(I => clkin125, O => clkin125_b);
-- Generate the clock to the ADC. We run the PLL oscillator at 1000MHz, (8
-- times the input clock), and then generate a 250MHz output.
adc_clk_pll : PLL_BASE
generic map(
BANDWIDTH => "LOW",
CLK_FEEDBACK => "CLKFBOUT",
DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 8,
CLKOUT0_DIVIDE => 4,
CLKOUT1_DIVIDE => 4, CLKOUT1_PHASE => 180.000,
CLKOUT2_DIVIDE => 5,
CLKOUT3_DIVIDE => 5, CLKOUT3_PHASE => 180.000,
CLKIN_PERIOD => 8.0)
port map(
-- Output clocks
CLKFBIN => adc_clk_fb, CLKFBOUT => adc_clk_fb,
CLKOUT0 => adc_clk_250,CLKOUT1 => adc_clk_neg_250,
CLKOUT2 => adc_clk_200,CLKOUT3 => adc_clk_neg_200,
RST => '0', LOCKED => adc_clk_locked,
CLKIN => clkin125_b);
adc_clk_bufg : BUFGMUX port map (
I0 => adc_clk_250, I1 => adc_clk_200, S => clock_select, O => adc_clk);
adc_clk_neg_bufg : BUFGMUX port map (
I0 => adc_clk_neg_250, I1 => adc_clk_neg_200,
S => clock_select, O => adc_clk_neg);
end go;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.