content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipelin... |
-------------------------------------------------------------------------------
-- Title : Direct Digital Synthesis
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : DDS with RAM Table, Table can be defined over MM Interface
-- The ... |
entity test is
end test;
architecture only of test is
type my_type is array(0 to 3) of integer;
begin -- only
p: process
begin -- process p
assert my_type'left = 0 report "TEST FAILED left = 0" severity failure;
report "TEST PASSED left = 0";
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type my_type is array(0 to 3) of integer;
begin -- only
p: process
begin -- process p
assert my_type'left = 0 report "TEST FAILED left = 0" severity failure;
report "TEST PASSED left = 0";
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type my_type is array(0 to 3) of integer;
begin -- only
p: process
begin -- process p
assert my_type'left = 0 report "TEST FAILED left = 0" severity failure;
report "TEST PASSED left = 0";
wait;
end process p;
end only;
|
library ieee;
use ieee.std_logic_1164.all;
use work.graphics_types_pkg.all;
use work.sprites_pkg.all;
use work.colors_pkg.all;
use work.basic_types_pkg.all;
-- It is worth noting that the sprites engine should not (and does not) access
-- any game-specific constants or code. Therefore, it can be readily reused... |
-- file: Clock_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a... |
-- Company:
-- Engineer:
--
-- Create Date: 16:52:41 06/05/2016
-- Design Name:
-- Module Name: mem_control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 06/23/2008
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module CAMELLIA256
--
-- Copyright (C) 2007 Paolo... |
-- Copyright (c) 2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, pu... |
-- Copyright (c) 2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, pu... |
-- File: gray_counter_4.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_4 is
port (
gray_count: out unsigned(3 downto 0);
enable: in std_logi... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clk200Hz_tb IS
END clk200Hz_tb;
ARCHITECTURE behavior OF clk200Hz_tb IS
COMPONENT clk200Hz
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clk200Hz_tb IS
END clk200Hz_tb;
ARCHITECTURE behavior OF clk200Hz_tb IS
COMPONENT clk200Hz
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
... |
----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either versio... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------[01.11.2014]
-- Encoder
-------------------------------------------------------------------------------
-- V1.0 03.08.2014 Initial release
-- V2.0 01.11.2014 Added AUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entit... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb is
port(
--Clock and Reset
clk : in std_logic;
reset_n : in std_logic;
-- USB Conduit interface to DE2 (Export)
USB_DATA : inout std_logic_vector(15 downto 0);
USB_ADDR : out std_logic_vector(1 downto 0);
USB_WR_N : out st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pwm is
generic(
N: integer := 4
);
port(
clk: in std_logic;
value: in std_logic_vector(N-1 downto 0);
output: out std_logic
);
end pwm;
architecture pwm_arch of pwm is
signal accumula... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture RTL of FIFO is
subtype read_size is integer range 0 to 9;
-- Violations below
subtype read_size is integer range 0 to 9;
subtype read_size is integer range 0 to 9;
begin
end architecture RTL;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_TB
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Andrew Powell
--
-- Create Date: 08/02/2016 04:12:55 PM
-- Design Name:
-- Module Name: spi_cntrl_0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue414 is
end issue414;
architecture behavioral of issue414 is
signal clk : std_logic := '0';
signal addr : std_logic_vector(55 downto 0);
signal wdata : std_logic_vector(31 downto 0);
subtype uword64 is unsigned(63 downto 0);
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:52:18 11/16/2016
-- Design Name:
-- Module Name: bcdadder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
--/////////////////////////////////////////////////////////////////////////
--// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
--//
--// XILINX CONFIDENTIAL PROPERTY
--// This document contains proprietary information which is
--// protected by copyright. All rights are reserved. ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ganesh Hegde and Alex
--
-- Create Date: 09/01/2015 10:52:25 AM
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencie... |
{{define "top"}}-- This file has been automatically generated by goFB and should not be edited by hand
-- Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
-- VHDL support is EXPERIMENTAL ONLY
{{$block := index .Blocks .BlockIndex}}{{$blocks := .Blocks}}{{$specialIO := $block.GetSpecialIO .Block... |
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0 is
port(
clk_clk_clk : in vl_logic;
clocks_c0_clk : in vl_logic;
cpu_reset_n_reset_bridge_in_reset_reset: in vl_logic;
sdram_reset_reset_bridge_in_reset_reset: in vl_logic;
cp... |
----------------------------------------------------------------------------------
-- Company:
-- EngINeer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: KbdTxData
-- Target Devices:
-- Tool versions: XilINx ISE 14.4
-- Description... |
----------------------------------------------------------------------------------
-- Company:
-- EngINeer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: KbdTxData
-- Target Devices:
-- Tool versions: XilINx ISE 14.4
-- Description... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_1_block.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock1_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig ... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 14:41:49 2017
-- Host : EffulgentTome running 64-bit m... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
port (
clock_50MHz: in std_logic;
clock_25MHz: out std_logic;
clock_1MHz: out std_logic;
clock_500KHz: out std_logic;
clock_115200Hz: out std_logic
);
end clk... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--================================================================================================================================
-- Copyright (c) 2020 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the Apache License (see LICENSE.TXT), if not,
-- contact Bitvis A... |
-------------------------------------------------------------------------------
-- Demonstration using two SpW interfaces
---
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
librar... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 15-02-2016
-- Module Name: mux_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.al... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNIYBMGPQQ is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNIYBMGPQQ is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNIYBMGPQQ is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNIYBMGPQQ is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lcdctl is
Port ( clk,reset : in STD_LOGIC;
vramaddr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ud : out STD_LOGIC;
rl : out STD_LOGIC;
enab : out ST... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MODULOPRINCIPAL is
Port ( rst : in STD_LOGIC;
CLK : in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0));
end MODULOPRINCIPAL;
architecture Behavioral of MODULOPRINCIPAL is
COMPONENT PC
PORT(
rst : IN std_logic;
... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
library IEEE;
use IEEE.std_logic_1164.all;
package pkg3 is
component com5 is
--
end component com5;
end package pkg3;
|
package pkg_6502_opcodes is
type t_opcode_array is array(0 to 255) of string(1 to 13);
constant opcode_array : t_opcode_array := (
"BRK ", "ORA ($nn,X) ", "HLT* ", "ASO*($nn,X) ",
"BOT*$nn ", "ORA $nn ", "ASL $nn ", "ASO*$nn ",
"PHP ", "ORA # ... |
package pkg_6502_opcodes is
type t_opcode_array is array(0 to 255) of string(1 to 13);
constant opcode_array : t_opcode_array := (
"BRK ", "ORA ($nn,X) ", "HLT* ", "ASO*($nn,X) ",
"BOT*$nn ", "ORA $nn ", "ASL $nn ", "ASO*$nn ",
"PHP ", "ORA # ... |
-- ledblinker.vhd
--
-- Created on: 12 May 2017
-- Author: Fabian Meyer
--
-- LED blinker with configurable frequency.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ledblinker is
generic(RSTDEF: std_logic := '1');
port (rst: in std_logic; -- reset,... |
use WORK.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.debugtools.all;
entity iomapper is
port (Clk : in std_logic;
cpuclock : in std_logic;
pixelclk : in std_logic;
uartclock : in std_logic;
clock50mhz : in std_logic;
phi0 : in std_logic;... |
use WORK.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.debugtools.all;
entity iomapper is
port (Clk : in std_logic;
cpuclock : in std_logic;
pixelclk : in std_logic;
uartclock : in std_logic;
clock50mhz : in std_logic;
phi0 : in std_logic;... |
use WORK.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.debugtools.all;
entity iomapper is
port (Clk : in std_logic;
cpuclock : in std_logic;
pixelclk : in std_logic;
uartclock : in std_logic;
clock50mhz : in std_logic;
phi0 : in std_logic;... |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the follow... |
architecture RTL of FIFO is
begin
process
begin
for_label : for index in 4 to 23 loop
end loop;
for_label : for index in 4 to 23 loop
end loop;
for_label : for index in 4 to 23 loop
end loop;
end process;
end;
|
ENTITY insertionsort IS
-- empty
END insertionsort;
ARCHITECTURE verhalten OF insertionsort IS
TYPE string IS array(natural RANGE <>) OF character;
BEGIN
PROCESS
CONSTANT N: natural := 20;
VARIABLE a: string(0 TO N-1) := "P91fQeZB4KvTMcrEfzM4";
VARIABLE b: string(0 TO N-1) := "1449BEKMMPQ... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
termina... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode... |
package data_bus_pkg is
type data_bus_device_t is (
DEV_NONE
,DEV_PIO
,DEV_SPI
,DEV_AIC
,DEV_UART0
,DEV_UART1
,DEV_UARTGPS
,DEV_SRAM
,DEV_DDR
,DEV_BL0
,DEV_EMAC
,DEV_I2C
);
type ext_bus_device_t is (
DEV_BL0,
DEV_EMAC,
DEV_I2C,
DEV_DDR
... |
package data_bus_pkg is
type data_bus_device_t is (
DEV_NONE
,DEV_PIO
,DEV_SPI
,DEV_AIC
,DEV_UART0
,DEV_UART1
,DEV_UARTGPS
,DEV_SRAM
,DEV_DDR
,DEV_BL0
,DEV_EMAC
,DEV_I2C
);
type ext_bus_device_t is (
DEV_BL0,
DEV_EMAC,
DEV_I2C,
DEV_DDR
... |
package data_bus_pkg is
type data_bus_device_t is (
DEV_NONE
,DEV_PIO
,DEV_SPI
,DEV_AIC
,DEV_UART0
,DEV_UART1
,DEV_UARTGPS
,DEV_SRAM
,DEV_DDR
,DEV_BL0
,DEV_EMAC
,DEV_I2C
);
type ext_bus_device_t is (
DEV_BL0,
DEV_EMAC,
DEV_I2C,
DEV_DDR
... |
-------------------------------------------------------------------------------
-- Title : rmii_transceiver_tb
-- Author : Gideon Zweijtzer (gideon.zweijtzer@gmail.com)
-------------------------------------------------------------------------------
-- Description: Testbench for rmii transceiver
---------------... |
-- file: nregister.vhd
-------------------------------------
-- n bit register for use in carry save counter
-- Shauna Rae
-- October 4, 1999
library ieee;
use ieee.std_logic_1164.all;
-- component nregister is
-- generic (data_width : positive := 16);
--- port(clock, reset : in ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library ... |
entity sub is
generic ( NUM : integer );
port ( s : in bit );
end entity;
architecture test of sub is
begin
process is
begin
wait for (NUM * 10 ns) + 1 ns;
assert s = '1';
wait;
end process;
end architecture;
---------------------------------------------------------------... |
entity sub is
generic ( NUM : integer );
port ( s : in bit );
end entity;
architecture test of sub is
begin
process is
begin
wait for (NUM * 10 ns) + 1 ns;
assert s = '1';
wait;
end process;
end architecture;
---------------------------------------------------------------... |
entity sub is
generic ( NUM : integer );
port ( s : in bit );
end entity;
architecture test of sub is
begin
process is
begin
wait for (NUM * 10 ns) + 1 ns;
assert s = '1';
wait;
end process;
end architecture;
---------------------------------------------------------------... |
entity sub is
generic ( NUM : integer );
port ( s : in bit );
end entity;
architecture test of sub is
begin
process is
begin
wait for (NUM * 10 ns) + 1 ns;
assert s = '1';
wait;
end process;
end architecture;
---------------------------------------------------------------... |
entity sub is
generic ( NUM : integer );
port ( s : in bit );
end entity;
architecture test of sub is
begin
process is
begin
wait for (NUM * 10 ns) + 1 ns;
assert s = '1';
wait;
end process;
end architecture;
---------------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
entity circular_queue_tb is
end;
architecture behavioural of circular_queue_tb is
constant queue_depth : integer := 2;
signal ctrl : ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY servo_pwm_contador_clk64kHz_tb IS
END servo_pwm_contador_clk64kHz_tb;
ARCHITECTURE behavior OF servo_pwm_contador_clk64kHz_tb IS
-- Unidad bajo prueba.
COMPONENT servo_pwm_contador_clk64kHz
PORT(
clk : IN std_logic;
reset : IN std_logic;
cnt_up: IN ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY servo_pwm_contador_clk64kHz_tb IS
END servo_pwm_contador_clk64kHz_tb;
ARCHITECTURE behavior OF servo_pwm_contador_clk64kHz_tb IS
-- Unidad bajo prueba.
COMPONENT servo_pwm_contador_clk64kHz
PORT(
clk : IN std_logic;
reset : IN std_logic;
cnt_up: IN ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity top is
port(
clk : in std_logic;
btn_north_i : in std_logic;
-- LCD Interface
lcd_db_io : inout std_logic_vector(7 downto 0);
lcd_rs_o : out std_logic;
... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_1_block6.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ----------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_external_wb8 is
generic(
ADDRBITS: integer := 19;
DATABITS: integer := 8
);
port(
-- signal naming according to Wishbone B4 spec
CLK_I: in std_logic;
STB_I: in std_logic;
WE_I: in std_logic;
ADR_I: in std_logic_vector(AD... |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : arg_mem_bank_v6.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 201... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- -*- vhdl -*-
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pyvivado_utils.all;
entity CombMinimumNonZeroRemainder is
generic (
WIDTH: integer;
N_INPUTS: integer;
INPUT_ADDRESS_WIDTH: integer := 0
);
port (
i_data: in std_logic_vector(N_INPUTS*WIDTH-1 downto... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.all;
use work.defs.all;
entity go is
port(adc_p : in unsigned7;
adc_n : in unsigned7;
adc_clk_p : out std_logic;
adc_clk_n : out std_logic;
adc_reclk_p... |
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