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------------------------------------------------------------
-- mini-projet VHDL
-- Le testBench du systemE de simulation d'un VGA
-- Elhamer Oussama abdelkhalek
-- après 1 ms le système declanche en mettant Reset a '0'
------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY VGA_Simulator_TB IS
END VGA_Simulator_TB;
ARCHITECTURE behavior OF VGA_Simulator_TB IS
COMPONENT VGA_SIMULATOR
PORT(
Reset : IN std_logic;
H_SYNC : INOUT std_logic;
V_SYNC : INOUT std_logic
);
END COMPONENT;
signal Reset : std_logic := '1' ;
signal H_SYNC : std_logic := '0';
signal V_SYNC : std_logic := '0';
BEGIN
uut: VGA_SIMULATOR PORT MAP (
Reset => Reset,
H_SYNC => H_SYNC,
V_SYNC => V_SYNC
);
-- Processus de simulation
proc_simulation: process (Reset)
begin
Reset <= '0' after 1ms ;
--Reset <= '1' after 16.223ms; -- the time to get one picture
end process;
END;
|
--
-- GPIOs on DE10-Nano
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Top is
port (
dips_i : in std_logic_vector(3 downto 0);
pbs_i : in std_logic_vector(1 downto 0);
leds_o : out std_logic_vector(7 downto 0)
);
end entity Top;
architecture RTL of Top is
begin
leds_o <= not(pbs_i) & pbs_i & dips_i;
end architecture RTL;
|
-- NEED RESULT: ARCH00381.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P11: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P12: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P13: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P14: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P15: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P16: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P17: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P17: Inertial transactions completed entirely passed
-- NEED RESULT: P16: Inertial transactions completed entirely passed
-- NEED RESULT: P15: Inertial transactions completed entirely passed
-- NEED RESULT: P14: Inertial transactions completed entirely passed
-- NEED RESULT: P13: Inertial transactions completed entirely passed
-- NEED RESULT: P12: Inertial transactions completed entirely passed
-- NEED RESULT: P11: Inertial transactions completed entirely passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00381
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00381(ARCH00381)
-- ENT00381_Test_Bench(ARCH00381_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00381 is
end ENT00381 ;
--
--
architecture ARCH00381 of ENT00381 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <=
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <=
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 4 ;
-- s_boolean <=
-- c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 5 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 6 ;
-- Last transaction above is marked
-- s_boolean <=
-- c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
wait until (not s_boolean'Quiet) and
(s_boolean_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with boolean_select select
s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when 1,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 2,
--
c_boolean_1 after 5 ns
when 3,
--
c_boolean_1 after 100 ns
when 4,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_boolean_1 after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <=
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <=
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 4 ;
-- s_bit <=
-- c_bit_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 5 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 6 ;
-- Last transaction above is marked
-- s_bit <=
-- c_bit_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
wait until (not s_bit'Quiet) and
(s_bit_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with bit_select select
s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when 1,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 2,
--
c_bit_1 after 5 ns
when 3,
--
c_bit_1 after 100 ns
when 4,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_bit_1 after 40 ns when 6 ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <=
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 4 ;
-- s_severity_level <=
-- c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 5 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 6 ;
-- Last transaction above is marked
-- s_severity_level <=
-- c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
wait until (not s_severity_level'Quiet) and
(s_severity_level_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with severity_level_select select
s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when 1,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 2,
--
c_severity_level_1 after 5 ns
when 3,
--
c_severity_level_1 after 100 ns
when 4,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_severity_level_1 after 40 ns when 6 ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <=
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <=
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 4 ;
-- s_character <=
-- c_character_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 5 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 6 ;
-- Last transaction above is marked
-- s_character <=
-- c_character_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
wait until (not s_character'Quiet) and
(s_character_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with character_select select
s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns
when 1,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 2,
--
c_character_1 after 5 ns
when 3,
--
c_character_1 after 100 ns
when 4,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_character_1 after 40 ns when 6 ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 4 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 5 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1 <=
-- c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
wait until (not s_st_enum1'Quiet) and
(s_st_enum1_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_enum1_select select
s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when 1,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 2,
--
c_st_enum1_1 after 5 ns
when 3,
--
c_st_enum1_1 after 100 ns
when 4,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_enum1_1 after 40 ns when 6 ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <=
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <=
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 4 ;
-- s_integer <=
-- c_integer_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 5 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 6 ;
-- Last transaction above is marked
-- s_integer <=
-- c_integer_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
wait until (not s_integer'Quiet) and
(s_integer_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with integer_select select
s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when 1,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 2,
--
c_integer_1 after 5 ns
when 3,
--
c_integer_1 after 100 ns
when 4,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_integer_1 after 40 ns when 6 ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <=
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 4 ;
-- s_st_int1 <=
-- c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 5 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_int1 <=
-- c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
wait until (not s_st_int1'Quiet) and
(s_st_int1_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_int1_select select
s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when 1,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 2,
--
c_st_int1_1 after 5 ns
when 3,
--
c_st_int1_1 after 100 ns
when 4,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_int1_1 after 40 ns when 6 ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <=
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <=
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 4 ;
-- s_time <=
-- c_time_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 5 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 6 ;
-- Last transaction above is marked
-- s_time <=
-- c_time_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
wait until (not s_time'Quiet) and
(s_time_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with time_select select
s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns
when 1,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 2,
--
c_time_1 after 5 ns
when 3,
--
c_time_1 after 100 ns
when 4,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_time_1 after 40 ns when 6 ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 4 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 5 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_phys1 <=
-- c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
wait until (not s_st_phys1'Quiet) and
(s_st_phys1_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_phys1_select select
s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when 1,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 2,
--
c_st_phys1_1 after 5 ns
when 3,
--
c_st_phys1_1 after 100 ns
when 4,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_phys1_1 after 40 ns when 6 ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <=
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <=
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 4 ;
-- s_real <=
-- c_real_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 5 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 6 ;
-- Last transaction above is marked
-- s_real <=
-- c_real_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
wait until (not s_real'Quiet) and
(s_real_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with real_select select
s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns
when 1,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 2,
--
c_real_1 after 5 ns
when 3,
--
c_real_1 after 100 ns
when 4,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_real_1 after 40 ns when 6 ;
--
CHG11 :
process
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P11" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <=
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 4 ;
-- s_st_real1 <=
-- c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 5 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real1 <=
-- c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
wait until (not s_st_real1'Quiet) and
(s_st_real1_savt /= Std.Standard.Now) ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions completed entirely",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
with st_real1_select select
s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when 1,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 2,
--
c_st_real1_1 after 5 ns
when 3,
--
c_st_real1_1 after 100 ns
when 4,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_real1_1 after 40 ns when 6 ;
--
CHG12 :
process
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P12" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 4 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 5 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1 <=
-- c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
wait until (not s_st_rec1'Quiet) and
(s_st_rec1_savt /= Std.Standard.Now) ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions completed entirely",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
with st_rec1_select select
s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when 1,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 2,
--
c_st_rec1_1 after 5 ns
when 3,
--
c_st_rec1_1 after 100 ns
when 4,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec1_1 after 40 ns when 6 ;
--
CHG13 :
process
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P13" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 4 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 5 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2 <=
-- c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
wait until (not s_st_rec2'Quiet) and
(s_st_rec2_savt /= Std.Standard.Now) ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions completed entirely",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
with st_rec2_select select
s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when 1,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 2,
--
c_st_rec2_1 after 5 ns
when 3,
--
c_st_rec2_1 after 100 ns
when 4,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec2_1 after 40 ns when 6 ;
--
CHG14 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P14" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3 <=
-- c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
with st_rec3_select select
s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when 1,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 2,
--
c_st_rec3_1 after 5 ns
when 3,
--
c_st_rec3_1 after 100 ns
when 4,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec3_1 after 40 ns when 6 ;
--
CHG15 :
process
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P15" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 4 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 5 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr1 <=
-- c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
wait until (not s_st_arr1'Quiet) and
(s_st_arr1_savt /= Std.Standard.Now) ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions completed entirely",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
with st_arr1_select select
s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when 1,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 2,
--
c_st_arr1_1 after 5 ns
when 3,
--
c_st_arr1_1 after 100 ns
when 4,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr1_1 after 40 ns when 6 ;
--
CHG16 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P16" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2 <=
-- c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
with st_arr2_select select
s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when 1,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 2,
--
c_st_arr2_1 after 5 ns
when 3,
--
c_st_arr2_1 after 100 ns
when 4,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_1 after 40 ns when 6 ;
--
CHG17 :
process
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P17" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 4 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 5 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr3 <=
-- c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
wait until (not s_st_arr3'Quiet) and
(s_st_arr3_savt /= Std.Standard.Now) ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions completed entirely",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
with st_arr3_select select
s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when 1,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 2,
--
c_st_arr3_1 after 5 ns
when 3,
--
c_st_arr3_1 after 100 ns
when 4,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr3_1 after 40 ns when 6 ;
--
end ARCH00381 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00381_Test_Bench is
end ENT00381_Test_Bench ;
--
--
architecture ARCH00381_Test_Bench of ENT00381_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00381 ( ARCH00381 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00381_Test_Bench ;
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_PHASE_n.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_PHASE_n IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_PHASE_n;
ARCHITECTURE SYN OF ram_dq_phase_n IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_n",
lpm_type => "altsyncram",
numwords_a => 32,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 5,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "PH_n"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_n"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_PHASE_n.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_PHASE_n IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_PHASE_n;
ARCHITECTURE SYN OF ram_dq_phase_n IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_n",
lpm_type => "altsyncram",
numwords_a => 32,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 5,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "PH_n"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_n"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1860.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01860ent IS
END c07s01b00x00p08n01i01860ent;
ARCHITECTURE c07s01b00x00p08n01i01860arch OF c07s01b00x00p08n01i01860ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
BEGIN
TESTING : PROCESS
BEGIN
lop : for i in small_int loop
obus(lop) <= 5 after 5 ns;
end loop lop;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01860 - Loop labels are not permitted as primaries in an index expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01860arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1860.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01860ent IS
END c07s01b00x00p08n01i01860ent;
ARCHITECTURE c07s01b00x00p08n01i01860arch OF c07s01b00x00p08n01i01860ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
BEGIN
TESTING : PROCESS
BEGIN
lop : for i in small_int loop
obus(lop) <= 5 after 5 ns;
end loop lop;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01860 - Loop labels are not permitted as primaries in an index expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01860arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1860.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01860ent IS
END c07s01b00x00p08n01i01860ent;
ARCHITECTURE c07s01b00x00p08n01i01860arch OF c07s01b00x00p08n01i01860ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
BEGIN
TESTING : PROCESS
BEGIN
lop : for i in small_int loop
obus(lop) <= 5 after 5 ns;
end loop lop;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01860 - Loop labels are not permitted as primaries in an index expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01860arch;
|
--Libraries imports
library ieee;
use ieee.std_logic_1164.all;
--Entity declaration
ENTITY minNbits IS
GENERIC(
N : IN NATURAL := 16
);
PORT(
A : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END;
--Architecture behavior
ARCHITECTURE behavior OF minNbits IS
COMPONENT NotNbit IS
GENERIC(
N : IN NATURAL := 16
);
PORT(
A : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT faG IS
GENERIC(
N : IN NATURAL := 16
);
PORT(
A,B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
Cin : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);
Cout : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL tempA, tempB : STD_LOGIC_VECTOR(N-1 DOWNTO 0);
SIGNAL tempCo : STD_LOGIC;
BEGIN
NotB : NotNbit GENERIC MAP (N) PORT MAP (A, tempA);
tempB(N-1 DOWNTO 1) <= (OTHERS => '0');
tempB(0) <= '1';
add : faG GENERIC MAP (N) PORT MAP (tempA, tempB, '0', S, tempCo);
END;
|
library ieee;
use ieee.std_logic_1164.all;
entity topo is
port (SW : IN STD_LOGIC_VECTOR(9 downto 0);
LEDR : OUT STD_LOGIC_VECTOR(9 downto 0)
);
end topo;
architecture topo_estru of topo is
signal C1, C2, C3, C4: std_logic;
component HA
port (A : in std_logic;
B : in std_logic;
COUT : out std_logic;
S : out std_logic);
end component;
component FA
port (A : in std_logic;
B : in std_logic;
C : in std_logic;
COUT : out std_logic;
S : out std_logic);
end component;
component FA2
port (A : in std_logic;
B : in std_logic;
C : in std_logic;
COUT : out std_logic;
S : out std_logic);
end component;
component FA3
port (A : in std_logic;
B : in std_logic;
C : in std_logic;
COUT : out std_logic;
S : out std_logic);
end component;
begin
L0: HA port map (SW(1), SW(0), C1, LEDR(0));
L1: FA port map (SW(3), SW(2), C1, C2, LEDR(1));
L2: FA port map (SW(5), SW(4), C2, C3, LEDR(2));
L3: FA port map (SW(7), SW(6), C3, LEDR(4), LEDR(3));
end topo_estru;
|
package pkg_FileIO is
-------------------------------
-- Define some basic data types
-------------------------------
subtype t_BYTE is integer range 0 to 2**8 - 1;
---------------------------------------
-- And arrays of those basic data types
---------------------------------------
type arr_t_BYTE is array(natural range <>) of t_BYTE;
----------------------------
-- And a pointer to an array
----------------------------
type ptr_arr_t_BYTE is access arr_t_BYTE;
procedure Read_File(File_Name: in STRING; Data: inout ptr_arr_t_BYTE; Length: out integer);
end pkg_FileIO;
package body pkg_FileIO is
procedure Read_File(File_Name: in STRING; Data: inout ptr_arr_t_BYTE; Length: out integer) is
begin
Data := new arr_t_BYTE(0 to 10);
for i in 0 to 10 loop
Data(i) := 0; -- Comment this line out and GHDL is happy
end loop;
Length := 11;
end Read_File;
end pkg_FileIO;
|
package pkg_FileIO is
-------------------------------
-- Define some basic data types
-------------------------------
subtype t_BYTE is integer range 0 to 2**8 - 1;
---------------------------------------
-- And arrays of those basic data types
---------------------------------------
type arr_t_BYTE is array(natural range <>) of t_BYTE;
----------------------------
-- And a pointer to an array
----------------------------
type ptr_arr_t_BYTE is access arr_t_BYTE;
procedure Read_File(File_Name: in STRING; Data: inout ptr_arr_t_BYTE; Length: out integer);
end pkg_FileIO;
package body pkg_FileIO is
procedure Read_File(File_Name: in STRING; Data: inout ptr_arr_t_BYTE; Length: out integer) is
begin
Data := new arr_t_BYTE(0 to 10);
for i in 0 to 10 loop
Data(i) := 0; -- Comment this line out and GHDL is happy
end loop;
Length := 11;
end Read_File;
end pkg_FileIO;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc700.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:06 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00700ent IS
END c03s04b01x00p23n01i00700ent;
ARCHITECTURE c03s04b01x00p23n01i00700arch OF c03s04b01x00p23n01i00700ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of NATURAL;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.08";
-- Declare a variable.
constant CON : NATURAL := 1;
variable VAR : NATURAL := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00700 - The output file will tested by test file s010432.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00700arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc700.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:06 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00700ent IS
END c03s04b01x00p23n01i00700ent;
ARCHITECTURE c03s04b01x00p23n01i00700arch OF c03s04b01x00p23n01i00700ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of NATURAL;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.08";
-- Declare a variable.
constant CON : NATURAL := 1;
variable VAR : NATURAL := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00700 - The output file will tested by test file s010432.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00700arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc700.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:06 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00700ent IS
END c03s04b01x00p23n01i00700ent;
ARCHITECTURE c03s04b01x00p23n01i00700arch OF c03s04b01x00p23n01i00700ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of NATURAL;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.08";
-- Declare a variable.
constant CON : NATURAL := 1;
variable VAR : NATURAL := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00700 - The output file will tested by test file s010432.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00700arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:01:04 12/13/2009
-- Design Name:
-- Module Name: rsa_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- synthesis translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.all;
-- synthesis translate_on
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rsa_top is
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
start_in : in std_logic;
x : in std_logic_vector(15 downto 0); -- estos 3 son x^y mod m
y : in std_logic_vector(15 downto 0);
m : in std_logic_vector(15 downto 0);
r_c : in std_logic_vector(15 downto 0); --constante de montgomery r^2 mod m
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic;
bit_size : in std_logic_vector(15 downto 0) --tamano bit del exponente y (log2(y))
);
end rsa_top;
architecture Behavioral of rsa_top is
component n_c_core
port (clk : in std_logic;
m_lsw : in std_logic_vector(15 downto 0);
ce : in std_logic;
n_c : out std_logic_vector(15 downto 0);
done : out std_logic
);
end component;
--Multiplicador de Montgomery que sera instanciado 2 veces
component montgomery_mult
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic -- es le valid out TODO : cambiar nombre
);
end component;
--Memoria para guardar el exponente y el modulo
component Mem_b
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(15 downto 0);
douta : out std_logic_vector(15 downto 0));
end component;
--fifos para los resultados de las mult parciales
component res_out_fifo
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
signal valid_in_mon_1, valid_in_mon_2, valid_out_mon_1, valid_out_mon_2, fifo_1_rd, fifo_1_wr : std_logic;
signal a_mon_1, b_mon_1, n_mon_1, s_p_mon_1, s_out_mon_1, a_mon_2, b_mon_2, n_mon_2, s_p_mon_2, s_out_mon_2, fifo_1_in, fifo_2_in, fifo_1_out, exp_out, n_out : std_logic_vector(15 downto 0);
signal fifo_out, fifo_in : std_logic_vector(31 downto 0);
signal addr_exp, addr_n, next_addr_exp, next_addr_n : std_logic_vector(5 downto 0);
type state_type is (wait_start, prepare_data, wait_constants, writting_cts_fifo, processing_data_0, processing_data_1, wait_results, transition, prepare_next, writting_results, final_mult, show_final, prepare_final, wait_final);
signal state, next_state : state_type;
signal w_numb, next_w_numb : std_logic_vector(7 downto 0);
--Señales registradas
signal n_c_reg, next_n_c_reg : std_logic_vector(15 downto 0);
--Cuenta los datos que se van metiendo al multiplicador para generar el padding por si solo.
signal count_input, next_count_input, bit_counter, next_bit_counter : std_logic_vector(15 downto 0);
signal bsize_reg, next_bsize_reg : std_logic_vector (15 downto 0);
signal write_b_n : std_logic_vector(0 downto 0);
signal n_c_o : std_logic_vector(15 downto 0);
signal n_c : std_logic_vector(15 downto 0);
signal n_c_load : std_logic;
begin
n_c1 : n_c_core
port map (
clk => clk,
m_lsw => m,
ce => start_in,
n_c => n_c_o,
done => n_c_load
);
mon_1 : montgomery_mult port map(
clk => clk,
reset => reset,
valid_in => valid_in_mon_1,
a => a_mon_1,
b => b_mon_1,
n => n_mon_1,
s_prev => s_p_mon_1,
n_c => n_c_reg,
s => s_out_mon_1,
valid_out => valid_out_mon_1
);
mon_2 : montgomery_mult port map(
clk => clk,
reset => reset,
valid_in => valid_in_mon_2,
a => a_mon_2,
b => b_mon_2,
n => n_mon_2,
s_prev => s_p_mon_2,
n_c => n_c_reg,
s => s_out_mon_2,
valid_out => valid_out_mon_2
);
fifo_mon_out : res_out_fifo
port map (
clk => clk,
rst => reset,
din => fifo_in,
wr_en => fifo_1_wr,
rd_en => fifo_1_rd,
dout => fifo_out
);
exp : Mem_b port map (
clka => clk,
wea => write_b_n,
addra => addr_exp,
dina => y,
douta => exp_out);
n_mod : Mem_b port map (
clka => clk,
wea => write_b_n,
addra => addr_n,
dina => m,
douta => n_out);
process(clk, reset)
begin
if(clk = '1' and clk'event) then
if(reset = '1')then
state <= wait_start;
n_c_reg <= (others => '0');
w_numb <= (others => '0');
count_input <= (others => '0');
addr_exp <= (others => '0');
addr_n <= (others => '0');
bit_counter <= (others => '0');
bsize_reg <= (others => '0');
n_c <= (others => '0');
else
if(n_c_load = '1') then
n_c <= n_c_o;
end if;
state <= next_state;
n_c_reg <= next_n_c_reg;
w_numb <= next_w_numb;
count_input <= next_count_input;
addr_exp <= next_addr_exp;
addr_n <= next_addr_n;
bit_counter <= next_bit_counter;
bsize_reg <= next_bsize_reg;
end if;
end if;
end process;
process(state, bsize_reg, n_c_reg, valid_in, x, n_c, r_c, m, y, w_numb, count_input, addr_exp, addr_n, s_out_mon_1, s_out_mon_2, bit_size, valid_out_mon_1, bit_counter, exp_out, fifo_out, n_out)
variable mask : std_logic_vector(3 downto 0);
begin
--Registers update
next_state <= state;
next_n_c_reg <= n_c_reg;
next_w_numb <= w_numb;
next_count_input <= count_input;
next_bsize_reg <= bsize_reg;
--Entradas de los montgomerys.
valid_in_mon_1 <= '0';
valid_in_mon_2 <= '0';
a_mon_1 <= (others => '0');
b_mon_1 <= (others => '0');
n_mon_1 <= (others => '0');
a_mon_2 <= (others => '0');
b_mon_2 <= (others => '0');
n_mon_2 <= (others => '0');
s_p_mon_1 <= (others => '0');
s_p_mon_2 <= (others => '0');
--Control de las fifos
fifo_1_rd <= '0';
fifo_in <= (others => '0');
fifo_1_wr <= '0';
--Control de memorias de exp y modulo
write_b_n <= b"0";
next_addr_exp <= addr_exp;
next_addr_n <= addr_n;
next_bit_counter <= bit_counter;
--Outputs
valid_out <= '0';
s <= (others => '0');
case state is
when wait_start =>
valid_in_mon_1 <= valid_in;
valid_in_mon_2 <= valid_in;
if(valid_in = '1') then
a_mon_1 <= x;
b_mon_1 <= r_c;
n_mon_1 <= m;
a_mon_2 <= x"0001";
b_mon_2 <= r_c;
n_mon_2 <= m;
next_w_numb <= x"23"; --Se extiende en 3 para poder usar las multiplicaciones modulares
next_n_c_reg <= n_c;
next_state <= prepare_data;
next_count_input <= x"0001";
write_b_n <= b"1"; --Notificamos que hay que guardar el exponente y modulo
next_addr_exp <= "000001";
next_addr_n <= "000001";
next_bsize_reg <= bit_size-1;
end if;
when prepare_data =>
next_count_input <= count_input+1;
valid_in_mon_1 <= '1';
valid_in_mon_2 <= '1';
--Esto es solo mientras los datos en la entrada son validos, cuando no lo son
--se meten 0s para la extension de 3 palabras en los montgomerys
if(valid_in = '1') then
a_mon_1 <= x;
b_mon_1 <= r_c;
n_mon_1 <= m;
b_mon_2 <= r_c;
n_mon_2 <= m;
write_b_n <= b"1";
next_addr_exp <= addr_exp+1;
next_addr_n <= addr_n+1;
end if;
if(count_input = w_numb) then
next_state <= wait_constants;
next_addr_n <= (others => '0');
next_addr_exp <= bsize_reg(9 downto 4);
--Decodificador para establecer la mascara
mask := bsize_reg(3 downto 0);
case (mask) is
when "0000" => next_bit_counter <= "0000000000000001";
when "0001" => next_bit_counter <= "0000000000000010";
when "0010" => next_bit_counter <= "0000000000000100";
when "0011" => next_bit_counter <= "0000000000001000";
when "0100" => next_bit_counter <= "0000000000010000";
when "0101" => next_bit_counter <= "0000000000100000";
when "0110" => next_bit_counter <= "0000000001000000";
when "0111" => next_bit_counter <= "0000000010000000";
when "1000" => next_bit_counter <= "0000000100000000";
when "1001" => next_bit_counter <= "0000001000000000";
when "1010" => next_bit_counter <= "0000010000000000";
when "1011" => next_bit_counter <= "0000100000000000";
when "1100" => next_bit_counter <= "0001000000000000";
when "1101" => next_bit_counter <= "0010000000000000";
when "1110" => next_bit_counter <= "0100000000000000";
when "1111" => next_bit_counter <= "1000000000000000";
when others =>
end case;
next_count_input <= (others => '0');
end if;
--Esperamos los valores validos de la salida de los montgomery
when wait_constants =>
--Comienzo a escribir en la fifo de datos
if(valid_out_mon_1 = '1') then
fifo_1_wr <= '1';
fifo_in <= s_out_mon_1 & s_out_mon_2;
next_count_input <= count_input+1;
next_state <= writting_cts_fifo;
end if;
--Escribimos las dos constantes iniciales en las fifos
when writting_cts_fifo =>
fifo_1_wr <= valid_out_mon_1;
next_count_input <= count_input+1;
if(count_input < x"20") then
fifo_in <= s_out_mon_1 & s_out_mon_2;
end if;
--Pedimos el siguiente input para la multiplicacion
if(valid_out_mon_1 = '0') then
next_count_input <= (others => '0');
next_state <= transition;
end if;
when transition =>
next_count_input <= count_input+1;
if(count_input > 2) then
next_count_input <= (others => '0');
--fifo_1_rd <= '1';
--next_addr_n <= addr_n+1;
if((bit_counter and exp_out) = x"0000") then
next_state <= processing_data_0;
else
next_state <= processing_data_1;
end if;
end if;
--se van ejecutando las multiplicaciones sucesivas
when processing_data_1 =>
if(count_input > x"0000")then
valid_in_mon_1 <= '1';
valid_in_mon_2 <= '1';
end if;
fifo_1_rd <= '1';
a_mon_1 <= fifo_out(31 downto 16);
b_mon_1 <= fifo_out(15 downto 0);
n_mon_1 <= n_out;
a_mon_2 <= fifo_out(31 downto 16);
b_mon_2 <= fifo_out(31 downto 16);
n_mon_2 <= n_out;
next_addr_n <= addr_n+1;
next_count_input <= count_input +1;
--Cuando llego al final cambio de estado a esperar resultados
if(count_input = w_numb) then
next_state <= wait_results;
end if;
when processing_data_0 =>
if(count_input > x"0000")then
valid_in_mon_1 <= '1';
valid_in_mon_2 <= '1';
end if;
fifo_1_rd <= '1';
a_mon_1 <= fifo_out(15 downto 0);
b_mon_1 <= fifo_out(15 downto 0);
n_mon_1 <= n_out;
a_mon_2 <= fifo_out(31 downto 16);
b_mon_2 <= fifo_out(15 downto 0);
n_mon_2 <= n_out;
next_addr_n <= addr_n+1;
next_count_input <= count_input +1;
--Cuando llego al final cambio de estado a esperar resultados
if(count_input = w_numb) then
next_state <= wait_results;
next_count_input <= (others => '0');
end if;
when wait_results =>
--Comienzo a escribir en la fifo de datos
if(valid_out_mon_1 = '1') then
fifo_1_wr <= '1';
fifo_in <= s_out_mon_2 & s_out_mon_1;
next_count_input <= x"0001";
next_state <= writting_results;
end if;
when writting_results =>
next_addr_n <= (others => '0');
fifo_1_wr <= valid_out_mon_1;
next_count_input <= count_input+1;
if(count_input < x"20") then
fifo_in <= s_out_mon_2 & s_out_mon_1;
end if;
--Pedimos el siguiente input para la multiplicacion
if(valid_out_mon_1 = '0') then
next_count_input <= (others => '0');
next_state <= prepare_next;
--Calculo del siguiente bit del exponente
--Shifto uno la mascara
next_bit_counter <= '0'&bit_counter(15 downto 1);
if(bit_counter = x"0001")
then
next_addr_exp <= addr_exp -1;
next_bit_counter <= "1000000000000000";
end if;
if((bit_counter = x"0001") and addr_exp = "000000000")
then
next_state <= final_mult;
next_count_input <= (others => '0');
next_addr_exp <= (others => '0');
end if;
end if;
when prepare_next =>
next_state <= transition;
next_count_input <= (others => '0');
fifo_1_rd <= '0';
when final_mult =>
next_count_input <= count_input+1;
if(count_input > 2) then
next_count_input <= (others => '0');
next_state <= prepare_final;
end if;
when prepare_final =>
if(count_input > x"0000")then
valid_in_mon_1 <= '1';
end if;
fifo_1_rd <= '1';
a_mon_1 <= fifo_out(15 downto 0);
if(count_input = x"0001") then
b_mon_1 <= x"0001";
end if;
n_mon_1 <= n_out;
next_addr_n <= addr_n+1;
next_count_input <= count_input +1;
--Cuando llego al final cambio de estado a esperar resultados
if(count_input = w_numb) then
next_state <= wait_final;
next_count_input <= (others => '0');
end if;
when wait_final =>
if(valid_out_mon_1 = '1') then
valid_out <= '1';
s <= s_out_mon_1;
next_state <= show_final;
next_count_input <= count_input +1;
end if;
when show_final =>
valid_out <= '1';
s <= s_out_mon_1;
next_count_input <= count_input +1;
--Cuando llego al final cambio de estado a esperar resultados
if(count_input = x"20") then
valid_out <= '0';
next_state <= wait_start;
end if;
end case;
end process;
end Behavioral;
|
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dpram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock1 : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => 10,
widthad_b => 10,
width_a => 4,
width_b => 4,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => wrclock,
data_a => data,
wren_a => wren,
address_b => rdaddress,
clock1 => rdclock,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "4"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_b 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dpram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- VHDL 93
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.example_vhd_pkg.all;
entity vhd_dut is
generic (
width : integer := 8;
addressWidth : integer := 8
);
port (
address : in std_ulogic_vector(addressWidth-1 downto 0);
writeEnable : in std_ulogic;
writeData : in std_ulogic_vector(width-1 downto 0);
readEnable : in std_ulogic;
readData : out std_ulogic_vector(width-1 downto 0);
clk : in std_ulogic;
rstn : in std_ulogic;
registers_i : in example_in_record_type;
registers_o : out example_out_record_type);
end vhd_dut;
architecture rtl of vhd_dut is
signal registers_i_i : example_in_record_type;
signal registers_o_i : example_out_record_type;
begin
process(clk, rstn)
begin
if rstn = '0' then
registers_o_i <= reset_example;
readData <= (others => '0');
elsif (clk = '1' and clk'event) then
registers_i_i <= registers_i;
if readEnable = '1' then
readData <= read_example(registers_i_i, registers_o_i, address);
elsif writeEnable = '1' then
registers_o_i <= write_example(writeData, address, registers_o_i);
end if;
-- If the design, as oppose of the CPU, wants to change the register values,
-- add code for it here.
end if;
end process;
registers_o <= registers_o_i;
end rtl;
|
-- VHDL 93
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.example_vhd_pkg.all;
entity vhd_dut is
generic (
width : integer := 8;
addressWidth : integer := 8
);
port (
address : in std_ulogic_vector(addressWidth-1 downto 0);
writeEnable : in std_ulogic;
writeData : in std_ulogic_vector(width-1 downto 0);
readEnable : in std_ulogic;
readData : out std_ulogic_vector(width-1 downto 0);
clk : in std_ulogic;
rstn : in std_ulogic;
registers_i : in example_in_record_type;
registers_o : out example_out_record_type);
end vhd_dut;
architecture rtl of vhd_dut is
signal registers_i_i : example_in_record_type;
signal registers_o_i : example_out_record_type;
begin
process(clk, rstn)
begin
if rstn = '0' then
registers_o_i <= reset_example;
readData <= (others => '0');
elsif (clk = '1' and clk'event) then
registers_i_i <= registers_i;
if readEnable = '1' then
readData <= read_example(registers_i_i, registers_o_i, address);
elsif writeEnable = '1' then
registers_o_i <= write_example(writeData, address, registers_o_i);
end if;
-- If the design, as oppose of the CPU, wants to change the register values,
-- add code for it here.
end if;
end process;
registers_o <= registers_o_i;
end rtl;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY ASTEROIDS IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ASTEROIDS;
ARCHITECTURE ASTEROIDS_arch OF ASTEROIDS IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ASTEROIDS_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ASTEROIDS_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ASTEROIDS_arch : ARCHITECTURE IS "ASTEROIDS,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ASTEROIDS_arch: ARCHITECTURE IS "ASTEROIDS,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=ASTEROIDS.mif,C_INIT_FILE=ASTEROIDS.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "ASTEROIDS.mif",
C_INIT_FILE => "ASTEROIDS.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END ASTEROIDS_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shifter is
port (
operation : in std_logic_vector(2 downto 0);
enable : in std_logic := '1'; -- instruction(1)
no_data_shift : in std_logic := '0';
c_in : in std_logic;
n_in : in std_logic;
z_in : in std_logic;
data_in : in std_logic_vector(7 downto 0);
c_out : out std_logic;
n_out : out std_logic;
z_out : out std_logic;
data_out : out std_logic_vector(7 downto 0) := X"00");
end shifter;
architecture gideon of shifter is
signal data_out_i : std_logic_vector(7 downto 0) := X"00";
signal zero : std_logic := '0';
signal oper4 : std_logic_vector(3 downto 0) := X"0";
begin
-- ASL $nn ROL $nn LSR $nn ROR $nn STX $nn LDX $nn DEC $nn INC $nn
with operation & no_data_shift select data_out_i <=
data_in(6 downto 0) & '0' when "0000",
data_in(6 downto 0) & c_in when "0010",
'0' & data_in(7 downto 1) when "0100",
c_in & data_in(7 downto 1) when "0110",
data_in - 1 when "1100",
data_in + 1 when "1110",
data_in when others;
zero <= '1' when data_out_i = X"00" else '0';
oper4 <= enable & operation;
with oper4 select c_out <=
data_in(7) when "1000" | "1001",
data_in(0) when "1010" | "1011",
c_in when others;
with oper4 select z_out <=
zero when "1000" | "1001" | "1010" | "1011" | "1101" | "1110" | "1111",
z_in when others;
with oper4 select n_out <=
data_out_i(7) when "1000" | "1001" | "1010" | "1011" | "1101" | "1110" | "1111",
n_in when others;
data_out <= data_out_i when enable='1' and no_data_shift='0' else data_in;
end gideon; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shifter is
port (
operation : in std_logic_vector(2 downto 0);
enable : in std_logic := '1'; -- instruction(1)
no_data_shift : in std_logic := '0';
c_in : in std_logic;
n_in : in std_logic;
z_in : in std_logic;
data_in : in std_logic_vector(7 downto 0);
c_out : out std_logic;
n_out : out std_logic;
z_out : out std_logic;
data_out : out std_logic_vector(7 downto 0) := X"00");
end shifter;
architecture gideon of shifter is
signal data_out_i : std_logic_vector(7 downto 0) := X"00";
signal zero : std_logic := '0';
signal oper4 : std_logic_vector(3 downto 0) := X"0";
begin
-- ASL $nn ROL $nn LSR $nn ROR $nn STX $nn LDX $nn DEC $nn INC $nn
with operation & no_data_shift select data_out_i <=
data_in(6 downto 0) & '0' when "0000",
data_in(6 downto 0) & c_in when "0010",
'0' & data_in(7 downto 1) when "0100",
c_in & data_in(7 downto 1) when "0110",
data_in - 1 when "1100",
data_in + 1 when "1110",
data_in when others;
zero <= '1' when data_out_i = X"00" else '0';
oper4 <= enable & operation;
with oper4 select c_out <=
data_in(7) when "1000" | "1001",
data_in(0) when "1010" | "1011",
c_in when others;
with oper4 select z_out <=
zero when "1000" | "1001" | "1010" | "1011" | "1101" | "1110" | "1111",
z_in when others;
with oper4 select n_out <=
data_out_i(7) when "1000" | "1001" | "1010" | "1011" | "1101" | "1110" | "1111",
n_in when others;
data_out <= data_out_i when enable='1' and no_data_shift='0' else data_in;
end gideon; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: mmuconfig
-- File: mmuconfig.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU types and constants
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
package mmuconfig is
constant M_CTX_SZ : integer := 8;
constant M_ENT_MAX : integer := 64;
constant XM_ENT_MAX_LOG : integer := log2(M_ENT_MAX);
constant M_ENT_MAX_LOG : integer := XM_ENT_MAX_LOG;
type mmu_idcache is (id_icache, id_dcache);
-- ##############################################################
-- 1.0 virtual address [sparc V8: p.243,Appx.H,Figure H-4]
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 24 23 18 17 12 11 0
constant VA_I1_SZ : integer := 8;
constant VA_I2_SZ : integer := 6;
constant VA_I3_SZ : integer := 6;
constant VA_I_SZ : integer := VA_I1_SZ+VA_I2_SZ+VA_I3_SZ;
constant VA_I_MAX : integer := 8;
constant VA_I1_U : integer := 31;
constant VA_I1_D : integer := 32-VA_I1_SZ;
constant VA_I2_U : integer := 31-VA_I1_SZ;
constant VA_I2_D : integer := 32-VA_I1_SZ-VA_I2_SZ;
constant VA_I3_U : integer := 31-VA_I1_SZ-VA_I2_SZ;
constant VA_I3_D : integer := 32-VA_I_SZ;
constant VA_I_U : integer := 31;
constant VA_I_D : integer := 32-VA_I_SZ;
constant VA_OFF_U : integer := 31-VA_I_SZ;
constant VA_OFF_D : integer := 0;
constant VA_OFFCTX_U : integer := 31;
constant VA_OFFCTX_D : integer := 0;
constant VA_OFFREG_U : integer := 31-VA_I1_SZ;
constant VA_OFFREG_D : integer := 0;
constant VA_OFFSEG_U : integer := 31-VA_I1_SZ-VA_I2_SZ;
constant VA_OFFSEG_D : integer := 0;
constant VA_OFFPAG_U : integer := 31-VA_I_SZ;
constant VA_OFFPAG_D : integer := 0;
-- 8k pages
-- 7 6 6 13
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 25 24 19 18 13 12 0
constant P8K_VA_I1_SZ : integer := 7;
constant P8K_VA_I2_SZ : integer := 6;
constant P8K_VA_I3_SZ : integer := 6;
constant P8K_VA_I_SZ : integer := P8K_VA_I1_SZ+P8K_VA_I2_SZ+P8K_VA_I3_SZ;
constant P8K_VA_I_MAX : integer := 7;
constant P8K_VA_I1_U : integer := 31;
constant P8K_VA_I1_D : integer := 32-P8K_VA_I1_SZ;
constant P8K_VA_I2_U : integer := 31-P8K_VA_I1_SZ;
constant P8K_VA_I2_D : integer := 32-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_VA_I3_U : integer := 31-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_VA_I3_D : integer := 32-P8K_VA_I_SZ;
constant P8K_VA_I_U : integer := 31;
constant P8K_VA_I_D : integer := 32-P8K_VA_I_SZ;
constant P8K_VA_OFF_U : integer := 31-P8K_VA_I_SZ;
constant P8K_VA_OFF_D : integer := 0;
constant P8K_VA_OFFCTX_U : integer := 31;
constant P8K_VA_OFFCTX_D : integer := 0;
constant P8K_VA_OFFREG_U : integer := 31-P8K_VA_I1_SZ;
constant P8K_VA_OFFREG_D : integer := 0;
constant P8K_VA_OFFSEG_U : integer := 31-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_VA_OFFSEG_D : integer := 0;
constant P8K_VA_OFFPAG_U : integer := 31-P8K_VA_I_SZ;
constant P8K_VA_OFFPAG_D : integer := 0;
-- 16k pages
-- 6 6 6 14
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 26 25 20 19 14 13 0
constant P16K_VA_I1_SZ : integer := 6;
constant P16K_VA_I2_SZ : integer := 6;
constant P16K_VA_I3_SZ : integer := 6;
constant P16K_VA_I_SZ : integer := P16K_VA_I1_SZ+P16K_VA_I2_SZ+P16K_VA_I3_SZ;
constant P16K_VA_I_MAX : integer := 6;
constant P16K_VA_I1_U : integer := 31;
constant P16K_VA_I1_D : integer := 32-P16K_VA_I1_SZ;
constant P16K_VA_I2_U : integer := 31-P16K_VA_I1_SZ;
constant P16K_VA_I2_D : integer := 32-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_VA_I3_U : integer := 31-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_VA_I3_D : integer := 32-P16K_VA_I_SZ;
constant P16K_VA_I_U : integer := 31;
constant P16K_VA_I_D : integer := 32-P16K_VA_I_SZ;
constant P16K_VA_OFF_U : integer := 31-P16K_VA_I_SZ;
constant P16K_VA_OFF_D : integer := 0;
constant P16K_VA_OFFCTX_U : integer := 31;
constant P16K_VA_OFFCTX_D : integer := 0;
constant P16K_VA_OFFREG_U : integer := 31-P16K_VA_I1_SZ;
constant P16K_VA_OFFREG_D : integer := 0;
constant P16K_VA_OFFSEG_U : integer := 31-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_VA_OFFSEG_D : integer := 0;
constant P16K_VA_OFFPAG_U : integer := 31-P16K_VA_I_SZ;
constant P16K_VA_OFFPAG_D : integer := 0;
-- 32k pages
-- 4 7 6 15
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 28 27 21 20 15 14 0
constant P32K_VA_I1_SZ : integer := 4;
constant P32K_VA_I2_SZ : integer := 7;
constant P32K_VA_I3_SZ : integer := 6;
constant P32K_VA_I_SZ : integer := P32K_VA_I1_SZ+P32K_VA_I2_SZ+P32K_VA_I3_SZ;
constant P32K_VA_I_MAX : integer := 7;
constant P32K_VA_I1_U : integer := 31;
constant P32K_VA_I1_D : integer := 32-P32K_VA_I1_SZ;
constant P32K_VA_I2_U : integer := 31-P32K_VA_I1_SZ;
constant P32K_VA_I2_D : integer := 32-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_VA_I3_U : integer := 31-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_VA_I3_D : integer := 32-P32K_VA_I_SZ;
constant P32K_VA_I_U : integer := 31;
constant P32K_VA_I_D : integer := 32-P32K_VA_I_SZ;
constant P32K_VA_OFF_U : integer := 31-P32K_VA_I_SZ;
constant P32K_VA_OFF_D : integer := 0;
constant P32K_VA_OFFCTX_U : integer := 31;
constant P32K_VA_OFFCTX_D : integer := 0;
constant P32K_VA_OFFREG_U : integer := 31-P32K_VA_I1_SZ;
constant P32K_VA_OFFREG_D : integer := 0;
constant P32K_VA_OFFSEG_U : integer := 31-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_VA_OFFSEG_D : integer := 0;
constant P32K_VA_OFFPAG_U : integer := 31-P32K_VA_I_SZ;
constant P32K_VA_OFFPAG_D : integer := 0;
-- ##############################################################
-- 2.0 PAGE TABE DESCRIPTOR (PTD) [sparc V8: p.247,Appx.H,Figure H-7]
--
-- +-------------------------------------------------+---+---+
-- | Page Table Pointer (PTP) | 0 | 0 |
-- +-------------------------------------------------+---+---+
-- 31 2 1 0
--
-- 2.1 PAGE TABE ENTRY (PTE) [sparc V8: p.247,Appx.H,Figure H-8]
--
-- +-----------------------------+---+---+---+-----------+---+
-- |Physical Page Number (PPN) | C | M | R | ACC | ET¦
-- +-----------------------------+---+---+---+-----------+---+
-- 31 8 7 6 5 4 2 1 0
--
constant PTD_PTP_U : integer := 31; -- PTD: page table pointer
constant PTD_PTP_D : integer := 2;
constant PTD_PTP32_U : integer := 27; -- PTD: page table pointer 32 bit
constant PTD_PTP32_D : integer := 2;
constant PTE_PPN_U : integer := 31; -- PTE: physical page number
constant PTE_PPN_D : integer := 8;
constant PTE_PPN_S : integer := (PTE_PPN_U+1)-PTE_PPN_D; -- PTE: pysical page number size
constant PTE_PPN32_U : integer := 27; -- PTE: physical page number 32 bit addr
constant PTE_PPN32_D : integer := 8;
constant PTE_PPN32_S : integer := (PTE_PPN32_U+1)-PTE_PPN32_D; -- PTE: pysical page number 32 bit size
constant PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant PTE_PPN32REG_D : integer := PTE_PPN32_U+1-VA_I1_SZ;
constant PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-VA_I1_SZ-VA_I2_SZ;
constant PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-VA_I_SZ;
-- 8k pages
constant P8K_PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant P8K_PTE_PPN32REG_D : integer := PTE_PPN32_U+1-P8K_VA_I1_SZ;
constant P8K_PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant P8K_PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant P8K_PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-P8K_VA_I_SZ;
-- 16k pages
constant P16K_PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant P16K_PTE_PPN32REG_D : integer := PTE_PPN32_U+1-P16K_VA_I1_SZ;
constant P16K_PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant P16K_PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant P16K_PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-P16K_VA_I_SZ;
-- 32k pages
constant P32K_PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant P32K_PTE_PPN32REG_D : integer := PTE_PPN32_U+1-P32K_VA_I1_SZ;
constant P32K_PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant P32K_PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant P32K_PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-P32K_VA_I_SZ;
constant PTE_C : integer := 7; -- PTE: Cacheable bit
constant PTE_M : integer := 6; -- PTE: Modified bit
constant PTE_R : integer := 5; -- PTE: Reference Bit - a "1" indicates an PTE
constant PTE_ACC_U : integer := 4; -- PTE: Access field
constant PTE_ACC_D : integer := 2;
constant ACC_W : integer := 2; -- PTE::ACC : write permission
constant ACC_E : integer := 3; -- PTE::ACC : exec permission
constant ACC_SU : integer := 4; -- PTE::ACC : privileged
constant PT_ET_U : integer := 1; -- PTD/PTE: PTE Type
constant PT_ET_D : integer := 0;
constant ET_INV : std_logic_vector(1 downto 0) := "00";
constant ET_PTD : std_logic_vector(1 downto 0) := "01";
constant ET_PTE : std_logic_vector(1 downto 0) := "10";
constant ET_RVD : std_logic_vector(1 downto 0) := "11";
constant PADDR_PTD_U : integer := 31;
constant PADDR_PTD_D : integer := 6;
-- ##############################################################
-- 3.0 TLBCAM TAG hardware representation (TTG)
--
type tlbcam_reg is record
ET : std_logic_vector(1 downto 0); -- et field
ACC : std_logic_vector(2 downto 0); -- on flush/probe this will become FPTY
M : std_logic; -- modified
R : std_logic; -- referenced
SU : std_logic; -- equal ACC >= 6
VALID : std_logic;
LVL : std_logic_vector(1 downto 0); -- level in pth
I1 : std_logic_vector(7 downto 0); -- vaddr
I2 : std_logic_vector(5 downto 0);
I3 : std_logic_vector(5 downto 0);
CTX : std_logic_vector(M_CTX_SZ-1 downto 0); -- ctx number
PPN : std_logic_vector(PTE_PPN_S-1 downto 0); -- physical page number
C : std_logic; -- cachable
end record;
constant tlbcam_reg_none : tlbcam_reg := ("00", "000", '0', '0', '0', '0',
"00", "00000000", "000000", "000000", "00000000", (others => '0'), '0');
-- tlbcam_reg::LVL
constant LVL_PAGE : std_logic_vector(1 downto 0) := "00"; -- equal tlbcam_tfp::TYP FPTY_PAGE
constant LVL_SEGMENT : std_logic_vector(1 downto 0) := "01"; -- equal tlbcam_tfp::TYP FPTY_SEGMENT
constant LVL_REGION : std_logic_vector(1 downto 0) := "10"; -- equal tlbcam_tfp::TYP FPTY_REGION
constant LVL_CTX : std_logic_vector(1 downto 0) := "11"; -- equal tlbcam_tfp::TYP FPTY_CTX
-- ##############################################################
-- 4.0 TLBCAM tag i/o for translation/flush/(probe)
--
type tlbcam_tfp is record
TYP : std_logic_vector(2 downto 0); -- f/(p) type
I1 : std_logic_vector(7 downto 0); -- vaddr
I2 : std_logic_vector(5 downto 0);
I3 : std_logic_vector(5 downto 0);
CTX : std_logic_vector(M_CTX_SZ-1 downto 0); -- ctx number
M : std_logic;
end record;
constant tlbcam_tfp_none : tlbcam_tfp := ("000", "00000000", "000000", "000000", "00000000", '0');
--tlbcam_tfp::TYP
constant FPTY_PAGE : std_logic_vector(2 downto 0) := "000"; -- level 3 PTE match I1+I2+I3
constant FPTY_SEGMENT : std_logic_vector(2 downto 0) := "001"; -- level 2/3 PTE/PTD match I1+I2
constant FPTY_REGION : std_logic_vector(2 downto 0) := "010"; -- level 1/2/3 PTE/PTD match I1
constant FPTY_CTX : std_logic_vector(2 downto 0) := "011"; -- level 0/1/2/3 PTE/PTD ctx
constant FPTY_N : std_logic_vector(2 downto 0) := "100"; -- entire tlb
-- ##############################################################
-- 5.0 MMU Control Register [sparc V8: p.253,Appx.H,Figure H-10]
--
-- +-------+-----+------------------+-----+-------+--+--+
-- | IMPL | VER | SC | PSO | resvd |NF|E |
-- +-------+-----+------------------+-----+-------+--+--+
-- 31 28 27 24 23 8 7 6 2 1 0
--
-- MMU Context Pointer [sparc V8: p.254,Appx.H,Figure H-11]
-- +-------------------------------------------+--------+
-- | Context Table Pointer | resvd |
-- +-------------------------------------------+--------+
-- 31 2 1 0
--
-- MMU Context Number [sparc V8: p.255,Appx.H,Figure H-12]
-- +----------------------------------------------------+
-- | Context Table Pointer |
-- +----------------------------------------------------+
-- 31 0
--
-- fault status/address register [sparc V8: p.256,Appx.H,Table H-13/14]
-- +------------+-----+---+----+----+-----+----+
-- | reserved | EBE | L | AT | FT | FAV | OW |
-- +------------+-----+---+----+----+-----+----+
-- 31 18 17 10 9 8 7 5 4 2 1 0
--
-- +----------------------------------------------------+
-- | fault address register |
-- +----------------------------------------------------+
-- 31 0
constant MMCTRL_CTXP_SZ : integer := 30;
constant MMCTRL_PTP32_U : integer := 25;
constant MMCTRL_PTP32_D : integer := 0;
constant MMCTRL_E : integer := 0;
constant MMCTRL_NF : integer := 1;
constant MMCTRL_PSO : integer := 7;
constant MMCTRL_SC_U : integer := 23;
constant MMCTRL_SC_D : integer := 8;
constant MMCTRL_PGSZ_U : integer := 17;
constant MMCTRL_PGSZ_D : integer := 16;
constant MMCTRL_VER_U : integer := 27;
constant MMCTRL_VER_D : integer := 24;
constant MMCTRL_IMPL_U : integer := 31;
constant MMCTRL_IMPL_D : integer := 28;
constant MMCTRL_TLBDIS : integer := 15;
constant MMCTRL_TLBSEP : integer := 14;
constant MMCTXP_U : integer := 31;
constant MMCTXP_D : integer := 2;
constant MMCTXNR_U : integer := M_CTX_SZ-1;
constant MMCTXNR_D : integer := 0;
constant FS_SZ : integer := 18; -- fault status size
constant FS_EBE_U : integer := 17;
constant FS_EBE_D : integer := 10;
constant FS_L_U : integer := 9;
constant FS_L_D : integer := 8;
constant FS_L_CTX : std_logic_vector(1 downto 0) := "00";
constant FS_L_L1 : std_logic_vector(1 downto 0) := "01";
constant FS_L_L2 : std_logic_vector(1 downto 0) := "10";
constant FS_L_L3 : std_logic_vector(1 downto 0) := "11";
constant FS_AT_U : integer := 7;
constant FS_AT_D : integer := 5;
constant FS_AT_LS : natural := 7; --L=0 S=1
constant FS_AT_ID : natural := 6; --D=0 I=1
constant FS_AT_SU : natural := 5; --U=0 SU=1
constant FS_AT_LUDS : std_logic_vector(2 downto 0) := "000";
constant FS_AT_LSDS : std_logic_vector(2 downto 0) := "001";
constant FS_AT_LUIS : std_logic_vector(2 downto 0) := "010";
constant FS_AT_LSIS : std_logic_vector(2 downto 0) := "011";
constant FS_AT_SUDS : std_logic_vector(2 downto 0) := "100";
constant FS_AT_SSDS : std_logic_vector(2 downto 0) := "101";
constant FS_AT_SUIS : std_logic_vector(2 downto 0) := "110";
constant FS_AT_SSIS : std_logic_vector(2 downto 0) := "111";
constant FS_FT_U : integer := 4;
constant FS_FT_D : integer := 2;
constant FS_FT_NONE : std_logic_vector(2 downto 0) := "000";
constant FS_FT_INV : std_logic_vector(2 downto 0) := "001";
constant FS_FT_PRO : std_logic_vector(2 downto 0) := "010";
constant FS_FT_PRI : std_logic_vector(2 downto 0) := "011";
constant FS_FT_TRANS : std_logic_vector(2 downto 0):= "110";
constant FS_FT_BUS : std_logic_vector(2 downto 0) := "101";
constant FS_FT_INT : std_logic_vector(2 downto 0) := "110";
constant FS_FT_RVD : std_logic_vector(2 downto 0) := "111";
constant FS_FAV : natural := 1;
constant FS_OW : natural := 0;
--# mmu ctrl reg
type mmctrl_type1 is record
e : std_logic; -- enable
nf : std_logic; -- no fault
pso : std_logic; -- partial store order
-- pre : std_logic; -- pretranslation source
-- pri : std_logic; -- i/d priority
pagesize : std_logic_vector(1 downto 0);-- page size
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);-- context nr
ctxp : std_logic_vector(MMCTRL_CTXP_SZ-1 downto 0); -- context table pointer
tlbdis : std_logic; -- tlb disabled
bar : std_logic_vector(1 downto 0); -- preplace barrier
end record;
constant mmctrl_type1_none : mmctrl_type1 := ('0', '0', '0', (others => '0'), (others => '0'), (others => '0'), '0', (others => '0'));
--# fault status reg
type mmctrl_fs_type is record
ow : std_logic;
fav : std_logic;
ft : std_logic_vector(2 downto 0); -- fault type
at_ls : std_logic; -- access type, load/store
at_id : std_logic; -- access type, i/dcache
at_su : std_logic; -- access type, su/user
l : std_logic_vector(1 downto 0); -- level
ebe : std_logic_vector(7 downto 0);
end record;
constant mmctrl_fs_zero : mmctrl_fs_type :=
('0', '0', "000", '0', '0', '0', "00", "00000000");
type mmctrl_type2 is record
fs : mmctrl_fs_type;
valid : std_logic;
fa : std_logic_vector(VA_I_SZ-1 downto 0); -- fault address register
end record;
constant mmctrl2_zero : mmctrl_type2 :=
(mmctrl_fs_zero, '0', zero32(VA_I_SZ-1 downto 0));
-- ##############################################################
-- 6. Virtual Flush/Probe address [sparc V8: p.249,Appx.H,Figure H-9]
-- +---------------------------------------+--------+-------+
-- | VIRTUAL FLUSH&Probe Address (VFPA) | type | rvd |
-- +---------------------------------------+--------+-------+
-- 31 12 11 8 7 0
--
--
subtype FPA is natural range 31 downto 12;
constant FPA_I1_U : integer := 31;
constant FPA_I1_D : integer := 24;
constant FPA_I2_U : integer := 23;
constant FPA_I2_D : integer := 18;
constant FPA_I3_U : integer := 17;
constant FPA_I3_D : integer := 12;
constant FPTY_U : integer := 10; -- only 3 bits
constant FPTY_D : integer := 8;
-- ##############################################################
-- 7. control register virtual address [sparc V8: p.253,Appx.H,Table H-5]
-- +---------------------------------+-----+--------+
-- | | CNR | rsvd |
-- +---------------------------------+-----+--------+
-- 31 10 8 7 0
constant CNR_U : integer := 10;
constant CNR_D : integer := 8;
constant CNR_CTRL : std_logic_vector(2 downto 0) := "000";
constant CNR_CTXP : std_logic_vector(2 downto 0) := "001";
constant CNR_CTX : std_logic_vector(2 downto 0) := "010";
constant CNR_F : std_logic_vector(2 downto 0) := "011";
constant CNR_FADDR : std_logic_vector(2 downto 0) := "100";
-- ##############################################################
-- 8. Precise flush (ASI 0x10-14) [sparc V8: p.266,Appx.I]
-- supported: ASI_FLUSH_PAGE
-- ASI_FLUSH_CTX
constant PFLUSH_PAGE : std_logic := '0';
constant PFLUSH_CTX : std_logic := '1';
-- ##############################################################
-- 9. Diagnostic access
--
constant DIAGF_LVL_U : integer := 1;
constant DIAGF_LVL_D : integer := 0;
constant DIAGF_WR : integer := 3;
constant DIAGF_HIT : integer := 4;
constant DIAGF_CTX_U : integer := 12;
constant DIAGF_CTX_D : integer := 5;
constant DIAGF_VALID : integer := 13;
end mmuconfig;
|
-----------------------------------------------------------------------------------
-- Created by Sam Rohrer --
-- Beamforms in the nearfield based on a generic for distance --
-- This is the actual processing that was written for the FPGA --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity nearfield_processing is
generic(
divisor : integer := 50; -- difference between system clock 1 us
speed_sound : integer := 13397; -- in inches/second
speaker_distance : integer := 2 * 10**3; -- in inches
sample_period : integer := 22
);
port(
i_datain_r : in std_logic_vector (7 downto 0); -- 8 bit from memory
i_datain_l : in std_logic_vector (7 downto 0); -- 8 bit from memory
i_clock : in std_logic; --
i_distance : in std_logic_vector (4 downto 0); -- Switches determine distance
i_reset : in std_logic ; -- To reset the entire system
i_sampleclock : in std_logic ; -- Rate at which the music is playing
o_speaker_enable : out std_logic; --LDAC enable
o_dataout : out std_logic_vector (7 downto 0); -- 8 bit to be multiplexed
o_channel : out std_logic_vector (4 downto 0); -- 5 bit to select which DAC to enable
o_us_clock : out std_logic
);
end nearfield_processing;
architecture Behavioral of nearfield_processing is
-- Holding Data
type sr_array is array(natural range <>) of std_logic_vector(7 downto 0);
signal shift_register_l : sr_array(4 downto 0);
signal shift_register_r : sr_array(4 downto 0);
--Sound dataout signals to hold before output
signal data_r_0 : std_logic_vector(7 downto 0);
signal data_r_1 : std_logic_vector(7 downto 0);
signal data_r_2 : std_logic_vector(7 downto 0);
signal data_r_3 : std_logic_vector(7 downto 0);
signal data_r_4 : std_logic_vector(7 downto 0);
signal data_l_0 : std_logic_vector(7 downto 0);
signal data_l_1 : std_logic_vector(7 downto 0);
signal data_l_2 : std_logic_vector(7 downto 0);
signal data_l_3 : std_logic_vector(7 downto 0);
signal data_l_4 : std_logic_vector(7 downto 0);
--Anti-Sound data signals
signal anti_data_r_0 : std_logic_vector(7 downto 0);
signal anti_data_r_1 : std_logic_vector(7 downto 0);
signal anti_data_r_2 : std_logic_vector(7 downto 0);
signal anti_data_r_3 : std_logic_vector(7 downto 0);
signal anti_data_r_4 : std_logic_vector(7 downto 0);
signal anti_data_l_0 : std_logic_vector(7 downto 0);
signal anti_data_l_1 : std_logic_vector(7 downto 0);
signal anti_data_l_2 : std_logic_vector(7 downto 0);
signal anti_data_l_3 : std_logic_vector(7 downto 0);
signal anti_data_l_4 : std_logic_vector(7 downto 0);
--Counts through delays
signal sample_edges : integer range 0 to 7;
signal output_counter_l_0 : integer range 0 to 127 := 0;
signal output_counter_r_0 : integer range 0 to 127 := 0;
signal output_counter_l_1 : integer range 0 to 127 := 0;
signal output_counter_r_1 : integer range 0 to 127 := 0;
signal output_counter_l_2 : integer range 0 to 127 := 0;
signal output_counter_r_2 : integer range 0 to 127 := 0;
signal output_counter_l_3 : integer range 0 to 127 := 0;
signal output_counter_r_3 : integer range 0 to 127 := 0;
signal output_counter_l_4 : integer range 0 to 127 := 0;
signal output_counter_r_4 : integer range 0 to 127 := 0;
-- Counts through 5 different channels
signal mux_counter : integer range 0 to 5;
signal temp_extended_0 : std_logic_vector (8 downto 0);
signal temp_extended_2_0 : std_logic_vector (8 downto 0);
signal temp_extended_1 : std_logic_vector (8 downto 0);
signal temp_extended_2_1 : std_logic_vector (8 downto 0);
signal temp_extended_2 : std_logic_vector (8 downto 0);
signal temp_extended_2_2 : std_logic_vector (8 downto 0);
signal temp_extended_3 : std_logic_vector (8 downto 0);
signal temp_extended_2_3 : std_logic_vector (8 downto 0);
signal temp_extended_4 : std_logic_vector (8 downto 0);
signal temp_extended_2_4 : std_logic_vector (8 downto 0);
signal anti_temp_extended_0 : std_logic_vector (8 downto 0);
signal anti_temp_extended_2_0 : std_logic_vector (8 downto 0);
signal anti_temp_extended_1 : std_logic_vector (8 downto 0);
signal anti_temp_extended_2_1 : std_logic_vector (8 downto 0);
signal anti_temp_extended_2 : std_logic_vector (8 downto 0);
signal anti_temp_extended_2_2 : std_logic_vector (8 downto 0);
signal anti_temp_extended_3 : std_logic_vector (8 downto 0);
signal anti_temp_extended_2_3 : std_logic_vector (8 downto 0);
signal anti_temp_extended_4 : std_logic_vector (8 downto 0);
signal anti_temp_extended_2_4 : std_logic_vector (8 downto 0);
signal result_0 : std_logic_vector (8 downto 0);
signal result_1 : std_logic_vector (8 downto 0);
signal result_2 : std_logic_vector (8 downto 0);
signal result_3 : std_logic_vector (8 downto 0);
signal result_4 : std_logic_vector (8 downto 0);
--Delays & Calculation Signals
signal delay_1 : integer range 0 to 127;
signal delay_2 : integer range 0 to 127;
signal delay_3 : integer range 0 to 127;
signal delay_4 : integer range 0 to 127;
signal us_clock : std_logic;
signal sqrt_est : integer range 0 to 31;
signal dif_dist_sq_1 : integer range 0 to 511;
signal dif_dist_sq_2 : integer range 0 to 511;
signal dif_dist_sq_3 : integer range 0 to 511;
signal dif_dist_sq_4 : integer range 0 to 511;
signal dif_dist_sqrt_1 : integer range 0 to 511 := 25;
signal dif_dist_sqrt_2 : integer range 0 to 511 := 25;
signal dif_dist_sqrt_3 : integer range 0 to 511 := 25;
signal dif_dist_sqrt_4 : integer range 0 to 511 := 25;
signal dif_time_1 : integer range 0 to 127;
signal dif_time_2 : integer range 0 to 127;
signal dif_time_3 : integer range 0 to 127;
signal dif_time_4 : integer range 0 to 127;
-- Distance to Delay Calculation Signals
signal distance : integer range 0 to 127;
--Clock Division
signal clockpulses : integer range 0 to 127;
begin
--************** Tying output signals ******************--
o_us_clock <= us_clock;
--************** From system clock to 1 us *************--
clock_division : process(i_reset, i_clock)
begin
if (i_reset = '1') then
clockpulses <= 0;
us_clock <= '0';
elsif(rising_edge(i_clock)) then
clockpulses <= clockpulses + 1 ;
if(clockpulses = (divisor-1)) then
us_clock <= Not us_clock;
clockpulses <= 0;
end if;
end if;
end process;
--*************** Distance to integer **************--
distance <= conv_integer(i_distance);
--*************** Distance to delay converter*******--
distance_to_delay : process (i_reset, i_clock, clockpulses,distance)
begin
if(i_reset = '1') then
delay_1 <= 0;
delay_2 <= 0;
delay_3 <= 0;
delay_4 <= 0;
sqrt_est <= 25;
dif_time_1 <= 0;
dif_time_2 <= 0;
dif_time_3 <= 0;
dif_time_4 <= 0;
elsif(rising_edge(i_clock)) then
if(clockpulses = 1) then
dif_dist_sq_1 <= (distance*distance + (1 * speaker_distance) * (1 * speaker_distance));
dif_dist_sq_2 <= (distance*distance + (2 * speaker_distance) * (2 * speaker_distance));
dif_dist_sq_3 <= (distance*distance + (3 * speaker_distance) * (3 * speaker_distance));
dif_dist_sq_4 <= (distance*distance + (4 * speaker_distance) * (4 * speaker_distance));
dif_dist_sqrt_1 <= sqrt_est;
dif_dist_sqrt_2 <= sqrt_est;
dif_dist_sqrt_3 <= sqrt_est;
dif_dist_sqrt_4 <= sqrt_est;
elsif(clockpulses = 2) then
dif_dist_sqrt_1 <= ((dif_dist_sqrt_1 + (dif_dist_sq_1 / dif_dist_sqrt_1))/2);
dif_dist_sqrt_2 <= ((dif_dist_sqrt_2 + (dif_dist_sq_2 / dif_dist_sqrt_2))/2);
dif_dist_sqrt_3 <= ((dif_dist_sqrt_3 + (dif_dist_sq_3 / dif_dist_sqrt_3))/2);
dif_dist_sqrt_4 <= ((dif_dist_sqrt_4 + (dif_dist_sq_4 / dif_dist_sqrt_4))/2);
elsif(clockpulses = 3) then
dif_dist_sqrt_1 <= ((dif_dist_sqrt_1 + (dif_dist_sq_1 / dif_dist_sqrt_1))/2);
dif_dist_sqrt_2 <= ((dif_dist_sqrt_2 + (dif_dist_sq_2 / dif_dist_sqrt_2))/2);
dif_dist_sqrt_3 <= ((dif_dist_sqrt_3 + (dif_dist_sq_3 / dif_dist_sqrt_3))/2);
dif_dist_sqrt_4 <= ((dif_dist_sqrt_4 + (dif_dist_sq_4 / dif_dist_sqrt_4))/2);
elsif(clockpulses = 4) then
dif_dist_sqrt_1 <= ((dif_dist_sqrt_1 + (dif_dist_sq_1 / dif_dist_sqrt_1))/2);
dif_dist_sqrt_2 <= ((dif_dist_sqrt_2 + (dif_dist_sq_2 / dif_dist_sqrt_2))/2);
dif_dist_sqrt_3 <= ((dif_dist_sqrt_3 + (dif_dist_sq_3 / dif_dist_sqrt_3))/2);
dif_dist_sqrt_4 <= ((dif_dist_sqrt_4 + (dif_dist_sq_4 / dif_dist_sqrt_4))/2);
elsif(clockpulses = 5) then
dif_dist_sqrt_1 <= ((dif_dist_sqrt_1 + (dif_dist_sq_1 / dif_dist_sqrt_1))/2);
dif_dist_sqrt_2 <= ((dif_dist_sqrt_2 + (dif_dist_sq_2 / dif_dist_sqrt_2))/2);
dif_dist_sqrt_3 <= ((dif_dist_sqrt_3 + (dif_dist_sq_3 / dif_dist_sqrt_3))/2);
dif_dist_sqrt_4 <= ((dif_dist_sqrt_4 + (dif_dist_sq_4 / dif_dist_sqrt_4))/2);
elsif(clockpulses = 6) then
dif_time_1 <= ((dif_dist_sqrt_1 - distance)/ speed_sound);
dif_time_2 <= ((dif_dist_sqrt_2 - distance)/ speed_sound);
dif_time_3 <= ((dif_dist_sqrt_3 - distance)/ speed_sound);
dif_time_4 <= ((dif_dist_sqrt_4 - distance)/ speed_sound);
elsif(clockpulses = 7) then
delay_1 <= (dif_time_4 - dif_time_3) * 10**6;
delay_2 <= (dif_time_4 - dif_time_2) * 10**6;
delay_3 <= (dif_time_4 - dif_time_1) * 10**6;
delay_4 <= (dif_time_4) * 10**6;
end if;
end if;
--********** Manually Set Delays ****************--
-- delay_1 <= (22+2); --42
-- delay_2 <= (44+2); --72
-- delay_3 <= (66+2); --91
-- delay_4 <= (88+2); --97
-- sample_period <= 22;
--********** End Manually Set Delays ************--
end process;
--**************** Filling Shift Registers ************--
fill_regs : process (i_reset, i_sampleclock)
begin
if (i_reset = '1') then
shift_register_l <= (others => X"00");
shift_register_r <= (others => X"00");
-- Conditions to shift in the shift register (every new sample)
elsif( rising_edge (i_sampleclock)) then
if(sample_edges = 0) then
shift_register_r(0) <= i_datain_r;
shift_register_l(0) <= i_datain_l;
elsif(sample_edges = 1) then
shift_register_r(1) <= i_datain_r;
shift_register_l(1) <= i_datain_l;
elsif(sample_edges = 2) then
shift_register_r(2) <= i_datain_r;
shift_register_l(2) <= i_datain_l;
elsif(sample_edges = 3) then
shift_register_r(3) <= i_datain_r;
shift_register_l(3) <= i_datain_l;
elsif(sample_edges = 4) then
shift_register_r(4) <= i_datain_r;
shift_register_l(4) <= i_datain_l;
end if;
end if;
end process;
--******************* Sample Edge Counter ***********************--
sample_edge_counter : process (i_reset, i_sampleclock)
begin
if(i_reset = '1') then
sample_edges <= 0;
elsif (rising_edge(i_sampleclock)) then
sample_edges <= sample_edges +1;
if (sample_edges = 4) then
sample_edges <= 0;
end if;
end if;
end process;
--************* Processes data by inserting delays **************--
speaker_processing_l : process(us_clock)
begin
if(rising_edge(us_clock)) then
if(i_reset = '1') then
output_counter_l_0 <= 0;
output_counter_l_1 <= sample_period;
output_counter_l_2 <= (sample_period*2);
output_counter_l_3 <= (sample_period*3);
output_counter_l_4 <= (sample_period*4);
data_l_0 <= X"00";
data_l_1 <= X"00";
data_l_2 <= X"00";
data_l_3 <= X"00";
data_l_4 <= X"00";
else
--Output Conditions based on delays calculated or inserted
if(output_counter_l_0 = 2) then
data_l_0 <= shift_register_l(0);
elsif(output_counter_l_0 = delay_1) then
data_l_1 <= shift_register_l(0);
elsif(output_counter_l_0 = delay_2) then
data_l_2 <= shift_register_l(0);
elsif(output_counter_l_0 = delay_3) then
data_l_3 <= shift_register_l(0);
elsif(output_counter_l_0 = delay_4) then
data_l_4 <= shift_register_l(0);
end if;
if(output_counter_l_1 = 2) then
data_l_0 <= shift_register_l(1);
elsif(output_counter_l_1 = delay_1) then
data_l_1 <= shift_register_l(1);
elsif(output_counter_l_1 = delay_2) then
data_l_2 <= shift_register_l(1);
elsif(output_counter_l_1 = delay_3) then
data_l_3 <= shift_register_l(1);
elsif(output_counter_l_1 = delay_4) then
data_l_4 <= shift_register_l(1);
end if;
if(output_counter_l_2 = 2) then
data_l_0 <= shift_register_l(2);
elsif(output_counter_l_2 = delay_1) then
data_l_1 <= shift_register_l(2);
elsif(output_counter_l_2 = delay_2) then
data_l_2 <= shift_register_l(2);
elsif(output_counter_l_2 = delay_3) then
data_l_3 <= shift_register_l(2);
elsif(output_counter_l_2 = delay_4) then
data_l_4 <= shift_register_l(2);
end if;
if(output_counter_l_3 = 2) then
data_l_0 <= shift_register_l(3);
elsif(output_counter_l_3 = delay_1) then
data_l_1 <= shift_register_l(3);
elsif(output_counter_l_3 = delay_2) then
data_l_2 <= shift_register_l(3);
elsif(output_counter_l_3 = delay_3) then
data_l_3 <= shift_register_l(3);
elsif(output_counter_l_3 = delay_4) then
data_l_4 <= shift_register_l(3);
end if;
if(output_counter_l_4 = 2) then
data_l_0 <= shift_register_l(4);
elsif(output_counter_l_4 = delay_1) then
data_l_1 <= shift_register_l(4);
elsif(output_counter_l_4 = delay_2) then
data_l_2 <= shift_register_l(4);
elsif(output_counter_l_4 = delay_3) then
data_l_3 <= shift_register_l(4);
elsif(output_counter_l_4 = delay_4) then
data_l_4 <= shift_register_l(4);
end if;
if(output_counter_l_0 = (sample_period*5-1)) then
output_counter_l_0 <= 0;
else
output_counter_l_0 <= output_counter_l_0 +1;
end if;
if(output_counter_l_1 = (sample_period*5-1)) then
output_counter_l_1 <= 0;
else
output_counter_l_1 <= output_counter_l_1 +1;
end if;
if(output_counter_l_2 = (sample_period*5-1)) then
output_counter_l_2 <= 0;
else
output_counter_l_2 <= output_counter_l_2 +1;
end if;
if(output_counter_l_3 = (sample_period*5-1)) then
output_counter_l_3 <= 0;
else
output_counter_l_3 <= output_counter_l_3 +1;
end if;
if(output_counter_l_4 = (sample_period*5-1)) then
output_counter_l_4 <= 0;
else
output_counter_l_4 <= output_counter_l_4 +1;
end if;
end if;
end if;
end process;
--************* Processes data by inserting delays **************--
speaker_processing_r : process(us_clock)
begin
if(rising_edge(us_clock)) then
if(i_reset = '1') then
output_counter_r_0 <= 0;
output_counter_r_1 <= sample_period;
output_counter_r_2 <= (sample_period*2);
output_counter_r_3 <= (sample_period*3);
output_counter_r_4 <= (sample_period*4);
data_r_0 <= X"00";
data_r_1 <= X"00";
data_r_2 <= X"00";
data_r_3 <= X"00";
data_r_4 <= X"00";
else
--Output Conditions based on delays calculated or inserted
if(output_counter_r_0 = 2) then
data_r_0 <= shift_register_r(0);
elsif(output_counter_r_0 = delay_1) then
data_r_1 <= shift_register_r(0);
elsif(output_counter_r_0 = delay_2) then
data_r_2 <= shift_register_r(0);
elsif(output_counter_r_0 = delay_3) then
data_r_3 <= shift_register_r(0);
elsif(output_counter_r_0 = delay_4) then
data_r_4 <= shift_register_r(0);
end if;
if(output_counter_r_1 = 2) then
data_r_0 <= shift_register_r(1);
elsif(output_counter_r_1 = delay_1) then
data_r_1 <= shift_register_r(1);
elsif(output_counter_r_1 = delay_2) then
data_r_2 <= shift_register_r(1);
elsif(output_counter_r_1 = delay_3) then
data_r_3 <= shift_register_r(1);
elsif(output_counter_r_1 = delay_4) then
data_r_4 <= shift_register_r(1);
end if;
if(output_counter_r_2 = 2) then
data_r_0 <= shift_register_r(2);
elsif(output_counter_r_2 = delay_1) then
data_r_1 <= shift_register_r(2);
elsif(output_counter_r_2 = delay_2) then
data_r_2 <= shift_register_r(2);
elsif(output_counter_r_2 = delay_3) then
data_r_3 <= shift_register_r(2);
elsif(output_counter_r_2 = delay_4) then
data_r_4 <= shift_register_r(2);
end if;
if(output_counter_r_3 = 2) then
data_r_0 <= shift_register_r(3);
elsif(output_counter_r_3 = delay_1) then
data_r_1 <= shift_register_r(3);
elsif(output_counter_r_3 = delay_2) then
data_r_2 <= shift_register_r(3);
elsif(output_counter_r_3 = delay_3) then
data_r_3 <= shift_register_r(3);
elsif(output_counter_r_3 = delay_4) then
data_r_4 <= shift_register_r(3);
end if;
if(output_counter_r_4 = 2) then
data_r_0 <= shift_register_r(4);
elsif(output_counter_r_4 = delay_1) then
data_r_1 <= shift_register_r(4);
elsif(output_counter_r_4 = delay_2) then
data_r_2 <= shift_register_r(4);
elsif(output_counter_r_4 = delay_3) then
data_r_3 <= shift_register_r(4);
elsif(output_counter_r_4 = delay_4) then
data_r_4 <= shift_register_r(4);
end if;
if(output_counter_r_0 = (sample_period*5-1)) then
output_counter_r_0 <= 0;
else
output_counter_r_0 <= output_counter_r_0 +1;
end if;
if(output_counter_r_1 = (sample_period*5-1)) then
output_counter_r_1 <= 0;
else
output_counter_r_1 <= output_counter_r_1 +1;
end if;
if(output_counter_r_2 = (sample_period*5-1)) then
output_counter_r_2 <= 0;
else
output_counter_r_2 <= output_counter_r_2 +1;
end if;
if(output_counter_r_3 = (sample_period*5-1)) then
output_counter_r_3 <= 0;
else
output_counter_r_3 <= output_counter_r_3 +1;
end if;
if(output_counter_r_4 = (sample_period*5-1)) then
output_counter_r_4 <= 0;
else
output_counter_r_4 <= output_counter_r_4 +1;
end if;
end if;
end if;
end process;
--*************** Anti-Sound Being Generated *************--
anti_sound: process(i_reset)
begin
if(i_reset = '1') then
anti_data_r_0 <= X"00";
anti_data_r_1 <= X"00";
anti_data_r_2 <= X"00";
anti_data_r_3 <= X"00";
anti_data_r_4 <= X"00";
anti_data_l_0 <= X"00";
anti_data_l_1 <= X"00";
anti_data_l_2 <= X"00";
anti_data_l_3 <= X"00";
anti_data_l_4 <= X"00";
else
anti_data_r_0 <= NOT data_r_0;
anti_data_r_1 <= NOT data_r_1;
anti_data_r_2 <= NOT data_r_2;
anti_data_r_3 <= NOT data_r_3;
anti_data_r_4 <= NOT data_r_4;
anti_data_l_0 <= NOT data_l_0;
anti_data_l_1 <= NOT data_l_1;
anti_data_l_2 <= NOT data_l_2;
anti_data_l_3 <= NOT data_l_3;
anti_data_l_4 <= NOT data_l_4;
end if;
end process;
----************* Output Selector (through MUX) *************--
output_selector : process (i_reset, us_clock, i_clock, clockpulses)
begin
if(rising_edge(i_clock)) then
if (i_reset = '1') then
mux_counter <= 0;
elsif(clockpulses = 40) then
o_channel <= (OTHERS => '1');
o_speaker_enable <= '1';
elsif (rising_edge (us_clock)) then
--Selects which DAC to output to (cycles every 6 us)
-- also selects the data to use on each output
if(mux_counter = 0) then
o_dataout <= result_0 (8 downto 1);
mux_counter <= mux_counter + 1;
o_speaker_enable <= '1';
o_channel <= (0=>'0', OTHERS=>'1');
elsif (mux_counter = 1) then
o_dataout <= result_1 (8 downto 1);
mux_counter <= mux_counter + 1;
o_speaker_enable <= '1';
o_channel <= (1=>'0', OTHERS=>'1');
elsif (mux_counter = 2) then
o_dataout <= result_2 (8 downto 1);
mux_counter <= mux_counter + 1;
o_speaker_enable <= '1';
o_channel <= (2=>'0', OTHERS=>'1');
elsif (mux_counter = 3) then
o_dataout <= result_3 (8 downto 1);
mux_counter <= mux_counter + 1;
o_speaker_enable <= '1';
o_channel <= (3=>'0', OTHERS=>'1');
elsif (mux_counter = 4) then
o_dataout <= result_4 (8 downto 1);
mux_counter <= mux_counter + 1;
o_speaker_enable <= '1';
o_channel <= (4=>'0', OTHERS=>'1');
elsif (mux_counter = 5) then
o_dataout <= X"00";
mux_counter <= 0;
o_speaker_enable <= '0';
o_channel <= (OTHERS=>'1');
end if;
end if;
end if;
end process;
--********************* Combinatorial to add data together **************************--
--Combinatorial Logic to fill the result registers
temp_extended_0 <= '0' & data_r_0;
temp_extended_2_0 <= '0' & data_l_4;
result_0 <= temp_extended_0 + temp_extended_2_0;
temp_extended_1 <= '0' & data_r_1;
temp_extended_2_1 <= '0' & data_l_3;
result_1 <= temp_extended_1 + temp_extended_2_1;
temp_extended_2 <= '0' & data_r_2;
temp_extended_2_2 <= '0' & data_l_2;
result_2 <= temp_extended_2 + temp_extended_2_2;
temp_extended_3 <= '0' & data_r_3;
temp_extended_2_3 <= '0' & data_l_1;
result_3 <= temp_extended_3 + temp_extended_2_3;
temp_extended_4 <= '0' & data_r_4;
temp_extended_2_4 <= '0' & data_l_0;
result_4 <= temp_extended_4 + temp_extended_2_4;
--**************************************************************--
end Behavioral;
|
---------------------------------------------------------------------
---- 7segment.vhdl ----
----
---- Contains definitions for 0-9 and A-f for 7-segment displays
----
---------------------------------------------------------------------
---- This program is free software: you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software ----
---- Foundation, either version 3 of the License, or (at your ----
---- option) any later version. ----
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bcd_seven is
port(bcd: in STD_LOGIC_VECTOR(3 downto 0);
seven: out STD_LOGIC_VECTOR(7 downto 1)); ---MSB is segment a, LSB is g
end entity bcd_seven;
architecture behavioral of bcd_seven is
begin
process (bcd)
begin
case bcd is
when "0000" => --0
seven <= "0000001";
when "0001" => --1
seven <= "1001111";
when "0010" => --2
seven <= "0010010";
when "0011" => --3
seven <= "0000110";
when "0100" => --4
seven <= "1001100";
when "0101" => --5
seven <= "0100100";
when "0110" => --6
seven <= "0100000";
when "0111" => --7
seven <= "0001111";
when "1000" => --8
seven <= "0000000";
when "1001" => --9
seven <= "0000100";
when "1010" => --A
seven <= "0001000";
when "1011" => --b
seven <= "1100000";
when "1100" => --c
seven <= "1110010";
when "1101" => --d
seven <= "1000010";
when "1110" => --E
seven <= "0110000";
when "1111" => --F
seven <= "0111000";
when others => --display nothing
seven <= "1111111";
end case;
end process;
end architecture behavioral;
|
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0 Nano Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, redrocket@gmx.at --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;
entity tb_qam is
end entity tb_qam;
architecture bhv of tb_qam is
constant QAM_1_N : natural := 1;
constant QAM_1_DATA_LEN : natural := 4**QAM_1_N;
constant QAM_1_OUT_LEN : natural := QAM_1_DATA_LEN / 2;
signal qam_1_data : std_ulogic_vector(QAM_1_DATA_LEN - 1 downto 0) := (others => '0');
signal qam_1_in_phase : sfixed(QAM_1_OUT_LEN - 1 downto 0);
signal qam_1_quadrature : sfixed(QAM_1_OUT_LEN - 1 downto 0);
begin
qam_1: entity work.qam_mapper(rtl)
generic map
(
n => QAM_1_N
)
port map
(
data => qam_1_data,
in_phase => qam_1_in_phase,
quadrature => qam_1_quadrature
);
stimu: process
begin
-- TODO: Set input
wait for 2 ns;
-- TODO: Check output
assert false report "Simulation failed" severity error;
assert false report "SIMULATION ENDED SUCCESSFULLY" severity note;
wait;
end process;
end architecture bhv;
|
entity tb_assert5 is
generic (with_err : boolean := False);
end tb_assert5;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_assert5 is
signal v : std_logic_Vector (7 downto 0);
signal en : std_logic := '0';
signal rst : std_logic;
signal clk : std_logic;
signal res : std_logic;
begin
dut: entity work.assert5
port map (v, en, clk, rst, res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
pulse;
rst <= '0';
en <= '1';
v <= b"0010_0000";
pulse;
assert res = '0' severity failure;
v <= b"0010_0001";
pulse;
assert res = '1' severity failure;
v <= b"0010_0011";
pulse;
assert res = '0' severity failure;
v <= b"0010_0010";
pulse;
assert res = '1' severity failure;
en <= '0';
v <= x"05";
pulse;
assert res = '1' severity failure;
rst <= '1';
wait for 1 ns;
assert res = '0' severity failure;
-- Trigger an error.
if with_err then
en <= '1';
rst <= '0';
pulse;
end if;
wait;
end process;
end behav;
|
-- VHDL de um Registrador de Deslocamento para a direita
library ieee;
use ieee.std_logic_1164.all;
entity registrador_deslocamento is
port(clock : in std_logic;
load : in std_logic;
shift : in std_logic;
RIN : in std_logic;
entrada : in std_logic_vector(6 downto 0);
bit_out : out std_logic := '1';
saida : out std_logic_vector(11 downto 0));
end registrador_deslocamento;
architecture exemplo of registrador_deslocamento is
signal IQ : std_logic_vector(11 downto 0);
signal paridade : std_logic;
begin
process (clock, load, shift, IQ)
begin
-- usaremos paridade PAR
paridade <= entrada(0) xor entrada(1) xor entrada(2)
xor entrada(3) xor entrada(4) xor entrada(5)
xor entrada (6);
if (clock'event and clock = '1') then
if (load = '1') then
IQ(0) <= '1'; -- bit de repouso
IQ(1) <= '0'; -- start bit
IQ(8 downto 2) <= entrada; -- bits do caractere ASCII
IQ(9) <= paridade; -- paridade
IQ(11 downto 10) <= "11"; -- stop bits
end if;
if (shift = '1') then
bit_out <= IQ(0);
IQ <= RIN & IQ(11 downto 1);
end if;
end if;
saida <= IQ;
end process;
end exemplo;
|
--
-- Copyright (c) 2008-2015 Sytse van Slooten
--
-- Permission is hereby granted to any person obtaining a copy of these VHDL source files and
-- other language source files and associated documentation files ("the materials") to use
-- these materials solely for personal, non-commercial purposes.
-- You are also granted permission to make changes to the materials, on the condition that this
-- copyright notice is retained unchanged.
--
-- The materials are distributed in the hope that they will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--
-- $Revision: 1.424 $
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pdp2011_cpu is
port(
addr_v : out std_logic_vector(15 downto 0); -- the virtual address that the cpu drives out to the bus for the current read or write
datain : in std_logic_vector(15 downto 0); -- when doing a read, the data input to the cpu
dataout : out std_logic_vector(15 downto 0); -- when doing a write, the data output from the cpu
wr : out std_logic; -- if '1', the cpu is doing a write to the bus and drives addr_v and dataout
rd : out std_logic; -- if '1', the cpu is doing a read from the bus, drives addr_v and reads datain
dw8 : out std_logic; -- if '1', the read or write initiated by the cpu is 8 bits wide
cp : out std_logic; -- if '1', the read or write should use the previous cpu mode
ifetch : out std_logic; -- if '1', this read is for an instruction fetch
id : out std_logic; -- if '1', the read or write should use data space
init : out std_logic; -- if '1', the devices on the bus should reset
iwait : out std_logic; -- if '1', the cpu is waiting for an interrupt
br7 : in std_logic; -- interrupt request, 7
bg7 : out std_logic; -- interrupt grant, 7
int_vector7 : in std_logic_vector(8 downto 0); -- interrupt vector, 7
br6 : in std_logic;
bg6 : out std_logic;
int_vector6 : in std_logic_vector(8 downto 0);
br5 : in std_logic;
bg5 : out std_logic;
int_vector5 : in std_logic_vector(8 downto 0);
bg4 : out std_logic; -- interrupt request, 4
br4 : in std_logic; -- interrupt grant, 4
int_vector4 : in std_logic_vector(8 downto 0); -- interrupt vector, 4
mmutrap : in std_logic; -- if '1', the mmu requests a trap to be serviced after the current instruction completes
ack_mmutrap : out std_logic; -- if '1', the mmu trap request is being acknowledged
mmuabort : in std_logic; -- if '1', the mmu requests that the current instruction is aborted because of a mmu fault
ack_mmuabort : out std_logic; -- if '1', the mmu abort request is being acknowledged
npr : in std_logic; -- non-processor request
npg : out std_logic; -- non-processor grant
nxmabort : in std_logic; -- nxm abort - a memory access cycle by the cpu refers to an address that does not exist
oddabort : in std_logic; -- odd abort - a memory access cycle by the cpu is for a full word, but uses an odd address
illhalt : out std_logic; -- a halt instruction was not executed because it was illegal in the current mode; for use in the cer cpu error register
ysv : out std_logic; -- a yellow stack trap is in progress - for use in the cer cpu error register
rsv : out std_logic; -- a red stack trap is in progress - for use in the cer cpu error register
cpu_stack_limit : in std_logic_vector(15 downto 0); -- the cpu stack limit control register value
cpu_kmillhalt : in std_logic; -- the control register setting for kernel mode illegal halt
sr0_ic : out std_logic; -- sr0/mmr0 instruction complete flag
sr1 : out std_logic_vector(15 downto 0); -- sr1/mmr1, address of the current instruction
sr2 : out std_logic_vector(15 downto 0); -- sr2, register autoincrement/autodecrement information for instruction restart
dstfreference : out std_logic; -- if '1', the destination reference is the final reference for this addressing mode
sr3csmenable : in std_logic; -- if '1', the enable csm instruction flag in sr3/mmr3 is set
psw_in : in std_logic_vector(15 downto 0); -- psw input from the control register address @ 177776
psw_in_we_even : in std_logic; -- psw input from the control register address @ 177776, write enable for the even address part
psw_in_we_odd : in std_logic; -- psw input from the control register address @ 177776, write enable for the odd address part
psw_out : out std_logic_vector(15 downto 0); -- psw output, current psw that the cpu uses
pir_in : in std_logic_vector(15 downto 0); -- pirq value input from the control register
modelcode : in integer range 0 to 255; -- cpu model code
have_fp : in integer range 0 to 2 := 2; -- floating point; 0=force disable; 1=force enable; 2=follow default for cpu model
have_fpa : in integer range 0 to 1 := 0; -- floating point accelerator present with J11 cpu
init_r7 : in std_logic_vector(15 downto 0) := x"f600"; -- start address after reset = o'173000' = m9312 hi rom
init_psw : in std_logic_vector(15 downto 0) := x"00e0"; -- initial psw for kernel mode, primary register set, priority 7
run : in std_logic := '0'; -- if '1', continue when the cpu is in halt state
clk : in std_logic; -- input clock
reset : in std_logic -- reset cpu, also causes init signal to devices on the bus to be asserted
);
end pdp2011_cpu;
architecture implementation of pdp2011_cpu is
component cpuregs is
port(
raddr : in std_logic_vector(5 downto 0);
waddr : in std_logic_vector(5 downto 0);
d : in std_logic_vector(15 downto 0);
o : out std_logic_vector(15 downto 0);
we : in std_logic;
clk : in std_logic
);
end component;
component fpuregs is
port(
raddr : in std_logic_vector(2 downto 0);
waddr : in std_logic_vector(2 downto 0);
d : in std_logic_vector(63 downto 0);
o : out std_logic_vector(63 downto 0);
fpmode : in std_logic;
we : in std_logic;
clk : in std_logic
);
end component;
type state_type is (
state_init, state_ifetch, state_idecode,
state_src0,
state_src1,
state_src2, state_src2w,
state_src3, state_src3a,
state_src4, state_src4w,
state_src5, state_src5a,
state_src6, state_src6a,
state_src7, state_src7a, state_src7b,
state_dst0,
state_dst1,
state_dst2,
state_dst3, state_dst3a,
state_dst4,
state_dst5, state_dst5a,
state_dst6, state_dst6a,
state_dst7, state_dst7a, state_dst7b,
state_sob,
state_jmp,
state_jsr, state_jsra, state_jsrb, state_jsrc,
state_rts, state_rtsa,
state_mark, state_marka, state_markb,
state_csm, state_csma, state_csmb, state_csmc, state_csmd, state_csme, state_csmf, state_csmg, state_csmh, state_csmi,
state_mfp, state_mfpa,
state_mtp, state_mtpa,
state_mtps,
state_dopr, state_dopra, state_doprb,
state_mul, state_mula, state_mulb,
state_div, state_diva, state_divb,
state_ash, state_ashb,
state_ashc, state_ashd, state_ashe,
state_xor,
state_ldfps,
state_stststore,
state_fptrap,
state_fpao,
state_fpso2,
state_fpwr, state_fpwr1, state_fpwr2,
state_fpd0,
state_fpir1, state_fpir2,
state_fpiwr, state_fpiww, state_fpiw1, state_fpiw2,
state_fpr1, state_fpr2, state_fpr3, state_fpr4,
state_fpww, state_fpw1, state_fpw2, state_fpw3, state_fpw4,
state_fprun,
state_fprunao,
state_tstset, state_wrtlck, state_wrtlcka,
state_rsv,
state_trap, state_trapa, state_trapb, state_trapc, state_trapw, state_trapd, state_trape, state_trapf,
state_rti, state_rtia, state_rtib,
state_illegalop,
state_mmuabort, state_mmutrap,
state_br7, state_br6, state_br5, state_br4,
state_store_alu_p, state_store_alu_w, state_store_alu_r,
state_npg
);
signal state : state_type := state_init;
signal pdststate : state_type := state_store_alu_r; -- initialize to a valid value, to enable optimizing
signal psrcstate : state_type := state_store_alu_r; -- initialize to a valid value, to enable optimizing
signal ir : std_logic_vector(15 downto 0);
signal ir_addr : std_logic_vector(15 downto 0);
signal ir_dop : std_logic;
signal ir_sop : std_logic;
signal ir_jmp : std_logic;
signal ir_jsr : std_logic;
signal ir_csm : std_logic;
signal ir_mfpi : std_logic;
signal ir_mfpd : std_logic;
signal ir_mf : std_logic;
signal ir_mtpi : std_logic;
signal ir_mtpd : std_logic;
signal ir_mt : std_logic;
signal ir_mtps : std_logic;
signal ir_mfps : std_logic;
signal ir_dopr : std_logic;
signal ir_fpsop1 : std_logic;
signal ir_fpsop2 : std_logic;
signal ir_fpao : std_logic;
signal ir_facdst : std_logic;
signal ir_facsrc : std_logic;
signal ir_facfdst : std_logic;
signal ir_facfsrc : std_logic;
signal ir_fpma48 : std_logic;
signal ir_fpmai : std_logic;
signal ir_fpmaf : std_logic;
signal ir_mpr : std_logic;
signal ir_rtt : std_logic;
signal ir_wait : std_logic;
signal ir_halt : std_logic;
signal ir_byte : std_logic;
signal ir_store : std_logic;
signal ir_srcr7 : std_logic;
signal ir_dstr7 : std_logic;
signal ir_dstm2r7 : std_logic;
signal temp_psw : std_logic_vector(15 downto 0);
signal trap_vector : std_logic_vector(8 downto 0);
signal trap_vectorp2 : std_logic_vector(8 downto 0);
-- addr
signal addr : std_logic_vector(15 downto 0);
-- psw
signal psw : std_logic_vector(15 downto 0) := init_psw;
signal pswmf : std_logic_vector(15 downto 8);
signal psw_delayedupdate : std_logic_vector(15 downto 0);
signal psw_delayedupdate_even : std_logic;
signal psw_delayedupdate_odd : std_logic;
-- pc
signal r7 : std_logic_vector(15 downto 0) := init_r7;
signal r7p2 : std_logic_vector(15 downto 0);
-- alu signals
signal alu_input : std_logic_vector(15 downto 0);
signal alus_input : std_logic_vector(15 downto 0);
signal alut_input : std_logic_vector(15 downto 0);
signal alu_output : std_logic_vector(15 downto 0);
signal alu_output_signext : std_logic_vector(15 downto 0);
signal alu_psw : std_logic_vector(3 downto 0);
-- register bus
signal rbus_raddr : std_logic_vector(5 downto 0);
signal rbus_waddr : std_logic_vector(5 downto 0);
signal rbus_d : std_logic_vector(15 downto 0);
signal rbus_o : std_logic_vector(15 downto 0);
signal rbus_we : std_logic;
signal rbus_ix : std_logic_vector(2 downto 0);
signal rbus_cpu_mode : std_logic_vector(1 downto 0);
signal rbus_data : std_logic_vector(15 downto 0);
signal rbus_data_m8 : std_logic_vector(15 downto 0);
signal rbus_data_m4 : std_logic_vector(15 downto 0);
signal rbus_data_m2 : std_logic_vector(15 downto 0);
signal rbus_data_m1 : std_logic_vector(15 downto 0);
signal rbus_data_p8 : std_logic_vector(15 downto 0);
signal rbus_data_p4 : std_logic_vector(15 downto 0);
signal rbus_data_p2 : std_logic_vector(15 downto 0);
signal rbus_data_p1 : std_logic_vector(15 downto 0);
signal rbus_data_mv : std_logic_vector(15 downto 0);
signal rbus_data_pv : std_logic_vector(15 downto 0);
-- sr1/mmr1
signal sr1_dst : std_logic_vector(7 downto 0);
signal sr1_src : std_logic_vector(7 downto 0);
signal sr1_dstd : std_logic_vector(4 downto 0);
signal sr1_srcd : std_logic_vector(4 downto 0);
signal sr1_p2 : std_logic_vector(4 downto 0);
signal sr1_pv : std_logic_vector(4 downto 0);
signal sr1_m2 : std_logic_vector(4 downto 0);
signal sr1_mv : std_logic_vector(4 downto 0);
-- current/previous mode flags
signal cp_req : std_logic;
signal cp_mf : std_logic;
signal cp_mt : std_logic;
-- id selector output based on state
signal id_select : std_logic;
-- rd output based on state
signal rd_select : std_logic;
signal rs_mt : std_logic;
signal rs_jj : std_logic;
-- address buffers
signal dest_addr : std_logic_vector(15 downto 0);
signal addr_indirect : std_logic_vector(15 downto 0);
signal finalreference : std_logic;
-- signals for eis operations (div, mul, ash, ashc)
signal eis_output : std_logic_vector(15 downto 0);
signal eis_output32 : std_logic_vector(15 downto 0);
signal eis_temp : std_logic_vector(15 downto 0);
signal eis_temp1 : std_logic_vector(31 downto 0);
signal eis_temp2 : std_logic_vector(31 downto 0);
signal eis_sequencer : std_logic_vector(4 downto 0);
signal eis_psw : std_logic_vector(3 downto 0);
signal eis_flag1 : std_logic;
signal eis_flag2 : std_logic;
-- counter for number of cycles to remain in init state
signal initcycles : integer range 0 to 7;
-- signals for yellow stack trap recognition
signal yellow_stack_trap : std_logic;
signal yellow_stack_trap_trigger : std_logic;
signal yellow_stack_trap_relevant_state : std_logic;
signal yellow_stack_trap_inhibit : std_logic;
-- signals for red stack trap recognition
signal red_stack_trap : std_logic;
signal red_stack_trap_trigger : std_logic;
signal red_stack_trap_relevant_state : std_logic;
-- floating point stuff
signal fps : std_logic_vector(15 downto 0);
signal fec : std_logic_vector(3 downto 0);
signal fea : std_logic_vector(15 downto 0);
-- floating point alu
signal falu_input : std_logic_vector(63 downto 0);
signal falus_input : std_logic_vector(63 downto 0);
signal falu_output : std_logic_vector(63 downto 0);
signal falu_output2 : std_logic_vector(63 downto 0);
signal falu_fps : std_logic_vector(3 downto 0);
signal falu_load : std_logic;
signal falu_done : std_logic;
signal falu_flag1 : std_logic;
type falu_fsm_type is (
falu_idle,
falu_align,
falu_mult,
falu_div,
falu_addsub,
falu_shift, falu_shift2, falu_shifte,
falu_norm,
falu_rt, falu_rtc,
falu_sep, falu_sep2, falu_sep3,
falu_zres,
falu_res
);
signal falu_fsm : falu_fsm_type := falu_idle;
signal falu_ccw : std_logic_vector(9 downto 0);
signal falu_state : integer range 0 to 163;
signal falu_work1 : std_logic_vector(58 downto 0);
signal falu_work2 : std_logic_vector(58 downto 0);
signal falu_pending_clear : std_logic;
signal falu_pending_fic : std_logic;
signal falu_pending_fiu : std_logic;
signal falu_pending_fiv : std_logic;
signal falu_pending_divz : std_logic;
-- floating point registers
signal fbus_raddr : std_logic_vector(2 downto 0);
signal fbus_waddr : std_logic_vector(2 downto 0);
signal fbus_d : std_logic_vector(63 downto 0);
signal fbus_o : std_logic_vector(63 downto 0);
signal fbus_we : std_logic;
signal fbus_fd : std_logic;
-- sob slowdown
signal sob_slowdown: integer range 0 to 255;
-- configuration stuff
signal have_sob_zkdjbug : integer range 0 to 1;
signal have_sob : integer range 0 to 1;
signal have_sxt : integer range 0 to 1;
signal have_rtt : integer range 0 to 1;
signal have_mark : integer range 0 to 1;
signal have_xor : integer range 0 to 1;
signal have_eis : integer range 0 to 1;
signal have_fpu_default : integer range 0 to 1;
signal have_fpu : integer range 0 to 1;
signal have_mtps : integer range 0 to 1;
signal have_mfp : integer range 0 to 1;
signal have_mpr : integer range 0 to 1;
signal have_spl : integer range 0 to 1;
signal have_csm : integer range 0 to 1;
signal have_red : integer range 0 to 1;
signal have_pswimmediateupdate : integer range 0 to 1;
signal have_mmuimmediateabort : integer range 0 to 1;
signal have_oddimmediateabort : integer range 0 to 1;
signal have_psw1512 : integer range 0 to 1;
signal have_psw11 : integer range 0 to 1;
signal have_psw8 : integer range 0 to 1;
begin
cpuregs0: cpuregs port map(
raddr => rbus_raddr,
waddr => rbus_waddr,
d => rbus_d,
o => rbus_o,
we => rbus_we,
clk => clk
);
fpuregs0: fpuregs port map(
raddr => fbus_raddr,
waddr => fbus_waddr,
d => fbus_d,
o => fbus_o,
fpmode => fbus_fd,
we => fbus_we,
clk => clk
);
r7p2 <= r7 + 2;
trap_vectorp2 <= trap_vector + 2;
alu_output_signext <= alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7 downto 0);
-- generate bus stuff
iwait <= ir_wait;
-- finalreference : this bit signals states that access the final operand
-- this is needed for a) byte accesses; b) m[f|t]p[i|d]; so several other access types can be omitted here
with state select finalreference <=
'1' when state_dst1,
'1' when state_dst2,
'1' when state_dst3a,
'1' when state_dst4,
'1' when state_dst5a,
'1' when state_dst6a,
'1' when state_dst7b,
'1' when state_src1,
'1' when state_src2,
'1' when state_src3a,
'1' when state_src4,
'1' when state_src5a,
'1' when state_src6a,
'1' when state_src7b,
'1' when state_store_alu_w,
'0' when others;
-- dstfreference : this bit signals states that access the final operand in dest mode only
-- this is needed for maintenance mode in the mmu, and then most likely only to be able
-- to pass diagnostics without error messages
with state select dstfreference <=
'1' when state_dst1,
'1' when state_dst2,
'1' when state_dst3a,
'1' when state_dst4,
'1' when state_dst5a,
'1' when state_dst6a,
'1' when state_dst7b,
'1' when state_store_alu_w,
'0' when others;
-- generate signals for yellow stack trap
with state select yellow_stack_trap_relevant_state <=
'1' when state_dst4,
'1' when state_dst5a,
'1' when state_src4,
'1' when state_src5a,
'1' when state_trapc,
'1' when state_trapd,
'1' when state_csmc,
'1' when state_csme,
'1' when state_csmg,
'0' when others;
yellow_stack_trap_trigger <= '1'
when yellow_stack_trap_relevant_state = '1'
and rbus_ix = "110"
and psw(15 downto 14) = "00"
and yellow_stack_trap_inhibit = '0'
and red_stack_trap = '0'
and unsigned(cpu_stack_limit) > unsigned(rbus_data_m2)
else '0';
ysv <= yellow_stack_trap_trigger;
-- generate signals for red stack trap
with state select red_stack_trap_relevant_state <=
'1' when state_trapc,
'1' when state_trapd,
'0' when others;
red_stack_trap_trigger <= '1'
when red_stack_trap_relevant_state = '1'
-- and (mmuabort = '1' or oddabort = '1' or nxmabort = '1')
and (oddabort = '1' or nxmabort = '1')
else '0';
rsv <= red_stack_trap_trigger;
-- dw8 : data width 8, signals that a byte is accessed
dw8 <= '1' when (finalreference = '1' and ir_byte = '1') else '0';
-- cp : this address refers to current or previous mode
cp_mf <= '1' when finalreference = '1' and state /= state_store_alu_w and (ir_mfpi = '1' or ir_mfpd = '1') else '0';
cp_mt <= '1' when state = state_store_alu_w and (ir_mtpi = '1' or ir_mtpd = '1') else '0';
cp_req <= '1' when cp_mf = '1' or cp_mt = '1' else '0';
cp <= cp_req;
-- rd : cpu needs read transaction
with state select rd_select <=
'1' when state_idecode,
'1' when state_dst1,
'1' when state_dst2,
'1' when state_dst3 | state_dst3a,
'1' when state_dst4,
'1' when state_dst5 | state_dst5a,
'1' when state_dst6 | state_dst6a,
'1' when state_dst7 | state_dst7a | state_dst7b,
'1' when state_src1,
'1' when state_src2,
'1' when state_src3 | state_src3a,
'1' when state_src4,
'1' when state_src5 | state_src5a,
'1' when state_src6 | state_src6a,
'1' when state_src7 | state_src7a | state_src7b,
'1' when state_mfpa,
'1' when state_mtpa,
'1' when state_fpir1 | state_fpir2,
'1' when state_fpr1 | state_fpr2 | state_fpr3 | state_fpr4,
'1' when state_trapa | state_trapf,
'1' when state_csmi,
'1' when state_rtsa,
'1' when state_markb,
'1' when state_rtia | state_rtib,
'0' when others;
-- rs signals - read suppression for specific cases, because raising the read line would cause a wrong memory access - potentially a trap
rs_mt <= '1' when (ir_mtpi = '1' or ir_mtpd = '1') and finalreference = '1' and state /= state_store_alu_w else '0';
rs_jj <= '1' when (ir_jmp = '1' or ir_jsr = '1') and finalreference = '1' else '0';
rd <= '0' when rs_mt = '1' or rs_jj = '1' or ir_wait = '1' else rd_select;
-- wr : cpu needs write transaction
with state select wr <=
ir_store when state_store_alu_w,
'1' when state_stststore,
'1' when state_fpiw1 | state_fpiw2,
'1' when state_fpw1 | state_fpw2 | state_fpw3 | state_fpw4,
'1' when state_jsrb,
'1' when state_trapc | state_trapd,
'1' when state_csmc | state_csme | state_csmg,
'0' when others;
-- select data to write
with state select dataout <=
alu_output when state_store_alu_w,
fea when state_stststore,
falu_output(63 downto 48) when state_fpw1,
falu_output(47 downto 32) when state_fpw2,
falu_output(31 downto 16) when state_fpw3,
falu_output(15 downto 0) when state_fpw4,
falu_output(63 downto 48) when state_fpiw1,
falu_output(47 downto 32) when state_fpiw2,
rbus_data when state_jsrb,
temp_psw when state_trapc,
r7 when state_trapd,
temp_psw when state_csmc,
r7 when state_csme,
alu_output when state_csmg,
"0000000000000000" when others;
-- addr : select address to drive
with state select addr <=
r7 when state_ifetch, -- r7 is driven out during wait or halt states - only used for debugging, not to drive actual logic
r7 when state_idecode,
rbus_data when state_dst1,
rbus_data when state_dst2,
rbus_data when state_dst3,
addr_indirect when state_dst3a,
rbus_data_mv when state_dst4,
rbus_data_m2 when state_dst5,
addr_indirect when state_dst5a,
r7 when state_dst6,
addr_indirect when state_dst6a,
r7 when state_dst7,
addr_indirect when state_dst7a,
addr_indirect when state_dst7b,
rbus_data when state_src1,
rbus_data when state_src2,
rbus_data when state_src3,
addr_indirect when state_src3a,
rbus_data_mv when state_src4,
rbus_data_m2 when state_src5,
addr_indirect when state_src5a,
r7 when state_src6,
addr_indirect when state_src6a,
r7 when state_src7,
addr_indirect when state_src7a,
addr_indirect when state_src7b,
rbus_data_m2 when state_mfpa,
rbus_data when state_mtpa,
addr_indirect when state_fpir1,
addr_indirect when state_fpir2,
addr_indirect when state_fpr1,
addr_indirect when state_fpr2,
addr_indirect when state_fpr3,
addr_indirect when state_fpr4,
addr_indirect when state_fpiw1,
addr_indirect when state_fpiw2,
addr_indirect when state_fpw1,
addr_indirect when state_fpw2,
addr_indirect when state_fpw3,
addr_indirect when state_fpw4,
"0000000" & trap_vectorp2 when state_trapa,
"0000000" & trap_vector when state_trapb,
rbus_data_m2 when state_trapc,
rbus_data_m2 when state_trapd,
"0000000" & trap_vector when state_trapf,
addr_indirect when state_jsrb,
addr_indirect when state_rtsa,
rbus_data when state_markb,
rbus_data when state_rtia,
rbus_data when state_rtib,
rbus_data_m2 when state_csmc,
rbus_data_m2 when state_csme,
rbus_data_m2 when state_csmg,
"0000000" & trap_vector when state_csmi,
dest_addr when state_store_alu_w,
dest_addr when state_stststore,
"0000000000000000" when others;
addr_v <= addr;
-- id : map states onto instruction or data access
ir_dstm2r7 <= '0' when ir(5 downto 0) = "010111" else '1';
ir_srcr7 <= '0' when ir(8 downto 6) = "111" else '1';
ir_dstr7 <= '0' when ir(2 downto 0) = "111" else '1';
with state select id_select <=
'0' when state_idecode,
ir_dstr7 when state_dst1,
ir_dstr7 when state_dst2,
ir_dstr7 when state_dst3,
'1' when state_dst3a,
ir_dstr7 when state_dst4,
ir_dstr7 when state_dst5,
'1' when state_dst5a,
'0' when state_dst6,
'1' when state_dst6a,
'0' when state_dst7,
'1' when state_dst7a,
'1' when state_dst7b,
ir_srcr7 when state_src1,
ir_srcr7 when state_src2,
ir_srcr7 when state_src3,
'1' when state_src3a,
ir_srcr7 when state_src4,
ir_srcr7 when state_src5,
'1' when state_src5a,
'0' when state_src6,
'1' when state_src6a,
'0' when state_src7,
'1' when state_src7a,
'1' when state_src7b,
ir_dstm2r7 when state_fpir1,
'1' when state_fpir2,
ir_dstm2r7 when state_fpiw1,
'1' when state_fpiw2,
ir_dstm2r7 when state_fpr1,
'1' when state_fpr2 | state_fpr3 | state_fpr4,
ir_dstm2r7 when state_fpw1,
'1' when state_fpw2 | state_fpw3 | state_fpw4,
'1' when state_stststore, -- always in d-space, this is the second store - first is handled by store_alu_w
'1' when state_mfpa, -- move from previous, stack push is to current d-space
'1' when state_mtpa, -- move to previous, stack pop is from current d-space
'1' when state_trapa, -- d-mapping for loading the trap psw from kernel d-space
'1' when state_trapb, -- to enable debugging output via addr - d-mapping should be 1 to 1, i-mapping likely is not
'1' when state_trapc, -- stack is in d-space
'1' when state_trapd, -- stack is in d-space
'1' when state_trapf, -- d-mapping for loading the trap vector from kernel d-space
'1' when state_jsrb,
'1' when state_rtsa,
'0' when state_mark,
'0' when state_marka,
'1' when state_rtia, -- stack is in d-space
'1' when state_rtib, -- stack is in d-space
'1' when state_csmc | state_csme | state_csmg,
'0' when state_csmi, -- apparently; this at least is suggested by 0174_CKKTBD0_1144mmgmt.pdf
ir_dstm2r7 when state_store_alu_w,
'0' when others;
id <=
'1' when ir_mfpi = '1' and psw(15 downto 12) = "1111" and cp_req = '1'
else '0' when ir_mfpi = '1' and cp_req = '1'
else '1' when ir_mfpd = '1' and cp_req = '1'
else '0' when ir_mtpi = '1' and cp_req = '1'
else '1' when ir_mtpd = '1' and cp_req = '1'
else id_select;
-- psw that is output to the mmu
psw_out <= rbus_cpu_mode & pswmf(13 downto 8) & psw(7 downto 0);
-- psw filtered by cpu modelcode
pswmf(15 downto 12) <= psw(15 downto 12) when have_psw1512 = 1 else "0000";
pswmf(11) <= psw(11) when have_psw11 = 1 else '0';
pswmf(10 downto 9) <= "00";
pswmf(8) <= psw(8) when have_psw8 = 1 else '0';
-- pswmf(7 downto 0) <= psw(7 downto 0);
-- registers
rbus_raddr <= rbus_cpu_mode & pswmf(11) & rbus_ix;
with rbus_ix select rbus_data <=
r7 when "111",
rbus_o when others;
-- calculate amount of autoincrement or autodecrement
ir_fpma48 <= '1' when (fps(7) = '1' and ir(11 downto 8) /= "1111") or (fps(7) = '0' and ir(11 downto 8) = "1111") else '0';
rbus_data_m8 <= rbus_data - 8;
rbus_data_m4 <= rbus_data - 4;
rbus_data_m2 <= rbus_data - 2;
rbus_data_m1 <= rbus_data - 1;
rbus_data_p8 <= rbus_data + 8;
rbus_data_p4 <= rbus_data + 4;
rbus_data_p2 <= rbus_data + 2;
rbus_data_p1 <= rbus_data + 1;
rbus_data_mv <= rbus_data_m8 when (ir_fpmaf = '1' and ir_fpma48 = '1' and rbus_ix /= "111")
else rbus_data_m4 when (ir_fpmaf = '1' and ir_fpma48 = '0' and rbus_ix /= "111")
else rbus_data_m4 when (ir_fpmai = '1' and fps(6) = '1' and rbus_ix /= "111")
else rbus_data_m1 when (ir_byte = '1' and rbus_ix(2 downto 1) /= "11")
else rbus_data_m2;
rbus_data_pv <= rbus_data_p8 when (ir_fpmaf = '1' and ir_fpma48 = '1' and rbus_ix /= "111")
else rbus_data_p4 when (ir_fpmaf = '1' and ir_fpma48 = '0' and rbus_ix /= "111")
else rbus_data_p4 when (ir_fpmai = '1' and fps(6) = '1' and rbus_ix /= "111")
else rbus_data_p1 when (ir_byte = '1' and rbus_ix(2 downto 1) /= "11")
else rbus_data_p2;
-- sr1 cq. mmr1 construction
ir_mf <= '1' when ir_mfpi = '1' or ir_mfpd = '1' else '0';
ir_mt <= '1' when ir_mtpi = '1' or ir_mtpd = '1' else '0';
sr1_dst <= sr1_dstd & ir(2 downto 0) when sr1_dstd /= "00000" and ir(2 downto 0) /= "111"
else "00000000";
sr1_src <= sr1_srcd & "110" when (ir_mt = '1' or ir_mf = '1' or ir_jsr = '1') and sr1_srcd /= "00000"
else sr1_srcd & ir(8 downto 6) when sr1_srcd /= "00000" and ir(8 downto 6) /= "111" and ir_dop = '1'
else "00000000";
sr1 <= sr1_dst & sr1_src when (ir_dop = '1' or ir_jsr = '1') and sr1_srcd /= "00000"
else sr1_dst & sr1_src when sr1_dstd = "00000"
else sr1_src & sr1_dst;
-- sr1 <= sr1_src & sr1_dst when sr1_dstd /= "00000" and sr1_src(2 downto 0) /= sr1_dst(2 downto 0)
-- else "00000000" & (sr1_src(7 downto 3) + sr1_dst(7 downto 3)) & sr1_dst(2 downto 0) when sr1_src(2 downto 0) = sr1_dst(2 downto 0)
-- else "00000000" & sr1_src;
sr1_p2 <= "00010";
sr1_pv <= "01000" when (ir_fpmaf = '1' and ir_fpma48 = '1' and rbus_ix /= "111")
else "00100" when (ir_fpmaf = '1' and ir_fpma48 = '0' and rbus_ix /= "111")
else "00100" when (ir_fpmai = '1' and fps(6) = '1' and rbus_ix /= "111")
else "00001" when (ir_byte = '1' and rbus_ix(2 downto 1) /= "11")
else "00010";
sr1_m2 <= "11110";
sr1_mv <= "11000" when (ir_fpmaf = '1' and ir_fpma48 = '1' and rbus_ix /= "111")
else "11100" when (ir_fpmaf = '1' and ir_fpma48 = '0' and rbus_ix /= "111")
else "11100" when (ir_fpmai = '1' and fps(6) = '1' and rbus_ix /= "111")
else "11111" when (ir_byte = '1' and rbus_ix(2 downto 1) /= "11")
else "11110";
-- cpu model configuration
have_sob_zkdjbug <= 0; -- set flag to enable bugfix for zkdj maindec
with modelcode select have_sob <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_sxt <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_rtt <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_mark <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_xor <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_eis <=
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_fpu_default <=
1 when 23 | 24, -- kdf11
1 when 34,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
have_fpu <= have_fpu_default when have_fp = 2 else have_fp;
with modelcode select have_mtps <=
1 when 3,
1 when 4,
1 when 23 | 24, -- kdf11
1 when 34 | 35 | 40, -- kt11d!
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_mfp <=
1 when 23 | 24, -- kdf11
1 when 34 | 35 | 40, -- kt11d!
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_mpr <=
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_spl <=
1 when 44,
1 when 45 | 50 | 55,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_csm <=
1 when 44,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_red <=
1 when 35 | 40,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_pswimmediateupdate <=
0 when 44, -- observed behaviour, at least from kkab
0 when 4,
-- 0 when 5 | 10, FIXME FIXME FIXME
-- 0 when 15 | 20,
1 when others;
with modelcode select have_mmuimmediateabort <=
-- 1 when 73 | 83 | 84 | 93 | 94, -- kdj11 -- as understood from 2.11BSD, trap.c
0 when others;
with modelcode select have_oddimmediateabort <=
1 when others; -- found no evidence that this is not actually what all pdps do
with modelcode select have_psw1512 <= -- curr/prev mode bits
1 when 23 | 24, -- kdf11
1 when 34 | 35 | 40, -- kt11d!
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_psw11 <= -- general purpose reg set bit
1 when 45 | 50 | 55,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_psw8 <= -- FIXME, what is this? 11/44 handbook has this as CIS insn suspension
1 when 23 | 24, -- kdf11
1 when 44,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
-- state sequencer
process(clk)
variable v_sop : std_logic;
variable v_dop : std_logic;
variable v_jmp : std_logic;
variable v_jsr : std_logic;
variable v_csm : std_logic;
variable v_mfpi : std_logic;
variable v_mfpd : std_logic;
variable v_mtpi : std_logic;
variable v_mtpd : std_logic;
variable v_mtps : std_logic;
variable v_mfps : std_logic;
variable v_dopr : std_logic;
variable v_mpr : std_logic;
variable v_fpsop1 : std_logic;
variable v_fpsop2 : std_logic;
variable v_fpao : std_logic;
begin
if clk='1' and clk'event then
--
-- synchronous reset; setup some signals that must have a known value after a reset signal to the cpu
--
if reset='1' then
r7 <= init_r7; -- start address
psw <= init_psw; -- initial psw
rbus_cpu_mode <= "00"; -- initial rbus access for kernel mode sp
ir_rtt <= '0'; -- no rtt
ir_wait <= '0'; -- not in wait state
ir_halt <= '0'; -- not halted
bg7 <= '0'; -- no bg7 active
bg6 <= '0'; -- no bg6 active
bg5 <= '0'; -- no bg5 active
bg4 <= '0'; -- no bg4 active
npg <= '0'; -- not granting bus
if have_red = 1 then
red_stack_trap <= '0'; -- not doing a red stack trap
end if;
yellow_stack_trap <= '0'; -- not doing a yellow stack trap
fps <= x"0000"; -- initial fp11 status register
fea <= x"0000"; -- initial fp11 error address register
fec <= "0000"; -- initial fp11 error code register
falu_load <= '0'; -- not doing a load of the fp11 fpao alu
psw_delayedupdate_even <= '0'; -- not updating psw after the fact - even address byte part
psw_delayedupdate_odd <= '0'; -- not updating psw after the fact - odd address byte
state <= state_init; -- first state in the major state machine after reset
initcycles <= 7; -- setup to stay this many cycles in state_init
init <= '1'; -- send reset signal to outside
rbus_waddr <= "000000"; -- select r0 in set 0
rbus_d <= conv_std_logic_vector(modelcode, 16); -- set modelcode on rbus
rbus_we <= '1'; -- pulse write
else
--
-- main state machine; setup some default values for signals that are applicable in each state
--
rbus_we <= '0'; -- default is not writing to the register file
fbus_we <= '0'; -- default is not writing to the fp11 register file
ifetch <= '0'; -- default is not an instruction fetch
ack_mmuabort <= '0'; -- default not acknowledging an mmu abort
ack_mmutrap <= '0'; -- default not acknowledging an mmu trap
illhalt <= '0'; -- no illegal halt
falu_pending_clear <= '0'; -- not clearing any pending fp11 interrupt flags
if yellow_stack_trap_trigger = '1' then -- do we have a pending yellow stack trap?
yellow_stack_trap <= '1'; -- signal to deal with it on the next pass through state_ifetch
end if;
--
-- aborts; these conditions abort the execution of instructions, no matter in which state the state machine is
--
-- the ir_csm check in here is really a dirty hack - it's to prevent state_csmi from changing r7 when an abort occurs in
-- the final memory reference. It's needed to pass zkdk - but, probably a more generic case exists for anything that changes
-- r7. The problem lies in what happens if r7 is changed, and subsequently an abort occurs - then r7 will be pushed, but
-- with the changed value, which most likely is incorrect - because the memory access was aborted.
-- It may make more sense to generically enable have_mmuimmediateabort, but, then 2.11BSD will not run - it needs the
-- decrement of a stack push to be reflected in the r6, because otherwise it will not grow a stack. Re. the ls -als problem.
if have_red = 1 and red_stack_trap_trigger = '1' then -- if the conditions for a red stack trap have tripped
red_stack_trap <= '1'; -- set flag
state <= state_rsv; -- start red trap sequence
elsif mmuabort = '1' and (have_mmuimmediateabort = 1 or ir_csm = '1') then -- signal from mmu that an access caused an abort. dealing with the abort here suppresses any actions taken by the state itself, re. code at end of state machine
state <= state_mmuabort; -- precursor state for mmu abort
ack_mmuabort <= '1'; -- set acknowledge flag to mmu core
elsif oddabort = '1' and (have_oddimmediateabort = 1 or ir_csm = '1') then -- odd abort signal, and need to deal with it and suppress the state machine actions?
trap_vector <= o"004"; -- set vector
state <= state_trap; -- do trap
else
--
-- state_init; this is the first state after a reset, both the hardware signal as well as the insn. This state will
-- set the init signal towards the 'bus', and stretch it a bit, to give slower things on the bus a bit of extra time
-- to reset in their turn. Since there are not really 'slower' things on the bus, this may not be necessary, but at
-- some point it did help in debugging.
--
case state is
when state_init =>
if initcycles = 0 then
state <= state_ifetch;
init <= '0';
else
init <= '1';
initcycles <= initcycles - 1;
end if;
--
-- state_ifetch; all things that need to happen before starting to decode a new instruction. Actually, this state
-- just sets up the memory to produce a new instruction; besides however there is a lot of logic that deduces
-- whether other things, such as handling interrupts need to be serviced before a new instruction can start.
--
-- the if-elsif statement is a priority encoder that determines the relative priority of interrupts.
--
when state_ifetch =>
rbus_cpu_mode <= pswmf(15 downto 14); -- set rbus to the current cpu mode
ir_wait <= '0';
if have_red = 1 then
red_stack_trap <= '0';
end if;
yellow_stack_trap_inhibit <= '0';
if ir_halt = '1' then
if run = '1' then -- mostly just to allow passing a halt in a test program
state <= state_ifetch;
ir_halt <= '0';
end if;
elsif npr = '1' then -- bus master request
state <= state_npg;
npg <= '1';
elsif mmutrap = '1' then -- mmu trap vector = 250
state <= state_mmutrap;
ack_mmutrap <= '1';
elsif yellow_stack_trap = '1' then
yellow_stack_trap <= '0';
yellow_stack_trap_inhibit <= '1';
trap_vector <= o"004"; -- yellow stack trap, vector = 004
state <= state_trap;
elsif falu_pending_fic = '1' then -- pending fic trap from fp11
state <= state_fptrap;
elsif falu_pending_fiu = '1' then -- pending fiu trap from fp11
state <= state_fptrap;
elsif falu_pending_fiv = '1' then -- pending fiv trap from fp11
state <= state_fptrap;
elsif falu_pending_divz = '1' then -- pending div by zero trap from fp11
state <= state_fptrap;
elsif pir_in(15) = '1' and unsigned(psw(7 downto 5)) < unsigned'("111") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif br7 = '1' and unsigned(psw(7 downto 5)) < unsigned'("111") then
state <= state_br7; -- external, level 7, vector determined by device
bg7 <= '1';
elsif pir_in(14) = '1' and unsigned(psw(7 downto 5)) < unsigned'("110") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif br6 = '1' and unsigned(psw(7 downto 5)) < unsigned'("110") then
state <= state_br6; -- external, level 6, vector determined by device
bg6 <= '1';
elsif pir_in(13) = '1' and unsigned(psw(7 downto 5)) < unsigned'("101") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif br5 = '1' and unsigned(psw(7 downto 5)) < unsigned'("101") then
state <= state_br5; -- external, level 5, vector determined by device
bg5 <= '1';
elsif pir_in(12) = '1' and unsigned(psw(7 downto 5)) < unsigned'("100") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif br4 = '1' and unsigned(psw(7 downto 5)) < unsigned'("100") then
state <= state_br4; -- external, level 4, vector determined by device
bg4 <= '1';
elsif pir_in(11) = '1' and unsigned(psw(7 downto 5)) < unsigned'("011") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif pir_in(10) = '1' and unsigned(psw(7 downto 5)) < unsigned'("010") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif pir_in(9) = '1' and unsigned(psw(7 downto 5)) < unsigned'("001") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif psw(4) = '1' and ir_rtt = '0' then
trap_vector <= o"014"; -- trace bit, vector = 014
state <= state_trap;
else
if ir_wait = '0' then -- if not in wait mode
state <= state_idecode; -- go process an instruction
ifetch <= '1'; -- set ifetch flag to signal instruction fetch to the outside world
else
ir_wait <= '1'; -- go into wait mode
end if;
sr1_srcd <= "00000"; -- setup mmu sr1 source part
sr1_dstd <= "00000"; -- setup mmu sr1 destination part
sr0_ic <= '1'; -- set mmu sr0 instruction complete flag
if modelcode = 44 -- fairly sure about this list, see kktb. Seems likely that at least 70 and J11 would also do this variant. However, not sure about F11 or other models
or modelcode = 45 or modelcode = 50 or modelcode = 55 -- and least sure of all about 45... but gamble is on this variant, seems 70 is most likely similar
or modelcode = 70
or modelcode = 73
or modelcode = 83
or modelcode = 84
or modelcode = 93
or modelcode = 94
then
sr2 <= r7; -- store address of instruction for mmu, sr2/mmr2
end if;
end if;
if have_pswimmediateupdate = 0 then -- some cpu models only effectuate the result of updates to the psw after the insn fetch following the update
if psw_delayedupdate_even = '1' then
psw(7 downto 5) <= psw_delayedupdate(7 downto 5); -- T bit can only be set with RTI/RTT instruction
if modelcode = 04 -- except for 11/04 etc
or modelcode = 05 or modelcode = 10
or modelcode = 15 or modelcode = 20
then
psw(4) <= psw_delayedupdate(4);
end if;
psw(3 downto 0) <= psw_delayedupdate(3 downto 0);
end if;
if psw_delayedupdate_odd = '1' then
psw(15 downto 8) <= psw_delayedupdate(15 downto 8);
rbus_cpu_mode <= psw_delayedupdate(15 downto 14); -- set rbus to the current cpu mode
end if;
psw_delayedupdate_even <= '0';
psw_delayedupdate_odd <= '0';
end if;
--
-- state_idecode; decode the instruction word and determine which path through the states will have to be initiated
--
--
-- first, set defaults for several status flags
--
when state_idecode =>
r7 <= r7p2; -- increment pc after instruction fetch
ir <= datain; -- store instruction word
ir_addr <= r7; -- store address of instruction
sr0_ic <= '0'; -- set instruction not complete in our part of sr0/mmr0
if modelcode = 34
or modelcode = 23 or modelcode = 24 -- fixme, verify this, but how?
then
sr2 <= r7; -- store address of instruction for mmu, sr2/mmr2
end if;
ir_fpmaf <= '0'; -- not a fp 4- or 8-byte memory access
ir_fpmai <= '0'; -- not a fp integer mode memory access
ir_sop <= '0'; -- current instruction is not single operand
ir_dop <= '0'; -- current instruction is not dual operand
ir_jmp <= '0'; -- current instruction is not jmp
ir_jsr <= '0'; -- current instruction is not jsr
ir_csm <= '0'; -- current instruction is not csm
ir_mfpi <= '0'; -- current instruction is not mfpi
ir_mfpd <= '0'; -- current instruction is not mfpd
ir_mtpi <= '0'; -- current instruction is not mtpi
ir_mtpd <= '0'; -- current instruction is not mtpd
ir_mtps <= '0'; -- current instruction is not mtps
ir_mfps <= '0'; -- current instruction is not mfps
ir_dopr <= '0'; -- current instruction is not dual operand register
ir_fpsop1 <= '0'; -- current instruction is not an fp single operand group 1 insn
ir_fpsop2 <= '0'; -- current instruction is not an fp single operand group 2 insn
ir_fpao <= '0'; -- current instruction is not an fp accumulator and operand insn
ir_facdst <= '0'; -- current instruction is not an fp accumulator and operand insn in cpu dst format
ir_facsrc <= '0'; -- current instruction is not an fp accumulator and operand insn in cpu src format
ir_facfdst <= '0'; -- current instruction is not an fp accumulator and operand insn in fp11 dst format
ir_facfsrc <= '0'; -- current instruction is not an fp accumulator and operand insn in fp11 src format
ir_mpr <= '0'; -- current instruction is not a multiprocessor instruction
ir_rtt <= '0'; -- current instruction is not rtt and no trace trap is being suppressed
fbus_fd <= fps(7); -- start on the assumption that access to the fp register set follows the fps fd flag
falu_pending_clear <= '1'; -- clear any leftover pending interrupt flags
state <= state_illegalop; -- set catch value in case we don't decode an insn
--
-- setup variables to classify which of several instruction groups the current instruction is, to make the decode logic easier to follow
--
-- sop - single operand insn
if datain(14 downto 9) = "0000101" -- single operand, word or byte (x05xxx)
or datain(14 downto 8) = "00001100" -- single operand, word or byte (x06xxx), first half of range
or datain(15 downto 6) = "0000000011" -- swab
or (datain(15 downto 6) = "0000110111" and have_sxt = 1) -- sxt
then
v_sop := '1';
else
v_sop := '0';
end if;
-- dop - double operand insn
if datain(14 downto 12) /= "000" and datain(14 downto 12) /= "111" then -- dop
v_dop := '1';
else
v_dop := '0';
end if;
-- jmp
if datain(15 downto 6) = "0000000001" then -- jmp
v_jmp := '1';
else
v_jmp := '0';
end if;
-- jsr
if datain(15 downto 9) = "0000100" then -- jsr
v_jsr := '1';
else
v_jsr := '0';
end if;
-- csm
if have_csm = 1 and datain(15 downto 6) = "0000111000" then -- csm
v_csm := '1';
else
v_csm := '0';
end if;
-- mfpi/mfpd/mtpi/mtpd
if have_mfp = 1 and datain(15 downto 6) = "0000110101" then -- mfpi
v_mfpi := '1';
else
v_mfpi := '0';
end if;
if have_mfp = 1 and datain(15 downto 6) = "1000110101" then -- mfpd
v_mfpd := '1';
else
v_mfpd := '0';
end if;
if have_mfp = 1 and datain(15 downto 6) = "0000110110" then -- mtpi
v_mtpi := '1';
else
v_mtpi := '0';
end if;
if have_mfp = 1 and datain(15 downto 6) = "1000110110" then -- mtpd
v_mtpd := '1';
else
v_mtpd := '0';
end if;
-- mtps/mfps
if have_mtps = 1 and datain(15 downto 6) = "1000110100" then -- mtps
v_mtps := '1';
else
v_mtps := '0';
end if;
if have_mtps = 1 and datain(15 downto 6) = "1000110111" then -- mfps
v_mfps := '1';
else
v_mfps := '0';
end if;
-- double operand, register - eis/xor
if (have_eis = 1 and datain(15 downto 11) = "01110") -- mul, div, ash, ashc
or (have_xor = 1 and datain(15 downto 9) = "0111100") then -- xor
v_dopr := '1';
else
v_dopr := '0';
end if;
-- multiprocessor insns - mpr
if have_mpr = 1 and datain(15 downto 7) = "000011101" then -- tstset/wrtlck
v_mpr := '1';
else
v_mpr := '0';
end if;
-- floating point insns - fpu, single op group 1 - those that dont have an ac as operand
if datain(15 downto 8) = "11110000"
and datain(7 downto 6) /= "00"
and have_fpu = 1
then -- fp11 single operand group 1: ldfps, stfps, stst
v_fpsop1 := '1';
else
v_fpsop1 := '0';
end if;
-- floating point insns - fpu, single op group 2 - those that have an ac as operand
if datain(15 downto 8) = "11110001"
and have_fpu = 1
then -- fp11 single operand group 2: clr(f/d), tst(f/d), abs(f/d), neg(f/d)
v_fpsop2 := '1';
else
v_fpsop2 := '0';
end if;
-- floating point insns - fpu, ac and operand group
if datain(15 downto 12) = "1111"
and datain(11 downto 9) /= "000"
and have_fpu = 1
then -- fp11 ac and operand group
v_fpao := '1';
else
v_fpao := '0';
end if;
--
-- setup signal copies of the variables just set, to be used in other states following idecode
--
if v_sop = '1' then
ir_sop <= '1';
end if;
if v_dop = '1' then
ir_dop <= '1';
end if;
if v_jmp = '1' then
ir_jmp <= '1';
end if;
if v_jsr = '1' then
ir_jsr <= '1';
end if;
if v_csm = '1' then
ir_csm <= '1';
end if;
if v_mfpi = '1' then
ir_mfpi <= '1';
end if;
if v_mfpd = '1' then
ir_mfpd <= '1';
end if;
if v_mtpi = '1' then
ir_mtpi <= '1';
end if;
if v_mtpd = '1' then
ir_mtpd <= '1';
end if;
if v_mtps = '1' then
ir_mtps <= '1';
end if;
if v_mfps = '1' then
ir_mfps <= '1';
end if;
if v_dopr = '1' then
ir_dopr <= '1';
end if;
if v_mpr = '1' then
ir_mpr <= '1';
end if;
-- with the floating point insns, here we also set flags that determine whether 2 or 4 (integer), or 4 or 8 (float/double) byte memory access is needed
if v_fpsop1 = '1' then
ir_fpsop1 <= '1';
end if;
if v_fpsop2 = '1' then
ir_fpsop2 <= '1';
ir_fpmaf <= '1';
end if;
if v_fpao = '1' then
ir_fpao <= '1';
ir_facdst <= '0';
ir_facsrc <= '0';
ir_facfdst <= '0';
ir_facfsrc <= '0';
if datain(11 downto 9) = "101" then -- stexp, stc(f|d)(i|l)
ir_facdst <= '1';
if datain(8) = '1' then -- stc(f|d)(i|l)
ir_fpmai <= '1'; -- needs 2 or 4 byte memory access
end if;
elsif datain(11 downto 8) = "1101" then -- ldexp
ir_facsrc <= '1';
elsif datain(11 downto 8) = "1110" then -- ldc(i|l)(f|d)
ir_facsrc <= '1';
ir_fpmai <= '1'; -- needs 2 or 4 byte memory access
elsif datain(11 downto 8) = "1000" then -- st(f|d)
ir_facfdst <= '1';
ir_fpmaf <= '1'; -- needs 4 or 8 byte memory access
elsif datain(11 downto 8) = "1100" then -- stc(f|d)
ir_facfdst <= '1';
ir_fpmaf <= '1'; -- needs 4 or 8 byte memory access
else -- if not any of the other special cases,
ir_facfsrc <= '1'; -- then it should be an fsrc format insn
ir_fpmaf <= '1'; -- needs 4 or 8 byte memory access
end if;
end if;
-- instruction decoder proper
if
v_sop = '1'
or v_dop = '1'
or v_jmp = '1'
or v_jsr = '1'
or v_csm = '1'
or v_mfpi = '1'
or v_mfpd = '1'
or v_mtpi = '1'
or v_mtpd = '1'
or v_mtps = '1'
or v_mfps = '1'
or v_dopr = '1'
or v_mpr = '1'
or v_fpsop1 = '1'
or v_fpsop2 = '1'
or v_fpao = '1'
then
case datain(5 downto 3) is
when "000" =>
psrcstate <= state_dst0;
when "001" =>
psrcstate <= state_dst1;
when "010" =>
psrcstate <= state_dst2;
when "011" =>
psrcstate <= state_dst3;
when "100" =>
psrcstate <= state_dst4;
when "101" =>
psrcstate <= state_dst5;
when "110" =>
psrcstate <= state_dst6;
when "111" =>
psrcstate <= state_dst7;
when others =>
null;
end case;
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
if v_dop = '1' then
case datain(11 downto 9) is
when "000" =>
rbus_ix <= datain(8 downto 6);
state <= state_src0;
when "001" =>
rbus_ix <= datain(8 downto 6);
state <= state_src1;
when "010" =>
rbus_ix <= datain(8 downto 6);
state <= state_src2;
when "011" =>
rbus_ix <= datain(8 downto 6);
state <= state_src3;
when "100" =>
rbus_ix <= datain(8 downto 6);
state <= state_src4;
when "101" =>
rbus_ix <= datain(8 downto 6);
state <= state_src5;
when "110" =>
rbus_ix <= datain(8 downto 6);
state <= state_src6;
when "111" =>
rbus_ix <= datain(8 downto 6);
state <= state_src7;
when others =>
null;
end case;
else
case datain(5 downto 3) is
when "000" =>
if v_jmp = '1' then
state <= state_illegalop; -- jmp with mode 0 is illegal
elsif v_jsr = '1' then
state <= state_illegalop; -- jsr with mode 0 is illegal
elsif have_mfp = 1 and (v_mfpi = '1' or v_mfpd = '1') then
if datain(2 downto 0) = "110" then
rbus_cpu_mode <= psw(13 downto 12);
end if;
rbus_ix <= datain(2 downto 0);
state <= state_dst0;
elsif have_mfp = 1 and (v_mtpi = '1' or v_mtpd = '1') then -- if mode is 0, it's not very interesting to try and read the register
rbus_ix <= "110";
state <= state_mtp;
elsif have_mpr = 1 and v_mpr = '1' then
state <= state_illegalop; -- tstset/wrtlck mode 0 are illegal
elsif have_fpu = 1 and v_fpao = '1' then
if datain(11 downto 9) /= "101" -- stexp, stc(f/d)(i/l)
and datain(11 downto 8) /= "1101" -- ldexp
and datain(11 downto 8) /= "1110" -- ldc(i/l)(f/d)
then
if datain(2 downto 1) = "11" then -- ac6 and ac7 do not exist
fec <= "0010";
state <= state_fptrap;
else
if datain(11) & datain(9 downto 8) = "100" then
fbus_raddr <= '0' & datain(7 downto 6); -- fdst insn, need ac
else
fbus_raddr <= datain(2 downto 0); -- fsrc insn, need mode 0 fsrc ac
end if;
state <= state_fpao;
end if;
else
fbus_raddr <= '0' & datain(7 downto 6); -- ldexp, ldc(i/l)(f/d), stexp, stc(f/d)(i/l) get ac
rbus_ix <= datain(2 downto 0);
state <= state_dst0;
end if;
elsif have_fpu = 1 and v_fpsop2 = '1' then
if datain(2 downto 1) = "11" then -- ac6 and ac7 do not exist
fec <= "0010";
state <= state_fptrap;
else
fbus_raddr <= datain(2 downto 0); -- fsrc insn, need mode 0 fsrc ac
state <= state_fpso2;
end if;
else
rbus_ix <= datain(2 downto 0);
state <= state_dst0;
end if;
when "001" =>
state <= state_dst1;
rbus_ix <= datain(2 downto 0);
when "010" =>
state <= state_dst2;
rbus_ix <= datain(2 downto 0);
when "011" =>
state <= state_dst3;
rbus_ix <= datain(2 downto 0);
when "100" =>
state <= state_dst4;
rbus_ix <= datain(2 downto 0);
when "101" =>
state <= state_dst5;
rbus_ix <= datain(2 downto 0);
when "110" =>
state <= state_dst6;
rbus_ix <= datain(2 downto 0);
when "111" =>
state <= state_dst7;
rbus_ix <= datain(2 downto 0);
when others =>
null;
end case;
if v_sop = '1' then
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
elsif v_jmp = '1' then
pdststate <= state_jmp;
elsif v_jsr = '1' then
pdststate <= state_jsr;
elsif v_csm = '1' then
pdststate <= state_csm;
elsif v_mfpi = '1' or v_mfpd = '1' then
pdststate <= state_mfp;
elsif v_mtpi = '1' or v_mtpd = '1' then
rbus_ix <= "110";
state <= state_mtp;
elsif have_mtps = 1 and v_mtps = '1' then
pdststate <= state_mtps;
elsif have_mtps = 1 and v_mfps = '1' then
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
elsif v_dopr = '1' then
pdststate <= state_dopr;
elsif v_mpr = '1' then
if datain(6) = '0' then
pdststate <= state_tstset;
else
pdststate <= state_wrtlck;
end if;
elsif have_fpu = 1 and v_fpsop1 = '1' then
case datain(7 downto 6) is
when "01" => -- ldfps
pdststate <= state_ldfps;
when "10" => -- stfps
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
when "11" => -- stst
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
when others =>
null;
end case;
elsif have_fpu = 1 and v_fpsop2 = '1' then
pdststate <= state_fpso2; -- clr(f|d),tst(f|d),abs(f|d),neg(f|d)
elsif have_fpu = 1 and v_fpao = '1' then
pdststate <= state_fpao;
if datain(11 downto 8) = "1101" -- ldexp
or datain(11 downto 8) = "1010" -- stexp
or datain(11) & datain(9 downto 8) = "100" -- st(f|d), stc(f|d)(d|f)
or datain(11 downto 8) = "1011" -- stc(f|d)(i|l)
then
fbus_raddr <= '0' & datain(7 downto 6); -- needed for st(f|d), stc(f|d)(d|f), ldexp, stexp
end if;
else
pdststate <= state_illegalop;
end if;
end if;
end if;
if datain(14 downto 11) = "0000" then -- pc and ps change, excl. jsr, emt, trap
if datain(15) = '0' and datain(10 downto 8) = "000" then -- halt group, jmp
-- halt is a complicated case - it is handled differently by most models - it traps either to 4, 10, or to the console, or plainly halts
-- don't have a console yet - so the last two are simple. Still, the mode bit for the J11 came as a surprise - thought I had seen all variants.
if datain(7 downto 0) = "00000000" then -- halt
if pswmf(15 downto 14) /= "00"
and (modelcode = 73 or modelcode = 44 or modelcode = 45 or modelcode = 50 or modelcode = 55 or modelcode = 70 or modelcode = 84 or modelcode = 83 or modelcode = 93 or modelcode = 94)
then
illhalt <= '1';
trap_vector <= o"004";
state <= state_trap;
elsif pswmf(15 downto 14) /= "00"
and (modelcode = 23 or modelcode = 24 or modelcode = 34 or modelcode = 35 or modelcode = 40 or modelcode = 60)
then
illhalt <= '1';
trap_vector <= o"010";
state <= state_trap;
elsif modelcode = 3 or modelcode = 21 or modelcode = 4 or modelcode = 5 or modelcode = 10 or modelcode = 15 or modelcode = 20
then
ir_halt <= '1';
state <= state_ifetch;
elsif pswmf(15 downto 14) = "00" and cpu_kmillhalt = '1'
then
illhalt <= '1';
trap_vector <= o"004";
state <= state_trap;
elsif pswmf(15 downto 14) = "00"
then
ir_halt <= '1';
state <= state_ifetch;
else -- the default, if we do not know the model of the cpu, is to follow the rule of J11
illhalt <= '1';
trap_vector <= o"004";
state <= state_trap;
end if;
end if;
if datain(7 downto 0) = "00000001" then -- wait
if pswmf(15 downto 14) = "00" then -- if not in kernel mode, this insn is a noop
ir_wait <= '1'; -- setting this flag will cause ifetch not to switch into idecode until an interrupt has occurred
end if;
state <= state_ifetch; -- next state is ifetch
end if;
if datain(7 downto 0) = "00000010" then -- rti
state <= state_rti;
rbus_ix <= "110";
if modelcode = 4 -- these models do not have rtt, but allow rti to set the t bit
or modelcode = 5 or modelcode = 10
or modelcode = 15 or modelcode = 20
then
if psw(4) = '0' then
ir_rtt <= '1';
end if;
end if;
end if;
if datain(7 downto 0) = "00000011" then -- bpt
trap_vector <= o"014"; -- bpt, vector = 014
state <= state_trap;
end if;
if datain(7 downto 0) = "00000100" then -- iot
trap_vector <= o"020"; -- iot, vector = 020
state <= state_trap;
end if;
if datain(7 downto 0) = "00000101" then -- reset
if pswmf(15 downto 14) = "00" then
initcycles <= 7; -- not as long as the original specs say, but just a bit more than a single cycle
state <= state_init;
else
state <= state_ifetch; -- reset is a no-op when not in kernel mode
end if;
end if;
if have_rtt = 1 and datain(7 downto 0) = "00000110" then -- rtt
state <= state_rti;
rbus_ix <= "110";
ir_rtt <= '1';
end if;
--
-- mfpt : the opcode 000007 is used by some diagnostics, including at least fkaa, 11/34 basic inst tst, to trigger an illegal instruction trap
-- also, obviously it should work differently for the appropriate models
--
if datain(7 downto 0) = "00000111" then -- mfpt
if modelcode = 21 then
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= '0' & o"00004"; -- 4 = T-11
rbus_we <= '1';
end if;
if modelcode = 23 or modelcode = 24 then
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= '0' & o"00003"; -- 3 = F-11
rbus_we <= '1';
end if;
if modelcode = 44 then
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= '0' & o"00001"; -- 1 = 11/44
rbus_we <= '1';
end if;
if modelcode = 73
or modelcode = 53
or modelcode = 83
or modelcode = 84
or modelcode = 93
or modelcode = 94
then
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= '0' & o"00005"; -- 5 = J11
rbus_we <= '1';
end if;
end if;
if datain(7 downto 3) = "10000" then -- rts
state <= state_rts;
rbus_ix <= "110";
end if;
if have_spl = 1 and datain(7 downto 3) = "10011" then -- spl
if pswmf(15 downto 14) = "00" then
psw(7 downto 5) <= datain(2 downto 0);
end if;
state <= state_ifetch;
end if;
if datain(7 downto 4) = "1010" then -- clear cc
psw(3 downto 0) <= psw(3 downto 0) and (not datain(3 downto 0));
state <= state_ifetch;
end if;
if datain(7 downto 4) = "1011" then -- set cc
psw(3 downto 0) <= psw(3 downto 0) or datain(3 downto 0);
state <= state_ifetch;
end if;
else -- branch group
-- the branch insns used to have a separate state to actually do the branch, including calculating the effective address
-- this variant, however notationally inelegant, uses less logic, and less cycles as well.
state <= state_ifetch;
case datain(15) & datain(10 downto 8) is
when "0001" => -- br
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
when "0010" => -- bne
if psw(2) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0011" => -- beq
if psw(2) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0100" => -- bge
if psw(3) = psw(1) then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0101" => -- blt
if psw(3) /= psw(1) then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0110" => -- bgt
if psw(2) = '0' and psw(3) = psw(1) then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0111" => -- ble
if psw(2) = '1' or psw(3) /= psw(1) then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1000" => -- bpl
if psw(3) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1001" => -- bmi
if psw(3) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1010" => -- bhi
if psw(2) = '0' and psw(0) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1011" => -- blos
if psw(2) = '1' or psw(0) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1100" => -- bvc
if psw(1) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1101" => -- bvs
if psw(1) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1110" => -- bhis
if psw(0) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1111" => -- blo
if psw(0) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when others =>
null;
end case;
end if;
end if;
if datain(15 downto 9) = "1000100" then -- trap, emt etc
if datain(8) = '0' then
trap_vector <= o"030"; -- emt, vector = 030
else
trap_vector <= o"034"; -- trap, vector = 034
end if;
state <= state_trap;
end if;
if have_sob = 1 and datain(15 downto 9) = "0111111" then -- sob
rbus_ix <= datain(8 downto 6);
state <= state_sob;
if have_sob_zkdjbug = 1 and (modelcode = 73 or modelcode = 83 or modelcode = 84 or modelcode = 93 or modelcode = 94) then
sob_slowdown <= 255;
end if;
end if;
if have_mark = 1 and datain(15 downto 6) = "0000110100" then -- mark
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= unsigned(r7p2) + unsigned(datain(5 downto 0) & '0');
rbus_we <= '1';
rbus_ix <= "101";
state <= state_mark;
end if;
if have_fpu = 1 and datain(15 downto 6) = "1111000000" then -- fp11 operate group
case datain(5 downto 0) is
when "000000" => -- cfcc
psw(3 downto 0) <= fps(3 downto 0);
state <= state_ifetch;
when "000001" => -- setf
fps(7) <= '0';
state <= state_ifetch;
when "000010" => -- seti
fps(6) <= '0';
state <= state_ifetch;
when "001001" => -- setd
fps(7) <= '1';
state <= state_ifetch;
when "001010" => -- setl
fps(6) <= '1';
state <= state_ifetch;
when others =>
if modelcode = 45 or modelcode = 50 or modelcode = 55 or modelcode = 70 then
if datain(5 downto 3) = "000" then
state <= state_ifetch; -- allow 45/55/70 specific insns ldub, ldsc, stao, mrs, stq0 not to cause a trap
else
fec <= "0010"; -- unknown insn, start trap seq
state <= state_fptrap;
end if;
else
fec <= "0010"; -- unknown insn, start trap seq
state <= state_fptrap;
end if;
end case;
end if;
--
-- illegal op : used for both catching unknown opcodes and for illegal operands to jmp and jsr, also tstset/wrtlck
--
when state_illegalop =>
--
-- vector for illegal operand, register mode jmp or jsr
-- manuals seem to incorrectly list what vector should be used; systems use either 004 or 010.
-- for instance, EK-DCJ11-UG-PRE_J11ug_Oct83.pdf pg. C-7 item 5
-- however, diagnostics reveal the following:
-- 11/34 - 004, source AC-8045D-MC_CFKABD0-1134-Traps-Tst_Apr77.pdf
-- 11/44 - 010, confirmed by running kkab
-- 11/45 - 010, source PDP1145_Handbook_1973.pdf, pg. 230
-- J11 - 010, source 0095_CZKDJB0_KDJ11.pdf, seq 166/K13
--
if have_fpu = 1 and ir(15 downto 12) = "1111" then
fec <= "0010";
state <= state_fptrap;
elsif ir_jmp = '1' or ir_jsr = '1' then
if modelcode = 34
or modelcode = 4 -- verified 04 behaviour by running gkab
then
trap_vector <= o"004";
else
trap_vector <= o"010";
end if;
state <= state_trap;
else
trap_vector <= o"010"; -- illegal op, vector = 010
state <= state_trap;
end if;
--
-- jmp : move dest addr as computed into r7
--
when state_jmp =>
r7 <= dest_addr;
state <= state_ifetch;
--
-- npg : non-processor grant, ie. allow the bus to another bus master while the npr signal is active
--
when state_npg =>
if npr = '0' then
state <= state_ifetch;
npg <= '0';
else
npg <= '1';
end if;
--
-- mmuabort : the mmu requests an abort of the current instruction, potentially halfway trough an instruction
--
when state_mmuabort =>
if have_psw1512 = 1 and mmuabort = '0' then
ack_mmuabort <= '0';
trap_vector <= o"250"; -- mmu, vector = 250
state <= state_trap;
end if;
--
-- mmutrap : the mmu has requested a trap after the current instruction has finished; this trap will now be initiated
--
when state_mmutrap =>
if have_psw1512 = 1 and mmutrap = '0' then
ack_mmutrap <= '0';
trap_vector <= o"250"; -- mmu, vector = 250
state <= state_trap;
end if;
-- bus request aka interrupt, prio level 7; handle br7/bg7 signals and initiate trap
when state_br7 =>
if br7 = '0' then
bg7 <= '0';
trap_vector <= int_vector7;
state <= state_trap;
if modelcode = 45 or modelcode = 50 or modelcode = 55
or modelcode = 70 then
sr2 <= "0000000" & int_vector7; -- set trap vector in sr2
sr0_ic <= '0'; -- make sure to flag instruction not complete
end if;
end if;
-- bus request, prio level 6; handle br6/bg6 signals and initiate trap
when state_br6 =>
if br6 = '0' then
bg6 <= '0';
trap_vector <= int_vector6;
state <= state_trap;
if modelcode = 45 or modelcode = 50 or modelcode = 55
or modelcode = 70 then
sr2 <= "0000000" & int_vector6; -- set trap vector in sr2
sr0_ic <= '0'; -- make sure to flag instruction not complete
end if;
end if;
-- bus request, prio level 5; handle br5/bg5 signals and initiate trap
when state_br5 =>
if br5 = '0' then
bg5 <= '0';
trap_vector <= int_vector5;
state <= state_trap;
if modelcode = 45 or modelcode = 50 or modelcode = 55
or modelcode = 70 then
sr2 <= "0000000" & int_vector5; -- set trap vector in sr2
sr0_ic <= '0'; -- make sure to flag instruction not complete
end if;
end if;
-- bus request, prio level 4; handle br4/bg4 signals and initiate trap
when state_br4 =>
if br4 = '0' then
bg4 <= '0';
trap_vector <= int_vector4;
state <= state_trap;
if modelcode = 45 or modelcode = 50 or modelcode = 55
or modelcode = 70 then
sr2 <= "0000000" & int_vector4; -- set trap vector in sr2
sr0_ic <= '0'; -- make sure to flag instruction not complete
end if;
end if;
-- floating point error trap : precursor state handles fid bit in fps and contents of fea, and pending conditions signalled by the floating point alu
when state_fptrap =>
if falu_pending_fic = '1' then -- note the order... if more than one bit is set, the order of precedence is v, u, c
fec <= "0110";
end if;
if falu_pending_fiu = '1' then
fec <= "1010";
end if;
if falu_pending_fiv = '1' then
fec <= "1000";
end if;
if falu_pending_divz = '1' then
fec <= "0100";
end if;
fea <= ir_addr;
fps(15) <= '1';
if fps(14) = '0' then
trap_vector <= o"244"; -- floating point trap, vector = 244
state <= state_trap;
else -- wait for pending interrupt flags to clear before continuing
if falu_pending_fic = '0' and falu_pending_fiu = '0' and falu_pending_fiv = '0' and falu_pending_divz = '0' then
state <= state_ifetch;
end if;
end if;
falu_pending_clear <= '1';
--
-- rsv: red stack trap
-- implemented by setting the kernel sp to 4, and then starting a trap
-- the trap states will then decrement the sp, and save psw and r7 in
-- the right locations.
-- this approach is not necessarily correct, but passes czkdjb0
-- and it is also as described in EK-KDJ1B-UG_KDJ11-B_Nov86.pdf
-- in chapter 1.3.2, page 1-10
-- this takes some extra attention when sequencing through the
-- trap code to select kernel sp, though. Need to ignore whatever
-- is set in loc. 6
--
-- some extra explanation is probably needed for the copying of
-- psw from temp_psw. The reason is as follows: a red trap by
-- definition is a result from an earlier trap gone wrong. In the
-- first step of a normal trap, the psw is copied into temp_psw.
-- State_rsv restores that original psw into the real psw - then
-- starts a new trap.
--
when state_rsv =>
if have_red = 1 then
psw <= temp_psw;
rbus_waddr <= "00" & "0110";
rbus_d <= x"0004";
rbus_we <= '1';
trap_vector <= o"004"; -- red stack trap, vector = 004
state <= state_trap;
end if;
-- trap: start a trap sequence, trap through trapf
when state_trap =>
temp_psw <= psw;
psw(15 downto 14) <= "00"; -- initial, we'll load the real mode to select the correct stack by in the next step
psw(13 downto 12) <= pswmf(15 downto 14);
rbus_cpu_mode <= "00"; -- force rbus cpu mode to 00 - this is output to the mmu to select the par/pdr set
state <= state_trapa;
when state_trapa =>
rbus_ix <= "110";
if have_red = 1 and red_stack_trap = '1' then
rbus_cpu_mode <= "00";
else
rbus_cpu_mode <= datain(15 downto 14);
end if;
psw(15 downto 14) <= datain(15 downto 14);
psw(11 downto 0) <= datain(11 downto 0);
state <= state_trapb;
when state_trapb =>
state <= state_trapc;
when state_trapc =>
if have_red = 1 and red_stack_trap = '1' then
rbus_waddr <= "00" & "0110";
else
rbus_waddr <= pswmf(15 downto 14) & "0110";
end if;
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_trapw;
when state_trapw =>
state <= state_trapd;
when state_trapd =>
if have_red = 1 and red_stack_trap = '1' then
rbus_waddr <= "00" & "0110";
else
rbus_waddr <= pswmf(15 downto 14) & "0110";
end if;
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_trape;
when state_trape =>
rbus_cpu_mode <= "00"; -- force rbus cpu mode to 00 - this is output to the mmu to select the par/pdr set
state <= state_trapf;
when state_trapf =>
r7 <= datain;
state <= state_ifetch;
-- rti: start a rti sequence, rti through rtib
when state_rti =>
state <= state_rtia;
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
when state_rtia =>
state <= state_rtib;
r7 <= datain;
when state_rtib =>
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
if modelcode = 4 then -- FIXME, probably other models as well - 5, 10, 15, 20? 04 behaviour tested with gkab
psw_delayedupdate <= datain;
psw_delayedupdate_even <= '1';
psw_delayedupdate_odd <= '1';
else
psw(4 downto 0) <= datain(4 downto 0);
if pswmf(15 downto 14) = "00" then
psw(7 downto 5) <= datain(7 downto 5);
end if;
psw(10 downto 8) <= datain(10 downto 8);
if pswmf(15 downto 14) = "00" then
psw(15 downto 11) <= datain(15 downto 11);
else
psw(15 downto 11) <= datain(15 downto 11) or pswmf(15 downto 11);
end if;
end if;
-- csm : process csm insn
when state_csm =>
if have_csm = 1 and sr3csmenable = '1' and psw(15 downto 14) /= "00" then
temp_psw(15 downto 4) <= psw(15 downto 4);
temp_psw(3 downto 0) <= "0000";
psw(15 downto 14) <= "01";
psw(13 downto 12) <= psw(15 downto 14);
psw(4) <= '0';
rbus_ix <= "110";
rbus_cpu_mode <= psw(15 downto 14);
state <= state_csma;
else
state <= state_illegalop;
end if;
when state_csma =>
rbus_waddr <= "01" & "0110"; -- address super sp
rbus_d <= rbus_data;
rbus_we <= '1';
state <= state_csmb;
when state_csmb =>
rbus_cpu_mode <= "01";
state <= state_csmc;
when state_csmc => -- push temp_psw
rbus_waddr <= "01" & "0110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_csmd;
when state_csmd =>
state <= state_csme;
when state_csme => -- push pc
rbus_waddr <= "01" & "0110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_csmf;
when state_csmf =>
state <= state_csmg;
when state_csmg => -- push alu_output
rbus_waddr <= "01" & "0110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_csmh;
when state_csmh =>
trap_vector <= o"010"; -- csm loads r7 from vector = 010, but from supervisor I-space
state <= state_csmi;
when state_csmi =>
r7 <= datain;
state <= state_ifetch;
-- sob: deal with sob instruction
when state_sob =>
if have_sob_zkdjbug = 1 and (modelcode = 73 or modelcode = 83 or modelcode = 84 or modelcode = 93 or modelcode = 94) then
if sob_slowdown = 0 then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_m1;
rbus_we <= '1';
if rbus_data_m1 = "0000000000000000" then
state <= state_ifetch;
else
r7 <= r7 - (ir(5 downto 0) & '0');
state <= state_ifetch;
end if;
else
sob_slowdown <= sob_slowdown - 1;
end if;
else
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_m1;
rbus_we <= '1';
if rbus_data_m1 = "0000000000000000" then
state <= state_ifetch;
else
r7 <= r7 - (ir(5 downto 0) & '0');
state <= state_ifetch;
end if;
end if;
-- move from previous i/d
when state_mfp =>
rbus_ix <= "110";
state <= state_mfpa;
when state_mfpa =>
dest_addr <= addr;
state <= state_store_alu_p;
sr1_srcd <= sr1_m2; -- it is the dest, actually - but that field is already used
rbus_waddr <= psw(15 downto 14) & '0' & "110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
-- move to previous i/d
when state_mtp =>
sr1_srcd <= sr1_p2;
rbus_waddr <= psw(15 downto 14) & '0' & "110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
state <= state_mtpa;
when state_mtpa =>
alus_input <= datain;
rbus_ix <= ir(2 downto 0);
state <= psrcstate;
-- mtps insn - move to ps
when state_mtps =>
if have_mtps = 1 then
if psw(15 downto 14) = "00" then
psw(7 downto 5) <= alu_output(7 downto 5);
psw(3 downto 0) <= alu_output(3 downto 0);
else
psw(3 downto 0) <= alu_output(3 downto 0);
end if;
state <= state_ifetch;
end if;
-- double operand,register instruction states dopr through doprb
-- these are for the EIS instruction set, ie mul, div, ash, ashc, xor
-- dopr is a precursor state, used to pick up the second operand from
-- the register file
when state_dopr =>
rbus_ix <= ir(8 downto 6);
state <= state_dopra;
-- dopra: setup the eis_sequencer to handle microstates for the eis alu
-- and dispatch to the states needed for each insn; also setup to read
-- ternary operand from the register file
when state_dopra =>
alus_input <= rbus_data;
rbus_ix <= ir(8 downto 7) & '1';
if ir(11 downto 9) = "000" then
eis_sequencer <= "11111";
state <= state_mul;
elsif ir(11 downto 9) = "010" then
eis_sequencer <= "11111";
state <= state_ash;
elsif ir(11 downto 9) = "100" then
state <= state_xor;
else
state <= state_doprb;
end if;
-- doprb: read ternary operand from the rbus, setup the
-- eis_sequencer for div and ashc
when state_doprb =>
alut_input <= rbus_data;
if ir (11 downto 9) = "001" then
if ir(6) = '1' then -- illegal, R must be even acc. EK-KDJ1B-UG_KDJ11-B_Nov86.pdf, pg. 9-31, and PDP1145_Handbook_1973.pdf, pg. 71
state <= state_ifetch; -- FIXME, does it make sense to go back to ifetch from here if the ir was illegal?
psw(3 downto 0) <= "0010"; -- not sure if this makes sense, but CZKDJB0 won't pass without
else
eis_sequencer <= "10000";
state <= state_div;
end if;
elsif ir(11 downto 9) = "011" then
eis_sequencer <= "11111";
state <= state_ashc;
else
state <= state_illegalop; -- should not be possible
end if;
-- mul through mulb: handle mul insn
when state_mul =>
if eis_sequencer = "00001" then
state <= state_mula;
end if;
eis_sequencer <= eis_sequencer + 1;
when state_mula =>
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= eis_output;
rbus_we <= '1';
else
r7 <= eis_output;
end if;
state <= state_mulb;
when state_mulb =>
if ir(8 downto 7) /= "11" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 7) & '1';
rbus_d <= eis_output32;
rbus_we <= '1';
else
r7 <= eis_output32;
end if;
psw(3 downto 0) <= eis_psw;
state <= state_ifetch;
-- div through divb: handle div insn
when state_div =>
if eis_sequencer = "11111" then
state <= state_diva;
end if;
eis_sequencer <= eis_sequencer - 1;
when state_diva =>
if eis_psw(1 downto 0) = "00" then
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= eis_output;
rbus_we <= '1';
else
r7 <= eis_output;
end if;
end if;
state <= state_divb;
when state_divb =>
if eis_psw(1 downto 0) = "00" then
if ir(8 downto 7) /= "11" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 7) & '1';
rbus_d <= eis_output32;
rbus_we <= '1';
else
r7 <= eis_output32;
end if;
end if;
psw(3 downto 0) <= eis_psw;
state <= state_ifetch;
-- ash through ashb: handle ash insn
when state_ash =>
if eis_sequencer = "11111" then
eis_sequencer <= eis_sequencer + 1;
else
if eis_flag2 = '1' then
state <= state_ashb;
end if;
end if;
when state_ashb =>
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= eis_output;
rbus_we <= '1';
else
r7 <= eis_output;
end if;
psw(3 downto 0) <= eis_psw;
state <= state_ifetch;
-- ashc through ashe: handle ashc insn
when state_ashc =>
if eis_sequencer = "11111" then
eis_sequencer <= eis_sequencer + 1;
else
if eis_flag2 = '1' then
state <= state_ashd;
end if;
end if;
when state_ashd =>
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= eis_output;
rbus_we <= '1';
else
r7 <= eis_output;
end if;
state <= state_ashe;
when state_ashe =>
if ir(8 downto 7) /= "11" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 7) & '1';
rbus_d <= eis_output32;
rbus_we <= '1';
else
r7 <= eis_output32;
end if;
psw(3 downto 0) <= eis_psw;
state <= state_ifetch;
-- xor: dispatch to state that stores result
when state_xor =>
if ir(5 downto 3) = "000" then
state <= state_store_alu_r;
else
state <= state_store_alu_p;
end if;
-- ldfps - load fpu state
when state_ldfps =>
fps <= alu_output;
state <= state_ifetch;
-- stst - store fpu fec and fea
when state_stststore =>
state <= state_ifetch;
-- dispatch insn in the fpso2 group - unless the insn is a clr(f|d), go into the
-- states that read an fp src operand
when state_fpso2 =>
addr_indirect <= dest_addr;
if ir(5 downto 3) /= "000" then
if ir(7 downto 6) = "00" then -- clr(f|d)
state <= state_fprun; -- don't need to read for clear
else
state <= state_fpr1;
end if;
else
falu_input <= fbus_o; -- fbus read already done in ifetch for mode 0
state <= state_fprun;
end if;
-- dispatch insn groups for the fp acc and operand format, in
-- all forms - fsrc, fsdt, src, dst, as signalled by the main
-- state machine - and cycle into the appropriate state to
-- handle the core accesses that are required to load the
-- operands, either in f|d, or i|l format.
when state_fpao =>
if ir(5 downto 3) /= "000" then
addr_indirect <= dest_addr;
if ir_facfsrc = '1' then
fbus_raddr <= '0' & ir(7 downto 6);
state <= state_fpr1;
elsif ir_facfdst = '1' then
falu_input <= fbus_o;
state <= state_fprun;
elsif ir_facdst = '1' then
falu_input <= fbus_o;
state <= state_fprun;
elsif ir_facsrc = '1' then
falu_input <= fbus_o;
state <= state_fpir1;
else
-- FIXME, go into some cpu error state?
end if;
else -- mode 0, so input from register!!!
if ir_facfsrc = '1' then
falu_input <= fbus_o;
fbus_raddr <= '0' & ir(7 downto 6);
state <= state_fprun;
elsif ir_facfdst = '1' then
falu_input <= fbus_o;
state <= state_fprun;
elsif ir_facdst = '1' then
falu_input <= fbus_o;
state <= state_fprun;
elsif ir_facsrc = '1' then
if ir(8) = '1' then -- ldexp
falu_input <= fbus_o;
falus_input(55 downto 40) <= rbus_data;
else -- ldc(i|l)(f|d)
falu_input(55 downto 40) <= "0000000000000000";
falu_input(39 downto 24) <= rbus_data;
falu_input(23 downto 0) <= "000000000000000000000000";
end if;
state <= state_fprun; -- FIXME, what about long data?
end if;
end if;
when state_fpir1 =>
if ir(8) = '1' then -- state is reachable only for ldexp and ldc(i|l)(f|d); ir(8) = 1 means ldexp
state <= state_fprun; -- ldexp
falus_input(55 downto 40) <= datain; -- FIXME, it does not really make sense to put the input value here?
else
falu_input(23 downto 0) <= "000000000000000000000000";
if fps(6) = '1' and ir(5 downto 0) /= "010111" then -- ldc(i|l)(f|d) mode 2, reg 7 : then only 1 word to be read
falu_input(55 downto 40) <= datain;
addr_indirect <= addr_indirect + 2;
state <= state_fpir2;
else
falu_input(55 downto 40) <= "0000000000000000";
falu_input(39 downto 24) <= datain;
state <= state_fprun;
end if;
end if;
when state_fpir2 =>
falu_input(39 downto 24) <= datain;
state <= state_fprun;
when state_fpr1 =>
if datain(15 downto 7) = "100000000" and fps(11) = '1' and fps(14) = '0' then -- do we need to trigger the fiuv trap for -0, undefined variable?
state <= state_fptrap; -- cause trap
fps(15) <= '1'; -- set error flag
fec <= "1100"; -- fiuv code
else
if datain(15 downto 7) = "100000000" and fps(11) = '1' then -- if interrupts are disabled, we still signal the error... FIXME, is this required at all?
fps(15) <= '1'; -- set error flag
fec <= "1100"; -- fiuv code
end if;
falu_input(63 downto 48) <= datain;
addr_indirect <= addr_indirect + 2;
if ir(5 downto 0) = "010111" then -- mode 2, reg 7 : then only 1 word to be loaded
falu_input(47 downto 0) <= "000000000000000000000000000000000000000000000000";
state <= state_fprun;
else
state <= state_fpr2;
end if;
end if;
when state_fpr2 =>
falu_input(47 downto 32) <= datain;
if fps(7) = '1' -- if mode is d
or (fps(7) = '0' and ir(11 downto 8) = "1111") -- or if mode is f, and the insn is ldcfd
then -- then we need to read the next two words
state <= state_fpr3;
addr_indirect <= addr_indirect + 2;
else
falu_input(31 downto 0) <= "00000000000000000000000000000000"; -- if mode is f, insn is not ldcfd, zero out the low 32 bits of the input
state <= state_fprun;
end if;
when state_fpr3 =>
falu_input(31 downto 16) <= datain;
addr_indirect <= addr_indirect + 2;
state <= state_fpr4;
when state_fpr4 =>
falu_input(15 downto 0) <= datain;
state <= state_fprun;
when state_fpwr =>
fbus_d <= falu_output;
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
fbus_waddr <= '0' & ir(7 downto 6);
fbus_we <= '1';
state <= state_ifetch;
if ir(11 downto 8) = "0011" and ir(6) = '0' then -- mod with even ac, need to store ac+1
state <= state_fpwr1;
end if;
when state_fpwr1 =>
state <= state_fpwr2;
when state_fpwr2 =>
fbus_d <= falu_output2;
fbus_waddr <= '0' & ir(7) & '1';
fbus_we <= '1';
state <= state_ifetch;
when state_fpd0 =>
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
if ir_fpsop2 = '1' and ir(7 downto 6) = "01" then -- tst(f/d)
state <= state_ifetch;
elsif ir(2 downto 1) /= "11" then
fbus_d <= falu_output;
fbus_waddr <= ir(2 downto 0);
fbus_we <= '1';
end if;
state <= state_ifetch;
when state_fpiwr =>
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= falu_output(63 downto 48);
rbus_we <= '1';
else
r7 <= falu_output(63 downto 48); -- FIXME, check what real pdp's do?
end if;
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
psw(3 downto 0) <= falu_fps;
state <= state_ifetch;
when state_fpiww =>
addr_indirect <= dest_addr;
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
psw(3 downto 0) <= falu_fps;
state <= state_fpiw1;
when state_fpiw1 =>
if ir(5 downto 0) = "010111" -- stc(f|d)(i|l) mode 2, reg 7 : then only 1 word to be written
or fps(6) = '0' -- stc(f|d)(i|l), short integer mode
or ir(11 downto 8) = "1010" -- stexp insn
then
state <= state_ifetch;
else
addr_indirect <= addr_indirect + 2;
state <= state_fpiw2;
end if;
when state_fpiw2 =>
state <= state_ifetch;
when state_fpww =>
addr_indirect <= dest_addr;
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
if ir_fpsop2 = '1' and ir(7 downto 6) = "01" then -- tst(f/d)
state <= state_ifetch;
else
state <= state_fpw1;
end if;
when state_fpw1 =>
if ir(5 downto 0) = "010111" then -- mode 2, reg 7 : then only 1 word to be written
state <= state_ifetch;
else
addr_indirect <= addr_indirect + 2;
state <= state_fpw2;
end if;
when state_fpw2 =>
if (fps(7) = '1' and ir(11 downto 8) /= "1100") -- reverse sense of fps D bit when insn is stc(f|d)(d|f)
or (fps(7) = '0' and ir(11 downto 8) = "1100")
then
state <= state_fpw3;
addr_indirect <= addr_indirect + 2;
else
state <= state_ifetch;
end if;
when state_fpw3 =>
addr_indirect <= addr_indirect + 2;
state <= state_fpw4;
when state_fpw4 =>
state <= state_ifetch;
when state_fprun =>
if ir_fpao = '1' then
if ir_facfsrc = '1' then
falus_input <= fbus_o;
end if;
state <= state_fprunao;
falu_load <= '1';
falu_state <= 0;
elsif ir_fpsop2 = '1' then
if ir(5 downto 3) = "000" then
state <= state_fpd0;
else
state <= state_fpww;
end if;
else
state <= state_ifetch; -- FIXME, needed?
end if;
when state_fprunao =>
falu_state <= falu_state + 1;
falu_load <= '0';
if falu_state > 160 then -- FIXME, this may prevent hangs. Why?
state <= state_ifetch; -- FIXME, error!
end if;
if falu_done = '1' then
falu_state <= 0;
case ir(11 downto 8) is
when "1000" => -- st(f|d)
if ir(5 downto 3) = "000" then
state <= state_fpd0;
else
state <= state_fpww;
end if;
when "1010" => -- stexp
if ir(5 downto 3) = "000" then
state <= state_fpiwr;
else
state <= state_fpiww;
end if;
when "1011" => -- stc(f|d)(i|l)
if ir(5 downto 3) = "000" then
state <= state_fpiwr;
else
state <= state_fpiww;
end if;
when "1100" => -- stc(f|d)(d|f)
fbus_fd <= '1'; -- enable full access to fp register bank
if ir(5 downto 3) = "000" then
state <= state_fpd0;
else
state <= state_fpww;
end if;
when "1111" => -- ldc(d|f)(f|d)
fbus_fd <= '1'; -- enable full access to fp register bank
state <= state_fpwr;
when others =>
state <= state_fpwr;
end case;
end if;
when state_tstset =>
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= alu_input;
rbus_we <= '1';
state <= state_store_alu_p;
when state_wrtlck =>
rbus_ix <= "000";
state <= state_wrtlcka;
when state_wrtlcka =>
alu_input <= rbus_data;
state <= state_store_alu_p;
when state_mark =>
r7 <= rbus_data;
rbus_ix <= "110";
state <= state_marka;
when state_marka =>
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
state <= state_markb;
when state_markb =>
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "101";
rbus_d <= datain;
rbus_we <= '1';
state <= state_ifetch;
when state_jsr =>
rbus_ix <= "110";
state <= state_jsra;
when state_jsra =>
addr_indirect <= rbus_data_m2;
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
sr1_srcd <= sr1_m2;
rbus_ix <= ir(8 downto 6);
state <= state_jsrb;
when state_jsrb =>
state <= state_jsrc;
when state_jsrc =>
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= r7;
rbus_we <= '1';
end if;
r7 <= dest_addr;
state <= state_ifetch;
when state_rts =>
addr_indirect <= rbus_data;
if ir(2 downto 0) /= "110" then -- the r6 special case; it is not really necessary to increment sp here, since it will be loaded in the next step. Does not harm either.
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
-- sr1_dstd <= sr1_p2; -- simh doesn't
end if;
rbus_ix <= ir(2 downto 0);
state <= state_rtsa;
when state_rtsa =>
if ir(2 downto 0) /= "111" then
r7 <= rbus_data;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= datain;
rbus_we <= '1';
else
r7 <= datain;
end if;
state <= state_ifetch;
when state_dst0 =>
alu_input <= rbus_data;
state <= pdststate;
rbus_cpu_mode <= pswmf(15 downto 14); -- may have been set temporarily to handle mode 0 r6 for mfp(i|d)
when state_src0 =>
-- handle issue 3 in programming differences list
if ir_dop = '1' and ir(8 downto 6) = "111"
and (ir(5 downto 4) = "11")
and (
modelcode = 15 or modelcode = 20 or modelcode = 35 or modelcode = 40
or modelcode = 53
or modelcode = 73 or modelcode = 83 or modelcode = 84 or modelcode = 93 or modelcode = 94
)
then
alus_input <= rbus_data_p2;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
else
alus_input <= rbus_data;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
end if;
when state_dst1 =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
when state_src1 =>
alus_input <= datain;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
when state_dst2 =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
sr1_dstd <= sr1_pv;
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= rbus_data_pv;
rbus_we <= '1';
else
r7 <= rbus_data_p2;
end if;
when state_src2 =>
alus_input <= datain;
if ir_dop = '1' and ir(8 downto 6) = ir(2 downto 0) and ir(2 downto 0) /= "111" then
state <= state_src2w;
else
state <= psrcstate;
end if;
rbus_ix <= ir(2 downto 0);
sr1_srcd <= sr1_pv;
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_pv;
rbus_we <= '1';
else
r7 <= rbus_data_p2;
end if;
when state_src2w =>
state <= psrcstate;
when state_dst3 =>
addr_indirect <= datain;
sr1_dstd <= sr1_p2;
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= rbus_data_p2;
rbus_we <= '1';
else
r7 <= rbus_data_p2;
end if;
state <= state_dst3a;
when state_dst3a =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
when state_src3 =>
addr_indirect <= datain;
rbus_ix <= ir(2 downto 0);
sr1_srcd <= sr1_p2;
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_p2;
rbus_we <= '1';
else
r7 <= rbus_data_p2;
end if;
state <= state_src3a;
when state_src3a =>
alus_input <= datain;
state <= psrcstate;
when state_dst4 =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
sr1_dstd <= sr1_mv;
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= rbus_data_mv;
rbus_we <= '1';
else
r7 <= rbus_data_m2; -- FIXME, where does this even begin to make sense - it would effectively jump to the same insn?
end if;
when state_src4 =>
alus_input <= datain;
if ir_dop = '1' and ir(8 downto 6) = ir(2 downto 0) and ir(2 downto 0) /= "111" then
state <= state_src4w;
else
state <= psrcstate;
end if;
rbus_ix <= ir(2 downto 0);
sr1_srcd <= sr1_mv;
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_mv;
rbus_we <= '1';
else
r7 <= rbus_data_m2;
end if;
when state_src4w =>
state <= psrcstate;
when state_dst5 =>
addr_indirect <= datain;
sr1_dstd <= sr1_m2;
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= rbus_data_m2;
rbus_we <= '1';
else
r7 <= rbus_data_m2;
end if;
state <= state_dst5a;
when state_dst5a =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
when state_src5 =>
addr_indirect <= datain;
rbus_ix <= ir(2 downto 0);
sr1_srcd <= sr1_m2;
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_m2;
rbus_we <= '1';
else
r7 <= rbus_data_m2;
end if;
state <= state_src5a;
when state_src5a =>
alus_input <= datain;
state <= psrcstate;
when state_dst6 =>
r7 <= r7p2;
if ir(2 downto 0) = "111" then
addr_indirect <= unsigned(datain) + unsigned(rbus_data_p2);
else
addr_indirect <= unsigned(datain) + unsigned(rbus_data);
end if;
state <= state_dst6a;
when state_dst6a =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
when state_src6 =>
r7 <= r7p2;
if ir(8 downto 6) = "111" then
addr_indirect <= unsigned(datain) + unsigned(rbus_data_p2);
else
addr_indirect <= unsigned(datain) + unsigned(rbus_data);
end if;
state <= state_src6a;
when state_src6a =>
alus_input <= datain;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
when state_dst7 =>
r7 <= r7p2;
if ir(2 downto 0) = "111" then
addr_indirect <= unsigned(datain) + unsigned(rbus_data_p2);
else
addr_indirect <= unsigned(datain) + unsigned(rbus_data);
end if;
state <= state_dst7a;
when state_dst7a =>
addr_indirect <= datain;
state <= state_dst7b;
when state_dst7b =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
rbus_ix <= "110";
when state_src7 =>
r7 <= r7p2;
if ir(8 downto 6) = "111" then
addr_indirect <= unsigned(datain) + unsigned(rbus_data_p2);
else
addr_indirect <= unsigned(datain) + unsigned(rbus_data);
end if;
state <= state_src7a;
when state_src7a =>
addr_indirect <= datain;
state <= state_src7b;
when state_src7b =>
alus_input <= datain;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
when state_store_alu_p =>
state <= state_store_alu_w;
when state_store_alu_w =>
psw(3 downto 0) <= alu_psw;
if psw_in_we_even = '1' then -- direct write into 777776 overrides psw setting from alu
if have_pswimmediateupdate = 1 then
psw(7 downto 5) <= psw_in(7 downto 5); -- T bit can only be set with RTI/RTT instruction
psw(3 downto 0) <= psw_in(3 downto 0);
else
psw_delayedupdate_even <= '1';
psw_delayedupdate(7 downto 0) <= psw_in(7 downto 0);
end if;
end if;
if psw_in_we_odd = '1' then
if have_pswimmediateupdate = 1 then
psw(15 downto 8) <= psw_in(15 downto 8);
else
psw_delayedupdate_odd <= '1';
psw_delayedupdate(15 downto 8) <= psw_in(15 downto 8);
end if;
end if;
state <= state_ifetch;
if ir(15 downto 6) = "1111000011" then -- stst?
if ir(5 downto 0) /= "010111" then -- not if mode 2, r7 -- immediate
state <= state_stststore;
dest_addr <= dest_addr + 2;
end if;
end if;
when state_store_alu_r =>
if ir_store = '1' then
if ir(2 downto 0) /= "111" then
if ir_mtpi = '1' or ir_mtpd = '1' then
rbus_waddr <= pswmf(13 downto 12) & pswmf(11) & ir(2 downto 0);
else
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
end if;
if ir(15 downto 12) = "1001" then -- movb? movb needs to sign extend if the result is moved to a register
rbus_d <= alu_output_signext;
elsif have_mtps = 1 and ir_mfps = '1' then -- mfps needs sign extend if the result is moved to a register
rbus_d <= alu_output_signext;
elsif ir_byte = '1' then
rbus_d <= alu_input(15 downto 8) & alu_output(7 downto 0);
else
rbus_d <= alu_output;
end if;
rbus_we <= '1';
else
r7 <= alu_output;
end if;
end if;
psw(3 downto 0) <= alu_psw;
state <= state_ifetch;
when others =>
null;
end case;
end if;
if nxmabort = '1' then
if modelcode = 34 -- FIXME, if this is disabled for these models, FKAB, KKAB will fail. However, if enabled for 45, unix v7 will fail during /etc/rc processing.
or modelcode = 44
or modelcode = 04
then
if state = state_src2 or state = state_src3 then
rbus_we <= '0';
sr1_srcd <= "00000";
end if;
if state = state_dst2 or state = state_dst3 then
rbus_we <= '0';
sr1_dstd <= "00000";
end if;
end if;
trap_vector <= o"004";
state <= state_trap;
end if;
if mmuabort = '1' and have_mmuimmediateabort = 0 then -- signal from mmu that an access caused an abort.
state <= state_mmuabort; -- precursor state for mmu abort
ack_mmuabort <= '1'; -- set acknowledge flag to mmu core
elsif oddabort = '1' and have_oddimmediateabort = 0 then -- odd abort signal
trap_vector <= o"004"; -- set vector
state <= state_trap; -- do trap
end if;
end if;
end if;
end process;
-- base instruction set alu
process(alu_input, alus_input, ir, psw(3 downto 0),
ir_sop, ir_dop, ir_mfpi, ir_csm, ir_mfpd, ir_mtpi, ir_mtpd, ir_mtps, ir_mfps, ir_dopr, ir_mpr, ir_fpsop1,
have_csm, have_mfp, have_mtps, have_xor, have_mpr, fps, fec,
modelcode)
variable result : std_logic_vector(15 downto 0);
variable result8 : std_logic_vector(7 downto 0);
begin
ir_byte <= '0';
ir_store <= '1';
if ir_sop = '1' then
case ir(15 downto 6) is
when "0000000011" => -- swab
result(15 downto 8) := alu_input(7 downto 0);
result(7 downto 0) := alu_input(15 downto 8);
alu_output <= result;
alu_psw(3) <= alu_input(15);
if alu_input(15 downto 8) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if modelcode = 15 or modelcode = 20 then
alu_psw(1) <= psw(1);
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= '0';
when "0000101000" => -- clr
result := "0000000000000000";
alu_output <= result;
alu_psw(3 downto 0) <= "0100";
when "1000101000" => -- clrb
ir_byte <= '1';
result := "0000000000000000";
alu_output <= result;
alu_psw(3 downto 0) <= "0100";
when "0000101001" => -- com
result := not alu_input;
alu_output <= result;
alu_psw(3) <= not alu_input(15);
if not alu_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1 downto 0) <= "01";
when "1000101001" => -- comb
ir_byte <= '1';
result := not alu_input;
alu_output <= result;
alu_psw(3) <= not alu_input(7);
if not alu_input(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1 downto 0) <= "01";
when "0000101010" => -- inc
result := alu_input + 1;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input = "0111111111111111" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= psw(0);
when "1000101010" => -- incb
ir_byte <= '1';
result := alu_input + 1;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input(7 downto 0) = "01111111" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= psw(0);
when "0000101011" => -- dec
result := alu_input - 1;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input = "1000000000000000" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= psw(0);
when "1000101011" => -- decb
ir_byte <= '1';
result := alu_input - 1;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input(7 downto 0) = "10000000" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= psw(0);
when "0000101100" => -- neg
result := (not alu_input) + 1;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
alu_psw(0) <= '0';
else
alu_psw(2) <= '0';
alu_psw(0) <= '1';
end if;
if result = "1000000000000000" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
when "1000101100" => -- negb
ir_byte <= '1';
result := (not alu_input) + 1;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
alu_psw(0) <= '0';
else
alu_psw(2) <= '0';
alu_psw(0) <= '1';
end if;
if result(7 downto 0) = "10000000" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
when "0000101101" => -- adc
result := alu_input + psw(0);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input = "0111111111111111" and psw(0) = '1' then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
if alu_input = "1111111111111111" and psw(0) = '1' then
alu_psw(0) <= '1';
else
alu_psw(0) <= '0';
end if;
when "1000101101" => -- adcb
ir_byte <= '1';
result := alu_input + psw(0);
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input(7 downto 0) = "01111111" and psw(0) = '1' then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
if alu_input(7 downto 0) = "11111111" and psw(0) = '1' then
alu_psw(0) <= '1';
else
alu_psw(0) <= '0';
end if;
when "0000101110" => -- sbc
result := alu_input - psw(0);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input = "1000000000000000" and psw(0) = '1' then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
if alu_input = "0000000000000000" and psw(0) = '1' then
alu_psw(0) <= '1';
else
alu_psw(0) <= '0';
end if;
when "1000101110" => -- sbcb
ir_byte <= '1';
result := alu_input - psw(0);
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input(7 downto 0) = "10000000" and psw(0) = '1' then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
if alu_input(7 downto 0) = "00000000" and psw(0) = '1' then
alu_psw(0) <= '1';
else
alu_psw(0) <= '0';
end if;
when "0000101111" => -- tst
result := alu_input;
alu_output <= result;
ir_store <= '0';
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1 downto 0) <= "00";
when "1000101111" => -- tstb
ir_byte <= '1';
result := alu_input;
alu_output <= result;
ir_store <= '0';
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1 downto 0) <= "00";
when "0000110000" => -- ror
result := psw(0) & alu_input(15 downto 1);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(0) xor result(15);
alu_psw(0) <= alu_input(0);
when "1000110000" => -- rorb
ir_byte <= '1';
result8 := psw(0) & alu_input(7 downto 1);
alu_output(7 downto 0) <= result8;
alu_output(15 downto 8) <= "XXXXXXXX";
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(0) xor result8(7);
alu_psw(0) <= alu_input(0);
when "0000110001" => -- rol
result := alu_input(14 downto 0) & psw(0);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(15) xor result(15);
alu_psw(0) <= alu_input(15);
when "1000110001" => -- rolb
ir_byte <= '1';
result8 := alu_input(6 downto 0) & psw(0);
alu_output(7 downto 0) <= result8;
alu_output(15 downto 8) <= "XXXXXXXX";
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(7) xor result8(7);
alu_psw(0) <= alu_input(7);
when "0000110010" => -- asr
result := alu_input(15) & alu_input(15 downto 1);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(0) xor result(15);
alu_psw(0) <= alu_input(0);
when "1000110010" => -- asrb
ir_byte <= '1';
result8 := alu_input(7) & alu_input(7 downto 1);
alu_output(7 downto 0) <= result8;
alu_output(15 downto 8) <= "XXXXXXXX";
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(0) xor result8(7);
alu_psw(0) <= alu_input(0);
when "0000110011" => -- asl
result := alu_input(14 downto 0) & '0';
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(15) xor result(15);
alu_psw(0) <= alu_input(15);
when "1000110011" => -- aslb
ir_byte <= '1';
result8 := alu_input(6 downto 0) & '0';
alu_output(7 downto 0) <= result8;
alu_output(15 downto 8) <= "XXXXXXXX";
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(7) xor result8(7);
alu_psw(0) <= alu_input(7);
when "0000110111" => -- sxt
if psw(3) = '0' then
result := "0000000000000000";
alu_psw(2) <= '1';
else
result := "1111111111111111";
alu_psw(2) <= '0';
end if;
alu_output <= result;
alu_psw(3) <= psw(3);
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when others =>
alu_output <= "XXXXXXXXXXXXXXXX";
alu_psw <= "XXXX";
end case;
elsif ir_dop = '1' then
case ir(15 downto 12) is
when "0001" => -- mov
result := alus_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "1001" => -- movb
ir_byte <= '1';
result := alus_input;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "0010" => -- cmp
result := alus_input - alu_input;
alu_output <= alu_input;
ir_store <= '0';
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if (alu_input(15) /= alus_input(15)) and (alus_input(15) /= result(15)) then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= ((not alus_input(15)) and alu_input(15)) or ((not alus_input(15)) and result(15)) or (alu_input(15) and result(15));
when "1010" => -- cmpb
ir_byte <= '1';
result8 := alus_input(7 downto 0) - alu_input(7 downto 0);
alu_output <= alu_input;
ir_store <= '0';
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if (alu_input(7) /= alus_input(7)) and (alus_input(7) /= result8(7)) then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= ((not alus_input(7)) and alu_input(7)) or ((not alus_input(7)) and result8(7)) or (alu_input(7) and result8(7));
when "0011" => -- bit
result := alus_input and alu_input;
alu_output <= alu_input;
ir_store <= '0';
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "1011" => -- bitb
ir_byte <= '1';
result := alus_input and alu_input;
alu_output <= alu_input;
ir_store <= '0';
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "0100" => -- bic
result := (not alus_input) and alu_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "1100" => -- bicb
ir_byte <= '1';
result := (not alus_input) and alu_input;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "0101" => -- bis
result := alus_input or alu_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "1101" => -- bisb
ir_byte <= '1';
result := alus_input or alu_input;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "0110" => -- add
result := alu_input + alus_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if (alu_input(15) = alus_input(15)) and (alus_input(15) /= result(15)) then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= (alu_input(15) and alus_input(15)) or (alu_input(15) and not result(15)) or (alus_input(15) and not result(15));
when "1110" => -- sub
result := alu_input - alus_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if (alu_input(15) /= alus_input(15)) and (alu_input(15) /= result(15)) then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= ((not alu_input(15)) and alus_input(15)) or ((not alu_input(15)) and result(15)) or (alus_input(15) and result(15));
when others =>
alu_output <= "XXXXXXXXXXXXXXXX";
alu_psw <= "XXXX";
end case;
-- misc insns
elsif have_csm = 1 and ir_csm = '1' then -- csm
alu_output <= alu_input;
alu_psw <= psw(3 downto 0);
elsif have_mfp = 1 and (ir_mfpi = '1' or ir_mfpd = '1') then -- mfpi, mfpd, mtpi, mtpd
alu_output <= alu_input;
alu_psw(3) <= alu_input(15);
if alu_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
elsif have_mfp = 1 and (ir_mtpi = '1' or ir_mtpd = '1') then -- mfpi, mfpd, mtpi, mtpd
alu_output <= alus_input;
alu_psw(3) <= alus_input(15);
if alus_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
elsif have_mtps = 1 and ir_mtps = '1' then -- mtps
ir_byte <= '1';
alu_output <= alu_input;
alu_psw <= psw(3 downto 0);
elsif have_mtps = 1 and ir_mfps = '1' then -- mfps
ir_byte <= '1';
alu_output <= psw;
alu_psw(3) <= psw(7);
if psw(7 downto 0) = "0000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
elsif have_xor = 1 and ir_dopr = '1' and ir(11 downto 9) = "100" then -- xor
result := alu_input xor alus_input; -- xor is handled here, not in the eis alu
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
elsif have_mpr = 1 and ir_mpr = '1' then
case ir(6) is
when '0' => -- tstset
result := alu_input(15 downto 1) & '1';
alu_output <= result;
alu_psw(3) <= alu_input(15);
if alu_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= alu_input(0);
when '1' => -- wrtlck
result := alu_input;
alu_output <= result;
alu_psw(3) <= alu_input(15);
if alu_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when others =>
null;
end case;
-- fp11 insns with simple integer result
elsif ir_fpsop1 = '1' then
alu_psw(3 downto 0) <= psw(3 downto 0);
case ir(7 downto 6) is
when "01" => -- ldfps
result := alu_input;
alu_output <= result;
when "10" => -- stfps
result(15 downto 14) := fps(15 downto 14);
result(13 downto 12) := "00"; -- set these unused bits to zero to stop the tests complaining
result(11 downto 0) := fps(11 downto 0);
alu_output <= result;
when "11" => -- stst
result := "000000000000" & fec;
alu_output <= result;
when others =>
alu_output <= "XXXXXXXXXXXXXXXX";
alu_psw <= "XXXX";
end case;
else
alu_output <= "XXXXXXXXXXXXXXXX";
alu_psw <= "XXXX";
end if;
end process;
--
-- eis alu: mul, div, ash, ashc insns
--
process(clk)
begin
if clk = '1' and clk'event then
if have_eis = 1 and ir_dopr = '1' and ir(11) = '0' then
case ir(10 downto 9) is
when "00" => -- mul
if eis_sequencer = "11111" then -- load seq. code
eis_temp1 <= signed(alu_input) * signed(alus_input); -- mul is easy, just use the hw multipliers
elsif eis_sequencer = "00000" then -- done seq. code
eis_output <= eis_temp1(31 downto 16); -- high part
eis_output32 <= eis_temp1(15 downto 0); -- low part
eis_psw(3) <= eis_temp1(31); -- set n
if eis_temp1 = "00000000000000000000000000000000" then -- set z
eis_psw(2) <= '1';
else
eis_psw(2) <= '0';
end if;
eis_psw(1) <= '0'; -- set v - always 0, 15bits*15bits into 31 cannot overflow
if (eis_temp1(31) = '1' and eis_temp1(30 downto 15) /= "1111111111111111")
or (eis_temp1(31) = '0' and eis_temp1(30 downto 15) /= "0000000000000000") then
eis_psw(0) <= '1';
else
eis_psw(0) <= '0';
end if;
end if;
when "01" => -- div
if eis_sequencer = "10000" then -- load seq. code
if alu_input(15) = '1' then -- if input negative
eis_temp1 <= '0' & ((not alu_input) + 1) & (14 downto 0 => '0'); -- take two's complement
eis_flag1 <= '1';
else
eis_temp1 <= '0' & alu_input & (14 downto 0 => '0');
eis_flag1 <= '0';
end if;
if alus_input(15) = '1' then
eis_temp2 <= (not (alus_input & alut_input)) + 1;
eis_flag2 <= '1';
else
eis_temp2 <= alus_input & alut_input;
eis_flag2 <= '0';
end if;
eis_psw <= "0000";
-- main div loop
elsif eis_sequencer(4) = '0' then
if unsigned(eis_temp1) <= unsigned(eis_temp2) then
if eis_sequencer(3 downto 0) = "1111" then
if unsigned(eis_temp1) <= unsigned(eis_temp2) then
eis_psw(1) <= '1';
end if;
end if;
eis_temp(conv_integer(eis_sequencer(3 downto 0))) <= '1';
eis_temp2 <= eis_temp2 - eis_temp1;
else
eis_temp(conv_integer(eis_sequencer(3 downto 0))) <= '0';
end if;
eis_temp1(30 downto 0) <= eis_temp1(31 downto 1);
else
-- post processing
-- setting the flags after the div instruction is the tricky part. A division by zero causes
-- the result not to be stored - which is handled by the state machine, results are only
-- stored if the v and c flags are 00. Still a very tricky thing considering all the
-- border cases. I believe the current model is correct - and also, it passes all the tests
-- I can find. Specifically, fkac, and zkdj - and the results make sense as well.
if eis_flag2 = '1' then -- if 2nd op was negative
eis_output32 <= (not eis_temp2(15 downto 0)) + 1; -- sign adjust remainder
else
eis_output32 <= eis_temp2(15 downto 0); -- or just the positive
end if;
if eis_flag1 /= eis_flag2 then -- if signs were different
eis_psw(3) <= '1'; -- set N
eis_output <= (not eis_temp) + 1; -- sign adjust result
else
eis_psw(3) <= '0'; -- clear n
eis_output <= eis_temp; -- copy result
end if;
-- special cases : result is zero
if eis_temp(14 downto 0) = (14 downto 0 => '0') then
if eis_temp(15) = '0' then
eis_psw(3) <= '0';
eis_psw(2) <= '1';
eis_output(15) <= '0';
else
eis_psw(2) <= '0';
end if;
if eis_temp(15) = '1' and eis_flag1 /= eis_flag2 then
eis_psw(1) <= '0'; -- special case: quotient is negative maxint - that isn't an overflow
end if;
else
eis_psw(2) <= '0';
end if;
-- set c and v if divisor was zero
if alu_input = (15 downto 0 => '0') then
if modelcode = 73 or modelcode = 83 or modelcode = 84 or modelcode = 93 or modelcode = 94 or modelcode = 53 then
eis_psw(2) <= psw(2); -- observed behaviour and needed to pass zkdj FIXME
end if;
eis_psw(1) <= '1';
eis_psw(0) <= '1';
end if;
end if;
when "10" => -- ash
if eis_sequencer = "11111" then
eis_output <= alus_input;
eis_flag2 <= '0';
eis_psw(1) <= '0';
eis_psw(0) <= '0';
eis_temp(15 downto 6) <= "0000000000"; -- for easier debugging
eis_flag1 <= alu_input(5);
if alu_input(4 downto 0) = "11111" then -- see EK-1184E-TM-001_Dec87.pdf, page B-17
if modelcode = 73
or modelcode = 53
or modelcode = 83
or modelcode = 84
or modelcode = 93
or modelcode = 94
then
if have_fpa = 0 then -- Speculative - see ashc case
eis_flag1 <= '1';
end if;
end if;
end if;
if alu_input(5) = '1' then
eis_temp(5 downto 0) <= (not alu_input(5 downto 0)) + 1;
else
eis_temp(5 downto 0) <= alu_input(5 downto 0);
end if;
else
if eis_temp(5 downto 0) /= "000000" then
if eis_flag1 = '1' then
eis_output <= eis_output(15) & eis_output(15 downto 1);
eis_psw(0) <= eis_output(0);
else
eis_output <= eis_output(14 downto 0) & '0';
if eis_output(15 downto 14) = "10" or eis_output(15 downto 14) = "01" then
eis_psw(1) <= '1';
end if;
eis_psw(0) <= eis_output(15);
end if;
eis_temp(5 downto 0) <= eis_temp(5 downto 0) - 1;
else
eis_flag2 <= '1';
eis_psw(3) <= eis_output(15);
if eis_output = "0000000000000000" then
eis_psw(2) <= '1';
else
eis_psw(2) <= '0';
end if;
end if;
end if;
when "11" => -- ashc
if eis_sequencer = "11111" then
eis_temp1 <= alus_input & alut_input;
eis_flag2 <= '0';
eis_psw(1) <= '0';
eis_psw(0) <= '0';
eis_temp(15 downto 6) <= "0000000000"; -- for easier debugging
eis_flag1 <= alu_input(5);
if alu_input(4 downto 0) = "11111" then -- see EK-1184E-TM-001_Dec87.pdf, page B-17
if modelcode = 73
or modelcode = 53
or modelcode = 83
or modelcode = 84
or modelcode = 93
or modelcode = 94
then
if have_fpa = 0 then -- As evidenced from the test code in RSTS V10.1L
eis_flag1 <= '1';
end if;
end if;
end if;
if alu_input(5) = '1' then
eis_temp(5 downto 0) <= ('0' & (not alu_input(4 downto 0))) + 1;
else
eis_temp(4 downto 0) <= alu_input(4 downto 0);
eis_temp(5) <= '0';
end if;
else
if eis_temp(5 downto 0) /= "000000" then
if eis_flag1 = '1' then
eis_temp1 <= eis_temp1(31) & eis_temp1(31 downto 1);
eis_psw(0) <= eis_temp1(0);
else
eis_temp1 <= eis_temp1(30 downto 0) & '0';
if eis_temp1(31 downto 30) = "10" or eis_temp1(31 downto 30) = "01" then
eis_psw(1) <= '1';
end if;
eis_psw(0) <= eis_temp1(31);
end if;
eis_temp(5 downto 0) <= eis_temp(5 downto 0) - 1;
else
eis_flag2 <= '1';
eis_output <= eis_temp1(31 downto 16);
eis_output32 <= eis_temp1(15 downto 0);
eis_psw(3) <= eis_temp1(31);
if eis_temp1 = "00000000000000000000000000000000" then
eis_psw(2) <= '1';
else
eis_psw(2) <= '0';
end if;
end if;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-- floating point alu
process(clk, reset, falu_pending_clear, ir_fpao, falu_load, falu_input, falus_input, ir_wait)
variable v_caseworkaround : std_logic_vector(3 downto 0);
begin
if clk = '1' and clk'event then
if have_fpu = 1 and reset = '1' then
falu_done <= '0';
falu_fsm <= falu_idle;
falu_fps <= "0000";
falu_flag1 <= '0';
falu_pending_fiu <= '0';
falu_pending_fiv <= '0';
falu_pending_fic <= '0';
falu_pending_divz <= '0';
elsif have_fpu = 1 and ir_wait = '0' then
if falu_pending_clear = '1' then
falu_pending_fiu <= '0';
falu_pending_fiv <= '0';
falu_pending_fic <= '0';
falu_pending_divz <= '0';
end if;
if ir_fpao = '1' then
-- if the falu_load bit is one, load the work registers and the initial state for the falu state machine.
-- both of which are dependent on exactly which instruction we need to process - the sequence in the
-- state machine needs to be started at a specific point, which is not the same for all insn - and
-- definitely all insn have their own initialization requirements and special cases.
--
-- also, the main cpu state machine includes
if falu_load = '1' then
falu_done <= '0';
falu_fps <= "0000";
case ir(11 downto 8) is
when "0010" | "0011" => -- mul(f|d), mod(f|d)
if falu_input(63) = falus_input(63) then -- set sign - positive if both operands are same sign, negative otherwise
falu_fps(3) <= '0';
else
falu_fps(3) <= '1';
end if;
falu_fps(2 downto 0) <= "000"; -- set default for fps bits
falu_fsm <= falu_mult;
falu_work1 <= (others => '0');
falu_work2 <= '0' & '1' & falus_input(54 downto 0) & '0' & '0';
if falu_input(62 downto 55) = "00000000" or falus_input(62 downto 55) = "00000000" then -- if either input exponent is zero, we don't need to multiply at all
falu_output <= (others => '0');
falu_output2 <= (others => '0');
falu_fps <= "0100";
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
falu_ccw <= ("00" & falu_input(62 downto 55)) + ("00" & falus_input(62 downto 55)) - "0010000001";
when "0100" | "0110" => -- add(f|d), sub(f|d)
falu_fsm <= falu_align;
falu_work1 <= '0' & '1' & falu_input(54 downto 0) & '0' & '0';
falu_work2 <= '0' & '1' & falus_input(54 downto 0) & '0' & '0';
falu_fps(3 downto 0) <= "0000"; -- set default for fps bits
if falu_input(62 downto 55) = "00000000" then -- if the primary input exponent is zero, we don't need to add (or subtract) at all
falu_output <= falus_input;
falu_fps(3) <= falus_input(63);
if falus_input(62 downto 55) = "00000000" then
falu_fps(2) <= '1';
else
falu_fps(2) <= '0';
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
elsif falus_input(62 downto 55) = "00000000" then -- if the secondary input exponent is zero, we don't need to add (or subtract) at all
falu_output(62 downto 0) <= falu_input(62 downto 0);
if ir(9) = '0' then
falu_fps(3) <= falu_input(63);
falu_output(63) <= falu_input(63);
else
falu_fps(3) <= not falu_input(63);
falu_output(63) <= not falu_input(63);
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
elsif unsigned(falu_input(62 downto 55)) < unsigned(falus_input(62 downto 55)) then
falu_ccw <= "00" & (unsigned(falus_input(62 downto 55)) - unsigned(falu_input(62 downto 55)));
falu_flag1 <= '1';
elsif unsigned(falu_input(62 downto 55)) = unsigned(falus_input(62 downto 55)) then
falu_ccw <= (others => '0');
if unsigned(falu_input(54 downto 0)) < unsigned(falus_input(54 downto 0)) then
falu_flag1 <= '1';
else
falu_flag1 <= '0';
end if;
else
falu_ccw <= "00" & (unsigned(falu_input(62 downto 55)) - unsigned(falus_input(62 downto 55)));
falu_flag1 <= '0';
end if;
when "0101" => -- ld(f|d)
falu_output <= falu_input;
falu_fps(3) <= falu_input(63);
if falu_input(62 downto 55) = "00000000" then
falu_fps(2) <= '1';
else
falu_fps(2) <= '0';
end if;
falu_fps(1 downto 0) <= "00"; -- set default for fps bits
falu_fsm <= falu_idle;
falu_done <= '1';
when "0111" => -- cmp(f|d)
falu_output <= falus_input;
falu_fps(3 downto 0) <= "0000"; -- set default for fps bits
if falu_input(63) = '1' and falus_input(63) = '0' then
falu_fps(3) <= '1';
elsif falu_input(63) = '0' and falus_input(63) = '0' then
if unsigned(falu_input(62 downto 55)) < unsigned(falus_input(62 downto 55)) then
falu_fps(3) <= '1';
elsif unsigned(falu_input(62 downto 55)) = unsigned(falus_input(62 downto 55)) then
if unsigned(falu_input(54 downto 0)) < unsigned(falus_input(54 downto 0)) then
falu_fps(3) <= '1';
elsif unsigned(falu_input(54 downto 0)) = unsigned(falus_input(54 downto 0)) then
falu_fps(2) <= '1';
else
-- n=0, z=0
end if;
else
-- n=0, z=0
end if;
elsif falu_input(63) = '1' and falus_input(63) = '1' then
if unsigned(falus_input(62 downto 55)) < unsigned(falu_input(62 downto 55)) then
falu_fps(3) <= '1';
elsif unsigned(falus_input(62 downto 55)) = unsigned(falu_input(62 downto 55)) then
if unsigned(falus_input(54 downto 0)) < unsigned(falu_input(54 downto 0)) then
falu_fps(3) <= '1';
elsif unsigned(falus_input(54 downto 0)) = unsigned(falu_input(54 downto 0)) then
falu_fps(2) <= '1';
else
-- n=0, z=0
end if;
else
-- n=0, z=0
end if;
end if;
if falu_input(62 downto 55) = "00000000" and falus_input(62 downto 55) = "00000000" then
falu_fps <= "0100";
falu_output <= (others => '0');
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
when "1000" => -- st(f|d)
falu_output <= falu_input;
falu_fps <= fps(3 downto 0);
falu_fsm <= falu_idle;
falu_done <= '1';
when "1001" => -- div(f|d)
if falu_input(63) = falus_input(63) then -- set sign - positive if both operands are same sign, negative otherwise
falu_fps(3) <= '0';
else
falu_fps(3) <= '1';
end if;
falu_fps(2 downto 0) <= "000"; -- set default for other fps bits
falu_fsm <= falu_div;
falu_work1 <= (others => '0');
falu_work2 <= '0' & '1' & falus_input(54 downto 0) & '0' & '0';
if falus_input(62 downto 55) = "00000000" then -- check ac operand first, then if fsrc is zero, those settings will take precedence over these
falu_output <= (others => '0');
falu_fps <= "0100";
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
if falu_input(62 downto 55) = "00000000" then
falu_pending_divz <= '1';
falu_output <= falus_input;
falu_fps <= fps(3 downto 0); -- the doc is unspecific... but xxdp jfpa seems to expect no updates to fps
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
falu_ccw <= "0000111010";
when "1010" => -- stexp
falu_output(55 downto 48) <= falu_input(62 downto 55) - "10000000";
if unsigned(falu_input(62 downto 55)) < unsigned'("10000000") then
falu_fps(3) <= '1';
falu_output(63 downto 56) <= (others => '1');
else
falu_fps(3) <= '0';
falu_output(63 downto 56) <= (others => '0');
end if;
if falu_input(62 downto 55) = "10000000" then
falu_fps(2) <= '1';
else
falu_fps(2) <= '0';
end if;
falu_fps(1) <= '0';
falu_fps(0) <= '0';
falu_fsm <= falu_idle;
falu_done <= '1';
when "1011" => -- stc(f|d)(i|l)
falu_fsm <= falu_shift;
falu_fps(3) <= falu_input(63); -- n is set from input
falu_fps(2 downto 0) <= "000"; -- set default for other fps bits
falu_work1 <= (others => '0'); -- the idea to use work1 here is that synthesis may reuse the shifter we already have for it
if fps(6) = '0' then -- if short integer mode
falu_work1(58 downto 43) <= '1' & falu_input(54 downto 40);
falu_ccw <= unsigned'("0010010000") - unsigned("00" & falu_input(62 downto 55)); -- exponent minus the bias
else
if fps(7) = '0' then -- if in long integer mode, we need to check if we're in float mode, because then we can only copy 23 bits of fraction
falu_work1(58 downto 35) <= '1' & falu_input(54 downto 32);
else
falu_work1(58 downto 26) <= '1' & falu_input(54 downto 23);
end if;
if ir(5 downto 3) = "000" or ir(5 downto 0) = "010111" then -- reg or mode 2, reg 7
falu_ccw <= unsigned'("0010010000") - unsigned("00" & falu_input(62 downto 55)); -- exponent minus the bias
else
falu_ccw <= unsigned'("0010100000") - unsigned("00" & falu_input(62 downto 55)); -- exponent minus the bias
end if;
end if;
if unsigned(falu_input(62 downto 55)) < unsigned'("10000001") then -- it is not entirely clear in the manuals, but if the input is less than 1, the output is zero, and only the Z flag is set. It is not a conversion error!
falu_output <= (others => '0');
falu_fps(3) <= '0';
falu_fps(2) <= '1';
falu_fps(1) <= '0';
falu_fps(0) <= '0';
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
when "1100" | "1111" => -- stc(f|d)(d|f), ldc(d|f)(f|d)
falu_fps(3) <= falu_input(63); -- n bit is in most cases a direct copy of the input
falu_output(63 downto 55) <= falu_input(63 downto 55); -- right in most cases
falu_fps(2 downto 0) <= "000"; -- set default for other fps bits
if falu_input(62 downto 55) = "00000000" then -- if the input exponent is zero, then the z bit in fps must be set
falu_fps(2) <= '1';
falu_fps(3) <= '0'; -- negative zero exp is ignored
falu_output <= (others => '0');
else
falu_fps(2) <= '0';
if (fps(7) = '0' and ir(11 downto 8) = "1100") or (fps(7) = '1' and ir(11 downto 8) = "1111") then -- convert to a double, or to a float?
falu_output(54 downto 32) <= falu_input(54 downto 32); -- just copy the high part if converting f to d
falu_output(31 downto 0) <= "00000000000000000000000000000000"; -- and set the low part to zeroes
else
if fps(5) = '1' then -- on d to f conversion, if round/trunc is trunc
falu_output(54 downto 32) <= falu_input(54 downto 32); -- just copy the high part
falu_output(31 downto 0) <= "00000000000000000000000000000000"; -- and set the low part to zeroes
else
if falu_input(62 downto 31) = "11111111111111111111111111111111" then -- this bit pattern causes overflow to occur
falu_output(62 downto 32) <= "0000000000000000000000000000000"; -- result after overflow is zeroes
falu_fps(2) <= '1'; -- set z bit, because of zeroes we just set!
falu_fps(1) <= '1'; -- set v bit to signal overflow
if fps(9) = '1' then -- if fiv enabled
falu_pending_fiv <= '1'; -- then signal the pending interrupt
end if;
else
falu_output(62 downto 31) <= falu_input(62 downto 31) + "1"; -- normal case, round bit added. Note that I count on normal arithmetic to handle increasing the exponent, if that is necessary to handle an overflow of the fraction part
end if;
falu_output(31 downto 0) <= "00000000000000000000000000000000"; -- in all cases, the low part is cleared
end if;
end if;
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
when "1101" => -- ldexp
falu_output(63) <= falu_input(63); -- setup sign, in all cases a copy of the input
falu_output(54 downto 0) <= falu_input(54 downto 0); -- fraction is in all cases same as input
falu_fps(3) <= falu_input(63); -- setup n bit
falu_fps(2 downto 0) <= "000"; -- set default for other fps bits
if falus_input(55) = '1' then -- sign bit on, ie. is this a negative 2-complement integer
if falus_input(54 downto 47) = "11111111" -- if yes, then the next 8 bits need to be ones too, else it is an overflow
and falus_input(47 downto 40) /= "10000000" then -- would produce an overflow as well - special case
falu_output(62 downto 55) <= falus_input(47 downto 40) + "10000000"; -- not an overflow --> assign the new exponent, biased w. 200 oct
else
if fps(10) = '1' then -- if fiu enabled
falu_output(62 downto 55) <= falus_input(47 downto 40) + "10000000";
if falus_input(47 downto 40) + "10000000" = "00000000" then
falu_fps(2) <= '1';
end if;
falu_pending_fiu <= '1';
else
falu_output <= (others => '0'); -- if fiu disabled, just set the output to zeroes
falu_fps(2) <= '1'; -- and dont forget to set the z bit either
falu_fps(3) <= '0'; -- and also dont forget zero is not negative
end if;
end if;
else -- positive exponent
if falus_input(54 downto 47) = "00000000" then -- for a positive exponent, the high 8 bits must be clear, otherwise it is an overflow
falu_output(62 downto 55) <= falus_input(47 downto 40) + "10000000"; -- not overflow - assign new exponent biased w. 200 oct
else
falu_fps(1) <= '1'; -- v bit is set only when exponent > 177
if fps(9) = '1' then -- if fiv is enabled
falu_output(62 downto 55) <= falus_input(47 downto 40) + "10000000";
if falus_input(47 downto 40) + "10000000" = "00000000" then
falu_fps(2) <= '1';
end if;
falu_pending_fiv <= '1';
else -- if fiv is disabled
falu_output <= (others => '0'); -- set the output to all zeroes
falu_fps(2) <= '1'; -- set z bit as well
falu_fps(3) <= '0';
end if;
end if;
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
when "1110" => -- ldc(i|l)(f|d)
falu_fsm <= falu_norm;
falu_fps(2 downto 0) <= "000"; -- set default for fps bits
if fps(6) = '0'
or ir(5 downto 3) = "000"
or ir(5 downto 0) = "010111" -- mode 2, reg 7 only
then
if fps(6) = '1' then -- if fl is set ie long mode, mode must be 0 or mode 2, reg 7, and the strange exception to use the single 16bit word as the upper applies.
falu_ccw <= "0010011111"; -- 37(8) or 31(10), max number of shifts for long mode; special case
else
falu_ccw <= "0010001111"; -- 17(8) or 15(10), max number of shifts for integer mode
end if;
falu_work1 <= (others => '0');
if falu_input(39) = '1' then
falu_fps(3) <= '1';
falu_work1(58 downto 43) <= (not falu_input(39 downto 24)) + 1;
else
falu_fps(3) <= '0';
falu_work1(58 downto 43) <= falu_input(39 downto 24);
end if;
else
falu_ccw <= "0010011111"; -- 37(8) or 31(10), max number of shifts for long mode
falu_work1 <= (others => '0');
if falu_input(55) = '1' then
falu_fps(3) <= '1';
falu_work1(58 downto 27) <= (not falu_input(55 downto 24)) + 1;
else
falu_fps(3) <= '0';
falu_work1(58 downto 27) <= falu_input(55 downto 24);
end if;
end if;
when others =>
null;
end case;
else
case falu_fsm is
-- multiply, ie. shifting and adding
-- this does not deal with the fd bit - all mult operations are full precision, regardless of the bit. The core
-- would be significantly faster for single prec if we would deal with the fd bit. FIXME!
when falu_mult =>
if falu_work2(57 downto 2) /= "00000000000000000000000000000000000000000000000000000000" then
if falu_work2(2) = '1' then -- if lowest order bit is a one
falu_work1 <= ('0' & falu_work1(58 downto 1) + ('0' & '1' & falu_input(54 downto 0) & "00")); -- then shift right and add
else
falu_work1 <= '0' & falu_work1(58 downto 1); -- if not set, then only shift right
end if;
falu_work2 <= '0' & falu_work2(58 downto 1); -- shift right for next round
else
falu_fsm <= falu_norm; -- if all bits done, then go into normalize state
end if;
-- align the operands for addition or subtraction
-- flag1 has which one of the operands needs to be shifted - and also, check the fd bit to see what the maximum value of the shift should be
-- falu_ccw has the difference - if it is 0, or shift- and decrement to 0, the addition/subtraction state is next up
when falu_align =>
if falu_ccw /= "0000000000" then
if falu_flag1 = '1' then
falu_work1 <= '0' & falu_work1(58 downto 1);
else
falu_work2 <= '0' & falu_work2(58 downto 1);
end if;
if fps(7) = '1' and unsigned(falu_ccw) > unsigned'("0000111001") then -- > 57 ??
falu_ccw <= "0000000000";
if falu_flag1 = '1' then
falu_work1 <= (others => '0');
else
falu_work2 <= (others => '0');
end if;
falu_fsm <= falu_addsub;
elsif fps(7) = '0' and unsigned(falu_ccw) > unsigned'("0000011001") then -- > 25 ??
falu_ccw <= "0000000000";
if falu_flag1 = '1' then
falu_work1 <= (others => '0');
else
falu_work2 <= (others => '0');
end if;
falu_fsm <= falu_addsub;
else
falu_ccw <= falu_ccw - 1;
end if;
else
falu_fsm <= falu_addsub;
end if;
when falu_addsub =>
-- this statement:
-- case ir(9) & falu_input(63) & falus_input(63) & falu_flag1 is
-- would be a nice and elegant way to express what I would like
-- alas, ISE cannot translate it. See:
-- AR #22098 - 8.2i XST-"ERROR:HDLParsers:818 - Cannot determine the type of the selector &"
v_caseworkaround := ir(9) & falu_input(63) & falus_input(63) & falu_flag1;
case v_caseworkaround is
when "0000" | "0001" => -- add, +|+
falu_work1 <= falu_work1 + falu_work2;
falu_fps(3) <= '0';
when "0100" => -- add, !work1<work2, -|+
falu_work1 <= falu_work1 - falu_work2;
falu_fps(3) <= '1';
when "0101" => -- add, work1<work2, -|+
falu_work1 <= falu_work2 - falu_work1;
falu_fps(3) <= '0';
when "0010" => -- add, !work1<work2, +|-
falu_work1 <= falu_work1 - falu_work2;
falu_fps(3) <= '0';
when "0011" => -- add, work1<work2, +|-
falu_work1 <= falu_work2 - falu_work1;
falu_fps(3) <= '1';
when "0110" | "0111" => -- add, -|-
falu_work1 <= falu_work1 + falu_work2;
falu_fps(3) <= '1';
when "1000" => -- sub, !work1<work2, +|+
falu_work1 <= falu_work1 - falu_work2;
falu_fps(3) <= '1';
when "1001" => -- sub, work1<work2, +|+
falu_work1 <= falu_work2 - falu_work1;
falu_fps(3) <= '0';
when "1100" | "1101" => -- sub, -|+
falu_work1 <= falu_work2 + falu_work1;
falu_fps(3) <= '0';
when "1010" | "1011" => -- sub, +|-
falu_work1 <= falu_work2 + falu_work1;
falu_fps(3) <= '1';
when "1110" => -- sub, !work1<work2, -|-
falu_work1 <= falu_work1 - falu_work2;
falu_fps(3) <= '0';
when "1111" => -- sub, work1<work2, -|-
falu_work1 <= falu_work2 - falu_work1;
falu_fps(3) <= '1';
when others =>
null;
end case;
if falu_flag1 = '1' then
falu_ccw <= "00" & falus_input(62 downto 55);
else
falu_ccw <= "00" & falu_input(62 downto 55);
end if;
falu_fsm <= falu_norm;
when falu_div =>
if unsigned(falu_work2) >= unsigned('0' & '1' & falu_input(54 downto 0) & "00") then
falu_work1 <= falu_work1(57 downto 0) & '1';
falu_work2 <= unsigned(falu_work2(57 downto 0) & '0') - unsigned('1' & falu_input(54 downto 0) & "000");
else
falu_work1 <= falu_work1(57 downto 0) & '0';
falu_work2 <= falu_work2(57 downto 0) & '0';
end if;
if falu_ccw /= "0000000000" then
falu_ccw <= falu_ccw - 1;
else
falu_fsm <= falu_norm;
falu_ccw <= unsigned("00" & falus_input(62 downto 55)) - unsigned("00" & falu_input(62 downto 55)) + unsigned'("0010000000");
end if;
when falu_shift =>
if falu_ccw /= "0000000000" then
falu_work1 <= '0' & falu_work1(58 downto 1);
falu_ccw <= falu_ccw - 1;
else
falu_output <= (others => '0');
if falu_input(63) = '1' then
falu_output(63 downto 32) <= (not falu_work1(58 downto 27)) + 1;
else
falu_output(63 downto 32) <= falu_work1(58 downto 27);
end if;
falu_fsm <= falu_shift2;
end if;
if fps(6) = '0' then
if unsigned(falu_ccw) > unsigned'("0000001111") then
falu_fsm <= falu_shifte;
end if;
else
if unsigned(falu_ccw) > unsigned'("0000011111") then
falu_fsm <= falu_shifte;
end if;
end if;
when falu_shift2 =>
if falu_output(63 downto 48) = "0000000000000000" then
if fps(6) = '0' then
falu_fps(3) <= '0';
falu_fps(2) <= '1';
else
if falu_output(47 downto 32) = "0000000000000000" then
falu_fps(3) <= '0';
falu_fps(2) <= '1';
end if;
end if;
end if;
if falu_output(63) /= falu_input(63) then
falu_fsm <= falu_shifte;
else
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
when falu_shifte =>
falu_fps(3) <= '0'; -- on error, result is not negative
falu_fps(2) <= '1';
falu_fps(1) <= '0'; -- V bit is not used
falu_fps(0) <= '1';
falu_output <= (others => '0');
if fps(8) = '1' then
falu_pending_fic <= '1';
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
when falu_norm =>
if falu_work1(58 downto 57) = "01" then -- hidden bit in the right place, overflow bit clear?
if ir(11 downto 8) = "0011" then
falu_fsm <= falu_sep;
else
falu_fsm <= falu_rt;
end if;
elsif falu_work1(58) = '1' then -- is the overflow bit set?
falu_work1 <= '0' & falu_work1(58 downto 1); -- shift right
falu_ccw <= falu_ccw + 1; -- increase exponent
if ir(11 downto 8) = "0011" then
falu_fsm <= falu_sep;
else
falu_fsm <= falu_rt;
end if;
else
-- 76543210987654321098765432109876543210987654321098765432
if falu_work1(57 downto 2) /= "00000000000000000000000000000000000000000000000000000000" then
falu_work1 <= falu_work1(57 downto 0) & '0'; -- shift left
falu_ccw <= falu_ccw - 1; -- decrease exponent
else -- coming here, we have lost all ones from the fraction; the output is zero
falu_fps(3) <= '0'; -- make sure that the n bit is cleared
falu_fsm <= falu_zres; -- result is zero
end if;
end if;
when falu_sep =>
if signed(falu_ccw) <= signed'("0010000000") then
falu_output2 <= (others => '0');
falu_fsm <= falu_rt;
elsif (signed(falu_ccw) > signed'("0010011000") and fps(7) = '0') or (signed(falu_ccw) > signed'("0010111000") and fps(7) = '1') then
falu_fsm <= falu_sep3;
else
falu_output2(63) <= falu_fps(3);
falu_output2(62 downto 55) <= falu_ccw(7 downto 0);
falu_output2(54 downto 0) <= falu_work1(56 downto 2);
falu_fsm <= falu_sep2;
falu_work2 <= (others => '0');
falu_work2(58 downto 57) <= "10";
end if;
when falu_sep2 =>
if signed(falu_ccw) > signed'("0010000000") then
falu_work1 <= falu_work1(57 downto 0) & '0'; -- shift left
falu_work2 <= '1' & falu_work2(58 downto 1); -- shift right
falu_ccw <= falu_ccw - 1;
elsif falu_work1(57) /= '1' and falu_ccw /= "0000000000" then
falu_work1 <= falu_work1(57 downto 0) & '0'; -- shift left
falu_ccw <= falu_ccw - 1;
if falu_work1(57 downto 2) = "00000000000000000000000000000000000000000000000000000000" then
falu_ccw <= "0000000000";
end if;
else
falu_output2(54 downto 0) <= falu_output2(54 downto 0) and falu_work2(56 downto 2);
falu_fsm <= falu_res;
if falu_ccw = "0000000000" then
falu_fsm <= falu_zres; -- zero result handled directly, because res would wrongly raise an underflow
end if;
end if;
when falu_sep3 =>
falu_output <= (others => '0'); -- set fraction output to zero
falu_fps(3) <= '0'; -- if the fraction is zero, so is its sign
falu_fps(2) <= '1'; -- set z for fraction
falu_output2(63) <= falu_fps(3);
falu_output2(62 downto 55) <= falu_ccw(7 downto 0);
falu_output2(54 downto 0) <= falu_work1(56 downto 2);
if falu_ccw(8) = '1' and falu_ccw(9) /= '1' then -- overflow?
falu_fps(1) <= '1'; -- set the flag
if fps(9) = '1' then -- are overflow traps enabled?
falu_pending_fiv <= '1'; -- yes, set flag
else
falu_output2 <= (others => '0');
end if;
end if;
falu_done <= '1';
falu_fsm <= falu_idle;
when falu_rt =>
if fps(5) = '0' then
if fps(7) = '0' then
-- 87654321098765432109876543 210987654321098765432109876543210
falu_work1 <= (unsigned(falu_work1(58 downto 33)) + unsigned'("00000000000000000000000001")) & "000000000000000000000000000000000";
else
falu_work1 <= falu_work1 + "10";
end if;
end if;
falu_fsm <= falu_rtc;
when falu_rtc =>
if falu_work1(58) = '1' then
falu_work1 <= '0' & falu_work1(58 downto 1);
falu_ccw <= falu_ccw + 1;
end if;
falu_fsm <= falu_res;
when falu_res =>
falu_output(63) <= falu_fps(3);
falu_output(62 downto 55) <= falu_ccw(7 downto 0);
falu_output(54 downto 0) <= falu_work1(56 downto 2);
falu_done <= '1';
falu_fsm <= falu_idle;
if falu_ccw(7 downto 0) = "00000000" then
falu_fps(2) <= '1';
else
falu_fps(2) <= '0';
end if;
if falu_ccw(9) = '1' or falu_ccw(9 downto 0) = "0000000000" then
if fps(10) = '1' then -- are underflow traps enabled?
falu_pending_fiu <= '1'; -- yes, set flag
else
falu_fsm <= falu_zres; -- traps are not enabled, output is zero
end if;
elsif falu_ccw(8) = '1' then
falu_fps(1) <= '1'; -- set the flag
if fps(9) = '1' then -- are overflow traps enabled?
falu_pending_fiv <= '1'; -- yes, set flag
else
falu_fsm <= falu_zres; -- traps are not enabled, output is zero
end if;
end if;
when falu_zres =>
falu_output <= (others => '0');
falu_fps(3) <= '0';
falu_fps(2) <= '1';
falu_fps(0) <= '0';
falu_done <= '1';
falu_fsm <= falu_idle;
when falu_idle =>
falu_done <= '0';
falu_ccw <= (others => '0');
falu_work1 <= (others => '0');
falu_work2 <= (others => '0');
falu_flag1 <= '0';
when others =>
null;
end case;
end if;
elsif ir_fpsop2 = '1' then
case ir(7 downto 6) is
when "00" => -- clr(f/d)
falu_output <= (others => '0');
falu_fps(3 downto 0) <= "0100";
when "01" => -- tst(f/d)
falu_output <= falu_input;
if falu_input(62 downto 55) = "00000000" then
falu_fps(2) <= '1';
falu_output <= (others => '0');
else
falu_fps(2) <= '0';
end if;
falu_fps(3) <= falu_input(63);
falu_fps(1) <= '0';
falu_fps(0) <= '0';
when "10" => -- abs(f/d)
falu_output <= '0' & falu_input(62 downto 0);
if falu_input(62 downto 55) = "00000000" then
falu_fps(2) <= '1';
falu_output <= (others => '0');
else
falu_fps(2) <= '0';
end if;
falu_fps(3) <= '0';
falu_fps(1) <= '0';
falu_fps(0) <= '0';
when "11" => -- neg(f/d)
if falu_input(63) = '0' then
falu_output <= '1' & falu_input(62 downto 0);
falu_fps(3) <= '1';
else
falu_output <= '0' & falu_input(62 downto 0);
falu_fps(3) <= '0';
end if;
if falu_input(62 downto 55) = "00000000" then
falu_output <= (others => '0');
falu_fps(2) <= '1';
falu_fps(3) <= '0';
else
falu_fps(2) <= '0';
end if;
falu_fps(1) <= '0';
falu_fps(0) <= '0';
when others =>
falu_output <= (others => 'X');
falu_fps(3 downto 0) <= "XXXX";
end case;
falu_output2 <= (others => 'X');
else
falu_output <= (others => 'X');
falu_output2 <= (others => 'X');
falu_fps(3 downto 0) <= "XXXX";
end if;
end if;
end if;
end process;
end implementation;
|
--
-- USB Full-Speed/Hi-Speed Device Controller core - ulpi_port.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
--! ULPI PHY controller
entity ulpi_port is
generic (
HIGH_SPEED: boolean := true
);
port (
rst : in std_logic; --! Global external asynchronous reset
--! ULPI PHY signals
ulpi_data_in : in std_logic_vector(7 downto 0);
ulpi_data_out : out std_logic_vector(7 downto 0);
ulpi_dir : in std_logic;
ulpi_nxt : in std_logic;
ulpi_stp : out std_logic;
ulpi_reset : out std_logic;
ulpi_clk : in std_logic;
--! RX AXI-Stream, first data is PID
axis_rx_tvalid : out std_logic;
axis_rx_tready : in std_logic;
axis_rx_tlast : out std_logic;
axis_rx_tdata : out std_logic_vector(7 downto 0);
--! TX AXI-Stream, first data should be PID (in 4 least significant bits)
axis_tx_tvalid : in std_logic;
axis_tx_tready : out std_logic;
axis_tx_tlast : in std_logic;
axis_tx_tdata : in std_logic_vector(7 downto 0);
usb_vbus_valid : out std_logic; --! VBUS has valid voltage
usb_reset : out std_logic; --! USB bus is in reset state
usb_idle : out std_logic; --! USB bus is in idle state
usb_suspend : out std_logic --! USB bus is in suspend state
);
end ulpi_port;
architecture ulpi_port of ulpi_port is
constant SUSPEND_TIME : integer := 190000; -- = ~3 ms
constant RESET_TIME : integer := 190000; -- = ~3 ms
constant CHIRP_K_TIME : integer := 66000; -- = ~1 ms
constant CHIRP_KJ_TIME: integer := 120; -- = ~2 us
constant SWITCH_TIME : integer := 6000; -- = ~100 us
type MACHINE is (S_Init, S_WriteReg_A, S_WriteReg_D, S_STP, S_Reset, S_Suspend,
S_Idle, S_TX, S_TX_Last, S_ChirpStart, S_ChirpStartK, S_ChirpK,
S_ChirpKJ, S_SwitchFSStart, S_SwitchFS);
signal state : MACHINE;
signal state_after : MACHINE;
signal dir_d : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal reg_data : std_logic_vector(7 downto 0);
signal buf_data : std_logic_vector(7 downto 0);
signal buf_last : std_logic;
signal buf_valid : std_logic;
signal tx_eop : std_logic := '0';
signal bus_tx_ready : std_logic := '0';
signal chirp_kj_counter : std_logic_vector(2 downto 0);
signal hs_enabled : std_logic := '0';
signal usb_line_state : std_logic_vector(1 downto 0);
signal state_counter : std_logic_vector(17 downto 0);
signal packet : std_logic := '0';
signal packet_buf : std_logic_vector(7 downto 0);
begin
OUTER : process(ulpi_clk) is
begin
if rising_edge(ulpi_clk) then
if dir_d = ulpi_dir and ulpi_dir = '1' and ulpi_nxt = '1' then
packet_buf <= ulpi_data_in;
if packet = '0' then
axis_rx_tvalid <= '0';
packet <= '1';
else
axis_rx_tdata <= packet_buf;
axis_rx_tvalid <= '1';
end if;
axis_rx_tlast <= '0';
elsif packet = '1' and dir_d = ulpi_dir and
((ulpi_dir = '1' and ulpi_data_in(4) = '0') or (ulpi_dir = '0')) then
axis_rx_tdata <= packet_buf;
axis_rx_tvalid <= '1';
axis_rx_tlast <= '1';
packet <= '0';
else
axis_rx_tvalid <= '0';
axis_rx_tlast <= '0';
end if;
end if;
end process;
STATE_COUNT: process(ulpi_clk) is
begin
if rising_edge(ulpi_clk) then
if dir_d = ulpi_dir and ulpi_dir = '1' and ulpi_nxt = '0' AND ulpi_data_in(1 downto 0) /= usb_line_state then
if state = S_ChirpKJ then
if ulpi_data_in(1 downto 0) = "01" then
chirp_kj_counter <= chirp_kj_counter + 1;
end if;
else
chirp_kj_counter <= (others => '0');
end if;
usb_line_state <= ulpi_data_in(1 downto 0);
state_counter <= (others => '0');
elsif state = S_ChirpStartK then
state_counter <= (others => '0');
elsif state = S_SwitchFSStart then
state_counter <= (others => '0');
else
state_counter <= state_counter + 1;
end if;
end if;
end process;
FSM : process(ulpi_clk) is
begin
if rising_edge(ulpi_clk) then
dir_d <= ulpi_dir;
if dir_d = ulpi_dir then
if ulpi_dir = '1' and ulpi_nxt = '0' then
if ulpi_data_in(3 downto 2) = "11" then
usb_vbus_valid <= '1';
else
usb_vbus_valid <= '0';
end if;
elsif ulpi_dir = '0' then
case state is
when S_Init =>
ulpi_data_out <= X"8A";
reg_data <= X"00";
state <= S_WriteReg_A;
state_after <= S_SwitchFSStart;
when S_WriteReg_A =>
if ulpi_nxt = '1' then
ulpi_data_out <= reg_data;
state <= S_WriteReg_D;
end if;
when S_WriteReg_D =>
if ulpi_nxt = '1' then
ulpi_data_out <= X"00";
state <= S_STP;
end if;
when S_Reset =>
usb_reset <= '1';
if hs_enabled = '0' and HIGH_SPEED then
state <= S_ChirpStart;
elsif HIGH_SPEED then
state <= S_SwitchFSStart;
else
if usb_line_state /= "00" then
state <= S_Idle;
end if;
end if;
when S_Suspend =>
-- Should be J state for 20 ms, but I'm too lazy
-- FIXME: Need valid resume sequence for HS
if usb_line_state /= "01" then
state <= S_Idle;
end if;
when S_STP =>
state <= state_after;
when S_Idle =>
usb_reset <= '0';
if usb_line_state = "00" and state_counter > RESET_TIME then
state <= S_Reset;
elsif hs_enabled = '0' and usb_line_state = "01" and state_counter > SUSPEND_TIME then
state <= S_Suspend;
elsif bus_tx_ready = '1' and axis_tx_tvalid = '1' then
ulpi_data_out <= "0100" & axis_tx_tdata(3 downto 0);
buf_valid <= '0';
if axis_tx_tlast = '1' then
state <= S_TX_Last;
else
state <= S_TX;
end if;
end if;
when S_TX =>
if ulpi_nxt = '1' then
if axis_tx_tvalid = '1' and buf_valid = '0' then
ulpi_data_out <= axis_tx_tdata;
if axis_tx_tlast = '1' then
state <= S_TX_Last;
end if;
elsif buf_valid = '1' then
ulpi_data_out <= buf_data;
buf_valid <= '0';
if buf_last = '1' then
state <= S_TX_Last;
end if;
else
ulpi_data_out <= X"00";
end if;
else
if axis_tx_tvalid = '1' and buf_valid = '0' then
buf_data <= axis_tx_tdata;
buf_last <= axis_tx_tlast;
buf_valid <= '1';
end if;
end if;
when S_TX_Last =>
if ulpi_nxt = '1' then
ulpi_data_out <= X"00";
state_after <= S_Idle;
state <= S_STP;
end if;
when S_ChirpStart =>
reg_data <= b"0_1_0_10_1_00";
ulpi_data_out <= X"84";
state <= S_WriteReg_A;
state_after <= S_ChirpStartK;
when S_ChirpStartK =>
if ulpi_nxt = '1' then
ulpi_data_out <= X"00";
state <= S_ChirpK;
else
ulpi_data_out <= X"40";
end if;
when S_ChirpK =>
if state_counter > CHIRP_K_TIME then
ulpi_data_out <= X"00";
state <= S_STP;
state_after <= S_ChirpKJ;
end if;
when S_ChirpKJ =>
if chirp_kj_counter > 3 AND state_counter > CHIRP_KJ_TIME then
reg_data <= b"0_1_0_00_0_00";
ulpi_data_out <= X"84";
state <= S_WriteReg_A;
state_after <= S_Idle;
hs_enabled <= '1';
end if;
when S_SwitchFSStart =>
reg_data <= b"0_1_0_00_1_01";
ulpi_data_out <= X"84";
state <= S_WriteReg_A;
hs_enabled <= '0';
state_after <= S_SwitchFS;
when S_SwitchFS =>
if state_counter > SWITCH_TIME then
if usb_line_state = "00" AND HIGH_SPEED then
state <= S_ChirpStart;
else
state <= S_Idle;
end if;
end if;
end case;
end if;
end if;
end if;
end process;
ulpi_stp <= '1' when ulpi_dir = '1' and axis_rx_tready = '0' else
'1' when state = S_STP else
'0';
ulpi_reset <= rst;
bus_tx_ready <= '1' when ulpi_dir = '0' and ulpi_dir = dir_d else
'0';
axis_tx_tready <= '1' when bus_tx_ready = '1' and state = S_Idle else
'1' when bus_tx_ready = '1' and state = S_TX and buf_valid = '0' else
'0';
usb_idle <= '1' when state = S_Idle else
'0';
usb_suspend <= '1' when state = S_Suspend else
'0';
end ulpi_port;
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Decode the ADS1281 bit streams M0 and M1 according to the equation from
-- the data sheet.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ads1281_filter_decoder is
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Buffered ADC bit streams
adc_m0_i : in std_ulogic_vector(2 downto 0);
adc_m1_i : in std_ulogic_vector(2 downto 0);
-- Decoded data
data_o : out signed(6 downto 0));
end entity ads1281_filter_decoder;
architecture rtl of ads1281_filter_decoder is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
constant addr_len_c : natural := adc_m0_i'length + adc_m1_i'length;
type lut_t is array (0 to 2**addr_len_c - 1) of integer range -49 to 49;
-- Look-up table with pre-calculated values using the following equation:
-- Y[n] = 3*M0[n-2] - 6*M0[n-3] + 4*M0[n-4] + 9*(M1[n] - 2*M1[n-1] + M1[n-2])
constant lut : lut_t := (
1, -17, 37, 19, -17, -35, 19, 1, -5, -23, 31, 13, -23, -41, 13, -5, 13, -5,
49, 31, -5, -23, 31, 13, 7, -11, 43, 25, -11, -29, 25, 7, -7, -25, 29, 11,
-25, -43, 11, -7, -13, -31, 23, 5, -31, -49, 5, -13, 5, -13, 41, 23, -13,
-31, 23, 5, -1, -19, 35, 17, -19, -37, 17, -1);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal data : signed(6 downto 0);
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal addr : unsigned(addr_len_c - 1 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
data_o <= data;
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- Combine samples and previous sample values to an address
addr <= adc_m0_i(2) & adc_m0_i(1) & adc_m0_i(0) & adc_m1_i(2) & adc_m1_i(1) & adc_m1_i(0);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
data <= to_signed(0, data'length);
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
-- Map combined address to pre-calculated output value
data <= to_signed(lut(to_integer(addr)), data'length);
end if;
end if;
end process regs;
end architecture rtl;
|
library verilog;
use verilog.vl_types.all;
entity cpu is
end cpu;
|
library verilog;
use verilog.vl_types.all;
entity cpu is
end cpu;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
use work.all;
--! E-link processor, 4bit output
entity EPROC_OUT4 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (3 downto 0);
TTCin : in std_logic_vector (4 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end EPROC_OUT4;
architecture Behavioral of EPROC_OUT4 is
constant zeros4bit : std_logic_vector (3 downto 0) := (others=>'0');
signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC1_case, EdataOUT_TTC2_case : std_logic_vector (3 downto 0);
signal rst_s, rst_case000, rst_case001, rst_case010, rst_case011 : std_logic;
signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case, getDataTrig_TTC_cases : std_logic;
begin
gen_enabled: if do_generate = true generate
rst_s <= rst or (not ENA);
-------------------------------------------------------------------------------------------
-- case 0: direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case000 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "000")) else '1';
direct_case: entity work.EPROC_OUT4_direct
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case000,
getDataTrig => getDataTrig_direct_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_direct_case
);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
EdataOUT_direct_case <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- case 1: DEC8b10b
-------------------------------------------------------------------------------------------
rst_case001 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "001")) else '1';
--
ENC8b10b_case: entity work.EPROC_OUT4_ENC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case001,
getDataTrig => getDataTrig_ENC8b10b_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_ENC8b10b_case
);
--
-------------------------------------------------------------------------------------------
-- case 2: HDLC
-------------------------------------------------------------------------------------------
rst_case010 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "010")) else '1';
--
getDataTrig_HDLC_case <= '0'; --'1' when (ENCODING(2 downto 0) = "010") else '0';
EdataOUT_HDLC_case <= (others=>'0'); --<---TBD
--
-------------------------------------------------------------------------------------------
-- case 3&4: TTC-1 & TTC-2
-------------------------------------------------------------------------------------------
rst_case011 <= '0' when ((rst_s = '0') and ((ENCODING(2 downto 0) = "011") or (ENCODING(2 downto 0) = "100"))) else '1';
--
getDataTrig_TTC_cases <= '0'; --'1' when ((ENCODING(2 downto 0) = "011") or (ENCODING(2 downto 0) = "100")) else '0';
--
ttc_r: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst_case011 = '1' then
EdataOUT_TTC1_case <= zeros4bit;
EdataOUT_TTC2_case <= zeros4bit;
else
EdataOUT_TTC1_case <= TTCin(1) & TTCin(3 downto 2) & TTCin(0);
EdataOUT_TTC2_case <= TTCin(4 downto 2) & TTCin(0);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- output data and busy according to the encoding settings
-------------------------------------------------------------------------------------------
dataOUTmux: entity work.MUX8_Nbit
generic map (N=>4)
port map(
data0 => EdataOUT_direct_case,
data1 => EdataOUT_ENC8b10b_case,
data2 => EdataOUT_HDLC_case,
data3 => EdataOUT_TTC1_case,
data4 => EdataOUT_TTC2_case,
data5 => zeros4bit,
data6 => zeros4bit,
data7 => zeros4bit,
sel => ENCODING(2 downto 0),
data_out => EDATA_OUT
);
--
getDataTrig <= ENA and (getDataTrig_TTC_cases or getDataTrig_HDLC_case or getDataTrig_ENC8b10b_case or getDataTrig_direct_case);
--
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
EDATA_OUT <= (others=>'0');
getDataTrig <= '0';
end generate gen_disabled;
end Behavioral;
|
-- tb_Test_Pattern_Generator.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:06
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Test_Pattern_Generator is
end entity tb_Test_Pattern_Generator;
architecture rtl of tb_Test_Pattern_Generator is
component Test_Pattern_Generator_GN is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset_n
Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
Avalon_ST_Source_valid : out std_logic; -- wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
Avalon_ST_Source_endofpacket : out std_logic; -- wire
Avalon_ST_Source_startofpacket : out std_logic; -- wire
Avalon_MM_Slave_write : in std_logic := 'X'; -- wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- wire
Avalon_ST_Source_ready : in std_logic := 'X' -- wire
);
end component Test_Pattern_Generator_GN;
component alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic (
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic; -- reset
clock_out : out std_logic; -- clk
reg_aclr_out : out std_logic; -- reset
tb_aclr : out std_logic -- reset
);
end component alt_dspbuilder_testbench_clock_GNCGUFKHRR;
component alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN6DKNTQ5M;
component alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN7Z4SHGOK;
component alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic -- wire
);
end component alt_dspbuilder_testbench_salt_GNDBMPYDND;
component alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_testbench_capture_GNQX2JTRTZ;
component alt_dspbuilder_testbench_capture_GNHCRI5YMO is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_testbench_capture_GNHCRI5YMO;
signal salt_avalon_mm_slave_address_output_wire : std_logic_vector(1 downto 0); -- salt_Avalon_MM_Slave_address:output -> dut:Avalon_MM_Slave_address
signal clock_clock_tb_reset : std_logic; -- Clock:tb_aclr -> [salt_Avalon_MM_Slave_address:aclr, salt_Avalon_MM_Slave_write:aclr, salt_Avalon_MM_Slave_writedata:aclr, salt_Avalon_ST_Source_ready:aclr]
signal clock_clock_tb_clk : std_logic; -- Clock:clock_out -> [capture_Avalon_ST_Source_data:clock, capture_Avalon_ST_Source_endofpacket:clock, capture_Avalon_ST_Source_startofpacket:clock, capture_Avalon_ST_Source_valid:clock, dut:Clock, salt_Avalon_MM_Slave_address:clock, salt_Avalon_MM_Slave_write:clock, salt_Avalon_MM_Slave_writedata:clock, salt_Avalon_ST_Source_ready:clock]
signal salt_avalon_mm_slave_writedata_output_wire : std_logic_vector(31 downto 0); -- salt_Avalon_MM_Slave_writedata:output -> dut:Avalon_MM_Slave_writedata
signal salt_avalon_mm_slave_write_output_wire : std_logic; -- salt_Avalon_MM_Slave_write:output -> dut:Avalon_MM_Slave_write
signal salt_avalon_st_source_ready_output_wire : std_logic; -- salt_Avalon_ST_Source_ready:output -> dut:Avalon_ST_Source_ready
signal dut_avalon_st_source_valid_wire : std_logic; -- dut:Avalon_ST_Source_valid -> capture_Avalon_ST_Source_valid:input
signal clock_clock_reg_reset_reset : std_logic; -- Clock:reg_aclr_out -> [capture_Avalon_ST_Source_data:aclr, capture_Avalon_ST_Source_endofpacket:aclr, capture_Avalon_ST_Source_startofpacket:aclr, capture_Avalon_ST_Source_valid:aclr]
signal dut_avalon_st_source_endofpacket_wire : std_logic; -- dut:Avalon_ST_Source_endofpacket -> capture_Avalon_ST_Source_endofpacket:input
signal dut_avalon_st_source_startofpacket_wire : std_logic; -- dut:Avalon_ST_Source_startofpacket -> capture_Avalon_ST_Source_startofpacket:input
signal dut_avalon_st_source_data_wire : std_logic_vector(23 downto 0); -- dut:Avalon_ST_Source_data -> capture_Avalon_ST_Source_data:input
signal clock_clock_output_reset : std_logic; -- Clock:aclr_out -> clock_clock_output_reset:in
signal clock_clock_output_reset_ports_inv : std_logic; -- clock_clock_output_reset:inv -> dut:aclr
begin
dut : component Test_Pattern_Generator_GN
port map (
Clock => clock_clock_tb_clk, -- Clock.clk
aclr => clock_clock_output_reset_ports_inv, -- .reset_n
Avalon_MM_Slave_address => salt_avalon_mm_slave_address_output_wire, -- Avalon_MM_Slave_address.wire
Avalon_ST_Source_valid => dut_avalon_st_source_valid_wire, -- Avalon_ST_Source_valid.wire
Avalon_MM_Slave_writedata => salt_avalon_mm_slave_writedata_output_wire, -- Avalon_MM_Slave_writedata.wire
Avalon_ST_Source_endofpacket => dut_avalon_st_source_endofpacket_wire, -- Avalon_ST_Source_endofpacket.wire
Avalon_ST_Source_startofpacket => dut_avalon_st_source_startofpacket_wire, -- Avalon_ST_Source_startofpacket.wire
Avalon_MM_Slave_write => salt_avalon_mm_slave_write_output_wire, -- Avalon_MM_Slave_write.wire
Avalon_ST_Source_data => dut_avalon_st_source_data_wire, -- Avalon_ST_Source_data.wire
Avalon_ST_Source_ready => salt_avalon_st_source_ready_output_wire -- Avalon_ST_Source_ready.wire
);
clock : component alt_dspbuilder_testbench_clock_GNCGUFKHRR
generic map (
SIMULATION_START_CYCLE => 5,
RESET_LATENCY => 0,
RESET_REGISTER_CASCADE_DEPTH => 0
)
port map (
clock_out => clock_clock_tb_clk, -- clock_tb.clk
tb_aclr => clock_clock_tb_reset, -- .reset
aclr_out => clock_clock_output_reset, -- clock_output.reset
reg_aclr_out => clock_clock_reg_reset_reset -- clock_reg_reset.reset
);
salt_avalon_mm_slave_address : component alt_dspbuilder_testbench_salt_GN6DKNTQ5M
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon-MM+Slave_address.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_address_output_wire -- output.wire
);
salt_avalon_mm_slave_writedata : component alt_dspbuilder_testbench_salt_GN7Z4SHGOK
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon-MM+Slave_writedata.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_writedata_output_wire -- output.wire
);
salt_avalon_mm_slave_write : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon-MM+Slave_write.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_write_output_wire -- output.wire
);
salt_avalon_st_source_ready : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_ready.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_source_ready_output_wire -- output.wire
);
capture_avalon_st_source_valid : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_valid.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_valid_wire -- input.wire
);
capture_avalon_st_source_endofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_endofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_endofpacket_wire -- input.wire
);
capture_avalon_st_source_startofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_startofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_startofpacket_wire -- input.wire
);
capture_avalon_st_source_data : component alt_dspbuilder_testbench_capture_GNHCRI5YMO
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_data.capture.msim",
DSPBTYPE => "UINT [24, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_data_wire -- input.wire
);
clock_clock_output_reset_ports_inv <= not clock_clock_output_reset;
end architecture rtl; -- of tb_Test_Pattern_Generator
|
-- tb_Test_Pattern_Generator.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:06
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Test_Pattern_Generator is
end entity tb_Test_Pattern_Generator;
architecture rtl of tb_Test_Pattern_Generator is
component Test_Pattern_Generator_GN is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset_n
Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
Avalon_ST_Source_valid : out std_logic; -- wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
Avalon_ST_Source_endofpacket : out std_logic; -- wire
Avalon_ST_Source_startofpacket : out std_logic; -- wire
Avalon_MM_Slave_write : in std_logic := 'X'; -- wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- wire
Avalon_ST_Source_ready : in std_logic := 'X' -- wire
);
end component Test_Pattern_Generator_GN;
component alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic (
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic; -- reset
clock_out : out std_logic; -- clk
reg_aclr_out : out std_logic; -- reset
tb_aclr : out std_logic -- reset
);
end component alt_dspbuilder_testbench_clock_GNCGUFKHRR;
component alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN6DKNTQ5M;
component alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN7Z4SHGOK;
component alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic -- wire
);
end component alt_dspbuilder_testbench_salt_GNDBMPYDND;
component alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_testbench_capture_GNQX2JTRTZ;
component alt_dspbuilder_testbench_capture_GNHCRI5YMO is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_testbench_capture_GNHCRI5YMO;
signal salt_avalon_mm_slave_address_output_wire : std_logic_vector(1 downto 0); -- salt_Avalon_MM_Slave_address:output -> dut:Avalon_MM_Slave_address
signal clock_clock_tb_reset : std_logic; -- Clock:tb_aclr -> [salt_Avalon_MM_Slave_address:aclr, salt_Avalon_MM_Slave_write:aclr, salt_Avalon_MM_Slave_writedata:aclr, salt_Avalon_ST_Source_ready:aclr]
signal clock_clock_tb_clk : std_logic; -- Clock:clock_out -> [capture_Avalon_ST_Source_data:clock, capture_Avalon_ST_Source_endofpacket:clock, capture_Avalon_ST_Source_startofpacket:clock, capture_Avalon_ST_Source_valid:clock, dut:Clock, salt_Avalon_MM_Slave_address:clock, salt_Avalon_MM_Slave_write:clock, salt_Avalon_MM_Slave_writedata:clock, salt_Avalon_ST_Source_ready:clock]
signal salt_avalon_mm_slave_writedata_output_wire : std_logic_vector(31 downto 0); -- salt_Avalon_MM_Slave_writedata:output -> dut:Avalon_MM_Slave_writedata
signal salt_avalon_mm_slave_write_output_wire : std_logic; -- salt_Avalon_MM_Slave_write:output -> dut:Avalon_MM_Slave_write
signal salt_avalon_st_source_ready_output_wire : std_logic; -- salt_Avalon_ST_Source_ready:output -> dut:Avalon_ST_Source_ready
signal dut_avalon_st_source_valid_wire : std_logic; -- dut:Avalon_ST_Source_valid -> capture_Avalon_ST_Source_valid:input
signal clock_clock_reg_reset_reset : std_logic; -- Clock:reg_aclr_out -> [capture_Avalon_ST_Source_data:aclr, capture_Avalon_ST_Source_endofpacket:aclr, capture_Avalon_ST_Source_startofpacket:aclr, capture_Avalon_ST_Source_valid:aclr]
signal dut_avalon_st_source_endofpacket_wire : std_logic; -- dut:Avalon_ST_Source_endofpacket -> capture_Avalon_ST_Source_endofpacket:input
signal dut_avalon_st_source_startofpacket_wire : std_logic; -- dut:Avalon_ST_Source_startofpacket -> capture_Avalon_ST_Source_startofpacket:input
signal dut_avalon_st_source_data_wire : std_logic_vector(23 downto 0); -- dut:Avalon_ST_Source_data -> capture_Avalon_ST_Source_data:input
signal clock_clock_output_reset : std_logic; -- Clock:aclr_out -> clock_clock_output_reset:in
signal clock_clock_output_reset_ports_inv : std_logic; -- clock_clock_output_reset:inv -> dut:aclr
begin
dut : component Test_Pattern_Generator_GN
port map (
Clock => clock_clock_tb_clk, -- Clock.clk
aclr => clock_clock_output_reset_ports_inv, -- .reset_n
Avalon_MM_Slave_address => salt_avalon_mm_slave_address_output_wire, -- Avalon_MM_Slave_address.wire
Avalon_ST_Source_valid => dut_avalon_st_source_valid_wire, -- Avalon_ST_Source_valid.wire
Avalon_MM_Slave_writedata => salt_avalon_mm_slave_writedata_output_wire, -- Avalon_MM_Slave_writedata.wire
Avalon_ST_Source_endofpacket => dut_avalon_st_source_endofpacket_wire, -- Avalon_ST_Source_endofpacket.wire
Avalon_ST_Source_startofpacket => dut_avalon_st_source_startofpacket_wire, -- Avalon_ST_Source_startofpacket.wire
Avalon_MM_Slave_write => salt_avalon_mm_slave_write_output_wire, -- Avalon_MM_Slave_write.wire
Avalon_ST_Source_data => dut_avalon_st_source_data_wire, -- Avalon_ST_Source_data.wire
Avalon_ST_Source_ready => salt_avalon_st_source_ready_output_wire -- Avalon_ST_Source_ready.wire
);
clock : component alt_dspbuilder_testbench_clock_GNCGUFKHRR
generic map (
SIMULATION_START_CYCLE => 5,
RESET_LATENCY => 0,
RESET_REGISTER_CASCADE_DEPTH => 0
)
port map (
clock_out => clock_clock_tb_clk, -- clock_tb.clk
tb_aclr => clock_clock_tb_reset, -- .reset
aclr_out => clock_clock_output_reset, -- clock_output.reset
reg_aclr_out => clock_clock_reg_reset_reset -- clock_reg_reset.reset
);
salt_avalon_mm_slave_address : component alt_dspbuilder_testbench_salt_GN6DKNTQ5M
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon-MM+Slave_address.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_address_output_wire -- output.wire
);
salt_avalon_mm_slave_writedata : component alt_dspbuilder_testbench_salt_GN7Z4SHGOK
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon-MM+Slave_writedata.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_writedata_output_wire -- output.wire
);
salt_avalon_mm_slave_write : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon-MM+Slave_write.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_write_output_wire -- output.wire
);
salt_avalon_st_source_ready : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_ready.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_source_ready_output_wire -- output.wire
);
capture_avalon_st_source_valid : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_valid.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_valid_wire -- input.wire
);
capture_avalon_st_source_endofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_endofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_endofpacket_wire -- input.wire
);
capture_avalon_st_source_startofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_startofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_startofpacket_wire -- input.wire
);
capture_avalon_st_source_data : component alt_dspbuilder_testbench_capture_GNHCRI5YMO
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_data.capture.msim",
DSPBTYPE => "UINT [24, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_data_wire -- input.wire
);
clock_clock_output_reset_ports_inv <= not clock_clock_output_reset;
end architecture rtl; -- of tb_Test_Pattern_Generator
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file fifo.vhd
--! @brief Configurable fifo
--! @author Benjamin Bässler
--! @email ccl@xunit.de
--! @date 2013-07-24
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.utils.all;
--! simple synchronous FIFO
entity fifo is
generic(
--! Size of the fifo in input words
G_SIZE : NATURAL := 64;
--! input width in bits
G_WORD_WIDTH : NATURAL := 8;
--! Threshold for the almost empty signal
G_ALMOST_EMPTY : NATURAL := 1;
--! Threshold for the nearly full signal in input words
G_ALMOST_FULL : NATURAL := 64 - 1;
--! First Word Fall Through
G_FWFT : BOOLEAN := false
);
port(
--! Reset input
rst_in : in STD_LOGIC;
--! Clock input
clk_in : in STD_LOGIC;
--! Data input
wr_d_in : in unsigned(G_WORD_WIDTH - 1 downto 0);
--! Data on write input valid
wr_valid_in : in STD_LOGIC;
--! Fifo reached the G_ALMOST_FULL threshold
almost_full_out : out STD_LOGIC;
--! Fifo is full
full_out : out STD_LOGIC;
--! Data output
rd_d_out : out unsigned(G_WORD_WIDTH - 1 downto 0);
--! Data on output read -> next
rd_next_in : in STD_LOGIC;
--! Fifo reached the G_ALMOST_EMPTY threshold
almost_empty_out : out STD_LOGIC;
--! Fifo is empty
empty_out : out STD_LOGIC;
--! Fill level of fifo
fill_lvl_out : out unsigned(log2_ceil(G_SIZE) downto 0)
);
end entity fifo;
architecture fifo_arc of fifo is
type T_BUFFER is array (G_SIZE - 1 downto 0)
of UNSIGNED(G_WORD_WIDTH - 1 downto 0);
signal buf_s : T_BUFFER;
signal rd_cnt_s : UNSIGNED(log2_ceil(G_SIZE) - 1 downto 0);
signal wr_cnt_s : UNSIGNED(log2_ceil(G_SIZE) - 1 downto 0);
signal fill_lvl_s : UNSIGNED(log2_ceil(G_SIZE) downto 0);
begin
--empty_out <= '1' when fill_lvl_s = 0 else '0';
empty_out <= '1' when rd_cnt_s = wr_cnt_s else '0';
full_out <= '1' when fill_lvl_s = G_SIZE else '0';
almost_full_out <= '1' when fill_lvl_s >= G_ALMOST_FULL else '0';
almost_empty_out <= '1' when fill_lvl_s <= G_ALMOST_EMPTY else '0';
fill_lvl_out <= fill_lvl_s;
p_fill_level : process (clk_in, rst_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
fill_lvl_s <= (others => '0');
else
if rd_next_in = '1' and wr_valid_in = '0' then
if fill_lvl_s > 0 then
fill_lvl_s <= fill_lvl_s - 1;
end if;
elsif rd_next_in = '0' and wr_valid_in = '1' then
if fill_lvl_s < G_SIZE then
fill_lvl_s <= fill_lvl_s + 1;
end if;
elsif rd_next_in = '1' and wr_valid_in = '1' then
if fill_lvl_s = 0 then
fill_lvl_s <= fill_lvl_s + 1;
end if;
end if;
end if;
end if;
end process p_fill_level;
p_write : process (clk_in, rst_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
wr_cnt_s <= (others => '0');
else
if wr_valid_in = '1' then
if fill_lvl_s < G_SIZE then
if not (G_FWFT and fill_lvl_s = 0) and
not (G_FWFT and fill_lvl_s = 1 and rd_next_in = '1') then
buf_s(to_integer(wr_cnt_s)) <= wr_d_in;
if wr_cnt_s = G_SIZE-1 then
wr_cnt_s <= (others => '0');
else
wr_cnt_s <= wr_cnt_s + 1;
end if;
end if;
else
report "Fifo Buffer overflow data droped" severity warning;
end if;
end if;
end if;
end if;
end process p_write;
p_read : process (clk_in, rst_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
rd_cnt_s <= (others => '0');
else
if G_FWFT and fill_lvl_s = 0 and wr_valid_in = '1' then
-- data are written to a empty fifo (no data on the output)
-- in first word fall through mode the data needs to be output
rd_d_out <= wr_d_in;
elsif rd_next_in = '1' and fill_lvl_s > 0 then
-- new data read from a filled fifo
if G_FWFT and fill_lvl_s = 1 and wr_valid_in = '1' then
-- in case of FWFT all words are on output new output is only
-- possible if new data arrives at the moment
rd_d_out <= wr_d_in;
else
rd_d_out <= buf_s(to_integer(rd_cnt_s));
if fill_lvl_s > 1 or not G_FWFT then
if rd_cnt_s = G_SIZE -1 then
rd_cnt_s <= (others => '0');
else
rd_cnt_s <= rd_cnt_s + 1;
end if;
end if;
end if;
else
assert rd_next_in = '0' report "Read from empty fifo" severity warning;
end if;
end if;
end if;
end process p_read;
end fifo_arc;
|
-------------------------------------------------------------------------------
--
-- Ce bloc envoie des messages tous les 1000 ticks au PC
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY checker IS
GENERIC(
MYADDR : STD_LOGIC_VECTOR(7 downto 0) := "00001010" -- 10
);
PORT(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 downto 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : out STD_LOGIC_VECTOR(43 downto 0);
busout_valid : out STD_LOGIC;
busout_eated : in STD_LOGIC;
);
END checker;
ARCHITECTURE montage OF checker IS
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
-- Registre de transfert entre busin et busout
type T_CMD_tft is (INIT, NOOP);
signal CMD_tft : T_CMD_tft ;
signal R_tft : STD_LOGIC_VECTOR (43 downto 0);
-- Commande pour 'busmsg'
-- LOAD => chargement du message
-- NOOP => charge un message vide (NOOP)
TYPE T_CMD_Msg IS (LOAD, NOOP);
signal CMD_Msg : T_CMD_Msg ;
-- registre stockant les 32 valeurs du 7 segments configurées (7 * 32 = 224)
signal R_SS : STD_LOGIC_VECTOR(229 downto 0);
-- registre stockant V (nombre de master clock à attendre avant de générer un tick)
signal R_N_CLOCK : STD_LOGIC_VECTOR(21 downto 0);
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- adresse destination
alias busin_addrdest : STD_LOGIC_VECTOR(7 downto 0) is busin(31 downto 24);
type STATE_TYPE is (
ST_READ_BUSIN, ST_WRITE_OUT, ST_LOAD_MSG
);
signal state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
PROCESS (reset, clk)
BEGIN
-- si on reset
IF reset = '1' THEN
-- 5 000 000 <=> 100 ticks par secondes
-- 5 000 000 / 2 = 2 500 000 = 0b1001100010010110100000
R_N_CLOCK <= "1001100010010110100000";
-- configure le serpentin pour qu'il soit vide
R_SS <= (5 => '1', others => '0');
ELSIF clk'event AND clk = '1' THEN
-- commandes de transfert bus ia
-- si l'on doit lire le message, on le stocke
-- dans le registre 'R_tft'
IF CMD_tft = INIT THEN
R_tft <= busin ;
END IF;
-- si le message doit être chargé
-- on met à jour le registre de stockage
IF CMD_Msg = LOAD THEN
-- switch l'id du message
CASE R_tft(23 downto 22) IS
-- hinit(n_clock)
WHEN "00" =>
R_N_CLOCK <= R_tft(21 downto 0);
-- clr(s)
WHEN "01" =>
R_SS <= (5 => '1', others => '0');
-- si commande set-N(n)
WHEN "10" =>
R_SS(5 downto 0) <= R_tft(5 downto 0);
-- si commande set-val(i, v)
WHEN "11" =>
-- TODO
-- R_SS((i + 1) * 7 - 1, i * 7) <= R_Msg(6 downto 0);
END CASE;
END IF ;
END IF;
END PROCESS;
-- sortie
busNClock <= R_N_CLOCK;
busSS <= R_SS;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: busin_valid, busout_eated, busin_addrdest
-- Outputs: busin_eated, busout_valid, CMD_tft
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
IF reset = '1' THEN
state <= ST_READ_BUSIN;
ELSIF clk'event AND clk = '1' THEN
CASE state IS
WHEN ST_READ_BUSIN =>
IF busin_valid='1' THEN
IF busin_addrdest = MYADDR THEN
state <= ST_LOAD_MSG ;
ELSE
state <= ST_WRITE_OUT ;
END IF ;
END IF ;
WHEN ST_WRITE_OUT =>
IF busout_eated = '1' THEN
state <= ST_READ_BUSIN;
END IF ;
WHEN ST_LOAD_MSG =>
state <= ST_READ_BUSIN;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
WITH state SELECT busin_eated <=
'1' WHEN ST_READ_BUSIN,
'0' WHEN others
;
WITH state SELECT busout_valid <=
'1' WHEN ST_WRITE_OUT,
'0' WHEN others
;
WITH state SELECT CMD_tft <=
INIT WHEN ST_READ_BUSIN,
NOOP WHEN others
;
WITH state SELECT CMD_Msg <=
LOAD WHEN ST_LOAD_MSG,
NOOP WHEN others
;
end montage;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 11:48:21 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_1_2,Vivado 2016.3";
begin
end;
|
-------------------------------------------------------------------------------
--
-- T8039 Microcontroller System
--
-- $Id: t8039-c.vhd,v 1.2 2004-12-03 19:43:12 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t8039_struct_c0 of t8039 is
for struct
for t8039_notri_b : t8039_notri
use configuration work.t8039_notri_struct_c0;
end for;
end for;
end t8039_struct_c0;
|
---------------------------------------------------------------------------------
-- Title : UDP TX Fragmenter
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : UdpTxFragmenter.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects UDP layer to IPv4 layer, decides how to fragment data into MTU-size
-- blocks.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity UdpTxFragmenter is
generic (
GATE_DELAY_G : time := 1 ns;
MTU_SIZE_G : integer := 1500;
ID_OFFSET_G : slv(15 downto 0) := (others => '0')
);
port (
-- 125 MHz ethernet clock in
ethTxClk : in sl;
ethTxRst : in sl := '0';
-- Header data
ipPacketLength : out slv(15 downto 0);
ipPacketId : out slv(15 downto 0);
ipMoreFragments : out sl;
ipFragOffset : out slv(12 downto 0);
ipProtocol : out slv( 7 downto 0);
-- User data to be sent
udpData : in slv(31 downto 0);
udpDataValid : in sl;
udpDataReady : out sl;
udpLength : in slv(15 downto 0);
udpReq : in sl;
udpAck : out sl;
-- Interface to IPv4 frame block
ipData : out slv(31 downto 0);
ipDataValid : out sl;
ipDataReady : in sl
);
end UdpTxFragmenter;
architecture rtl of UdpTxFragmenter is
type StateType is (IDLE_S, CHECK_SIZE_S,
SEND_MTU_PAUSE_S, SEND_MTU_S,
SEND_REMAINDER_PAUSE_S, SEND_REMAINDER_S,
WAIT_S);
type RegType is record
state : StateType;
udpBytesLeft : slv(15 downto 0);
mtuCount : slv(15 downto 0);
ipPacketLength : slv(15 downto 0);
ipPacketId : slv(15 downto 0);
ipMoreFragments : sl;
ipFragOffset : slv(12 downto 0);
ipProtocol : slv( 7 downto 0);
udpAck : sl;
ipData : slv(31 downto 0);
ipDataValid : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
udpBytesLeft => (others => '0'),
mtuCount => (others => '0'),
ipPacketLength => (others => '0'),
ipPacketId => ID_OFFSET_G,
ipMoreFragments => '0',
ipFragOffset => (others => '0'),
ipProtocol => (others => '0'),
udpAck => '0',
ipData => (others => '0'),
ipDataValid => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,ethTxRst,udpData,udpDataValid,udpLength,
udpReq,ipDataReady) is
variable v : RegType;
begin
v := r;
-- Set defaults / reset any pulsed signals
udpDataReady <= '0';
ipDataValid <= '0';
ipData <= (others => '0');
v.ipProtocol := UDP_PROTOCOL_C;
-- State machine
case(r.state) is
when IDLE_S =>
if udpDataValid = '1' then
v.udpBytesLeft := udpLength - 4;
v.ipFragOffset := (others => '0');
v.state := CHECK_SIZE_S;
end if;
when CHECK_SIZE_S =>
-- Wait for last transfer to finish
if r.ipDataValid = '0' then
-- If the size of the UDP payload + IPv4 header (20 bytes) is
-- less than an MTU, then this is the only packet
if conv_integer(r.udpBytesLeft) + 24 <= MTU_SIZE_G then
v.ipPacketLength := r.udpBytesLeft + 24;
v.ipMoreFragments := '0';
v.state := SEND_REMAINDER_PAUSE_S;
else
v.ipPacketLength := conv_std_logic_vector(MTU_SIZE_G,v.ipPacketLength'length);
v.ipMoreFragments := '1';
-- Offset here to stop on the right word
v.mtuCount := conv_std_logic_vector(MTU_SIZE_G - 20 - 4,v.mtuCount'length);
v.state := SEND_MTU_PAUSE_S;
end if;
end if;
when SEND_MTU_PAUSE_S =>
v.state := SEND_MTU_S;
when SEND_MTU_S =>
ipData <= udpData;
ipDataValid <= udpDataValid;
udpDataReady <= ipDataReady;
if ipDataReady = '1' and udpDataValid = '1' then
v.mtuCount := r.mtuCount - 4;
v.udpBytesLeft := r.udpBytesLeft - 4;
if r.mtuCount = 0 then
v.ipFragOffset := r.ipFragOffset + ( (MTU_SIZE_G-20)/8 );
v.state := CHECK_SIZE_S;
end if;
end if;
when SEND_REMAINDER_PAUSE_S =>
v.state := SEND_REMAINDER_S;
when SEND_REMAINDER_S =>
ipData <= udpData;
ipDataValid <= udpDataValid;
udpDataReady <= ipDataReady;
if ipDataReady = '1' and udpDataValid = '1' then
v.udpBytesLeft := r.udpBytesLeft - 4;
if r.udpBytesLeft = 0 then
v.udpAck := '1';
v.state := WAIT_S;
end if;
end if;
when WAIT_S =>
if udpReq = '0' then
v.ipPacketId := r.ipPacketId + 1;
v.udpAck := '0';
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (ethTxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
ipPacketLength <= r.ipPacketLength;
ipPacketId <= r.ipPacketId;
ipMoreFragments <= r.ipMoreFragments;
ipFragOffset <= r.ipFragOffset;
ipProtocol <= r.ipProtocol;
udpAck <= r.udpAck;
-- ipData <= r.ipData;
-- ipDataValid <= r.ipDataValid;
-- Assign variable to signal
rin <= v;
end process;
seq : process (ethTxClk) is
begin
if (rising_edge(ethTxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- DEBUG
--use std.textio.all;
--library util;
--use util.io_pkg.all;
-- END DEBUG
library util;
use util.numeric_pkg.all;
use util.types_pkg.all;
use work.uart_pkg.all;
architecture behav of uart is
type uartfile is file of character;
file ifile : uartfile;
file ofile : uartfile;
type register_type is record
dataout : std_ulogic_vector2(data_bytes-1 downto 0, byte_bits-1 downto 0);
end record;
signal r : register_type;
begin
dataout <= r.dataout;
seq : process (clk) is
variable v_byte_address : std_ulogic_vector(uart_rsel_bits-1 downto 0);
variable v_status : file_open_status;
variable v_r_next : register_type;
variable v_char : character;
-- DEBUG
--variable tmpline : line;
-- END DEBUG
begin
if rising_edge(clk) then
if rstn = '0' then
file_close (ifile);
file_close (ofile);
file_open (v_status, ifile, ifilename, read_mode);
if (v_status /= open_ok) then
report "could not open UART input file " & ifilename severity error;
end if;
file_open (v_status, ofile, ofilename, write_mode);
if (v_status /= open_ok) then
report "could not open UART output file " & ofilename severity error;
end if;
r <= (
dataout => (others => (others => 'X'))
);
else
v_r_next := r;
if enable = '1' then
if wenable = '1' then
v_r_next.dataout := (others => (others => 'X'));
for n in 0 to data_bytes-1 loop
v_byte_address := address & std_ulogic_vector(to_unsigned(n, log2(data_bytes)));
if wmask(n) = '1' then
case v_byte_address is
when uart_rsel_tx => -- uart_rsel_dll
v_char := character'val(to_integer(unsigned(std_ulogic_vector2_row(datain, n))));
write(ofile, v_char);
when uart_rsel_dlm => -- uart_rsel_ier
when uart_rsel_fcr => -- uart_rsel_efr
when uart_rsel_lcr =>
when uart_rsel_mcr =>
when uart_rsel_scr =>
when others =>
end case;
end if;
end loop;
else
-- DEBUG
--write(tmpline, string'("reading address "));
--write(tmpline, address);
--write(tmpline, string'(" wmask "));
--write(tmpline, wmask);
--report tmpline.all;
--deallocate(tmpline);
-- END DEBUG
for n in 0 to data_bytes-1 loop
v_byte_address := address & std_ulogic_vector(to_unsigned(n, log2(data_bytes)));
-- DEBUG
--write(tmpline, string'("checking byte address "));
--write(tmpline, v_byte_address);
--report tmpline.all;
--deallocate(tmpline);
-- END DEBUG
if wmask(n) = '1' then
set_std_ulogic_vector2_row(v_r_next.dataout, n, (byte_bits-1 downto 0 => 'X'));
case v_byte_address is
when uart_rsel_rx =>
when uart_rsel_iir => -- uart_rsel_efr
when uart_rsel_lsr =>
set_std_ulogic_vector2_row(v_r_next.dataout, n, uart_lsr_temt or uart_lsr_thre);
-- DEBUG
--write(tmpline, string'("outputting "));
--write(tmpline, std_ulogic_vector2_row(v_r_next.dataout, n));
--report tmpline.all;
--deallocate(tmpline);
-- END DEBUG
when uart_rsel_msr =>
when uart_rsel_scr =>
when others =>
end case;
else
set_std_ulogic_vector2_row(v_r_next.dataout, n, (byte_bits-1 downto 0 => 'X'));
end if;
end loop;
end if;
end if;
r <= v_r_next;
end if;
end if;
end process;
end;
|
-- $Id: tb_tst_sram_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_sram_n4d
-- Description: Configuration for tb_tst_sram_n4d for tb_nexys4d_dram
--
-- Dependencies: sys_tst_sram_n4d
--
-- To test: sys_tst_sram_n4d
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2013-??-?? 534 - 0.29 13.1 O40d xc6slx16 ???
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_sram_n4d of tb_nexys4d_dram is
for sim
for all : nexys4d_dram_aif
use entity work.sys_tst_sram_n4d;
end for;
end for;
end tb_tst_sram_n4d;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity ROM is
port ( address : in natural;
data : out bit_vector(0 to 7);
enable : in bit );
begin
trace_reads : process (enable) is
begin
if enable = '1' then
report "ROM read at time " & time'image(now)
& " from address " & natural'image(address);
end if;
end process trace_reads;
end entity ROM;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity ROM is
port ( address : in natural;
data : out bit_vector(0 to 7);
enable : in bit );
begin
trace_reads : process (enable) is
begin
if enable = '1' then
report "ROM read at time " & time'image(now)
& " from address " & natural'image(address);
end if;
end process trace_reads;
end entity ROM;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity ROM is
port ( address : in natural;
data : out bit_vector(0 to 7);
enable : in bit );
begin
trace_reads : process (enable) is
begin
if enable = '1' then
report "ROM read at time " & time'image(now)
& " from address " & natural'image(address);
end if;
end process trace_reads;
end entity ROM;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
signal dataToCache : std_logic_vector(31 downto 0);
signal triggerCPFault : std_ulogic;
SIGNAL knockState : std_logic_vector ( 1 downto 0 );
SIGNAL catchAddress : std_logic_vector ( 31 downto 0 );
SIGNAL targetAddress : std_logic_vector ( 31 downto 0 );
SIGNAL knockAddress : std_logic_vector ( 31 downto 0 );
signal addressToCache : std_logic_vector(31 downto 0);
SIGNAL hackStateM1 : std_logic;
-- Signals used for tracking if a handler fired and which one
signal dfp_trap_vector : std_logic_vector(9 downto 0);
signal dfp_trap_mem : std_logic_vector(dfp_trap_vector'left downto dfp_trap_vector'right);
signal or_reduce_1 : std_logic;
signal dfp_delay_start : integer range 0 to 15;
signal handlerTrap : std_ulogic;
-- Signals that serve as shadow signals for variables used in the pairs
signal EX_EDATA2_shadow : WORD;
signal V_E_SU_shadow : STD_ULOGIC;
signal V_M_RESULT_shadow : WORD;
signal V_A_SU_shadow : STD_ULOGIC;
signal V_M_SU_shadow : STD_ULOGIC;
-- Intermediate value holding signal declarations
signal R_M_RESULT_intermed_3 : std_logic_vector(31 downto 0);
signal TARGETADDRESS_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_M_RESULT_intermed_4 : std_logic_vector(31 downto 0);
signal R_M_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_RESULT_intermed_2 : std_logic_vector(31 downto 0);
signal V_M_RESULT_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal RIN_M_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal EX_EDATA2_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_M_RESULT_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_2 : STD_ULOGIC;
signal V_A_SU_shadow_intermed_1 : STD_ULOGIC;
signal DCI_EDATA_intermed_5 : STD_LOGIC_VECTOR(31 downto 0);
signal DCI_EDATA_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal ADDRESSTOCACHE_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal R_A_SU_intermed_2 : STD_ULOGIC;
signal DCI_EDATA_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal TARGETADDRESS_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal TARGETADDRESS_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_SU_shadow_intermed_2 : STD_ULOGIC;
signal DATATOCACHE_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal R_E_SU_intermed_1 : STD_ULOGIC;
signal DCI_MADDRESS_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal V_M_RESULT_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal EX_EDATA2_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_3 : STD_ULOGIC;
signal DCI_EDATA_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
signal EX_EDATA2_shadow_intermed_5 : std_logic_vector(31 downto 0);
signal R_A_SU_intermed_1 : STD_ULOGIC;
signal KNOCKADDRESS_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal EX_EDATA2_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal EX_EDATA2_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal DCI_MADDRESS_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal DATATOCACHE_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_SU_intermed_1 : STD_ULOGIC;
signal RIN_E_SU_intermed_2 : STD_ULOGIC;
signal RIN_E_SU_intermed_1 : STD_ULOGIC;
signal RIN_M_RESULT_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_A_SU_intermed_2 : STD_ULOGIC;
signal DATATOCACHE_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal DCI_EDATA_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_SU_intermed_3 : STD_ULOGIC;
signal ADDRESSTOCACHE_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_M_RESULT_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal R_M_RESULT_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_M_SU_intermed_1 : STD_ULOGIC;
signal DCI_MADDRESS_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_SU_shadow_intermed_1 : STD_ULOGIC;
signal V_M_SU_shadow_intermed_1 : STD_ULOGIC;
signal DATATOCACHE_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp, handlerTrap)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap or handlerTrap;
v.x.nerror := rp.error;
if(handlerTrap = '1')then
xc_vectt := "00" & TT_WATCH;
elsif(triggerCPFault = '1')then
xc_vectt := "00" & TT_CPDIS;
xc_trap := '1';
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
if(r.m.result = catchAddress)then
dci.maddress <= targetAddress;
dci.msu <= '1';
dci.esu <= '1';
else
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
end if;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
-- Assignments to be moved with variables
-- These assignments must be moved to process COMB/
EX_EDATA2_shadow <= EX_EDATA2;
V_E_SU_shadow <= V.E.SU;
V_M_RESULT_shadow <= V.M.RESULT;
V_A_SU_shadow <= V.A.SU;
V_M_SU_shadow <= V.M.SU;
end process;
dfp_delay : process(clk) begin
if(clk'event and clk = '1')then
ADDRESSTOCACHE_intermed_1 <= ADDRESSTOCACHE;
ADDRESSTOCACHE_intermed_2 <= ADDRESSTOCACHE_intermed_1;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
EX_EDATA2_shadow_intermed_3 <= EX_EDATA2_shadow_intermed_2;
EX_EDATA2_shadow_intermed_4 <= EX_EDATA2_shadow_intermed_3;
EX_EDATA2_shadow_intermed_5 <= EX_EDATA2_shadow_intermed_4;
V_M_RESULT_shadow_intermed_1 <= V_M_RESULT_shadow;
V_M_RESULT_shadow_intermed_2 <= V_M_RESULT_shadow_intermed_1;
V_M_RESULT_shadow_intermed_3 <= V_M_RESULT_shadow_intermed_2;
V_M_RESULT_shadow_intermed_4 <= V_M_RESULT_shadow_intermed_3;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DATATOCACHE_intermed_2 <= DATATOCACHE_intermed_1;
DATATOCACHE_intermed_3 <= DATATOCACHE_intermed_2;
DATATOCACHE_intermed_4 <= DATATOCACHE_intermed_3;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
DCI_EDATA_intermed_3 <= DCI_EDATA_intermed_2;
DCI_EDATA_intermed_4 <= DCI_EDATA_intermed_3;
DCI_EDATA_intermed_5 <= DCI_EDATA_intermed_4;
DCI_MADDRESS_intermed_1 <= DCI.MADDRESS;
DCI_MADDRESS_intermed_2 <= DCI_MADDRESS_intermed_1;
DCI_MADDRESS_intermed_3 <= DCI_MADDRESS_intermed_2;
KNOCKADDRESS_intermed_1 <= KNOCKADDRESS;
RIN_M_RESULT_intermed_1 <= RIN.M.RESULT;
RIN_M_RESULT_intermed_2 <= RIN_M_RESULT_intermed_1;
RIN_M_RESULT_intermed_3 <= RIN_M_RESULT_intermed_2;
RIN_M_RESULT_intermed_4 <= RIN_M_RESULT_intermed_3;
R_M_RESULT_intermed_1 <= R.M.RESULT;
R_M_RESULT_intermed_2 <= R_M_RESULT_intermed_1;
R_M_RESULT_intermed_3 <= R_M_RESULT_intermed_2;
TARGETADDRESS_intermed_1 <= TARGETADDRESS;
TARGETADDRESS_intermed_2 <= TARGETADDRESS_intermed_1;
TARGETADDRESS_intermed_3 <= TARGETADDRESS_intermed_2;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
R_A_SU_intermed_1 <= R.A.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
RIN_E_SU_intermed_1 <= RIN.E.SU;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
V_M_RESULT_shadow_intermed_1 <= V_M_RESULT_shadow;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
RIN_M_RESULT_intermed_1 <= RIN.M.RESULT;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
V_A_SU_shadow_intermed_3 <= V_A_SU_shadow_intermed_2;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
V_E_SU_shadow_intermed_2 <= V_E_SU_shadow_intermed_1;
V_M_SU_shadow_intermed_1 <= V_M_SU_shadow;
R_A_SU_intermed_1 <= R.A.SU;
R_A_SU_intermed_2 <= R_A_SU_intermed_1;
R_E_SU_intermed_1 <= R.E.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
RIN_A_SU_intermed_3 <= RIN_A_SU_intermed_2;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_SU_intermed_2 <= RIN_E_SU_intermed_1;
RIN_M_SU_intermed_1 <= RIN.M.SU;
ADDRESSTOCACHE_intermed_1 <= ADDRESSTOCACHE;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
EX_EDATA2_shadow_intermed_3 <= EX_EDATA2_shadow_intermed_2;
EX_EDATA2_shadow_intermed_4 <= EX_EDATA2_shadow_intermed_3;
V_M_RESULT_shadow_intermed_1 <= V_M_RESULT_shadow;
V_M_RESULT_shadow_intermed_2 <= V_M_RESULT_shadow_intermed_1;
V_M_RESULT_shadow_intermed_3 <= V_M_RESULT_shadow_intermed_2;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DATATOCACHE_intermed_2 <= DATATOCACHE_intermed_1;
DATATOCACHE_intermed_3 <= DATATOCACHE_intermed_2;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
DCI_EDATA_intermed_3 <= DCI_EDATA_intermed_2;
DCI_EDATA_intermed_4 <= DCI_EDATA_intermed_3;
DCI_MADDRESS_intermed_1 <= DCI.MADDRESS;
DCI_MADDRESS_intermed_2 <= DCI_MADDRESS_intermed_1;
RIN_M_RESULT_intermed_1 <= RIN.M.RESULT;
RIN_M_RESULT_intermed_2 <= RIN_M_RESULT_intermed_1;
RIN_M_RESULT_intermed_3 <= RIN_M_RESULT_intermed_2;
R_M_RESULT_intermed_1 <= R.M.RESULT;
R_M_RESULT_intermed_2 <= R_M_RESULT_intermed_1;
TARGETADDRESS_intermed_1 <= TARGETADDRESS;
TARGETADDRESS_intermed_2 <= TARGETADDRESS_intermed_1;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
end if;
end process;
dfp_trap_vector(0) <= '1' when (TRIGGERCPFAULT /= '0') else '0';
dfp_trap_vector(1) <= '1' when (HACKSTATEM1 /= '0') else '0';
dfp_trap_vector(2) <= '1' when (CATCHADDRESS /= X"00000000") else '0';
dfp_trap_vector(3) <= '1' when (CATCHADDRESS /= KNOCKADDRESS_intermed_1) else '0';
dfp_trap_vector(4) <= '1' when (CATCHADDRESS /= TARGETADDRESS_intermed_3) else '0';
dfp_trap_vector(5) <= '1' when (DCI.MADDRESS /= R.M.RESULT) else '0';
dfp_trap_vector(6) <= '1' when (KNOCKADDRESS /= X"00000000") else '0';
dfp_trap_vector(7) <= '1' when (KNOCKADDRESS /= TARGETADDRESS_intermed_2) else '0';
dfp_trap_vector(8) <= '1' when (KNOCKSTATE /= "00") else '0';
dfp_trap_vector(9) <= '1' when (TARGETADDRESS /= X"00000000") else '0';
dfp_or_reduce : process(dfp_trap_vector)
variable or_reduce_5 : std_logic_vector(4 downto 0);
variable or_reduce_3 : std_logic_vector(2 downto 0);
variable or_reduce_2 : std_logic_vector(1 downto 0);
begin
or_reduce_5 := dfp_trap_vector(9 downto 5) OR dfp_trap_vector(4 downto 0);
or_reduce_3 := or_reduce_5(4 downto 2) OR ("0" & or_reduce_5(1 downto 0));
or_reduce_2 := or_reduce_3(2 downto 1) OR ("0" & or_reduce_3(0 downto 0));
or_reduce_1 <= or_reduce_2(0) OR or_reduce_2(1);
end process;
trap_enable_delay : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_delay_start <= 15;
elsif(dfp_delay_start /= 0)then
dfp_delay_start <= dfp_delay_start - 1;
end if;
end if;
end process;
trap_mem : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_trap_mem <= (others => '0');
elsif(dfp_delay_start = 0)then
dfp_trap_mem <= dfp_trap_mem OR dfp_trap_vector;
end if;
end if;
end process;
handlerTrap <= or_reduce_1 when (dfp_delay_start = 0) else '0';
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
hackStateM1 <= '0';
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
else
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80082000" ) THEN
hackStateM1 <= '1';
END IF;
IF ( hackStateM1 = '1' and r.d.inst ( conv_integer ( r.d.set ) ) = X"80102000" ) THEN
r.w.s.s <= '1';
END IF;
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
shadow_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
triggerCPFault <= '0';
IF(dci.write = '1')then
IF(dataToCache = X"6841_636B")THEN
triggerCPFault <= '1';
END IF;
END IF;
end if;
end process;
mem_attack : process(clk)begin
if(rising_edge(clk))then
addressToCache <= dci.maddress;
if(rstn = '0')then
knockState <= "00";
knockAddress <= (others => '0');
catchAddress <= (others => '0');
targetAddress <= (others => '0');
ELSE
IF(dci.write = '1')then
IF(dataToCache = X"AAAA_5555")THEN
knockState <= "01";
knockAddress <= addressToCache;
ELSIF(knockState = "01" and addressToCache = knockAddress and dataToCache = X"5555_AAAA")THEN
knockState <= "10";
ELSIF(knockState = "10" and addressToCache = knockAddress and dataToCache = X"CA5C_CA5C")THEN
knockState <= "11";
ELSIF(knockState = "11" and addressToCache = knockAddress)THEN
targetAddress <= dataToCache;
catchAddress <= knockAddress;
knockState <= "00";
END IF;
END IF;
END IF;
end if;
end process;
end;
|
-------------------------------------------------------------------------------
--! @file onewire_interface.vhd
--! @author Johannes Walter <johannes@greenshire.io>
--! @copyright LGPL v2.1
--! @brief 1-wire bus interface.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.lfsr_pkg.all;
--! @brief Entity declaration of onewire_interface
entity onewire_interface is
generic (
--! System clock frequency in Hz
clk_frequency_g : natural := 40e6);
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Internal signals
--! @{
--! Send a bus reset command
bus_rst_i : in std_ulogic;
--! Send data bit
send_i : in std_ulogic;
--! The data bit to be sent
data_i : in std_ulogic;
--! Receive data bit
recv_i : in std_ulogic;
--! The received data bit
data_o : out std_ulogic;
--! The received data bit enable
data_en_o : out std_ulogic;
--! Done flag
done_o : out std_ulogic;
--! @}
--! @name External signals
--! @{
--! Receiving bus input
rx_i : in std_ulogic;
--! Transmitting bus output
tx_o : out std_ulogic);
--! @}
end entity onewire_interface;
--! RTL implementation of onewire_interface
architecture rtl of onewire_interface is
-----------------------------------------------------------------------------
--! @name Types and Constants
-----------------------------------------------------------------------------
--! @{
--! Time to start a read or write operation in seconds
constant t_rw_start_c : real := 0.000005;
--! Time to wait until input is sampled during a read operation in seconds
constant t_rw_smpl_c : real := 0.000010;
--! Time to hold the state during a write operation or wait during a read operation in seconds
constant t_rw_hold_c : real := 0.00006;
--! Time to recover from a read or write operation in seconds
constant t_rw_recvr_c : real := t_rw_hold_c + 0.00001;
--! Time to start a reset command in seconds
constant t_rst_start_c : real := 0.0005;
--! Time to wait until presence pulse is sampled in seconds
constant t_rst_smpl_c : real := 0.00057;
--! Total length of reset command in seconds
constant t_rst_end_c : real := 0.001;
constant clk_period_c : real := 1.0 / real(clk_frequency_g);
constant cnt_rw_start_c : natural := natural(ceil(t_rw_start_c / clk_period_c));
constant cnt_rw_recvr_c : natural := natural(ceil(t_rw_recvr_c / clk_period_c));
constant cnt_rw_hold_c : natural := natural(ceil(t_rw_hold_c / clk_period_c));
constant cnt_rw_smpl_c : natural := natural(ceil(t_rw_smpl_c / clk_period_c));
constant cnt_rst_start_c : natural := natural(ceil(t_rst_start_c / clk_period_c));
constant cnt_rst_smpl_c : natural := natural(ceil(t_rst_smpl_c / clk_period_c));
constant cnt_rst_end_c : natural := natural(ceil(t_rst_end_c / clk_period_c));
constant lfsr_len_c : natural := lfsr_length(cnt_rst_end_c);
subtype lfsr_t is std_ulogic_vector(lfsr_len_c - 1 downto 0);
constant lfsr_seed_c : lfsr_t := lfsr_seed(lfsr_len_c);
constant max_rw_start_c : lfsr_t := x"CC73"; --lfsr_shift(lfsr_seed_c, cnt_rw_start_c - 1);
constant max_rw_recvr_c : lfsr_t := x"6EA4"; --lfsr_shift(lfsr_seed_c, cnt_rw_recvr_c - 1);
constant max_rw_hold_c : lfsr_t := x"EE75"; --lfsr_shift(lfsr_seed_c, cnt_rw_hold_c - 1);
constant max_rw_smpl_c : lfsr_t := x"8C97"; --lfsr_shift(lfsr_seed_c, cnt_rw_smpl_c - 1);
constant max_rst_start_c : lfsr_t := x"FD03"; --lfsr_shift(lfsr_seed_c, cnt_rst_start_c - 1);
constant max_rst_smpl_c : lfsr_t := x"672B"; --lfsr_shift(lfsr_seed_c, cnt_rst_smpl_c - 1);
constant max_rst_end_c : lfsr_t := x"0170"; --lfsr_shift(lfsr_seed_c, cnt_rst_end_c - 1);
type state_t is (IDLE, RESET, SEND, RECEIVE);
type reg_t is record
state : state_t;
lfsr : lfsr_t;
tx : std_ulogic;
done : std_ulogic;
data : std_ulogic;
data_en : std_ulogic;
end record;
constant init_c : reg_t := (
state => IDLE,
lfsr => lfsr_seed_c,
tx => '1',
done => '0',
data => '0',
data_en => '0');
--! @}
-----------------------------------------------------------------------------
--! @name Internal Registers
-----------------------------------------------------------------------------
--! @{
signal reg : reg_t;
--! @}
-----------------------------------------------------------------------------
--! @name Internal Wires
-----------------------------------------------------------------------------
--! @{
signal nxt_reg : reg_t;
--! @}
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
data_o <= reg.data;
data_en_o <= reg.data_en;
done_o <= reg.done;
tx_o <= reg.tx;
-----------------------------------------------------------------------------
-- Registers
-----------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= nxt_reg;
end if;
end if;
end process regs;
-----------------------------------------------------------------------------
-- Combinatorics
-----------------------------------------------------------------------------
comb : process (reg, bus_rst_i, send_i, recv_i, data_i, rx_i) is
begin -- process comb
-- Defaults
nxt_reg <= reg;
nxt_reg.done <= init_c.done;
nxt_reg.data_en <= init_c.data_en;
case reg.state is
when IDLE =>
if bus_rst_i = '1' then
nxt_reg.state <= RESET;
nxt_reg.tx <= '0';
elsif send_i = '1' then
nxt_reg.state <= SEND;
nxt_reg.tx <= '0';
nxt_reg.data <= data_i;
elsif recv_i = '1' then
nxt_reg.state <= RECEIVE;
nxt_reg.tx <= '0';
end if;
when RESET =>
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
if reg.lfsr = max_rst_start_c then
nxt_reg.tx <= '1';
end if;
if reg.lfsr = max_rst_smpl_c then
nxt_reg.data <= rx_i;
end if;
if reg.lfsr = max_rst_end_c then
nxt_reg <= init_c;
nxt_reg.done <= '1';
nxt_reg.data <= reg.data;
end if;
when SEND =>
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
if reg.lfsr = max_rw_start_c then
nxt_reg.tx <= reg.data;
end if;
if reg.lfsr = max_rw_hold_c then
nxt_reg.tx <= '1';
end if;
if reg.lfsr = max_rw_recvr_c then
nxt_reg <= init_c;
nxt_reg.done <= '1';
end if;
when RECEIVE =>
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
if reg.lfsr = max_rw_start_c then
nxt_reg.tx <= '1';
end if;
if reg.lfsr = max_rw_smpl_c then
nxt_reg.data <= rx_i;
end if;
if reg.lfsr = max_rw_recvr_c then
nxt_reg <= init_c;
nxt_reg.done <= '1';
nxt_reg.data <= reg.data;
nxt_reg.data_en <= '1';
end if;
end case;
end process comb;
end architecture rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:38:15 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_zed_vga_0_0 -prefix
-- system_zed_vga_0_0_ system_zed_vga_0_0_stub.vhdl
-- Design : system_zed_vga_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_zed_vga_0_0 is
Port (
rgb565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end system_zed_vga_0_0;
architecture stub of system_zed_vga_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rgb565[15:0],vga_r[3:0],vga_g[3:0],vga_b[3:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "zed_vga,Vivado 2016.4";
begin
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: scanregi, scanrego, scanregio
-- File: scanreg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Technology wrapper for boundary scan registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanregi is
generic (
tech : integer := 0;
intesten: integer := 1
);
port (
pad : in std_ulogic;
core : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupd : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic
);
end;
architecture tmap of scanregi is
signal d1, d2, q1, q2, m3i, o1o : std_ulogic;
begin
gen0: if tech = 0 generate
x: scanregi_inf generic map (intesten) port map (pad,core,tck,tckn,tdi,tdo,bsshft,bscapt,bsupd,bsdrive,bshighz);
end generate;
map0: if tech /= 0 generate
iten: if intesten /= 0 generate
m1 : grmux2 generic map (tech) port map (pad, q1, bsdrive, core);
f1 : grdff generic map (tech) port map (tckn, d1, q1);
m2 : grmux2 generic map (tech) port map (q1, q2, bsupd, d1);
end generate;
itdis: if intesten = 0 generate
core <= pad;
q1 <= '0';
d1 <= '0';
end generate;
m3 : grmux2 generic map (tech) port map (m3i, tdi, bsshft, d2);
m4 : grmux2 generic map (tech) port map (q2, o1o, bscapt, m3i);
o1 : gror2 generic map (tech) port map (pad, bshighz, o1o);
f2 : grdff generic map (tech) port map (tck, d2, q2);
tdo <= q2;
end generate;
end;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanrego is
generic (
tech : integer := 0
);
port (
pad : out std_ulogic;
core : in std_ulogic;
samp : in std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupd : in std_ulogic;
bsdrive : in std_ulogic
);
end;
architecture tmap of scanrego is
signal d1, d2, q1, q2, m3i, o1o : std_ulogic;
begin
gen0: if tech = 0 generate
x: scanrego_inf port map (pad,core,samp,tck,tckn,tdi,tdo,bsshft,bscapt,bsupd,bsdrive);
end generate;
map0: if tech /= 0 generate
m1 : grmux2 generic map (tech) port map (core, q1, bsdrive, pad);
m2 : grmux2 generic map (tech) port map (q1, q2, bsupd, d1);
m3 : grmux2 generic map (tech) port map (m3i, tdi, bsshft, d2);
m4 : grmux2 generic map (tech) port map (q2, samp, bscapt, m3i);
f1 : grdff generic map (tech) port map (tckn, d1, q1);
f2 : grdff generic map (tech) port map (tck, d2, q2);
tdo <= q2;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanregto is
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1;
scantest: integer range 0 to 1 := 0
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
samp : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapto : in std_ulogic;
bscaptoe: in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic
);
end;
architecture tmap of scanregto is
signal tdo1, padoenx,padoenxx : std_ulogic;
begin
x1: scanrego generic map (tech)
port map (pado, coreo, samp, tck, tckn, tdo1, tdo, bsshft, bscapto, bsupdo, bsdrive);
x2: scanrego generic map (tech)
port map (padoenx, coreoen, coreoen, tck, tckn, tdi, tdo1, bsshft, bscaptoe, bsupdo, bsdrive);
hz : if hzsup = 1 generate
x3 : if oepol = 0 generate
x33 : gror2 generic map (tech) port map (padoenx, bshighz, padoenxx);
end generate;
x4 : if oepol = 1 generate
x33 : grand12 generic map (tech) port map (padoenx, bshighz, padoenxx);
end generate;
end generate;
nohz : if hzsup = 0 generate
padoenxx <= padoenx;
end generate;
oem: if scantest /= 0 generate
x4: grmux2 generic map (tech) port map (padoenxx, testoen, testen, padoen);
end generate;
nooem: if scantest = 0 generate
padoen <= padoenxx;
end generate;
end;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanregio is
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1;
intesten: integer range 0 to 1 := 1;
scantest: integer range 0 to 1 := 0
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
padi : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
corei : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapti : in std_ulogic;
bscapto : in std_ulogic;
bscaptoe: in std_ulogic;
bsupdi : in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic
);
end;
architecture tmap of scanregio is
signal tdo1, tdo2, padoenx : std_ulogic;
begin
gen0: if tech = 0 generate
x: scanregio_inf
generic map (hzsup,intesten)
port map (pado,padoen,padi,coreo,coreoen,corei,tck,tckn,tdi,tdo,
bsshft,bscapti,bsupdi,bsupdo,bsdrive,bshighz);
end generate;
map0: if tech /= 0 generate
x0: scanregi generic map (tech,intesten)
port map (padi, corei, tck, tckn, tdo1, tdo, bsshft, bscapti, bsupdi, bsdrive, bshighz);
x1: scanregto generic map (tech, hzsup, oepol, scantest)
port map (pado, padoen, coreo, coreo, coreoen,
tck, tckn, tdi, tdo1, bsshft, bscapto, bscaptoe, bsupdo, bsdrive, bshighz, testen, testoen);
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use work.aua_types.all;
entity aua_tb is
end aua_tb;
architecture aua_test of aua_tb is
component aua
port (
clk_in : in std_logic;
reset_pin : in std_logic;
switch_pins : in std_logic_vector(15 downto 0);
led_pins : out std_logic_vector(15 downto 0);
digit0_pins : out std_logic_vector(6 downto 0);
digit1_pins : out std_logic_vector(6 downto 0);
digit2_pins : out std_logic_vector(6 downto 0);
digit3_pins : out std_logic_vector(6 downto 0);
digit4_pins : out std_logic_vector(6 downto 0);
digit5_pins : out std_logic_vector(6 downto 0);
sram_addr : out std_logic_vector(RAM_ADDR_SIZE-1 downto 0);
sram_dq : inout word_t;
sram_we : out std_logic;
-- sram_oe : out std_logic;
sram_ub : out std_logic;
sram_lb : out std_logic;
-- sram_ce : out std_logic
txd : out std_logic;
rxd : in std_ulogic
--~ ncts : in std_logic;
--~ nrts : out std_logic
);
end component;
signal clk : std_logic;
signal reset_pin : std_logic;
signal switch_pins : std_logic_vector(15 downto 0);
signal led_pins : std_logic_vector(15 downto 0);
signal digit0_pins : std_logic_vector(6 downto 0);
signal digit1_pins : std_logic_vector(6 downto 0);
signal digit2_pins : std_logic_vector(6 downto 0);
signal digit3_pins : std_logic_vector(6 downto 0);
signal digit4_pins : std_logic_vector(6 downto 0);
signal digit5_pins : std_logic_vector(6 downto 0);
signal sram_addr : std_logic_vector(RAM_ADDR_SIZE-1 downto 0);
signal sram_dq : word_t;
signal sram_we : std_logic;
signal sram_ub : std_logic;
signal sram_lb : std_logic;
signal txd : std_logic;
signal rxd : std_logic;
constant freq: natural := 70000000;
constant clk_tick: natural := 1000000000/freq;
constant uart_baud: natural := 115200;
constant uart_clks: natural := freq/uart_baud;
begin
uart: process
procedure icwait(cycles : natural) is
begin
for i in 1 to cycles loop
wait until clk = '0' and clk'event;
end loop;
end;
begin
rxd <= '0';
icwait(uart_clks*2);
rxd <= '1';
icwait(uart_clks);
rxd <= '0';
icwait(uart_clks*2);
rxd <= '1';
icwait(uart_clks*2);
rxd <= '0';
icwait(uart_clks*2);
rxd <= '1';
icwait(uart_clks*2);
end process;
aua1: configuration work.aua_cache
port map (
clk_in => clk,
reset_pin => reset_pin,
switch_pins => switch_pins,
led_pins => led_pins,
digit0_pins => digit0_pins,
digit1_pins => digit1_pins,
digit2_pins => digit2_pins,
digit3_pins => digit3_pins,
digit4_pins => digit4_pins,
digit5_pins => digit5_pins,
sram_addr => sram_addr,
sram_dq => sram_dq,
sram_we => sram_we,
sram_ub => sram_ub,
sram_lb => sram_lb,
txd => txd,
rxd => rxd
);
CLKGEN: process
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process CLKGEN;
TEST: process
procedure icwait(cycles : natural) is
begin
for i in 1 to cycles loop
wait until clk = '0' and clk'event;
end loop;
end;
begin
reset_pin <= '0';
switch_pins <= x"ffff";
sram_dq <= (others => '0');
--~ rxd <= '0';
icwait(2);
reset_pin <= '1';
icwait(9000);
assert false report "sim finish" SEVERITY failure;
end process TEST;
end aua_test;
|
-------------------------------------------------------------------------------
--! @file openhub-rtl-ea.vhd
--
--! @brief OpenHUB
--
--! @details This is the openHUB using RMII Rx and Tx lines.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
--! use openmac package
use work.openmacPkg.all;
entity openhub is
generic (
--! Number of ports
gPortCount : integer := 3
);
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII receive paths
iRx : in tRmiiPathArray(gPortCount downto 1);
--! RMII transmit paths
oTx : out tRmiiPathArray(gPortCount downto 1);
--! Determine number of internal port (to MAC)
iIntPort : in integer range 1 to gPortCount := 1;
--! Transmit mask to enable ports
iTxMask : in std_logic_vector(gPortCount downto 1) := (others => cActivated);
--! Gives the number of the currectly receiving port
oRxPort : out integer range 0 to gPortCount
);
end entity openhub;
architecture rtl of openhub is
--! All ports inactive constant
constant cPortsAreInactive : std_logic_vector(gPortCount downto 0) := (others => cInactivated);
--! Receive path array
signal rxPath : tRmiiPathArray(gPortCount downto 0);
--! Receive path array delayed by one cycle
signal rxPath_l : tRmiiPathArray(gPortCount downto 0);
--! Transmit path array
signal txPath : tRmiiPathArray(gPortCount downto 0);
--! Stored transmit mask (is taken from iTxMask when to packet transfer is in progress)
signal txMask_reg : std_logic_vector(gPortCount downto 1);
begin
rxPath <= iRx & cRmiiPathInit;
oTx <= txPath(oTx'range);
do: process (iRst, iClk)
variable vActive : boolean;
variable vMaster : integer range 0 to gPortCount;
variable vMasterAtCollision : integer range 0 to gPortCount;
variable vCollision : boolean;
variable vRxDvm : std_logic_vector(gPortCount downto 0);
begin
if iRst = cActivated then
rxPath_l <= (others => cRmiiPathInit);
txPath <= (others => cRmiiPathInit);
vActive := false;
vMaster := 0;
vMasterAtCollision := 0;
vCollision := false;
txMask_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
rxPath_l <= rxPath;
if vActive = false then
if rmiiGetEnable(rxPath_l) /= cPortsAreInactive then
for i in 1 to gPortCount loop
if (rxPath_l(i).enable = cActivated and
(rxPath_l(i).data(0) = cActivated or rxPath_l(i).data(1) = cActivated)) then
vMaster := i;
vActive := true;
exit;
end if;
end loop;
end if;
else
if rxPath_l(vMaster).enable = cInactivated and rxPath(vMaster).enable = cInactivated then
vMaster := 0;
end if;
if rmiiGetEnable(rxPath_l) = cPortsAreInactive and rmiiGetEnable(rxPath) = cPortsAreInactive then
vActive := false;
end if;
end if;
if vMaster = 0 then
txPath <= (others => cRmiiPathInit);
-- overtake new iTxMask only, when there is no active frame.
txMask_reg <= iTxMask;
else
for i in 1 to gPortCount loop -- output received frame to every port
if i /= vMaster then -- but not to the port where it is coming from - "eh kloar!"
-- only send data to active ports (=> iTxMask is set to cActivated) or the internal port (mac)
if txMask_reg(i) = cActivated or vMaster = iIntPort then
txPath(i).enable <= cActivated;
txPath(i).data <= rxPath_l(vMaster).data;
end if;
-- if there is a frame received and another is sent => collision!
if rxPath_l(i).enable = cActivated then
vCollision := true;
vMasterAtCollision := vMaster;
end if;
end if;
end loop;
end if;
if vCollision = true then
txPath(vMasterAtCollision).enable <= cActivated;
txPath(vMasterAtCollision).data <= "01";
vRxDvm := rmiiGetEnable(rxPath_l);
vRxDvm(vMasterAtCollision) := cInactivated;
if vRxDvm = cPortsAreInactive then
txPath(vMasterAtCollision) <= cRmiiPathInit;
vCollision := false;
vMasterAtCollision := 0;
end if;
end if;
-- output the master port - identifies the port (1...n) which has received the packet.
-- if master is 0, the hub is inactive.
oRxPort <= vMaster;
end if;
end process do;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spax
-- File: ddr2spax.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: DDR2 memory controller with asynch AHB interface
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
library techmap;
use techmap.gencomp.ddr2phy_has_datavalid;
use techmap.gencomp.ddr2phy_ptctrl;
entity ddr2spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
-- dqsgating : integer := 0;
nosync : integer := 0;
dqsgating : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
hwidth : in std_ulogic
);
end ddr2spax;
architecture rtl of ddr2spax is
constant REVISION : integer := 1;
constant ramwt: integer := 0;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
function pick(choice: boolean; t,f: integer) return integer is
begin
if choice then return t; else return f; end if;
end;
constant xahbw: integer := pick(ft/=0 and ahbbits<64, 64, ahbbits);
constant l2ahbw: integer := log2(xahbw);
-- For non-FT, write buffer has room for two write bursts and is addressable
-- down to 32-bit level on write (AHB) side.
-- For FT, the write buffer has room for one write burst and is addressable
-- down to 64-bit level on write side.
-- Write buffer dimensions
constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw;
constant wbuf_rabits_r: integer := wbuf_rabits_s-FT;
constant wbuf_rdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits);
constant wbuf_wabits: integer := pick(ft/=0, l2blen-6, 1+l2blen-5);
constant wbuf_wdbits: integer := pick(ft/=0, xahbw+xahbw/2, xahbw);
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw;
constant rbuf_rdbits: integer := wbuf_wdbits;
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits);
signal request : ddr_request_type;
signal start_tog : std_logic;
signal response : ddr_response_type;
signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0);
signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0);
signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0);
signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0);
signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0);
signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0);
signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0);
signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0);
signal wbwrite,wbwritebig,rbwrite: std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of rbwdata : signal is true;
attribute syn_keep of rbwdata : signal is true;
attribute syn_preserve of rbwdata : signal is true;
signal vcc: std_ulogic;
signal sdox: ddrctrl_out_type;
signal ce: std_logic;
begin
vcc <= '1';
gft0: if ft=0 generate
ahbc : ddr2spax_ahb
generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
nosync => nosync, burstlen => burstlen, ahbbits => xahbw, revision => revision,
ddrbits => ddrbits, regarea => 0)
port map (ahb_rst, clk_ahb, ahbsi, ahbso, request, start_tog, response,
wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, hwidth, FTFE_BEID_DDR2);
ce <= '0';
end generate;
gft1: if ft/=0 generate
ftc: ft_ddr2spax_ahb
generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
nosync => nosync, burstlen => burstlen, ahbbits => xahbw, bufbits => xahbw+xahbw/2,
ddrbits => ddrbits, hwidthen => hwidthen, devid => GAISLER_DDR2SP, revision => revision)
port map (ahb_rst, clk_ahb, ahbsi, ahbso, ce, request, start_tog, response,
wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, hwidth, '0', open, open, FTFE_BEID_DDR2);
end generate;
ddrc : ddr2spax_ddr
generic map (ddrbits => ddrbits,
pwron => pwron, MHz => MHz, TRFC => TRFC, col => col, Mbyte => Mbyte,
readdly => readdly, odten => odten, octen => octen, dqsgating => dqsgating,
nosync => nosync, eightbanks => eightbanks, dqsse => dqsse, burstlen => burstlen,
chkbits => ft*ddrbits/2, bigmem => bigmem, raspipe => raspipe,
hwidthen => hwidthen, phytech => phytech, hasdqvalid => ddr2phy_has_datavalid(phytech),
rstdel => rstdel, phyptctrl => ddr2phy_ptctrl(phytech), scantest => scantest,
ddr_syncrst => ddr_syncrst)
port map (ddr_rst, clk_ddr, request, start_tog, response, sdi, sdox,
wbraddr, wbrdata, rbwaddr, rbwdata, rbwrite, hwidth,
'0', ddr_request_none, open, ahbsi.testen, ahbsi.testrst, ahbsi.testoen);
sdoproc: process(sdox,ce)
variable o: ddrctrl_out_type;
begin
o := sdox;
o.ce := ce;
sdo <= o;
end process;
wbuf: ddr2buf
generic map (tech => memtech, wabits => wbuf_wabits, wdbits => wbuf_wdbits,
rabits => wbuf_rabits_r, rdbits => wbuf_rdbits,
sepclk => 1, wrfst => ramwt)
port map ( rclk => clk_ddr, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0),
dataout => wbrdata, wclk => clk_ahb, write => wbwrite,
writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata);
rbuf: ddr2buf
generic map (tech => memtech, wabits => rbuf_wabits, wdbits => rbuf_wdbits,
rabits => rbuf_rabits, rdbits => rbuf_rdbits,
sepclk => 1, wrfst => ramwt)
port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr,
dataout => rbrdata,
wclk => clk_ddr, write => rbwrite,
writebig => '0', waddress => rbwaddr, datain => rbwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddr2spa: DDR2 controller rev " &
tost(REVISION) & ", " & tost(ddrbits) & " bit width, " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkgen_actel
-- File: clkgen_actel.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Clock generator for Actel fpga
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library axcelerator;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_axcelerator is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture struct of clkgen_axcelerator is
component hclkbuf
port( pad : in std_logic; y : out std_logic); end component;
component hclkbuf_pci
port( pad : in std_logic; y : out std_logic); end component;
signal clkint, pciclkint : std_ulogic;
begin
c0 : if (PCIEN = 0) or (PCISYSCLK=0) generate
u0 : hclkbuf port map (pad => clkin, y => clkint);
clk <= clkint;
clkn <= not clkint;
end generate;
c2 : if PCIEN/=0 generate
c1 : if PCISYSCLK=1 generate
clk <= pciclkint;
clkn <= not pciclkint;
end generate;
u0 : hclkbuf_pci port map (pad => pciclkin, y => pciclkint);
pciclk <= pciclkint;
end generate;
cgo.pcilock <= '1';
cgo.clklock <= '1';
sdclk <= '0';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_axcelerator" & ": using HCLKBUF as clock buffer");
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkgen_actel
-- File: clkgen_actel.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Clock generator for Actel fpga
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library axcelerator;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_axcelerator is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture struct of clkgen_axcelerator is
component hclkbuf
port( pad : in std_logic; y : out std_logic); end component;
component hclkbuf_pci
port( pad : in std_logic; y : out std_logic); end component;
signal clkint, pciclkint : std_ulogic;
begin
c0 : if (PCIEN = 0) or (PCISYSCLK=0) generate
u0 : hclkbuf port map (pad => clkin, y => clkint);
clk <= clkint;
clkn <= not clkint;
end generate;
c2 : if PCIEN/=0 generate
c1 : if PCISYSCLK=1 generate
clk <= pciclkint;
clkn <= not pciclkint;
end generate;
u0 : hclkbuf_pci port map (pad => pciclkin, y => pciclkint);
pciclk <= pciclkint;
end generate;
cgo.pcilock <= '1';
cgo.clklock <= '1';
sdclk <= '0';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_axcelerator" & ": using HCLKBUF as clock buffer");
-- pragma translate_on
end;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneii_atom_pack.all;
package cycloneii_components is
--
-- cycloneii_ram_block
--
COMPONENT cycloneii_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneii_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneii_jtag
--
COMPONENT cycloneii_jtag
generic (
lpm_type : string := "cycloneii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- cycloneii_crcblock
--
COMPONENT cycloneii_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneii_asmiblock
--
COMPONENT cycloneii_asmiblock
generic (
lpm_type : string := "cycloneii_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
END COMPONENT;
--
-- cycloneii_pll
--
COMPONENT cycloneii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "manual";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneii_pll";
family_name : string := "CycloneII";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
testclearlock : in std_logic := '0';
sbdin : in std_logic := '0';
clk : out std_logic_vector(2 downto 0);
locked : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
sbdout : out std_logic
);
END COMPONENT;
--
-- cycloneii_routing_wire
--
COMPONENT cycloneii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- cycloneii_lcell_ff
--
COMPONENT cycloneii_lcell_ff
generic (
x_on_violation : string := "on";
lpm_type : string := "cycloneii_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_sdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_sdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
sdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
END COMPONENT;
--
-- cycloneii_lcell_comb
--
COMPONENT cycloneii_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
lpm_type : string := "cycloneii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
END COMPONENT;
--
-- cycloneii_io
--
COMPONENT cycloneii_io
generic (
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
use_differential_input : string := "false";
lpm_type : string := "cycloneii_io";
input_power_up : string := "low");
port (
datain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '1';
linkin : in std_logic := '0';
differentialin : in std_logic := '0';
differentialout : out std_logic;
linkout : out std_logic;
combout : out std_logic;
regout : out std_logic;
padio : inout std_logic
);
END COMPONENT;
--
-- cycloneii_clk_delay_ctrl
--
COMPONENT cycloneii_clk_delay_ctrl
generic (
behavioral_sim_delay : integer := 0;
delay_chain : STRING := "54";
delay_chain_mode : STRING := "static";
uses_calibration : STRING := "false";
use_new_style_dq_detection : STRING := "false";
tan_delay_under_delay_ctrl_signal : STRING := "unused";
delay_ctrl_sim_delay_15_0 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_31_16 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_47_32 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_63_48 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
lpm_type : STRING := "cycloneii_clk_delay_ctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
tpd_disablecalibration_clkout : VitalDelayType01 := DefPropDelay01;
tpd_pllcalibrateclkdelayedin_clkout : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_disablecalibration : VitalDelayType01 := DefPropDelay01;
tipd_pllcalibrateclkdelayedin : VitalDelayType01 := DefPropDelay01
);
port (
clk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
disablecalibration : in std_logic := '1';
pllcalibrateclkdelayedin: in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
clkout : out std_logic
);
END COMPONENT;
--
-- cycloneii_clk_delay_cal_ctrl
--
COMPONENT cycloneii_clk_delay_cal_ctrl
generic (
delay_ctrl_sim_delay_15_0 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_31_16 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_47_32 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_63_48 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
lpm_type : STRING := "cycloneii_clk_delay_cal_ctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_plldataclk_calibratedata : VitalDelayType01 := DefPropDelay01;
tpd_disablecalibration_calibratedata : VitalDelayType01 := DefPropDelay01;
tpd_pllcalibrateclk_pllcalibrateclkdelayedout : VitalDelayType01 := DefPropDelay01;
tpd_disablecalibration_pllcalibrateclkdelayedout : VitalDelayType01 := DefPropDelay01;
tipd_plldataclk : VitalDelayType01 := DefPropDelay01;
tipd_pllcalibrateclk : VitalDelayType01 := DefPropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_disablecalibration : VitalDelayType01 := DefPropDelay01
);
port (
plldataclk : in std_logic := '0';
pllcalibrateclk : in std_logic := '0';
disablecalibration : in std_logic := '1';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
calibratedata : out std_logic;
pllcalibrateclkdelayedout : out std_logic
);
END COMPONENT;
--
-- cycloneii_mac_mult
--
COMPONENT cycloneii_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneii_mac_out
--
COMPONENT cycloneii_mac_out
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneii_clkctrl
--
COMPONENT cycloneii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
end cycloneii_components;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity MicroProcessor is
port(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
stop : out std_logic
);
end MicroProcessor;
architecture MicroProcessor_Behavioural of MicroProcessor is
component MicroROM is
port(
read_enable : in std_logic;
address : in std_logic_vector(7 downto 0);
data_output : out std_logic_vector(27 downto 0)
);
end component;
component MRAM is
port(
clk : in std_logic;
read_write : in std_logic;
read_address_1 : in std_logic_vector(7 downto 0);
read_address_2 : in std_logic_vector(7 downto 0);
write_address : in std_logic_vector(7 downto 0);
read_data_port_1 : out std_logic_vector(7 downto 0);
read_data_port_2 : out std_logic_vector(7 downto 0);
write_data_port : in std_logic_vector(7 downto 0)
);
end component;
component Datapath is
port(
enabled : in std_logic;
operation_code : in std_logic_vector(3 downto 0);
operand_1 : in std_logic_vector(7 downto 0);
operand_2 : in std_logic_vector(7 downto 0);
result : out std_logic_vector(7 downto 0);
zero_flag : out std_logic;
significant_bit_flag : out std_logic
);
end component;
component Controller is
port(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
stop : out std_logic;
rom_enabled : out std_logic;
rom_address : out std_logic_vector(7 downto 0);
rom_data_output : in std_logic_vector(27 downto 0);
ram_read_write : out std_logic;
ram_write_data_port : out std_logic_vector(7 downto 0);
ram_write_address : out std_logic_vector(7 downto 0);
ram_read_data_port_1 : in std_logic_vector(7 downto 0);
ram_read_data_port_2 : in std_logic_vector(7 downto 0);
ram_read_address_1 : out std_logic_vector(7 downto 0);
ram_read_address_2 : out std_logic_vector(7 downto 0);
datapath_enabled : out std_logic;
datapath_operation_code : out std_logic_vector(3 downto 0);
datapath_operand_1 : out std_logic_vector(7 downto 0);
datapath_operand_2 : out std_logic_vector(7 downto 0);
datapath_result : in std_logic_vector(7 downto 0);
datapath_zero_flag : in std_logic;
datapath_significant_bit_flag : in std_logic
);
end component;
signal mp_ram_read_write : std_logic;
signal mp_ram_read_address_1 : std_logic_vector(7 downto 0);
signal mp_ram_read_address_2 : std_logic_vector(7 downto 0);
signal mp_ram_write_address : std_logic_vector(7 downto 0);
signal mp_ram_read_data_port_1 : std_logic_vector(7 downto 0);
signal mp_ram_read_data_port_2 : std_logic_vector(7 downto 0);
signal mp_ram_write_data_port : std_logic_vector(7 downto 0);
signal mp_rom_read_enable : std_logic;
signal mp_rom_address : std_logic_vector(7 downto 0);
signal mp_rom_data_output : std_logic_vector(27 downto 0);
signal mp_datapath_enabled : std_logic;
signal mp_datapath_operation_code : std_logic_vector(3 downto 0);
signal mp_datapath_operand_1 : std_logic_vector(7 downto 0);
signal mp_datapath_operand_2 : std_logic_vector(7 downto 0);
signal mp_datapath_result : std_logic_vector(7 downto 0);
signal mp_datapath_zero_flag : std_logic;
signal mp_datapath_significant_bit_flag : std_logic;
begin
U_RAM : entity MRAM port map(
clk => clk,
write_data_port => mp_ram_write_data_port,
write_address => mp_ram_write_address,
read_data_port_1 => mp_ram_read_data_port_1,
read_data_port_2 => mp_ram_read_data_port_2,
read_address_1 => mp_ram_read_address_1,
read_address_2 => mp_ram_read_address_2,
read_write => mp_ram_read_write
);
U_ROM : entity MicroROM port map(
read_enable => mp_rom_read_enable,
address => mp_rom_address,
data_output => mp_rom_data_output
);
U_DATAPATH : Datapath port map(
enabled => mp_datapath_enabled,
operation_code => mp_datapath_operation_code,
operand_1 => mp_datapath_operand_1,
operand_2 => mp_datapath_operand_2,
result => mp_datapath_result,
zero_flag => mp_datapath_zero_flag,
significant_bit_flag => mp_datapath_significant_bit_flag
);
U_CONTROLLER : Controller port map(
clk => clk,
rst => rst,
start => start,
stop => stop,
rom_enabled => mp_rom_read_enable,
rom_address => mp_rom_address,
rom_data_output => mp_rom_data_output,
ram_read_write => mp_ram_read_write,
ram_write_data_port => mp_ram_write_data_port,
ram_write_address => mp_ram_write_address,
ram_read_data_port_1 => mp_ram_read_data_port_1,
ram_read_data_port_2 => mp_ram_read_data_port_2,
ram_read_address_1 => mp_ram_read_address_1,
ram_read_address_2 => mp_ram_read_address_2,
datapath_enabled => mp_datapath_enabled,
datapath_operation_code => mp_datapath_operation_code,
datapath_operand_1 => mp_datapath_operand_1,
datapath_operand_2 => mp_datapath_operand_2,
datapath_result => mp_datapath_result,
datapath_zero_flag => mp_datapath_zero_flag,
datapath_significant_bit_flag => mp_datapath_significant_bit_flag
);
end MicroProcessor_Behavioural;
|
package bug_pkg is
procedure proc_bug(constant t : in time := 8.68 us);
procedure proc_ok1(constant t : in time);
procedure proc_ok2(constant t : in integer := 5);
end bug_pkg;
package body bug_pkg is
procedure proc_bug(constant t : in time := 8.68 us) is
begin
end proc_bug;
procedure proc_ok1(constant t : in time) is
begin
end proc_ok1;
procedure proc_ok2(constant t : in integer := 5) is
begin
end proc_ok2;
end bug_pkg;
|
package bug_pkg is
procedure proc_bug(constant t : in time := 8.68 us);
procedure proc_ok1(constant t : in time);
procedure proc_ok2(constant t : in integer := 5);
end bug_pkg;
package body bug_pkg is
procedure proc_bug(constant t : in time := 8.68 us) is
begin
end proc_bug;
procedure proc_ok1(constant t : in time) is
begin
end proc_ok1;
procedure proc_ok2(constant t : in integer := 5) is
begin
end proc_ok2;
end bug_pkg;
|
-------------------------------------------------------------------------------
-- File Name : JFIFGen.vhd
--
-- Project : JPEG_ENC
--
-- Module : JFIFGen
--
-- Content : JFIF Header Generator
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090309: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JFIFGen is
port
(
CLK : in std_logic;
RST : in std_logic;
outif_almost_full : in std_logic;
-- CTRL
start : in std_logic;
ready : out std_logic;
eoi : in std_logic;
-- ByteStuffer
num_enc_bytes : in std_logic_vector(23 downto 0);
-- HOST IF
qwren : in std_logic;
qwaddr : in std_logic_vector(6 downto 0);
qwdata : in std_logic_vector(7 downto 0);
image_size_reg : in std_logic_vector(31 downto 0);
image_size_reg_wr : in std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0)
);
end entity JFIFGen;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JFIFGen is
constant C_SIZE_Y_H : integer := 25;
constant C_SIZE_Y_L : integer := 26;
constant C_SIZE_X_H : integer := 27;
constant C_SIZE_X_L : integer := 28;
constant C_EOI : std_logic_vector(15 downto 0) := X"FFD9";
constant C_QLUM_BASE : integer := 44;
constant C_QCHR_BASE : integer := 44+69;
signal hr_data : std_logic_vector(7 downto 0):=(others =>'0');
signal hr_waddr : std_logic_vector(9 downto 0):=(others =>'0');
signal hr_raddr : std_logic_vector(9 downto 0):=(others =>'0');
signal hr_we : std_logic:='0';
signal hr_q : std_logic_vector(7 downto 0):=(others =>'0');
signal size_wr_cnt : unsigned(2 downto 0):=(others =>'0');
signal size_wr : std_logic:='0';
signal rd_cnt : unsigned(9 downto 0):=(others =>'0');
signal rd_en : std_logic:='0';
signal rd_en_d1 : std_logic:='0';
signal rd_cnt_d1 : unsigned(rd_cnt'range):=(others =>'0');
signal rd_cnt_d2 : unsigned(rd_cnt'range):=(others =>'0');
signal eoi_cnt : unsigned(1 downto 0):=(others =>'0');
signal eoi_wr : std_logic:='0';
signal eoi_wr_d1 : std_logic:='0';
signal reading_header : std_logic;
component HeaderRam is
port
(
d : in STD_LOGIC_VECTOR(7 downto 0);
waddr : in STD_LOGIC_VECTOR(9 downto 0);
raddr : in STD_LOGIC_VECTOR(9 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Header RAM
-------------------------------------------------------------------
U_Header_RAM : HeaderRam
port map
(
d => hr_data,
waddr => hr_waddr,
raddr => hr_raddr,
we => hr_we,
clk => CLK,
q => hr_q
);
hr_raddr <= std_logic_vector(rd_cnt);
-------------------------------------------------------------------
-- Host programming
-------------------------------------------------------------------
p_host_wr : process(CLK, RST)
begin
if RST = '1' then
size_wr_cnt <= (others => '0');
size_wr <= '0';
hr_we <= '0';
hr_data <= (others => '0');
hr_waddr <= (others => '0');
elsif CLK'event and CLK = '1' then
hr_we <= '0';
if image_size_reg_wr = '1' then
size_wr_cnt <= (others => '0');
size_wr <= '1';
end if;
-- write image size
if size_wr = '1' then
if size_wr_cnt = 4 then
size_wr_cnt <= (others => '0');
size_wr <= '0';
else
size_wr_cnt <= size_wr_cnt + 1;
hr_we <= '1';
case size_wr_cnt is
-- height H byte
when "000" =>
hr_data <= image_size_reg(15 downto 8);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_H,hr_waddr'length));
-- height L byte
when "001" =>
hr_data <= image_size_reg(7 downto 0);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_L,hr_waddr'length));
-- width H byte
when "010" =>
hr_data <= image_size_reg(31 downto 24);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_H,hr_waddr'length));
-- width L byte
when "011" =>
hr_data <= image_size_reg(23 downto 16);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_L,hr_waddr'length));
when others =>
null;
end case;
end if;
-- write Quantization table
elsif qwren = '1' then
-- luminance table select
if qwaddr(6) = '0' then
hr_waddr <= std_logic_vector
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
to_unsigned(C_QLUM_BASE,hr_waddr'length));
else
-- chrominance table select
hr_waddr <= std_logic_vector
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
to_unsigned(C_QCHR_BASE,hr_waddr'length));
end if;
hr_we <= '1';
hr_data <= qwdata;
end if;
end if;
end process;
-------------------------------------------------------------------
-- CTRL
-------------------------------------------------------------------
p_ctrl : process(CLK, RST)
begin
if RST = '1' then
ready <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
rd_cnt_d1 <= (others => '0');
rd_cnt_d2 <= (others => '0');
rd_cnt_d1 <= (others => '0');
rd_en_d1 <= '0';
eoi_wr_d1 <= '0';
eoi_wr <= '0';
eoi_cnt <= (others => '0');
ram_wren <= '0';
ram_byte <= (others => '0');
ram_wraddr <= (others => '0');
reading_header <= '0';
elsif CLK'event and CLK = '1' then
ready <= '0';
rd_cnt_d1 <= rd_cnt;
rd_cnt_d2 <= rd_cnt_d1;
rd_en_d1 <= rd_en;
eoi_wr_d1 <= eoi_wr;
-- defaults: encoded data write
ram_wren <= rd_en_d1;
ram_wraddr <= std_logic_vector(resize(rd_cnt_d1,ram_wraddr'length));
ram_byte <= hr_q;
-- start JFIF
if start = '1' and eoi = '0' then
rd_cnt <= (others => '0');
rd_en <= '1';
reading_header <= '1';
elsif start = '1' and eoi = '1' then
eoi_wr <= '1';
eoi_cnt <= (others => '0');
end if;
-- read JFIF Header
if reading_header = '1' then
if rd_cnt = C_HDR_SIZE-1 then
reading_header <= '0';
rd_en <= '0';
ready <= '1';
else
if outif_almost_full = '0' then
rd_en <= '1';
rd_cnt <= rd_cnt + 1;
else
rd_en <= '0';
end if;
end if;
end if;
-- EOI MARKER write
if eoi_wr = '1' then
if eoi_cnt = 2 then
eoi_cnt <= (others => '0');
eoi_wr <= '0';
ready <= '1';
else
eoi_cnt <= eoi_cnt + 1;
ram_wren <= '1';
if eoi_cnt = 0 then
ram_byte <= C_EOI(15 downto 8);
ram_wraddr <= num_enc_bytes;
elsif eoi_cnt = 1 then
ram_byte <= C_EOI(7 downto 0);
ram_wraddr <= std_logic_vector(unsigned(num_enc_bytes) +
to_unsigned(1,ram_wraddr'length));
end if;
end if;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : JFIFGen.vhd
--
-- Project : JPEG_ENC
--
-- Module : JFIFGen
--
-- Content : JFIF Header Generator
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090309: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JFIFGen is
port
(
CLK : in std_logic;
RST : in std_logic;
outif_almost_full : in std_logic;
-- CTRL
start : in std_logic;
ready : out std_logic;
eoi : in std_logic;
-- ByteStuffer
num_enc_bytes : in std_logic_vector(23 downto 0);
-- HOST IF
qwren : in std_logic;
qwaddr : in std_logic_vector(6 downto 0);
qwdata : in std_logic_vector(7 downto 0);
image_size_reg : in std_logic_vector(31 downto 0);
image_size_reg_wr : in std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0)
);
end entity JFIFGen;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JFIFGen is
constant C_SIZE_Y_H : integer := 25;
constant C_SIZE_Y_L : integer := 26;
constant C_SIZE_X_H : integer := 27;
constant C_SIZE_X_L : integer := 28;
constant C_EOI : std_logic_vector(15 downto 0) := X"FFD9";
constant C_QLUM_BASE : integer := 44;
constant C_QCHR_BASE : integer := 44+69;
signal hr_data : std_logic_vector(7 downto 0):=(others =>'0');
signal hr_waddr : std_logic_vector(9 downto 0):=(others =>'0');
signal hr_raddr : std_logic_vector(9 downto 0):=(others =>'0');
signal hr_we : std_logic:='0';
signal hr_q : std_logic_vector(7 downto 0):=(others =>'0');
signal size_wr_cnt : unsigned(2 downto 0):=(others =>'0');
signal size_wr : std_logic:='0';
signal rd_cnt : unsigned(9 downto 0):=(others =>'0');
signal rd_en : std_logic:='0';
signal rd_en_d1 : std_logic:='0';
signal rd_cnt_d1 : unsigned(rd_cnt'range):=(others =>'0');
signal rd_cnt_d2 : unsigned(rd_cnt'range):=(others =>'0');
signal eoi_cnt : unsigned(1 downto 0):=(others =>'0');
signal eoi_wr : std_logic:='0';
signal eoi_wr_d1 : std_logic:='0';
signal reading_header : std_logic;
component HeaderRam is
port
(
d : in STD_LOGIC_VECTOR(7 downto 0);
waddr : in STD_LOGIC_VECTOR(9 downto 0);
raddr : in STD_LOGIC_VECTOR(9 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Header RAM
-------------------------------------------------------------------
U_Header_RAM : HeaderRam
port map
(
d => hr_data,
waddr => hr_waddr,
raddr => hr_raddr,
we => hr_we,
clk => CLK,
q => hr_q
);
hr_raddr <= std_logic_vector(rd_cnt);
-------------------------------------------------------------------
-- Host programming
-------------------------------------------------------------------
p_host_wr : process(CLK, RST)
begin
if RST = '1' then
size_wr_cnt <= (others => '0');
size_wr <= '0';
hr_we <= '0';
hr_data <= (others => '0');
hr_waddr <= (others => '0');
elsif CLK'event and CLK = '1' then
hr_we <= '0';
if image_size_reg_wr = '1' then
size_wr_cnt <= (others => '0');
size_wr <= '1';
end if;
-- write image size
if size_wr = '1' then
if size_wr_cnt = 4 then
size_wr_cnt <= (others => '0');
size_wr <= '0';
else
size_wr_cnt <= size_wr_cnt + 1;
hr_we <= '1';
case size_wr_cnt is
-- height H byte
when "000" =>
hr_data <= image_size_reg(15 downto 8);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_H,hr_waddr'length));
-- height L byte
when "001" =>
hr_data <= image_size_reg(7 downto 0);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_L,hr_waddr'length));
-- width H byte
when "010" =>
hr_data <= image_size_reg(31 downto 24);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_H,hr_waddr'length));
-- width L byte
when "011" =>
hr_data <= image_size_reg(23 downto 16);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_L,hr_waddr'length));
when others =>
null;
end case;
end if;
-- write Quantization table
elsif qwren = '1' then
-- luminance table select
if qwaddr(6) = '0' then
hr_waddr <= std_logic_vector
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
to_unsigned(C_QLUM_BASE,hr_waddr'length));
else
-- chrominance table select
hr_waddr <= std_logic_vector
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
to_unsigned(C_QCHR_BASE,hr_waddr'length));
end if;
hr_we <= '1';
hr_data <= qwdata;
end if;
end if;
end process;
-------------------------------------------------------------------
-- CTRL
-------------------------------------------------------------------
p_ctrl : process(CLK, RST)
begin
if RST = '1' then
ready <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
rd_cnt_d1 <= (others => '0');
rd_cnt_d2 <= (others => '0');
rd_cnt_d1 <= (others => '0');
rd_en_d1 <= '0';
eoi_wr_d1 <= '0';
eoi_wr <= '0';
eoi_cnt <= (others => '0');
ram_wren <= '0';
ram_byte <= (others => '0');
ram_wraddr <= (others => '0');
reading_header <= '0';
elsif CLK'event and CLK = '1' then
ready <= '0';
rd_cnt_d1 <= rd_cnt;
rd_cnt_d2 <= rd_cnt_d1;
rd_en_d1 <= rd_en;
eoi_wr_d1 <= eoi_wr;
-- defaults: encoded data write
ram_wren <= rd_en_d1;
ram_wraddr <= std_logic_vector(resize(rd_cnt_d1,ram_wraddr'length));
ram_byte <= hr_q;
-- start JFIF
if start = '1' and eoi = '0' then
rd_cnt <= (others => '0');
rd_en <= '1';
reading_header <= '1';
elsif start = '1' and eoi = '1' then
eoi_wr <= '1';
eoi_cnt <= (others => '0');
end if;
-- read JFIF Header
if reading_header = '1' then
if rd_cnt = C_HDR_SIZE-1 then
reading_header <= '0';
rd_en <= '0';
ready <= '1';
else
if outif_almost_full = '0' then
rd_en <= '1';
rd_cnt <= rd_cnt + 1;
else
rd_en <= '0';
end if;
end if;
end if;
-- EOI MARKER write
if eoi_wr = '1' then
if eoi_cnt = 2 then
eoi_cnt <= (others => '0');
eoi_wr <= '0';
ready <= '1';
else
eoi_cnt <= eoi_cnt + 1;
ram_wren <= '1';
if eoi_cnt = 0 then
ram_byte <= C_EOI(15 downto 8);
ram_wraddr <= num_enc_bytes;
elsif eoi_cnt = 1 then
ram_byte <= C_EOI(7 downto 0);
ram_wraddr <= std_logic_vector(unsigned(num_enc_bytes) +
to_unsigned(1,ram_wraddr'length));
end if;
end if;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Syndrome_Calculator_n
-- Module Name: Tb_Syndrome_Calculator_n
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for syndrome_calculator_n circuit.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_units :
--
-- The number of units that compute each syndrome at the same time.
-- This number must be 1 or greater.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword or in this case the ciphertext. Both the codeword
-- and ciphertext has the same size.
--
-- size_codeword :
--
-- The number of bits necessary to hold the ciphertext/codeword.
-- This is ceil(log2(length_codeword)).
--
-- length_syndrome :
--
-- The size of the syndrome array. This parameter depends of the
-- Goppa code used.
--
-- size_syndrome :
--
-- The number of bits necessary to hold the array syndrome.
-- This is ceil(log2(length_syndrome)).
--
-- file_memory_L :
--
-- The file that holds all support elements L.
-- This is part of the private key of the cryptosystem.
--
-- file_memory_h :
--
-- The file that holds all inverted evaluations of support elements L in polynomial g.
-- Therefore, g(L)^-1.
-- This is part of the private key of the cryptosystem.
--
-- file_memory_codeword :
--
-- The file that holds the received ciphertext necessary for computing the syndrome.
--
-- file_memory_syndrome :
--
-- The file that holds the syndrome previously computed.
-- This is necessary to be compared with circuit computed syndrome to verify if it worked.
--
-- dump_file_memory_syndrome :
--
-- The file that will hold the computed syndrome by the circuit.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- syndrome_calculator_n Rev 1.0
-- ram Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_syndrome_calculator_n is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- number_of_units : integer := 8;
-- gf_2_m : integer range 1 to 20 := 6;
-- length_codeword : integer := 52;
-- size_codeword : integer := 6;
-- length_syndrome : integer := 8;
-- size_syndrome : integer := 3;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_52_28_4_6.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_52_28_4_6.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_52_28_4_6.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_52_28_4_6.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 54;
-- size_syndrome : integer := 6;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1751_27_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1751_27_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1751_27_11.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_goppa_2048_1751_27_11.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 100;
-- size_syndrome : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1498_50_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1498_50_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1498_50_11.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_goppa_2048_1498_50_11.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 132;
-- size_syndrome : integer := 8;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_3307_2515_66_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_3307_2515_66_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_3307_2515_66_12.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_goppa_3307_2515_66_12.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_units : integer := 16;
gf_2_m : integer range 1 to 20 := 12;
length_codeword : integer := 2528;
size_codeword : integer := 12;
length_syndrome : integer := 64;
size_syndrome : integer := 7;
file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2528_2144_32_12.dat";
file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2528_2144_32_12.dat";
file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2528_2144_32_12.dat";
file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_2528_2144_32_12.dat";
dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2816_2048_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2816_2048_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2816_2048_64_12.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_2816_2048_64_12.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_3328_2560_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_3328_2560_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_3328_2560_64_12.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_3328_2560_64_12.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- length_syndrome : integer := 256;
-- size_syndrome : integer := 8;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_7296_5632_128_13.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_7296_5632_128_13.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_7296_5632_128_13.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_7296_5632_128_13.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_7296_5632_128_13.dat"
);
end tb_syndrome_calculator_n;
architecture Behavioral of tb_syndrome_calculator_n is
component syndrome_calculator_n
Generic(
gf_2_m : integer range 1 to 20 := 11;
length_codeword : integer := 1792;
size_codeword : integer := 11;
length_syndrome : integer := 128;
size_syndrome : integer := 7;
number_of_units : integer := 1
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_L : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_L : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0)
);
end component;
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal value_h : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_L : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_codeword : STD_LOGIC_VECTOR(0 downto 0);
signal syndrome_finalized : STD_LOGIC;
signal write_enable_new_syndrome : STD_LOGIC;
signal new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal address_h : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal address_L : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal address_syndrome : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal test_address_syndrome : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal true_address_syndrome : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal test_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal true_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal error_syndrome : STD_LOGIC;
signal test_syndrome_dump : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for mem_L : ram use entity work.ram(file_load);
for mem_h : ram use entity work.ram(file_load);
for mem_codeword : ram use entity work.ram(file_load);
for test_syndrome : ram use entity work.ram(simple);
for true_syndrome : ram use entity work.ram(file_load);
begin
test : syndrome_calculator_n
Generic Map(
gf_2_m => gf_2_m,
length_codeword => length_codeword,
size_codeword => size_codeword,
length_syndrome => length_syndrome,
size_syndrome => size_syndrome,
number_of_units => number_of_units
)
Port Map(
clk => clk,
rst => rst,
value_h => value_h,
value_L => value_L,
value_syndrome => test_value_syndrome,
value_codeword => value_codeword,
syndrome_finalized => syndrome_finalized,
write_enable_new_syndrome => write_enable_new_syndrome,
new_value_syndrome => new_value_syndrome,
address_h => address_h,
address_L => address_L,
address_codeword => address_codeword,
address_syndrome => test_address_syndrome
);
mem_L : ram
Generic Map(
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_L,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_L,
rst_value => (others => '0'),
data_out => value_L
);
mem_h : ram
Generic Map(
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_h,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_h,
rst_value => (others => '0'),
data_out => value_h
);
mem_codeword : ram
Generic Map(
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_codeword,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_codeword,
rst_value => (others => '0'),
data_out => value_codeword
);
test_syndrome : ram
Generic Map(
ram_address_size => size_syndrome,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => dump_file_memory_syndrome
)
Port Map(
data_in => new_value_syndrome,
rw => write_enable_new_syndrome,
clk => clk,
rst => rst,
dump => test_syndrome_dump,
address => address_syndrome,
rst_value => (others => '0'),
data_out => test_value_syndrome
);
true_syndrome : ram
Generic Map(
ram_address_size => size_syndrome,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_syndrome,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_syndrome,
rst_value => (others => '0'),
data_out => true_value_syndrome
);
address_syndrome <= true_address_syndrome when syndrome_finalized = '1' else test_address_syndrome;
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
--clk <= not clk after PERIOD/2;
process
variable i : integer;
begin
true_address_syndrome <= (others => '0');
rst <= '1';
error_syndrome <= '0';
test_syndrome_dump <= '0';
wait for PERIOD*2;
rst <= '0';
wait until syndrome_finalized = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_syndrome)) loop
true_address_syndrome <= std_logic_vector(to_unsigned(i, test_address_syndrome'Length));
wait for PERIOD*2;
if (true_value_syndrome = test_value_syndrome) then
error_syndrome <= '0';
else
error_syndrome <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error_syndrome <= '0';
wait for PERIOD;
i := i + 1;
end loop;
test_syndrome_dump <= '1';
wait for PERIOD;
test_syndrome_dump <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
--
-- EnvelopeGenerator.vhd
-- The envelope generator module of VM2413
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity EnvelopeGenerator is
port (clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
am : in AM_TYPE;
tl : in DB_TYPE;
ar : in AR_TYPE;
dr : in DR_TYPE;
sl : in SL_TYPE;
rr : in RR_TYPE;
rks : in RKS_TYPE;
key : in std_logic;
egout : out DB_TYPE);
end EnvelopeGenerator;
architecture RTL of EnvelopeGenerator is
component EnvelopeMemory port (
clk : in std_logic;
reset : in std_logic;
waddr : in SLOT_TYPE;
wr : in std_logic;
wdata : in EGDATA_TYPE;
raddr : in SLOT_TYPE;
rdata : out EGDATA_TYPE
);
end component;
component AttackTable port (
clk : in std_logic;
addr : in integer range 0 to 2 ** (DB_TYPE'high+1) - 1;
data : out DB_TYPE
);
end component;
signal rslot : SLOT_TYPE;
signal memin, memout : EGDATA_TYPE;
signal memwr : std_logic;
signal aridx : integer range 0 to 2 ** (DB_TYPE'high+1) - 1;
signal ardata : DB_TYPE;
begin
ARTBL : AttackTable port map ( clk, aridx, ardata );
EGMEM : EnvelopeMemory port map ( clk, reset, slot, memwr, memin, rslot, memout );
process(clk, reset)
variable lastkey : std_logic_vector(MAXSLOT-1 downto 0);
variable rm : std_logic_vector(4 downto 0);
variable egtmp : std_logic_vector(DB_TYPE'high + 2 downto 0);
variable ntable : std_logic_vector(17 downto 0);
variable amphase : std_logic_vector(19 downto 0);
variable rslot_buf : SLOT_TYPE;
variable egphase : EGPHASE_TYPE;
variable egstate : EGSTATE_TYPE;
variable dphase : EGPHASE_TYPE;
begin
if(reset = '1') then
rm := (others=>'0');
lastkey := (others=>'0');
ntable := (others=>'1');
amphase(amphase'high downto amphase'high-4) := "00001";
amphase(amphase'high-5 downto 0) := (others=>'0');
memwr <= '0';
egstate := Finish;
egphase := (others=>'0');
rslot_buf := 0;
elsif(clk'event and clk='1') then if clkena ='1' then
-- White noise generator
for I in 17 downto 1 loop
ntable(I) := ntable(I-1);
end loop;
ntable(0) := ntable(17) xor ntable(14);
-- Amplitude oscillator ( -4.8dB to 0dB , 3.7Hz )
amphase := amphase + '1';
if amphase(amphase'high downto amphase'high-4) = "11111" then
amphase(amphase'high downto amphase'high-4) := "00001";
end if;
if stage = 0 then
egstate := memout.state;
egphase := memout.phase;
aridx <= CONV_INTEGER( egphase( egphase'high-1 downto egphase'high-7 ) );
elsif stage = 1 then
-- Wait for AttackTable
elsif stage = 2 then
case egstate is
when Attack =>
rm := '0'&ar;
egtmp := ("00"&tl) + ("00"&ardata);
when Decay =>
rm := '0'&dr;
egtmp := ("00"&tl) + ("00"&egphase(egphase'high-1 downto egphase'high-7));
when Release=>
rm := '0'&rr;
egtmp := ("00"&tl) + ("00"&egphase(egphase'high-1 downto egphase'high-7));
when Finish =>
egtmp(egtmp'high downto egtmp'high -1) := "00";
egtmp(egtmp'high-2 downto 0) := (others=>'1');
end case;
-- SD and HH
if ntable(0)='1' and slot/2 = 7 and rhythm = '1' then
egtmp := egtmp + "010000000";
end if;
-- Amplitude LFO
if am ='1' then
if (amphase(amphase'high) = '0') then
egtmp := egtmp + ("00000"&(amphase(amphase'high-1 downto amphase'high-4)-'1'));
else
egtmp := egtmp + ("00000"&("1111"-amphase(amphase'high-1 downto amphase'high-4)));
end if;
end if;
-- Generate output
if egtmp(egtmp'high downto egtmp'high-1) = "00" then
egout <= egtmp(egout'range);
else
egout <= (others=>'1');
end if;
if rm /= "00000" then
rm := rm + rks(3 downto 2);
if rm(rm'high)='1' then
rm(3 downto 0):="1111";
end if;
case egstate is
when Attack =>
dphase(dphase'high downto 5) := (others=>'0');
dphase(5 downto 0) := "110" * ('1'&rks(1 downto 0));
dphase := SHL( dphase, rm(3 downto 0) );
egphase := egphase - dphase(egphase'range);
when Decay | Release =>
dphase(dphase'high downto 3) := (others=>'0');
dphase(2 downto 0) := '1'&rks(1 downto 0);
dphase := SHL(dphase, rm(3 downto 0) - '1');
egphase := egphase + dphase(egphase'range);
when Finish =>
null;
end case;
end if;
case egstate is
when Attack =>
if egphase(egphase'high) = '1' then
egphase := (others=>'0');
egstate := Decay;
end if;
when Decay =>
if egphase(egphase'high downto egphase'high-4) >= '0'&sl then
egstate := Release;
end if;
when Release =>
if( egphase(egphase'high downto egphase'high-4) >= "01111" ) then
egstate:= Finish;
end if;
when Finish =>
egphase := (others => '1');
end case;
if lastkey(slot) = '0' and key = '1' then
egphase(egphase'high):= '0';
egphase(egphase'high-1 downto 0) := (others =>'1');
egstate:= Attack;
elsif lastkey(slot) = '1' and key = '0' and egstate /= Finish then
egstate:= Release;
end if;
lastkey(slot) := key;
-- update phase and state memory
memin <= ( state => egstate, phase => egphase );
memwr <='1';
-- read phase of next slot (prefetch)
if slot = 17 then
rslot_buf := 0;
else
rslot_buf := slot + 1;
end if;
rslot <= rslot_buf;
elsif stage = 3 then
-- wait for phase memory
memwr <='0';
end if;
end if; end if;
end process;
end RTL;
|
--
-- EnvelopeGenerator.vhd
-- The envelope generator module of VM2413
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity EnvelopeGenerator is
port (clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
am : in AM_TYPE;
tl : in DB_TYPE;
ar : in AR_TYPE;
dr : in DR_TYPE;
sl : in SL_TYPE;
rr : in RR_TYPE;
rks : in RKS_TYPE;
key : in std_logic;
egout : out DB_TYPE);
end EnvelopeGenerator;
architecture RTL of EnvelopeGenerator is
component EnvelopeMemory port (
clk : in std_logic;
reset : in std_logic;
waddr : in SLOT_TYPE;
wr : in std_logic;
wdata : in EGDATA_TYPE;
raddr : in SLOT_TYPE;
rdata : out EGDATA_TYPE
);
end component;
component AttackTable port (
clk : in std_logic;
addr : in integer range 0 to 2 ** (DB_TYPE'high+1) - 1;
data : out DB_TYPE
);
end component;
signal rslot : SLOT_TYPE;
signal memin, memout : EGDATA_TYPE;
signal memwr : std_logic;
signal aridx : integer range 0 to 2 ** (DB_TYPE'high+1) - 1;
signal ardata : DB_TYPE;
begin
ARTBL : AttackTable port map ( clk, aridx, ardata );
EGMEM : EnvelopeMemory port map ( clk, reset, slot, memwr, memin, rslot, memout );
process(clk, reset)
variable lastkey : std_logic_vector(MAXSLOT-1 downto 0);
variable rm : std_logic_vector(4 downto 0);
variable egtmp : std_logic_vector(DB_TYPE'high + 2 downto 0);
variable ntable : std_logic_vector(17 downto 0);
variable amphase : std_logic_vector(19 downto 0);
variable rslot_buf : SLOT_TYPE;
variable egphase : EGPHASE_TYPE;
variable egstate : EGSTATE_TYPE;
variable dphase : EGPHASE_TYPE;
begin
if(reset = '1') then
rm := (others=>'0');
lastkey := (others=>'0');
ntable := (others=>'1');
amphase(amphase'high downto amphase'high-4) := "00001";
amphase(amphase'high-5 downto 0) := (others=>'0');
memwr <= '0';
egstate := Finish;
egphase := (others=>'0');
rslot_buf := 0;
elsif(clk'event and clk='1') then if clkena ='1' then
-- White noise generator
for I in 17 downto 1 loop
ntable(I) := ntable(I-1);
end loop;
ntable(0) := ntable(17) xor ntable(14);
-- Amplitude oscillator ( -4.8dB to 0dB , 3.7Hz )
amphase := amphase + '1';
if amphase(amphase'high downto amphase'high-4) = "11111" then
amphase(amphase'high downto amphase'high-4) := "00001";
end if;
if stage = 0 then
egstate := memout.state;
egphase := memout.phase;
aridx <= CONV_INTEGER( egphase( egphase'high-1 downto egphase'high-7 ) );
elsif stage = 1 then
-- Wait for AttackTable
elsif stage = 2 then
case egstate is
when Attack =>
rm := '0'&ar;
egtmp := ("00"&tl) + ("00"&ardata);
when Decay =>
rm := '0'&dr;
egtmp := ("00"&tl) + ("00"&egphase(egphase'high-1 downto egphase'high-7));
when Release=>
rm := '0'&rr;
egtmp := ("00"&tl) + ("00"&egphase(egphase'high-1 downto egphase'high-7));
when Finish =>
egtmp(egtmp'high downto egtmp'high -1) := "00";
egtmp(egtmp'high-2 downto 0) := (others=>'1');
end case;
-- SD and HH
if ntable(0)='1' and slot/2 = 7 and rhythm = '1' then
egtmp := egtmp + "010000000";
end if;
-- Amplitude LFO
if am ='1' then
if (amphase(amphase'high) = '0') then
egtmp := egtmp + ("00000"&(amphase(amphase'high-1 downto amphase'high-4)-'1'));
else
egtmp := egtmp + ("00000"&("1111"-amphase(amphase'high-1 downto amphase'high-4)));
end if;
end if;
-- Generate output
if egtmp(egtmp'high downto egtmp'high-1) = "00" then
egout <= egtmp(egout'range);
else
egout <= (others=>'1');
end if;
if rm /= "00000" then
rm := rm + rks(3 downto 2);
if rm(rm'high)='1' then
rm(3 downto 0):="1111";
end if;
case egstate is
when Attack =>
dphase(dphase'high downto 5) := (others=>'0');
dphase(5 downto 0) := "110" * ('1'&rks(1 downto 0));
dphase := SHL( dphase, rm(3 downto 0) );
egphase := egphase - dphase(egphase'range);
when Decay | Release =>
dphase(dphase'high downto 3) := (others=>'0');
dphase(2 downto 0) := '1'&rks(1 downto 0);
dphase := SHL(dphase, rm(3 downto 0) - '1');
egphase := egphase + dphase(egphase'range);
when Finish =>
null;
end case;
end if;
case egstate is
when Attack =>
if egphase(egphase'high) = '1' then
egphase := (others=>'0');
egstate := Decay;
end if;
when Decay =>
if egphase(egphase'high downto egphase'high-4) >= '0'&sl then
egstate := Release;
end if;
when Release =>
if( egphase(egphase'high downto egphase'high-4) >= "01111" ) then
egstate:= Finish;
end if;
when Finish =>
egphase := (others => '1');
end case;
if lastkey(slot) = '0' and key = '1' then
egphase(egphase'high):= '0';
egphase(egphase'high-1 downto 0) := (others =>'1');
egstate:= Attack;
elsif lastkey(slot) = '1' and key = '0' and egstate /= Finish then
egstate:= Release;
end if;
lastkey(slot) := key;
-- update phase and state memory
memin <= ( state => egstate, phase => egphase );
memwr <='1';
-- read phase of next slot (prefetch)
if slot = 17 then
rslot_buf := 0;
else
rslot_buf := slot + 1;
end if;
rslot <= rslot_buf;
elsif stage = 3 then
-- wait for phase memory
memwr <='0';
end if;
end if; end if;
end process;
end RTL;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for pad_tb
--
-- Generated
-- by: wig
-- on: Thu Jan 19 07:44:48 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_tb-struct-conf-c.vhd,v 1.4 2006/01/19 08:50:41 wig Exp $
-- $Date: 2006/01/19 08:50:41 $
-- $Log: pad_tb-struct-conf-c.vhd,v $
-- Revision 1.4 2006/01/19 08:50:41 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration pad_tb_struct_conf / pad_tb
--
configuration pad_tb_struct_conf of pad_tb is
for struct
-- Generated Configuration
for i_padframe : padframe
use configuration work.padframe_struct_conf;
end for;
end for;
end pad_tb_struct_conf;
--
-- End of Generated Configuration pad_tb_struct_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity control is
port(
reset : in vl_logic;
rb : in vl_logic;
eq : in vl_logic;
d7 : in vl_logic;
d711 : in vl_logic;
d2312 : in vl_logic;
roll : out vl_logic;
win : out vl_logic;
lose : out vl_logic;
sp : out vl_logic
);
end control;
|
-- Author: Osama G. Attia
-- email: ogamal [at] iastate dot edu
-- Create Date: 16:57:25 06/23/2014
-- Module Name: scc_process2 - Behavioral
-- Description: Request rInfo[id] and SCC[id]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity scc_process2 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
-- Process 2 information
p2_done : out std_logic;
p2_count : out unsigned(63 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
rgraph_info : in std_logic_vector(63 downto 0);
scc_results : in std_logic_vector(63 downto 0);
-- Process 2 information
p1_done : in std_logic;
p1_count : in unsigned(63 downto 0);
-- Process 2 SCC req queue signals
p2_scc_req_almost_full : in std_logic;
p2_scc_req_wr_en : out std_logic;
p2_scc_req_din : out std_logic_vector(63 downto 0);
-- Process 2 rInfo req queue signals
p2_rInfo_req_almost_full : in std_logic;
p2_rInfo_req_wr_en : out std_logic;
p2_rInfo_req_din : out std_logic_vector(63 downto 0);
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end scc_process2;
architecture Behavioral of scc_process2 is
signal count : unsigned (63 downto 0);
begin
p2_count <= count;
p2 : process (clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
p2_done <= '0';
count <= (others => '0');
p2_scc_req_wr_en <= '0';
p2_scc_req_din <= (others => '0');
p2_rInfo_req_wr_en <= '0';
p2_rInfo_req_din <= (others => '0');
else
if (enable = '1') then
-- Got process 1 response
if (p2_scc_req_almost_full = '0' and p2_rInfo_req_almost_full = '0' and mc_rsp_push = '1' and mc_rsp_rdctl(7 downto 0) = x"01") then
-- request scc[ID]
p2_scc_req_wr_en <= '1';
p2_scc_req_din <= std_logic_vector(resize(8 * unsigned(mc_rsp_data) + unsigned(scc_results), 64));
-- request rInfo[ID]
p2_rInfo_req_wr_en <= '1';
p2_rInfo_req_din <= std_logic_vector(resize(8 * unsigned(mc_rsp_data) + unsigned(rgraph_info), 64));
-- increment counter
count <= count + 1;
else
p2_scc_req_wr_en <= '0';
p2_scc_req_din <= (others => '0');
p2_rInfo_req_wr_en <= '0';
p2_rInfo_req_din <= (others => '0');
end if;
-- Process 2 is done if process 1 is done and count = p1_count
if (p1_done = '1' and count = p1_count) then
p2_done <= '1';
end if;
else
p2_done <= '0';
count <= (others => '0');
p2_scc_req_wr_en <= '0';
p2_scc_req_din <= (others => '0');
p2_rInfo_req_wr_en <= '0';
p2_rInfo_req_din <= (others => '0');
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- process 2
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc173.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00173ent IS
END c04s03b03x01p03n02i00173ent;
ARCHITECTURE c04s03b03x01p03n02i00173arch OF c04s03b03x01p03n02i00173ent IS
signal Addr : bit;
alias SIGN : bit is Addr; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
Addr <= '1' after 10 ns;
wait for 10 ns;
assert NOT( SIGN = '1' )
report "***PASSED TEST: c04s03b03x01p03n02i00173"
severity NOTE;
assert ( SIGN = '1' )
report "***FAILED TEST: c04s03b03x01p03n02i00173 - The base type of the name being defined by the declaration is the same as the base type of the subtype indication test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00173arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc173.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00173ent IS
END c04s03b03x01p03n02i00173ent;
ARCHITECTURE c04s03b03x01p03n02i00173arch OF c04s03b03x01p03n02i00173ent IS
signal Addr : bit;
alias SIGN : bit is Addr; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
Addr <= '1' after 10 ns;
wait for 10 ns;
assert NOT( SIGN = '1' )
report "***PASSED TEST: c04s03b03x01p03n02i00173"
severity NOTE;
assert ( SIGN = '1' )
report "***FAILED TEST: c04s03b03x01p03n02i00173 - The base type of the name being defined by the declaration is the same as the base type of the subtype indication test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00173arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc173.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00173ent IS
END c04s03b03x01p03n02i00173ent;
ARCHITECTURE c04s03b03x01p03n02i00173arch OF c04s03b03x01p03n02i00173ent IS
signal Addr : bit;
alias SIGN : bit is Addr; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
Addr <= '1' after 10 ns;
wait for 10 ns;
assert NOT( SIGN = '1' )
report "***PASSED TEST: c04s03b03x01p03n02i00173"
severity NOTE;
assert ( SIGN = '1' )
report "***FAILED TEST: c04s03b03x01p03n02i00173 - The base type of the name being defined by the declaration is the same as the base type of the subtype indication test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00173arch;
|
-- $Id: sys_conf.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-18 410 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;
|
-- $Id: sys_conf.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-18 410 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;
|
LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ImageFilter_tb IS
END ImageFilter_tb;
ARCHITECTURE behavior OF ImageFilter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ImageFilter
PORT(
Din : IN std_logic_vector(7 downto 0);
CLK : IN std_logic;
WR_EN: IN STD_LOGIC;
RESET : IN std_logic;
m1 : in signed(3 downto 0);
m2 : in signed(3 downto 0);
m3 : in signed(3 downto 0);
m4 : in signed(3 downto 0);
m5 : in signed(3 downto 0);
m6 : in signed(3 downto 0);
m7 : in signed(3 downto 0);
m8 : in signed(3 downto 0);
m9 : in signed(3 downto 0);
RD_EN: OUT STD_LOGIC;
Dout : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal Din : std_logic_vector(7 downto 0) := (others => '0');
signal CLK : std_logic := '0';
signal WR_EN: std_logic := '0';
signal RESET : std_logic := '0';
--Outputs
signal Dout : std_logic_vector(7 downto 0);
signal RD_EN: std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ImageFilter PORT MAP (
Din => Din,
CLK => CLK,
WR_EN => WR_EN,
m1 => m1,
m2 => m2,
m3 => m3,
m4 => m4,
m5 => m5,
m6 => m6,
m7 => m7,
m8 => m8,
m9 => m9,
divider_selector => divider_selector,
RD_EN => RD_EN,
RESET => RESET,
Dout => Dout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Reset process
-- or in one line without using a process
-- reset <= '1', '0' after 10 ns;
rst_proc : process
begin
RESET <= '1';
wait for clk_period * 5;
RESET <= '0';
wait for clk_period * 5;
wait;
end process;
-- Stimulus process
stim_proc1: process
FILE datain : text;
variable linein : line;
variable linein_var :std_logic_vector (7 downto 0);
begin
wait for clk_period * 10;
wait for clk_period * 1;
wr_en <= '1';
file_open (datain,"Lena128x128g_8bits.dat", read_mode);
while not endfile(datain) loop
readline (datain,linein);
read (linein, linein_var);
din <= linein_var; --push 1 pixel/all of its 8 bits into queue
wait for clk_period * 1;
end loop;
file_close (datain);
wr_en <= '0';
-- prog_full_thresh <= "00" & x"02";
-- assert false report "NONE. End of your simulation." severity failure;
wait;
end process;
stim_proc2: process
FILE dataout : text;
variable lineout : line;
variable lineout_var :std_logic_vector (7 downto 0);
begin
wait for clk_period * 10;
while rd_en = '0' loop
wait for clk_period * 1;
end loop;
file_open (dataout,"Lena128x128g_8bits_o.dat", write_mode);
while rd_en = '1' loop
wait for clk_period * 1;
lineout_var := dout;
write (lineout,lineout_var);
writeline (dataout,lineout);
end loop;
file_close (dataout);
wait for clk_period * 10;
assert false report "NONE. End of your simulation." severity failure;
end process;
END; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity adder is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
y : out std_logic_vector(31 downto 0)
);
end entity;
architecture BH of adder is
begin
process(a, b) begin
y <= a + b;
end process;
end BH;
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: lpm_compare0.vhd
-- Megafunction Name(s):
-- lpm_compare
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
AleB : OUT STD_LOGIC
);
END lpm_compare0;
ARCHITECTURE SYN OF lpm_compare0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
AleB : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
AleB <= sub_wire0;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 32
)
PORT MAP (
dataa => dataa,
datab => datab,
AleB => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "1"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: AleB 0 0 0 0 OUTPUT NODEFVAL AleB
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
-- Retrieval info: CONNECT: AleB 0 0 0 0 @AleB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0_inst.vhd TRUE
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.approximationTable.all;
entity static_approximation_wrapper is
generic (
numInj : integer := 268;
numIn : integer := 70;
numOut : integer := 41);
port (
clk : in std_logic;
rst : in std_logic;
injectionVector : in std_logic_vector(numInj-1 downto 0);
testVector : in std_logic_vector(numIn-1 downto 0);
resultVector : out std_logic_vector(numOut-1 downto 0));
end entity static_approximation_wrapper;
architecture struct of static_approximation_wrapper is
component circuit_under_test is
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0);
injectionvector : in std_logic_vector(numInj-1 downto 0));
end component circuit_under_test;
begin -- architecture struct
circuit_under_test_1 : circuit_under_test
port map (
clk => clk,
rst => rst,
testvector => testvector,
resultvector => resultvector,
injectionvector => approximationVector);
end architecture struct;
|
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.utils.all;
use work.memory_map.all;
use work.txt_utils.all;
entity async_ram is
generic (
MEMSIZE :integer := 8
);
port (
address : in addr_t;
din : in word_t;
dout : out word_t;
size : in ctrl_memwidth_t;
wr : in std_logic;
en : in std_logic
);
end entity;
architecture behav of async_ram is
signal data_out : word_t;
type ram_t is array (integer range <>)of byte_t;
signal mem : ram_t (0 to MEMSIZE-1);
signal mem_word0 : word_t;
constant NOCARE : byte_t := (others => '-');
begin
dout <= data_out when en = '1' and wr = '0' else HI_Z;
-- FIXME use size of ram for masking
memwrite: process (address, din, en, wr)
variable index : natural;
begin
index := vtou(address and not mmap(mmap_ram).base);
if en = '1' and wr = '1' then
case size is
when WIDTH_BYTE => mem(index ) <= din( 7 downto 0);
when WIDTH_HALF => mem(index+0) <= din(15 downto 8);
mem(index+1) <= din(7 downto 0);
when WIDTH_WORD => mem(index+0) <= din(31 downto 24);
mem(index+1) <= din(23 downto 16);
mem(index+2) <= din(15 downto 8);
mem(index+3) <= din( 7 downto 0);
when others => null;
end case;
end if;
end process;
memread: process (address, en, wr, size, mem)
variable index : natural;
begin
index := vtou(address and not mmap(mmap_ram).base);
-- printf(ANSI_GREEN & " iNDEX is %d\n", index);
if en = '1' and wr = '0' then
case size is
when WIDTH_BYTE => data_out <= NOCARE & NOCARE & NOCARE & mem(0);
when WIDTH_HALF => data_out <= NOCARE & NOCARE & mem(0) & mem(1);
when WIDTH_WORD => data_out <= mem(0) & mem(1) & mem(2) & mem(3);
when others => null;
end case;
end if;
end process;
mem_word0 <= mem(0) & mem(1) & mem(2) & mem(3); -- this is crappy
end behav;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: Keyboard IP
-- Target Devices:
-- Tool versions: Xilinx ISE 14.4
-- Description:
-- Keyboard Core Top file
--
-- Dependencies:
-- KbdRxData.vhd
-- KbdTxData.vhd
-- KbdDataCtrl.vhd
-- KbdFilter.vhd
-- IOBuffer.xco
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- statusReg :
-- 0 : Full OUTput buffer
-- 1 : Full Input buffer
-- 2 :
-- 3 :
-- 4 :
-- 5 :
-- 6 : Empty Input buffer
-- 7 : Empty OUTput buffer
-- controlReg :
-- 0 :
-- 1 :
-- 2 :
-- 3 :
-- 4 :
-- 5 :
-- 6 :
-- 7 :
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity KbdCore is
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
rdOBuff : IN STD_LOGIC;
wrIBuffer : IN STD_LOGIC;
dataFromHost : IN STD_LOGIC_VECTOR(7 downto 0);
KBData : INOUT STD_LOGIC;
KBClk : INOUT STD_LOGIC;
statusReg : OUT STD_LOGIC_VECTOR(7 downto 0);
dataToHost : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end KbdCore;
architecture Behavioral of KbdCore is
Component KbdTxData
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
Tx_en : IN STD_LOGIC;
kbd_dataf : IN STD_LOGIC;
kbd_clkf : IN STD_LOGIC;
Data : IN STD_LOGIC_VECTOR(7 downto 0);
busy : OUT STD_LOGIC;
T_Data : OUT STD_LOGIC; --when T=0, IO = OUT; when T=1, IO = IN;
T_Clk : OUT STD_LOGIC; --when T=0, IO = OUT; when T=1, IO = IN;
KbdData : OUT STD_LOGIC;
KbdClk : OUT STD_LOGIC
);
end component;
Component KbdRxData
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
kbd_Data : IN STD_LOGIC;
kbd_clk : IN STD_LOGIC;
Rx_en : IN STD_LOGIC;
busy : OUT STD_LOGIC;
dataValid : OUT STD_LOGIC;
Data : OUT STD_LOGIC_VECTOR (7 downto 0)
);
end component;
Component KbdDataCtrl
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
busyRx : IN STD_LOGIC;
busyTx : in STD_LOGIC;
validDataKb : IN STD_LOGIC;
dataInIBuff : IN STD_LOGIC;
DataFromKb : IN STD_LOGIC_VECTOR (7 downto 0);
DataFromIBuff : IN STD_LOGIC_VECTOR (7 downto 0);
Rx_en : OUT STD_LOGIC;
Tx_en : OUT STD_LOGIC;
rd_en : OUT STD_LOGIC;
wr_en : OUT STD_LOGIC;
DataTokb : OUT STD_LOGIC_VECTOR (7 downto 0);
DataToOBuff : OUT STD_LOGIC_VECTOR (7 downto 0)
);
end component;
Component KbdFilter
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
kbdClk : IN STD_LOGIC;
kbdData : IN STD_LOGIC;
kbdClkF : OUT STD_LOGIC;
kbdDataF : OUT STD_LOGIC
);
end component;
COMPONENT IOBuffer
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT IOBUF
PORT (
I : IN std_logic;
IO : INOUT std_logic;
O : OUT std_logic;
T : IN std_logic
);
END COMPONENT;
SIGNAL dataFromKB : STD_LOGIC;
SIGNAL dataToKB : STD_LOGIC;
SIGNAL ClkToKb : STD_LOGIC;
SIGNAL ClkFromKb : STD_LOGIC;
SIGNAL TData : STD_LOGIC; --when T=0, IO = OUT; when T=1, IO = IN;
SIGNAL TClk : STD_LOGIC; --when T=0, IO = OUT; when T=1, IO = IN;
SIGNAL Tx_en : STD_LOGIC;
SIGNAL Rx_en : STD_LOGIC;
SIGNAL busyRx : STD_LOGIC;
SIGNAL busyTx : STD_LOGIC;
SIGNAL dataValid : STD_LOGIC;
SIGNAL kbdDataF : STD_LOGIC;
SIGNAL kbdClkF : STD_LOGIC;
SIGNAL emptyIBuff : STD_LOGIC;
SIGNAL wrOBuff : STD_LOGIC;
SIGNAL rdIBuff : STD_LOGIC;
SIGNAL DataFromIBuff : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL DataToOBuff : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL DataTxKb : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL DataRxKb : STD_LOGIC_VECTOR(7 downto 0);
BEGIN
SendKB: KbdTxData
PORT MAP(
clk => clk,
rst => rst,
Tx_en => Tx_en,
kbd_dataf => kbdDataF,
kbd_clkf => kbdClkF,
Data => DataTxKb,
busy => busyTx,
T_Data => TData,
T_Clk => TClk,
KbdData => dataToKb,
KbdClk => ClkToKb
);
RecieveKb: KbdRxData
PORT MAP(
clk => clk,
rst => rst,
kbd_Data => kbdDataF,
kbd_clk => kbdClkF,
Rx_en => Rx_en,
busy => BusyRx,
dataValid => dataValid,
Data => DataRxKb
);
ProcData:KbdDataCtrl
PORT MAP(
clk => clk,
rst => rst,
busyRx => busyRx,
busyTx => busyTx,
validDataKb => dataValid,
dataInIBuff => emptyIBuff,
DataFromKb => DataRxKb,
DataFromIBuff => DataFromIBuff,
rd_en => rdIBuff,
wr_en => wrOBuff,
Rx_en => Rx_en,
Tx_en => Tx_en,
DataTokb => DataTxKb,
DataToOBuff => DataToOBuff
);
Filter:KbdFilter
PORT MAP(
clk => clk,
rst => rst,
kbdClk => clkFromKb,
kbdData => dataFromKb,
kbdClkF => kbdClkF,
kbdDataF => kbdDataF
);
OBuffer : IOBuffer
PORT MAP (
clk => clk,
rst => rst,
din => DataToOBuff,
wr_en => wrOBuff,
rd_en => rdOBuff,
dOUT => dataToHost,
full => statusReg(0),
empty => statusReg(7)
);
IBuffer : IOBuffer
PORT MAP (
clk => clk,
rst => rst,
din => dataFromHost,
wr_en => wrIBuffer,
rd_en => rdIBuff,
dOUT => DataFromIBuff,
full => statusReg(1),
empty => emptyIBuff
);
IOData: IOBUF
PORT MAP(
I => dataToKb,
IO => KBData,
O => dataFromKB,
T => TData
);
IOClk: IOBUF
PORT MAP(
I => ClkToKb,
IO => KBClk,
O => ClkFromKb,
T => TClk
);
statusReg(6 DOWNTO 2) <= (OTHERS => '0');
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: Keyboard IP
-- Target Devices:
-- Tool versions: Xilinx ISE 14.4
-- Description:
-- Keyboard Core Top file
--
-- Dependencies:
-- KbdRxData.vhd
-- KbdTxData.vhd
-- KbdDataCtrl.vhd
-- KbdFilter.vhd
-- IOBuffer.xco
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- statusReg :
-- 0 : Full OUTput buffer
-- 1 : Full Input buffer
-- 2 :
-- 3 :
-- 4 :
-- 5 :
-- 6 : Empty Input buffer
-- 7 : Empty OUTput buffer
-- controlReg :
-- 0 :
-- 1 :
-- 2 :
-- 3 :
-- 4 :
-- 5 :
-- 6 :
-- 7 :
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity KbdCore is
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
rdOBuff : IN STD_LOGIC;
wrIBuffer : IN STD_LOGIC;
dataFromHost : IN STD_LOGIC_VECTOR(7 downto 0);
KBData : INOUT STD_LOGIC;
KBClk : INOUT STD_LOGIC;
statusReg : OUT STD_LOGIC_VECTOR(7 downto 0);
dataToHost : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end KbdCore;
architecture Behavioral of KbdCore is
Component KbdTxData
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
Tx_en : IN STD_LOGIC;
kbd_dataf : IN STD_LOGIC;
kbd_clkf : IN STD_LOGIC;
Data : IN STD_LOGIC_VECTOR(7 downto 0);
busy : OUT STD_LOGIC;
T_Data : OUT STD_LOGIC; --when T=0, IO = OUT; when T=1, IO = IN;
T_Clk : OUT STD_LOGIC; --when T=0, IO = OUT; when T=1, IO = IN;
KbdData : OUT STD_LOGIC;
KbdClk : OUT STD_LOGIC
);
end component;
Component KbdRxData
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
kbd_Data : IN STD_LOGIC;
kbd_clk : IN STD_LOGIC;
Rx_en : IN STD_LOGIC;
busy : OUT STD_LOGIC;
dataValid : OUT STD_LOGIC;
Data : OUT STD_LOGIC_VECTOR (7 downto 0)
);
end component;
Component KbdDataCtrl
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
busyRx : IN STD_LOGIC;
busyTx : in STD_LOGIC;
validDataKb : IN STD_LOGIC;
dataInIBuff : IN STD_LOGIC;
DataFromKb : IN STD_LOGIC_VECTOR (7 downto 0);
DataFromIBuff : IN STD_LOGIC_VECTOR (7 downto 0);
Rx_en : OUT STD_LOGIC;
Tx_en : OUT STD_LOGIC;
rd_en : OUT STD_LOGIC;
wr_en : OUT STD_LOGIC;
DataTokb : OUT STD_LOGIC_VECTOR (7 downto 0);
DataToOBuff : OUT STD_LOGIC_VECTOR (7 downto 0)
);
end component;
Component KbdFilter
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
kbdClk : IN STD_LOGIC;
kbdData : IN STD_LOGIC;
kbdClkF : OUT STD_LOGIC;
kbdDataF : OUT STD_LOGIC
);
end component;
COMPONENT IOBuffer
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT IOBUF
PORT (
I : IN std_logic;
IO : INOUT std_logic;
O : OUT std_logic;
T : IN std_logic
);
END COMPONENT;
SIGNAL dataFromKB : STD_LOGIC;
SIGNAL dataToKB : STD_LOGIC;
SIGNAL ClkToKb : STD_LOGIC;
SIGNAL ClkFromKb : STD_LOGIC;
SIGNAL TData : STD_LOGIC; --when T=0, IO = OUT; when T=1, IO = IN;
SIGNAL TClk : STD_LOGIC; --when T=0, IO = OUT; when T=1, IO = IN;
SIGNAL Tx_en : STD_LOGIC;
SIGNAL Rx_en : STD_LOGIC;
SIGNAL busyRx : STD_LOGIC;
SIGNAL busyTx : STD_LOGIC;
SIGNAL dataValid : STD_LOGIC;
SIGNAL kbdDataF : STD_LOGIC;
SIGNAL kbdClkF : STD_LOGIC;
SIGNAL emptyIBuff : STD_LOGIC;
SIGNAL wrOBuff : STD_LOGIC;
SIGNAL rdIBuff : STD_LOGIC;
SIGNAL DataFromIBuff : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL DataToOBuff : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL DataTxKb : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL DataRxKb : STD_LOGIC_VECTOR(7 downto 0);
BEGIN
SendKB: KbdTxData
PORT MAP(
clk => clk,
rst => rst,
Tx_en => Tx_en,
kbd_dataf => kbdDataF,
kbd_clkf => kbdClkF,
Data => DataTxKb,
busy => busyTx,
T_Data => TData,
T_Clk => TClk,
KbdData => dataToKb,
KbdClk => ClkToKb
);
RecieveKb: KbdRxData
PORT MAP(
clk => clk,
rst => rst,
kbd_Data => kbdDataF,
kbd_clk => kbdClkF,
Rx_en => Rx_en,
busy => BusyRx,
dataValid => dataValid,
Data => DataRxKb
);
ProcData:KbdDataCtrl
PORT MAP(
clk => clk,
rst => rst,
busyRx => busyRx,
busyTx => busyTx,
validDataKb => dataValid,
dataInIBuff => emptyIBuff,
DataFromKb => DataRxKb,
DataFromIBuff => DataFromIBuff,
rd_en => rdIBuff,
wr_en => wrOBuff,
Rx_en => Rx_en,
Tx_en => Tx_en,
DataTokb => DataTxKb,
DataToOBuff => DataToOBuff
);
Filter:KbdFilter
PORT MAP(
clk => clk,
rst => rst,
kbdClk => clkFromKb,
kbdData => dataFromKb,
kbdClkF => kbdClkF,
kbdDataF => kbdDataF
);
OBuffer : IOBuffer
PORT MAP (
clk => clk,
rst => rst,
din => DataToOBuff,
wr_en => wrOBuff,
rd_en => rdOBuff,
dOUT => dataToHost,
full => statusReg(0),
empty => statusReg(7)
);
IBuffer : IOBuffer
PORT MAP (
clk => clk,
rst => rst,
din => dataFromHost,
wr_en => wrIBuffer,
rd_en => rdIBuff,
dOUT => DataFromIBuff,
full => statusReg(1),
empty => emptyIBuff
);
IOData: IOBUF
PORT MAP(
I => dataToKb,
IO => KBData,
O => dataFromKB,
T => TData
);
IOClk: IOBUF
PORT MAP(
I => ClkToKb,
IO => KBClk,
O => ClkFromKb,
T => TClk
);
statusReg(6 DOWNTO 2) <= (OTHERS => '0');
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
-- VAGE (VHDL Advanced Game Engine) demo using the 'Adventure' game demo and
-- the Altera DE2 board as a hardware platform. The purpose of this file is
-- simply to instantiate the game top entity. It should not contain any game-
-- related code. This is also a perfect place for vendor-specific and board-
-- specific code, such as PLLs.
entity de2_adventure_demo_top is
-- Port names as defined in the standard DE2 settings file.
port (
-- 50 MHz clock provided by the DE2 board
clock_50: in std_logic;
-- Input toggle switches
sw: in std_logic_vector(17 downto 0);
-- Input push-button switches, active low
key: in std_logic_vector(3 downto 0);
-- Green leds
ledg: out std_logic_vector(7 downto 0);
-- Pixel clock for the ADV7123 video DAC
vga_clk: out std_logic;
-- VGA blank signal, high outside of active area
vga_blank: out std_logic;
-- VGA horizontal sync, pulsed low between lines
vga_hs: out std_logic;
-- VGA vertical sync, pulsed low between frames
vga_vs: out std_logic;
-- Composite sync for the ADV7123; if not used, should be tied low
vga_sync: out std_logic;
-- VGA red channel output
vga_r: out std_logic_vector(9 downto 0);
-- VGA green channel output
vga_g: out std_logic_vector(9 downto 0);
-- VGA blue channel output
vga_b: out std_logic_vector(9 downto 0)
);
end;
architecture rtl of de2_adventure_demo_top is
-- Component declaration for the PLL used to generate the 25 MHz pixel
-- clock from the board 50 MHz system clock
component video_pll
port(
inclk0: in std_logic := '0';
c0: out std_logic
);
end component;
signal vga_pll_clock_out: std_logic;
begin
game: entity work.adventure_demo_top
port map(
clock_50_Mhz => clock_50,
reset => sw(17),
debug_bits => ledg,
vga_clock_in => vga_pll_clock_out,
vga_clock_out => vga_clk,
vga_blank => vga_blank,
vga_n_hsync => vga_hs,
vga_n_vsync => vga_vs,
vga_n_sync => vga_sync,
vga_red => vga_r,
vga_green => vga_g,
vga_blue => vga_b,
input_switches => sw(1 downto 0),
input_buttons => not key
);
-- Instantiate a PLL to generate the pixel clock frequency (~25 MHZ),
-- using the DE2 50Mhz clock as input
video_PLL_inst : video_PLL port map (
inclk0 => clock_50,
c0 => vga_pll_clock_out
);
end; |
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`protect end_protected
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_adder_subtractor:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_adder_subtractor_0_1 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_adder_subtractor_0_1;
ARCHITECTURE affine_block_ieee754_fp_adder_subtractor_0_1_arch OF affine_block_ieee754_fp_adder_subtractor_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_adder_subtractor_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_adder_subtractor IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_adder_subtractor;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_adder_subtractor_0_1_arch: ARCHITECTURE IS "ieee754_fp_adder_subtractor,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_adder_subtractor_0_1_arch : ARCHITECTURE IS "affine_block_ieee754_fp_adder_subtractor_0_1,ieee754_fp_adder_subtractor,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_adder_subtractor_0_1_arch: ARCHITECTURE IS "affine_block_ieee754_fp_adder_subtractor_0_1,ieee754_fp_adder_subtractor,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_adder_subtractor,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ieee754_fp_adder_subtractor
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_adder_subtractor_0_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_adder_subtractor:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_adder_subtractor_0_1 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_adder_subtractor_0_1;
ARCHITECTURE affine_block_ieee754_fp_adder_subtractor_0_1_arch OF affine_block_ieee754_fp_adder_subtractor_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_adder_subtractor_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_adder_subtractor IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_adder_subtractor;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_adder_subtractor_0_1_arch: ARCHITECTURE IS "ieee754_fp_adder_subtractor,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_adder_subtractor_0_1_arch : ARCHITECTURE IS "affine_block_ieee754_fp_adder_subtractor_0_1,ieee754_fp_adder_subtractor,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_adder_subtractor_0_1_arch: ARCHITECTURE IS "affine_block_ieee754_fp_adder_subtractor_0_1,ieee754_fp_adder_subtractor,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_adder_subtractor,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ieee754_fp_adder_subtractor
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_adder_subtractor_0_1_arch;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "adc_ltc2351_module"
-- Project :
-------------------------------------------------------------------------------
-- File : adc_ltc2351_module_tb.vhd
-- Author : strongly-typed
-- Company :
-- Created : 2012-04-10
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-- Tests the ADC LTC2351 module including a simulation of the ADC.
-- It is not self checking. The expected result after an ADC cycle (when done
-- went '1' is that the register file (reg_i(0) to reg_i(5)) contains the
-- predefined ADC values from adc_ltc2351_model.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity adc_ltc2351_module_tb is
end adc_ltc2351_module_tb;
-------------------------------------------------------------------------------
architecture tb of adc_ltc2351_module_tb is
use work.adc_ltc2351_pkg.all;
use work.reg_file_pkg.all;
use work.bus_pkg.all;
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 0;
-- component ports
signal adc_out_p : adc_ltc2351_spi_out_type;
signal adc_in_p : adc_ltc2351_spi_in_type;
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type;
signal sck_p : std_logic;
signal conv_p : std_logic;
signal sdo_p : std_logic;
-- clock
signal clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : adc_ltc2351_module
generic map (
BASE_ADDRESS => BASE_ADDRESS
)
port map (
adc_out_p => adc_out_p,
adc_in_p => adc_in_p,
bus_o => bus_o,
bus_i => bus_i,
adc_values_o => open,
done_p => open,
clk => clk
);
STIM : adc_ltc2351_model
port map (
sck => sck_p,
conv => conv_p,
sdo => sdo_p
);
-- --------------------------------------------------------------------------
-- clock generation
-----------------------------------------------------------------------------
clk <= not clk after 10 ns;
sck_p <= adc_out_P.sck;
conv_p <= adc_out_p.conv;
adc_in_p.sdo <= sdo_p;
-- --------------------------------------------------------------------------
-- waveform generation
-- --------------------------------------------------------------------------
-- waveform generation
bus_stimulus_proc : process
begin
bus_i.addr <= (others => '0');
bus_i.data <= (others => '0');
bus_i.re <= '0';
bus_i.we <= '0';
wait until Clk = '1';
-- write 0x01 to 0x00
wait until Clk = '1';
bus_i.addr <= (others => '0');
bus_i.data <= "0000" & "0000" & "0000" & "0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until Clk = '1';
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
-- write 0x01 to 0x01
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.data <= "0000" & "0000" & "0000" & "0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until Clk = '1';
bus_i.data <= (others => '0');
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- read the registers
bus_i.addr(0) <= '0';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- do the same reads, but the DUT shouldn't react
bus_i.addr(0) <= '0';
bus_i.addr(8) <= '0'; -- another address
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
wait for 10000 ns;
end process bus_stimulus_proc;
end tb;
-------------------------------------------------------------------------------
configuration adc_ltc2351_module_tb_tb_cfg of adc_ltc2351_module_tb is
for tb
end for;
end adc_ltc2351_module_tb_tb_cfg;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "adc_ltc2351_module"
-- Project :
-------------------------------------------------------------------------------
-- File : adc_ltc2351_module_tb.vhd
-- Author : strongly-typed
-- Company :
-- Created : 2012-04-10
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-- Tests the ADC LTC2351 module including a simulation of the ADC.
-- It is not self checking. The expected result after an ADC cycle (when done
-- went '1' is that the register file (reg_i(0) to reg_i(5)) contains the
-- predefined ADC values from adc_ltc2351_model.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity adc_ltc2351_module_tb is
end adc_ltc2351_module_tb;
-------------------------------------------------------------------------------
architecture tb of adc_ltc2351_module_tb is
use work.adc_ltc2351_pkg.all;
use work.reg_file_pkg.all;
use work.bus_pkg.all;
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 0;
-- component ports
signal adc_out_p : adc_ltc2351_spi_out_type;
signal adc_in_p : adc_ltc2351_spi_in_type;
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type;
signal sck_p : std_logic;
signal conv_p : std_logic;
signal sdo_p : std_logic;
-- clock
signal clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : adc_ltc2351_module
generic map (
BASE_ADDRESS => BASE_ADDRESS
)
port map (
adc_out_p => adc_out_p,
adc_in_p => adc_in_p,
bus_o => bus_o,
bus_i => bus_i,
adc_values_o => open,
done_p => open,
clk => clk
);
STIM : adc_ltc2351_model
port map (
sck => sck_p,
conv => conv_p,
sdo => sdo_p
);
-- --------------------------------------------------------------------------
-- clock generation
-----------------------------------------------------------------------------
clk <= not clk after 10 ns;
sck_p <= adc_out_P.sck;
conv_p <= adc_out_p.conv;
adc_in_p.sdo <= sdo_p;
-- --------------------------------------------------------------------------
-- waveform generation
-- --------------------------------------------------------------------------
-- waveform generation
bus_stimulus_proc : process
begin
bus_i.addr <= (others => '0');
bus_i.data <= (others => '0');
bus_i.re <= '0';
bus_i.we <= '0';
wait until Clk = '1';
-- write 0x01 to 0x00
wait until Clk = '1';
bus_i.addr <= (others => '0');
bus_i.data <= "0000" & "0000" & "0000" & "0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until Clk = '1';
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
-- write 0x01 to 0x01
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.data <= "0000" & "0000" & "0000" & "0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until Clk = '1';
bus_i.data <= (others => '0');
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- read the registers
bus_i.addr(0) <= '0';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- do the same reads, but the DUT shouldn't react
bus_i.addr(0) <= '0';
bus_i.addr(8) <= '0'; -- another address
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
wait for 10000 ns;
end process bus_stimulus_proc;
end tb;
-------------------------------------------------------------------------------
configuration adc_ltc2351_module_tb_tb_cfg of adc_ltc2351_module_tb is
for tb
end for;
end adc_ltc2351_module_tb_tb_cfg;
-------------------------------------------------------------------------------
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Basic test for functions that work with unbounded vectors as return
-- and param types.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package vhdl_unbounded_func_pkg is
function f_manch_encoder (word_i :std_logic_vector) return std_logic_vector;
end vhdl_unbounded_func_pkg;
package body vhdl_unbounded_func_pkg is
function f_manch_encoder (word_i : std_logic_vector) return std_logic_vector is
variable word_manch_o : std_logic_vector((2*word_i'length) - 1 downto 0);
begin
for I in word_i'range loop
word_manch_o (I*2) := not word_i(I);
word_manch_o (I*2+1) := word_i(I);
end loop;
return word_manch_o;
end function;
end vhdl_unbounded_func_pkg;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Basic test for functions that work with unbounded vectors as return
-- and param types.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package vhdl_unbounded_func_pkg is
function f_manch_encoder (word_i :std_logic_vector) return std_logic_vector;
end vhdl_unbounded_func_pkg;
package body vhdl_unbounded_func_pkg is
function f_manch_encoder (word_i : std_logic_vector) return std_logic_vector is
variable word_manch_o : std_logic_vector((2*word_i'length) - 1 downto 0);
begin
for I in word_i'range loop
word_manch_o (I*2) := not word_i(I);
word_manch_o (I*2+1) := word_i(I);
end loop;
return word_manch_o;
end function;
end vhdl_unbounded_func_pkg;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Basic test for functions that work with unbounded vectors as return
-- and param types.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package vhdl_unbounded_func_pkg is
function f_manch_encoder (word_i :std_logic_vector) return std_logic_vector;
end vhdl_unbounded_func_pkg;
package body vhdl_unbounded_func_pkg is
function f_manch_encoder (word_i : std_logic_vector) return std_logic_vector is
variable word_manch_o : std_logic_vector((2*word_i'length) - 1 downto 0);
begin
for I in word_i'range loop
word_manch_o (I*2) := not word_i(I);
word_manch_o (I*2+1) := word_i(I);
end loop;
return word_manch_o;
end function;
end vhdl_unbounded_func_pkg;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
P_config_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
P_config_V_TVALID : IN STD_LOGIC;
P_config_V_TREADY : OUT STD_LOGIC;
P_WandB_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_WandB_TVALID : IN STD_LOGIC;
P_WandB_TREADY : OUT STD_LOGIC;
P_uOut_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
P_uOut_TVALID : OUT STD_LOGIC;
P_uOut_TREADY : IN STD_LOGIC;
P_netIn_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_netIn_TVALID : IN STD_LOGIC;
P_netIn_TREADY : OUT STD_LOGIC;
P_netOut_V_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0);
P_netOut_V_TVALID : OUT STD_LOGIC;
P_netOut_V_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of feedforward is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"feedforward,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=18,HLS_SYN_DSP=39,HLS_SYN_FF=8096,HLS_SYN_LUT=11564}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (148 downto 0) := "00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (148 downto 0) := "00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (148 downto 0) := "00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (148 downto 0) := "00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (148 downto 0) := "00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st144_fsm_143 : STD_LOGIC_VECTOR (148 downto 0) := "00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st145_fsm_144 : STD_LOGIC_VECTOR (148 downto 0) := "00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st146_fsm_145 : STD_LOGIC_VECTOR (148 downto 0) := "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st147_fsm_146 : STD_LOGIC_VECTOR (148 downto 0) := "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st148_fsm_147 : STD_LOGIC_VECTOR (148 downto 0) := "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st149_fsm_148 : STD_LOGIC_VECTOR (148 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv32_78 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111000";
constant ap_const_lv32_8B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001011";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_58 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011000";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_52 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010010";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_5D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011101";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_5E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011110";
constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
constant ap_const_lv32_70 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110000";
constant ap_const_lv32_4B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001011";
constant ap_const_lv32_71 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv32_4A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001010";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
constant ap_const_lv32_76 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110110";
constant ap_const_lv32_77 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110111";
constant ap_const_lv32_88 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001000";
constant ap_const_lv32_8A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001010";
constant ap_const_lv32_8C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001100";
constant ap_const_lv32_8D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001101";
constant ap_const_lv32_8E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001110";
constant ap_const_lv32_90 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010000";
constant ap_const_lv32_91 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010001";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_92 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010010";
constant ap_const_lv32_93 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010011";
constant ap_const_lv32_94 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010100";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv32_4C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001100";
constant ap_const_lv32_89 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001001";
constant ap_const_lv14_0 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000";
constant ap_const_lv32_8F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001111";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv32_72 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110010";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_53 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010011";
constant ap_const_lv32_59 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011001";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv8_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_const_lv15_23 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100011";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv9_23 : STD_LOGIC_VECTOR (8 downto 0) := "000100011";
constant ap_const_lv9_1FF : STD_LOGIC_VECTOR (8 downto 0) := "111111111";
constant ap_const_lv16_23 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000100011";
constant ap_const_lv9_1FE : STD_LOGIC_VECTOR (8 downto 0) := "111111110";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
constant ap_const_lv8_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
constant ap_const_lv14_23 : STD_LOGIC_VECTOR (13 downto 0) := "00000000100011";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv23_0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_167 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal P_mode_V : STD_LOGIC_VECTOR (7 downto 0);
signal ST_numLayer_V : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_WandB_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal ST_WandB_ce0 : STD_LOGIC;
signal ST_WandB_we0 : STD_LOGIC;
signal ST_WandB_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_WandB_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal feedforward_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal p_uOut_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_565 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_249 : BOOLEAN;
signal ap_sig_cseq_ST_st80_fsm_79 : STD_LOGIC;
signal ap_sig_bdd_256 : BOOLEAN;
signal ap_sig_cseq_ST_st121_fsm_120 : STD_LOGIC;
signal ap_sig_bdd_264 : BOOLEAN;
signal ap_sig_cseq_ST_st140_fsm_139 : STD_LOGIC;
signal ap_sig_bdd_272 : BOOLEAN;
signal reg_572 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_281 : BOOLEAN;
signal ap_sig_cseq_ST_st89_fsm_88 : STD_LOGIC;
signal ap_sig_bdd_290 : BOOLEAN;
signal grp_fu_513_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_578 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_300 : BOOLEAN;
signal ap_sig_cseq_ST_st83_fsm_82 : STD_LOGIC;
signal ap_sig_bdd_307 : BOOLEAN;
signal grp_fu_506_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_317 : BOOLEAN;
signal ap_sig_cseq_ST_st88_fsm_87 : STD_LOGIC;
signal ap_sig_bdd_324 : BOOLEAN;
signal reg_589 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st20_fsm_19 : STD_LOGIC;
signal ap_sig_bdd_333 : BOOLEAN;
signal ap_sig_cseq_ST_st94_fsm_93 : STD_LOGIC;
signal ap_sig_bdd_340 : BOOLEAN;
signal grp_fu_527_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_594 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st21_fsm_20 : STD_LOGIC;
signal ap_sig_bdd_350 : BOOLEAN;
signal ap_sig_cseq_ST_st95_fsm_94 : STD_LOGIC;
signal ap_sig_bdd_357 : BOOLEAN;
signal grp_fu_544_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_599 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st39_fsm_38 : STD_LOGIC;
signal ap_sig_bdd_367 : BOOLEAN;
signal ap_sig_cseq_ST_st113_fsm_112 : STD_LOGIC;
signal ap_sig_bdd_374 : BOOLEAN;
signal grp_fu_524_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_605 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st76_fsm_75 : STD_LOGIC;
signal ap_sig_bdd_384 : BOOLEAN;
signal ap_sig_cseq_ST_st114_fsm_113 : STD_LOGIC;
signal ap_sig_bdd_391 : BOOLEAN;
signal P_mode_V_read_reg_1437 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_611_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_404 : BOOLEAN;
signal tmp_reg_1442 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_numLayer_V_load_reg_1446 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_fu_621_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1454 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_layerSize_V_0_load_reg_1458 : STD_LOGIC_VECTOR (7 downto 0);
signal P_config_V_read_reg_1463 : STD_LOGIC_VECTOR (7 downto 0);
signal i_8_fu_638_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_428 : BOOLEAN;
signal exitcond1_fu_633_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_434 : BOOLEAN;
signal tmp_62_cast_fu_664_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_62_cast_reg_1479 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_444 : BOOLEAN;
signal tmp_7_fu_649_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_668_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_6_reg_1484 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_16_fu_682_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_16_reg_1489 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_20_fu_688_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_20_reg_1494 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_24_fu_711_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_24_reg_1499 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_64_cast_fu_715_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_64_cast_reg_1506 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_26_fu_719_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_26_reg_1511 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_33_fu_729_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_reg_1516 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_35_fu_735_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_35_reg_1521 : STD_LOGIC_VECTOR (1 downto 0);
signal j_5_fu_762_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_5_reg_1529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_474 : BOOLEAN;
signal tmp_19_fu_768_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_reg_1534 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_14_fu_756_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_60_fu_815_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_60_reg_1540 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_1_reg_1546 : STD_LOGIC_VECTOR (7 downto 0);
signal i_10_fu_821_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal k_3_fu_832_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal k_3_reg_1559 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_496 : BOOLEAN;
signal exitcond2_fu_827_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_534_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_30_reg_1579 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st44_fsm_43 : STD_LOGIC;
signal ap_sig_bdd_516 : BOOLEAN;
signal grp_fu_539_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_31_reg_1584 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st75_fsm_74 : STD_LOGIC;
signal ap_sig_bdd_525 : BOOLEAN;
signal tmp_15_fu_894_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_15_reg_1589 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st78_fsm_77 : STD_LOGIC;
signal ap_sig_bdd_534 : BOOLEAN;
signal i_12_fu_917_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_12_reg_1598 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_fu_923_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_23_reg_1603 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_18_fu_911_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_64_fu_974_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_64_reg_1609 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_3_reg_1615 : STD_LOGIC_VECTOR (7 downto 0);
signal j_6_fu_985_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal j_6_reg_1623 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st79_fsm_78 : STD_LOGIC;
signal ap_sig_bdd_555 : BOOLEAN;
signal exitcond3_fu_980_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st119_fsm_118 : STD_LOGIC;
signal ap_sig_bdd_574 : BOOLEAN;
signal i_11_fu_1037_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_11_reg_1651 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st120_fsm_119 : STD_LOGIC;
signal ap_sig_bdd_583 : BOOLEAN;
signal p_uOut_addr_5_reg_1656 : STD_LOGIC_VECTOR (7 downto 0);
signal exitcond4_fu_1032_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_41_fu_1057_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_41_reg_1661 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_519_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_43_reg_1665 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st137_fsm_136 : STD_LOGIC;
signal ap_sig_bdd_601 : BOOLEAN;
signal ap_sig_cseq_ST_st139_fsm_138 : STD_LOGIC;
signal ap_sig_bdd_610 : BOOLEAN;
signal tmp_44_fu_1062_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_ioackin_P_netOut_V_TREADY : STD_LOGIC;
signal tmp_74_fu_1095_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_74_reg_1683 : STD_LOGIC_VECTOR (8 downto 0);
signal next_mul_fu_1099_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal next_mul_reg_1688 : STD_LOGIC_VECTOR (13 downto 0);
signal i_14_fu_1110_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_14_reg_1696 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_fu_1116_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_75_reg_1701 : STD_LOGIC_VECTOR (1 downto 0);
signal exitcond_fu_1105_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_uOut_q1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_4_reg_1706 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_56_fu_1197_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_56_reg_1712 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st141_fsm_140 : STD_LOGIC;
signal ap_sig_bdd_654 : BOOLEAN;
signal p_netOut_V_1_fu_1203_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st142_fsm_141 : STD_LOGIC;
signal ap_sig_bdd_663 : BOOLEAN;
signal i_15_fu_1210_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal j_7_fu_1239_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_7_reg_1730 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st143_fsm_142 : STD_LOGIC;
signal ap_sig_bdd_674 : BOOLEAN;
signal tmp_59_fu_1233_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_fu_1259_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_reg_1740 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st145_fsm_144 : STD_LOGIC;
signal ap_sig_bdd_689 : BOOLEAN;
signal tmp_61_cast_fu_1274_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_cast_reg_1744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_fu_1278_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_4_reg_1749 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_7_t_fu_1282_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_7_t_reg_1753 : STD_LOGIC_VECTOR (1 downto 0);
signal j_4_fu_1288_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_4_reg_1758 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st146_fsm_145 : STD_LOGIC;
signal ap_sig_bdd_707 : BOOLEAN;
signal tmp_46_fu_1333_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_46_reg_1781 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st147_fsm_146 : STD_LOGIC;
signal ap_sig_bdd_732 : BOOLEAN;
signal tmp_11_fu_1298_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_9_fu_1339_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal k_2_fu_1392_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st148_fsm_147 : STD_LOGIC;
signal ap_sig_bdd_748 : BOOLEAN;
signal tmp_22_fu_1386_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_755 : BOOLEAN;
signal exitcond5_fu_1398_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond5_reg_1799 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st149_fsm_148 : STD_LOGIC;
signal ap_sig_bdd_765 : BOOLEAN;
signal ap_sig_bdd_769 : BOOLEAN;
signal i_7_fu_1403_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce0 : STD_LOGIC;
signal p_uOut_we0 : STD_LOGIC;
signal p_uOut_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce1 : STD_LOGIC;
signal i_2_reg_277 : STD_LOGIC_VECTOR (7 downto 0);
signal i_3_reg_288 : STD_LOGIC_VECTOR (7 downto 0);
signal j_1_reg_300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st77_fsm_76 : STD_LOGIC;
signal ap_sig_bdd_800 : BOOLEAN;
signal sum_reg_311 : STD_LOGIC_VECTOR (31 downto 0);
signal k_1_reg_323 : STD_LOGIC_VECTOR (7 downto 0);
signal sumsoft_reg_334 : STD_LOGIC_VECTOR (31 downto 0);
signal i_4_reg_346 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_1_reg_357 : STD_LOGIC_VECTOR (31 downto 0);
signal j_2_reg_369 : STD_LOGIC_VECTOR (7 downto 0);
signal i_5_reg_380 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st138_fsm_137 : STD_LOGIC;
signal ap_sig_bdd_821 : BOOLEAN;
signal p_s_reg_391 : STD_LOGIC_VECTOR (7 downto 0);
signal p_netOut_V_reg_404 : STD_LOGIC_VECTOR (7 downto 0);
signal i_6_reg_416 : STD_LOGIC_VECTOR (7 downto 0);
signal phi_mul_reg_427 : STD_LOGIC_VECTOR (13 downto 0);
signal j_3_reg_438 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st144_fsm_143 : STD_LOGIC;
signal ap_sig_bdd_847 : BOOLEAN;
signal ap_sig_ioackin_P_uOut_TREADY : STD_LOGIC;
signal i_1_reg_449 : STD_LOGIC_VECTOR (7 downto 0);
signal j_reg_461 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_layerSize_V_load_1_phi_reg_473 : STD_LOGIC_VECTOR (7 downto 0);
signal k_reg_484 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_495 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_8_fu_644_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_70_cast_fu_786_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_80_cast_fu_851_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_81_cast_fu_861_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_79_cast_fu_874_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_74_cast_fu_945_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_83_cast_fu_1004_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_84_cast_fu_1014_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_82_cast_fu_1027_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_85_cast_fu_1052_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_87_cast_fu_1076_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_88_cast_fu_1090_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_89_cast_fu_1254_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_78_cast_fu_1354_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_2_fu_1409_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ioackin_P_netOut_V_TREADY : STD_LOGIC := '0';
signal ap_reg_ioackin_P_uOut_TREADY : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st115_fsm_114 : STD_LOGIC;
signal ap_sig_bdd_963 : BOOLEAN;
signal grp_fu_506_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_506_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_987 : BOOLEAN;
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_994 : BOOLEAN;
signal ap_sig_cseq_ST_st84_fsm_83 : STD_LOGIC;
signal ap_sig_bdd_1002 : BOOLEAN;
signal ap_sig_cseq_ST_st90_fsm_89 : STD_LOGIC;
signal ap_sig_bdd_1009 : BOOLEAN;
signal grp_fu_524_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_527_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_fu_889_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_fu_658_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_fu_658_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_3_fu_672_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_16_fu_682_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal lhs_V_1_cast_fu_692_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_fu_695_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_21_fu_705_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_21_fu_705_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal r_V_2_fu_723_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_12_fu_739_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_13_fu_752_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_fu_781_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_49_fu_791_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_51_fu_803_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl2_cast_fu_795_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl3_cast_fu_807_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_33_cast_fu_842_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_69_fu_846_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_33_cast7_fu_838_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_856_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_26_cast_fu_866_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_68_fu_869_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_35_to_int_fu_879_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_35_neg_fu_883_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_fu_907_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_cast_fu_936_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_61_fu_940_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_62_fu_950_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_63_fu_962_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl4_cast_fu_954_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl5_cast_fu_966_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_39_cast_fu_995_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_72_fu_999_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_39_cast6_fu_991_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_73_fu_1009_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_35_cast_fu_1019_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_71_fu_1022_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_42_cast_fu_1043_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_67_fu_1047_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_46_cast_fu_1067_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_76_fu_1071_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_47_cast_fu_1081_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_77_fu_1085_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal p_uOut_load_3_to_int_fu_1120_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_4_to_int_fu_1138_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_48_fu_1124_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_fu_1134_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs_fu_1161_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_1155_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_fu_1141_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_fu_1151_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs1_fu_1179_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_1173_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_52_fu_1167_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_53_fu_1185_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_54_fu_1191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_55_fu_530_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_57_fu_1216_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_58_fu_1229_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_80_fu_1245_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_81_fu_1249_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_s_fu_1268_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_s_fu_1268_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_10_fu_1294_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_39_fu_1304_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_42_fu_1309_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_45_fu_1321_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl_cast_fu_1313_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl1_cast_fu_1325_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_65_fu_1345_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_66_fu_1349_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_25_fu_1359_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal lhs_V_cast_fu_1372_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_fu_1376_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_21_cast_fu_1382_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_506_ce : STD_LOGIC;
signal grp_fu_513_ce : STD_LOGIC;
signal grp_fu_519_ce : STD_LOGIC;
signal tmp_55_fu_530_opcode : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_534_ce : STD_LOGIC;
signal grp_fu_539_ce : STD_LOGIC;
signal grp_fu_544_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (148 downto 0);
signal tmp_16_fu_682_p10 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_5_fu_658_p10 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_s_fu_1268_p10 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_sig_bdd_724 : BOOLEAN;
signal ap_sig_bdd_942 : BOOLEAN;
component feedforward_fadd_32ns_32ns_32_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fmul_32ns_32ns_32_4_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fdiv_32ns_32ns_32_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fptrunc_64ns_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fpext_32ns_64_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_fcmp_32ns_32ns_1_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component feedforward_dadd_64ns_64ns_64_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_ddiv_64ns_64ns_64_31 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_dexp_64ns_64ns_64_18_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_mux_4to1_sel2_8_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
din5_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (7 downto 0);
din3 : IN STD_LOGIC_VECTOR (7 downto 0);
din4 : IN STD_LOGIC_VECTOR (7 downto 0);
din5 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component feedforward_ST_WandB IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_p_uOut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
P_mode_V : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
ST_WandB_U : component feedforward_ST_WandB
generic map (
DataWidth => 32,
AddressRange => 5040,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_WandB_address0,
ce0 => ST_WandB_ce0,
we0 => ST_WandB_we0,
d0 => ST_WandB_d0,
q0 => ST_WandB_q0);
feedforward_AXILiteS_s_axi_U : component feedforward_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => feedforward_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
P_mode_V => P_mode_V);
p_uOut_U : component feedforward_p_uOut
generic map (
DataWidth => 32,
AddressRange => 140,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => p_uOut_address0,
ce0 => p_uOut_ce0,
we0 => p_uOut_we0,
d0 => p_uOut_d0,
q0 => p_uOut_q0,
address1 => p_uOut_address1,
ce1 => p_uOut_ce1,
q1 => p_uOut_q1);
feedforward_fadd_32ns_32ns_32_5_full_dsp_U0 : component feedforward_fadd_32ns_32ns_32_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_506_p0,
din1 => grp_fu_506_p1,
ce => grp_fu_506_ce,
dout => grp_fu_506_p2);
feedforward_fmul_32ns_32ns_32_4_max_dsp_U1 : component feedforward_fmul_32ns_32ns_32_4_max_dsp
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => p_uOut_q0,
din1 => ST_WandB_q0,
ce => grp_fu_513_ce,
dout => grp_fu_513_p2);
feedforward_fdiv_32ns_32ns_32_16_U2 : component feedforward_fdiv_32ns_32ns_32_16
generic map (
ID => 1,
NUM_STAGE => 16,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_565,
din1 => sumsoft_reg_334,
ce => grp_fu_519_ce,
dout => grp_fu_519_p2);
feedforward_fptrunc_64ns_32_1_U3 : component feedforward_fptrunc_64ns_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
dout_WIDTH => 32)
port map (
din0 => grp_fu_524_p0,
dout => grp_fu_524_p1);
feedforward_fpext_32ns_64_1_U4 : component feedforward_fpext_32ns_64_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
din0 => grp_fu_527_p0,
dout => grp_fu_527_p1);
feedforward_fcmp_32ns_32ns_1_1_U5 : component feedforward_fcmp_32ns_32ns_1_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 1)
port map (
din0 => reg_565,
din1 => p_uOut_load_4_reg_1706,
opcode => tmp_55_fu_530_opcode,
dout => tmp_55_fu_530_p2);
feedforward_dadd_64ns_64ns_64_5_full_dsp_U6 : component feedforward_dadd_64ns_64ns_64_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_599,
din1 => ap_const_lv64_3FF0000000000000,
ce => grp_fu_534_ce,
dout => grp_fu_534_p2);
feedforward_ddiv_64ns_64ns_64_31_U7 : component feedforward_ddiv_64ns_64ns_64_31
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_3FF0000000000000,
din1 => tmp_30_reg_1579,
ce => grp_fu_539_ce,
dout => grp_fu_539_p2);
feedforward_dexp_64ns_64ns_64_18_full_dsp_U8 : component feedforward_dexp_64ns_64ns_64_18_full_dsp
generic map (
ID => 1,
NUM_STAGE => 18,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_0,
din1 => reg_594,
ce => grp_fu_544_ce,
dout => grp_fu_544_p2);
feedforward_mux_4to1_sel2_8_1_U9 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_6_reg_1484,
dout => tmp_12_fu_739_p6);
feedforward_mux_4to1_sel2_8_1_U10 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_20_reg_1494,
dout => tmp_19_fu_768_p6);
feedforward_mux_4to1_sel2_8_1_U11 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_26_reg_1511,
dout => tmp_15_fu_894_p6);
feedforward_mux_4to1_sel2_8_1_U12 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_35_reg_1521,
dout => tmp_23_fu_923_p6);
feedforward_mux_4to1_sel2_8_1_U13 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_75_reg_1701,
dout => tmp_57_fu_1216_p6);
feedforward_mux_4to1_sel2_8_1_U14 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_7_t_reg_1753,
dout => tmp_25_fu_1359_p6);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_P_netOut_V_TREADY assign process. --
ap_reg_ioackin_P_netOut_V_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_0;
else
if (ap_sig_bdd_942) then
if (not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY)))) then
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_netOut_V_TREADY)) then
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ioackin_P_uOut_TREADY assign process. --
ap_reg_ioackin_P_uOut_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_uOut_TREADY)) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- ST_layerSize_V_load_1_phi_reg_473 assign process. --
ST_layerSize_V_load_1_phi_reg_473_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
if (ap_sig_bdd_724) then
ST_layerSize_V_load_1_phi_reg_473 <= ST_layerSize_V_3;
elsif ((tmp_4_reg_1749 = ap_const_lv2_2)) then
ST_layerSize_V_load_1_phi_reg_473 <= ST_layerSize_V_2;
elsif ((tmp_4_reg_1749 = ap_const_lv2_1)) then
ST_layerSize_V_load_1_phi_reg_473 <= ST_layerSize_V_1;
end if;
end if;
end if;
end process;
-- i_1_reg_449 assign process. --
i_1_reg_449_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_611_p2 = ap_const_lv1_0) and not(ap_sig_bdd_404) and not((ap_const_lv1_0 = tmp_1_fu_621_p2)))) then
i_1_reg_449 <= ap_const_lv8_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and (ap_const_lv1_0 = tmp_11_fu_1298_p2))) then
i_1_reg_449 <= i_9_fu_1339_p2;
end if;
end if;
end process;
-- i_2_reg_277 assign process. --
i_2_reg_277_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_611_p2 = ap_const_lv1_0) and not(ap_sig_bdd_404) and (ap_const_lv1_0 = tmp_1_fu_621_p2))) then
i_2_reg_277 <= ap_const_lv8_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_633_p2) and not(ap_sig_bdd_434))) then
i_2_reg_277 <= i_8_fu_638_p2;
end if;
end if;
end process;
-- i_3_reg_288 assign process. --
i_3_reg_288_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_434) and not((ap_const_lv1_0 = exitcond1_fu_633_p2)))) then
i_3_reg_288 <= ap_const_lv8_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (ap_const_lv1_0 = tmp_14_fu_756_p2))) then
i_3_reg_288 <= i_10_fu_821_p2;
end if;
end if;
end process;
-- i_4_reg_346 assign process. --
i_4_reg_346_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_7_fu_649_p2))) then
i_4_reg_346 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
i_4_reg_346 <= i_12_reg_1598;
end if;
end if;
end process;
-- i_5_reg_380 assign process. --
i_5_reg_380_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) and (ap_const_lv1_0 = tmp_18_fu_911_p2))) then
i_5_reg_380 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137)) then
i_5_reg_380 <= i_11_reg_1651;
end if;
end if;
end process;
-- i_6_reg_416 assign process. --
i_6_reg_416_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_59_fu_1233_p2))) then
i_6_reg_416 <= i_14_reg_1696;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) and not((ap_const_lv1_0 = exitcond4_fu_1032_p2)) and not((ap_const_lv1_0 = tmp_41_fu_1057_p2)))) then
i_6_reg_416 <= ap_const_lv8_0;
end if;
end if;
end process;
-- i_reg_495 assign process. --
i_reg_495_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and (ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769))) then
i_reg_495 <= i_7_fu_1403_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_611_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_404))) then
i_reg_495 <= ap_const_lv8_0;
end if;
end if;
end process;
-- j_1_reg_300 assign process. --
j_1_reg_300_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = tmp_7_fu_649_p2)))) then
j_1_reg_300 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76)) then
j_1_reg_300 <= j_5_reg_1529;
end if;
end if;
end process;
-- j_2_reg_369 assign process. --
j_2_reg_369_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) and not((ap_const_lv1_0 = tmp_18_fu_911_p2)))) then
j_2_reg_369 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) then
j_2_reg_369 <= j_6_reg_1623;
end if;
end if;
end process;
-- j_3_reg_438 assign process. --
j_3_reg_438_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and (ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_41_reg_1661)) and (ap_const_lv1_0 = exitcond_fu_1105_p2))) then
j_3_reg_438 <= ap_const_lv32_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143) and not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY)))) then
j_3_reg_438 <= j_7_reg_1730;
end if;
end if;
end process;
-- j_reg_461 assign process. --
j_reg_461_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and (ap_const_lv1_0 = tmp_22_fu_1386_p2) and not(ap_sig_bdd_755))) then
j_reg_461 <= j_4_reg_1758;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144) and not((ap_const_lv1_0 = tmp_9_fu_1259_p2)))) then
j_reg_461 <= ap_const_lv32_0;
end if;
end if;
end process;
-- k_1_reg_323 assign process. --
k_1_reg_323_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = tmp_14_fu_756_p2)))) then
k_1_reg_323 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
k_1_reg_323 <= k_3_reg_1559;
end if;
end if;
end process;
-- k_reg_484 assign process. --
k_reg_484_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and not((ap_const_lv1_0 = tmp_11_fu_1298_p2)))) then
k_reg_484 <= ap_const_lv32_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and not((ap_const_lv1_0 = tmp_22_fu_1386_p2)) and not(ap_sig_bdd_755))) then
k_reg_484 <= k_2_fu_1392_p2;
end if;
end if;
end process;
-- p_netOut_V_reg_404 assign process. --
p_netOut_V_reg_404_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) and not((ap_const_lv1_0 = exitcond4_fu_1032_p2)) and (ap_const_lv1_0 = tmp_41_fu_1057_p2))) then
p_netOut_V_reg_404 <= ap_const_lv8_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
p_netOut_V_reg_404 <= i_15_fu_1210_p2;
end if;
end if;
end process;
-- p_s_reg_391 assign process. --
p_s_reg_391_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) and not((ap_const_lv1_0 = exitcond4_fu_1032_p2)) and (ap_const_lv1_0 = tmp_41_fu_1057_p2))) then
p_s_reg_391 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
p_s_reg_391 <= p_netOut_V_1_fu_1203_p3;
end if;
end if;
end process;
-- phi_mul_reg_427 assign process. --
phi_mul_reg_427_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_59_fu_1233_p2))) then
phi_mul_reg_427 <= next_mul_reg_1688;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) and not((ap_const_lv1_0 = exitcond4_fu_1032_p2)) and not((ap_const_lv1_0 = tmp_41_fu_1057_p2)))) then
phi_mul_reg_427 <= ap_const_lv14_0;
end if;
end if;
end process;
-- sum_1_reg_357 assign process. --
sum_1_reg_357_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) and not((ap_const_lv1_0 = tmp_18_fu_911_p2)))) then
sum_1_reg_357 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) then
sum_1_reg_357 <= grp_fu_506_p2;
end if;
end if;
end process;
-- sum_reg_311 assign process. --
sum_reg_311_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = tmp_14_fu_756_p2)))) then
sum_reg_311 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
sum_reg_311 <= grp_fu_506_p2;
end if;
end if;
end process;
-- sumsoft_reg_334 assign process. --
sumsoft_reg_334_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_7_fu_649_p2))) then
sumsoft_reg_334 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
sumsoft_reg_334 <= grp_fu_506_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_611_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_404))) then
P_config_V_read_reg_1463 <= P_config_V_TDATA;
ST_numLayer_V <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_404))) then
P_mode_V_read_reg_1437 <= P_mode_V;
ST_numLayer_V_load_reg_1446 <= ST_numLayer_V;
tmp_reg_1442 <= tmp_fu_611_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and (ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769) and (tmp_2_fu_1409_p1 = ap_const_lv2_0))) then
ST_layerSize_V_0 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_611_p2 = ap_const_lv1_0) and not(ap_sig_bdd_404) and (ap_const_lv1_0 = tmp_1_fu_621_p2))) then
ST_layerSize_V_0_load_reg_1458 <= ST_layerSize_V_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and (ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769) and (ap_const_lv2_1 = tmp_2_fu_1409_p1))) then
ST_layerSize_V_1 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and (ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769) and (ap_const_lv2_2 = tmp_2_fu_1409_p1))) then
ST_layerSize_V_2 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and (ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769) and not((ap_const_lv2_2 = tmp_2_fu_1409_p1)) and not((ap_const_lv2_1 = tmp_2_fu_1409_p1)) and not((tmp_2_fu_1409_p1 = ap_const_lv2_0)))) then
ST_layerSize_V_3 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and not(ap_sig_bdd_769))) then
exitcond5_reg_1799 <= exitcond5_fu_1398_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) then
i_11_reg_1651 <= i_11_fu_1037_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) then
i_12_reg_1598 <= i_12_fu_917_p2;
tmp_15_reg_1589 <= tmp_15_fu_894_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and (ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_41_reg_1661)))) then
i_14_reg_1696 <= i_14_fu_1110_p2;
next_mul_reg_1688 <= next_mul_fu_1099_p2;
tmp_74_reg_1683 <= tmp_74_fu_1095_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
j_4_reg_1758 <= j_4_fu_1288_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
j_5_reg_1529 <= j_5_fu_762_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
j_6_reg_1623 <= j_6_fu_985_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
j_7_reg_1730 <= j_7_fu_1239_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
k_3_reg_1559 <= k_3_fu_832_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = tmp_14_fu_756_p2)))) then
p_uOut_addr_1_reg_1546 <= tmp_70_cast_fu_786_p1(8 - 1 downto 0);
tmp_19_reg_1534 <= tmp_19_fu_768_p6;
tmp_60_reg_1540(13 downto 2) <= tmp_60_fu_815_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) and not((ap_const_lv1_0 = tmp_18_fu_911_p2)))) then
p_uOut_addr_3_reg_1615 <= tmp_74_cast_fu_945_p1(8 - 1 downto 0);
tmp_23_reg_1603 <= tmp_23_fu_923_p6;
tmp_64_reg_1609(13 downto 2) <= tmp_64_fu_974_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) and (ap_const_lv1_0 = exitcond4_fu_1032_p2))) then
p_uOut_addr_5_reg_1656 <= tmp_85_cast_fu_1052_p1(8 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st140_fsm_139)) then
p_uOut_load_4_reg_1706 <= p_uOut_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) or (ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_120) or (ap_const_logic_1 = ap_sig_cseq_ST_st140_fsm_139))) then
reg_565 <= p_uOut_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88))) then
reg_572 <= ST_WandB_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82))) then
reg_578 <= grp_fu_513_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
reg_589 <= grp_fu_506_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or (ap_const_logic_1 = ap_sig_cseq_ST_st95_fsm_94))) then
reg_594 <= grp_fu_527_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_38) or (ap_const_logic_1 = ap_sig_cseq_ST_st113_fsm_112))) then
reg_599 <= grp_fu_544_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st76_fsm_75) or (ap_const_logic_1 = ap_sig_cseq_ST_st114_fsm_113))) then
reg_605 <= grp_fu_524_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = tmp_7_fu_649_p2)))) then
tmp_16_reg_1489 <= tmp_16_fu_682_p2;
tmp_20_reg_1494 <= tmp_20_fu_688_p1;
tmp_62_cast_reg_1479(14 downto 0) <= tmp_62_cast_fu_664_p1(14 downto 0);
tmp_6_reg_1484 <= tmp_6_fu_668_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_611_p2 = ap_const_lv1_0) and not(ap_sig_bdd_404))) then
tmp_1_reg_1454 <= tmp_1_fu_621_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_7_fu_649_p2))) then
tmp_24_reg_1499 <= tmp_24_fu_711_p1;
tmp_26_reg_1511 <= tmp_26_fu_719_p1;
tmp_33_reg_1516 <= tmp_33_fu_729_p2;
tmp_35_reg_1521 <= tmp_35_fu_735_p1;
tmp_64_cast_reg_1506 <= tmp_64_cast_fu_715_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43)) then
tmp_30_reg_1579 <= grp_fu_534_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st75_fsm_74)) then
tmp_31_reg_1584 <= grp_fu_539_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) and not((ap_const_lv1_0 = exitcond4_fu_1032_p2)))) then
tmp_41_reg_1661 <= tmp_41_fu_1057_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st137_fsm_136)) then
tmp_43_reg_1665 <= grp_fu_519_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and not((ap_const_lv1_0 = tmp_11_fu_1298_p2)))) then
tmp_46_reg_1781(13 downto 2) <= tmp_46_fu_1333_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144) and not((ap_const_lv1_0 = tmp_9_fu_1259_p2)))) then
tmp_4_reg_1749 <= tmp_4_fu_1278_p1;
tmp_61_cast_reg_1744(14 downto 0) <= tmp_61_cast_fu_1274_p1(14 downto 0);
tmp_7_t_reg_1753 <= tmp_7_t_fu_1282_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) then
tmp_56_reg_1712 <= tmp_56_fu_1197_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and (ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_41_reg_1661)) and (ap_const_lv1_0 = exitcond_fu_1105_p2))) then
tmp_75_reg_1701 <= tmp_75_fu_1116_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144)) then
tmp_9_reg_1740 <= tmp_9_fu_1259_p2;
end if;
end if;
end process;
tmp_62_cast_reg_1479(31 downto 15) <= "00000000000000000";
tmp_60_reg_1540(1 downto 0) <= "00";
tmp_64_reg_1609(1 downto 0) <= "00";
tmp_61_cast_reg_1744(31 downto 15) <= "00000000000000000";
tmp_46_reg_1781(1 downto 0) <= "00";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, tmp_fu_611_p2, ap_sig_bdd_404, tmp_reg_1442, tmp_1_fu_621_p2, tmp_1_reg_1454, exitcond1_fu_633_p2, ap_sig_bdd_434, tmp_7_fu_649_p2, tmp_14_fu_756_p2, exitcond2_fu_827_p2, tmp_18_fu_911_p2, exitcond3_fu_980_p2, exitcond4_fu_1032_p2, tmp_41_reg_1661, tmp_44_fu_1062_p2, ap_sig_ioackin_P_netOut_V_TREADY, exitcond_fu_1105_p2, tmp_59_fu_1233_p2, tmp_9_fu_1259_p2, tmp_9_reg_1740, tmp_11_fu_1298_p2, tmp_22_fu_1386_p2, ap_sig_bdd_755, exitcond5_fu_1398_p2, exitcond5_reg_1799, ap_sig_bdd_769, ap_sig_ioackin_P_uOut_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if ((not((tmp_fu_611_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_404))) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
elsif (((tmp_fu_611_p2 = ap_const_lv1_0) and not(ap_sig_bdd_404) and (ap_const_lv1_0 = tmp_1_fu_621_p2))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((tmp_fu_611_p2 = ap_const_lv1_0) and not(ap_sig_bdd_404) and not((ap_const_lv1_0 = tmp_1_fu_621_p2)))) then
ap_NS_fsm <= ap_ST_st145_fsm_144;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (((ap_const_lv1_0 = exitcond1_fu_633_p2) and not(ap_sig_bdd_434))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not(ap_sig_bdd_434) and not((ap_const_lv1_0 = exitcond1_fu_633_p2)))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if ((ap_const_lv1_0 = tmp_7_fu_649_p2)) then
ap_NS_fsm <= ap_ST_st78_fsm_77;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st4_fsm_3 =>
if ((ap_const_lv1_0 = tmp_14_fu_756_p2)) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
if (not((ap_const_lv1_0 = exitcond2_fu_827_p2))) then
ap_NS_fsm <= ap_ST_st15_fsm_14;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st78_fsm_77 =>
if (not((ap_const_lv1_0 = tmp_18_fu_911_p2))) then
ap_NS_fsm <= ap_ST_st79_fsm_78;
else
ap_NS_fsm <= ap_ST_st120_fsm_119;
end if;
when ap_ST_st79_fsm_78 =>
if (not((ap_const_lv1_0 = exitcond3_fu_980_p2))) then
ap_NS_fsm <= ap_ST_st89_fsm_88;
else
ap_NS_fsm <= ap_ST_st80_fsm_79;
end if;
when ap_ST_st80_fsm_79 =>
ap_NS_fsm <= ap_ST_st81_fsm_80;
when ap_ST_st81_fsm_80 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st82_fsm_81 =>
ap_NS_fsm <= ap_ST_st83_fsm_82;
when ap_ST_st83_fsm_82 =>
ap_NS_fsm <= ap_ST_st84_fsm_83;
when ap_ST_st84_fsm_83 =>
ap_NS_fsm <= ap_ST_st85_fsm_84;
when ap_ST_st85_fsm_84 =>
ap_NS_fsm <= ap_ST_st86_fsm_85;
when ap_ST_st86_fsm_85 =>
ap_NS_fsm <= ap_ST_st87_fsm_86;
when ap_ST_st87_fsm_86 =>
ap_NS_fsm <= ap_ST_st88_fsm_87;
when ap_ST_st88_fsm_87 =>
ap_NS_fsm <= ap_ST_st79_fsm_78;
when ap_ST_st89_fsm_88 =>
ap_NS_fsm <= ap_ST_st90_fsm_89;
when ap_ST_st90_fsm_89 =>
ap_NS_fsm <= ap_ST_st91_fsm_90;
when ap_ST_st91_fsm_90 =>
ap_NS_fsm <= ap_ST_st92_fsm_91;
when ap_ST_st92_fsm_91 =>
ap_NS_fsm <= ap_ST_st93_fsm_92;
when ap_ST_st93_fsm_92 =>
ap_NS_fsm <= ap_ST_st94_fsm_93;
when ap_ST_st94_fsm_93 =>
ap_NS_fsm <= ap_ST_st95_fsm_94;
when ap_ST_st95_fsm_94 =>
ap_NS_fsm <= ap_ST_st96_fsm_95;
when ap_ST_st96_fsm_95 =>
ap_NS_fsm <= ap_ST_st97_fsm_96;
when ap_ST_st97_fsm_96 =>
ap_NS_fsm <= ap_ST_st98_fsm_97;
when ap_ST_st98_fsm_97 =>
ap_NS_fsm <= ap_ST_st99_fsm_98;
when ap_ST_st99_fsm_98 =>
ap_NS_fsm <= ap_ST_st100_fsm_99;
when ap_ST_st100_fsm_99 =>
ap_NS_fsm <= ap_ST_st101_fsm_100;
when ap_ST_st101_fsm_100 =>
ap_NS_fsm <= ap_ST_st102_fsm_101;
when ap_ST_st102_fsm_101 =>
ap_NS_fsm <= ap_ST_st103_fsm_102;
when ap_ST_st103_fsm_102 =>
ap_NS_fsm <= ap_ST_st104_fsm_103;
when ap_ST_st104_fsm_103 =>
ap_NS_fsm <= ap_ST_st105_fsm_104;
when ap_ST_st105_fsm_104 =>
ap_NS_fsm <= ap_ST_st106_fsm_105;
when ap_ST_st106_fsm_105 =>
ap_NS_fsm <= ap_ST_st107_fsm_106;
when ap_ST_st107_fsm_106 =>
ap_NS_fsm <= ap_ST_st108_fsm_107;
when ap_ST_st108_fsm_107 =>
ap_NS_fsm <= ap_ST_st109_fsm_108;
when ap_ST_st109_fsm_108 =>
ap_NS_fsm <= ap_ST_st110_fsm_109;
when ap_ST_st110_fsm_109 =>
ap_NS_fsm <= ap_ST_st111_fsm_110;
when ap_ST_st111_fsm_110 =>
ap_NS_fsm <= ap_ST_st112_fsm_111;
when ap_ST_st112_fsm_111 =>
ap_NS_fsm <= ap_ST_st113_fsm_112;
when ap_ST_st113_fsm_112 =>
ap_NS_fsm <= ap_ST_st114_fsm_113;
when ap_ST_st114_fsm_113 =>
ap_NS_fsm <= ap_ST_st115_fsm_114;
when ap_ST_st115_fsm_114 =>
ap_NS_fsm <= ap_ST_st116_fsm_115;
when ap_ST_st116_fsm_115 =>
ap_NS_fsm <= ap_ST_st117_fsm_116;
when ap_ST_st117_fsm_116 =>
ap_NS_fsm <= ap_ST_st118_fsm_117;
when ap_ST_st118_fsm_117 =>
ap_NS_fsm <= ap_ST_st119_fsm_118;
when ap_ST_st119_fsm_118 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st120_fsm_119 =>
if (not((ap_const_lv1_0 = exitcond4_fu_1032_p2))) then
ap_NS_fsm <= ap_ST_st139_fsm_138;
else
ap_NS_fsm <= ap_ST_st121_fsm_120;
end if;
when ap_ST_st121_fsm_120 =>
ap_NS_fsm <= ap_ST_st122_fsm_121;
when ap_ST_st122_fsm_121 =>
ap_NS_fsm <= ap_ST_st123_fsm_122;
when ap_ST_st123_fsm_122 =>
ap_NS_fsm <= ap_ST_st124_fsm_123;
when ap_ST_st124_fsm_123 =>
ap_NS_fsm <= ap_ST_st125_fsm_124;
when ap_ST_st125_fsm_124 =>
ap_NS_fsm <= ap_ST_st126_fsm_125;
when ap_ST_st126_fsm_125 =>
ap_NS_fsm <= ap_ST_st127_fsm_126;
when ap_ST_st127_fsm_126 =>
ap_NS_fsm <= ap_ST_st128_fsm_127;
when ap_ST_st128_fsm_127 =>
ap_NS_fsm <= ap_ST_st129_fsm_128;
when ap_ST_st129_fsm_128 =>
ap_NS_fsm <= ap_ST_st130_fsm_129;
when ap_ST_st130_fsm_129 =>
ap_NS_fsm <= ap_ST_st131_fsm_130;
when ap_ST_st131_fsm_130 =>
ap_NS_fsm <= ap_ST_st132_fsm_131;
when ap_ST_st132_fsm_131 =>
ap_NS_fsm <= ap_ST_st133_fsm_132;
when ap_ST_st133_fsm_132 =>
ap_NS_fsm <= ap_ST_st134_fsm_133;
when ap_ST_st134_fsm_133 =>
ap_NS_fsm <= ap_ST_st135_fsm_134;
when ap_ST_st135_fsm_134 =>
ap_NS_fsm <= ap_ST_st136_fsm_135;
when ap_ST_st136_fsm_135 =>
ap_NS_fsm <= ap_ST_st137_fsm_136;
when ap_ST_st137_fsm_136 =>
ap_NS_fsm <= ap_ST_st138_fsm_137;
when ap_ST_st138_fsm_137 =>
ap_NS_fsm <= ap_ST_st120_fsm_119;
when ap_ST_st139_fsm_138 =>
if ((not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2)) or (not((ap_const_lv1_0 = tmp_reg_1442)) and not((ap_const_lv1_0 = exitcond5_reg_1799))) or ((ap_const_lv1_0 = tmp_reg_1442) and not((ap_const_lv1_0 = tmp_1_reg_1454)) and (ap_const_lv1_0 = tmp_9_reg_1740)) or ((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not((ap_const_lv1_0 = tmp_41_reg_1661)) and not((ap_const_lv1_0 = exitcond_fu_1105_p2)))))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
elsif (((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_41_reg_1661)) and (ap_const_lv1_0 = exitcond_fu_1105_p2))) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
elsif (((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_44_fu_1062_p2)))) then
ap_NS_fsm <= ap_ST_st140_fsm_139;
else
ap_NS_fsm <= ap_ST_st139_fsm_138;
end if;
when ap_ST_st140_fsm_139 =>
ap_NS_fsm <= ap_ST_st141_fsm_140;
when ap_ST_st141_fsm_140 =>
ap_NS_fsm <= ap_ST_st142_fsm_141;
when ap_ST_st142_fsm_141 =>
ap_NS_fsm <= ap_ST_st139_fsm_138;
when ap_ST_st143_fsm_142 =>
if (not((ap_const_lv1_0 = tmp_59_fu_1233_p2))) then
ap_NS_fsm <= ap_ST_st144_fsm_143;
else
ap_NS_fsm <= ap_ST_st139_fsm_138;
end if;
when ap_ST_st144_fsm_143 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
else
ap_NS_fsm <= ap_ST_st144_fsm_143;
end if;
when ap_ST_st145_fsm_144 =>
if (not((ap_const_lv1_0 = tmp_9_fu_1259_p2))) then
ap_NS_fsm <= ap_ST_st146_fsm_145;
else
ap_NS_fsm <= ap_ST_st139_fsm_138;
end if;
when ap_ST_st146_fsm_145 =>
ap_NS_fsm <= ap_ST_st147_fsm_146;
when ap_ST_st147_fsm_146 =>
if ((ap_const_lv1_0 = tmp_11_fu_1298_p2)) then
ap_NS_fsm <= ap_ST_st145_fsm_144;
else
ap_NS_fsm <= ap_ST_st148_fsm_147;
end if;
when ap_ST_st148_fsm_147 =>
if ((not((ap_const_lv1_0 = tmp_22_fu_1386_p2)) and not(ap_sig_bdd_755))) then
ap_NS_fsm <= ap_ST_st148_fsm_147;
elsif (((ap_const_lv1_0 = tmp_22_fu_1386_p2) and not(ap_sig_bdd_755))) then
ap_NS_fsm <= ap_ST_st146_fsm_145;
else
ap_NS_fsm <= ap_ST_st148_fsm_147;
end if;
when ap_ST_st149_fsm_148 =>
if (((ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769))) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
elsif ((not(ap_sig_bdd_769) and not((ap_const_lv1_0 = exitcond5_fu_1398_p2)))) then
ap_NS_fsm <= ap_ST_st139_fsm_138;
else
ap_NS_fsm <= ap_ST_st149_fsm_148;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- P_WandB_TREADY assign process. --
P_WandB_TREADY_assign_proc : process(ap_sig_cseq_ST_st148_fsm_147, tmp_22_fu_1386_p2, ap_sig_bdd_755)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and not((ap_const_lv1_0 = tmp_22_fu_1386_p2)) and not(ap_sig_bdd_755))) then
P_WandB_TREADY <= ap_const_logic_1;
else
P_WandB_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_config_V_TREADY assign process. --
P_config_V_TREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, tmp_fu_611_p2, ap_sig_bdd_404, exitcond5_fu_1398_p2, ap_sig_cseq_ST_st149_fsm_148, ap_sig_bdd_769)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_611_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_404)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and (ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769)))) then
P_config_V_TREADY <= ap_const_logic_1;
else
P_config_V_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_netIn_TREADY assign process. --
P_netIn_TREADY_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_633_p2, ap_sig_bdd_434)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_633_p2) and not(ap_sig_bdd_434))) then
P_netIn_TREADY <= ap_const_logic_1;
else
P_netIn_TREADY <= ap_const_logic_0;
end if;
end process;
P_netOut_V_TDATA <= p_s_reg_391;
-- P_netOut_V_TVALID assign process. --
P_netOut_V_TVALID_assign_proc : process(tmp_reg_1442, tmp_1_reg_1454, tmp_41_reg_1661, ap_sig_cseq_ST_st139_fsm_138, tmp_44_fu_1062_p2, ap_reg_ioackin_P_netOut_V_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and (ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_reg_ioackin_P_netOut_V_TREADY))) then
P_netOut_V_TVALID <= ap_const_logic_1;
else
P_netOut_V_TVALID <= ap_const_logic_0;
end if;
end process;
P_uOut_TDATA <= p_uOut_q1;
-- P_uOut_TVALID assign process. --
P_uOut_TVALID_assign_proc : process(ap_sig_cseq_ST_st144_fsm_143, ap_reg_ioackin_P_uOut_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143) and (ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY))) then
P_uOut_TVALID <= ap_const_logic_1;
else
P_uOut_TVALID <= ap_const_logic_0;
end if;
end process;
-- ST_WandB_address0 assign process. --
ST_WandB_address0_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4, exitcond2_fu_827_p2, ap_sig_cseq_ST_st79_fsm_78, exitcond3_fu_980_p2, ap_sig_cseq_ST_st148_fsm_147, tmp_80_cast_fu_851_p1, tmp_79_cast_fu_874_p1, tmp_83_cast_fu_1004_p1, tmp_82_cast_fu_1027_p1, tmp_78_cast_fu_1354_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147)) then
ST_WandB_address0 <= tmp_78_cast_fu_1354_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and not((ap_const_lv1_0 = exitcond3_fu_980_p2)))) then
ST_WandB_address0 <= tmp_82_cast_fu_1027_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and (ap_const_lv1_0 = exitcond3_fu_980_p2))) then
ST_WandB_address0 <= tmp_83_cast_fu_1004_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((ap_const_lv1_0 = exitcond2_fu_827_p2)))) then
ST_WandB_address0 <= tmp_79_cast_fu_874_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (ap_const_lv1_0 = exitcond2_fu_827_p2))) then
ST_WandB_address0 <= tmp_80_cast_fu_851_p1(13 - 1 downto 0);
else
ST_WandB_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- ST_WandB_ce0 assign process. --
ST_WandB_ce0_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4, exitcond2_fu_827_p2, ap_sig_cseq_ST_st79_fsm_78, exitcond3_fu_980_p2, ap_sig_cseq_ST_st148_fsm_147, ap_sig_bdd_755)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (ap_const_lv1_0 = exitcond2_fu_827_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((ap_const_lv1_0 = exitcond2_fu_827_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and (ap_const_lv1_0 = exitcond3_fu_980_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and not((ap_const_lv1_0 = exitcond3_fu_980_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and not(ap_sig_bdd_755)))) then
ST_WandB_ce0 <= ap_const_logic_1;
else
ST_WandB_ce0 <= ap_const_logic_0;
end if;
end process;
ST_WandB_d0 <= P_WandB_TDATA;
-- ST_WandB_we0 assign process. --
ST_WandB_we0_assign_proc : process(ap_sig_cseq_ST_st148_fsm_147, tmp_22_fu_1386_p2, ap_sig_bdd_755)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and not((ap_const_lv1_0 = tmp_22_fu_1386_p2)) and not(ap_sig_bdd_755)))) then
ST_WandB_we0 <= ap_const_logic_1;
else
ST_WandB_we0 <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(tmp_reg_1442, tmp_1_reg_1454, tmp_41_reg_1661, ap_sig_cseq_ST_st139_fsm_138, tmp_44_fu_1062_p2, ap_sig_ioackin_P_netOut_V_TREADY, exitcond_fu_1105_p2, tmp_9_reg_1740, exitcond5_reg_1799)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2)) or (not((ap_const_lv1_0 = tmp_reg_1442)) and not((ap_const_lv1_0 = exitcond5_reg_1799))) or ((ap_const_lv1_0 = tmp_reg_1442) and not((ap_const_lv1_0 = tmp_1_reg_1454)) and (ap_const_lv1_0 = tmp_9_reg_1740)) or ((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not((ap_const_lv1_0 = tmp_41_reg_1661)) and not((ap_const_lv1_0 = exitcond_fu_1105_p2)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(tmp_reg_1442, tmp_1_reg_1454, tmp_41_reg_1661, ap_sig_cseq_ST_st139_fsm_138, tmp_44_fu_1062_p2, ap_sig_ioackin_P_netOut_V_TREADY, exitcond_fu_1105_p2, tmp_9_reg_1740, exitcond5_reg_1799)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2)) or (not((ap_const_lv1_0 = tmp_reg_1442)) and not((ap_const_lv1_0 = exitcond5_reg_1799))) or ((ap_const_lv1_0 = tmp_reg_1442) and not((ap_const_lv1_0 = tmp_1_reg_1454)) and (ap_const_lv1_0 = tmp_9_reg_1740)) or ((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not((ap_const_lv1_0 = tmp_41_reg_1661)) and not((ap_const_lv1_0 = exitcond_fu_1105_p2)))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_1002 assign process. --
ap_sig_bdd_1002_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1002 <= (ap_const_lv1_1 = ap_CS_fsm(83 downto 83));
end process;
-- ap_sig_bdd_1009 assign process. --
ap_sig_bdd_1009_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1009 <= (ap_const_lv1_1 = ap_CS_fsm(89 downto 89));
end process;
-- ap_sig_bdd_167 assign process. --
ap_sig_bdd_167_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_167 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_249 assign process. --
ap_sig_bdd_249_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_249 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_256 assign process. --
ap_sig_bdd_256_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_256 <= (ap_const_lv1_1 = ap_CS_fsm(79 downto 79));
end process;
-- ap_sig_bdd_264 assign process. --
ap_sig_bdd_264_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_264 <= (ap_const_lv1_1 = ap_CS_fsm(120 downto 120));
end process;
-- ap_sig_bdd_272 assign process. --
ap_sig_bdd_272_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_272 <= (ap_const_lv1_1 = ap_CS_fsm(139 downto 139));
end process;
-- ap_sig_bdd_281 assign process. --
ap_sig_bdd_281_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_281 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_290 assign process. --
ap_sig_bdd_290_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_290 <= (ap_const_lv1_1 = ap_CS_fsm(88 downto 88));
end process;
-- ap_sig_bdd_300 assign process. --
ap_sig_bdd_300_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_300 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_307 assign process. --
ap_sig_bdd_307_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_307 <= (ap_const_lv1_1 = ap_CS_fsm(82 downto 82));
end process;
-- ap_sig_bdd_317 assign process. --
ap_sig_bdd_317_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_317 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_324 assign process. --
ap_sig_bdd_324_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_324 <= (ap_const_lv1_1 = ap_CS_fsm(87 downto 87));
end process;
-- ap_sig_bdd_333 assign process. --
ap_sig_bdd_333_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_333 <= (ap_const_lv1_1 = ap_CS_fsm(19 downto 19));
end process;
-- ap_sig_bdd_340 assign process. --
ap_sig_bdd_340_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_340 <= (ap_const_lv1_1 = ap_CS_fsm(93 downto 93));
end process;
-- ap_sig_bdd_350 assign process. --
ap_sig_bdd_350_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_350 <= (ap_const_lv1_1 = ap_CS_fsm(20 downto 20));
end process;
-- ap_sig_bdd_357 assign process. --
ap_sig_bdd_357_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_357 <= (ap_const_lv1_1 = ap_CS_fsm(94 downto 94));
end process;
-- ap_sig_bdd_367 assign process. --
ap_sig_bdd_367_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_367 <= (ap_const_lv1_1 = ap_CS_fsm(38 downto 38));
end process;
-- ap_sig_bdd_374 assign process. --
ap_sig_bdd_374_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_374 <= (ap_const_lv1_1 = ap_CS_fsm(112 downto 112));
end process;
-- ap_sig_bdd_384 assign process. --
ap_sig_bdd_384_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_384 <= (ap_const_lv1_1 = ap_CS_fsm(75 downto 75));
end process;
-- ap_sig_bdd_391 assign process. --
ap_sig_bdd_391_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_391 <= (ap_const_lv1_1 = ap_CS_fsm(113 downto 113));
end process;
-- ap_sig_bdd_404 assign process. --
ap_sig_bdd_404_assign_proc : process(ap_start, P_config_V_TVALID, tmp_fu_611_p2)
begin
ap_sig_bdd_404 <= (((P_config_V_TVALID = ap_const_logic_0) and not((tmp_fu_611_p2 = ap_const_lv1_0))) or (ap_start = ap_const_logic_0));
end process;
-- ap_sig_bdd_428 assign process. --
ap_sig_bdd_428_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_428 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_434 assign process. --
ap_sig_bdd_434_assign_proc : process(P_netIn_TVALID, exitcond1_fu_633_p2)
begin
ap_sig_bdd_434 <= ((P_netIn_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = exitcond1_fu_633_p2));
end process;
-- ap_sig_bdd_444 assign process. --
ap_sig_bdd_444_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_444 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_474 assign process. --
ap_sig_bdd_474_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_474 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_496 assign process. --
ap_sig_bdd_496_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_496 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_516 assign process. --
ap_sig_bdd_516_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_516 <= (ap_const_lv1_1 = ap_CS_fsm(43 downto 43));
end process;
-- ap_sig_bdd_525 assign process. --
ap_sig_bdd_525_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_525 <= (ap_const_lv1_1 = ap_CS_fsm(74 downto 74));
end process;
-- ap_sig_bdd_534 assign process. --
ap_sig_bdd_534_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_534 <= (ap_const_lv1_1 = ap_CS_fsm(77 downto 77));
end process;
-- ap_sig_bdd_555 assign process. --
ap_sig_bdd_555_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_555 <= (ap_const_lv1_1 = ap_CS_fsm(78 downto 78));
end process;
-- ap_sig_bdd_574 assign process. --
ap_sig_bdd_574_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_574 <= (ap_const_lv1_1 = ap_CS_fsm(118 downto 118));
end process;
-- ap_sig_bdd_583 assign process. --
ap_sig_bdd_583_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_583 <= (ap_const_lv1_1 = ap_CS_fsm(119 downto 119));
end process;
-- ap_sig_bdd_601 assign process. --
ap_sig_bdd_601_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_601 <= (ap_const_lv1_1 = ap_CS_fsm(136 downto 136));
end process;
-- ap_sig_bdd_610 assign process. --
ap_sig_bdd_610_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_610 <= (ap_const_lv1_1 = ap_CS_fsm(138 downto 138));
end process;
-- ap_sig_bdd_654 assign process. --
ap_sig_bdd_654_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_654 <= (ap_const_lv1_1 = ap_CS_fsm(140 downto 140));
end process;
-- ap_sig_bdd_663 assign process. --
ap_sig_bdd_663_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_663 <= (ap_const_lv1_1 = ap_CS_fsm(141 downto 141));
end process;
-- ap_sig_bdd_674 assign process. --
ap_sig_bdd_674_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_674 <= (ap_const_lv1_1 = ap_CS_fsm(142 downto 142));
end process;
-- ap_sig_bdd_689 assign process. --
ap_sig_bdd_689_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_689 <= (ap_const_lv1_1 = ap_CS_fsm(144 downto 144));
end process;
-- ap_sig_bdd_707 assign process. --
ap_sig_bdd_707_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_707 <= (ap_const_lv1_1 = ap_CS_fsm(145 downto 145));
end process;
-- ap_sig_bdd_724 assign process. --
ap_sig_bdd_724_assign_proc : process(tmp_4_reg_1749)
begin
ap_sig_bdd_724 <= (not((tmp_4_reg_1749 = ap_const_lv2_2)) and not((tmp_4_reg_1749 = ap_const_lv2_1)));
end process;
-- ap_sig_bdd_732 assign process. --
ap_sig_bdd_732_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_732 <= (ap_const_lv1_1 = ap_CS_fsm(146 downto 146));
end process;
-- ap_sig_bdd_748 assign process. --
ap_sig_bdd_748_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_748 <= (ap_const_lv1_1 = ap_CS_fsm(147 downto 147));
end process;
-- ap_sig_bdd_755 assign process. --
ap_sig_bdd_755_assign_proc : process(P_WandB_TVALID, tmp_22_fu_1386_p2)
begin
ap_sig_bdd_755 <= ((P_WandB_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_22_fu_1386_p2)));
end process;
-- ap_sig_bdd_765 assign process. --
ap_sig_bdd_765_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_765 <= (ap_const_lv1_1 = ap_CS_fsm(148 downto 148));
end process;
-- ap_sig_bdd_769 assign process. --
ap_sig_bdd_769_assign_proc : process(P_config_V_TVALID, exitcond5_fu_1398_p2)
begin
ap_sig_bdd_769 <= ((P_config_V_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = exitcond5_fu_1398_p2));
end process;
-- ap_sig_bdd_800 assign process. --
ap_sig_bdd_800_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_800 <= (ap_const_lv1_1 = ap_CS_fsm(76 downto 76));
end process;
-- ap_sig_bdd_821 assign process. --
ap_sig_bdd_821_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_821 <= (ap_const_lv1_1 = ap_CS_fsm(137 downto 137));
end process;
-- ap_sig_bdd_847 assign process. --
ap_sig_bdd_847_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_847 <= (ap_const_lv1_1 = ap_CS_fsm(143 downto 143));
end process;
-- ap_sig_bdd_942 assign process. --
ap_sig_bdd_942_assign_proc : process(tmp_reg_1442, tmp_1_reg_1454, tmp_41_reg_1661, ap_sig_cseq_ST_st139_fsm_138, tmp_44_fu_1062_p2)
begin
ap_sig_bdd_942 <= ((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and (ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2));
end process;
-- ap_sig_bdd_963 assign process. --
ap_sig_bdd_963_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_963 <= (ap_const_lv1_1 = ap_CS_fsm(114 downto 114));
end process;
-- ap_sig_bdd_987 assign process. --
ap_sig_bdd_987_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_987 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_994 assign process. --
ap_sig_bdd_994_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_994 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_987)
begin
if (ap_sig_bdd_987) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st113_fsm_112 assign process. --
ap_sig_cseq_ST_st113_fsm_112_assign_proc : process(ap_sig_bdd_374)
begin
if (ap_sig_bdd_374) then
ap_sig_cseq_ST_st113_fsm_112 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st113_fsm_112 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st114_fsm_113 assign process. --
ap_sig_cseq_ST_st114_fsm_113_assign_proc : process(ap_sig_bdd_391)
begin
if (ap_sig_bdd_391) then
ap_sig_cseq_ST_st114_fsm_113 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st114_fsm_113 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st115_fsm_114 assign process. --
ap_sig_cseq_ST_st115_fsm_114_assign_proc : process(ap_sig_bdd_963)
begin
if (ap_sig_bdd_963) then
ap_sig_cseq_ST_st115_fsm_114 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st115_fsm_114 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st119_fsm_118 assign process. --
ap_sig_cseq_ST_st119_fsm_118_assign_proc : process(ap_sig_bdd_574)
begin
if (ap_sig_bdd_574) then
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st120_fsm_119 assign process. --
ap_sig_cseq_ST_st120_fsm_119_assign_proc : process(ap_sig_bdd_583)
begin
if (ap_sig_bdd_583) then
ap_sig_cseq_ST_st120_fsm_119 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st120_fsm_119 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st121_fsm_120 assign process. --
ap_sig_cseq_ST_st121_fsm_120_assign_proc : process(ap_sig_bdd_264)
begin
if (ap_sig_bdd_264) then
ap_sig_cseq_ST_st121_fsm_120 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st121_fsm_120 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st137_fsm_136 assign process. --
ap_sig_cseq_ST_st137_fsm_136_assign_proc : process(ap_sig_bdd_601)
begin
if (ap_sig_bdd_601) then
ap_sig_cseq_ST_st137_fsm_136 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st137_fsm_136 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st138_fsm_137 assign process. --
ap_sig_cseq_ST_st138_fsm_137_assign_proc : process(ap_sig_bdd_821)
begin
if (ap_sig_bdd_821) then
ap_sig_cseq_ST_st138_fsm_137 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st138_fsm_137 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st139_fsm_138 assign process. --
ap_sig_cseq_ST_st139_fsm_138_assign_proc : process(ap_sig_bdd_610)
begin
if (ap_sig_bdd_610) then
ap_sig_cseq_ST_st139_fsm_138 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st139_fsm_138 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st140_fsm_139 assign process. --
ap_sig_cseq_ST_st140_fsm_139_assign_proc : process(ap_sig_bdd_272)
begin
if (ap_sig_bdd_272) then
ap_sig_cseq_ST_st140_fsm_139 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st140_fsm_139 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st141_fsm_140 assign process. --
ap_sig_cseq_ST_st141_fsm_140_assign_proc : process(ap_sig_bdd_654)
begin
if (ap_sig_bdd_654) then
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st142_fsm_141 assign process. --
ap_sig_cseq_ST_st142_fsm_141_assign_proc : process(ap_sig_bdd_663)
begin
if (ap_sig_bdd_663) then
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st143_fsm_142 assign process. --
ap_sig_cseq_ST_st143_fsm_142_assign_proc : process(ap_sig_bdd_674)
begin
if (ap_sig_bdd_674) then
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st144_fsm_143 assign process. --
ap_sig_cseq_ST_st144_fsm_143_assign_proc : process(ap_sig_bdd_847)
begin
if (ap_sig_bdd_847) then
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st145_fsm_144 assign process. --
ap_sig_cseq_ST_st145_fsm_144_assign_proc : process(ap_sig_bdd_689)
begin
if (ap_sig_bdd_689) then
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st146_fsm_145 assign process. --
ap_sig_cseq_ST_st146_fsm_145_assign_proc : process(ap_sig_bdd_707)
begin
if (ap_sig_bdd_707) then
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st147_fsm_146 assign process. --
ap_sig_cseq_ST_st147_fsm_146_assign_proc : process(ap_sig_bdd_732)
begin
if (ap_sig_bdd_732) then
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st148_fsm_147 assign process. --
ap_sig_cseq_ST_st148_fsm_147_assign_proc : process(ap_sig_bdd_748)
begin
if (ap_sig_bdd_748) then
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st149_fsm_148 assign process. --
ap_sig_cseq_ST_st149_fsm_148_assign_proc : process(ap_sig_bdd_765)
begin
if (ap_sig_bdd_765) then
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_317)
begin
if (ap_sig_bdd_317) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_281)
begin
if (ap_sig_bdd_281) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_994)
begin
if (ap_sig_bdd_994) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_167)
begin
if (ap_sig_bdd_167) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st20_fsm_19 assign process. --
ap_sig_cseq_ST_st20_fsm_19_assign_proc : process(ap_sig_bdd_333)
begin
if (ap_sig_bdd_333) then
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st21_fsm_20 assign process. --
ap_sig_cseq_ST_st21_fsm_20_assign_proc : process(ap_sig_bdd_350)
begin
if (ap_sig_bdd_350) then
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_428)
begin
if (ap_sig_bdd_428) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st39_fsm_38 assign process. --
ap_sig_cseq_ST_st39_fsm_38_assign_proc : process(ap_sig_bdd_367)
begin
if (ap_sig_bdd_367) then
ap_sig_cseq_ST_st39_fsm_38 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st39_fsm_38 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_444)
begin
if (ap_sig_bdd_444) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st44_fsm_43 assign process. --
ap_sig_cseq_ST_st44_fsm_43_assign_proc : process(ap_sig_bdd_516)
begin
if (ap_sig_bdd_516) then
ap_sig_cseq_ST_st44_fsm_43 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st44_fsm_43 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_474)
begin
if (ap_sig_bdd_474) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_496)
begin
if (ap_sig_bdd_496) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_249)
begin
if (ap_sig_bdd_249) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st75_fsm_74 assign process. --
ap_sig_cseq_ST_st75_fsm_74_assign_proc : process(ap_sig_bdd_525)
begin
if (ap_sig_bdd_525) then
ap_sig_cseq_ST_st75_fsm_74 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st75_fsm_74 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st76_fsm_75 assign process. --
ap_sig_cseq_ST_st76_fsm_75_assign_proc : process(ap_sig_bdd_384)
begin
if (ap_sig_bdd_384) then
ap_sig_cseq_ST_st76_fsm_75 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st76_fsm_75 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st77_fsm_76 assign process. --
ap_sig_cseq_ST_st77_fsm_76_assign_proc : process(ap_sig_bdd_800)
begin
if (ap_sig_bdd_800) then
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st78_fsm_77 assign process. --
ap_sig_cseq_ST_st78_fsm_77_assign_proc : process(ap_sig_bdd_534)
begin
if (ap_sig_bdd_534) then
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st79_fsm_78 assign process. --
ap_sig_cseq_ST_st79_fsm_78_assign_proc : process(ap_sig_bdd_555)
begin
if (ap_sig_bdd_555) then
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st80_fsm_79 assign process. --
ap_sig_cseq_ST_st80_fsm_79_assign_proc : process(ap_sig_bdd_256)
begin
if (ap_sig_bdd_256) then
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st83_fsm_82 assign process. --
ap_sig_cseq_ST_st83_fsm_82_assign_proc : process(ap_sig_bdd_307)
begin
if (ap_sig_bdd_307) then
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st84_fsm_83 assign process. --
ap_sig_cseq_ST_st84_fsm_83_assign_proc : process(ap_sig_bdd_1002)
begin
if (ap_sig_bdd_1002) then
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st88_fsm_87 assign process. --
ap_sig_cseq_ST_st88_fsm_87_assign_proc : process(ap_sig_bdd_324)
begin
if (ap_sig_bdd_324) then
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st89_fsm_88 assign process. --
ap_sig_cseq_ST_st89_fsm_88_assign_proc : process(ap_sig_bdd_290)
begin
if (ap_sig_bdd_290) then
ap_sig_cseq_ST_st89_fsm_88 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st89_fsm_88 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st90_fsm_89 assign process. --
ap_sig_cseq_ST_st90_fsm_89_assign_proc : process(ap_sig_bdd_1009)
begin
if (ap_sig_bdd_1009) then
ap_sig_cseq_ST_st90_fsm_89 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st90_fsm_89 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st94_fsm_93 assign process. --
ap_sig_cseq_ST_st94_fsm_93_assign_proc : process(ap_sig_bdd_340)
begin
if (ap_sig_bdd_340) then
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st95_fsm_94 assign process. --
ap_sig_cseq_ST_st95_fsm_94_assign_proc : process(ap_sig_bdd_357)
begin
if (ap_sig_bdd_357) then
ap_sig_cseq_ST_st95_fsm_94 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st95_fsm_94 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_300)
begin
if (ap_sig_bdd_300) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_P_netOut_V_TREADY assign process. --
ap_sig_ioackin_P_netOut_V_TREADY_assign_proc : process(P_netOut_V_TREADY, ap_reg_ioackin_P_netOut_V_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_netOut_V_TREADY)) then
ap_sig_ioackin_P_netOut_V_TREADY <= P_netOut_V_TREADY;
else
ap_sig_ioackin_P_netOut_V_TREADY <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ioackin_P_uOut_TREADY assign process. --
ap_sig_ioackin_P_uOut_TREADY_assign_proc : process(P_uOut_TREADY, ap_reg_ioackin_P_uOut_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY)) then
ap_sig_ioackin_P_uOut_TREADY <= P_uOut_TREADY;
else
ap_sig_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end process;
exitcond1_fu_633_p2 <= "1" when (i_2_reg_277 = ST_layerSize_V_0_load_reg_1458) else "0";
exitcond2_fu_827_p2 <= "1" when (k_1_reg_323 = tmp_19_reg_1534) else "0";
exitcond3_fu_980_p2 <= "1" when (j_2_reg_369 = tmp_23_reg_1603) else "0";
exitcond4_fu_1032_p2 <= "1" when (i_5_reg_380 = tmp_15_reg_1589) else "0";
exitcond5_fu_1398_p2 <= "1" when (i_reg_495 = P_config_V_read_reg_1463) else "0";
exitcond_fu_1105_p2 <= "1" when (i_6_reg_416 = ST_numLayer_V_load_reg_1446) else "0";
feedforward_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
grp_fu_506_ce <= ap_const_logic_1;
-- grp_fu_506_p0 assign process. --
grp_fu_506_p0_assign_proc : process(sum_reg_311, sumsoft_reg_334, sum_1_reg_357, ap_sig_cseq_ST_st115_fsm_114, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st84_fsm_83, ap_sig_cseq_ST_st90_fsm_89)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114)) then
grp_fu_506_p0 <= sumsoft_reg_334;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83) or (ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89))) then
grp_fu_506_p0 <= sum_1_reg_357;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15))) then
grp_fu_506_p0 <= sum_reg_311;
else
grp_fu_506_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_506_p1 assign process. --
grp_fu_506_p1_assign_proc : process(reg_572, reg_578, reg_605, ap_sig_cseq_ST_st115_fsm_114, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st84_fsm_83, ap_sig_cseq_ST_st90_fsm_89)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114)) then
grp_fu_506_p1 <= reg_605;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89))) then
grp_fu_506_p1 <= reg_572;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83))) then
grp_fu_506_p1 <= reg_578;
else
grp_fu_506_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_513_ce <= ap_const_logic_1;
grp_fu_519_ce <= ap_const_logic_1;
-- grp_fu_524_p0 assign process. --
grp_fu_524_p0_assign_proc : process(reg_599, ap_sig_cseq_ST_st76_fsm_75, ap_sig_cseq_ST_st114_fsm_113, tmp_31_reg_1584)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st114_fsm_113)) then
grp_fu_524_p0 <= reg_599;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st76_fsm_75)) then
grp_fu_524_p0 <= tmp_31_reg_1584;
else
grp_fu_524_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_527_p0 assign process. --
grp_fu_527_p0_assign_proc : process(reg_589, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st95_fsm_94, tmp_27_fu_889_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st95_fsm_94)) then
grp_fu_527_p0 <= reg_589;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) then
grp_fu_527_p0 <= tmp_27_fu_889_p1;
else
grp_fu_527_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_534_ce <= ap_const_logic_1;
grp_fu_539_ce <= ap_const_logic_1;
grp_fu_544_ce <= ap_const_logic_1;
i_10_fu_821_p2 <= std_logic_vector(unsigned(i_3_reg_288) + unsigned(ap_const_lv8_1));
i_11_fu_1037_p2 <= std_logic_vector(unsigned(i_5_reg_380) + unsigned(ap_const_lv8_1));
i_12_fu_917_p2 <= std_logic_vector(unsigned(i_4_reg_346) + unsigned(ap_const_lv32_1));
i_14_fu_1110_p2 <= std_logic_vector(unsigned(ap_const_lv8_1) + unsigned(i_6_reg_416));
i_15_fu_1210_p2 <= std_logic_vector(unsigned(ap_const_lv8_1) + unsigned(p_netOut_V_reg_404));
i_7_fu_1403_p2 <= std_logic_vector(unsigned(i_reg_495) + unsigned(ap_const_lv8_1));
i_8_fu_638_p2 <= std_logic_vector(unsigned(i_2_reg_277) + unsigned(ap_const_lv8_1));
i_9_fu_1339_p2 <= std_logic_vector(unsigned(i_1_reg_449) + unsigned(ap_const_lv8_1));
j_4_fu_1288_p2 <= std_logic_vector(unsigned(j_reg_461) + unsigned(ap_const_lv32_1));
j_5_fu_762_p2 <= std_logic_vector(unsigned(j_1_reg_300) + unsigned(ap_const_lv32_1));
j_6_fu_985_p2 <= std_logic_vector(unsigned(j_2_reg_369) + unsigned(ap_const_lv8_1));
j_7_fu_1239_p2 <= std_logic_vector(unsigned(j_3_reg_438) + unsigned(ap_const_lv32_1));
k_2_fu_1392_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(k_reg_484));
k_3_fu_832_p2 <= std_logic_vector(unsigned(k_1_reg_323) + unsigned(ap_const_lv8_1));
lhs_V_1_cast_fu_692_p1 <= std_logic_vector(resize(unsigned(ST_numLayer_V_load_reg_1446),9));
lhs_V_cast_fu_1372_p1 <= std_logic_vector(resize(unsigned(tmp_25_fu_1359_p6),9));
next_mul_fu_1099_p2 <= std_logic_vector(unsigned(ap_const_lv14_23) + unsigned(phi_mul_reg_427));
notlhs1_fu_1173_p2 <= "0" when (tmp_50_fu_1141_p4 = ap_const_lv8_FF) else "1";
notlhs_fu_1155_p2 <= "0" when (tmp_48_fu_1124_p4 = ap_const_lv8_FF) else "1";
notrhs1_fu_1179_p2 <= "1" when (tmp_79_fu_1151_p1 = ap_const_lv23_0) else "0";
notrhs_fu_1161_p2 <= "1" when (tmp_78_fu_1134_p1 = ap_const_lv23_0) else "0";
p_netOut_V_1_fu_1203_p3 <=
p_netOut_V_reg_404 when (tmp_56_reg_1712(0) = '1') else
p_s_reg_391;
p_shl1_cast_fu_1325_p3 <= (tmp_45_fu_1321_p1 & ap_const_lv2_0);
p_shl2_cast_fu_795_p3 <= (tmp_49_fu_791_p1 & ap_const_lv5_0);
p_shl3_cast_fu_807_p3 <= (tmp_51_fu_803_p1 & ap_const_lv2_0);
p_shl4_cast_fu_954_p3 <= (tmp_62_fu_950_p1 & ap_const_lv5_0);
p_shl5_cast_fu_966_p3 <= (tmp_63_fu_962_p1 & ap_const_lv2_0);
p_shl_cast_fu_1313_p3 <= (tmp_42_fu_1309_p1 & ap_const_lv5_0);
-- p_uOut_address0 assign process. --
p_uOut_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, p_uOut_addr_1_reg_1546, ap_sig_cseq_ST_st5_fsm_4, p_uOut_addr_3_reg_1615, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st120_fsm_119, p_uOut_addr_5_reg_1656, ap_sig_cseq_ST_st139_fsm_138, ap_sig_cseq_ST_st77_fsm_76, ap_sig_cseq_ST_st138_fsm_137, tmp_8_fu_644_p1, tmp_81_cast_fu_861_p1, tmp_84_cast_fu_1014_p1, tmp_85_cast_fu_1052_p1, tmp_87_cast_fu_1076_p1, ap_sig_cseq_ST_st115_fsm_114)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137)) then
p_uOut_address0 <= p_uOut_addr_5_reg_1656;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114)) then
p_uOut_address0 <= p_uOut_addr_3_reg_1615;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76)) then
p_uOut_address0 <= p_uOut_addr_1_reg_1546;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_address0 <= tmp_8_fu_644_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138)) then
p_uOut_address0 <= tmp_87_cast_fu_1076_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) then
p_uOut_address0 <= tmp_85_cast_fu_1052_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
p_uOut_address0 <= tmp_84_cast_fu_1014_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
p_uOut_address0 <= tmp_81_cast_fu_861_p1(8 - 1 downto 0);
else
p_uOut_address0 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_address1 assign process. --
p_uOut_address1_assign_proc : process(ap_sig_cseq_ST_st139_fsm_138, ap_sig_cseq_ST_st143_fsm_142, tmp_88_cast_fu_1090_p1, tmp_89_cast_fu_1254_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
p_uOut_address1 <= tmp_89_cast_fu_1254_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138)) then
p_uOut_address1 <= tmp_88_cast_fu_1090_p1(8 - 1 downto 0);
else
p_uOut_address1 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_ce0 assign process. --
p_uOut_ce0_assign_proc : process(tmp_reg_1442, tmp_1_reg_1454, ap_sig_cseq_ST_st2_fsm_1, ap_sig_bdd_434, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st120_fsm_119, tmp_41_reg_1661, ap_sig_cseq_ST_st139_fsm_138, tmp_44_fu_1062_p2, ap_sig_ioackin_P_netOut_V_TREADY, ap_sig_cseq_ST_st77_fsm_76, ap_sig_cseq_ST_st138_fsm_137, ap_sig_cseq_ST_st115_fsm_114)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_434)) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) or ((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76) or (ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137) or (ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114))) then
p_uOut_ce0 <= ap_const_logic_1;
else
p_uOut_ce0 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_ce1 assign process. --
p_uOut_ce1_assign_proc : process(tmp_reg_1442, tmp_1_reg_1454, tmp_41_reg_1661, ap_sig_cseq_ST_st139_fsm_138, tmp_44_fu_1062_p2, ap_sig_ioackin_P_netOut_V_TREADY, ap_sig_cseq_ST_st143_fsm_142)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142))) then
p_uOut_ce1 <= ap_const_logic_1;
else
p_uOut_ce1 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_d0 assign process. --
p_uOut_d0_assign_proc : process(P_netIn_TDATA, reg_605, ap_sig_cseq_ST_st2_fsm_1, tmp_43_reg_1665, ap_sig_cseq_ST_st77_fsm_76, ap_sig_cseq_ST_st138_fsm_137, ap_sig_cseq_ST_st115_fsm_114)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137)) then
p_uOut_d0 <= tmp_43_reg_1665;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76) or (ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114))) then
p_uOut_d0 <= reg_605;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_d0 <= P_netIn_TDATA;
else
p_uOut_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
p_uOut_load_3_to_int_fu_1120_p1 <= reg_565;
p_uOut_load_4_to_int_fu_1138_p1 <= p_uOut_load_4_reg_1706;
-- p_uOut_we0 assign process. --
p_uOut_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_633_p2, ap_sig_bdd_434, ap_sig_cseq_ST_st77_fsm_76, ap_sig_cseq_ST_st138_fsm_137, ap_sig_cseq_ST_st115_fsm_114)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_633_p2) and not(ap_sig_bdd_434)) or (ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76) or (ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137) or (ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114))) then
p_uOut_we0 <= ap_const_logic_1;
else
p_uOut_we0 <= ap_const_logic_0;
end if;
end process;
r_V_1_fu_695_p2 <= std_logic_vector(signed(ap_const_lv9_1FF) + signed(lhs_V_1_cast_fu_692_p1));
r_V_2_fu_723_p2 <= std_logic_vector(signed(ap_const_lv9_1FE) + signed(lhs_V_1_cast_fu_692_p1));
r_V_fu_1376_p2 <= std_logic_vector(unsigned(ap_const_lv9_1) + unsigned(lhs_V_cast_fu_1372_p1));
tmp_10_fu_1294_p1 <= std_logic_vector(resize(unsigned(ST_layerSize_V_load_1_phi_reg_473),32));
tmp_11_fu_1298_p2 <= "1" when (signed(j_reg_461) < signed(tmp_10_fu_1294_p1)) else "0";
tmp_13_fu_752_p1 <= std_logic_vector(resize(unsigned(tmp_12_fu_739_p6),32));
tmp_14_fu_756_p2 <= "1" when (signed(j_1_reg_300) < signed(tmp_13_fu_752_p1)) else "0";
tmp_16_fu_682_p1 <= tmp_16_fu_682_p10(8 - 1 downto 0);
tmp_16_fu_682_p10 <= std_logic_vector(resize(unsigned(tmp_3_fu_672_p2),9));
tmp_16_fu_682_p2 <= std_logic_vector(resize(unsigned(ap_const_lv9_23) * unsigned(tmp_16_fu_682_p1), 9));
tmp_17_fu_907_p1 <= std_logic_vector(resize(unsigned(tmp_15_fu_894_p6),32));
tmp_18_fu_911_p2 <= "1" when (signed(i_4_reg_346) < signed(tmp_17_fu_907_p1)) else "0";
tmp_1_fu_621_p2 <= "1" when (P_mode_V = ap_const_lv8_2) else "0";
tmp_20_fu_688_p1 <= tmp_3_fu_672_p2(2 - 1 downto 0);
tmp_21_cast_fu_1382_p1 <= std_logic_vector(resize(unsigned(r_V_fu_1376_p2),32));
tmp_21_fu_705_p1 <= r_V_1_fu_695_p2;
tmp_21_fu_705_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv16_23) * signed(tmp_21_fu_705_p1))), 16));
tmp_22_fu_1386_p2 <= "1" when (signed(k_reg_484) < signed(tmp_21_cast_fu_1382_p1)) else "0";
tmp_24_cast_fu_936_p1 <= std_logic_vector(resize(signed(i_4_reg_346),33));
tmp_24_fu_711_p1 <= tmp_21_fu_705_p2(9 - 1 downto 0);
tmp_26_cast_fu_866_p1 <= std_logic_vector(resize(unsigned(tmp_19_reg_1534),14));
tmp_26_fu_719_p1 <= r_V_1_fu_695_p2(2 - 1 downto 0);
tmp_27_fu_889_p1 <= tmp_35_neg_fu_883_p2;
tmp_2_fu_1409_p1 <= i_reg_495(2 - 1 downto 0);
tmp_33_cast7_fu_838_p1 <= std_logic_vector(resize(unsigned(k_1_reg_323),9));
tmp_33_cast_fu_842_p1 <= std_logic_vector(resize(unsigned(k_1_reg_323),14));
tmp_33_fu_729_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv9_23) * signed(r_V_2_fu_723_p2))), 9));
tmp_35_cast_fu_1019_p1 <= std_logic_vector(resize(unsigned(tmp_23_reg_1603),14));
tmp_35_fu_735_p1 <= r_V_2_fu_723_p2(2 - 1 downto 0);
tmp_35_neg_fu_883_p2 <= (tmp_35_to_int_fu_879_p1 xor ap_const_lv32_80000000);
tmp_35_to_int_fu_879_p1 <= reg_589;
tmp_39_cast6_fu_991_p1 <= std_logic_vector(resize(unsigned(j_2_reg_369),9));
tmp_39_cast_fu_995_p1 <= std_logic_vector(resize(unsigned(j_2_reg_369),14));
tmp_39_fu_1304_p2 <= std_logic_vector(unsigned(j_reg_461) + unsigned(tmp_61_cast_reg_1744));
tmp_3_fu_672_p2 <= std_logic_vector(signed(ap_const_lv8_FF) + signed(i_3_reg_288));
tmp_41_fu_1057_p2 <= "1" when (P_mode_V_read_reg_1437 = ap_const_lv8_3) else "0";
tmp_42_cast_fu_1043_p1 <= std_logic_vector(resize(unsigned(i_5_reg_380),9));
tmp_42_fu_1309_p1 <= tmp_39_fu_1304_p2(9 - 1 downto 0);
tmp_44_fu_1062_p2 <= "1" when (unsigned(p_netOut_V_reg_404) < unsigned(tmp_15_reg_1589)) else "0";
tmp_45_fu_1321_p1 <= tmp_39_fu_1304_p2(12 - 1 downto 0);
tmp_46_cast_fu_1067_p1 <= std_logic_vector(resize(unsigned(p_netOut_V_reg_404),9));
tmp_46_fu_1333_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_1313_p3) + unsigned(p_shl1_cast_fu_1325_p3));
tmp_47_cast_fu_1081_p1 <= std_logic_vector(resize(unsigned(p_s_reg_391),9));
tmp_47_fu_781_p2 <= std_logic_vector(unsigned(j_1_reg_300) + unsigned(tmp_62_cast_reg_1479));
tmp_48_fu_1124_p4 <= p_uOut_load_3_to_int_fu_1120_p1(30 downto 23);
tmp_49_fu_791_p1 <= tmp_47_fu_781_p2(9 - 1 downto 0);
tmp_4_fu_1278_p1 <= i_1_reg_449(2 - 1 downto 0);
tmp_50_fu_1141_p4 <= p_uOut_load_4_to_int_fu_1138_p1(30 downto 23);
tmp_51_fu_803_p1 <= tmp_47_fu_781_p2(12 - 1 downto 0);
tmp_52_fu_1167_p2 <= (notrhs_fu_1161_p2 or notlhs_fu_1155_p2);
tmp_53_fu_1185_p2 <= (notrhs1_fu_1179_p2 or notlhs1_fu_1173_p2);
tmp_54_fu_1191_p2 <= (tmp_52_fu_1167_p2 and tmp_53_fu_1185_p2);
tmp_55_fu_530_opcode <= ap_const_lv5_2;
tmp_56_fu_1197_p2 <= (tmp_54_fu_1191_p2 and tmp_55_fu_530_p2);
tmp_58_fu_1229_p1 <= std_logic_vector(resize(unsigned(tmp_57_fu_1216_p6),32));
tmp_59_fu_1233_p2 <= "1" when (signed(j_3_reg_438) < signed(tmp_58_fu_1229_p1)) else "0";
tmp_5_fu_658_p1 <= tmp_5_fu_658_p10(8 - 1 downto 0);
tmp_5_fu_658_p10 <= std_logic_vector(resize(unsigned(i_3_reg_288),15));
tmp_5_fu_658_p2 <= std_logic_vector(resize(unsigned(ap_const_lv15_23) * unsigned(tmp_5_fu_658_p1), 15));
tmp_60_fu_815_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_795_p3) + unsigned(p_shl3_cast_fu_807_p3));
tmp_61_cast_fu_1274_p1 <= std_logic_vector(resize(unsigned(tmp_s_fu_1268_p2),32));
tmp_61_fu_940_p2 <= std_logic_vector(signed(tmp_24_cast_fu_936_p1) + signed(tmp_64_cast_reg_1506));
tmp_62_cast_fu_664_p1 <= std_logic_vector(resize(unsigned(tmp_5_fu_658_p2),32));
tmp_62_fu_950_p1 <= tmp_61_fu_940_p2(9 - 1 downto 0);
tmp_63_fu_962_p1 <= tmp_61_fu_940_p2(12 - 1 downto 0);
tmp_64_cast_fu_715_p1 <= std_logic_vector(resize(signed(tmp_21_fu_705_p2),33));
tmp_64_fu_974_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_954_p3) + unsigned(p_shl5_cast_fu_966_p3));
tmp_65_fu_1345_p1 <= k_reg_484(14 - 1 downto 0);
tmp_66_fu_1349_p2 <= std_logic_vector(unsigned(tmp_46_reg_1781) + unsigned(tmp_65_fu_1345_p1));
tmp_67_fu_1047_p2 <= std_logic_vector(unsigned(tmp_24_reg_1499) + unsigned(tmp_42_cast_fu_1043_p1));
tmp_68_fu_869_p2 <= std_logic_vector(unsigned(tmp_60_reg_1540) + unsigned(tmp_26_cast_fu_866_p1));
tmp_69_fu_846_p2 <= std_logic_vector(unsigned(tmp_60_reg_1540) + unsigned(tmp_33_cast_fu_842_p1));
tmp_6_fu_668_p1 <= i_3_reg_288(2 - 1 downto 0);
tmp_70_cast_fu_786_p1 <= std_logic_vector(resize(signed(tmp_47_fu_781_p2),64));
tmp_70_fu_856_p2 <= std_logic_vector(unsigned(tmp_16_reg_1489) + unsigned(tmp_33_cast7_fu_838_p1));
tmp_71_fu_1022_p2 <= std_logic_vector(unsigned(tmp_64_reg_1609) + unsigned(tmp_35_cast_fu_1019_p1));
tmp_72_fu_999_p2 <= std_logic_vector(unsigned(tmp_64_reg_1609) + unsigned(tmp_39_cast_fu_995_p1));
tmp_73_fu_1009_p2 <= std_logic_vector(unsigned(tmp_33_reg_1516) + unsigned(tmp_39_cast6_fu_991_p1));
tmp_74_cast_fu_945_p1 <= std_logic_vector(resize(signed(tmp_61_fu_940_p2),64));
tmp_74_fu_1095_p1 <= phi_mul_reg_427(9 - 1 downto 0);
tmp_75_fu_1116_p1 <= i_6_reg_416(2 - 1 downto 0);
tmp_76_fu_1071_p2 <= std_logic_vector(unsigned(tmp_24_reg_1499) + unsigned(tmp_46_cast_fu_1067_p1));
tmp_77_fu_1085_p2 <= std_logic_vector(unsigned(tmp_24_reg_1499) + unsigned(tmp_47_cast_fu_1081_p1));
tmp_78_cast_fu_1354_p1 <= std_logic_vector(resize(unsigned(tmp_66_fu_1349_p2),64));
tmp_78_fu_1134_p1 <= p_uOut_load_3_to_int_fu_1120_p1(23 - 1 downto 0);
tmp_79_cast_fu_874_p1 <= std_logic_vector(resize(unsigned(tmp_68_fu_869_p2),64));
tmp_79_fu_1151_p1 <= p_uOut_load_4_to_int_fu_1138_p1(23 - 1 downto 0);
tmp_7_fu_649_p2 <= "1" when (unsigned(i_3_reg_288) < unsigned(ST_numLayer_V_load_reg_1446)) else "0";
tmp_7_t_fu_1282_p2 <= std_logic_vector(signed(ap_const_lv2_3) + signed(tmp_4_fu_1278_p1));
tmp_80_cast_fu_851_p1 <= std_logic_vector(resize(unsigned(tmp_69_fu_846_p2),64));
tmp_80_fu_1245_p1 <= j_3_reg_438(9 - 1 downto 0);
tmp_81_cast_fu_861_p1 <= std_logic_vector(resize(signed(tmp_70_fu_856_p2),64));
tmp_81_fu_1249_p2 <= std_logic_vector(unsigned(tmp_74_reg_1683) + unsigned(tmp_80_fu_1245_p1));
tmp_82_cast_fu_1027_p1 <= std_logic_vector(resize(unsigned(tmp_71_fu_1022_p2),64));
tmp_83_cast_fu_1004_p1 <= std_logic_vector(resize(unsigned(tmp_72_fu_999_p2),64));
tmp_84_cast_fu_1014_p1 <= std_logic_vector(resize(signed(tmp_73_fu_1009_p2),64));
tmp_85_cast_fu_1052_p1 <= std_logic_vector(resize(signed(tmp_67_fu_1047_p2),64));
tmp_87_cast_fu_1076_p1 <= std_logic_vector(resize(signed(tmp_76_fu_1071_p2),64));
tmp_88_cast_fu_1090_p1 <= std_logic_vector(resize(signed(tmp_77_fu_1085_p2),64));
tmp_89_cast_fu_1254_p1 <= std_logic_vector(resize(unsigned(tmp_81_fu_1249_p2),64));
tmp_8_fu_644_p1 <= std_logic_vector(resize(unsigned(i_2_reg_277),64));
tmp_9_fu_1259_p2 <= "1" when (unsigned(i_1_reg_449) < unsigned(ST_numLayer_V_load_reg_1446)) else "0";
tmp_fu_611_p2 <= "1" when (P_mode_V = ap_const_lv8_1) else "0";
tmp_s_fu_1268_p1 <= tmp_s_fu_1268_p10(8 - 1 downto 0);
tmp_s_fu_1268_p10 <= std_logic_vector(resize(unsigned(i_1_reg_449),15));
tmp_s_fu_1268_p2 <= std_logic_vector(resize(unsigned(ap_const_lv15_23) * unsigned(tmp_s_fu_1268_p1), 15));
end behav;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/11/2017 10:26:23 AM
-- Design Name:
-- Module Name: app_package - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work;
use work.board_pkg.all;
package app_pkg is
--constant c_TX_CHANNELS : integer := 8;
--constant c_RX_CHANNELS : integer := 8;
component simple_counter is
Port (
enable_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
count_o : out STD_LOGIC_VECTOR (28 downto 0);
gray_count_o : out STD_LOGIC_VECTOR (28 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- _clk_640___640.000______0.000______50.0______468.793____919.522
-- _clk_160___160.000______0.000______50.0______568.382____919.522
-- __clk_80____80.000______0.000______50.0______625.965____919.522
-- __clk_40____40.000______0.000______50.0______689.448____919.522
-- clk_40_90____40.000_____90.000______50.0______689.448____919.522
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_____________250____________0.010
component clk_gen
port
(-- Clock in ports
clk_250_in : in std_logic;
-- Clock out ports
clk_300 : out std_logic;
clk_640 : out std_logic;
clk_160 : out std_logic;
clk_80 : out std_logic;
clk_40 : out std_logic;
clk_40_90 : out std_logic;
clk_250 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
--//----------------------------------------------------------------------------
--// Output Output Phase Duty Cycle Pk-to-Pk Phase
--// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
--//----------------------------------------------------------------------------
--// __clk_40____40.000______0.000______50.0______161.245____154.081
--// __clk_80____80.000______0.000______50.0______143.262____154.081
--// _clk_160___160.000______0.000______50.0______128.042____154.081
--// _clk_320___320.000______0.000______50.0______114.518____154.081
--// _clk_640___640.000______0.000______50.0______102.510____154.081
--// _clk_300___320.000______0.000______50.0______114.518____154.081
--// _clk_250___256.000______0.000______50.0______118.698____154.081
--//
--//----------------------------------------------------------------------------
--// Input Clock Freq (MHz) Input Jitter (UI)
--//----------------------------------------------------------------------------
--// __primary_________200.000____________0.010
component clk_200_gen
port
(-- Clock in ports
clk_200_in : in std_logic;
-- Clock out ports
clk_40 : out std_logic;
clk_80 : out std_logic;
clk_160 : out std_logic;
clk_320 : out std_logic;
clk_640 : out std_logic;
clk_300 : out std_logic;
clk_250 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end component;
COMPONENT axis_data_fifo_0
PORT (
s_axis_aresetn : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tuser : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
m_axis_aclk : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tuser : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT axis_data_fifo_1
PORT (
s_axis_aresetn : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_aclk : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
component synchronizer is
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end component;
component wshexp_core is
Generic(
AXI_BUS_WIDTH : integer := 64
);
Port (
clk_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
--sys_clk_n_i : IN STD_LOGIC;
--sys_clk_p_i : IN STD_LOGIC;
rst_i : in STD_LOGIC;
--user_lnk_up_i : in STD_LOGIC;
--user_app_rdy_i : in STD_LOGIC;
---------------------------------------------------------
-- AXI-Stream bus
m_axis_tx_tready_i : in STD_LOGIC;
m_axis_tx_tdata_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
m_axis_tx_tkeep_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
m_axis_tx_tlast_o : out STD_LOGIC;
m_axis_tx_tvalid_o : out STD_LOGIC;
m_axis_tx_tuser_o : out STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR(21 DOWNTO 0);
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_adr_o : out std_logic_vector(31 downto 0); -- Adress
dma_dat_o : out std_logic_vector(63 downto 0); -- Data out
dma_dat_i : in std_logic_vector(63 downto 0); -- Data in
dma_sel_o : out std_logic_vector(7 downto 0); -- Byte select
dma_cyc_o : out std_logic; -- Read or write cycle
dma_stb_o : out std_logic; -- Read or write strobe
dma_we_o : out std_logic; -- Write
dma_ack_i : in std_logic; -- Acknowledge
dma_stall_i : in std_logic; -- for pipelined Wishbone
---------------------------------------------------------
-- CSR wishbone interface (master classic)
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
csr_err_i : in std_logic;
csr_rty_i : in std_logic; -- not used internally
csr_int_i : in std_logic; -- not used internally
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_adr_i : in std_logic_vector(31 downto 0);
dma_reg_dat_i : in std_logic_vector(31 downto 0);
dma_reg_sel_i : in std_logic_vector(3 downto 0);
dma_reg_stb_i : in std_logic;
dma_reg_we_i : in std_logic;
dma_reg_cyc_i : in std_logic;
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- PCIe interrupt config
cfg_interrupt_o : out STD_LOGIC;
cfg_interrupt_rdy_i : in STD_LOGIC;
cfg_interrupt_assert_o : out STD_LOGIC;
cfg_interrupt_di_o : out STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable_i : in STD_LOGIC;
cfg_interrupt_msixenable_i : in STD_LOGIC;
cfg_interrupt_msixfm_i : in STD_LOGIC;
cfg_interrupt_stat_o : out STD_LOGIC;
cfg_pciecap_interrupt_msgnum_o : out STD_LOGIC_VECTOR(4 DOWNTO 0);
---------------------------------------------------------
-- PCIe ID
cfg_bus_number_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number_i : in STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number_i : in STD_LOGIC_VECTOR(2 DOWNTO 0)
);
end component;
component k_bram is
generic (
constant ADDR_WIDTH : integer := 9+4;
constant DATA_WIDTH : integer := 64
);
Port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(9+4-1 downto 0);
wb_dat_i : in std_logic_vector(64-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_lock_i : in std_logic; -- nyi
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(64-1 downto 0);
wb_ack_o : out std_logic
);
end component;
component k_dual_bram is
Port (
-- SYS CON
clk_i : in std_logic;
rst_i : in std_logic;
-- Wishbone Slave in
wba_adr_i : in std_logic_vector(32-1 downto 0);
wba_dat_i : in std_logic_vector(64-1 downto 0);
wba_we_i : in std_logic;
wba_stb_i : in std_logic;
wba_cyc_i : in std_logic;
-- Wishbone Slave out
wba_dat_o : out std_logic_vector(64-1 downto 0);
wba_ack_o : out std_logic;
-- Wishbone Slave in
wbb_adr_i : in std_logic_vector(32-1 downto 0);
wbb_dat_i : in std_logic_vector(64-1 downto 0);
wbb_we_i : in std_logic;
wbb_stb_i : in std_logic;
wbb_cyc_i : in std_logic;
-- Wishbone Slave out
wbb_dat_o : out std_logic_vector(64-1 downto 0);
wbb_ack_o : out std_logic
);
end component;
component wb_addr_decoder is
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end component;
component ctrl_regs is
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Register Outputs R/W
ctrl_reg_0_o : out std_logic_vector(31 downto 0);
ctrl_reg_1_o : out std_logic_vector(31 downto 0);
ctrl_reg_2_o : out std_logic_vector(31 downto 0);
ctrl_reg_3_o : out std_logic_vector(31 downto 0);
ctrl_reg_4_o : out std_logic_vector(31 downto 0);
ctrl_reg_5_o : out std_logic_vector(31 downto 0);
-- Static registers RO
static_reg_0_o : out std_logic_vector(31 downto 0);
static_reg_1_o : out std_logic_vector(31 downto 0);
static_reg_2_o : out std_logic_vector(31 downto 0);
static_reg_3_o : out std_logic_vector(31 downto 0)
);
end component;
component mig_7series_0
port (
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(28 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(511 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(63 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(511 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_rst : in std_logic
);
end component mig_7series_0;
component ddr3_ctrl_wb
generic(
g_BYTE_ADDR_WIDTH : integer := 29;
g_MASK_SIZE : integer := 8;
g_DATA_PORT_SIZE : integer := 64
);
port(
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
----------------------------------------------------------------------------
-- Status
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DDR controller port
----------------------------------------------------------------------------
ddr_addr_o : out std_logic_vector(28 downto 0);
ddr_cmd_o : out std_logic_vector(2 downto 0);
ddr_cmd_en_o : out std_logic;
ddr_wdf_data_o : out std_logic_vector(511 downto 0);
ddr_wdf_end_o : out std_logic;
ddr_wdf_mask_o : out std_logic_vector(63 downto 0);
ddr_wdf_wren_o : out std_logic;
ddr_rd_data_i : in std_logic_vector(511 downto 0);
ddr_rd_data_end_i : in std_logic;
ddr_rd_data_valid_i : in std_logic;
ddr_rdy_i : in std_logic;
ddr_wdf_rdy_i : in std_logic;
ddr_sr_req_o : out std_logic;
ddr_ref_req_o : out std_logic;
ddr_zq_req_o : out std_logic;
ddr_sr_active_i : in std_logic;
ddr_ref_ack_i : in std_logic;
ddr_zq_ack_i : in std_logic;
ddr_ui_clk_i : in std_logic;
ddr_ui_clk_sync_rst_i : in std_logic;
ddr_init_calib_complete_i : in std_logic;
----------------------------------------------------------------------------
-- Wishbone bus port
----------------------------------------------------------------------------
wb_clk_i : in std_logic;
wb_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(31 downto 0);
wb_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Wishbone bus port
----------------------------------------------------------------------------
wb1_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb1_cyc_i : in std_logic;
wb1_stb_i : in std_logic;
wb1_we_i : in std_logic;
wb1_addr_i : in std_logic_vector(32 - 1 downto 0);
wb1_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb1_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb1_ack_o : out std_logic;
wb1_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Debug ports
----------------------------------------------------------------------------
ddr_wb_rd_mask_dout_do : out std_logic_vector(7 downto 0);
ddr_wb_rd_mask_addr_dout_do : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_rd_mask_rd_data_count_do : out std_logic_vector(3 downto 0);
ddr_rd_data_rd_data_count_do : out std_logic_vector(3 downto 0);
ddr_rd_fifo_full_do : out std_logic_vector(1 downto 0);
ddr_rd_fifo_empty_do : out std_logic_vector(1 downto 0);
ddr_rd_fifo_rd_do : out std_logic_vector(1 downto 0)
);
end component ddr3_ctrl_wb;
component wb_tx_core
generic (
g_NUM_TX : integer range 1 to 32 := c_TX_CHANNELS
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- TX
tx_clk_i : in std_logic;
tx_data_o : out std_logic_vector(g_NUM_TX-1 downto 0);
trig_pulse_o : out std_logic;
-- TRIGGER
ext_trig_i : in std_logic
);
end component;
component wb_rx_core
generic (
g_NUM_RX : integer range 1 to 32 := c_RX_CHANNELS;
g_TYPE : string := c_FE_TYPE;
g_NUM_LANES : integer range 1 to 4 := c_RX_NUM_LANES
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- RX IN
rx_clk_i : in std_logic;
rx_serdes_clk_i : in std_logic;
rx_data_i_p : in std_logic_vector((g_NUM_RX*g_NUM_LANES)-1 downto 0);
rx_data_i_n : in std_logic_vector((g_NUM_RX*g_NUM_LANES)-1 downto 0);
trig_tag_i : in std_logic_vector(31 downto 0);
-- RX OUT (sync to sys_clk)
rx_valid_o : out std_logic;
rx_data_o : out std_logic_vector(63 downto 0);
busy_o : out std_logic;
debug_o : out std_logic_vector(31 downto 0)
);
end component;
component wb_rx_bridge is
port (
-- Sys Connect
sys_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Wishbone DMA Master Interface
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(63 downto 0);
dma_dat_i : in std_logic_vector(63 downto 0);
dma_cyc_o : out std_logic;
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
-- Rx Interface
rx_data_i : in std_logic_vector(63 downto 0);
rx_valid_i : in std_logic;
-- Status in
trig_pulse_i : in std_logic;
-- Status out
irq_o : out std_logic;
busy_o : out std_logic
);
end component;
component i2c_master_wb_top
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
arst_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_inta_o: out std_logic;
scl : inout std_logic;
sda : inout std_logic
);
end component;
component wb_trigger_logic
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- To/From outside world
ext_trig_i : in std_logic_vector(3 downto 0);
ext_trig_o : out std_logic;
ext_busy_i : in std_logic;
ext_busy_o : out std_logic;
-- Eudet TLU
eudet_clk_o : out std_logic;
eudet_busy_o : out std_logic;
eudet_trig_i : in std_logic;
eudet_rst_i : in std_logic;
-- To/From inside world
clk_i : in std_logic;
--int_trig_i : in std_logic_vector(3 downto 0);
--int_trig_o : out std_logic;
--int_busy_i : in std_logic;
trig_tag : out std_logic_vector(31 downto 0);
debug_o : out std_logic_vector(31 downto 0)
);
end component;
COMPONENT ila_axis
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe21 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe23 : IN STD_LOGIC_VECTOR(28 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_wsh_pipe
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)--;
-- probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- probe10 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
-- probe11 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
-- probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe17 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_ddr
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_rx_dma_wb
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ;
end app_pkg;
package body app_pkg is
end app_pkg;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_opamp is
end tb_opamp;
architecture TB_opamp of tb_opamp is
-- Component declarations
-- Signal declarations
terminal in_src, op_neg2, out_opamp2 : electrical;
terminal out_opamp1, op_neg1, op_neg3, out_opamp3, out_opamp3_res, op_neg3_res : electrical;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0e-3
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
OP1 : entity work.opamp(slew_limited)
port map(
plus_in => electrical_ref,
minus_in => op_neg1,
output => out_opamp1
);
R1in : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => in_src,
p2 => op_neg1
);
R1F : entity work.resistor(ideal)
generic map(
res => 10.0e9
)
port map(
p1 => op_neg1,
p2 => out_opamp1
);
Rload1 : entity work.resistor(ideal)
generic map(
res => 1.0e3
)
port map(
p1 => out_opamp1,
p2 => electrical_ref
);
end TB_opamp;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_opamp is
end tb_opamp;
architecture TB_opamp of tb_opamp is
-- Component declarations
-- Signal declarations
terminal in_src, op_neg2, out_opamp2 : electrical;
terminal out_opamp1, op_neg1, op_neg3, out_opamp3, out_opamp3_res, op_neg3_res : electrical;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0e-3
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
OP1 : entity work.opamp(slew_limited)
port map(
plus_in => electrical_ref,
minus_in => op_neg1,
output => out_opamp1
);
R1in : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => in_src,
p2 => op_neg1
);
R1F : entity work.resistor(ideal)
generic map(
res => 10.0e9
)
port map(
p1 => op_neg1,
p2 => out_opamp1
);
Rload1 : entity work.resistor(ideal)
generic map(
res => 1.0e3
)
port map(
p1 => out_opamp1,
p2 => electrical_ref
);
end TB_opamp;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_opamp is
end tb_opamp;
architecture TB_opamp of tb_opamp is
-- Component declarations
-- Signal declarations
terminal in_src, op_neg2, out_opamp2 : electrical;
terminal out_opamp1, op_neg1, op_neg3, out_opamp3, out_opamp3_res, op_neg3_res : electrical;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0e-3
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
OP1 : entity work.opamp(slew_limited)
port map(
plus_in => electrical_ref,
minus_in => op_neg1,
output => out_opamp1
);
R1in : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => in_src,
p2 => op_neg1
);
R1F : entity work.resistor(ideal)
generic map(
res => 10.0e9
)
port map(
p1 => op_neg1,
p2 => out_opamp1
);
Rload1 : entity work.resistor(ideal)
generic map(
res => 1.0e3
)
port map(
p1 => out_opamp1,
p2 => electrical_ref
);
end TB_opamp;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cachemem
-- File: cachemem.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity cachemem is
generic (
tech : integer range 0 to NTECH := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
mmuen : integer range 0 to 1 := 0;
testen : integer range 0 to 3 := 0
);
port (
clk : in std_ulogic;
crami : in cram_in_type;
cramo : out cram_out_type;
sclk : in std_ulogic;
testin: in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of cachemem is
constant DSNOOPSEP : boolean := (dsnoop > 3);
constant DSNOOPFAST : boolean := (dsnoop = 2) or (dsnoop = 6);
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant ITAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + ilinesize + 1;
constant DTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + dlinesize + 1;
constant IPTAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + 1;
constant ILRR_BIT : integer := creplalg_tbl(irepl);
constant DLRR_BIT : integer := creplalg_tbl(drepl);
constant ITAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant DTAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant ICLOCK_BIT : integer := isetlock;
constant DCLOCK_BIT : integer := dsetlock;
constant ILRAM_BITS : integer := log2(ilramsize) + 10;
constant DLRAM_BITS : integer := log2(dlramsize) + 10;
constant ITDEPTH : natural := 2**IOFFSET_BITS;
constant DTDEPTH : natural := 2**DOFFSET_BITS;
constant MMUCTX_BITS : natural := 8*mmuen;
-- i/d tag layout
-- +-----+----------+---+--------+-----+-------+
-- | LRR | LOCK_BIT |PAR| MMUCTX | TAG | VALID |
-- +-----+----------+---+--------+-----+-------+
-- [opt] [ opt ] [ ] [ opt ] [ ]
constant ITWIDTH : natural := ITAG_BITS + ILRR_BIT + ICLOCK_BIT + MMUCTX_BITS
;
constant DTWIDTH : natural := DTAG_BITS + DLRR_BIT + DCLOCK_BIT + MMUCTX_BITS
;
constant IDWIDTH : natural := 32
;
constant DDWIDTH : natural := 32
;
constant DPTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + 1;
constant DTLRR_BIT_POS : natural := DTWIDTH-DLRR_BIT; -- if DTLRR_BIT=0 discard (pos DTWIDTH)
constant DTLOCK_BIT_POS : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT); -- if DTCLOCK_BIT=0 but DTLRR_BIT=1 lrr will overwrite
constant DTMMU_VEC_U : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT
)-1;
constant DTMMU_VEC_D : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT+
MMUCTX_BITS);
constant ITLRR_BIT_POS : natural := ITWIDTH-ILRR_BIT; -- if DLRR_BIT=0 discard (pos DTWIDTH)
constant ITLOCK_BIT_POS : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT); -- if DCLOCK_BIT=0 but DLRR_BIT=1 lrr will overwrite
constant ITMMU_VEC_U : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT
)-1;
constant ITMMU_VEC_D : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT+
MMUCTX_BITS);
constant DPTAG_RAM_BITS : integer := DPTAG_BITS
;
constant DTAG_RAM_BITS : integer := DTAG_BITS
;
subtype dtdatain_vector is std_logic_vector(DTWIDTH downto 0);
type dtdatain_type is array (0 to MAXSETS-1) of dtdatain_vector;
subtype itdatain_vector is std_logic_vector(ITWIDTH downto 0);
type itdatain_type is array (0 to MAXSETS-1) of itdatain_vector;
subtype dddatain_vector is std_logic_vector(DDWIDTH-1 downto 0);
type dddatain_type is array (0 to MAXSETS-1) of dddatain_vector;
subtype itdataout_vector is std_logic_vector(ITWIDTH downto 0);
type itdataout_type is array (0 to MAXSETS-1) of itdataout_vector;
subtype iddataout_vector is std_logic_vector(IDWIDTH -1 downto 0);
type iddataout_type is array (0 to MAXSETS-1) of iddataout_vector;
subtype dtdataout_vector is std_logic_vector(DTWIDTH downto 0);
type dtdataout_type is array (0 to MAXSETS-1) of dtdataout_vector;
subtype dddataout_vector is std_logic_vector(DDWIDTH -1 downto 0);
type dddataout_type is array (0 to MAXSETS-1) of dddataout_vector;
signal itaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
signal idaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
signal ildaddr : std_logic_vector(ILRAM_BITS-3 downto 0);
signal itdatain : itdatain_type;
signal itdatainx : itdatain_type;
signal itdatain_cmp : itdatain_type;
signal itdataout : itdataout_type;
signal iddatain : std_logic_vector(IDWIDTH -1 downto 0);
signal iddatainx : std_logic_vector(IDWIDTH -1 downto 0);
signal iddatain_cmp : std_logic_vector(IDWIDTH -1 downto 0);
signal iddataout : iddataout_type;
signal ildataout : std_logic_vector(31 downto 0);
signal itenable : std_ulogic;
signal idenable : std_ulogic;
signal itwrite : std_logic_vector(0 to MAXSETS-1);
signal idwrite : std_logic_vector(0 to MAXSETS-1);
signal dtaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr2 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr3 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal ddaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
signal ldaddr : std_logic_vector(DLRAM_BITS-1 downto 2);
signal dtdatain : dtdatain_type;
signal dtdatainx : dtdatain_type;
signal dtdatain_cmp : dtdatain_type;
signal dtdatain2 : dtdatain_type;
signal dtdatain3 : dtdatain_type;
signal dtdatainu : dtdatain_type;
signal dtdataout : dtdataout_type;
signal dtdataout2: dtdataout_type;
signal dtdataout3: dtdataout_type;
signal dddatain : dddatain_type;
signal dddatainx : dddatain_type;
signal dddatain_cmp : dddatain_type;
signal dddataout : dddataout_type;
signal lddatain, ldataout : std_logic_vector(31 downto 0);
signal dtenable : std_logic_vector(0 to MAXSETS-1);
signal dtenable2 : std_logic_vector(0 to MAXSETS-1);
signal ddenable : std_logic_vector(0 to MAXSETS-1);
signal dtwrite : std_logic_vector(0 to MAXSETS-1);
signal dtwrite2 : std_logic_vector(0 to MAXSETS-1);
signal dtwrite3 : std_logic_vector(0 to MAXSETS-1);
signal ddwrite : std_logic_vector(0 to MAXSETS-1);
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
itaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
idaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto 0);
ildaddr <= crami.icramin.address(ILRAM_BITS-3 downto 0);
itinsel : process(clk, crami, dtdataout2, dtdataout3
)
variable viddatain : std_logic_vector(IDWIDTH -1 downto 0);
variable vdddatain : dddatain_type;
variable vitdatain : itdatain_type;
variable vdtdatain : dtdatain_type;
variable vdtdatain2 : dtdatain_type;
variable vdtdatain3 : dtdatain_type;
variable vdtdatainu : dtdatain_type;
begin
viddatain := (others => '0');
vdddatain := (others => (others => '0'));
viddatain(31 downto 0) := crami.icramin.data;
for i in 0 to DSETS-1 loop
vdtdatain(i) := (others => '0');
if mmuen = 1 then
vdtdatain(i)(DTMMU_VEC_U downto DTMMU_VEC_D) := crami.dcramin.ctx(i);
end if;
vdtdatain(i)(DTLOCK_BIT_POS) := crami.dcramin.tag(i)(CTAG_LOCKPOS);
if drepl = lrr then
vdtdatain(i)(DTLRR_BIT_POS) := crami.dcramin.tag(i)(CTAG_LRRPOS);
end if;
vdtdatain(i)(DTAG_BITS-1 downto 0) := crami.dcramin.tag(i)(TAG_HIGH downto DTAG_LOW) & crami.dcramin.tag(i)(dlinesize-1 downto 0);
if (crami.dcramin.flush(i) = '1') then
vdtdatain(i) := (others => '0');
vdtdatain(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"FF";
vdtdatain(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
for i in 0 to DSETS-1 loop
vdtdatain2(i) := (others => '0');
vdddatain(i)(31 downto 0) := crami.dcramin.data(i);
vdtdatain2(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"FF";
vdtdatain2(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain2(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end loop;
vdtdatainu := (others => (others => '0'));
vdtdatain3 := (others => (others => '0'));
for i in 0 to DSETS-1 loop
vdtdatain3(i) := (others => '0');
vdtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS) := crami.dcramin.ptag(i)(TAG_HIGH downto DTAG_LOW);
if DSNOOPSEP and (crami.dcramin.flush(i) = '1') then
vdtdatain3(i) := (others => '0');
vdtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"F3";
vdtdatain3(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain3(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
for i in 0 to ISETS-1 loop
vitdatain(i) := (others => '0');
if mmuen = 1 then
vitdatain(i)(ITMMU_VEC_U downto ITMMU_VEC_D) := crami.icramin.ctx;
end if;
vitdatain(i)(ITLOCK_BIT_POS) := crami.icramin.tag(i)(CTAG_LOCKPOS);
if irepl = lrr then
vitdatain(i)(ITLRR_BIT_POS) := crami.icramin.tag(i)(CTAG_LRRPOS);
end if;
vitdatain(i)(ITAG_BITS-1 downto 0) := crami.icramin.tag(i)(TAG_HIGH downto ITAG_LOW)
& crami.icramin.tag(i)(ilinesize-1 downto 0);
if (crami.icramin.flush = '1') then
vitdatain(i) := (others => '0');
vitdatain(i)(ITAG_BITS-1 downto ITAG_BITS-8) := X"FF";
vitdatain(i)(ITAG_BITS-9 downto ITAG_BITS-10) := conv_std_logic_vector(i,2);
vitdatain(i)(ITAG_BITS-11 downto ITAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
-- pragma translate_off
itdatainx <= vitdatain; iddatainx <= viddatain;
dtdatainx <= vdtdatain; dddatainx <= vdddatain;
-- pragma translate_on
itdatain <= vitdatain; iddatain <= viddatain;
dtdatain <= vdtdatain; dtdatain2 <= vdtdatain2; dddatain <= vdddatain;
dtdatain3 <= vdtdatain3;
end process;
itwrite <= crami.icramin.twrite;
idwrite <= crami.icramin.dwrite;
itenable <= crami.icramin.tenable;
idenable <= crami.icramin.denable;
dtaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
dtaddr2 <= crami.dcramin.saddress(DOFFSET_BITS-1 downto 0);
dtaddr3 <= crami.dcramin.faddress(DOFFSET_BITS-1 downto 0);
ddaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto 0);
ldaddr <= crami.dcramin.ldramin.address(DLRAM_BITS-1 downto 2);
dtwrite <= crami.dcramin.twrite;
dtwrite2 <= crami.dcramin.swrite;
dtwrite3 <= crami.dcramin.tpwrite;
ddwrite <= crami.dcramin.dwrite;
dtenable <= crami.dcramin.tenable;
dtenable2 <= crami.dcramin.senable;
ddenable <= crami.dcramin.denable;
ime : if icen = 1 generate
im0 : for i in 0 to ISETS-1 generate
itags0 : syncram generic map (tech, IOFFSET_BITS, ITWIDTH, testen, memtest_vlen)
port map ( clk, itaddr, itdatain(i)(ITWIDTH-1 downto 0), itdataout(i)(ITWIDTH-1 downto 0), itenable, itwrite(i), testin
);
idata0 : syncram generic map (tech, IOFFSET_BITS+ILINE_BITS, IDWIDTH, testen, memtest_vlen)
port map (clk, idaddr, iddatain, iddataout(i), idenable, idwrite(i), testin
);
itdataout(i)(ITWIDTH) <= '0';
end generate;
end generate;
imd : if icen = 0 generate
ind0 : for i in 0 to ISETS-1 generate
itdataout(i) <= (others => '0');
iddataout(i) <= (others => '0');
end generate;
end generate;
ild0 : if ilram = 1 generate
ildata0 : syncram
generic map (tech, ILRAM_BITS-2, 32, testen, memtest_vlen)
port map (clk, ildaddr, iddatain, ildataout,
crami.icramin.ldramin.enable, crami.icramin.ldramin.write, testin
);
end generate;
dme : if dcen = 1 generate
dtags0 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram
generic map (tech, DOFFSET_BITS, DTWIDTH, testen, memtest_vlen)
port map (clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i), testin
);
end generate;
end generate;
dtags1 : if DSNOOP /= 0 generate
dt1 : if not DSNOOPSEP generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH, testen, memtest_vlen) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto 0),
dtdataout2(i)(DTWIDTH-1 downto 0), dtenable2(i), dtwrite2(i), testin
);
end generate;
end generate;
-- virtual address snoop case
mdt1 : if DSNOOPSEP generate
slow : if not DSNOOPFAST generate
mdt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH-dlinesize+1, testen, memtest_vlen) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto dlinesize-1),
dtdataout(i)(DTWIDTH-1 downto dlinesize-1), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto dlinesize-1),
dtdataout2(i)(DTWIDTH-1 downto dlinesize-1), dtenable2(i), dtwrite2(i), testin
);
dtags1 : syncram_dp
generic map (tech, DOFFSET_BITS, DPTAG_RAM_BITS, testen, memtest_vlen) port map (
clk, dtaddr, dtdatain3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
open, dtwrite3(i), dtwrite3(i),
sclk, dtaddr2, dtdatainu(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
dtdataout3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS), dtenable2(i), dtwrite2(i),
testin
);
end generate;
end generate;
fast : if DSNOOPFAST generate
mdt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_2p
generic map (tech, DOFFSET_BITS, DTWIDTH-dlinesize+1, 0, 1, testen, 0, memtest_vlen) port map (
clk, dtenable(i), dtaddr, dtdataout(i)(DTWIDTH-1 downto dlinesize-1),
sclk, dtwrite2(i), dtaddr3, dtdatain(i)(DTWIDTH-1 downto dlinesize-1), testin
);
dtags1 : syncram_2p
generic map (tech, DOFFSET_BITS, DPTAG_RAM_BITS, 0, 1, testen, 0, memtest_vlen) port map (
sclk, dtenable2(i), dtaddr2, dtdataout3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
clk, dtwrite3(i), dtaddr, dtdatain3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
testin
);
end generate;
end generate;
end generate;
end generate;
nodtags1 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtdataout2(i)(DTWIDTH-1 downto 0) <= zero64(DTWIDTH-1 downto 0);
end generate;
end generate;
dd0 : for i in 0 to DSETS-1 generate
ddata0 : syncram
generic map (tech, DOFFSET_BITS+DLINE_BITS, DDWIDTH, testen, memtest_vlen)
port map (clk, ddaddr, dddatain(i), dddataout(i), ddenable(i), ddwrite(i), testin
);
dtdataout(i)(DTWIDTH) <= '0';
end generate;
end generate;
dmd : if dcen = 0 generate
dnd0 : for i in 0 to DSETS-1 generate
dtdataout(i) <= (others => '0');
dtdataout2(i) <= (others => '0');
dddataout(i) <= (others => '0');
end generate;
end generate;
ldxs0 : if not ((dlram = 1) and (DSETS > 1)) generate
lddatain <= dddatain(0)(31 downto 0);
end generate;
ldxs1 : if (dlram = 1) and (DSETS > 1) generate
lddatain <= dddatain(1)(31 downto 0);
end generate;
ld0 : if dlram = 1 generate
ldata0 : syncram
generic map (tech, DLRAM_BITS-2, 32, testen, memtest_vlen)
port map (clk, ldaddr, lddatain, ldataout, crami.dcramin.ldramin.enable,
crami.dcramin.ldramin.write, testin
);
end generate;
itx : for i in 0 to ISETS-1 generate
cramo.icramo.tag(i)(TAG_HIGH downto ITAG_LOW) <= itdataout(i)(ITAG_BITS-1 downto (ITAG_BITS-1) - (TAG_HIGH - ITAG_LOW));
--(ITWIDTH-1-(ILRR_BIT+ICLOCK_BIT) downto ITWIDTH-(TAG_HIGH-ITAG_LOW)-(ILRR_BIT+ICLOCK_BIT)-1);
cramo.icramo.tag(i)(ilinesize-1 downto 0) <= itdataout(i)(ilinesize-1 downto 0);
cramo.icramo.tag(i)(CTAG_LRRPOS) <= itdataout(i)(ITLRR_BIT_POS);
cramo.icramo.tag(i)(CTAG_LOCKPOS) <= itdataout(i)(ITLOCK_BIT_POS);
ictx : if mmuen = 1 generate
cramo.icramo.ctx(i) <= itdataout(i)(ITMMU_VEC_U downto ITMMU_VEC_D);
end generate;
noictx : if mmuen = 0 generate
cramo.icramo.ctx(i) <= (others => '0');
end generate;
cramo.icramo.data(i) <= ildataout when (ilram = 1) and ((ISETS = 1) or (i = 1)) and (crami.icramin.ldramin.read = '1') else iddataout(i)(31 downto 0);
itv : if ilinesize = 4 generate
cramo.icramo.tag(i)(7 downto 4) <= (others => '0');
end generate;
ite : for j in 10 to ITAG_LOW-1 generate
cramo.icramo.tag(i)(j) <= '0';
end generate;
end generate;
itx2 : for i in ISETS to MAXSETS-1 generate
cramo.icramo.tag(i) <= (others => '0');
cramo.icramo.data(i) <= (others => '0');
cramo.icramo.ctx(i) <= (others => '0');
end generate;
itd : for i in 0 to DSETS-1 generate
cramo.dcramo.tag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
-- cramo.dcramo.tag(i)(dlinesize-1 downto 0) <= dtdataout(i)(dlinesize-1 downto 0);
cramo.dcramo.tag(i)(dlinesize-1 downto 0) <= (others => dtdataout(i)(dlinesize-1));
cramo.dcramo.tag(i)(CTAG_LRRPOS) <= dtdataout(i)(DTLRR_BIT_POS);
cramo.dcramo.tag(i)(CTAG_LOCKPOS) <= dtdataout(i)(DTLOCK_BIT_POS);
dctx : if mmuen /= 0 generate
cramo.dcramo.ctx(i) <= dtdataout(i)(DTMMU_VEC_U downto DTMMU_VEC_D);
end generate;
nodctx : if mmuen = 0 generate
cramo.dcramo.ctx(i) <= (others => '0');
end generate;
stagv : if DSNOOPSEP generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout3(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
cramo.dcramo.stag(i)(DTAG_LOW-1 downto 0) <= (others =>'0');
end generate;
stagp : if not DSNOOPSEP generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout2(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
cramo.dcramo.stag(i)(DTAG_LOW-1 downto 0) <= (others =>'0');
end generate;
cramo.dcramo.data(i) <= ldataout when (dlram = 1) and ((DSETS = 1) or (i = 1)) and (crami.dcramin.ldramin.read = '1')
else dddataout(i)(31 downto 0);
dtv : if dlinesize = 4 generate
cramo.dcramo.tag(i)(7 downto 4) <= (others => '0');
end generate;
dte : for j in 10 to DTAG_LOW-1 generate
cramo.dcramo.tag(i)(j) <= '0';
end generate;
end generate;
itd2 : for i in DSETS to MAXSETS-1 generate
cramo.dcramo.tag(i) <= (others => '0');
cramo.dcramo.stag(i) <= (others => '0');
cramo.dcramo.data(i) <= (others => '0');
cramo.dcramo.ctx(i) <= (others => '0');
end generate;
noilr: if ilram=0 generate
ildataout <= (others => '0');
end generate;
nodlr: if dlram=0 generate
ldataout <= (others => '0');
end generate;
end ;
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Simple parameterized clock divider that uses a counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all; -- don't use for synthesis, but OK for static numbers
entity clk_div is
generic (
clk_in_freq : natural;
clk_out_freq : natural
);
port (
rst : in std_logic;
clk_in : in std_logic;
clk_out : out std_logic
);
end clk_div;
architecture BHV of clk_div is
constant OUT_PERIOD_COUNT : integer := (clk_in_freq/clk_out_freq)-1;
begin
process(clk_in, rst)
variable count : integer range 0 to OUT_PERIOD_COUNT; -- note: integer type defaults to 32-bits wide unless you specify the range yourself
begin
if(rst = '1') then
count := 0;
clk_out <= '0';
elsif(rising_edge(clk_in)) then
if(count = OUT_PERIOD_COUNT) then
count := 0;
else
count := count + 1;
end if;
if(count > OUT_PERIOD_COUNT/2) then
clk_out <= '1';
else
clk_out <= '0';
end if;
end if;
end process;
end BHV;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1916.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01916ent IS
END c07s02b01x00p01n01i01916ent;
ARCHITECTURE c07s02b01x00p01n01i01916arch OF c07s02b01x00p01n01i01916ent IS
BEGIN
TESTING: PROCESS
variable b1 : bit := '0';
BEGIN
b1 := b1 or b1;
assert NOT(b1 = '0')
report "***PASSED TEST: c07s02b01x00p01n01i01916"
severity NOTE;
assert (b1 = '0')
report "***FAILED TEST: c07s02b01x00p01n01i01916 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01916arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1916.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01916ent IS
END c07s02b01x00p01n01i01916ent;
ARCHITECTURE c07s02b01x00p01n01i01916arch OF c07s02b01x00p01n01i01916ent IS
BEGIN
TESTING: PROCESS
variable b1 : bit := '0';
BEGIN
b1 := b1 or b1;
assert NOT(b1 = '0')
report "***PASSED TEST: c07s02b01x00p01n01i01916"
severity NOTE;
assert (b1 = '0')
report "***FAILED TEST: c07s02b01x00p01n01i01916 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01916arch;
|
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