content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity testbench is
end entity;
architecture simu of testbench is
-- Dummy control
signal clk : std_logic := '0';
signal simu_clock_enable : std_logic := '1';
-- Dummy source signal
signal data_src : std_lo... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
-- Date : Wed Mar 15 19:17:33 2017
-- Host : ul-43 running 64-bit Service Pac... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
-- Date : Wed Mar 15 19:17:33 2017
-- Host : ul-43 running 64-bit Service Pac... |
--!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: counter.vhd
--! @brief:
--! @author: Antonio Gutierrez
--! @date: 2014-05-23
--!
--!
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.al... |
-- *********************************************************************/
-- Copyright 1998 Actel Corporation. All rights reserved.
--
-- File: TBPACK.VHD
--
-- Description: Package used by the Testbench for the UART
--
-- Rev: 1.0 08Apr98 IPB Development 1.0
--
-- Notes:
--
-- ********************************... |
library ieee;
use ieee.std_logic_1164.all;
package types_pkg is
type sl2d_t is array(natural range <>,natural range <>) of std_logic;
type slv_7_0_t is array(natural range <>) of std_logic_vector(7 downto 0);
subtype ram_bank_t is slv_7_0_t(0 to 32767);
type ram_t is array(0 to 3) of ram_bank_t;
end pa... |
--------------------------------------------------------------------------------
--! @file topmetal_analog_scan.vhd
--! @brief Generate appropriate signals for driving the analog scan of Topmetal array.
--! @author Yuan Mei
--!
--! The bram_sdp_w32r4 must have read latency of 1 (select no register on output).
---------... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 IS
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 IS
when STATE_1=>
a <= b;
... |
----------------------------------------------------------------------------------
-- Responsáveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
-- Ultima mod.: 03/jun/2017
-- Nome do Módulo: Registrador
-- Descrição: Registrador com largura de palavra parametrizável
-- e com habili... |
package pack1 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
package pack2 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
use work.pack1;
use work.p... |
package pack1 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
package pack2 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
use work.pack1;
use work.p... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNJGR7GQ2L is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNJGR7GQ2L is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNJGR7GQ2L is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNJGR7GQ2L is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNJGR7GQ2L is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNJGR7GQ2L is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNJGR7GQ2L is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNJGR7GQ2L is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
-------------------------------------------------------------------------------
--
-- File: Packet_Decoder.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright ... |
-------------------------------------------------------------------------------
--
-- File: Packet_Decoder.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CPU is
port (
-- debug
Control : IN std_logic_vector( 5 downto 0);
Operand1 : IN std_logic_vector(31 downto 0);
Operand2 : IN std_logic_vector(31 downto 0);
Result1 : OUT std_logic_vector(31 downto 0);
Result2 :... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
... |
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
... |
entity test is
type t is protected body end protected;
end;
|
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ***********************************************... |
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ***********************************************... |
---------------------------------------------------------------------------------
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is f... |
---------------------------------------------------------------------------------
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is f... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.NoCPackage.all;
entity Thor_crossbar is
port(
data_av: in regNport;
data_in: in arrayNport_regflit;
data_ack: out regNport;
sender: in regNport;
free: in regNport;
tab_in: in arrayNpor... |
-- Gray_Processing_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.11:11:33
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Processing_GN is
port (
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- Avalon_ST_Source_dat... |
-- Gray_Processing_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.11:11:33
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Processing_GN is
port (
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- Avalon_ST_Source_dat... |
-- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- Control workflow
-- Requests Multiplexer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity master is
port (
-- control signals
clk : in std_log... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_5_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 06:48:17 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
--------------------------------------------------------------------------------
-- Title : DMA Master FSM
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_dma_mstr.vhd
-- Author : michael.miehling@men.de
-- Organization ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- cpu.vhd: Simple 8-bit CPU (BrainFuck interpreter)
-- Copyright (C) 2014 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Dávid Mikuš (xmikus15)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- -------... |
-- Simon.vhd
-- Copyright 2016 Michael Calvin McCoy
-- calvin.mccoy@gmail.com
-- see LICENSE.md
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.SIMON_CONSTANTS.all;
entity SIMON_CIPHER is
Generic(KEY_SIZE : integer range 0 to 256 := 256;
BLOCK_SIZE : integer range 0 to 128 := 128;
... |
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-----------------------------------------------------------------------------------------------... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... |
library verilog;
use verilog.vl_types.all;
entity reservation_alu3_entry is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE_VALID : in vl_logic;
iREGISTER_VALID : in vl_logic;
iREGISTER_CMD : in vl_logic_vector(4 downto 0);
... |
--
-- bubble_sorter_tb.vhd
-- Simulation testbench for bubble_sorter.vhd
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Pad... |
--
-- bubble_sorter_tb.vhd
-- Simulation testbench for bubble_sorter.vhd
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Pad... |
library verilog;
use verilog.vl_types.all;
entity Controller_vlg_vec_tst is
end Controller_vlg_vec_tst;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2016-03-25 13:21:34.929354
-- Design Name: Wishbone intercon
-- Module Name: the_intercon
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
--... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity test is
end test;
architecture only of test is
begin -- only
p: process
begin -- process p
wait for 1 ns;
assert now = 1 ns report "TEST FAILED" severity FAILURE;
wait for 10 ns;
assert now = 11 ns report "TEST FAILED" severity FAILURE;
report "PASSED TEST" severity NOTE;
wait;
e... |
entity test is
end test;
architecture only of test is
begin -- only
p: process
begin -- process p
wait for 1 ns;
assert now = 1 ns report "TEST FAILED" severity FAILURE;
wait for 10 ns;
assert now = 11 ns report "TEST FAILED" severity FAILURE;
report "PASSED TEST" severity NOTE;
wait;
e... |
entity test is
end test;
architecture only of test is
begin -- only
p: process
begin -- process p
wait for 1 ns;
assert now = 1 ns report "TEST FAILED" severity FAILURE;
wait for 10 ns;
assert now = 11 ns report "TEST FAILED" severity FAILURE;
report "PASSED TEST" severity NOTE;
wait;
e... |
package myfixed is
generic ( whole : natural; frac : natural );
constant width : natural := whole + frac;
type fixed_t is array (1 to width) of bit;
function "+"(x, y : fixed_t) return fixed_t;
function total_bits return natural;
end package;
package body myfixed is
function total_bits re... |
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 02/10/2018 06:05:22 PM
-- Module Name: simple_core - Behavioral
-- Description: Incremental build of the simplified processor core
--
-- Additional Comments:
--
---------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 11:18:33 11/14/2015
-- Design Name:
-- Module Name: PCAdder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenci... |
library verilog;
use verilog.vl_types.all;
entity tb_FinalProject is
generic(
BYTE : integer := 8;
ADDR_WIDTH : vl_notype;
WORD : vl_notype;
DATA_WIDTH : vl_notype;
MEM_DEPTH : integer := 256
);
attribute mti_svvh_generic_type : i... |
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any deriv... |
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any deriv... |
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any deriv... |
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any deriv... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This progra... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity menu is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
nes_up, nes_down: in std_logic;
selection: out std_logic;
rgb_pixel: out std_logic_vector(2 downto 0)
... |
library ieee;
use ieee.std_logic_1164.all;
entity gen_AND_bit is
generic
(
width : integer := 4
);
port
(
input : std_logic_vector(width - 1 downto 0);
output : out std_logic
);
end gen_AND_bit;
architecture Behavior of gen_AND_bit is
begin
P0 : process (input)
variable result : std_logic;
begin
res... |
architecture b of a is
begin -- architecture b
end architecture b;
|
architecture b of a is
begin -- architecture b
end architecture b;
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for BPM Orbit Interlock Interface Registers
---------------------------------------------------------------------------------------
-- File : wb_orbit_intlk_regs.vhd
-- Author ... |
Library ieee;
use ieee.std_logic_1164.all;
entity secondb is
port(
A, B, C: buffer std_logic;
CLK: in std_logic
);
end secondb;
architecture solution of secondb is
component jk
port(
J,K, CLK : IN std_logic;
Q: OUT std_logic
);
end component;
begin
jk2: jk port map(
'1', C or B, CLK, A
);
... |
-- file: clk_wiz_v3_6.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is n... |
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s832_jed is
port(
clock: in std_logic;
input: in std_logic_vector(17 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s832_jed;
architecture behaviour of s832_jed is
constant s00000: std_logic_vector(4 downto 0)... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity de0_nano_system is
port
( CLOCK_50 : in std_logic
; GPIO_0 : inout std_logic_vector(33 downto 0)
; GPIO_1 : inout std_logic_vector(33 downto 0)
-- Removed for logic analyser GPIO_2 : inou... |
entity snum02 is
port (ok : out boolean);
end snum02;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of snum02 is
-- add sgn int
constant a1 : signed (7 downto 0) := x"1d";
constant b1 : integer := 3;
constant r1 : signed (7 downto 0) := a1 + b1;
constant a2 : ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity data_maker is
port (
CLK : in std_logic;
RST_n : in std_logic;
VOUT : out std_logic;
DOUT : o... |
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