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------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: usbhc_unisimpkg
-- File: usbhc_unisimpkg.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: Component declartions for the tech wrapper for unisim/xilinx
-- usbhc netlists
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package usbhc_unisimpkg is
component usbhc_unisim_comb0
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_unisim_comb1
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*0 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*0 downto 1*0);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hlock : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbmo_hwrite : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*0 downto 1*0);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*0 downto 1*0);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hresp : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*0 downto 1*0);
uhc_ahbso_hcache : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hirq : out std_logic_vector(1*0 downto 1*0);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
sie11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
sie11_pb_en : out std_logic_vector(1*0 downto 1*0);
sie11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_sie11_data : in std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
mbc11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_en : out std_logic_vector(1*0 downto 1*0);
mbc11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_mbc11_data : in std_logic_vector((1*32)*0 downto 1*0);
bufsel : out std_ulogic);
end component;
component usbhc_unisim_comb2
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_unisim_comb3
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((2*2)-1) downto 0);
termsel : out std_logic_vector((2-1) downto 0);
suspendm : out std_logic_vector((2-1) downto 0);
opmode : out std_logic_vector(((2*2)-1) downto 0);
txvalid : out std_logic_vector((2-1) downto 0);
drvvbus : out std_logic_vector((2-1) downto 0);
dataho : out std_logic_vector(((2*8)-1) downto 0);
validho : out std_logic_vector((2-1) downto 0);
host : out std_logic_vector((2-1) downto 0);
stp : out std_logic_vector((2-1) downto 0);
datao : out std_logic_vector(((2*8)-1) downto 0);
utm_rst : out std_logic_vector((2-1) downto 0);
dctrlo : out std_logic_vector((2-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((2*2)-1) downto 0);
txready : in std_logic_vector((2-1) downto 0);
rxvalid : in std_logic_vector((2-1) downto 0);
rxactive : in std_logic_vector((2-1) downto 0);
rxerror : in std_logic_vector((2-1) downto 0);
vbusvalid : in std_logic_vector((2-1) downto 0);
datahi : in std_logic_vector(((2*8)-1) downto 0);
validhi : in std_logic_vector((2-1) downto 0);
hostdisc : in std_logic_vector((2-1) downto 0);
nxt : in std_logic_vector((2-1) downto 0);
dir : in std_logic_vector((2-1) downto 0);
datai : in std_logic_vector(((2*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean;
end usbhc_unisimpkg;
package body usbhc_unisimpkg is
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean is
begin
-- comb0
if nports = 1 and ehcgen = 0 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb1
if nports = 1 and ehcgen = 1 and uhcgen = 0 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb2
if nports = 1 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb3
if nports = 2 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 2 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
return false;
end valid_comb;
end usbhc_unisimpkg;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cham_rom_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY cham_rom_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE cham_rom_synth_ARCH OF cham_rom_synth IS
COMPONENT cham_rom_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: cham_rom_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY reg_file IS
generic
(
BYTES : natural := 1;
WIDTH : natural := 1
);
PORT
(
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END reg_file;
ARCHITECTURE vhdl OF reg_file IS
component complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END component;
type reg_file_type is array(bytes-1 downto 0) of std_LOGIC_VECTOR(7 downto 0);
signal digit_next : reg_file_type;
signal digit_reg : reg_file_type;
signal addr_decoded : std_logic_vector(2**width-1 downto 0);
BEGIN
complete_address_decoder1 : complete_address_decoder
generic map (width => WIDTH)
port map (addr_in => addr, addr_decoded => addr_decoded);
-- next state logic
process(digit_reg,addr_decoded,data_in,WR_EN)
begin
digit_next <= digit_reg;
if (WR_EN = '1') then
comp_gen:
for i in 0 to (BYTES-1) loop
if (addr_decoded(i) = '1') then
digit_next(i) <= data_in;
end if;
end loop;
end if;
end process;
-- register
process(clk)
begin
if (clk'event and clk='1') then
digit_reg <= digit_next;
end if;
end process;
-- output
process(addr_decoded,digit_reg)
begin
data_out <= X"FF";
comp_gen:
for i in 0 to (BYTES-1) loop
if (addr_decoded(i) = '1') then
data_out <= digit_reg(i);
end if;
end loop;
end process;
END vhdl; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 4;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex6_jed is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(7 downto 0)
);
end ex6_jed;
architecture behaviour of ex6_jed is
constant s1: std_logic_vector(2 downto 0) := "000";
constant s3: std_logic_vector(2 downto 0) := "010";
constant s2: std_logic_vector(2 downto 0) := "111";
constant s4: std_logic_vector(2 downto 0) := "110";
constant s5: std_logic_vector(2 downto 0) := "001";
constant s6: std_logic_vector(2 downto 0) := "011";
constant s7: std_logic_vector(2 downto 0) := "100";
constant s8: std_logic_vector(2 downto 0) := "101";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--------";
case current_state is
when s1 =>
if std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11000000";
elsif std_match(input, "10---") then next_state <= s4; output <= "00101000";
end if;
when s2 =>
if std_match(input, "0-0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--1--") then next_state <= s5; output <= "00001110";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s3 =>
if std_match(input, "10---") then next_state <= s4; output <= "00111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11010000";
elsif std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "01---") then next_state <= s6; output <= "00110101";
end if;
when s4 =>
if std_match(input, "010--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "--1--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "000--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s5 =>
if std_match(input, "1-10-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--11-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "0-10-") then next_state <= s5; output <= "00001110";
end if;
when s6 =>
if std_match(input, "----1") then next_state <= s2; output <= "11000001";
elsif std_match(input, "10--0") then next_state <= s4; output <= "00101001";
elsif std_match(input, "00--0") then next_state <= s2; output <= "11000001";
elsif std_match(input, "11--0") then next_state <= s3; output <= "10111001";
elsif std_match(input, "01--0") then next_state <= s6; output <= "00100101";
end if;
when s7 =>
if std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "011--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "001--") then next_state <= s2; output <= "11000000";
end if;
when s8 =>
if std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "0-1--") then next_state <= s8; output <= "10000100";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
end if;
when others => next_state <= "---"; output <= "--------";
end case;
end process;
end behaviour;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.picpkg.all;
entity datapath is
Port ( clk,reset : in STD_LOGIC;
instr10 : in STD_LOGIC_VECTOR(10 downto 0);
writedata : out std_logic_vector(7 downto 0);
readdata : in std_logic_vector(7 downto 0);
alu_op : in alu_ctrl;
write_en : out std_logic;
bmux,rwmux,writew : in std_logic;
amux : in std_logic_vector(1 downto 0);
status_flags : out std_logic_Vector(4 downto 0);
status_c_in : in std_logic;
skip_ex : in std_logic);
end datapath;
architecture Behavioral of datapath is
signal wnext, w : std_logic_vector(7 downto 0);
signal alu_z, alu_c, alu_dc : std_logic;
signal amux_out, bmux_out : std_logic_vector(7 downto 0);
signal alu_result : std_logic_vector(7 downto 0);
begin
-- If skip_ex is '1' skipped instruction is computed, but not stored
-- Write ALU result to RAM
write_en <= rwmux and not skip_ex;
-- Source of next W value
wnext <= alu_result when writew = '1' and skip_ex = '0' else w;
-- RAM input data is always ALU result
writedata <= alu_result;
-- Status flags from ALU to IO
status_flags <= "00"&alu_z&alu_dc&alu_c;
w_reg : entity work.flopr
generic map( WIDTH => 8)
port map(clk => clk,
reset => reset,
d => wnext,
q => w
);
-- ALU A mux
amux_out <= instr10(7 downto 0) when amux = "00" else
readdata when amux = "01" else
"00000000" when amux = "10" else
"--------";
-- ALU B mux
bmux_out <= w when bmux = '0' else "00000001";
alu1 : entity work.alu
Port map( a => amux_out,
b => bmux_out,
ctrl => alu_op,
bit_clr_set => instr10(10),
bit_sel => instr10(9 downto 7),
status_c => status_c_in,
r => alu_result,
z => alu_z,
c => alu_c,
dc => alu_dc
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.10.2017 19:54:01
-- Design Name:
-- Module Name: get_mark_points - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity get_mark_points is
GENERIC(byte_per_pixel : natural := 3;
width : natural := 480;
hight : natural := 640);
PORT(resetn : in STD_LOGIC;
clk : in STD_LOGIC;
vsync : in STD_LOGIC;
href : in STD_LOGIC;
px_data : in STD_LOGIC_VECTOR(7 downto 0);
--- out
data_ready : out STD_LOGIC; -- auf steigende flanke clk, data abnehmen
px_count_out, line_count_out : out positive;
px_data_out : out STD_LOGIC_VECTOR(byte_per_pixel*8 - 1 downto 0)
);
end get_mark_points;
architecture Behavioral of get_mark_points is
signal bit_number : natural := 0;
begin
byte_counts : process(clk)
variable px_count, line_count : natural := 0;
begin
if (clk'event and clk = '0') then
if resetn = '0' then
px_data_out <= (others => '0');
data_ready <= '0';
else
-- VSYNC
if (vsync = '1') then
px_count := 0;
line_count := 0;
end if;
data_ready <= '0';
if (href = '1') then
case bit_number is
when 0 => px_data_out(23 downto 16) <= px_data;
when 1 => px_data_out(15 downto 8) <= px_data;
when 2 => px_data_out(7 downto 0) <= px_data;
when others =>
end case;
if ( bit_number = byte_per_pixel - 1) then
px_count := px_count + 1;
bit_number <= 0;
data_ready <= '1';
else
bit_number <= bit_number + 1;
end if;
else
px_count := 0;
bit_number <= 0;
end if;
if px_count = width then
line_count := line_count + 1;
end if;
px_count_out <= px_count;
line_count_out <= line_count;
end if;
end if;
end process;
end Behavioral;
|
-- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : general_purpose_register_bank
-- Date : 07/07/2016
--
-- Description : Bank of 32 general purpose registers
--
-- --------------------------------------------------------------------------------
-- Modifications
-- --------------------------------------------------------------------------------
-- Date : Ver. : Author : Modification comments
-- --------------------------------------------------------------------------------
-- : : :
-- 25/07/2016 : 1.0 : B.Lemoine : First draft
-- : : :
-- **********************************************************************************
-- MIT License
--
-- Copyright (c) 07/07/2016, Benjamin Lemoine
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- **********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity general_purpose_register_bank is
generic(
D_WIDTH : natural := 32
);
port(
clk : in std_logic;
addr_i : in std_logic_vector(4 downto 0);
data_i : in std_logic_vector(D_WIDTH-1 downto 0);
wr_i : in std_logic;
data_o : in std_logic_vector(D_WIDTH-1 downto 0);
);
)end general_purpose_register_bank;
architecture rtl of general_purpose_register_bank is
-- Component declaration
-- -----------------------
component ram_single_port is
generic (
ADDR_WIDTH : integer := 15;
DATA_WIDTH : integer := 32
);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
di : in std_logic_vector(NB_COL*COL_WIDTH-1 downto 0);
do : out std_logic_vector(NB_COL*COL_WIDTH-1 downto 0)
);
end component;
-- Signal declaration
-- -----------------------
signal s_wr_en_filt : std_logic := '0';
begin
-- R0 : Always has a value of zero. Anything written to R0 is discarded
s_wr_en_filt <= '0' when addr_i = (others => '0') else wr_i;
i_reg32 : ram_single_port
generic map(
ADDR_WIDTH => 4,
DATA_WIDTH => D_WIDTH,
)
port map(
clk => clk,
we => s_wr_en_filt,
addr => addr_i,
di => data_i,
do => data_o
);
end rtl;
|
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`protect end_protected
|
--------------------------------------------
-- Project: FE65-P2 addon
-- Author: Timon Heim (timon.heim@cern.ch)
-- Description: Attaches to serial port and controls FE65-P2 adapter
-- Dependencies: -
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity fe65p2_addon is
port (
clk_i : IN std_logic;
rst_n : IN std_logic;
serial_in : IN std_logic;
clk_rx_i : IN std_logic;
-- TO FMC
clk_bx_o : out std_logic;
trig_o : out std_logic;
clk_cnfg_o : out std_logic;
en_pix_sr_cnfg_o : out std_logic;
ld_cnfg_o : out std_logic;
si_cnfg_o : out std_logic;
pix_d_cnfg_o : out std_logic;
clk_data_o : out std_logic;
rst_0_o : out std_logic;
rst_1_o : out std_logic;
dac_sclk_o : out std_logic;
dac_sdi_o : out std_logic;
dac_ld_o : out std_logic;
dac_cs_o : out std_logic;
inj_sw_o : out std_logic
);
end fe65p2_addon;
architecture behavioral of fe65p2_addon is
-- System signals
signal sys_rst : std_logic;
signal clk_40 : std_logic;
-- clocks
signal clk_bx_t : std_logic;
signal clk_cnfg_t : std_logic;
signal clk_data_t : std_logic;
signal en_bx_clk : std_logic;
signal en_conf_clk : std_logic;
signal en_data_clk : std_logic;
-- cmd deserialiser
signal yarr_cmd : std_logic;
signal cmd_count : unsigned(7 downto 0);
signal cmd_valid : std_logic;
signal cmd_sreg : std_logic_vector(31 downto 0);
-- cmd decoder
signal new_cmd : std_logic;
signal adr : std_logic_vector(15 downto 0);
signal payload : std_logic_vector(15 downto 0);
-- registers
signal conf_reg : std_logic_vector(159 downto 0);
signal pix_reg : std_logic_vector(255 downto 0);
signal static_reg : std_logic_vector(15 downto 0);
signal pulser_reg : std_logic_vector(15 downto 0);
signal latency : unsigned(8 downto 0);
signal dac_setting : std_logic_vector(15 downto 0);
signal trig_multiplier : unsigned(3 downto 0);
signal delay_setting : std_logic_vector(7 downto 0);
-- config serialiser
signal conf_load : std_logic_vector(7 downto 0);
signal conf_sreg_cnt : unsigned(7 downto 0);
signal conf_sreg : std_logic_vector(144 downto 0);
signal pix_sreg_cnt : unsigned(8 downto 0);
signal pix_sreg : std_logic_vector(255 downto 0);
signal en_pix_reg : std_logic;
-- inject & trigger
signal dig_inj : std_logic;
signal trigger : std_logic;
signal pulser_trig_t : std_logic_vector(40 downto 0);
signal inject_cnt : unsigned(8 downto 0);
signal trig_cnt : unsigned(4 downto 0);
signal en_inj : std_logic;
signal inj_sw_t : std_logic;
-- DAC
signal dac_load : std_logic_vector(15 downto 0);
signal dac_cs_t : std_logic;
signal dac_sreg_cnt : unsigned(7 downto 0);
signal dac_sreg : std_logic_vector(15 downto 0);
signal dac_sclk_t : std_logic;
component delay_line
generic (
width : positive := 8);
port (
clk : in std_logic;
rst : in std_logic;
input : IN std_logic;
output : OUT std_logic;
setting : IN std_logic_vector(width-1 downto 0) );
end component delay_line;
begin
sys_rst <= not rst_n;
clk_40 <= clk_i;
clk_bx_t <= clk_40;
clk_cnfg_t <= clk_40;
clk_data_t <= clk_rx_i;
-- Outputs
trig_o <= trigger;
en_pix_sr_cnfg_o <= en_pix_reg;
ld_cnfg_o <= conf_load(4) or conf_load(5) or conf_load(6) or conf_load(7) or dig_inj;
si_cnfg_o <= conf_sreg(144) or pix_sreg(255);
dac_sclk_o <= dac_sclk_t;
dac_sdi_o <= dac_sreg(15);
dac_ld_o <= not (dac_load(15) or dac_load(14) or dac_load(13) or dac_load(12) or dac_load(11) or
dac_load(10) or dac_load(9) or dac_load(8) or dac_load(7) or dac_load(6) or dac_load(5));
dac_cs_o <= dac_cs_t;
inj_sw_t <= '0' when (unsigned(pulser_trig_t) = 0) else '1';
-- Fine delay for pulser
cmp_inj_delay: delay_line
GENERIC MAP(
width => 7)
PORT MAP(
clk => clk_40,
rst => sys_rst,
input => inj_sw_t,
output => inj_sw_o,
setting => delay_setting(6 downto 0)
);
-- Static settings
en_data_clk <= static_reg(0);
en_bx_clk <= static_reg(1);
pix_d_cnfg_o <= static_reg(2);
en_inj <= static_reg(3);
rst_0_o <= not static_reg(4);
rst_1_o <= not static_reg(5);
yarr_cmd <= serial_in;
cmd_deserialiser: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
cmd_sreg <= (others => '0');
cmd_count <= (others => '0');
cmd_valid <= '0';
elsif rising_edge(clk_40) then
cmd_sreg <= cmd_sreg(30 downto 0) & yarr_cmd;
if (cmd_count = TO_UNSIGNED(31,8)) then
cmd_count <= (others => '0');
cmd_valid <= '1';
elsif (cmd_count > 0) then
cmd_count <= cmd_count + 1;
cmd_valid <= '0';
elsif (yarr_cmd = '1' and cmd_count = TO_UNSIGNED(0,8)) then -- start bit
cmd_count <= cmd_count + 1;
cmd_valid <= '0';
else
cmd_valid <= '0';
end if;
end if;
end process cmd_deserialiser;
cmd_decoder: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
new_cmd <= '0';
adr <= (others => '0');
payload <= (others => '0');
conf_reg <= (others => '0');
pix_reg <= (others => '0');
static_reg <= (others => '0');
pulser_reg <= (others => '0');
latency <= (others => '0');
dac_setting <= (others => '0');
trig_multiplier <= x"5";
delay_setting <= (others => '0');
elsif rising_edge(clk_40) then
new_cmd <= '0';
if (cmd_valid = '1') then
adr <= '0' & cmd_sreg(30 downto 16);
payload <= cmd_sreg(15 downto 0);
new_cmd <= '1';
end if;
-- pulses 1 clk cycle
pulser_reg <= (others => '0');
-- [0] : start shift conf reg
-- [1] : inject & trigger
-- [2] : start shift pixel reg
-- [3] : pulse load line
-- [4] : shift SR by one
-- [5] : load DAC
-- [6] : switch pulser
-- [7] : trigger (no inject)
if (new_cmd = '1') then
case (adr) is
-- Global Shift reg (145 bit)
when x"0000" => conf_reg(0) <= payload(0);
when x"0001" => conf_reg(1) <= payload(0);
when x"0002" => conf_reg(2) <= payload(0);
when x"0003" => conf_reg(6 downto 3) <= payload(3 downto 0);
when x"0004" => conf_reg(8 downto 7) <= payload(1 downto 0);
when x"0005" => conf_reg(9) <= payload(0);
when x"0006" => conf_reg(10) <= payload(0);
when x"0007" => conf_reg(11) <= payload(0);
when x"0008" => conf_reg(20 downto 12) <= payload(8 downto 0);
when x"0009" => conf_reg(36 downto 21) <= payload(15 downto 0);
when x"000a" => conf_reg(52 downto 37) <= payload(15 downto 0);
when x"000b" => conf_reg(56 downto 53) <= payload(3 downto 0);
when x"000c" => conf_reg(64 downto 57) <= payload(7 downto 0);
when x"000d" => conf_reg(72 downto 65) <= payload(7 downto 0);
when x"000e" => conf_reg(80 downto 73) <= payload(7 downto 0);
when x"000f" => conf_reg(88 downto 81) <= payload(7 downto 0);
when x"0010" => conf_reg(96 downto 89) <= payload(7 downto 0);
when x"0011" => conf_reg(104 downto 97) <= payload(7 downto 0);
when x"0012" => conf_reg(112 downto 105) <= payload(7 downto 0);
when x"0013" => conf_reg(120 downto 113) <= payload(7 downto 0);
when x"0014" => conf_reg(128 downto 121) <= payload(7 downto 0);
when x"0015" => conf_reg(136 downto 129) <= payload(7 downto 0);
when x"0016" => conf_reg(144 downto 137) <= payload(7 downto 0);
-- Pixel Shift reg (256 bit)
when x"0020" => pix_reg(15 downto 0) <= payload(15 downto 0);
when x"0021" => pix_reg(31 downto 16) <= payload(15 downto 0);
when x"0022" => pix_reg(47 downto 32) <= payload(15 downto 0);
when x"0023" => pix_reg(63 downto 48) <= payload(15 downto 0);
when x"0024" => pix_reg(79 downto 64) <= payload(15 downto 0);
when x"0025" => pix_reg(95 downto 80) <= payload(15 downto 0);
when x"0026" => pix_reg(111 downto 96) <= payload(15 downto 0);
when x"0027" => pix_reg(127 downto 112) <= payload(15 downto 0);
when x"0028" => pix_reg(143 downto 128) <= payload(15 downto 0);
when x"0029" => pix_reg(159 downto 144) <= payload(15 downto 0);
when x"002a" => pix_reg(175 downto 160) <= payload(15 downto 0);
when x"002b" => pix_reg(191 downto 176) <= payload(15 downto 0);
when x"002c" => pix_reg(207 downto 192) <= payload(15 downto 0);
when x"002d" => pix_reg(223 downto 208) <= payload(15 downto 0);
when x"002e" => pix_reg(239 downto 224) <= payload(15 downto 0);
when x"002f" => pix_reg(255 downto 240) <= payload(15 downto 0);
-- Modes
when x"0030" => static_reg <= payload;
when x"0031" => pulser_reg <= payload;
when x"0032" => latency <= unsigned(payload(8 downto 0));
when x"0033" => dac_setting <= payload(15 downto 0);
when x"0034" => trig_multiplier <= unsigned(payload(3 downto 0));
when x"0035" => delay_setting <= payload(7 downto 0);
when others =>
end case;
end if;
end if;
end process cmd_decoder;
conf_serialiser: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
conf_sreg_cnt <= (others => '0');
conf_sreg <= (others => '0');
en_conf_clk <= '0';
conf_load <= (others => '0');
pix_sreg_cnt <= (others => '0');
pix_sreg <= (others => '0');
en_pix_reg <= '0';
elsif rising_edge(clk_40) then
-- Configuration serialiser
conf_load(0) <= '0';
if (pulser_reg(0) = '1') then
conf_sreg_cnt <= TO_UNSIGNED(145, 8);
conf_sreg <= conf_reg(144 downto 0);
en_conf_clk <= '1';
elsif (conf_sreg_cnt = TO_UNSIGNED(1, 8)) then
conf_sreg <= conf_sreg(143 downto 0) & '0';
conf_load(0) <= '1';
en_conf_clk <= '0';
conf_sreg_cnt <= conf_sreg_cnt - 1;
elsif (conf_sreg_cnt > 0) then
conf_sreg <= conf_sreg(143 downto 0) & '0';
conf_sreg_cnt <= conf_sreg_cnt - 1;
en_conf_clk <= '1';
end if;
-- Pulse load line
if (pulser_reg(3) = '1') then
conf_load(0) <= '1';
end if;
-- Pixel sreg serialiser
en_pix_reg <= '0';
if (pulser_reg(2) = '1') then
pix_sreg_cnt <= TO_UNSIGNED(256, 9);
pix_sreg <= pix_reg(255 downto 0);
en_conf_clk <= '1';
en_pix_reg <= '1';
elsif (pix_sreg_cnt = TO_UNSIGNED(1, 9)) then
pix_sreg <= pix_sreg(254 downto 0) & '0';
--conf_load <= '1';
en_pix_reg <= '0';
en_conf_clk <= '0';
pix_sreg_cnt <= pix_sreg_cnt - 1;
elsif (pix_sreg_cnt > 0) then
pix_sreg <= pix_sreg(254 downto 0) & '0';
pix_sreg_cnt <= pix_sreg_cnt - 1;
en_conf_clk <= '1';
en_pix_reg <= '1';
end if;
conf_load(1) <= conf_load(0);
conf_load(2) <= conf_load(1);
conf_load(3) <= conf_load(2);
conf_load(4) <= conf_load(3);
conf_load(5) <= conf_load(4);
conf_load(6) <= conf_load(5);
conf_load(7) <= conf_load(6);
end if;
end process conf_serialiser;
inject_proc: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
dig_inj <= '0';
trigger <= '0';
pulser_trig_t(0) <= '0';
inject_cnt <= (others => '0');
trig_cnt <= (others => '0');
elsif rising_edge(clk_40) then
dig_inj <= '0';
trigger <= '0';
pulser_trig_t(0) <= '0';
if (pulser_reg(1) = '1') then
inject_cnt <= TO_UNSIGNED((TO_INTEGER(latency) + 2), 9); -- Latency vonfig
if (en_inj = '0') then
dig_inj <= '1';
else
pulser_trig_t(0) <= '1';
end if;
elsif (inject_cnt > ((TO_INTEGER(latency) - 6))) then -- TODO change to pulse length
if (en_inj = '0') then
dig_inj <= '1';
end if;
inject_cnt <= inject_cnt - 1;
elsif ((inject_cnt <= (TO_INTEGER(trig_multiplier))) and inject_cnt > 1) then -- TODO change to trigger multiplier
inject_cnt <= inject_cnt - 1;
dig_inj <= '0';
trigger <= '1';
elsif (inject_cnt = 1) then
inject_cnt <= inject_cnt - 1;
dig_inj <= '0';
trigger <= '1';
elsif (inject_cnt > 0) then
inject_cnt <= inject_cnt - 1;
dig_inj <= '0';
end if;
if (pulser_reg(7) = '1') then
trig_cnt <= TO_UNSIGNED((TO_INTEGER(trig_multiplier) + 1), 5);
elsif (trig_cnt > 0) then
trig_cnt <= trig_cnt - 1;
trigger <= '1';
end if;
end if;
end process inject_proc;
pulse_delay: for I in 1 to pulser_trig_t'length-1 generate
begin
delay_proc: process(clk_40)
begin
if (sys_rst = '1') then
pulser_trig_t(I) <= '0';
elsif rising_edge(clk_40) then
pulser_trig_t(I) <= pulser_trig_t(I-1);
end if;
end process delay_proc;
end generate;
dac_proc: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
dac_load <= (others => '0');
dac_cs_t <= '1';
dac_sreg_cnt <= (others => '0');
dac_sreg <= (others => '0');
dac_sclk_t <= '0';
elsif rising_edge(clk_40) then
dac_load(0) <= '0';
dac_cs_t <= '1';
if (pulser_reg(5) = '1') then
dac_sreg_cnt <= TO_UNSIGNED(160, 8);
dac_sreg <= dac_setting(15 downto 0);
dac_sclk_t <= '0';
dac_cs_t <= '0';
elsif (dac_sreg_cnt = TO_UNSIGNED(1, 8)) then
dac_sreg <= dac_sreg(14 downto 0) & '0';
dac_load(0) <= '1';
dac_sreg_cnt <= dac_sreg_cnt - 1;
dac_sclk_t <= '0';
dac_cs_t <= '0';
elsif (dac_sreg_cnt > 0) then
if ((dac_sreg_cnt mod 10) = 1) then
dac_sreg <= dac_sreg(14 downto 0) & '0';
end if;
if ((dac_sreg_cnt mod 5) = 1) then
dac_sclk_t <= not dac_sclk_t;
end if;
dac_sreg_cnt <= dac_sreg_cnt - 1;
dac_cs_t <= '0';
end if;
dac_load(1) <= dac_load(0);
dac_load(2) <= dac_load(1);
dac_load(3) <= dac_load(2);
dac_load(4) <= dac_load(3);
dac_load(5) <= dac_load(4);
dac_load(6) <= dac_load(5);
dac_load(7) <= dac_load(6);
dac_load(8) <= dac_load(7);
dac_load(9) <= dac_load(8);
dac_load(10) <= dac_load(9);
dac_load(11) <= dac_load(10);
dac_load(12) <= dac_load(11);
dac_load(13) <= dac_load(12);
dac_load(14) <= dac_load(13);
dac_load(15) <= dac_load(14);
end if;
end process dac_proc;
-- clock ddr2 buffers
conf_clk_buf : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_cnfg_o, -- 1-bit output data
C0 => clk_cnfg_t, -- 1-bit clock input
C1 => not clk_cnfg_t, -- 1-bit clock input
CE => en_conf_clk, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => sys_rst, -- 1-bit reset input
S => open -- 1-bit set input
);
bx_clk_buf : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_bx_o, -- 1-bit output data
C0 => clk_bx_t, -- 1-bit clock input
C1 => not clk_bx_t, -- 1-bit clock input
CE => en_bx_clk, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => sys_rst, -- 1-bit reset input
S => open -- 1-bit set input
);
data_clk_buf : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_data_o, -- 1-bit output data
C0 => clk_data_T, -- 1-bit clock input
C1 => not clk_data_t, -- 1-bit clock input
CE => en_data_clk, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => sys_rst, -- 1-bit reset input
S => open -- 1-bit set input
);
end behavioral;
|
--------------------------------------------
-- Project: FE65-P2 addon
-- Author: Timon Heim (timon.heim@cern.ch)
-- Description: Attaches to serial port and controls FE65-P2 adapter
-- Dependencies: -
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity fe65p2_addon is
port (
clk_i : IN std_logic;
rst_n : IN std_logic;
serial_in : IN std_logic;
clk_rx_i : IN std_logic;
-- TO FMC
clk_bx_o : out std_logic;
trig_o : out std_logic;
clk_cnfg_o : out std_logic;
en_pix_sr_cnfg_o : out std_logic;
ld_cnfg_o : out std_logic;
si_cnfg_o : out std_logic;
pix_d_cnfg_o : out std_logic;
clk_data_o : out std_logic;
rst_0_o : out std_logic;
rst_1_o : out std_logic;
dac_sclk_o : out std_logic;
dac_sdi_o : out std_logic;
dac_ld_o : out std_logic;
dac_cs_o : out std_logic;
inj_sw_o : out std_logic
);
end fe65p2_addon;
architecture behavioral of fe65p2_addon is
-- System signals
signal sys_rst : std_logic;
signal clk_40 : std_logic;
-- clocks
signal clk_bx_t : std_logic;
signal clk_cnfg_t : std_logic;
signal clk_data_t : std_logic;
signal en_bx_clk : std_logic;
signal en_conf_clk : std_logic;
signal en_data_clk : std_logic;
-- cmd deserialiser
signal yarr_cmd : std_logic;
signal cmd_count : unsigned(7 downto 0);
signal cmd_valid : std_logic;
signal cmd_sreg : std_logic_vector(31 downto 0);
-- cmd decoder
signal new_cmd : std_logic;
signal adr : std_logic_vector(15 downto 0);
signal payload : std_logic_vector(15 downto 0);
-- registers
signal conf_reg : std_logic_vector(159 downto 0);
signal pix_reg : std_logic_vector(255 downto 0);
signal static_reg : std_logic_vector(15 downto 0);
signal pulser_reg : std_logic_vector(15 downto 0);
signal latency : unsigned(8 downto 0);
signal dac_setting : std_logic_vector(15 downto 0);
signal trig_multiplier : unsigned(3 downto 0);
signal delay_setting : std_logic_vector(7 downto 0);
-- config serialiser
signal conf_load : std_logic_vector(7 downto 0);
signal conf_sreg_cnt : unsigned(7 downto 0);
signal conf_sreg : std_logic_vector(144 downto 0);
signal pix_sreg_cnt : unsigned(8 downto 0);
signal pix_sreg : std_logic_vector(255 downto 0);
signal en_pix_reg : std_logic;
-- inject & trigger
signal dig_inj : std_logic;
signal trigger : std_logic;
signal pulser_trig_t : std_logic_vector(40 downto 0);
signal inject_cnt : unsigned(8 downto 0);
signal trig_cnt : unsigned(4 downto 0);
signal en_inj : std_logic;
signal inj_sw_t : std_logic;
-- DAC
signal dac_load : std_logic_vector(15 downto 0);
signal dac_cs_t : std_logic;
signal dac_sreg_cnt : unsigned(7 downto 0);
signal dac_sreg : std_logic_vector(15 downto 0);
signal dac_sclk_t : std_logic;
component delay_line
generic (
width : positive := 8);
port (
clk : in std_logic;
rst : in std_logic;
input : IN std_logic;
output : OUT std_logic;
setting : IN std_logic_vector(width-1 downto 0) );
end component delay_line;
begin
sys_rst <= not rst_n;
clk_40 <= clk_i;
clk_bx_t <= clk_40;
clk_cnfg_t <= clk_40;
clk_data_t <= clk_rx_i;
-- Outputs
trig_o <= trigger;
en_pix_sr_cnfg_o <= en_pix_reg;
ld_cnfg_o <= conf_load(4) or conf_load(5) or conf_load(6) or conf_load(7) or dig_inj;
si_cnfg_o <= conf_sreg(144) or pix_sreg(255);
dac_sclk_o <= dac_sclk_t;
dac_sdi_o <= dac_sreg(15);
dac_ld_o <= not (dac_load(15) or dac_load(14) or dac_load(13) or dac_load(12) or dac_load(11) or
dac_load(10) or dac_load(9) or dac_load(8) or dac_load(7) or dac_load(6) or dac_load(5));
dac_cs_o <= dac_cs_t;
inj_sw_t <= '0' when (unsigned(pulser_trig_t) = 0) else '1';
-- Fine delay for pulser
cmp_inj_delay: delay_line
GENERIC MAP(
width => 7)
PORT MAP(
clk => clk_40,
rst => sys_rst,
input => inj_sw_t,
output => inj_sw_o,
setting => delay_setting(6 downto 0)
);
-- Static settings
en_data_clk <= static_reg(0);
en_bx_clk <= static_reg(1);
pix_d_cnfg_o <= static_reg(2);
en_inj <= static_reg(3);
rst_0_o <= not static_reg(4);
rst_1_o <= not static_reg(5);
yarr_cmd <= serial_in;
cmd_deserialiser: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
cmd_sreg <= (others => '0');
cmd_count <= (others => '0');
cmd_valid <= '0';
elsif rising_edge(clk_40) then
cmd_sreg <= cmd_sreg(30 downto 0) & yarr_cmd;
if (cmd_count = TO_UNSIGNED(31,8)) then
cmd_count <= (others => '0');
cmd_valid <= '1';
elsif (cmd_count > 0) then
cmd_count <= cmd_count + 1;
cmd_valid <= '0';
elsif (yarr_cmd = '1' and cmd_count = TO_UNSIGNED(0,8)) then -- start bit
cmd_count <= cmd_count + 1;
cmd_valid <= '0';
else
cmd_valid <= '0';
end if;
end if;
end process cmd_deserialiser;
cmd_decoder: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
new_cmd <= '0';
adr <= (others => '0');
payload <= (others => '0');
conf_reg <= (others => '0');
pix_reg <= (others => '0');
static_reg <= (others => '0');
pulser_reg <= (others => '0');
latency <= (others => '0');
dac_setting <= (others => '0');
trig_multiplier <= x"5";
delay_setting <= (others => '0');
elsif rising_edge(clk_40) then
new_cmd <= '0';
if (cmd_valid = '1') then
adr <= '0' & cmd_sreg(30 downto 16);
payload <= cmd_sreg(15 downto 0);
new_cmd <= '1';
end if;
-- pulses 1 clk cycle
pulser_reg <= (others => '0');
-- [0] : start shift conf reg
-- [1] : inject & trigger
-- [2] : start shift pixel reg
-- [3] : pulse load line
-- [4] : shift SR by one
-- [5] : load DAC
-- [6] : switch pulser
-- [7] : trigger (no inject)
if (new_cmd = '1') then
case (adr) is
-- Global Shift reg (145 bit)
when x"0000" => conf_reg(0) <= payload(0);
when x"0001" => conf_reg(1) <= payload(0);
when x"0002" => conf_reg(2) <= payload(0);
when x"0003" => conf_reg(6 downto 3) <= payload(3 downto 0);
when x"0004" => conf_reg(8 downto 7) <= payload(1 downto 0);
when x"0005" => conf_reg(9) <= payload(0);
when x"0006" => conf_reg(10) <= payload(0);
when x"0007" => conf_reg(11) <= payload(0);
when x"0008" => conf_reg(20 downto 12) <= payload(8 downto 0);
when x"0009" => conf_reg(36 downto 21) <= payload(15 downto 0);
when x"000a" => conf_reg(52 downto 37) <= payload(15 downto 0);
when x"000b" => conf_reg(56 downto 53) <= payload(3 downto 0);
when x"000c" => conf_reg(64 downto 57) <= payload(7 downto 0);
when x"000d" => conf_reg(72 downto 65) <= payload(7 downto 0);
when x"000e" => conf_reg(80 downto 73) <= payload(7 downto 0);
when x"000f" => conf_reg(88 downto 81) <= payload(7 downto 0);
when x"0010" => conf_reg(96 downto 89) <= payload(7 downto 0);
when x"0011" => conf_reg(104 downto 97) <= payload(7 downto 0);
when x"0012" => conf_reg(112 downto 105) <= payload(7 downto 0);
when x"0013" => conf_reg(120 downto 113) <= payload(7 downto 0);
when x"0014" => conf_reg(128 downto 121) <= payload(7 downto 0);
when x"0015" => conf_reg(136 downto 129) <= payload(7 downto 0);
when x"0016" => conf_reg(144 downto 137) <= payload(7 downto 0);
-- Pixel Shift reg (256 bit)
when x"0020" => pix_reg(15 downto 0) <= payload(15 downto 0);
when x"0021" => pix_reg(31 downto 16) <= payload(15 downto 0);
when x"0022" => pix_reg(47 downto 32) <= payload(15 downto 0);
when x"0023" => pix_reg(63 downto 48) <= payload(15 downto 0);
when x"0024" => pix_reg(79 downto 64) <= payload(15 downto 0);
when x"0025" => pix_reg(95 downto 80) <= payload(15 downto 0);
when x"0026" => pix_reg(111 downto 96) <= payload(15 downto 0);
when x"0027" => pix_reg(127 downto 112) <= payload(15 downto 0);
when x"0028" => pix_reg(143 downto 128) <= payload(15 downto 0);
when x"0029" => pix_reg(159 downto 144) <= payload(15 downto 0);
when x"002a" => pix_reg(175 downto 160) <= payload(15 downto 0);
when x"002b" => pix_reg(191 downto 176) <= payload(15 downto 0);
when x"002c" => pix_reg(207 downto 192) <= payload(15 downto 0);
when x"002d" => pix_reg(223 downto 208) <= payload(15 downto 0);
when x"002e" => pix_reg(239 downto 224) <= payload(15 downto 0);
when x"002f" => pix_reg(255 downto 240) <= payload(15 downto 0);
-- Modes
when x"0030" => static_reg <= payload;
when x"0031" => pulser_reg <= payload;
when x"0032" => latency <= unsigned(payload(8 downto 0));
when x"0033" => dac_setting <= payload(15 downto 0);
when x"0034" => trig_multiplier <= unsigned(payload(3 downto 0));
when x"0035" => delay_setting <= payload(7 downto 0);
when others =>
end case;
end if;
end if;
end process cmd_decoder;
conf_serialiser: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
conf_sreg_cnt <= (others => '0');
conf_sreg <= (others => '0');
en_conf_clk <= '0';
conf_load <= (others => '0');
pix_sreg_cnt <= (others => '0');
pix_sreg <= (others => '0');
en_pix_reg <= '0';
elsif rising_edge(clk_40) then
-- Configuration serialiser
conf_load(0) <= '0';
if (pulser_reg(0) = '1') then
conf_sreg_cnt <= TO_UNSIGNED(145, 8);
conf_sreg <= conf_reg(144 downto 0);
en_conf_clk <= '1';
elsif (conf_sreg_cnt = TO_UNSIGNED(1, 8)) then
conf_sreg <= conf_sreg(143 downto 0) & '0';
conf_load(0) <= '1';
en_conf_clk <= '0';
conf_sreg_cnt <= conf_sreg_cnt - 1;
elsif (conf_sreg_cnt > 0) then
conf_sreg <= conf_sreg(143 downto 0) & '0';
conf_sreg_cnt <= conf_sreg_cnt - 1;
en_conf_clk <= '1';
end if;
-- Pulse load line
if (pulser_reg(3) = '1') then
conf_load(0) <= '1';
end if;
-- Pixel sreg serialiser
en_pix_reg <= '0';
if (pulser_reg(2) = '1') then
pix_sreg_cnt <= TO_UNSIGNED(256, 9);
pix_sreg <= pix_reg(255 downto 0);
en_conf_clk <= '1';
en_pix_reg <= '1';
elsif (pix_sreg_cnt = TO_UNSIGNED(1, 9)) then
pix_sreg <= pix_sreg(254 downto 0) & '0';
--conf_load <= '1';
en_pix_reg <= '0';
en_conf_clk <= '0';
pix_sreg_cnt <= pix_sreg_cnt - 1;
elsif (pix_sreg_cnt > 0) then
pix_sreg <= pix_sreg(254 downto 0) & '0';
pix_sreg_cnt <= pix_sreg_cnt - 1;
en_conf_clk <= '1';
en_pix_reg <= '1';
end if;
conf_load(1) <= conf_load(0);
conf_load(2) <= conf_load(1);
conf_load(3) <= conf_load(2);
conf_load(4) <= conf_load(3);
conf_load(5) <= conf_load(4);
conf_load(6) <= conf_load(5);
conf_load(7) <= conf_load(6);
end if;
end process conf_serialiser;
inject_proc: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
dig_inj <= '0';
trigger <= '0';
pulser_trig_t(0) <= '0';
inject_cnt <= (others => '0');
trig_cnt <= (others => '0');
elsif rising_edge(clk_40) then
dig_inj <= '0';
trigger <= '0';
pulser_trig_t(0) <= '0';
if (pulser_reg(1) = '1') then
inject_cnt <= TO_UNSIGNED((TO_INTEGER(latency) + 2), 9); -- Latency vonfig
if (en_inj = '0') then
dig_inj <= '1';
else
pulser_trig_t(0) <= '1';
end if;
elsif (inject_cnt > ((TO_INTEGER(latency) - 6))) then -- TODO change to pulse length
if (en_inj = '0') then
dig_inj <= '1';
end if;
inject_cnt <= inject_cnt - 1;
elsif ((inject_cnt <= (TO_INTEGER(trig_multiplier))) and inject_cnt > 1) then -- TODO change to trigger multiplier
inject_cnt <= inject_cnt - 1;
dig_inj <= '0';
trigger <= '1';
elsif (inject_cnt = 1) then
inject_cnt <= inject_cnt - 1;
dig_inj <= '0';
trigger <= '1';
elsif (inject_cnt > 0) then
inject_cnt <= inject_cnt - 1;
dig_inj <= '0';
end if;
if (pulser_reg(7) = '1') then
trig_cnt <= TO_UNSIGNED((TO_INTEGER(trig_multiplier) + 1), 5);
elsif (trig_cnt > 0) then
trig_cnt <= trig_cnt - 1;
trigger <= '1';
end if;
end if;
end process inject_proc;
pulse_delay: for I in 1 to pulser_trig_t'length-1 generate
begin
delay_proc: process(clk_40)
begin
if (sys_rst = '1') then
pulser_trig_t(I) <= '0';
elsif rising_edge(clk_40) then
pulser_trig_t(I) <= pulser_trig_t(I-1);
end if;
end process delay_proc;
end generate;
dac_proc: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
dac_load <= (others => '0');
dac_cs_t <= '1';
dac_sreg_cnt <= (others => '0');
dac_sreg <= (others => '0');
dac_sclk_t <= '0';
elsif rising_edge(clk_40) then
dac_load(0) <= '0';
dac_cs_t <= '1';
if (pulser_reg(5) = '1') then
dac_sreg_cnt <= TO_UNSIGNED(160, 8);
dac_sreg <= dac_setting(15 downto 0);
dac_sclk_t <= '0';
dac_cs_t <= '0';
elsif (dac_sreg_cnt = TO_UNSIGNED(1, 8)) then
dac_sreg <= dac_sreg(14 downto 0) & '0';
dac_load(0) <= '1';
dac_sreg_cnt <= dac_sreg_cnt - 1;
dac_sclk_t <= '0';
dac_cs_t <= '0';
elsif (dac_sreg_cnt > 0) then
if ((dac_sreg_cnt mod 10) = 1) then
dac_sreg <= dac_sreg(14 downto 0) & '0';
end if;
if ((dac_sreg_cnt mod 5) = 1) then
dac_sclk_t <= not dac_sclk_t;
end if;
dac_sreg_cnt <= dac_sreg_cnt - 1;
dac_cs_t <= '0';
end if;
dac_load(1) <= dac_load(0);
dac_load(2) <= dac_load(1);
dac_load(3) <= dac_load(2);
dac_load(4) <= dac_load(3);
dac_load(5) <= dac_load(4);
dac_load(6) <= dac_load(5);
dac_load(7) <= dac_load(6);
dac_load(8) <= dac_load(7);
dac_load(9) <= dac_load(8);
dac_load(10) <= dac_load(9);
dac_load(11) <= dac_load(10);
dac_load(12) <= dac_load(11);
dac_load(13) <= dac_load(12);
dac_load(14) <= dac_load(13);
dac_load(15) <= dac_load(14);
end if;
end process dac_proc;
-- clock ddr2 buffers
conf_clk_buf : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_cnfg_o, -- 1-bit output data
C0 => clk_cnfg_t, -- 1-bit clock input
C1 => not clk_cnfg_t, -- 1-bit clock input
CE => en_conf_clk, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => sys_rst, -- 1-bit reset input
S => open -- 1-bit set input
);
bx_clk_buf : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_bx_o, -- 1-bit output data
C0 => clk_bx_t, -- 1-bit clock input
C1 => not clk_bx_t, -- 1-bit clock input
CE => en_bx_clk, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => sys_rst, -- 1-bit reset input
S => open -- 1-bit set input
);
data_clk_buf : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_data_o, -- 1-bit output data
C0 => clk_data_T, -- 1-bit clock input
C1 => not clk_data_t, -- 1-bit clock input
CE => en_data_clk, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => sys_rst, -- 1-bit reset input
S => open -- 1-bit set input
);
end behavioral;
|
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
--the order of events:
-- e.g. sw event = 1 and hw event = 2
-- event = (HW1 & HW0 & SW0)
-- pcp only sets SW0, but can read SW0
-- ap ack all events
entity pdiEvent is
generic (
genOnePdiClkDomain_g : boolean := false;
iSwEvent_g : integer := 1;
iHwEvent_g : integer := 2
);
port (
--port A -> PCP
clkA : in std_logic;
rstA : in std_logic;
eventSetA : in std_logic_vector(iSwEvent_g-1 downto 0); --to set event (pulse!)
eventReadA : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set (can be acked by ap!!!)
--port B -> AP
clkB : in std_logic;
rstB : in std_logic;
eventAckB : in std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to ack events (pulse!)
eventReadB : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set
--hw event set pulse (must be synchronous to clkB!)
hwEventSetPulseB : in std_logic_vector(iHwEvent_g-1 downto 0)
);
end entity pdiEvent;
architecture rtl of pdiEvent is
--in clk domain A
signal eventA_s, --stores the events in A domain
eventA_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventA_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
signal hwEventA_setPulse --sets the hw event only
: std_logic_vector(iHwEvent_g-1 downto 0);
--in clk domain B
signal eventB_s, --stores the events in B domain
eventB_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventB_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
begin
--pcp
eventReadA <= eventA_s;
--eventA_s stores all events
--eventA_ackPulse sends acks for all events
--eventA_setPulse sends set for sw event only
eventA_setPulse <= eventSetA;
--hwEventA_setPulse sends set for hw event only
process(clkA, rstA)
variable event_var : std_logic_vector(eventA_s'range);
begin
if rstA = '1' then
eventA_s <= (others => '0');
elsif clkA = '1' and clkA'event then
--get event state to do magic
event_var := eventA_s;
--first let the ack does its work...
event_var := event_var and not eventA_ackPulse;
--second the sw events may overwrite the ack...
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventA_setPulse(iSwEvent_g-1 downto 0);
--last but not least, the hw events have its chance too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventA_setPulse(iHwEvent_g-1 downto 0);
--and now, export it
eventA_s <= event_var;
end if;
end process;
--ap
eventReadB <= eventB_s;
--eventB_s stores all events
--eventB_ackPulse sends acks for all events
eventB_ackPulse <= eventAckB;
--eventB_setPulse sends set for sw event only
--hwEventSetPulseB sends set for hw event only
process(clkB, rstB)
variable event_var : std_logic_vector(eventB_s'range);
begin
if rstB = '1' then
eventB_s <= (others => '0');
elsif clkB = '1' and clkB'event then
--I know, its almost the same as for A, but for clarity...
--get event state
event_var := eventB_s;
--doing ack
event_var := event_var and not eventB_ackPulse;
--sw events may overwrite
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventB_setPulse(iSwEvent_g-1 downto 0);
--hw events may overwrite too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventSetPulseB(iHwEvent_g-1 downto 0);
--and let's export
eventB_s <= event_var;
end if;
end process;
--xing the domains a to b
syncEventSetGen : for i in 0 to iSwEvent_g-1 generate
--only the software events are transferred!
syncEventSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkA,
rstSrc => rstA,
dataSrc => eventA_setPulse(i),
clkDst => clkB,
rstDst => rstB,
dataDst => eventB_setPulse(i)
);
end generate;
--xing the domains b to a
syncEventAckGen : for i in eventB_s'range generate
--all events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => eventB_ackPulse(i),
clkDst => clkA,
rstDst => rstA,
dataDst => eventA_ackPulse(i)
);
end generate;
syncHwEventGen : for i in 0 to iHwEvent_g-1 generate
--hw events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => hwEventSetPulseB(i),
clkDst => clkA,
rstDst => rstA,
dataDst => hwEventA_setPulse(i)
);
end generate;
end architecture rtl; |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
--the order of events:
-- e.g. sw event = 1 and hw event = 2
-- event = (HW1 & HW0 & SW0)
-- pcp only sets SW0, but can read SW0
-- ap ack all events
entity pdiEvent is
generic (
genOnePdiClkDomain_g : boolean := false;
iSwEvent_g : integer := 1;
iHwEvent_g : integer := 2
);
port (
--port A -> PCP
clkA : in std_logic;
rstA : in std_logic;
eventSetA : in std_logic_vector(iSwEvent_g-1 downto 0); --to set event (pulse!)
eventReadA : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set (can be acked by ap!!!)
--port B -> AP
clkB : in std_logic;
rstB : in std_logic;
eventAckB : in std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to ack events (pulse!)
eventReadB : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set
--hw event set pulse (must be synchronous to clkB!)
hwEventSetPulseB : in std_logic_vector(iHwEvent_g-1 downto 0)
);
end entity pdiEvent;
architecture rtl of pdiEvent is
--in clk domain A
signal eventA_s, --stores the events in A domain
eventA_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventA_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
signal hwEventA_setPulse --sets the hw event only
: std_logic_vector(iHwEvent_g-1 downto 0);
--in clk domain B
signal eventB_s, --stores the events in B domain
eventB_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventB_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
begin
--pcp
eventReadA <= eventA_s;
--eventA_s stores all events
--eventA_ackPulse sends acks for all events
--eventA_setPulse sends set for sw event only
eventA_setPulse <= eventSetA;
--hwEventA_setPulse sends set for hw event only
process(clkA, rstA)
variable event_var : std_logic_vector(eventA_s'range);
begin
if rstA = '1' then
eventA_s <= (others => '0');
elsif clkA = '1' and clkA'event then
--get event state to do magic
event_var := eventA_s;
--first let the ack does its work...
event_var := event_var and not eventA_ackPulse;
--second the sw events may overwrite the ack...
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventA_setPulse(iSwEvent_g-1 downto 0);
--last but not least, the hw events have its chance too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventA_setPulse(iHwEvent_g-1 downto 0);
--and now, export it
eventA_s <= event_var;
end if;
end process;
--ap
eventReadB <= eventB_s;
--eventB_s stores all events
--eventB_ackPulse sends acks for all events
eventB_ackPulse <= eventAckB;
--eventB_setPulse sends set for sw event only
--hwEventSetPulseB sends set for hw event only
process(clkB, rstB)
variable event_var : std_logic_vector(eventB_s'range);
begin
if rstB = '1' then
eventB_s <= (others => '0');
elsif clkB = '1' and clkB'event then
--I know, its almost the same as for A, but for clarity...
--get event state
event_var := eventB_s;
--doing ack
event_var := event_var and not eventB_ackPulse;
--sw events may overwrite
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventB_setPulse(iSwEvent_g-1 downto 0);
--hw events may overwrite too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventSetPulseB(iHwEvent_g-1 downto 0);
--and let's export
eventB_s <= event_var;
end if;
end process;
--xing the domains a to b
syncEventSetGen : for i in 0 to iSwEvent_g-1 generate
--only the software events are transferred!
syncEventSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkA,
rstSrc => rstA,
dataSrc => eventA_setPulse(i),
clkDst => clkB,
rstDst => rstB,
dataDst => eventB_setPulse(i)
);
end generate;
--xing the domains b to a
syncEventAckGen : for i in eventB_s'range generate
--all events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => eventB_ackPulse(i),
clkDst => clkA,
rstDst => rstA,
dataDst => eventA_ackPulse(i)
);
end generate;
syncHwEventGen : for i in 0 to iHwEvent_g-1 generate
--hw events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => hwEventSetPulseB(i),
clkDst => clkA,
rstDst => rstA,
dataDst => hwEventA_setPulse(i)
);
end generate;
end architecture rtl; |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
--the order of events:
-- e.g. sw event = 1 and hw event = 2
-- event = (HW1 & HW0 & SW0)
-- pcp only sets SW0, but can read SW0
-- ap ack all events
entity pdiEvent is
generic (
genOnePdiClkDomain_g : boolean := false;
iSwEvent_g : integer := 1;
iHwEvent_g : integer := 2
);
port (
--port A -> PCP
clkA : in std_logic;
rstA : in std_logic;
eventSetA : in std_logic_vector(iSwEvent_g-1 downto 0); --to set event (pulse!)
eventReadA : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set (can be acked by ap!!!)
--port B -> AP
clkB : in std_logic;
rstB : in std_logic;
eventAckB : in std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to ack events (pulse!)
eventReadB : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set
--hw event set pulse (must be synchronous to clkB!)
hwEventSetPulseB : in std_logic_vector(iHwEvent_g-1 downto 0)
);
end entity pdiEvent;
architecture rtl of pdiEvent is
--in clk domain A
signal eventA_s, --stores the events in A domain
eventA_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventA_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
signal hwEventA_setPulse --sets the hw event only
: std_logic_vector(iHwEvent_g-1 downto 0);
--in clk domain B
signal eventB_s, --stores the events in B domain
eventB_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventB_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
begin
--pcp
eventReadA <= eventA_s;
--eventA_s stores all events
--eventA_ackPulse sends acks for all events
--eventA_setPulse sends set for sw event only
eventA_setPulse <= eventSetA;
--hwEventA_setPulse sends set for hw event only
process(clkA, rstA)
variable event_var : std_logic_vector(eventA_s'range);
begin
if rstA = '1' then
eventA_s <= (others => '0');
elsif clkA = '1' and clkA'event then
--get event state to do magic
event_var := eventA_s;
--first let the ack does its work...
event_var := event_var and not eventA_ackPulse;
--second the sw events may overwrite the ack...
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventA_setPulse(iSwEvent_g-1 downto 0);
--last but not least, the hw events have its chance too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventA_setPulse(iHwEvent_g-1 downto 0);
--and now, export it
eventA_s <= event_var;
end if;
end process;
--ap
eventReadB <= eventB_s;
--eventB_s stores all events
--eventB_ackPulse sends acks for all events
eventB_ackPulse <= eventAckB;
--eventB_setPulse sends set for sw event only
--hwEventSetPulseB sends set for hw event only
process(clkB, rstB)
variable event_var : std_logic_vector(eventB_s'range);
begin
if rstB = '1' then
eventB_s <= (others => '0');
elsif clkB = '1' and clkB'event then
--I know, its almost the same as for A, but for clarity...
--get event state
event_var := eventB_s;
--doing ack
event_var := event_var and not eventB_ackPulse;
--sw events may overwrite
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventB_setPulse(iSwEvent_g-1 downto 0);
--hw events may overwrite too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventSetPulseB(iHwEvent_g-1 downto 0);
--and let's export
eventB_s <= event_var;
end if;
end process;
--xing the domains a to b
syncEventSetGen : for i in 0 to iSwEvent_g-1 generate
--only the software events are transferred!
syncEventSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkA,
rstSrc => rstA,
dataSrc => eventA_setPulse(i),
clkDst => clkB,
rstDst => rstB,
dataDst => eventB_setPulse(i)
);
end generate;
--xing the domains b to a
syncEventAckGen : for i in eventB_s'range generate
--all events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => eventB_ackPulse(i),
clkDst => clkA,
rstDst => rstA,
dataDst => eventA_ackPulse(i)
);
end generate;
syncHwEventGen : for i in 0 to iHwEvent_g-1 generate
--hw events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => hwEventSetPulseB(i),
clkDst => clkA,
rstDst => rstA,
dataDst => hwEventA_setPulse(i)
);
end generate;
end architecture rtl; |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
--the order of events:
-- e.g. sw event = 1 and hw event = 2
-- event = (HW1 & HW0 & SW0)
-- pcp only sets SW0, but can read SW0
-- ap ack all events
entity pdiEvent is
generic (
genOnePdiClkDomain_g : boolean := false;
iSwEvent_g : integer := 1;
iHwEvent_g : integer := 2
);
port (
--port A -> PCP
clkA : in std_logic;
rstA : in std_logic;
eventSetA : in std_logic_vector(iSwEvent_g-1 downto 0); --to set event (pulse!)
eventReadA : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set (can be acked by ap!!!)
--port B -> AP
clkB : in std_logic;
rstB : in std_logic;
eventAckB : in std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to ack events (pulse!)
eventReadB : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set
--hw event set pulse (must be synchronous to clkB!)
hwEventSetPulseB : in std_logic_vector(iHwEvent_g-1 downto 0)
);
end entity pdiEvent;
architecture rtl of pdiEvent is
--in clk domain A
signal eventA_s, --stores the events in A domain
eventA_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventA_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
signal hwEventA_setPulse --sets the hw event only
: std_logic_vector(iHwEvent_g-1 downto 0);
--in clk domain B
signal eventB_s, --stores the events in B domain
eventB_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventB_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
begin
--pcp
eventReadA <= eventA_s;
--eventA_s stores all events
--eventA_ackPulse sends acks for all events
--eventA_setPulse sends set for sw event only
eventA_setPulse <= eventSetA;
--hwEventA_setPulse sends set for hw event only
process(clkA, rstA)
variable event_var : std_logic_vector(eventA_s'range);
begin
if rstA = '1' then
eventA_s <= (others => '0');
elsif clkA = '1' and clkA'event then
--get event state to do magic
event_var := eventA_s;
--first let the ack does its work...
event_var := event_var and not eventA_ackPulse;
--second the sw events may overwrite the ack...
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventA_setPulse(iSwEvent_g-1 downto 0);
--last but not least, the hw events have its chance too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventA_setPulse(iHwEvent_g-1 downto 0);
--and now, export it
eventA_s <= event_var;
end if;
end process;
--ap
eventReadB <= eventB_s;
--eventB_s stores all events
--eventB_ackPulse sends acks for all events
eventB_ackPulse <= eventAckB;
--eventB_setPulse sends set for sw event only
--hwEventSetPulseB sends set for hw event only
process(clkB, rstB)
variable event_var : std_logic_vector(eventB_s'range);
begin
if rstB = '1' then
eventB_s <= (others => '0');
elsif clkB = '1' and clkB'event then
--I know, its almost the same as for A, but for clarity...
--get event state
event_var := eventB_s;
--doing ack
event_var := event_var and not eventB_ackPulse;
--sw events may overwrite
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventB_setPulse(iSwEvent_g-1 downto 0);
--hw events may overwrite too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventSetPulseB(iHwEvent_g-1 downto 0);
--and let's export
eventB_s <= event_var;
end if;
end process;
--xing the domains a to b
syncEventSetGen : for i in 0 to iSwEvent_g-1 generate
--only the software events are transferred!
syncEventSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkA,
rstSrc => rstA,
dataSrc => eventA_setPulse(i),
clkDst => clkB,
rstDst => rstB,
dataDst => eventB_setPulse(i)
);
end generate;
--xing the domains b to a
syncEventAckGen : for i in eventB_s'range generate
--all events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => eventB_ackPulse(i),
clkDst => clkA,
rstDst => rstA,
dataDst => eventA_ackPulse(i)
);
end generate;
syncHwEventGen : for i in 0 to iHwEvent_g-1 generate
--hw events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => hwEventSetPulseB(i),
clkDst => clkA,
rstDst => rstA,
dataDst => hwEventA_setPulse(i)
);
end generate;
end architecture rtl; |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
--the order of events:
-- e.g. sw event = 1 and hw event = 2
-- event = (HW1 & HW0 & SW0)
-- pcp only sets SW0, but can read SW0
-- ap ack all events
entity pdiEvent is
generic (
genOnePdiClkDomain_g : boolean := false;
iSwEvent_g : integer := 1;
iHwEvent_g : integer := 2
);
port (
--port A -> PCP
clkA : in std_logic;
rstA : in std_logic;
eventSetA : in std_logic_vector(iSwEvent_g-1 downto 0); --to set event (pulse!)
eventReadA : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set (can be acked by ap!!!)
--port B -> AP
clkB : in std_logic;
rstB : in std_logic;
eventAckB : in std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to ack events (pulse!)
eventReadB : out std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0); --to read event set
--hw event set pulse (must be synchronous to clkB!)
hwEventSetPulseB : in std_logic_vector(iHwEvent_g-1 downto 0)
);
end entity pdiEvent;
architecture rtl of pdiEvent is
--in clk domain A
signal eventA_s, --stores the events in A domain
eventA_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventA_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
signal hwEventA_setPulse --sets the hw event only
: std_logic_vector(iHwEvent_g-1 downto 0);
--in clk domain B
signal eventB_s, --stores the events in B domain
eventB_ackPulse --ack the event (by ap)
: std_logic_vector(iSwEvent_g+iHwEvent_g-1 downto 0);
signal eventB_setPulse --sets the sw event only (by pcp)
: std_logic_vector(iSwEvent_g-1 downto 0);
begin
--pcp
eventReadA <= eventA_s;
--eventA_s stores all events
--eventA_ackPulse sends acks for all events
--eventA_setPulse sends set for sw event only
eventA_setPulse <= eventSetA;
--hwEventA_setPulse sends set for hw event only
process(clkA, rstA)
variable event_var : std_logic_vector(eventA_s'range);
begin
if rstA = '1' then
eventA_s <= (others => '0');
elsif clkA = '1' and clkA'event then
--get event state to do magic
event_var := eventA_s;
--first let the ack does its work...
event_var := event_var and not eventA_ackPulse;
--second the sw events may overwrite the ack...
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventA_setPulse(iSwEvent_g-1 downto 0);
--last but not least, the hw events have its chance too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventA_setPulse(iHwEvent_g-1 downto 0);
--and now, export it
eventA_s <= event_var;
end if;
end process;
--ap
eventReadB <= eventB_s;
--eventB_s stores all events
--eventB_ackPulse sends acks for all events
eventB_ackPulse <= eventAckB;
--eventB_setPulse sends set for sw event only
--hwEventSetPulseB sends set for hw event only
process(clkB, rstB)
variable event_var : std_logic_vector(eventB_s'range);
begin
if rstB = '1' then
eventB_s <= (others => '0');
elsif clkB = '1' and clkB'event then
--I know, its almost the same as for A, but for clarity...
--get event state
event_var := eventB_s;
--doing ack
event_var := event_var and not eventB_ackPulse;
--sw events may overwrite
event_var(iSwEvent_g-1 downto 0) := event_var(iSwEvent_g-1 downto 0) or
eventB_setPulse(iSwEvent_g-1 downto 0);
--hw events may overwrite too
event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) := event_var(iSwEvent_g+iHwEvent_g-1 downto iSwEvent_g) or
hwEventSetPulseB(iHwEvent_g-1 downto 0);
--and let's export
eventB_s <= event_var;
end if;
end process;
--xing the domains a to b
syncEventSetGen : for i in 0 to iSwEvent_g-1 generate
--only the software events are transferred!
syncEventSet : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkA,
rstSrc => rstA,
dataSrc => eventA_setPulse(i),
clkDst => clkB,
rstDst => rstB,
dataDst => eventB_setPulse(i)
);
end generate;
--xing the domains b to a
syncEventAckGen : for i in eventB_s'range generate
--all events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => eventB_ackPulse(i),
clkDst => clkA,
rstDst => rstA,
dataDst => eventA_ackPulse(i)
);
end generate;
syncHwEventGen : for i in 0 to iHwEvent_g-1 generate
--hw events are transferred
syncEventAck : entity work.slow2fastSync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
port map (
clkSrc => clkB,
rstSrc => rstB,
dataSrc => hwEventSetPulseB(i),
clkDst => clkA,
rstDst => rstA,
dataDst => hwEventA_setPulse(i)
);
end generate;
end architecture rtl; |
--Led Display
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED_DISP IS
PORT( CLK_DISP :IN STD_LOGIC;
DATA_IN_1 :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN_2 :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN_3 :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA2LED :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SEL2LED :OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY LED_DISP;
ARCHITECTURE ART1 OF LED_DISP IS
SIGNAL DOUT_OCT: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS (CLK_DISP)
VARIABLE VAR: STD_LOGIC_VECTOR (1 DOWNTO 0):="00";
BEGIN
IF(CLK_DISP 'EVENT AND CLK_DISP='1') THEN
IF(VAR="11")THEN
VAR:="00";
END IF;
IF(VAR="00")THEN
SEL2LED <="001";
DOUT_OCT <= DATA_IN_1;
ELSIF(VAR="01")THEN
SEL2LED <="010";
DOUT_OCT <= DATA_IN_2;
ELSE
SEL2LED <="100";
DOUT_OCT <= DATA_IN_3;
END IF;
VAR:=VAR+1;
END IF;
END PROCESS;
PROCESS(DOUT_OCT)
BEGIN
CASE DOUT_OCT IS
WHEN"0000"=> DATA2LED <="1111110";
WHEN"0001"=> DATA2LED <="0110000";
WHEN"0010"=> DATA2LED <="1101101";
WHEN"0011"=> DATA2LED <="1111001";
WHEN"0100"=> DATA2LED <="0110011";
WHEN"0101"=> DATA2LED <="1011011";
WHEN"0110"=> DATA2LED <="1011111";
WHEN"0111"=> DATA2LED <="1110000";
WHEN"1000"=> DATA2LED <="1111111";
WHEN"1001"=> DATA2LED <="1111011";
WHEN OTHERS => DATA2LED <="0000000";
END CASE;
END PROCESS;
END ARCHITECTURE ART1;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity axi_dynclk is
generic (
-- Users to add parameters here
kRefClkFreqHz : natural := 100_000_000;
kVersionMajor : natural := 1;
kVersionMinor : natural := 0;
kAddBUFMR : boolean := false; --true, if BUFMR should be added between MMCM and BUFIO
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI_LITE
C_S_AXI_LITE_DATA_WIDTH : integer := 32;
C_S_AXI_LITE_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI_LITE
s_axi_lite_aclk : in std_logic;
s_axi_lite_aresetn : in std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_awprot : in std_logic_vector(2 downto 0);
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_wstrb : in std_logic_vector((C_S_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_arprot : in std_logic_vector(2 downto 0);
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic
);
end axi_dynclk;
architecture arch_imp of axi_dynclk is
-- component declaration
component axi_dynclk_S00_AXI is
generic (
kRefClkFreqHz : natural := 100_000_000;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
CTRL_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
STAT_REG :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_O_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FB_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FRAC_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_DIV_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_LOCK_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FLTR_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_dynclk_S00_AXI;
component mmcme2_drp
generic (
DIV_F : integer
);
port(
SEN : in std_logic;
SCLK : in std_logic;
RST : in std_logic;
S1_CLKOUT0 : in std_logic_vector(35 downto 0);
S1_CLKFBOUT : in std_logic_vector(35 downto 0);
S1_DIVCLK : in std_logic_vector(13 downto 0);
S1_LOCK : in std_logic_vector(39 downto 0);
S1_DIGITAL_FILT : in std_logic_vector(9 downto 0);
REF_CLK : in std_logic;
CLKFBOUT_I : in std_logic;
CLKFBOUT_O : out std_logic;
SRDY : out std_logic;
PXL_CLK : out std_logic;
LOCKED_O : out std_logic
);
end component;
signal CTRL_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal STAT_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal CLK_O_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal CLK_FB_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal CLK_FRAC_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal CLK_DIV_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal CLK_LOCK_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal CLK_FLTR_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
type CLK_STATE_TYPE is (RESET, WAIT_LOCKED, WAIT_EN, WAIT_SRDY, ENABLED);
signal clk_state : CLK_STATE_TYPE := RESET;
signal srdy : std_logic;
signal pxl_clk : std_logic;
signal aLocked, xLocked, xBUFR_Rst : std_logic;
signal xLckdFallingFlag, xLckdRisingFlag : std_logic;
signal xLocked_q : std_logic_vector(1 downto 0);
signal sen_reg : std_logic := '0';
signal mmcm_fbclk_in : std_logic;
signal mmcm_fbclk_out : std_logic;
signal mmcm_clk : std_logic;
signal bufio_in : std_logic;
begin
-- Instantiation of Axi Bus Interface S00_AXI
axi_dynclk_S00_AXI_inst : axi_dynclk_S00_AXI
generic map (
kRefClkFreqHz => kRefClkFreqHz,
C_S_AXI_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH
)
port map (
CTRL_REG => CTRL_REG,
STAT_REG => STAT_REG,
CLK_O_REG => CLK_O_REG,
CLK_FB_REG => CLK_FB_REG,
CLK_FRAC_REG => CLK_FRAC_REG,
CLK_DIV_REG => CLK_DIV_REG,
CLK_LOCK_REG => CLK_LOCK_REG,
CLK_FLTR_REG => CLK_FLTR_REG,
S_AXI_ACLK => s_axi_lite_aclk,
S_AXI_ARESETN => s_axi_lite_aresetn,
S_AXI_AWADDR => s_axi_lite_awaddr,
S_AXI_AWPROT => s_axi_lite_awprot,
S_AXI_AWVALID => s_axi_lite_awvalid,
S_AXI_AWREADY => s_axi_lite_awready,
S_AXI_WDATA => s_axi_lite_wdata,
S_AXI_WSTRB => s_axi_lite_wstrb,
S_AXI_WVALID => s_axi_lite_wvalid,
S_AXI_WREADY => s_axi_lite_wready,
S_AXI_BRESP => s_axi_lite_bresp,
S_AXI_BVALID => s_axi_lite_bvalid,
S_AXI_BREADY => s_axi_lite_bready,
S_AXI_ARADDR => s_axi_lite_araddr,
S_AXI_ARPROT => s_axi_lite_arprot,
S_AXI_ARVALID => s_axi_lite_arvalid,
S_AXI_ARREADY => s_axi_lite_arready,
S_AXI_RDATA => s_axi_lite_rdata,
S_AXI_RRESP => s_axi_lite_rresp,
S_AXI_RVALID => s_axi_lite_rvalid,
S_AXI_RREADY => s_axi_lite_rready
);
GenerateBUFMR: if kAddBUFMR generate
BUFMR_inst : BUFMR
port map (
O => bufio_in, -- 1-bit output: Clock output (connect to BUFIOs/BUFRs)
I => mmcm_clk -- 1-bit input: Clock input (Connect to IBUF)
);
end generate GenerateBUFMR;
DontGenerateBUFMR: if not kAddBUFMR generate
bufio_in <= mmcm_clk;
end generate DontGenerateBUFMR;
-- Add user logic here
BUFIO_inst : BUFIO
port map (
O => PXL_CLK_5X_O, -- 1-bit output: Clock output (connect to I/O clock loads).
I => bufio_in -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => xBUFR_Rst, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => bufio_in -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
xBUFR_Rst <= xLckdRisingFlag; --pulse CLR on BUFR once the clock returns
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 2
)
PORT MAP(
SEN => sen_reg,
SCLK => s_axi_lite_aclk,
RST => not(s_axi_lite_aresetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => aLocked
);
mmcm_fbclk_in <= mmcm_fbclk_out; --Don't bother compensating for any delay, because we don't need a phase relationship between
--REF_CLK and PXL_CLK
SyncAsyncLocked: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2, --use double FF synchronizer
kResetPolarity => '0')
port map (
aReset => s_axi_lite_aresetn,
aIn => aLocked,
OutClk => s_axi_lite_aclk,
oOut => xLocked);
LockedDetect: process(s_axi_lite_aclk)
begin
if Rising_Edge(s_axi_lite_aclk) then
xLocked_q <= xLocked & xLocked_q(1);
xLckdFallingFlag <= xLocked_q(1) and not xLocked;
xLckdRisingFlag <= not xLocked_q(1) and xLocked;
end if;
end process LockedDetect;
PXL_CLK_O <= pxl_clk;
LOCKED_O <= aLocked; --dcm_locked of processor system reset expects direct connection to MMCM_Locked
process (s_axi_lite_aclk)
begin
if (rising_edge(s_axi_lite_aclk)) then
if (s_axi_lite_aresetn = '0') then
clk_state <= RESET;
else
case clk_state is
when RESET =>
clk_state <= WAIT_LOCKED;
when WAIT_LOCKED =>
-- This state ensures that the initial SRDY pulse
-- doesnt interfere with the WAIT_SRDY state
if (xLocked = '1') then
clk_state <= WAIT_EN;
end if;
when WAIT_EN =>
if (CTRL_REG(0) = '1') then
clk_state <= WAIT_SRDY;
end if;
when WAIT_SRDY =>
if (srdy = '1') then
clk_state <= ENABLED;
end if;
when ENABLED =>
if (CTRL_REG(0) = '0') then
clk_state <= WAIT_EN;
end if;
when others => --Never reached
clk_state <= RESET;
end case;
end if;
end if;
end process;
STAT_REG(0) <= '1' when clk_state = ENABLED else
'0';
process (s_axi_lite_aclk)
begin
if (rising_edge(s_axi_lite_aclk)) then
if (s_axi_lite_aresetn = '0') then
sen_reg <= '0';
else
if (clk_state = WAIT_EN and CTRL_REG(0) = '1') then
sen_reg <= '1';
else
sen_reg <= '0';
end if;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
-------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_fifo;
use axi_datamover_v5_1_10.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_datamover_wrdata_cntl;
architecture implementation of axi_datamover_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
--sig_strbgen_bytes <= (others => '1'); -- set to the max value
-- set the length to the max number of bytes per databeat
sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Indeterminate BTT case. Strobes come from the Stream
-- input from the Indeterminate BTT module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Indeterminate BTT Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_INDET_BTT;
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_fifo;
use axi_datamover_v5_1_10.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_datamover_wrdata_cntl;
architecture implementation of axi_datamover_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
--sig_strbgen_bytes <= (others => '1'); -- set to the max value
-- set the length to the max number of bytes per databeat
sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Indeterminate BTT case. Strobes come from the Stream
-- input from the Indeterminate BTT module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Indeterminate BTT Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_INDET_BTT;
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_fifo;
use axi_datamover_v5_1_10.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_datamover_wrdata_cntl;
architecture implementation of axi_datamover_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
--sig_strbgen_bytes <= (others => '1'); -- set to the max value
-- set the length to the max number of bytes per databeat
sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Indeterminate BTT case. Strobes come from the Stream
-- input from the Indeterminate BTT module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Indeterminate BTT Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_INDET_BTT;
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:16:06 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/dds/dds_stub.vhdl
-- Design : dds
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dds is
Port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 39 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 39 downto 0 )
);
end dds;
architecture stub of dds is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_phase_tvalid,s_axis_phase_tdata[39:0],m_axis_data_tvalid,m_axis_data_tdata[31:0],m_axis_phase_tvalid,m_axis_phase_tdata[39:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "dds_compiler_v6_0,Vivado 2014.1";
begin
end;
|
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_ALU.vhd 2653 2018-06-05 18:14:10Z gary.mups $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Op : in T_ALU_OP;
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
signal SBX_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
variable CT : std_logic;
begin
CT:='0';
if( Op=ALU_OP_AND or --"0001" These OpCodes used to have LSB set
Op=ALU_OP_ADC or --"0011"
Op=ALU_OP_EQ2 or --"0101"
Op=ALU_OP_SBC or --"0111"
Op=ALU_OP_ROL or --"1001"
Op=ALU_OP_ROR or --"1011"
-- Op=ALU_OP_EQ3 or --"1101"
Op=ALU_OP_INC --"1111"
) then
CT:='1';
end if;
C := P_In(Flag_C) or not CT;--was: or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
if P_In(Flag_D) = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
variable Q_t : std_logic_vector(7 downto 0);
variable Q2_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
Q2_t := BusA;
case Op is
when ALU_OP_OR=>
Q_t := BusA or BusB;
when ALU_OP_AND=>
Q_t := BusA and BusB;
when ALU_OP_EOR=>
Q_t := BusA xor BusB;
when ALU_OP_ADC=>
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when ALU_OP_CMP=>
P_Out(Flag_C) <= SBC_C;
when ALU_OP_SAX=>
P_Out(Flag_C) <= SBC_C;
Q_t := SBX_Q; -- undoc: subtract (A & X) - (immediate)
when ALU_OP_SBC=>
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q; -- undoc: subtract (A & X) - (immediate), then decimal correction
when ALU_OP_ASL=>
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when ALU_OP_ROL=>
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when ALU_OP_LSR=>
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when ALU_OP_ROR=>
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when ALU_OP_ARR=>
Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1));
P_Out(Flag_V) <= Q_t(5) xor Q_t(6);
Q2_t := Q_t;
if P_In(Flag_D)='1' then
if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then
Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6");
end if;
if (BusA(7 downto 4) and BusB(7 downto 4)) > "0100" then
Q2_t(7 downto 4) := std_logic_vector(unsigned(Q_t(7 downto 4)) + x"6");
P_Out(Flag_C) <= '1';
else
P_Out(Flag_C) <= '0';
end if;
else
P_Out(Flag_C) <= Q_t(6);
end if;
when ALU_OP_BIT=>
P_Out(Flag_V) <= BusB(6);
when ALU_OP_DEC=>
Q_t := std_logic_vector(unsigned(BusA) - 1);
when ALU_OP_INC=>
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
null;
--EQ1,EQ2,EQ3 passes BusA to Q_t and P_in to P_out
end case;
case Op is
when ALU_OP_ADC=>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when ALU_OP_CMP|ALU_OP_SBC|ALU_OP_SAX=>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when ALU_OP_EQ1=>--dont touch P
when ALU_OP_BIT=>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when ALU_OP_ANC=>
P_Out(Flag_N) <= Q_t(7);
P_Out(Flag_C) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
if Op=ALU_OP_ARR then
-- handled above in ARR code
Q <= Q2_t;
else
Q <= Q_t;
end if;
end process;
end;
|
----------------------------------------------------------------------------------
-- Module Name: test_source_3840_2160_YCC_422_ch2 - Behavioral
--
-- Description: Generate a valid DisplayPort symbol stream for testing. In this
-- case a 3840x2160 @ 30p grey screen.
-- Timings:
-- YCC 422, 8 bits per component
-- H Vis 3840 V Vis 2160
-- H Front 48 V Front 3
-- H Sync 32 V Sync 5
-- H Back 112 V Back 23
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email (hamster@snap.net.nz)?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity colour_bars_3840 is
port (
clk : in std_logic;
new_frame : in std_logic;
next_pixels : in std_logic;
y0 : out std_logic(7 downto 0);
y1 : out std_logic(7 downto 0);
cb : out std_logic(7 downto 0);
cr : out std_logic(7 downto 0));
);
end test_source_3840_2160_YCC_422_ch2;
architecture arch of colour_bars_3840 is
constant BAR0_Y : std_logic_vector(8 downto 0) := "11110000";
constant BAR0_Cb : std_logic_vector(8 downto 0) := "10000000";
constant BAR0_Cr : std_logic_vector(8 downto 0) := "10000000";
constant BAR1_Y0 : std_logic_vector(8 downto 0) := "111000000"; -- 0xC0
constant BAR1_Y1 : std_logic_vector(8 downto 0) := "010000000"; -- 0xC0
constant BAR1_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR1_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR2_Y0 : std_logic_vector(8 downto 0) := "110100000"; -- 0xC0
constant BAR2_Y1 : std_logic_vector(8 downto 0) := "010000000"; -- 0xC0
constant BAR2_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR2_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR3_Y0 : std_logic_vector(8 downto 0) := "110000000"; -- 0xC0
constant BAR3_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR3_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR4_Y0 : std_logic_vector(8 downto 0) := "010000000"; -- 0xC0
constant BAR4_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR4_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR5_Y0 : std_logic_vector(8 downto 0) := "010000000"; -- 0xC0
constant BAR5_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR5_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR6_Y0 : std_logic_vector(8 downto 0) := "010000000"; -- 0xC0
constant BAR6_Cb : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
constant BAR6_Cr : std_logic_vector(8 downto 0) := "010000000"; -- 0x80
signal col_count : unsigned(10 downto 0) := (others => '0');
constant max_col_count : unsigned(10 downto 0) := to_unsigned(1919,12); -- (3840+32+48+112)*270/265-1
begin
------------------------------------------------------------------
-- The M number here is almost magic. Here's how to calculate it.
--
-- The pixel clock is 265MHz, or 53/54 of the DisplayPort's 270MHz
-- symbol rate. As I am using YCC 422 53 pixels are being sent
-- every 54 cycles, allowing a constant TU size of 54 symbols with
-- one FE symbol for padding.
--
-- So you should expect M to be 53/54 * 0x80000 = 0x07DA12.
--
-- And you will be wrong. Bash your head against the wall for a
-- week wrong.
--
-- Here's the right way. A line is sent every 2054 cycles of the
-- 135 MHz clock, or 4108 link symbols. Each line is 4032 pixel
-- clocks (at 265 MHz). So the M value should be 4032/4108*0x80000
-- = 514588.4 = 0x07DA1C.
--
-- That small difference is enough to make things not work.
--
-- So why the difference? It's because line length (4032) doesn't
-- divide evenly by 53. To get this bang-on you would need to add
-- an extra 13 symbols every 52 lines, and as it needs to transmit
-- two symbols per cycle this would be awkward.
--
-- However the second way gives actual pixel clock is 4032/4108*270
-- 265.004,868 MHz.
--
--
-- The upside of this scheme is that an accurate Mvid[7:0] value
-- followingthe BS and VB_ID be constant for all raster lines. So
-- you can use any legal value you like.
--
-- The downside is that you have to drive your pixel generator from
-- the transceiver's reference clock.
--------------------------------------------------------------------
M_value <= x"07DA1C"; -- For 265MHz/270Mhz
N_value <= x"080000";
H_visible <= x"F00"; -- 3840
H_total <= x"FC0"; -- 4032
H_sync_width <= x"030"; -- 128
H_start <= x"0A0"; -- 160
V_visible <= x"870"; -- 2160
V_total <= x"88F"; -- 2191
V_sync_width <= x"003"; -- 3
V_start <= x"01A"; -- 26
H_vsync_active_high <= '1';
V_vsync_active_high <= '1';
flag_sync_clock <= '1';
flag_YCCnRGB <= '1';
flag_422n444 <= '1';
flag_range_reduced <= '1';
flag_interlaced_even <= '0';
flag_YCC_colour_709 <= '0';
flags_3d_Indicators <= (others => '0');
bits_per_colour <= "01000";
stream_channel_count <= "010";
ready <= '1';
data(72) <= switch_point;
data(71 downto 36) <= (others => '0');
process(clk)
begin
if rising_edge(clk) then
switch_point <= '0';
block_count <= block_count+1;
if col_count = 0 then
if active_line = '1' then
data(35 downto 0) <= BE & DUMMY & BE & DUMMY;
else
data(35 downto 0) <= DUMMY & DUMMY & DUMMY & DUMMY;
end if;
phase <= '0';
block_count <= (others => '0');
-- we do this here to get the VB_ID field correct
elsif col_count < 1957 then
------------------------------------
-- Pixel data goes here
------------------------------------
if active_line = '1' then
if block_count = 26 then
if phase = '0' then
data(35 downto 0) <= FE & PIX_Cr & FE & PIX_Cb;
else
data(35 downto 0) <= FE & PIX_Y1 & FE & PIX_Y0;
end if;
block_count <= (others => '0');
phase <= not phase;
else
if phase = '0' then
data(35 downto 0) <= PIX_Y1 & PIX_Cr & PIX_Y0 & PIX_Cb;
else
data(35 downto 0) <= PIX_Cr & PIX_Y1 & PIX_Cb & PIX_Y0;
end if;
block_count <= block_count + 1;
end if;
else
data(35 downto 0) <= DUMMY & DUMMY & DUMMY & DUMMY;
switch_point <= '1';
end if;
elsif col_count = 1957 then
if active_line = '1' then
data(35 downto 0) <= VB_NVS & BS & VB_NVS & BS;
else
data(35 downto 0) <= VB_VS & BS & VB_VS & BS;
end if;
elsif col_count = 1958 then
data(35 downto 0) <= Maud & Mvid & Maud & Mvid;
elsif col_count = 1959 then
if active_line = '1' then
data(35 downto 0) <= Mvid & VB_NVS & Mvid & VB_NVS;
else
data(35 downto 0) <= Mvid & VB_VS & Mvid & VB_VS;
end if;
elsif col_count = 1960 then data(35 downto 0) <= DUMMY & Maud & DUMMY & Maud;
else data(35 downto 0) <= DUMMY & DUMMY & DUMMY & DUMMY;
end if;
----------------------------------
-- When to update the active_line,
-- use to set VB-ID field after
-- te BS symbols and control
-- emitting pixels
----------------------------------
if col_count = 1956 then
if line_count = max_active_line then
active_line <= '0';
end if;
end if;
if col_count = max_col_count then
if line_count = max_line_count then
active_line <= '1';
end if;
end if;
----------------------------------
-- Update the counters
----------------------------------
if col_count = max_col_count then
col_count <= (others => '0');
if line_count = max_line_count then
line_count <= (others => '0');
else
line_count <= line_count + 1;
end if;
else
col_count <= col_count + 1;
end if;
end if;
end process;
end architecture; |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for sine wave LUT
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
entity lut_Sine_tb is
end;
architecture test of lut_Sine_tb is
constant CLOCK_1_PERIOD : TIME := 10 ns;
signal Clock1 : STD_LOGIC := '1';
signal sim_Stop : STD_LOGIC := '0';
signal lut_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal lut_Q1_in : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q1_out : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q2_in : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q2_out : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q3_in : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q3_out : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q4_in : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q4_out : STD_LOGIC_VECTOR(7 downto 0);
begin
ClockProcess1 : process(Clock1)
begin
Clock1 <= (Clock1 xnor sim_Stop) after CLOCK_1_PERIOD / 2;
end process;
process
begin
wait for 4 * CLOCK_1_PERIOD;
for i in 0 to 1024 loop
lut_in <= to_slv(i, lut_in'length);
wait for CLOCK_1_PERIOD;
end loop;
wait for 4 * CLOCK_1_PERIOD;
sim_Stop <= '1';
wait;
end process;
lut_Q1_in <= lut_in;
lut_Q2_in <= lut_in;
lut_Q3_in <= lut_in;
lut_Q4_in <= lut_in;
lutQ1 : entity PoC.lut_Sine
generic map (
REG_OUTPUT => TRUE,
MAX_AMPLITUDE => 127,
POINTS => 256,
OFFSET_DEG => 0.0,
QUARTERS => 1
)
port map (
Clock => Clock1, --
Input => lut_Q1_in, --
Output => lut_Q1_out --
);
lutQ2 : entity PoC.lut_Sine
generic map (
REG_OUTPUT => TRUE,
MAX_AMPLITUDE => 127,
POINTS => 256,
OFFSET_DEG => 0.0,
QUARTERS => 2
)
port map (
Clock => Clock1, --
Input => lut_Q2_in, --
Output => lut_Q2_out --
);
lutQ3 : entity PoC.lut_Sine
generic map (
REG_OUTPUT => TRUE,
MAX_AMPLITUDE => 127,
POINTS => 256,
OFFSET_DEG => 0.0,
QUARTERS => 4
)
port map (
Clock => Clock1, --
Input => lut_Q3_in, --
Output => lut_Q3_out --
);
lutQ4 : entity PoC.lut_Sine
generic map (
REG_OUTPUT => TRUE,
MAX_AMPLITUDE => 127,
POINTS => 256,
OFFSET_DEG => 45.0,
QUARTERS => 4
)
port map (
Clock => Clock1, --
Input => lut_Q4_in, --
Output => lut_Q4_out --
);
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for sine wave LUT
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
entity lut_Sine_tb is
end;
architecture test of lut_Sine_tb is
constant CLOCK_1_PERIOD : TIME := 10 ns;
signal Clock1 : STD_LOGIC := '1';
signal sim_Stop : STD_LOGIC := '0';
signal lut_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal lut_Q1_in : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q1_out : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q2_in : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q2_out : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q3_in : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q3_out : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q4_in : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q4_out : STD_LOGIC_VECTOR(7 downto 0);
begin
ClockProcess1 : process(Clock1)
begin
Clock1 <= (Clock1 xnor sim_Stop) after CLOCK_1_PERIOD / 2;
end process;
process
begin
wait for 4 * CLOCK_1_PERIOD;
for i in 0 to 1024 loop
lut_in <= to_slv(i, lut_in'length);
wait for CLOCK_1_PERIOD;
end loop;
wait for 4 * CLOCK_1_PERIOD;
sim_Stop <= '1';
wait;
end process;
lut_Q1_in <= lut_in;
lut_Q2_in <= lut_in;
lut_Q3_in <= lut_in;
lut_Q4_in <= lut_in;
lutQ1 : entity PoC.lut_Sine
generic map (
REG_OUTPUT => TRUE,
MAX_AMPLITUDE => 127,
POINTS => 256,
OFFSET_DEG => 0.0,
QUARTERS => 1
)
port map (
Clock => Clock1, --
Input => lut_Q1_in, --
Output => lut_Q1_out --
);
lutQ2 : entity PoC.lut_Sine
generic map (
REG_OUTPUT => TRUE,
MAX_AMPLITUDE => 127,
POINTS => 256,
OFFSET_DEG => 0.0,
QUARTERS => 2
)
port map (
Clock => Clock1, --
Input => lut_Q2_in, --
Output => lut_Q2_out --
);
lutQ3 : entity PoC.lut_Sine
generic map (
REG_OUTPUT => TRUE,
MAX_AMPLITUDE => 127,
POINTS => 256,
OFFSET_DEG => 0.0,
QUARTERS => 4
)
port map (
Clock => Clock1, --
Input => lut_Q3_in, --
Output => lut_Q3_out --
);
lutQ4 : entity PoC.lut_Sine
generic map (
REG_OUTPUT => TRUE,
MAX_AMPLITUDE => 127,
POINTS => 256,
OFFSET_DEG => 45.0,
QUARTERS => 4
)
port map (
Clock => Clock1, --
Input => lut_Q4_in, --
Output => lut_Q4_out --
);
end;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_icon_8_port.vhd
-- /___/ /\ Timestamp : Fri Jun 13 11:37:00 BRT 2014
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_icon_8_port IS
port (
CONTROL0: inout std_logic_vector(35 downto 0);
CONTROL1: inout std_logic_vector(35 downto 0);
CONTROL2: inout std_logic_vector(35 downto 0);
CONTROL3: inout std_logic_vector(35 downto 0);
CONTROL4: inout std_logic_vector(35 downto 0);
CONTROL5: inout std_logic_vector(35 downto 0);
CONTROL6: inout std_logic_vector(35 downto 0);
CONTROL7: inout std_logic_vector(35 downto 0));
END chipscope_icon_8_port;
ARCHITECTURE chipscope_icon_8_port_a OF chipscope_icon_8_port IS
BEGIN
END chipscope_icon_8_port_a;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc750.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00750ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive :=1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00750ent;
ARCHITECTURE c01s01b01x01p05n02i00750arch OF c01s01b01x01p05n02i00750ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record:= (C85,C86,C88);
signal V1 : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
signal V2 : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
signal V3 : integer_vector(zero to fifteen) := (zero to fifteen => C5);
signal V4 : real_vector(zero to fifteen) := (zero to fifteen => C6);
signal V5 : time_vector (zero to fifteen) := (zero to fifteen => C7);
signal V6 : natural_vector(zero to fifteen):= (zero to fifteen => C8);
signal V7 : positive_vector(zero to fifteen):= (zero to fifteen => C9);
signal V8 : boolean_cons_vector:= C19;
signal V9 : severity_level_cons_vector:= C20;
signal V10 : integer_cons_vector:= C21;
signal V11 : real_cons_vector:= C22;
signal V12 : time_cons_vector:= C23;
signal V13 : natural_cons_vector := C24;
signal V14 : positive_cons_vector := C25;
signal V15 : boolean_cons_vectorofvector := C26;
signal V16 : severity_level_cons_vectorofvector:= C27;
signal V17 : integer_cons_vectorofvector:= C28;
signal V18 : real_cons_vectorofvector:= C29;
signal V19 : time_cons_vectorofvector:= C30;
signal V20 : natural_cons_vectorofvector:= C31;
signal V21 : positive_cons_vectorofvector:= C32;
signal V22 : record_std_package:= C50;
signal V23 : record_cons_array := C51;
signal V24 : record_cons_arrayofarray := C53 ;
signal V25 : boolean_vector_st := C70 ;
signal V26 : severity_level_vector_st:= C71;
signal V27 : integer_vector_st := C72;
signal V28 : real_vector_st := C73;
signal V29 : time_vector_st := C74;
signal V30 : natural_vector_st := C75;
signal V31 : positive_vector_st := C76;
signal V32 : record_array_st := C54a;
signal V33 : record_array_st := C54a;
signal V34 : record_array_new:= C54b;
signal V35 : record_of_records := C55;
signal V36 : byte := C60;
signal V37 : word := C61;
signal V41 : boolean_vector_range := C78;
signal V42 : severity_level_vector_range := C79;
signal V43 : integer_vector_range := C80;
signal V44 : real_vector_range:= C81 ;
signal V45 : time_vector_range := C82;
signal V46 : natural_vector_range := C83;
signal V47 : positive_vector_range := C84;
signal V48 : array_rec_std(zero to seven) := C85;
signal V49 : array_rec_cons(zero to seven) := C86;
signal V50 : array_rec_rec(zero to seven) := C88;
signal V51 : record_of_arr_of_record := C102;
BEGIN
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34= C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00750"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00750 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00750arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc750.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00750ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive :=1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00750ent;
ARCHITECTURE c01s01b01x01p05n02i00750arch OF c01s01b01x01p05n02i00750ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record:= (C85,C86,C88);
signal V1 : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
signal V2 : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
signal V3 : integer_vector(zero to fifteen) := (zero to fifteen => C5);
signal V4 : real_vector(zero to fifteen) := (zero to fifteen => C6);
signal V5 : time_vector (zero to fifteen) := (zero to fifteen => C7);
signal V6 : natural_vector(zero to fifteen):= (zero to fifteen => C8);
signal V7 : positive_vector(zero to fifteen):= (zero to fifteen => C9);
signal V8 : boolean_cons_vector:= C19;
signal V9 : severity_level_cons_vector:= C20;
signal V10 : integer_cons_vector:= C21;
signal V11 : real_cons_vector:= C22;
signal V12 : time_cons_vector:= C23;
signal V13 : natural_cons_vector := C24;
signal V14 : positive_cons_vector := C25;
signal V15 : boolean_cons_vectorofvector := C26;
signal V16 : severity_level_cons_vectorofvector:= C27;
signal V17 : integer_cons_vectorofvector:= C28;
signal V18 : real_cons_vectorofvector:= C29;
signal V19 : time_cons_vectorofvector:= C30;
signal V20 : natural_cons_vectorofvector:= C31;
signal V21 : positive_cons_vectorofvector:= C32;
signal V22 : record_std_package:= C50;
signal V23 : record_cons_array := C51;
signal V24 : record_cons_arrayofarray := C53 ;
signal V25 : boolean_vector_st := C70 ;
signal V26 : severity_level_vector_st:= C71;
signal V27 : integer_vector_st := C72;
signal V28 : real_vector_st := C73;
signal V29 : time_vector_st := C74;
signal V30 : natural_vector_st := C75;
signal V31 : positive_vector_st := C76;
signal V32 : record_array_st := C54a;
signal V33 : record_array_st := C54a;
signal V34 : record_array_new:= C54b;
signal V35 : record_of_records := C55;
signal V36 : byte := C60;
signal V37 : word := C61;
signal V41 : boolean_vector_range := C78;
signal V42 : severity_level_vector_range := C79;
signal V43 : integer_vector_range := C80;
signal V44 : real_vector_range:= C81 ;
signal V45 : time_vector_range := C82;
signal V46 : natural_vector_range := C83;
signal V47 : positive_vector_range := C84;
signal V48 : array_rec_std(zero to seven) := C85;
signal V49 : array_rec_cons(zero to seven) := C86;
signal V50 : array_rec_rec(zero to seven) := C88;
signal V51 : record_of_arr_of_record := C102;
BEGIN
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34= C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00750"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00750 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00750arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc750.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00750ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive :=1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00750ent;
ARCHITECTURE c01s01b01x01p05n02i00750arch OF c01s01b01x01p05n02i00750ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record:= (C85,C86,C88);
signal V1 : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
signal V2 : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
signal V3 : integer_vector(zero to fifteen) := (zero to fifteen => C5);
signal V4 : real_vector(zero to fifteen) := (zero to fifteen => C6);
signal V5 : time_vector (zero to fifteen) := (zero to fifteen => C7);
signal V6 : natural_vector(zero to fifteen):= (zero to fifteen => C8);
signal V7 : positive_vector(zero to fifteen):= (zero to fifteen => C9);
signal V8 : boolean_cons_vector:= C19;
signal V9 : severity_level_cons_vector:= C20;
signal V10 : integer_cons_vector:= C21;
signal V11 : real_cons_vector:= C22;
signal V12 : time_cons_vector:= C23;
signal V13 : natural_cons_vector := C24;
signal V14 : positive_cons_vector := C25;
signal V15 : boolean_cons_vectorofvector := C26;
signal V16 : severity_level_cons_vectorofvector:= C27;
signal V17 : integer_cons_vectorofvector:= C28;
signal V18 : real_cons_vectorofvector:= C29;
signal V19 : time_cons_vectorofvector:= C30;
signal V20 : natural_cons_vectorofvector:= C31;
signal V21 : positive_cons_vectorofvector:= C32;
signal V22 : record_std_package:= C50;
signal V23 : record_cons_array := C51;
signal V24 : record_cons_arrayofarray := C53 ;
signal V25 : boolean_vector_st := C70 ;
signal V26 : severity_level_vector_st:= C71;
signal V27 : integer_vector_st := C72;
signal V28 : real_vector_st := C73;
signal V29 : time_vector_st := C74;
signal V30 : natural_vector_st := C75;
signal V31 : positive_vector_st := C76;
signal V32 : record_array_st := C54a;
signal V33 : record_array_st := C54a;
signal V34 : record_array_new:= C54b;
signal V35 : record_of_records := C55;
signal V36 : byte := C60;
signal V37 : word := C61;
signal V41 : boolean_vector_range := C78;
signal V42 : severity_level_vector_range := C79;
signal V43 : integer_vector_range := C80;
signal V44 : real_vector_range:= C81 ;
signal V45 : time_vector_range := C82;
signal V46 : natural_vector_range := C83;
signal V47 : positive_vector_range := C84;
signal V48 : array_rec_std(zero to seven) := C85;
signal V49 : array_rec_cons(zero to seven) := C86;
signal V50 : array_rec_rec(zero to seven) := C88;
signal V51 : record_of_arr_of_record := C102;
BEGIN
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34= C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00750"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00750 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00750arch;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: digit_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY digit_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END digit_exdes;
ARCHITECTURE xilinx OF digit_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT digit IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : digit
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY drigmorn1_top IS
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
vramaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
-- Architecture declarations
signal csromn : std_logic;
signal csesramn : std_logic;
signal csisramn : std_logic;
-- Internal signal declarations
signal vramaddr2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal vrambase : STD_LOGIC_VECTOR(15 DOWNTO 0):=x"4000";
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_esram : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(2 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
-- COMPONENT blk_mem_40K
-- PORT (
-- addra : IN std_logic_VECTOR (15 DOWNTO 0);
-- clka : IN std_logic;
-- dina : IN std_logic_VECTOR (7 DOWNTO 0);
-- wea : IN std_logic_VECTOR (0 DOWNTO 0);
-- douta : OUT std_logic_VECTOR (7 DOWNTO 0)
-- );
-- END COMPONENT;
component blk_mem_40K
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END component;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
BEGIN
sram_addr <= '0' & abus;
---- sram_data <= dbus_.
-- dbus_esram <= sram_data;
-- sram_data <= (others => 'Z') when rdn='0' else sram_data;
-- sram_ce <= csesramn;
-- sram_we <= wrn;
-- sram_oe <= rdn;
process(csesramn,wrn,rdn,dbus_out,sram_data)
begin
sram_ce <= '1';
sram_we <= '1';
sram_oe <= '1';
sram_data <= (others => 'Z');
if csesramn='0' then
sram_ce <= '0';
if wrn='0' then
sram_data <= dbus_out;
sram_we <= '0';
else
if rdn='0' then
dbus_esram <= sram_data;
sram_oe <= '0';
end if;
end if;
end if;
end process;
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram)
begin
case sel_s is
when "011" => dbus_in_cpu <= dbus_com1; -- UART
when "101" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when "110" => dbus_in_cpu <= dbus_in; -- Embedded SRAM
when others => dbus_in_cpu <= dbus_esram; -- External SRAM
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk <= CLOCK_40MHZ;
wrcom <= not wrn;
wea(0)<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn & csisramn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- external SRAM
-- 0x5F8-0x5FF
csesramn <= '0' when (csromn='1' and csisramn='1' AND iom='0') else '1';
-- csesramn <= not (cscom1 and csromnn and csiramn);
-- internal SRAM
-- below 0x4000
csisramn <= '0' when (abus(19 downto 14)="000000" AND iom='0') else '1';
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
-- U_3 : blk_mem_40K
-- PORT MAP (
-- clka => clk,
-- dina => dbus_out,
-- addra => abus(15 DOWNTO 0),
-- wea => wea,
-- douta => dbus_in
-- );
vramaddr2 <= vramaddr + vrambase;
U_3 : blk_mem_40K
PORT MAP (
clka => clk,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in
,
clkb => clk,
dinb => (others => '0'),
addrb => vramaddr2,
web => (others => '0'),
doutb => vramdata
);
U_2 : bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
|
--------------------------------------------------------------------------------
-- MIPS I CPU - Wishbone Master --
--------------------------------------------------------------------------------
-- --
-- KNOWN BUGS: --
-- --
-- o The master cause some severe trouble when communicating with slave --
-- interfaces that run on a different frequency than the master itself. --
-- In order to get the DDR to work with a 50 MHz master, I added an --
-- interface solely running at 50 MHz while the remaining DDR controller --
-- runs at 25 MHz. --
-- --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iwb.all;
use work.icpu.all;
entity wbm is
port(
mi : in master_in_t;
mo : out master_out_t;
-- Non Wishbone Signals
ci : out cpu_in_t;
co : in cpu_out_t;
irq : in std_logic_vector(7 downto 0)
);
end wbm;
architecture rtl of wbm is
type state_t is (Init, I0, I1, I2, D0, D1, D2, Cpu);
type regs_t is
record
s : state_t;
i : std_logic_vector(31 downto 0);
d : std_logic_vector(31 downto 0);
end record;
constant regs_d : regs_t :=
regs_t'( Init, (others => '0'), (others => '0') );
signal r, rin : regs_t := regs_d;
begin
ci.clk <= mi.clk;
ci.rst <= mi.rst;
process(irq, r, co, mi.ack, mi.dat)
variable t2 : std_logic_vector(31 downto 0);
begin
rin <= r;
t2 := (others => '0');
ci.hld <= '1';
ci.ins <= (others => '0'); -- AREA: (others => '-');
ci.dat <= (others => '0'); -- AREA: (others => '-');
ci.irq <= irq;
mo.adr <= (others => '0'); -- AREA: (others => '-');
mo.dat <= (others => '0'); -- AREA: (others => '-');
mo.we <= '0';
mo.sel <= (others => '0');
mo.stb <= '0';
case r.s is
when Init =>
rin.s <= I0;
-----------------------------------------------------------------------
-- Instruction --
-----------------------------------------------------------------------
-- First stage of instruction fetch. Wait for memory device to be done
-- loading desired data.
when I0 =>
mo.adr <= co.iadr;
mo.sel <= "1111";
mo.stb <= '1';
if mi.ack = '1' then
--rin.i <= mi.dat;
rin.s <= I1;
end if;
-- Latch fetched instruction.
-- If co.sel is not null, there is data to be processed from the memory
-- stage. Else directly execute instruction.
when I1 =>
mo.adr <= co.iadr;
mo.sel <= "1111";
mo.stb <= '1';
rin.i <= mi.dat;
rin.s <= I2;
when I2 =>
if mi.ack = '0' then
if co.sel = x"0" then
rin.s <= Cpu;
else
rin.s <= D0;
end if;
end if;
-----------------------------------------------------------------------
-- Data --
-----------------------------------------------------------------------
-- Set data to be written to propper location on the 32bit bus,
-- according to co.sel.
-- Wait until I/O device is ready.
when D0 =>
mo.adr <= co.dadr;
case co.sel is
when "0001" => mo.dat(7 downto 0) <= co.dat(7 downto 0);
when "0010" => mo.dat(15 downto 8) <= co.dat(7 downto 0);
when "0100" => mo.dat(23 downto 16) <= co.dat(7 downto 0);
when "1000" => mo.dat(31 downto 24) <= co.dat(7 downto 0);
when "0011" => mo.dat(15 downto 0) <= co.dat(15 downto 0);
when "1100" => mo.dat(31 downto 16) <= co.dat(15 downto 0);
when others => mo.dat <= co.dat;
end case;
mo.we <= co.we;
mo.sel <= co.sel;
mo.stb <= '1';
if mi.ack = '1' then
rin.s <= D1;
end if;
-- Finish write cycle or latch read data.
when D1 =>
mo.adr <= co.dadr;
-- Read.
case co.sel is
when "0001" => t2(7 downto 0) := mi.dat(7 downto 0);
when "0010" => t2(7 downto 0) := mi.dat(15 downto 8);
when "0100" => t2(7 downto 0) := mi.dat(23 downto 16);
when "1000" => t2(7 downto 0) := mi.dat(31 downto 24);
when "0011" => t2(15 downto 0) := mi.dat(15 downto 0);
when "1100" => t2(15 downto 0) := mi.dat(31 downto 16);
when others => t2 := mi.dat;
end case;
-- Write.
case co.sel is
when "0001" => mo.dat(7 downto 0) <= co.dat(7 downto 0);
when "0010" => mo.dat(15 downto 8) <= co.dat(7 downto 0);
when "0100" => mo.dat(23 downto 16) <= co.dat(7 downto 0);
when "1000" => mo.dat(31 downto 24) <= co.dat(7 downto 0);
when "0011" => mo.dat(15 downto 0) <= co.dat(15 downto 0);
when "1100" => mo.dat(31 downto 16) <= co.dat(15 downto 0);
when others => mo.dat <= co.dat;
end case;
mo.we <= co.we;
mo.sel <= co.sel;
mo.stb <= '1';
rin.d <= t2;
rin.s <= D2;
when D2 =>
if mi.ack = '0' then
rin.s <= Cpu;
end if;
-----------------------------------------------------------------------
-- Run CPU --
-----------------------------------------------------------------------
-- Enable CPU and run it for one cycle, then at least fetch the next
-- instruction.
when Cpu =>
ci.hld <= '0';
ci.ins <= r.i;
ci.dat <= r.d;
rin.s <= I0;
end case;
end process;
reg : process(mi.clk)
begin
if rising_edge(mi.clk) then
if mi.rst = '1' then r <= regs_d; else r <= rin; end if;
end if;
end process;
end architecture; |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
signal state_out, state_in : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- +--------+ +--------+
-- healthy | | | |-------------------+
-- +---header-->| Header |---Healthy body-->| Body |------------+ |
-- | +--------+ +--------+ | |
-- | | ^ | Healthy | ^ Healthy |
-- | | | | body | | Tail |
-- | | | | +---+ | |
-- | | | | v |
-- +--------+ | | | +--------+ |
-- No +-->| | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | Tail |--)--+
-- +---| | | +-----------Healthy Header--------------| | | |
-- +--------+ | +--------+ | |
-- ^ | ^ | No Faulty | |
-- | | | | Flit Flit | |
-- | | | +-Faulty Flit+ +---+ +---+ | |
-- | | | | | | | | | |
-- | | | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if (read_en ='1' or fake_credit = '1') then
credit_in <= '1';
end if;
if read_en = '0' and fake_credit = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, flit_type, valid_in)begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= Body_flit;
elsif flit_type ="100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= state_out;
elsif flit_type = "100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and flit_type = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and flit_type ="100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fetch_register is
Port ( mem_addr : in STD_LOGIC_VECTOR(5 downto 0);
mem_amount : in STD_LOGIC_VECTOR(4 downto 0);
--reg_val_lower : out STD_LOGIC_VECTOR(64 downto 0);
--reg_val_upper : out STD_LOGIC_VECTOR(64 downto 0);
reg_val : out STD_LOGIC_VECTOR(127 downto 0);
masterReset : in STD_LOGIC;
clk : in STD_LOGIC
);
end fetch_register;
architecture Behavioral of fetch_register is
type RAM is array (0 to 63) of integer range 0 to 255;
signal V : RAM := ( 12, 23, 222, 12, 231,42, 56, 121, 78,76,
23, 119, 12, 45, 55,100, 21, 3, 96, 34,
67, 1,1, 54, 133,55, 0, 5, 88, 64,
88, 123, 123, 24, 133,99, 25, 44, 98, 66,
200, 255, 20, 45, 255,255, 255, 255, 255, 54,
1, 251, 49, 234, 77,23, 33, 94, 66, 88,
222,12, 73, 75 );
begin
process (masterReset, clk)
variable address : integer range 0 to 64;
variable temp : std_logic_vector(127 downto 0);
begin
if (masterReset = '1') then
--reg_val_lower <= (others => '0');
--reg_val_upper <= (others => '0');
reg_val <= (others => '0');
elsif (clk'event and clk = '1') then
temp := (others => '0');
for I in 0 to conv_integer( IEEE.std_logic_arith.unsigned(mem_amount-1)) loop
--lowerAddr := 8*I;
--upperAddr := lowerAddr + 7;
address := conv_integer( IEEE.std_logic_arith.unsigned(mem_addr));
temp( (8*I + 7) downto 8*I) := std_logic_vector(IEEE.numeric_std.to_unsigned(V(address + I), 8));
--counter := counter + 1;
end loop;
reg_val <= temp;
end if;
end process;
end Behavioral; |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ba
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ba-rtl-a.vhd,v 1.3 2005/11/30 14:04:01 wig Exp $
-- $Date: 2005/11/30 14:04:01 $
-- $Log: ent_ba-rtl-a.vhd,v $
-- Revision 1.3 2005/11/30 14:04:01 wig
-- Updated testcase references
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Revision: 1.42 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ba
--
architecture rtl of ent_ba is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report """""";
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report """""";
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report """""";
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report """""";
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report """""";
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2to1 is
generic(
DATA_WIDTH : natural := 32
);
Port (
SEL : in STD_LOGIC;
A, B : in STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
X : out STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0)
);
end mux2to1;
architecture behavioral of mux2to1 is
begin
X <= A when (SEL = '0') else B;
end behavioral; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1448.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01448ent IS
END c08s07b00x00p02n01i01448ent;
ARCHITECTURE c08s07b00x00p02n01i01448arch OF c08s07b00x00p02n01i01448ent IS
begin
transmit: process
procedure ARITH(op : in integer;
z : out integer) is
begin
if (op > 5) then
z := 5;
return;
end if;
end ARITH;
variable k : integer ;
variable m : integer := 6;
begin
ARITH(m,k);
assert (k = 5)
report "***FAILED TEST: c08s07b00x00p02n01i01448 - RETURN statement to be sequence statements of IF statement"
severity ERROR;
assert NOT(k = 5)
report "***PASSED TEST: c08s07b00x00p02n01i01448"
severity NOTE;
wait;
end process;
END c08s07b00x00p02n01i01448arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1448.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01448ent IS
END c08s07b00x00p02n01i01448ent;
ARCHITECTURE c08s07b00x00p02n01i01448arch OF c08s07b00x00p02n01i01448ent IS
begin
transmit: process
procedure ARITH(op : in integer;
z : out integer) is
begin
if (op > 5) then
z := 5;
return;
end if;
end ARITH;
variable k : integer ;
variable m : integer := 6;
begin
ARITH(m,k);
assert (k = 5)
report "***FAILED TEST: c08s07b00x00p02n01i01448 - RETURN statement to be sequence statements of IF statement"
severity ERROR;
assert NOT(k = 5)
report "***PASSED TEST: c08s07b00x00p02n01i01448"
severity NOTE;
wait;
end process;
END c08s07b00x00p02n01i01448arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1448.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01448ent IS
END c08s07b00x00p02n01i01448ent;
ARCHITECTURE c08s07b00x00p02n01i01448arch OF c08s07b00x00p02n01i01448ent IS
begin
transmit: process
procedure ARITH(op : in integer;
z : out integer) is
begin
if (op > 5) then
z := 5;
return;
end if;
end ARITH;
variable k : integer ;
variable m : integer := 6;
begin
ARITH(m,k);
assert (k = 5)
report "***FAILED TEST: c08s07b00x00p02n01i01448 - RETURN statement to be sequence statements of IF statement"
severity ERROR;
assert NOT(k = 5)
report "***PASSED TEST: c08s07b00x00p02n01i01448"
severity NOTE;
wait;
end process;
END c08s07b00x00p02n01i01448arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2701.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p05n02i02701ent IS
END c13s04b01x00p05n02i02701ent;
ARCHITECTURE c13s04b01x00p05n02i02701arch OF c13s04b01x00p05n02i02701ent IS
constant i : integer := 12E6;
constant e : integer := 12e6;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(i = e)
report "***PASSED TEST: c13s04b01x00p05n02i02701"
severity NOTE;
assert ( i= e )
report "***FAILED TEST: c13s04b01x00p05n02i02701 - The letter E of the exponent of the integer can be written either in lower case or in upper case with the same meaning."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p05n02i02701arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2701.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p05n02i02701ent IS
END c13s04b01x00p05n02i02701ent;
ARCHITECTURE c13s04b01x00p05n02i02701arch OF c13s04b01x00p05n02i02701ent IS
constant i : integer := 12E6;
constant e : integer := 12e6;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(i = e)
report "***PASSED TEST: c13s04b01x00p05n02i02701"
severity NOTE;
assert ( i= e )
report "***FAILED TEST: c13s04b01x00p05n02i02701 - The letter E of the exponent of the integer can be written either in lower case or in upper case with the same meaning."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p05n02i02701arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2701.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p05n02i02701ent IS
END c13s04b01x00p05n02i02701ent;
ARCHITECTURE c13s04b01x00p05n02i02701arch OF c13s04b01x00p05n02i02701ent IS
constant i : integer := 12E6;
constant e : integer := 12e6;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(i = e)
report "***PASSED TEST: c13s04b01x00p05n02i02701"
severity NOTE;
assert ( i= e )
report "***FAILED TEST: c13s04b01x00p05n02i02701 - The letter E of the exponent of the integer can be written either in lower case or in upper case with the same meaning."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p05n02i02701arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library WORK;
use WORK.all;
entity c_multiplier is
generic
(
width : integer := 4
);
port
(
input1 : std_logic_vector((width - 1) downto 0);
input2 : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_multiplier;
architecture behavior of c_multiplier is
function bits_to_int (input : std_logic_vector)return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
end loop;
return ret_val;
end bits_to_int;
begin
process (input1, input2)
variable value : integer;
variable result : std_logic_Vector((width - 1) downto 0);
begin
value := bits_to_int(input1) * bits_to_int(input2);
for i in 0 to width - 1 loop
if (value rem 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
value := value / 2;
end loop;
output <= result;
end process;
end behavior; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ADDMPCoreAndMemory is
PORT (
in0 : IN std_logic_vector(31 DOWNTO 0);
in1 : IN std_logic_vector(31 DOWNTO 0);
out0 : OUT std_logic_vector(31 DOWNTO 0);
out1 : OUT std_logic_vector(31 DOWNTO 0);
frame_pointer : IN std_logic_vector(31 DOWNTO 0);
frame_pointer_out : OUT std_logic_vector(31 DOWNTO 0);
rst : IN std_logic;
clck : IN std_logic;
mem_wait : IN std_logic;
mem_push : IN std_logic_vector(31 DOWNTO 0)
);
end ADDMPCoreAndMemory;
architecture Structure of ADDMPCoreAndMemory is
component GreenDroidADDMPCore
PORT (
i00 : IN std_logic_vector(31 DOWNTO 0);
i01 : IN std_logic_vector(31 DOWNTO 0);
r00 : OUT std_logic_vector(31 DOWNTO 0);
r01 : OUT std_logic_vector(31 DOWNTO 0);
FP : IN std_logic_vector(31 DOWNTO 0);
FPout : OUT std_logic_vector(31 DOWNTO 0);
M_ADDR : OUT std_logic_vector(31 DOWNTO 0);
M_DATA : INOUT std_logic_vector(31 DOWNTO 0);
M_RD : INOUT std_logic;
M_WR : INOUT std_logic;
M_RDY : IN std_logic;
reset : IN std_logic;
CLK : IN std_logic
);
end component;
component mem
PORT (
M_ADDR : IN std_logic_vector(31 DOWNTO 0);
M_DATA : INOUT std_logic_vector(31 DOWNTO 0);
M_RD : IN std_logic;
M_WR : IN std_logic;
M_RDY : OUT std_logic;
MWAIT : IN std_logic;
MDAT : IN std_logic_vector(31 DOWNTO 0)
);
end component;
signal sig_M_ADDR, sig_M_DATA : std_logic_vector(31 DOWNTO 0);
signal sig_M_RD, sig_M_WR, sig_M_RDY : std_logic;
begin
Core: GreenDroidADDMPCore
port map (
i00 => in0, i01 => in1,
r00 => out0, r01 => out1,
FP => frame_pointer, FPout => frame_pointer_out,
M_ADDR => sig_M_ADDR,
M_DATA => sig_M_DATA,
M_RD => sig_M_RD,
M_WR => sig_M_WR,
M_RDY => sig_M_RDY,
reset => rst,
CLK => clck
);
mymem: mem
port map(
M_ADDR => sig_M_ADDR,
M_DATA => sig_M_DATA,
M_RD => sig_M_RD,
M_WR => sig_M_WR,
M_RDY => sig_M_RDY,
MWAIT => mem_wait,
MDAT => mem_push
);
end Structure;
|
library ieee ;
use ieee.std_logic_1164.all;
entity test_load is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
sot_in : in std_ulogic;
dat_o : out std_ulogic_vector(0 to 2559)
);
end test_load;
architecture RTL of test_load is
signal w : std_ulogic_vector(0 to 2559);
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
w <= dat_i & w(0 to 2559-32);
end if;
end process;
dat_o <= w;
end RTL;
|
library ieee ;
use ieee.std_logic_1164.all;
entity test_load is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
sot_in : in std_ulogic;
dat_o : out std_ulogic_vector(0 to 2559)
);
end test_load;
architecture RTL of test_load is
signal w : std_ulogic_vector(0 to 2559);
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
w <= dat_i & w(0 to 2559-32);
end if;
end process;
dat_o <= w;
end RTL;
|
entity e is
end entity;
architecture a of e is
signal x : integer := -3 * 4 + 2;
type t is range -5 to 11 - 3;
constant c : integer := +4 + 1;
signal y : t;
type int_array is array (integer range <>) of integer;
constant a1 : int_array(1 to 5) := (1, 2, 3, 4, 5);
constant a2 : int_array(1 to 7) := (2 to 3 => 6, others => 5);
constant a3 : int_array(1 to 9) := (8 => 24, others => 0);
constant a4 : int_array(5 downto 1) := (1, 2, 3, 4, 5);
constant a5 : int_array(5 downto 1) := (5 downto 3 => -1, others => 1);
begin
process is
variable b : boolean;
begin
x <= c / 2;
y <= t'high;
y <= t'left;
b := t'right = 8;
b := (t'right - t'left) = 2;
b := t'high /= 2;
b := true and true;
b := true and false;
b := true or false;
b := true xor true;
b := not true;
b := not false;
b := true xnor false;
b := false nand false;
b := false nor true;
b := 7 > 5 and 6 < 2;
x <= a1(2);
x <= a2(1);
x <= a2(3);
x <= a3(8);
x <= a1'length;
x <= a4(2);
x <= a5(4);
x <= 2 ** 4;
end process;
process is
begin
if true then
x <= 1;
end if;
if false then
x <= 5;
end if;
if false then
null;
else
x <= 5;
end if;
while false loop
null;
end loop;
if true then
x <= 1;
x <= 5;
null;
end if;
end process;
process is
variable r : real;
variable b : boolean;
begin
r := 1.0 + 0.0;
r := 1.5 * 4.0;
r := 2.0 / 2.0;
b := 4.6 > 1.2;
end process;
process
variable k : time;
begin
end process;
process
type int2_vec is array (66 to 67) of integer;
variable b : boolean;
begin
b := a1'length = 5;
b := a1'low(1) = 1;
b := a1'high(1) = 5;
b := a1'left = 1;
b := a1'right = 5;
b := int2_vec'length = 2;
b := int2_vec'low = 66;
end process;
process is
begin
case 1 is
when 1 => null;
when others => report "bang";
end case;
end process;
process is
variable r : real;
begin
r := 1.5 * 2;
r := 3 * 0.2;
r := 5.0 / 2;
r := 2.0 ** 4;
end process;
process is
constant one : bit := '1';
variable b : boolean;
begin
b := one = '1';
b := '0' /= one;
end process;
-- Billowitch tc3170
tc3170: process is
constant L : REAL := -10.0;
constant R : REAL := 10.0;
type RT1 is range L to R;
begin
assert ( RT1'right = RT1(R) ); -- Should be removed
end process;
bitvec: process is
constant x : bit_vector(1 to 3) := "101";
constant y : bit_vector(1 to 3) := "110";
constant z : bit_vector(3 downto 1) := "011";
variable b : boolean;
begin
b := (x and y) = "100";
b := (y and z) = "010";
b := (x or y) = "111";
b := not x = "010";
b := (x xor y) = "011";
b := (x xnor y) = "100";
b := (x nand y) = "011";
b := (x nor y) = "000";
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc303.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p04n01i00303ent IS
END c03s01b04x00p04n01i00303ent;
ARCHITECTURE c03s01b04x00p04n01i00303arch OF c03s01b04x00p04n01i00303ent IS
type REAL2 is range 0.0 to TRUE; -- Failure_here
-- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
-- DEFINITION MUST BE OF FLOATING POINT TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b04x00p04n01i00303 - Range constraint must be floating point."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p04n01i00303arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc303.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p04n01i00303ent IS
END c03s01b04x00p04n01i00303ent;
ARCHITECTURE c03s01b04x00p04n01i00303arch OF c03s01b04x00p04n01i00303ent IS
type REAL2 is range 0.0 to TRUE; -- Failure_here
-- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
-- DEFINITION MUST BE OF FLOATING POINT TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b04x00p04n01i00303 - Range constraint must be floating point."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p04n01i00303arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc303.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p04n01i00303ent IS
END c03s01b04x00p04n01i00303ent;
ARCHITECTURE c03s01b04x00p04n01i00303arch OF c03s01b04x00p04n01i00303ent IS
type REAL2 is range 0.0 to TRUE; -- Failure_here
-- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
-- DEFINITION MUST BE OF FLOATING POINT TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b04x00p04n01i00303 - Range constraint must be floating point."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p04n01i00303arch;
|
-- Author: Varun Nagpal
-- Net Id: vxn180010
-- VLSI Design Homework 1
-- 3rd Sept, 2018
--
-- Design: Testbench for the Generic Nth order (L = N+1 taps) Transposed Direct-form FIR-filter
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;
use work.fir_filter_shared_package.all;
entity Testbench is
end Testbench;
architecture test of testbench is
-- clock and asynchronous reset
signal clk : std_logic := '1';
signal rst : std_logic := '0';
-- Handshaking interface as source
signal valid_x_out : std_logic := '0';
signal ready_x_in : std_logic;
signal valid_h_out : std_logic := '0';
signal ready_h_in : std_logic;
-- Handshaking interface as sink
signal valid_in : std_logic;
signal ready_out : std_logic := '0';
-- Signals for Input samples & coefficients to filter and reading Output samples of filter
signal x_data_out : signed(X_BIT_SIZE-1 downto 0) := (others => '0');
signal h_data_out : signed(H_BIT_SIZE-1 downto 0) := (others => '0');
signal y_data_in : signed(Y_BIT_SIZE-1 downto 0);
begin
-- Create an instance of the FIR filter
DUT: entity work.fir_generic_transposed_filter(fir_rtl_arch) port map ( clk => clk,
rst => rst,
valid_x_in => valid_x_out,
ready_x_out => ready_x_in,
valid_h_in => valid_h_out,
ready_h_out => ready_h_in,
valid_out => valid_in,
ready_in => ready_out,
x_data_in => x_data_out,
h_data_in => h_data_out,
y_data_out => y_data_in );
-- Clock generation
clk_gen: process
begin
clk <= '0';
wait for CLK_HIGH_TIME;
clk <= '1';
wait for CLK_LOW_TIME;
end process clk_gen;
-- Reset generation
rst <= '1',
'0' after CLK_HIGH_TIME;
valid_h_out <= '0',
'1' after 1 * CLK_CYCLE_TIME,
'0' after 5 * CLK_CYCLE_TIME;
h_data_out <= ( others => '0' ),
( 0 => '1', others => '0' ) after 1 * CLK_CYCLE_TIME,
( others => '0' ) after 5 * CLK_CYCLE_TIME;
valid_x_out <= '0',
'1' after 5 * CLK_CYCLE_TIME;
x_data_out <= ( others => '0' ),
( 0 => '1', others => '0' ) after 5 * CLK_CYCLE_TIME,
( others => '1' ) after 15 * CLK_CYCLE_TIME;
print_messages: process begin
report "ready_h = " & to_string( ready_h_in ) &
" | valid_h = " & to_string( valid_h_out ) &
" | h_data = " & to_string( to_integer( signed( h_data_out ) ) ) &
" | ready_x = " & to_string( ready_x_in ) &
" | valid_x = " & to_string( valid_x_out ) &
" | x_data = " & to_string( to_integer( signed( x_data_out ) ) ) &
" | ready_y = " & to_string( ready_out ) &
" | valid_y = " & to_string( valid_in ) &
" | y_data = " & to_string( to_integer( signed( y_data_in ) ) );
wait for CLK_CYCLE_TIME;
end process print_messages;
stop_sim: process begin
wait for 24*CLK_CYCLE_TIME;
std.env.stop;
end process stop_sim;
end architecture test;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity seven_segment_ctrl is
port (
clk_i : in std_logic;
num_i : in std_logic_vector(15 downto 0);
an_o : out std_logic_vector(7 downto 0);
c_o : out std_logic_vector(7 downto 0)
);
end entity;
architecture behavioral of seven_segment_ctrl is
signal active_digit_s : std_logic_vector(3 downto 0);
signal pattern_s : std_logic_vector(7 downto 0);
signal digit_s : unsigned(3 downto 0);
signal turn_s : unsigned(2 downto 0); -- who's turn is it?
signal turn_next_s : unsigned(2 downto 0);
signal cycle_count_s : unsigned(15 downto 0); -- on overflow (every 65,535 cycles, increment turn)
signal cycle_count_next_s : unsigned(15 downto 0);
begin
an_o <= "11111110" when turn_s = 0 else
"11111101" when turn_s = 1 else
"11111011" when turn_s = 2 else
"11110111" when turn_s = 3 else
--"11101111" when turn_s = 4 else
--"11011111" when turn_s = 5 else
--"10111111" when turn_s = 6 else
--"01111111" when turn_s = 7 else
"11111111";
c_o <= pattern_s;
active_digit_s <= num_i(1 * 4 - 1 downto 0 * 4) when turn_s = 0 else
num_i(2 * 4 - 1 downto 1 * 4) when turn_s = 1 else
num_i(3 * 4 - 1 downto 2 * 4) when turn_s = 2 else
num_i(4 * 4 - 1 downto 3 * 4) when turn_s = 3 else
--num_i(5 * 4 - 1 downto 4 * 4) when turn_s = 4 else
--num_i(6 * 4 - 1 downto 5 * 4) when turn_s = 5 else
--num_i(7 * 4 - 1 downto 6 * 4) when turn_s = 6 else
--num_i(8 * 4 - 1 downto 7 * 4) when turn_s = 7 else
x"0";
digit_s <= unsigned(active_digit_s);
pattern_s <= "00000011" when digit_s = x"0" else
"10011111" when digit_s = x"1" else
"00100101" when digit_s = x"2" else
"00001101" when digit_s = x"3" else
"10011001" when digit_s = x"4" else
"01001001" when digit_s = x"5" else
"01000001" when digit_s = x"6" else
"00011111" when digit_s = x"7" else
"00000001" when digit_s = x"8" else
"00001001" when digit_s = x"9" else
"00010001" when digit_s = x"A" else
"11000001" when digit_s = x"B" else
"01100011" when digit_s = x"C" else
"10000101" when digit_s = x"D" else
"01100001" when digit_s = x"E" else
"01110001" when digit_s = x"F" else
"11111111";
clock_proc : process (clk_i)
begin
if rising_edge(clk_i) then
turn_s <= turn_next_s;
cycle_count_s <= cycle_count_next_s;
end if;
end process;
comb_proc : process (cycle_count_s)
begin
turn_next_s <= turn_s;
cycle_count_next_s <= cycle_count_s + 1;
if cycle_count_s = x"FFFF" then
turn_next_s <= turn_s + 1;
cycle_count_next_s <= x"0000";
end if;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2942.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n04i02942pkg is
procedure proc1 (x:integer; y : integer);
end c02s02b00x00p07n04i02942pkg;
package body c02s02b00x00p07n04i02942pkg is
procedure proc1 (x, y :in integer) is --Failure_here
begin
end proc1;
end c02s02b00x00p07n04i02942pkg;
ENTITY c02s02b00x00p07n04i02942ent IS
END c02s02b00x00p07n04i02942ent;
ARCHITECTURE c02s02b00x00p07n04i02942arch OF c02s02b00x00p07n04i02942ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n04i02942 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n04i02942arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2942.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n04i02942pkg is
procedure proc1 (x:integer; y : integer);
end c02s02b00x00p07n04i02942pkg;
package body c02s02b00x00p07n04i02942pkg is
procedure proc1 (x, y :in integer) is --Failure_here
begin
end proc1;
end c02s02b00x00p07n04i02942pkg;
ENTITY c02s02b00x00p07n04i02942ent IS
END c02s02b00x00p07n04i02942ent;
ARCHITECTURE c02s02b00x00p07n04i02942arch OF c02s02b00x00p07n04i02942ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n04i02942 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n04i02942arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2942.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n04i02942pkg is
procedure proc1 (x:integer; y : integer);
end c02s02b00x00p07n04i02942pkg;
package body c02s02b00x00p07n04i02942pkg is
procedure proc1 (x, y :in integer) is --Failure_here
begin
end proc1;
end c02s02b00x00p07n04i02942pkg;
ENTITY c02s02b00x00p07n04i02942ent IS
END c02s02b00x00p07n04i02942ent;
ARCHITECTURE c02s02b00x00p07n04i02942arch OF c02s02b00x00p07n04i02942ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n04i02942 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n04i02942arch;
|
entity tc3 is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tc3 is
signal clk : std_logic;
signal tg : std_logic;
begin
process (clk) is
begin
if falling_edge(clk) and (tg) then
null;
end if;
end process;
end behav;
|
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_jtag_debug_module_wrapper is
port(
MonDReg : in vl_logic_vector(31 downto 0);
break_readreg : in vl_logic_vector(31 downto 0);
clk : in vl_logic;
dbrk_hit0_latch : in vl_logic;
dbrk_hit1_latch : in vl_logic;
dbrk_hit2_latch : in vl_logic;
dbrk_hit3_latch : in vl_logic;
debugack : in vl_logic;
monitor_error : in vl_logic;
monitor_ready : in vl_logic;
reset_n : in vl_logic;
resetlatch : in vl_logic;
tracemem_on : in vl_logic;
tracemem_trcdata: in vl_logic_vector(35 downto 0);
tracemem_tw : in vl_logic;
trc_im_addr : in vl_logic_vector(6 downto 0);
trc_on : in vl_logic;
trc_wrap : in vl_logic;
trigbrktype : in vl_logic;
trigger_state_1 : in vl_logic;
jdo : out vl_logic_vector(37 downto 0);
jrst_n : out vl_logic;
st_ready_test_idle: out vl_logic;
take_action_break_a: out vl_logic;
take_action_break_b: out vl_logic;
take_action_break_c: out vl_logic;
take_action_ocimem_a: out vl_logic;
take_action_ocimem_b: out vl_logic;
take_action_tracectrl: out vl_logic;
take_action_tracemem_a: out vl_logic;
take_action_tracemem_b: out vl_logic;
take_no_action_break_a: out vl_logic;
take_no_action_break_b: out vl_logic;
take_no_action_break_c: out vl_logic;
take_no_action_ocimem_a: out vl_logic;
take_no_action_tracemem_a: out vl_logic
);
end usb_system_cpu_jtag_debug_module_wrapper;
|
entity tb_forloop2 is
end tb_forloop2;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_forloop2 is
signal vin : std_logic_vector (7 downto 0);
signal vout : std_logic_vector (3 downto 0);
signal clk : std_logic;
signal b : std_logic;
signal c : std_logic;
signal z : std_logic;
begin
dut: entity work.forloop2
port map (vin => vin, vout => vout, clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
vin <= x"00";
pulse;
assert vout = x"0" severity failure;
wait;
end process;
end behav;
|
--------------------------------------------------------------------------------------
-- _ _ _____ _ _____ _____ _____ _____ _ _____ _ __
-- | | / / / _ \ | | |_ _| | ____| | _ \ | ___| | | / _ \ | | / /
-- | | / / | | | | | | | | | |__ | | | | | |__ | | | | | | | | __ / /
-- | | / / | | | | | | | | | __| | | | | | __| | | | | | | | | / | / /
-- | |/ / | |_| | | |__ | | | |___ | |_| | | | | |___ | |_| | | |/ |/ /
-- |___/ \_____/ |_____| |_| |_____| |_____/ |_| |_____| \_____/ |___/|___/
--
-------------------------------------------------------------------------------------
-- OCI O'Connor Informatics
-- Allwegmatte 10
-- CH 6372 Ennetmoos, Switzerland
--
-----------------------------------------------------------------------------------
-- Unit : const_reconfig_vector.m.vhd
-- Author : Marco Tinner, NTB Buchs
-- Created : July 2012
-----------------------------------------------------------------------------------
-- Copyright(C) 2012: OCI O'Connor Informatics, Switzerland
-----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY const_reconfig_vector IS
PORT (
test_out: OUT std_logic_vector(3 DOWNTO 0)
);
END ENTITY const_reconfig_vector;
ARCHITECTURE rtl OF const_reconfig_vector IS
BEGIN
test_out <= x"2";
END ARCHITECTURE rtl; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--NOTE: the "diff" input comes from the output of the add_sub module.
--the way the opcodes are defined, the output is always the difference
--of A and B if the user is requesting a comparison operation. Otherwise,
--the output of this module will technically be undefined/wrong, but it
--doesn't matter because we won't be selecting it for the final output.
entity comparator is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
op : in STD_LOGIC_VECTOR (2 downto 0);
zero : in STD_LOGIC;
cout : in STD_LOGIC;
overflow : in STD_LOGIC;
diff : in STD_LOGIC_VECTOR (3 downto 0);
R : out STD_LOGIC
);
end comparator;
architecture Behavioral of comparator is
--signals
signal a_GEQ_b_SIGNED_R : std_logic:='0';
signal a_LE_b_SIGNED_R : std_logic:='0';
signal a_NEQ_b_UNSIGNED_R : std_logic:='0';
signal a_EQ_b_UNSIGNED_R : std_logic:='0';
signal a_GEQ_b_UNSIGNED_R : std_logic:='0';
signal a_LE_b_UNSIGNED_R : std_logic:='0';
signal s : std_logic_vector(3 downto 0);
begin
-------------------------------------------
--SIGNED PORTIONS
-------------------------------------------
--SIGNED is a bit more tricky. However, we can take
--advantage of the overflow flag and arrive at the
--following conclusions:
--(thanks to: http://teahlab.com/4-Bit_Signed_Comparator/)
-- X = Y <--> zero
-- X < Y <--> diff(3) XOR overflow
-- X > Y <--> !( zero OR ( diff(3) XOR overflow) )
--GEQ SIGNED
a_GEQ_b_SIGNED_R <= NOT(zero OR (diff(3) XOR overflow) ) OR zero;
--LE SIGNED
a_LE_b_SIGNED_R <= diff(3) XOR overflow;
-------------------------------------------
--UNSIGNED PORTIONS
-------------------------------------------
--EQ/NEQ
--well, *that* was easy :D
a_NEQ_b_UNSIGNED_R <= NOT(zero);
a_EQ_b_UNSIGNED_R <= zero;
--GEQ UNSIGNED
--Well, it turns out unsigned is harder. I'm way behind and
--so close to being done, so I'm borrowing some code from here
--to make sure the tests all work:
--http://sid-vlsiarena.blogspot.com/2013/03/4-bit-magnitude-comparator-vhdl-code.html
--I'll have to explain the karnaugh map theory behind it later in the report.
s(0)<= a(0) xnor b(0);
s(1)<= a(1) xnor b(1);
s(2)<= a(2) xnor b(2);
s(3)<= a(3) xnor b(3);
a_GEQ_b_UNSIGNED_R <= (a(3) and (not b(3)))
or (s(3) and a(2) and (not b(2)))
or (s(3) and s(2) and a(1)and (not b(1)))
or (s(3) and s(2) and s(1) and a(0) and (not b(0)))
or zero;
--LE UNSIGNED
a_LE_b_UNSIGNED_R <= (b(3) and (not a(3)))
or (s(3) and b(2) and (not a(2)))
or (s(3) and s(2) and b(1)and (not a(1)))
or (s(3) and s(2) and s(1) and b(0) and (not a(0)));
-------------------------------------------
--select output based on opcode
-------------------------------------------
output: entity work.mux8_bit port map (open, a_GEQ_b_SIGNED_R, a_LE_B_SIGNED_R,
a_NEQ_b_UNSIGNED_R, a_EQ_b_UNSIGNED_R, a_GEQ_b_UNSIGNED_R, a_LE_b_UNSIGNED_R,
open, op, R);
end Behavioral;
|
{{define "basicFB"}}-- This file has been automatically generated by goFB and should not be edited by hand
-- Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
-- VHDL support is EXPERIMENTAL ONLY
{{$block := index .Blocks .BlockIndex}}{{$blocks := .Blocks}}{{$basicFB := $block.BasicFB}}
-- This file represents the Basic Function Block for {{$block.Name}}
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
{{template "_entityFB" .}}
architecture rtl of {{$block.Name}} is
-- Build an enumerated type for the state machine
type state_type is ({{range $index, $state := $basicFB.States}}{{if $index}}, {{end}}STATE_{{$state.Name}}{{end}});
-- Register to hold the current state
signal state : state_type := STATE_{{(index $basicFB.States 0).Name}};
{{range $index, $event := $block.EventInputs}}signal {{$event.Name}} : std_logic;
{{end}}
{{if $block.InputVars}}-- signals to store variable sampled on enable {{range $index, $var := $block.InputVars}}
signal {{$var.Name}} : {{getVhdlType $var.Type}} := {{if eq (getVhdlType $var.Type) "std_logic"}}'0'{{else}}(others => '0'){{end}}; --register for input{{end}}
{{end}}
{{if $block.OutputVars}}-- signals to rename outputs {{range $index, $var := $block.OutputVars}}
signal {{$var.Name}} : {{getVhdlType $var.Type}} := {{if eq (getVhdlType $var.Type) "std_logic"}}'0'{{else}}(others => '0'){{end}}; {{end}}
{{end}}
{{if $block.EventOutputs}}
--signals to rename output events
{{range $index, $event := $block.EventOutputs}}signal {{$event.Name}}_eO_ecc_out : std_logic := '0'; --used when event driven from ECC (normal FB behaviour)
signal {{$event.Name}}_eO_alg_out : std_logic := '0'; --used when event driven from algorithm (normal SIFB behaviour)
{{end}}{{end}}
-- signals for enabling algorithms {{range $algIndex, $alg := $basicFB.Algorithms}}
signal {{$alg.Name}}_alg_en : std_logic := '0';
signal {{$alg.Name}}_alg_done : std_logic := '1';
{{end}}
-- signal for algorithm completion
signal AlgorithmsStart : std_logic := '0';
signal AlgorithmsDone : std_logic;
{{if $basicFB.InternalVars}}--internal variables {{range $varIndex, $var := $basicFB.InternalVars}}{{if not (or (variableIsTOPIO_IN $var) (variableIsTOPIO_OUT $var))}}{{/*ignore the special IO cos they are in the port list*/}}
signal {{$var.Name}} : {{getVhdlType $var.Type}}; --type was {{$var.Type}} {{end}}{{end}}{{end}}
begin
{{range $index, $event := $block.EventInputs}}{{$event.Name}} <= {{$event.Name}}_eI;
{{end}}
{{if $block.EventInputs}}{{if $block.InputVars}}-- Registers for data variables (only updated on relevant events)
process (clk)
begin
if rising_edge(clk) then
if sync = '1' then
{{range $eventIndex, $event := $block.EventInputs}}{{if $event.With}}
if {{$event.Name}}_eI = '1' then{{range $varIndex, $var := $block.InputVars}}{{if $event.IsLoadFor $var}}
{{$var.Name}} <= {{$var.Name}}_I;{{end}}{{end}}
end if;
{{end}}{{end}}
end if;
end if;
end process;{{end}}{{end}}
{{if $block.OutputVars}}--output var renaming, no output registers as inputs are stored where they are processed
{{range $varIndex, $var := $block.OutputVars}}{{$var.Name}}_O <= {{$var.Name}};
{{end}}{{end}}
-- Logic to advance to the next state
process (clk, reset)
begin
if reset = '1' then
state <= STATE_{{(index $basicFB.States 0).Name}};
AlgorithmsStart <= '1';
elsif (rising_edge(clk)) then
if AlgorithmsStart = '1' then --algorithms should be triggered only once via this pulse signal
AlgorithmsStart <= '0';
elsif enable = '1' then
--default values
state <= state;
AlgorithmsStart <= '0';
--next state logic
case state is
{{range $curStateIndex, $curState := $basicFB.States}}when STATE_{{$curState.Name}} =>
{{range $transIndex, $trans := $basicFB.GetTransitionsForState $curState.Name}}{{if $transIndex}}els{{end}}if {{$trans.Condition}} then
state <= STATE_{{$trans.Destination}};
AlgorithmsStart <= '1';
{{end}}end if;
{{end}}
end case;
end if;
end if;
end process;
-- Event outputs and internal algorithm triggers depend solely on the current state
process (state)
begin
--default values
{{if $block.EventOutputs}}--events
{{range $index, $event := $block.EventOutputs}}{{$event.Name}}_eO_ecc_out <= '0';
{{end}}{{end}}
{{if $basicFB.Algorithms}}--algorithms{{range $algIndex, $alg := $basicFB.Algorithms}}
{{$alg.Name}}_alg_en <= '0'; {{end}}{{end}}
case state is
{{range $curStateIndex, $curState := $basicFB.States}}when STATE_{{$curState.Name}} =>
{{range $actionIndex, $action := $curState.ECActions}}{{if $action.Algorithm}}{{$action.Algorithm}}_alg_en <= '1';
{{end}}{{if $action.Output}}{{$action.Output}}_eO_ecc_out <= '1';
{{end}}{{end}}
{{end}}
end case;
end process;
{{if $basicFB.Algorithms}}-- Algorithms process
process(clk)
begin
if rising_edge(clk) then
if AlgorithmsStart = '1' then
{{range $algIndex, $alg := $basicFB.Algorithms}}
if {{$alg.Name}}_alg_en = '1' then -- Algorithm {{$alg.Name}}
{{$alg.Name}}_alg_done <= '0';
{{if $block.EventOutputs}}
--logic for resetting algorithm-driven output events
{{range $index, $event := $block.EventOutputs}}{{$event.Name}}_eO_alg_out <= '0';
{{end}}{{end}}
end if;
{{end}}
end if;
{{range $algIndex, $alg := $basicFB.Algorithms}}
if {{$alg.Name}}_alg_done = '0' then -- Algorithm {{$alg.Name}}
--begin algorithm raw text
{{renameDoneSignal $alg.Other.Text $alg.Name}}
--end algorithm raw text
end if;
{{end}}
end if;
end process;{{else}}--This Basic FB had no algorithms
{{end}}
--Done signal
AlgorithmsDone <= (not AlgorithmsStart) and (not enable){{if $basicFB.Algorithms}} and{{range $algIndex, $alg := $basicFB.Algorithms}}{{if $algIndex}} and{{end}} {{$alg.Name}}_alg_done{{end}}{{end}};
Done <= AlgorithmsDone;
{{if $block.EventOutputs}}
--logic for renamed output events
{{range $index, $event := $block.EventOutputs}}{{$event.Name}}_eO <= {{$event.Name}}_eO_ecc_out or {{$event.Name}}_eO_alg_out;
{{end}}{{end}}
end rtl;
{{end}}
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
-- Title : TIE-50206, Bonus 5
-- Project :
-------------------------------------------------------------------------------
-- File : piano.vhd
-- Author : Jonas Nikula, Tuomas Huuki
-- Company : TUT
-- Created : 10.2.2016
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Pieno synth player (sequencer actually).
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 10.02.2016 1.0 huukit Created from synthesizer.vhd.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity piano is -- synthesizer generics and ports
-- generics
generic(
clk_freq_g : integer := 18432000;
melody_clk_div : integer := 18432000 / 2; -- Speed of melody.
sample_rate_g : integer := 48000;
data_width_g : integer := 16;
n_keys_g : integer := 4
);
-- ports
port(
clk : in std_logic;
rst_n : in std_logic;
keys_in : in std_logic_vector(n_keys_g - 1 downto 0);
melody_in : in std_logic;
aud_bclk_out : out std_logic;
aud_data_out : out std_logic;
aud_lrclk_out : out std_logic
);
end piano;
architecture rtl of piano is -- Defining used signals and components
component wave_gen is
generic(
width_g : integer; -- Width of the generated wave in bits.
step_g : integer -- Width of one step.
);
port(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, actove low.
sync_clear_in : in std_logic; -- Sync bit input to clear the counter.
value_out : out std_logic_vector(width_g - 1 downto 0) -- Counter value out.
);
end component;
component multi_port_adder is
generic(
operand_width_g : integer := 16; -- Specify default value for both.
num_of_operands_g : integer := 4
);
port(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, active low.
operands_in : in std_logic_vector((operand_width_g * num_of_operands_g) - 1 downto 0); -- Operand inputs
sum_out : out std_logic_vector(operand_width_g - 1 downto 0) -- Calculation result.
);
end component;
component audio_ctrl is
generic(
ref_clk_freq_g : integer := 18432000; -- Reference clock.
sample_rate_g : integer := 48000; -- Sample clock fs.
data_width_g : integer := 16 -- Data width.
);
port(
clk : in std_logic; -- Main clock.
rst_n : in std_logic; -- Reset, active low.
left_data_in : in std_logic_vector(data_width_g - 1 downto 0); -- Data in, left.
right_data_in : in std_logic_vector(data_width_g - 1 downto 0); -- Data in, right.
aud_bclk_out : out std_logic; -- Audio bitclock.
aud_data_out : out std_logic; -- Audio data.
aud_lrclk_out : out std_logic -- Audio bitclock L/R select.
);
end component;
type wavegen_output_arr is array (0 to n_keys_g - 1) -- Define an array type to hold
of std_logic_vector(data_width_g - 1 downto 0); -- wavegen output values,
-- so they can be easily modified
constant melody_len_c : integer := 32; -- Define the array and length to hold the
type melody_arr is array (0 to melody_len_c - 1) -- melody that is supposed to play.
of std_logic_vector(n_keys_g -1 downto 0);
constant melody_data_c : melody_arr :=( "1110", -- Melody data, not very musical. :)
"1101",
"1011",
"0111",
"1011",
"1101",
"1110",
"1100",
"1001",
"0011",
"1001",
"1100",
"1010",
"0101",
"0111",
"1101",
"1011",
"1110",
"0111",
"1011",
"1101",
"1110",
"1110",
"1101",
"1011",
"0111",
"0000",
"1111",
"1001",
"1111",
"0110",
"1111");
-- registers
signal wavegen_output_r : wavegen_output_arr;
signal adder_input_r : std_logic_vector((data_width_g * n_keys_g) - 1 downto 0);
signal adder_output_r : std_logic_vector(data_width_g - 1 downto 0);
signal aud_bclk_r : std_logic;
signal aud_data_r : std_logic;
signal aud_lrclk_r : std_logic;
signal keys_input_r : std_logic_vector(n_keys_g - 1 downto 0);
signal melody_counter_r : integer;
signal melody_clkcnt_r : integer;
constant melody_clkdiv_c : integer := melody_clk_div;
begin -- rtl
-- registers to outputs
aud_bclk_out <= aud_bclk_r;
aud_data_out <= aud_data_r;
aud_lrclk_out <= aud_lrclk_r;
-- Melody player. Reads keys, or plays the melody.
melody_play : process(clk, rst_n)
begin
if(rst_n = '0') then -- Reset outputs.
melody_clkcnt_r <= melody_clkdiv_c;
melody_counter_r <= 0;
keys_input_r <= (others => '1');
elsif(clk'event and clk = '1') then
if(melody_in = '0') then -- If no melody requested, use keys.
keys_input_r <= keys_in;
melody_counter_r <= 0;
else -- Else step through sequencer pattern.
keys_input_r <= melody_data_c(melody_counter_r);
if(melody_clkcnt_r = 0) then
melody_clkcnt_r <= melody_clkdiv_c;
melody_counter_r <= melody_counter_r + 1;
if(melody_counter_r = (melody_len_c - 1)) then
melody_counter_r <= 0;
end if;
else
melody_clkcnt_r <= melody_clkcnt_r - 1;
end if;
end if;
end if;
end process melody_play;
-- a process that scales wavegen output according to how many wavegenerators
-- are online. If 1 is on, output is divided by 1, 2 = 2, and so on.
-- This prevents overflow that comes from adding two signals together.
waveform_scaling : process(clk, rst_n)
-- process variables
variable temp : integer := 0;
variable divider : integer := 0;
begin
-- Only process on clock rising edge, and when NOT in reset mode
if(clk'event and clk = '1' and rst_n = '1') then -- Calculate on rising edge of clock.
divider := 0;
for I in 0 to n_keys_g - 1 loop -- calculate how many buttons are pushed
if (keys_input_r(I) = '0') then
divider := divider + 1;
end if;
end loop;
if (divider = 0) then -- failsafe to prevent div-by-0
divider := 1;
end if;
for I in 0 to n_keys_g - 1 loop -- modify wavegen outputs
temp := to_integer(signed(wavegen_output_r(I)));
temp := temp / divider;
adder_input_r((I+1)*data_width_g - 1 downto I*data_width_g) <= std_logic_vector(to_signed(temp, wavegen_output_r(I)'length));
end loop;
end if;
end process waveform_scaling;
-- instantiate as many wave generators as needed
wave_generators:
for I in 0 to n_keys_g - 1 generate
wavegen_arr : wave_gen
generic map
(
width_g => data_width_g,
step_g => 2**I
)
port map
(
clk => clk,
rst_n => rst_n,
sync_clear_in => keys_input_r(I),
value_out => wavegen_output_r(I)
);
end generate wave_generators;
i_adder : multi_port_adder
generic map
(
operand_width_g => data_width_g,
num_of_operands_g => n_keys_g
)
port map
(
clk => clk,
rst_n => rst_n,
operands_in => adder_input_r,
sum_out => adder_output_r
);
i_audio_ctrl : audio_ctrl
generic map
(
ref_clk_freq_g => clk_freq_g,
sample_rate_g => sample_rate_g,
data_width_g => data_width_g
)
port map
(
clk => clk,
rst_n => rst_n,
left_data_in => adder_output_r,
right_data_in => adder_output_r,
aud_bclk_out => aud_bclk_r,
aud_data_out => aud_data_r,
aud_lrclk_out => aud_lrclk_r
);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.xtcpkg.all;
use work.txt_util.all;
entity tracer is
generic (
trace_file: string := "trace.txt"
);
port (
clk: in std_logic;
dbgi: in execute_debug_type
);
end entity tracer;
architecture sim of tracer is
file t_file : TEXT open write_mode is trace_file;
signal clock: unsigned(31 downto 0) := (others => '0');
begin
logger: process(clk)
variable executed: string(1 to 1);
variable op: string(1 to 8);
begin
if rising_edge(clk) then
clock <= clock + 1;
if dbgi.valid then
if dbgi.executed then
executed := "E";
else
executed := " ";
end if;
if dbgi.dual then
op := hstr(dbgi.opcode2) & hstr(dbgi.opcode1);
else
op := hstr(dbgi.opcode2) & " ";
end if;
if TRACECLOCK then
print( t_file, executed & " 0x" & hstr(std_logic_vector(clock)) & " 0x" &
hstr(std_logic_vector(dbgi.pc)) & " 0x" & op & " 0x"
& hstr(std_logic_vector(dbgi.lhs))
& " 0x" & hstr(std_logic_vector(dbgi.rhs))
);
else
print( t_file, executed & " 0x" &
hstr(std_logic_vector(dbgi.pc)) & " 0x" & op & " 0x"
& hstr(std_logic_vector(dbgi.lhs))
& " 0x" & hstr(std_logic_vector(dbgi.rhs))
);
end if;
end if;
end if;
end process;
end sim;
|
architecture RTL of ENT is begin end architecture RTL;
architecture RTL
of
ENT is
begin
end;
architecture RTL
-- Some domment
of ENT is
begin
end;
architecture RTL--some comment
of ENT is
begin
end;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 4.25e-06,
scope => private
)
port map(
D => net2,
G => net1,
S => net3
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 4.25e-06,
scope => private
)
port map(
D => out1,
G => out1,
S => net3
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 3.52e-05
)
port map(
D => net3,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.1e-06,
W => Wcm_1,
Wcm_1init => 1.25e-06,
scope => private
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.1e-06,
W => Wcmout_1,
Wcmout_1init => 6.28e-05,
scope => private
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.5e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.5e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net5,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net5,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net5,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:34:18 10/20/2014
-- Design Name:
-- Module Name: filter - arc1
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY Filter is
PORT ( clk : in STD_LOGIC;
R0 : in STD_LOGIC_VECTOR (31 downto 0);
R1 : in STD_LOGIC_VECTOR (31 downto 0);
R2 : in STD_LOGIC_VECTOR (31 downto 0);
R3 : out STD_LOGIC_VECTOR (31 downto 0)
);
end Filter;
architecture arc1 of Filter is
signal ready : STD_LOGIC := '0';
signal k0, k1, k2, k3, k4, k5, k6, k7, k8 : STD_LOGIC_VECTOR(7 downto 0);
signal result : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
COMPONENT Mask is
PORT (
ready : in STD_LOGIC;
k0, k1, k2, k3, k4, k5, k6, k7, k8 : in STD_LOGIC_VECTOR (7 downto 0);
result : out STD_LOGIC_VECTOR (7 downto 0)
);
END COMPONENT Mask;
BEGIN theMask : Mask PORT MAP (
ready => ready,
result => result,
k0 => k0,
k1 => k1,
k2 => k2,
k3 => k3,
k4 => k4,
k5 => k5,
k6 => k6,
k7 => k7,
k8 => k8
);
PROCESS(R2) is
BEGIN
R3 <= (others=>'0');
for j in 3 downto 0 loop
k0 <= R0(j*8 + 7 downto j*8);
k1 <= R0(j*8 + 7 downto j*8);
k2 <= R0(j*8 + 7 downto j*8);
k3 <= R1(j*8 + 7 downto j*8);
k4 <= R1(j*8 + 7 downto j*8);
k5 <= R1(j*8 + 7 downto j*8);
k6 <= R2(j*8 + 7 downto j*8);
k7 <= R2(j*8 + 7 downto j*8);
k8 <= R2(j*8 + 7 downto j*8);
end loop;
END PROCESS;
PROCESS is
BEGIN
for j in 3 downto 0 loop
wait on result;
R3( j*8 + 7 downto j*8 ) <= result;
end loop;
END PROCESS;
end arc1;
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- 8 - B I T G P I O E A S Y C O R E
-- (gpio8.vhd)
--
-- Structural
--
-- Adapts the verilog gpio module to vhdl and the wbs/wbm types
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
-------------------------------------------------------------------------------
ENTITY gpio8 is
-------------------------------------------------------------------------------
port (
-- WISHBONE interface (with clock input)
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- GPIO pins
gpio0 : inout std_logic;
gpio1 : inout std_logic;
gpio2 : inout std_logic;
gpio3 : inout std_logic;
gpio4 : inout std_logic;
gpio5 : inout std_logic;
gpio6 : inout std_logic;
gpio7 : inout std_logic
);
end gpio8;
-------------------------------------------------------------------------------
ARCHITECTURE structural of gpio8 is
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
COMPONENT gpio_top is
-- this component is the link to the verilog module.
-- here, the signal names from simple_spi_top.v are used
-------------------------------------------------------------------------------
port (
-- WISHBONE interface
wb_clk_i : in std_logic; -- clock
wb_rst_i : in std_logic; -- reset (asynchronous active low)
wb_cyc_i : in std_logic; -- cycle
wb_stb_i : in std_logic; -- strobe
wb_adr_i : in std_logic_vector(7 downto 0); -- address
wb_we_i : in std_logic; -- write enable
wb_dat_i : in std_logic_vector(31 downto 0);-- data input
wb_dat_o : out std_logic_vector(31 downto 0);-- data output
wb_ack_o : out std_logic; -- bus termination
wb_inta_o : out std_logic; -- interrupt output
wb_sel_i : in std_logic_vector(3 downto 0); -- byte select (constant "0001")
-- GPIO interface
ext_pad_o : out std_logic_vector(7 downto 0); -- GPIO outputs
ext_pad_i : in std_logic_vector(7 downto 0); -- GPIO inputs
ext_padoe_o : out std_logic_vector(7 downto 0) -- output driver enables
);
END COMPONENT;
signal ext_pad_i_s : std_logic_vector(7 downto 0);
signal ext_pad_o_s : std_logic_vector(7 downto 0);
signal ext_padoe_o_s : std_logic_vector(7 downto 0);
signal dat_i_tmp_s : std_logic_vector(31 downto 0);
signal dat_o_tmp_s : std_logic_vector(31 downto 0);
signal wb_sel_s : std_logic_vector(3 downto 0);
--------------------------------------------------------------------------------
begin -- architecture structural
-------------------------------------------------------------------------------
-- data width adaption
dat_i_tmp_s <= x"000000" & wbs_in.dat;
wbs_out.dat <= dat_o_tmp_s(7 downto 0);
-- constant byte selection lines
wb_sel_s <= "0001";
-- tristate-able drivers
ext_pad_i_s(0) <= gpio0;
gpio0 <= 'Z' when ext_padoe_o_s(0) = '0' else ext_pad_o_s(0);
ext_pad_i_s(1) <= gpio1;
gpio1 <= 'Z' when ext_padoe_o_s(1) = '0' else ext_pad_o_s(1);
ext_pad_i_s(2) <= gpio2;
gpio2 <= 'Z' when ext_padoe_o_s(2) = '0' else ext_pad_o_s(2);
ext_pad_i_s(3) <= gpio3;
gpio3 <= 'Z' when ext_padoe_o_s(3) = '0' else ext_pad_o_s(3);
ext_pad_i_s(4) <= gpio4;
gpio4 <= 'Z' when ext_padoe_o_s(4) = '0' else ext_pad_o_s(4);
ext_pad_i_s(5) <= gpio5;
gpio5 <= 'Z' when ext_padoe_o_s(5) = '0' else ext_pad_o_s(5);
ext_pad_i_s(6) <= gpio6;
gpio6 <= 'Z' when ext_padoe_o_s(6) = '0' else ext_pad_o_s(6);
ext_pad_i_s(7) <= gpio7;
gpio7 <= 'Z' when ext_padoe_o_s(7) = '0' else ext_pad_o_s(7);
-------------------------------------------------------------------------------
GPIO_CORE : gpio_top
-------------------------------------------------------------------------------
port map (
-- WISHBONE interface
wb_clk_i => wbs_in.clk,
wb_rst_i => wbs_in.rst,
wb_cyc_i => wbs_in.cyc,
wb_stb_i => wbs_in.stb,
wb_adr_i => wbs_in.adr(7 downto 0),
wb_we_i => wbs_in.we,
wb_dat_i => dat_i_tmp_s,
wb_dat_o => dat_o_tmp_s,
wb_ack_o => wbs_out.ack,
wb_inta_o => wbs_out.irq,
wb_sel_i => wb_sel_s,
-- GPIO interface
ext_pad_o => ext_pad_o_s,
ext_pad_i => ext_pad_i_s,
ext_padoe_o => ext_padoe_o_s
);
end structural;
|
component ghrd_10as066n2_issp_0 is
port (
source_clk : in std_logic := 'X'; -- clk
source : out std_logic_vector(2 downto 0) -- source
);
end component ghrd_10as066n2_issp_0;
u0 : component ghrd_10as066n2_issp_0
port map (
source_clk => CONNECTED_TO_source_clk, -- source_clk.clk
source => CONNECTED_TO_source -- sources.source
);
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cc_cmplr_v3_0_964aa42461b15ac2.vhd when simulating
-- the core, cc_cmplr_v3_0_964aa42461b15ac2. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cc_cmplr_v3_0_964aa42461b15ac2 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END cc_cmplr_v3_0_964aa42461b15ac2;
ARCHITECTURE cc_cmplr_v3_0_964aa42461b15ac2_a OF cc_cmplr_v3_0_964aa42461b15ac2 IS
-- synthesis translate_off
COMPONENT wrapped_cc_cmplr_v3_0_964aa42461b15ac2
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cc_cmplr_v3_0_964aa42461b15ac2 USE ENTITY XilinxCoreLib.cic_compiler_v3_0(behavioral)
GENERIC MAP (
c_c1 => 58,
c_c2 => 58,
c_c3 => 58,
c_c4 => 0,
c_c5 => 0,
c_c6 => 0,
c_clk_freq => 2,
c_component_name => "cc_cmplr_v3_0_964aa42461b15ac2",
c_diff_delay => 2,
c_family => "artix7",
c_filter_type => 1,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_dout_tready => 0,
c_has_rounding => 0,
c_i1 => 58,
c_i2 => 58,
c_i3 => 58,
c_i4 => 0,
c_i5 => 0,
c_i6 => 0,
c_input_width => 24,
c_m_axis_data_tdata_width => 64,
c_m_axis_data_tuser_width => 16,
c_max_rate => 1120,
c_min_rate => 1120,
c_num_channels => 2,
c_num_stages => 3,
c_output_width => 58,
c_rate => 1120,
c_rate_type => 0,
c_s_axis_config_tdata_width => 1,
c_s_axis_data_tdata_width => 24,
c_sample_freq => 1,
c_use_dsp => 1,
c_use_streaming_interface => 1,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cc_cmplr_v3_0_964aa42461b15ac2
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tlast => m_axis_data_tlast,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing
);
-- synthesis translate_on
END cc_cmplr_v3_0_964aa42461b15ac2_a;
|
entity bounds28 is
end entity;
architecture test of bounds28 is
signal n : integer;
begin
main: process is
variable t : delay_length;
begin
n <= 1;
wait for 1 ns;
t := n * ms; -- OK
n <= -5;
wait for 1 ns;
t := n * fs; -- Error
wait;
end process;
end architecture;
|
-- Ian Roth
-- ECE 8455
-- VGA module, final project
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY VGA IS
PORT(
VGA_CLK, VGA_BLANK_N, VGA_HS, VGA_VS, start :OUT STD_LOGIC;
clk, rst :IN STD_LOGIC
);
END ENTITY VGA;
ARCHITECTURE Behavior OF VGA IS
SIGNAL Hcount :UNSIGNED(10 downto 0);
SIGNAL Vcount :UNSIGNED(10 downto 0);
SIGNAL int_hs, int_vs :STD_LOGIC;
CONSTANT Hactive :UNSIGNED(10 downto 0) := "10000000000"; -- 1024
CONSTANT Hsyncs :UNSIGNED(10 downto 0) := "10000011001"; -- 1048 = 1024 + 24 (+1)
CONSTANT Hsynce :UNSIGNED(10 downto 0) := "10010100001"; -- 1184 = 1024 + 24 + 136 (+1)
CONSTANT Htotal :UNSIGNED(10 downto 0) := "10101000000"; -- 1344
CONSTANT Vactive :UNSIGNED(9 downto 0) := "1100000000"; -- 768
CONSTANT Vsysns :UNSIGNED(9 downto 0) := "1100000011"; -- 768 + 3 (+1)
CONSTANT Vsynce :UNSIGNED(9 downto 0) := "1100001001"; -- 768 + 3 + 6 (+1)
CONSTANT Vtotal :UNSIGNED(9 downto 0) := "1100100110"; -- 806
BEGIN
VGA_CLK <= NOT clk;
start <= (NOT int_hs) AND (NOT int_vs);
VGA_HS <= int_hs;
VGA_VS <= int_vs;
PROCESS(clk, rst)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (rst = '1') THEN
Hcount <= "00000000000";
Vcount <= "00000000000";
int_hs <= '1';
int_vs <= '1';
ELSE
IF (Hcount < Htotal) THEN
Hcount <= Hcount + 1;
ELSE
Hcount <= "00000000000";
END IF;
IF (Hcount = Hsyncs) THEN
int_hs <= '0';
END IF;
IF (Hcount = Hsynce) THEN
int_hs <= '1';
IF (Vcount < Vtotal) THEN
Vcount <= Vcount + 1;
ELSE
Vcount <= "00000000000";
END IF;
END IF;
IF (Vcount = Vsysns) THEN
int_vs <= '0';
END IF;
IF (Vcount = Vsynce) THEN
int_vs <= '1';
END IF;
IF ((Hcount < Hactive) AND (Vcount < Vactive)) THEN
VGA_BLANK_N <= '1';
ELSE
VGA_BLANK_N <= '0';
END IF;
END IF;
END IF;
END PROCESS;
END Behavior; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
entity GPIO is
generic (BitWidth: integer);
port ( IO_sel: in std_logic;
IO: inout std_logic_vector (BitWidth-1 downto 0);
WrtData: in std_logic_vector (BitWidth-1 downto 0);
RdData: out std_logic_vector (BitWidth-1 downto 0)
);
end GPIO;
architecture behavioral of GPIO is
begin
IO_CONT:process(IO_sel, IO, WrtData)begin
if IO_sel = '0' then
IO <= (others => 'Z');
RdData <= IO;
else
IO <= WrtData;
end if;
end process;
end behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_ztex
-- File: ahb2mig_ztex.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus.
-------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <belousov.oleg@gmail.com>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_ztex is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
MEMCLK_PERIOD : integer := 5000
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem : in std_logic
);
end ;
architecture rtl of ahb2mig_ztex is
component mig_37
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
signal r, rin : reg_type;
signal i : mcb_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
MCB_inst : entity work.mig_37 generic map(
C3_RST_ACT_LOW => 1,
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_MEMCLK_PERIOD => MEMCLK_PERIOD
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_sys_clk => clk_mem,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error
);
end;
|
------------------------------------------------------------------------------
-- Stuff for handling the ZUnit configuration(s)
--
-- Project :
-- File : $Id: configPkg.vhd 218 2005-01-13 17:02:10Z plessl $
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/08
-- Last changed: $LastChangedDate: 2005-01-13 18:02:10 +0100 (Thu, 13 Jan 2005) $
------------------------------------------------------------------------------
-- This package provides a number of functions that convert the configuration
-- of the Zippy array from a human readable, hierarchical VHDL-record form
-- to a bitstring representation.
-- The configuration can also be transformed into a C header file. The data
-- from this header file is used to configure the zunit via the host interface.
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-08 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.txt_util.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.AuxPkg.all;
package ConfigPkg is
constant PE_CFGLEN : integer := procConfig_length;
constant RE_CFGLEN : integer := routConfig_length;
constant CELL_CFGLEN : integer := cellConfig_length;
constant ROW_CFGLEN : integer := rowConfig_length;
constant GRID_CFGLEN : integer := gridConfig_length;
constant PORT_CFGLEN : integer := ioportConfig_length;
constant INPDRV_CFGLEN : integer := inputDriverConfig_length;
constant OUTPDRV_CFGLEN : integer := outputDriverConfig_length;
constant INPORT_CFGLEN : integer := inportConfig_length;
constant OUTPORT_CFGLEN : integer := outportConfig_length;
constant MEM_CFGLEN : integer := memoryConfig_length;
constant ENGN_CFGLEN : integer := engineConfig_length;
constant NPARTS : integer := num_partitions(ENGN_CFGLEN, PARTWIDTH);
constant CELLROUTINGINPUTCONFIGREC_LEN : integer :=
N_LOCALCON + N_HBUSN + N_HBUSS + N_VBUSE;
subtype cfgPartType is std_logic_vector(PARTWIDTH-1 downto 0);
type cfgPartArray is array (NPARTS-1 downto 0) of cfgPartType;
subtype contextType is std_logic_vector(ENGN_CFGLEN-1 downto 0);
type contextArray is array (N_CONTEXTS-1 downto 0) of contextType;
type contextPartArray is array (N_CONTEXTS-1 downto 0) of cfgPartArray;
-- initializes a procConfig record
function init_procConfig return procConfigRec;
-- initializes a routConfig record
function init_routConfig return routConfigRec;
-- initializes a cellConfig record
function init_cellConfig return cellConfigRec;
-- initializes a cellInputRec record
function init_cellInput return cellInputRec;
-- initializes a rowConfig array
function init_rowConfig return rowConfigArray;
-- initializes a rowInput array
function init_rowInput return rowInputArray;
-- initializes a gridConfig array
function init_gridConfig return gridConfigArray;
-- initializes an ioportConfig record
function init_ioportConfig return ioportConfigRec;
-- initializes an engineInportConfigArray
function init_inportConfig return engineInportConfigArray;
-- initializes an engineOutportConfigArray
function init_outportConfig return engineOutportConfigArray;
-- initializes an engineHBusNorthInputDriver array
function init_inputDriverConfig return engineHBusNorthInputDriverArray;
-- initializes an engineHBusNorthOutputDriver array
function init_outputDriverConfig return engineHBusNorthOutputDriverArray;
-- initializes an engineConfig record
function init_engineConfig return engineConfigRec;
-- converts a procConfig record to a vector
function to_procConfig_vec (Cfg : procConfigRec) return std_logic_vector;
-- converts a procConfig vector to a record
function to_procConfig_rec (CfgxD : std_logic_vector(PE_CFGLEN-1 downto 0))
return procConfigRec;
-- converts a routConfig record to a vector
function to_routConfig_vec (Cfg : routConfigRec) return std_logic_vector;
-- converts a routConfig vector to a record
function to_routConfig_rec (CfgxD : std_logic_vector(RE_CFGLEN-1 downto 0))
return routConfigRec;
-- converts a cellConfig record to a vector
function to_cellConfig_vec (Cfg : cellConfigRec) return std_logic_vector;
-- converts a cellConfig vector to a record
function to_cellConfig_rec (CfgxD : std_logic_vector(CELL_CFGLEN-1 downto 0))
return cellConfigRec;
-- converts a rowConfig array to a vector
function to_rowConfig_vec (Cfg : rowConfigArray) return std_logic_vector;
-- converts a rowConfig vector to an array
function to_rowConfig_arr (CfgxD : std_logic_vector(ROW_CFGLEN-1 downto 0))
return rowConfigArray;
-- converts a gridConfig array to a vector
function to_gridConfig_vec (Cfg : gridConfigArray) return std_logic_vector;
-- converts a gridConfig vector to an array
function to_gridConfig_arr (CfgxD : std_logic_vector(GRID_CFGLEN-1 downto 0))
return gridConfigArray;
-- convert a inputDriverConfig array to a vector
function to_inputDriverConfig_vec (Cfg : engineHBusNorthInputDriverArray)
return std_logic_vector;
-- convert a inputDriverConfig vector to an array
function to_inputDriverConfig_arr (
vec : std_logic_vector(INPDRV_CFGLEN-1 downto 0))
return engineHBusNorthInputDriverArray;
-- convert a outputDriverConfig array to a vector
function to_outputDriverConfig_vec (Cfg : engineHBusNorthOutputDriverArray)
return std_logic_vector;
-- convert a outputDriverConfig vector to an array
function to_outputDriverConfig_arr (
vec : std_logic_vector(INPDRV_CFGLEN-1 downto 0))
return engineHBusNorthOutputDriverArray;
-- converts an ioportConfig record to a vector
function to_ioportConfig_vec (Cfg : ioportConfigRec) return std_logic_vector;
-- converts an ioportConfig vector to a record
function to_ioportConfig_rec (
CfgxD : std_logic_vector(PORT_CFGLEN-1 downto 0))
return ioportConfigRec;
-- convert inportConfig vector to an array of records
function to_inportConfig_arr (
CfgxD : std_logic_vector(INPORT_CFGLEN-1 downto 0))
return engineInportConfigArray;
-- convert inportConfig array of records to vector
function to_inportConfig_vec (Cfg : engineInportConfigArray)
return std_logic_vector;
-- convert outportConfig vector to an array of records
function to_outportConfig_arr (
CfgxD : std_logic_vector(OUTPORT_CFGLEN-1 downto 0))
return engineOutportConfigArray;
-- convert outportConfig array of records to vector
function to_outportConfig_vec (Cfg : engineOutportConfigArray)
return std_logic_vector;
-----------------------------------------------------------------------------
-- memory configuration handling functions
-----------------------------------------------------------------------------
function init_memoryConfig return engineMemoryConfigArray;
function to_memoryConfig_vec (Cfg : engineMemoryConfigArray)
return std_logic_vector;
function to_memoryConfig_arr (CfgxD : std_logic_vector(MEM_CFGLEN-1 downto 0))
return engineMemoryConfigArray;
-- converts an engineConfig record to a vector
function to_engineConfig_vec (Cfg : engineConfigRec) return std_logic_vector;
-- converts an engineConfig vector to a record
function to_engineConfig_rec (
CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0))
return engineConfigRec;
-- partitions the configuration into partitions of equal width
function partition_config (
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0))
return cfgPartArray;
-- generate .h file for coupled simulation
procedure gen_cfghfile (file hfile : text; CfgArr : in cfgPartArray);
-- generate .h file for coupled simulation (multi-context)
procedure gen_contexthfile2 (file hfile : text; cpArr : in contextPartArray);
end ConfigPkg;
------------------------------------------------------------------------------
-- BODY
------------------------------------------------------------------------------
package body ConfigPkg is
-- initializes a procConfig record
function init_procConfig return procConfigRec is
variable Cfg : procConfigRec;
begin
Cfg.OpMuxS := (others => I_NOREG);
Cfg.OpCtxRegSelxS := (others => (others => '0'));
Cfg.OutMuxS := O_NOREG;
Cfg.OutCtxRegSelxS := (others => '0');
Cfg.AluOpxS := ALU_OP_PASS0;
Cfg.ConstOpxD := (others => '0');
return Cfg;
end init_procConfig;
-- initializes a routConfig record
function init_routConfig return routConfigRec is
variable Cfg : routConfigRec;
begin
for inp in Cfg.i'range loop
Cfg.i(inp).LocalxE := (others => '0');
Cfg.i(inp).HBusNxE := (others => '0');
Cfg.i(inp).HBusSxE := (others => '0');
Cfg.i(inp).VBusExE := (others => '0');
end loop; -- inp
Cfg.o.HBusNxE := (others => '0');
Cfg.o.HBusSxE := (others => '0');
Cfg.o.VBusExE := (others => '0');
return Cfg;
end init_routConfig;
-- initializes a cellConfig record
function init_cellConfig return CellConfigRec is
variable Cfg : CellConfigRec;
begin
Cfg.procConf := init_procConfig;
Cfg.routConf := init_routConfig;
return Cfg;
end init_cellConfig;
-- initializes a cellInputRec record
function init_cellInput return cellInputRec is
variable Inp : cellInputRec;
begin
Inp.LocalxDI := (others => (others => '0'));
Inp.HBusNxDI := (others => (others => '0'));
Inp.HBusSxDI := (others => (others => '0'));
Inp.VBusExDI := (others => (others => '0'));
return Inp;
end init_cellInput;
-- initializes a rowConfig array
function init_rowConfig return rowConfigArray is
variable Cfg : rowConfigArray;
begin
for i in Cfg'range loop
Cfg(i) := init_cellConfig;
end loop; -- i
return Cfg;
end init_rowConfig;
-- initializes a rowInput array
function init_rowInput return rowInputArray is
variable Inp : rowInputArray;
begin
for i in Inp'range loop
Inp(i) := init_cellInput;
end loop; -- i
return Inp;
end init_rowInput;
-- initializes a gridConfig array
function init_gridConfig return gridConfigArray is
variable Cfg : gridConfigArray;
begin
for i in Cfg'range loop
Cfg(i) := init_rowConfig;
end loop; -- i
return Cfg;
end init_gridConfig;
-- initializes an ioportConfig record
function init_ioportConfig return ioportConfigRec is
variable Cfg : ioportConfigRec;
begin
Cfg.Cmp0MuxS := '0';
Cfg.Cmp0ModusxS := '0';
Cfg.Cmp0ConstxD := (others => '0');
Cfg.Cmp1MuxS := '0';
Cfg.Cmp1ModusxS := '0';
Cfg.Cmp1ConstxD := (others => '0');
Cfg.LUT4FunctxD := (others => '0');
return Cfg;
end init_ioportConfig;
-- initializes an engineInportConfigArray
function init_inportConfig return engineInportConfigArray is
variable Cfg : engineInportConfigArray;
begin
for inp in Cfg'range loop
Cfg(inp) := init_ioportConfig;
end loop; -- inp
return Cfg;
end init_inportConfig;
-- initializes an engineOutportConfigArray
function init_outportConfig return engineOutportConfigArray is
variable Cfg : engineOutportConfigArray;
begin
for outp in Cfg'range loop
Cfg(outp) := init_ioportConfig;
end loop; -- outp
return Cfg;
end init_outportConfig;
-----------------------------------------------------------------------------
-- functions for memory configuration handling
-----------------------------------------------------------------------------
-- initializes a memoryConfigArray
function init_memoryConfig return engineMemoryConfigArray is
variable arr : engineMemoryConfigArray;
begin
arr := (others => (others => (others => '0')));
return arr;
end init_memoryConfig;
function to_memoryConfig_vec (Cfg : engineMemoryConfigArray)
return std_logic_vector is
variable vec : std_logic_vector(MEM_CFGLEN-1 downto 0);
variable fromInd, toInd : integer;
constant SINGLEROMLEN : integer := N_MEMDEPTH*DATAWIDTH;
begin
for rom in Cfg'range loop
for i in Cfg(0)'range loop
fromInd := rom*SINGLEROMLEN + (i+1)*DATAWIDTH-1;
toInd := rom*SINGLEROMLEN + i*DATAWIDTH;
vec(fromInd downto toInd) := Cfg(rom)(i);
end loop;
end loop;
return vec;
end to_memoryConfig_vec;
function to_memoryConfig_arr (CfgxD : std_logic_vector(MEM_CFGLEN-1 downto 0))
return engineMemoryConfigArray is
variable Cfg : engineMemoryConfigArray;
variable fromInd, toInd : integer;
constant SINGLEROMLEN : integer := N_MEMDEPTH*DATAWIDTH;
begin
for rom in Cfg'range loop
for i in Cfg(0)'range loop
fromInd := rom*SINGLEROMLEN + (i+1)*DATAWIDTH-1;
toInd := rom*SINGLEROMLEN + i*DATAWIDTH;
Cfg(rom)(i) := CfgxD(fromInd downto toInd);
end loop;
end loop;
return Cfg;
end to_memoryConfig_arr;
-------------------------------------------------------------------------------
-- input and output driver configuration functions
-------------------------------------------------------------------------------
function init_inputDriverConfig return engineHBusNorthInputDriverArray is
variable Cfg : engineHBusNorthInputDriverArray;
begin
Cfg := (others => (others => (others => '0')));
return Cfg;
end init_inputDriverConfig;
function init_outputDriverConfig return engineHBusNorthOutputDriverArray is
variable Cfg : engineHBusNorthOutputDriverArray;
begin
Cfg := (others => (others => (others => '0')));
return Cfg;
end init_outputDriverConfig;
function to_inputDriverConfig_vec (Cfg : engineHBusNorthInputDriverArray)
return std_logic_vector is
variable vec : std_logic_vector(INPDRV_CFGLEN-1 downto 0);
begin
for inp in Cfg'range loop
for row in Cfg(0)'range loop
for p in Cfg(0)(0)'range loop
vec( (inp*Cfg(0)'length + row)*Cfg(0)(0)'length + p) := Cfg(inp)(row)(p);
end loop; -- p
end loop; -- row
end loop; -- inp
return vec;
end to_inputDriverConfig_vec;
function to_outputDriverConfig_vec (Cfg : engineHBusNorthOutputDriverArray)
return std_logic_vector is
variable vec : std_logic_vector(OUTPDRV_CFGLEN-1 downto 0);
begin
for outp in Cfg'range loop
for row in Cfg(0)'range loop
for p in Cfg(0)(0)'range loop
vec( (outp*Cfg(0)'length + row)*Cfg(0)(0)'length + p) := Cfg(outp)(row)(p);
end loop; -- p
end loop; -- row
end loop; -- outp
return vec;
end to_outputDriverConfig_vec;
function to_inputDriverConfig_arr (
vec : std_logic_vector(INPDRV_CFGLEN-1 downto 0))
return engineHBusNorthInputDriverArray is
variable Cfg : engineHBusNorthInputDriverArray;
begin
for inp in Cfg'range loop
for row in Cfg(0)'range loop
for p in Cfg(0)(0)'range loop
Cfg(inp)(row)(p) := vec( (inp*Cfg(0)'length + row)*Cfg(0)(0)'length + p);
end loop; -- p
end loop; -- row
end loop; -- inp
return Cfg;
end to_inputDriverConfig_arr;
function to_outputDriverConfig_arr (
vec : std_logic_vector(INPDRV_CFGLEN-1 downto 0))
return engineHBusNorthOutputDriverArray is
variable Cfg : engineHBusNorthOutputDriverArray;
begin
for outp in Cfg'range loop
for row in Cfg(0)'range loop
for p in Cfg(0)(0)'range loop
Cfg(outp)(row)(p) := vec( (outp*Cfg(0)'length + row)*Cfg(0)(0)'length + p);
end loop; -- p
end loop; -- row
end loop; -- outp
return Cfg;
end to_outputDriverConfig_arr;
-- initializes an engineConfig record
function init_engineConfig return engineConfigRec is
variable Cfg : engineConfigRec;
begin
Cfg.gridConf := init_gridConfig;
Cfg.inputDriverConf := init_inputDriverConfig;
Cfg.outputDriverConf := init_outputDriverConfig;
Cfg.inportConf := init_inportConfig;
Cfg.outportConf := init_outportConfig;
Cfg.memoryConf := init_memoryConfig;
return Cfg;
end init_engineConfig;
-- type procConfigRec is
-- record
-- OpMuxS : procInputMuxArray; -- PE_CFGLEN-1 downto bnd0
-- OpCtxRegSelxS : procInputCtxRegSelectArray; -- bnd0-1 downto bnd1
-- OutMuxS : procOutputMux; -- bnd1-1 downto bnd2
-- OutCtxRegSelxS : procOutputCtxRegSelect; -- bnd2-1 downto bnd3
-- AluOpxS : aluOpType; -- bnd3-1 downto bnd4
-- ConstOpxD : data_word; -- bnd4-1 downto 0
-- end record;
-- converts a procConfig record to a vector
function to_procConfig_vec (Cfg : procConfigRec) return std_logic_vector is
variable vec : std_logic_vector(PE_CFGLEN-1 downto 0);
constant bnd0 : natural := PE_CFGLEN - Cfg.OpMuxS'length*Cfg.OpMuxS(0)'length;
constant bnd1 : natural := bnd0 - Cfg.OpCtxRegSelxS'length*Cfg.OpCtxRegSelxS(0)'length;
constant bnd2 : natural := bnd1 - Cfg.OutMuxS'length;
constant bnd3 : natural := bnd2 - Cfg.OutCtxRegSelxS'length;
constant bnd4 : natural := bnd3 - ALUOPWIDTH;
begin
for inp in Cfg.OpMuxS'range loop
vec((inp+1)*Cfg.OpMuxS(0)'length-1+bnd0 downto
inp*Cfg.OpMuxS(0)'length+bnd0) := Cfg.OpMuxS(inp);
end loop;
for inp in Cfg.OpMuxS'range loop
vec((inp+1)*Cfg.OpCtxRegSelxS(0)'length-1+bnd1
downto inp*Cfg.OpCtxRegSelxS(0)'length+bnd1) := Cfg.OpCtxRegSelxS(inp);
end loop; -- inp
vec(bnd1-1 downto bnd2) := Cfg.OutMuxS;
vec(bnd2-1 downto bnd3) := Cfg.OutCtxRegSelxS;
vec(bnd3-1 downto bnd4) := std_logic_vector(to_unsigned(Cfg.AluOpxS, ALUOPWIDTH));
vec(bnd4-1 downto 0) := Cfg.ConstOpxD;
return vec;
end to_procConfig_vec;
-- converts a procConfig vector to a record
function to_procConfig_rec (CfgxD : std_logic_vector(PE_CFGLEN-1 downto 0))
return procConfigRec
is
variable rec : procConfigRec;
constant bnd0 : natural := PE_CFGLEN - rec.OpMuxS'length*rec.OpMuxS(0)'length;
constant bnd1 : natural := bnd0 - rec.OpCtxRegSelxS'length*rec.OpCtxRegSelxS(0)'length;
constant bnd2 : natural := bnd1 - rec.OutMuxS'length;
constant bnd3 : natural := bnd2 - rec.OutCtxRegSelxS'length;
constant bnd4 : natural := bnd3 - ALUOPWIDTH;
begin
for inp in rec.OpMuxS'range loop
rec.OpMuxS(inp) := CfgxD((inp+1)*rec.OpMuxS(0)'length-1+bnd0 downto
inp*rec.OpMuxS(0)'length+bnd0);
end loop; -- inp
for inp in rec.OpCtxRegSelxS'range loop
rec.OpCtxRegSelxS(inp) := CfgxD((inp+1)*rec.OpCtxRegSelxS(0)'length-1+bnd1
downto inp*rec.OpCtxRegSelxS(0)'length+bnd1);
end loop; -- inp
rec.OutMuxS := CfgxD(bnd1-1 downto bnd2);
rec.OutCtxRegSelxS := CfgxD(bnd2-1 downto bnd3);
rec.AluOpxS := to_integer(unsigned(CfgxD(bnd3-1 downto bnd4)));
rec.ConstOpxD := CfgxD(bnd4-1 downto 0);
return rec;
end to_procConfig_rec;
-- converts a routConfig record to a vector
function to_routConfig_vec (Cfg : routConfigRec) return std_logic_vector is
constant OUTPLEN : integer := Cfg.o.HBusNxE'length +
Cfg.o.HBusSxE'length +
Cfg.o.VBusExE'length;
constant INPLEN : integer := Cfg.i'length*(Cfg.i(0).LocalxE'length +
Cfg.i(0).HBusNxE'length +
Cfg.i(0).HBusSxE'length +
Cfg.i(0).VBusExE'length);
variable vec_inp : std_logic_vector(INPLEN-1 downto 0);
variable vec_outp : std_logic_vector(OUTPLEN-1 downto 0);
variable vec : std_logic_vector(RE_CFGLEN-1 downto 0);
variable start, bnd0, bnd1, bnd2, bnd3, bnd4, bnd5, bnd6 : integer;
begin
-- convert configuration for inputs to vector
for inp in Cfg.i'range loop
start := (inp+1)*CELLROUTINGINPUTCONFIGREC_LEN;
bnd0 := start - N_LOCALCON;
bnd1 := bnd0 - N_HBUSN;
bnd2 := bnd1 - N_HBUSS;
bnd3 := bnd2 - N_VBUSE;
vec_inp(start-1 downto bnd0) := Cfg.i(inp).LocalxE;
vec_inp(bnd0-1 downto bnd1) := Cfg.i(inp).HBusNxE;
vec_inp(bnd1-1 downto bnd2) := Cfg.i(inp).HBusSxE;
vec_inp(bnd2-1 downto bnd3) := Cfg.i(inp).VBusExE;
end loop; -- inp
-- convert configuration for output to vector
bnd4 := OUTPLEN - N_HBUSN;
bnd5 := bnd4 - N_HBUSS;
bnd6 := bnd5 - N_VBUSE;
vec_outp(OUTPLEN-1 downto bnd4) := Cfg.o.HBusNxE;
vec_outp(bnd4-1 downto bnd5) := Cfg.o.HBusSxE;
vec_outp(bnd5-1 downto bnd6) := Cfg.o.VBusExE;
vec := vec_inp & vec_outp;
return vec;
end to_routConfig_vec;
-- converts a routConfig vector to a record
function to_routConfig_rec (CfgxD : std_logic_vector(RE_CFGLEN-1 downto 0))
return routConfigRec
is
variable CfgRec : routConfigRec;
constant OUTPLEN : integer := CfgRec.o.HBusNxE'length +
CfgRec.o.HBusSxE'length +
CfgRec.o.VBusExE'length;
constant INPLEN : integer := CfgRec.i'length*(CfgRec.i(0).LocalxE'length +
CfgRec.i(0).HBusNxE'length +
CfgRec.i(0).HBusSxE'length +
CfgRec.i(0).VBusExE'length);
variable CfgInpxD : std_logic_vector(INPLEN-1 downto 0);
variable CfgOutpxD : std_logic_vector(OUTPLEN-1 downto 0);
variable start, bnd0, bnd1, bnd2, bnd3, bnd4, bnd5, bnd6 : integer;
begin
CfgInpxD := CfgxD(RE_CFGLEN-1 downto RE_CFGLEN-INPLEN);
CfgOutpxD := CfgxD(OUTPLEN-1 downto 0);
-- convert configuration for inputs to record entries
for inp in CfgRec.i'range loop
start := (inp+1)*CELLROUTINGINPUTCONFIGREC_LEN;
bnd0 := start - N_LOCALCON;
bnd1 := bnd0 - N_HBUSN;
bnd2 := bnd1 - N_HBUSS;
bnd3 := bnd2 - N_VBUSE;
CfgRec.i(inp).LocalxE := CfgInpxD(start-1 downto bnd0);
CfgRec.i(inp).HBusNxE := CfgInpxD(bnd0-1 downto bnd1);
CfgRec.i(inp).HBusSxE := CfgInpxD(bnd1-1 downto bnd2);
CfgRec.i(inp).VBusExE := CfgInpxD(bnd2-1 downto bnd3);
end loop; -- inp
-- convert configuration for outputs to record entry
bnd4 := OUTPLEN-N_HBUSN;
bnd5 := bnd4-N_HBUSS;
bnd6 := bnd5-N_VBUSE;
CfgRec.o.HBusNxE := CfgOutpxD(OUTPLEN-1 downto bnd4);
CfgRec.o.HBusSxE := CfgOutpxD(bnd4-1 downto bnd5);
CfgRec.o.VBusExE := CfgOutpxD(bnd5-1 downto bnd6);
return CfgRec;
end to_routConfig_rec;
-- converts a cellConfig record to a vector
function to_cellConfig_vec (Cfg : cellConfigRec) return std_logic_vector is
variable vec : std_logic_vector(CELL_CFGLEN-1 downto 0);
begin
vec := to_procConfig_vec(Cfg.procConf) & to_routConfig_vec(Cfg.routConf);
return vec;
end to_cellConfig_vec;
-- converts a cellConfig vector to a record
function to_cellConfig_rec (CfgxD : std_logic_vector(CELL_CFGLEN-1 downto 0))
return cellConfigRec
is
variable rec : cellConfigRec;
begin
rec.procConf := to_procConfig_rec(CfgxD(CELL_CFGLEN-1 downto RE_CFGLEN));
rec.routConf := to_routConfig_rec(CfgxD(RE_CFGLEN-1 downto 0));
return rec;
end to_cellConfig_rec;
-- converts a rowConfig array to a vector
function to_rowConfig_vec (Cfg : rowConfigArray) return std_logic_vector is
variable vec : std_logic_vector(ROW_CFGLEN-1 downto 0);
begin
for i in Cfg'range loop
vec(CELL_CFGLEN*(i+1)-1 downto CELL_CFGLEN*i) :=
to_cellConfig_vec(Cfg(i));
end loop; -- i
return vec;
end to_rowConfig_vec;
-- converts a rowConfig vector to an array
function to_rowConfig_arr (CfgxD : std_logic_vector(ROW_CFGLEN-1 downto 0))
return rowConfigArray
is
variable arr : rowConfigArray;
begin
for i in arr'range loop
arr(i) :=
to_cellConfig_rec(CfgxD(CELL_CFGLEN*(i+1)-1 downto CELL_CFGLEN*i));
end loop; -- i
return arr;
end to_rowConfig_arr;
-- converts a gridConfig array to a vector
function to_gridConfig_vec (Cfg : gridConfigArray) return std_logic_vector is
variable vec : std_logic_vector(GRID_CFGLEN-1 downto 0);
begin
for i in Cfg'range loop
vec(ROW_CFGLEN*(i+1)-1 downto ROW_CFGLEN*i) := to_rowConfig_vec(Cfg(i));
end loop; -- i
return vec;
end to_gridConfig_vec;
-- converts a gridConfig vector to an array
function to_gridConfig_arr (CfgxD : std_logic_vector(GRID_CFGLEN-1 downto 0))
return gridConfigArray
is
variable arr : gridConfigArray;
begin
for i in arr'range loop
arr(i) :=
to_rowConfig_arr(CfgxD(ROW_CFGLEN*(i+1)-1 downto ROW_CFGLEN*i));
end loop; -- i
return arr;
end to_gridConfig_arr;
-- converts an ioportConfig record to a vector
function to_ioportConfig_vec (Cfg : ioportConfigRec) return std_logic_vector
is
variable vec : std_logic_vector(PORT_CFGLEN-1 downto 0);
begin
vec := Cfg.LUT4FunctxD & Cfg.Cmp0MuxS & Cfg.Cmp1MuxS & Cfg.Cmp0ModusxS &
Cfg.Cmp1ModusxS & Cfg.Cmp0ConstxD & Cfg.Cmp1ConstxD;
return vec;
end to_ioportConfig_vec;
-- converts an ioportConfig vector to a record
function to_ioportConfig_rec (
CfgxD : std_logic_vector(PORT_CFGLEN-1 downto 0))
return ioportConfigRec
is
variable rec : ioportConfigRec;
variable clen : integer := rec.Cmp0ConstxD'length; -- constant length
begin
rec.LUT4FunctxD := CfgxD(PORT_CFGLEN-1 downto PORT_CFGLEN-16);
rec.Cmp0MuxS := CfgxD(PORT_CFGLEN-17);
rec.Cmp1MuxS := CfgxD(PORT_CFGLEN-18);
rec.Cmp0ModusxS := CfgxD(PORT_CFGLEN-19);
rec.Cmp1ModusxS := CfgxD(PORT_CFGLEN-20);
rec.Cmp0ConstxD := CfgxD(2*clen-1 downto clen);
rec.Cmp1ConstxD := CfgxD(clen-1 downto 0);
return rec;
end to_ioportConfig_rec;
function to_inportConfig_vec (Cfg : engineInportConfigArray)
return std_logic_vector
is
variable vec : std_logic_vector(INPORT_CFGLEN-1 downto 0);
begin
for inp in Cfg'range loop
vec((inp+1)*PORT_CFGLEN-1 downto inp*PORT_CFGLEN) :=
to_ioportConfig_vec(Cfg(inp));
end loop; -- inp
return vec;
end to_inportConfig_vec;
function to_outportConfig_vec (Cfg : engineOutportConfigArray)
return std_logic_vector
is
variable vec : std_logic_vector(OUTPORT_CFGLEN-1 downto 0);
begin
for outp in Cfg'range loop
vec((outp+1)*PORT_CFGLEN-1 downto outp*PORT_CFGLEN) :=
to_ioportConfig_vec(Cfg(outp));
end loop; -- outp
return vec;
end to_outportConfig_vec;
--FIXME
--Check code for splitting up vector into chunks of equal size
function to_outportConfig_arr (
CfgxD : std_logic_vector(OUTPORT_CFGLEN-1 downto 0))
return engineOutportConfigArray
is
variable arr : engineOutportConfigArray;
begin
for outp in arr'range loop
arr(outp) := to_ioportConfig_rec(CfgxD((outp+1)*PORT_CFGLEN-1 downto
outp*PORT_CFGLEN));
end loop; -- outp
return arr;
end to_outportConfig_arr;
function to_inportConfig_arr (
CfgxD : std_logic_vector(INPORT_CFGLEN-1 downto 0))
return engineInportConfigArray
is
variable arr : engineInportConfigArray;
begin
for inp in arr'range loop
arr(inp) := to_ioportConfig_rec(CfgxD((inp+1)*PORT_CFGLEN-1 downto
inp*PORT_CFGLEN));
end loop; -- inp
return arr;
end to_inportConfig_arr;
-- converts an engineConfig record to a vector
function to_engineConfig_vec (Cfg : engineConfigRec) return std_logic_vector
is
variable vec : std_logic_vector(ENGN_CFGLEN-1 downto 0);
begin
vec := to_gridConfig_vec(Cfg.gridConf) &
to_inputDriverConfig_vec(Cfg.inputDriverConf) &
to_outputDriverConfig_vec(Cfg.outputDriverConf) &
to_inportConfig_vec(Cfg.inportConf) &
to_outportConfig_vec(Cfg.outportConf) &
to_memoryConfig_vec(Cfg.memoryConf);
return vec;
end to_engineConfig_vec;
-- converts an engineConfig vector to a record
function to_engineConfig_rec (
CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0))
return engineConfigRec
is
variable rec : engineConfigRec;
-- note: order is from last engineConfigRec entry to first
variable bnd0 : integer := MEM_CFGLEN;
variable bnd1 : integer := bnd0 + OUTPORT_CFGLEN;
variable bnd2 : integer := bnd1 + INPORT_CFGLEN;
variable bnd3 : integer := bnd2 + OUTPDRV_CFGLEN;
variable bnd4 : integer := bnd3 + INPDRV_CFGLEN;
begin
rec.gridConf := to_gridConfig_arr(CfgxD(ENGN_CFGLEN-1 downto bnd4));
rec.inputDriverConf := to_inputDriverConfig_arr(CfgxD(bnd4-1 downto bnd3));
rec.outputDriverConf := to_outputDriverConfig_arr(CfgxD(bnd3-1 downto bnd2));
rec.inportConf := to_inportConfig_arr(CfgxD(bnd2-1 downto bnd1));
rec.outportConf := to_outportConfig_arr(CfgxD(bnd1-1 downto bnd0));
rec.memoryConf := to_memoryConfig_arr(CfgxD(bnd0-1 downto 0));
return rec;
end to_engineConfig_rec;
-- partitions the configuration into partitions of equal widths
function partition_config (
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0))
return cfgPartArray
is
variable parts : cfgPartArray;
variable hi : natural;
variable lo : natural;
function std_resize (arg : std_logic_vector; new_size : natural)
return std_logic_vector
is
variable result : std_logic_vector(new_size downto 0) := (others => '0');
begin
return std_logic_vector(resize(unsigned(arg), new_size));
end std_resize;
begin -- partition_config
for i in parts'low to parts'high-1 loop
lo := PARTWIDTH * i;
hi := lo + PARTWIDTH - 1;
parts(i) := CfgxD(hi downto lo);
end loop; -- i
-- special treatment for the highest, probably shorter partition
lo := parts'high * PARTWIDTH;
hi := CfgxD'high;
parts(parts'high) := std_resize(CfgxD(hi downto lo), PARTWIDTH);
return parts;
end partition_config;
-- generate .h file for coupled simulation
procedure gen_cfghfile (file hfile : text; CfgArr : in cfgPartArray)
is
variable buf : line;
begin -- gen_cfghfile
-- comment
write(buf, string'("/* ZUnit configuration partitions "));
write(buf, string'("(automatically generated) */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- PARTWIDTH define
write(buf, string'("#define PARTWIDTH "));
write(buf, PARTWIDTH);
write(buf, string'(" /* partition width (bits) */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- NCFGPARTS define
write(buf, string'("#define NCFGPARTS "));
write(buf, CfgArr'length);
write(buf, string'(" /* no. of partitions */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- config. array
write(buf, string'("unsigned int config[NCFGPARTS] = {"));
writeline(hfile, buf);
for i in CfgArr'low to CfgArr'high loop
write(buf, string'(" 0X"));
hwrite(buf, std_logic_vector(CfgArr(i)));
if i < CfgArr'high then
write(buf, string'(","));
else
write(buf, string'(" "));
end if;
write(buf, string'(" /* "));
write(buf, CfgArr(i));
write(buf, string'("b, "));
write(buf, to_integer(unsigned(CfgArr(i))), right, 11);
write(buf, string'("d */"));
writeline(hfile, buf);
end loop; -- i
write(buf, string'(" };"));
writeline(hfile, buf);
end gen_cfghfile;
procedure gen_contexthfile2 (file hfile : text; cpArr : in contextPartArray)
is
variable buf : line;
variable cp : cfgPartArray;
begin -- gen_contexthfile2
-- comment
write(buf, string'("/* ZUnit multi-context configuration partitions "));
write(buf, string'("(automatically generated) */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- NCONTEXTS define
write(buf, string'("#define NCONTEXTS "));
write(buf, N_CONTEXTS);
write(buf, string'(" /* no. of contexts */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- PARTWIDTH define
write(buf, string'("#define PARTWIDTH "));
write(buf, PARTWIDTH);
write(buf, string'(" /* partition width (bits) */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- NCFGPARTS define
write(buf, string'("#define NCFGPARTS "));
write(buf, cp'length);
write(buf, string'(" /* no. of partitions */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- contexts
write(buf, string'("unsigned int contextdata"));
write(buf, string'("[NCONTEXTS][NCFGPARTS] = {"));
writeline(hfile, buf);
for c in 0 to N_CONTEXTS-1 loop
cp := cpArr(c);
write(buf, string'(" /* context "));
write(buf, c);
write(buf, string'(" */"));
writeline(hfile, buf);
write(buf, string'(" {"));
writeline(hfile, buf);
for i in cp'low to cp'high loop
write(buf, string'(" 0X"));
hwrite(buf, std_logic_vector(cp(i)));
if i < cp'high then
write(buf, string'(","));
else
write(buf, string'(" "));
end if;
write(buf, string'(" /* "));
write(buf, cp(i));
write(buf, string'("b, "));
write(buf, to_integer(unsigned(cp(i))), right, 11);
write(buf, string'("d */"));
writeline(hfile, buf);
end loop; -- i
write(buf, string'(" }"));
if c < N_CONTEXTS-1 then
write(buf, string'(","));
end if;
writeline(hfile, buf);
end loop; -- c
write(buf, string'("};"));
writeline(hfile, buf);
end gen_contexthfile2;
end ConfigPkg;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNGITJD4MB is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000011111111";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNGITJD4MB is
Begin
-- Constant
output <= "000000000000000011111111";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNGITJD4MB is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000011111111";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNGITJD4MB is
Begin
-- Constant
output <= "000000000000000011111111";
end architecture; |
--------------------------------------------------------------------------------
-- PS2 Keyboard Controller --
--------------------------------------------------------------------------------
-- The controller does not distinguish extended and normal keys. Most of the --
-- practically relevant keys are without ambiguity. The controller ignores --
-- all unmapped keys (see ascii.vhd). --
-- --
-- REFERENCES --
-- --
-- [1] Chu Pong P., FPGA Prototyping By VHDL Examples, --
-- John Wiley & Sons Inc., Hoboken, New Jersy, 2008, --
-- ISBN: 978-0470185315 --
-- --
-- [2] Z80 System On A Chip --
-- <http://www.opencores.org/?do=project&who=z80soc> --
-- [3] Keyboard Scancode Table --
-- <http://www.computer-engineering.org/ps2keyboard/scancodes2.html> --
-- [4] PS2 Protocol --
-- <http://pcbheaven.com/wikipages/The_PS2_protocol/> --
-- --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iwb.all;
package ikeyb is
component keyb is
port(
si : in slave_in_t;
so : out slave_out_t;
-- Non-Wishbone Signals
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
intr : out std_logic
);
end component;
end ikeyb; |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: read_data_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity read_data_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(13-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(13-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(13-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(13-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(256-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(13-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end read_data_fifo_top_wrapper;
architecture xilinx of read_data_fifo_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component read_data_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : read_data_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-- $Id: sn_4x7segctl.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_4x7segctl - syn
-- Description: Quad 7 segment display controller (for s3board and nexys2/3)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.2.1 now numeric_std clean
-- 2011-07-30 400 1.2 digit dark in last quarter (not 16 clocks)
-- 2011-07-08 390 1.1.2 renamed from s3_dispdrv
-- 2010-04-17 278 1.1.1 renamed from dispdrv
-- 2010-03-29 272 1.1 add all ANO off time to allow to driver turn-off
-- delay and to avoid cross talk between digits
-- 2007-12-16 101 1.0.1 use _N for active low
-- 2007-09-16 83 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity sn_4x7segctl is -- Quad 7 segment display controller
generic (
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv16; -- data
DP : in slv4; -- decimal points
ANO_N : out slv4; -- anodes (act.low)
SEG_N : out slv8 -- segements (act.low)
);
end sn_4x7segctl;
architecture syn of sn_4x7segctl is
type regs_type is record
cdiv : slv(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv2; -- digit counter
end record regs_type;
constant regs_init : regs_type := (
slv(to_unsigned(0,CDWIDTH)),
(others=>'0')
);
type hex2segtbl_type is array (0 to 15) of slv7;
constant hex2segtbl : hex2segtbl_type :=
("0111111", -- 0: "0000"
"0000110", -- 1: "0001"
"1011011", -- 2: "0010"
"1001111", -- 3: "0011"
"1100110", -- 4: "0100"
"1101101", -- 5: "0101"
"1111101", -- 6: "0110"
"0000111", -- 7: "0111"
"1111111", -- 8: "1000"
"1101111", -- 9: "1001"
"1110111", -- a: "1010"
"1111100", -- b: "1011"
"0111001", -- c: "1100"
"1011110", -- d: "1101"
"1111001", -- e: "1110"
"1110001" -- f: "1111"
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert CDWIDTH >= 5
report "assert(CDWIDTH >= 5): CDWIDTH too small"
severity FAILURE;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, DIN, DP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable cano : slv4 := "0000";
variable chex : slv4 := "0000";
variable cdp : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
n.cdiv := slv(unsigned(r.cdiv) - 1);
if unsigned(r.cdiv) = 0 then
n.dcnt := slv(unsigned(r.dcnt) + 1);
end if;
chex := "0000";
cdp := '0';
case r.dcnt is
when "00" => chex := DIN( 3 downto 0); cdp := DP(0);
when "01" => chex := DIN( 7 downto 4); cdp := DP(1);
when "10" => chex := DIN(11 downto 8); cdp := DP(2);
when "11" => chex := DIN(15 downto 12); cdp := DP(3);
when others => chex := "----"; cdp := '-';
end case;
-- the logic below ensures that the anode PNP driver transistor is switched
-- off in the last quarter of the digit cycle.This prevents 'cross talk'
-- between digits due to transistor turn off delays.
-- For a nexys2 board at 50 MHz observed:
-- no or 4 cycles gap well visible cross talk
-- with 8 cycles still some weak cross talk
-- with 16 cycles none is visible.
-- --> The turn-off delay of the anode driver PNP's this therefore
-- larger 160 ns and below 320 ns.
-- As consquence CDWIDTH should be at least 6 for 50 MHz and 7 for 100 MHz.
cano := "1111";
if r.cdiv(CDWIDTH-1 downto CDWIDTH-2) /= "00" then
cano(to_integer(unsigned(r.dcnt))) := '0';
end if;
N_REGS <= n;
ANO_N <= cano;
SEG_N <= not (cdp & hex2segtbl(to_integer(unsigned(chex))));
end process proc_next;
end syn;
|
-- $Id: sn_4x7segctl.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_4x7segctl - syn
-- Description: Quad 7 segment display controller (for s3board and nexys2/3)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.2.1 now numeric_std clean
-- 2011-07-30 400 1.2 digit dark in last quarter (not 16 clocks)
-- 2011-07-08 390 1.1.2 renamed from s3_dispdrv
-- 2010-04-17 278 1.1.1 renamed from dispdrv
-- 2010-03-29 272 1.1 add all ANO off time to allow to driver turn-off
-- delay and to avoid cross talk between digits
-- 2007-12-16 101 1.0.1 use _N for active low
-- 2007-09-16 83 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity sn_4x7segctl is -- Quad 7 segment display controller
generic (
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv16; -- data
DP : in slv4; -- decimal points
ANO_N : out slv4; -- anodes (act.low)
SEG_N : out slv8 -- segements (act.low)
);
end sn_4x7segctl;
architecture syn of sn_4x7segctl is
type regs_type is record
cdiv : slv(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv2; -- digit counter
end record regs_type;
constant regs_init : regs_type := (
slv(to_unsigned(0,CDWIDTH)),
(others=>'0')
);
type hex2segtbl_type is array (0 to 15) of slv7;
constant hex2segtbl : hex2segtbl_type :=
("0111111", -- 0: "0000"
"0000110", -- 1: "0001"
"1011011", -- 2: "0010"
"1001111", -- 3: "0011"
"1100110", -- 4: "0100"
"1101101", -- 5: "0101"
"1111101", -- 6: "0110"
"0000111", -- 7: "0111"
"1111111", -- 8: "1000"
"1101111", -- 9: "1001"
"1110111", -- a: "1010"
"1111100", -- b: "1011"
"0111001", -- c: "1100"
"1011110", -- d: "1101"
"1111001", -- e: "1110"
"1110001" -- f: "1111"
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert CDWIDTH >= 5
report "assert(CDWIDTH >= 5): CDWIDTH too small"
severity FAILURE;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, DIN, DP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable cano : slv4 := "0000";
variable chex : slv4 := "0000";
variable cdp : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
n.cdiv := slv(unsigned(r.cdiv) - 1);
if unsigned(r.cdiv) = 0 then
n.dcnt := slv(unsigned(r.dcnt) + 1);
end if;
chex := "0000";
cdp := '0';
case r.dcnt is
when "00" => chex := DIN( 3 downto 0); cdp := DP(0);
when "01" => chex := DIN( 7 downto 4); cdp := DP(1);
when "10" => chex := DIN(11 downto 8); cdp := DP(2);
when "11" => chex := DIN(15 downto 12); cdp := DP(3);
when others => chex := "----"; cdp := '-';
end case;
-- the logic below ensures that the anode PNP driver transistor is switched
-- off in the last quarter of the digit cycle.This prevents 'cross talk'
-- between digits due to transistor turn off delays.
-- For a nexys2 board at 50 MHz observed:
-- no or 4 cycles gap well visible cross talk
-- with 8 cycles still some weak cross talk
-- with 16 cycles none is visible.
-- --> The turn-off delay of the anode driver PNP's this therefore
-- larger 160 ns and below 320 ns.
-- As consquence CDWIDTH should be at least 6 for 50 MHz and 7 for 100 MHz.
cano := "1111";
if r.cdiv(CDWIDTH-1 downto CDWIDTH-2) /= "00" then
cano(to_integer(unsigned(r.dcnt))) := '0';
end if;
N_REGS <= n;
ANO_N <= cano;
SEG_N <= not (cdp & hex2segtbl(to_integer(unsigned(chex))));
end process proc_next;
end syn;
|
entity cover1 is
end entity;
architecture test of cover1 is
signal s : integer;
begin
process is
variable v : integer;
begin
v := 1;
s <= 2;
wait for 1 ns;
if s = 2 or s > 10 then
v := 3;
else
v := 2;
end if;
while v > 0 loop
if v mod 2 = 0 then
v := v - 1;
else
v := (v / 2) * 2;
end if;
end loop;
wait;
end process;
end architecture;
|
entity cover1 is
end entity;
architecture test of cover1 is
signal s : integer;
begin
process is
variable v : integer;
begin
v := 1;
s <= 2;
wait for 1 ns;
if s = 2 or s > 10 then
v := 3;
else
v := 2;
end if;
while v > 0 loop
if v mod 2 = 0 then
v := v - 1;
else
v := (v / 2) * 2;
end if;
end loop;
wait;
end process;
end architecture;
|
entity cover1 is
end entity;
architecture test of cover1 is
signal s : integer;
begin
process is
variable v : integer;
begin
v := 1;
s <= 2;
wait for 1 ns;
if s = 2 or s > 10 then
v := 3;
else
v := 2;
end if;
while v > 0 loop
if v mod 2 = 0 then
v := v - 1;
else
v := (v / 2) * 2;
end if;
end loop;
wait;
end process;
end architecture;
|
entity cover1 is
end entity;
architecture test of cover1 is
signal s : integer;
begin
process is
variable v : integer;
begin
v := 1;
s <= 2;
wait for 1 ns;
if s = 2 or s > 10 then
v := 3;
else
v := 2;
end if;
while v > 0 loop
if v mod 2 = 0 then
v := v - 1;
else
v := (v / 2) * 2;
end if;
end loop;
wait;
end process;
end architecture;
|
entity cover1 is
end entity;
architecture test of cover1 is
signal s : integer;
begin
process is
variable v : integer;
begin
v := 1;
s <= 2;
wait for 1 ns;
if s = 2 or s > 10 then
v := 3;
else
v := 2;
end if;
while v > 0 loop
if v mod 2 = 0 then
v := v - 1;
else
v := (v / 2) * 2;
end if;
end loop;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : eth_crc32.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-11-04
-- Last update: 2012-11-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-04 1.0 root Created
-- 经过测试没有问题！计算后输出到外面的crc值需要按照以太网的大小端模式发送才是正确的！
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY eth_crc32 IS
PORT (
iClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
iInit : IN STD_LOGIC;
iCalcEn : IN STD_LOGIC;
iData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
oCRC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oCRCErr : OUT STD_LOGIC);
END ENTITY eth_crc32;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF eth_crc32 IS
SIGNAL crc, nxtCrc : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN -- ARCHITECTURE rtl
nxtCrc(0) <= crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(1) <= crc(25) XOR crc(31) XOR iData(0) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(2) <= crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(3) <= crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(4) <= crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(5) <= crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(6) <= crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(7) <= crc(31) XOR iData(0) XOR crc(29) XOR iData(2) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(24) XOR iData(7);
nxtCrc(8) <= crc(0) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(25) XOR iData(6) XOR crc(24) XOR iData(7);
nxtCrc(9) <= crc(1) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(26) XOR iData(5) XOR crc(25) XOR iData(6);
nxtCrc(10) <= crc(2) XOR crc(29) XOR iData(2) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(24) XOR iData(7);
nxtCrc(11) <= crc(3) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(25) XOR iData(6) XOR crc(24) XOR iData(7);
nxtCrc(12) <= crc(4) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(26) XOR iData(5) XOR crc(25) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(13) <= crc(5) XOR crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(14) <= crc(6) XOR crc(31) XOR iData(0) XOR crc(30) XOR iData(1) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5);
nxtCrc(15) <= crc(7) XOR crc(31) XOR iData(0) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4);
nxtCrc(16) <= crc(8) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(24) XOR iData(7);
nxtCrc(17) <= crc(9) XOR crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(25) XOR iData(6);
nxtCrc(18) <= crc(10) XOR crc(31) XOR iData(0) XOR crc(30) XOR iData(1) XOR crc(26) XOR iData(5);
nxtCrc(19) <= crc(11) XOR crc(31) XOR iData(0) XOR crc(27) XOR iData(4);
nxtCrc(20) <= crc(12) XOR crc(28) XOR iData(3);
nxtCrc(21) <= crc(13) XOR crc(29) XOR iData(2);
nxtCrc(22) <= crc(14) XOR crc(24) XOR iData(7);
nxtCrc(23) <= crc(15) XOR crc(25) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(24) <= crc(16) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(25) <= crc(17) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5);
nxtCrc(26) <= crc(18) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(27) <= crc(19) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(28) <= crc(20) XOR crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(26) XOR iData(5);
nxtCrc(29) <= crc(21) XOR crc(31) XOR iData(0) XOR crc(30) XOR iData(1) XOR crc(27) XOR iData(4);
nxtCrc(30) <= crc(22) XOR crc(31) XOR iData(0) XOR crc(28) XOR iData(3);
nxtCrc(31) <= crc(23) XOR crc(29) XOR iData(2);
PROCESS (iClk,iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
crc <= (OTHERS => '0');
ELSIF rising_edge(iClk) THEN
IF iInit = '1' THEN
crc <= (OTHERS => '1');
ELSIF iCalcEn = '1' THEN
crc <= nxtCrc;
END IF;
END IF;
END PROCESS;
oCRC(31 DOWNTO 24) <= NOT (crc(24)&crc(25)&crc(26)&crc(27)&crc(28)&crc(29)&crc(30)&crc(31));
oCRC(23 DOWNTO 16) <= NOT (crc(16)&crc(17)&crc(18)&crc(19)&crc(20)&crc(21)&crc(22)&crc(23));
oCRC(15 DOWNTO 8) <= NOT (crc(8)&crc(9)&crc(10)&crc(11)&crc(12)&crc(13)&crc(14)&crc(15));
oCRC(7 DOWNTO 0) <= NOT (crc(0)&crc(1)&crc(2)&crc(3)&crc(4)&crc(5)&crc(6)&crc(7));
oCRCErr <= '1' WHEN crc /= X"c704dd7b" ELSE '0'; -- CRC not equal to magic number
END ARCHITECTURE rtl;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief TileLink-to-AXI4 bridge implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library rocketlib;
use rocketlib.types_rocket.all;
entity AxiBridge is
port (
clk : in std_logic;
nrst : in std_logic;
--! Tile-to-AXI direction
tloi : in tile_out_type;
msto : out nasti_master_out_type;
--! AXI-to-Tile direction
msti : in nasti_master_in_type;
tlio : out tile_in_type
);
end;
architecture arch_AxiBridge of AxiBridge is
type tile_rstatetype is (rwait_acq, reading);
type tile_wstatetype is (wwait_acq, writting);
type registers is record
rstate : tile_rstatetype;
rd_addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
rd_addr_incr : integer;
rd_beat_cnt : integer;
rd_xsize : std_logic_vector(2 downto 0); -- encoded AXI4 bytes size
rd_xact_id : std_logic_vector(2 downto 0);
rd_g_type : std_logic_vector(3 downto 0);
wstate : tile_wstatetype;
wr_addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
wr_addr_incr : integer;
wr_beat_cnt : integer;
wr_xsize : std_logic_vector(2 downto 0); -- encoded AXI4 bytes size
wr_xact_id : std_logic_vector(2 downto 0);
wr_g_type : std_logic_vector(3 downto 0);
wmask : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
wdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
end record;
signal r, rin : registers;
function functionAxi4MetaData(
a : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
len : integer;
sz : std_logic_vector(2 downto 0)
) return nasti_metadata_type is
variable ret : nasti_metadata_type;
begin
ret.addr := a;
ret.len := conv_std_logic_vector(len,8);
ret.size := sz;
ret.burst := NASTI_BURST_INCR;
ret.lock := '0';
ret.cache := (others => '0');
ret.prot := (others => '0');
ret.qos := (others => '0');
ret.region := (others => '0');
return (ret);
end function;
begin
comblogic : process(tloi, msti, r)
variable v : registers;
variable vmsto : nasti_master_out_type;
variable vtlio : tile_in_type;
variable addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
variable write : std_logic;
variable next_ena : std_logic;
variable wWrite : std_logic;
variable wb_xsize : std_logic_vector(2 downto 0);
variable wbByteAddr : std_logic_vector(2 downto 0);
begin
v := r;
addr := (others => '0');
write := '0';
vmsto.aw_valid := '0';
vmsto.aw_bits := META_NONE;
vmsto.aw_id := (others => '0');
vmsto.w_valid := '0';
vmsto.w_data := (others => '0');
vmsto.w_last := '0';
vmsto.w_strb := (others => '0');
vmsto.ar_valid := '0';
vmsto.ar_bits := META_NONE;
vmsto.ar_id := (others => '0');
vmsto.r_ready := '0';
vmsto.ar_user := '0';
vmsto.aw_user := '0';
vmsto.w_user := '0';
vmsto.b_ready := '1';
vtlio.a_ready := '0';
vtlio.b_valid := '0';
vtlio.b_opcode := "000";
vtlio.b_param := "00";
vtlio.b_size := "0000";
vtlio.b_source := "000";
vtlio.b_address := (others => '0');
vtlio.b_mask := (others => '0');
vtlio.b_data := (others => '0');
vtlio.c_ready := '0';
vtlio.d_valid := '0';
vtlio.d_opcode := "001";
vtlio.d_param := "00";
vtlio.d_size := "0000";
vtlio.d_source := "000";
vtlio.d_sink := "0000";
vtlio.d_addr_lo := "000";
vtlio.d_data := (others => '0');
vtlio.d_error := '0';
vtlio.e_ready := '1';
wWrite := not tloi.a_opcode(2);
if tloi.a_size(3 downto 2) /= "00" then
wb_xsize := "011";
else
wb_xsize := '0' & tloi.a_size(1 downto 0);
end if;
vmsto.aw_valid := tloi.a_valid and wWrite;
vmsto.ar_valid := tloi.a_valid and not wWrite;
case r.wstate is
when wwait_acq =>
if vmsto.aw_valid = '1' and r.rstate = rwait_acq then
v.wr_xsize := wb_xsize;
v.wr_addr := tloi.a_address;
v.wr_addr_incr := XSizeToBytes(conv_integer(wb_xsize));
v.wr_beat_cnt := conv_integer(tloi.a_size(3 downto 2));
v.wr_xact_id := tloi.a_source;
v.wmask := tloi.a_mask;
if msti.aw_ready = '1' then
v.wstate := writting;
v.wdata := tloi.a_data;
end if;
vmsto.aw_bits := functionAxi4MetaData(tloi.a_address, v.wr_beat_cnt, wb_xsize);
vmsto.aw_id(2 downto 0) := tloi.a_source;
vmsto.aw_id(CFG_ROCKET_ID_BITS-1 downto 3) := (others => '0');
vtlio.a_ready := tloi.a_valid and msti.aw_ready;
end if;
when writting =>
if r.wr_beat_cnt = 0 and msti.w_ready = '1' then
vmsto.w_last := '1';
v.wstate := wwait_acq;
elsif msti.w_ready = '1' and tloi.a_valid = '1' then
v.wr_beat_cnt := r.wr_beat_cnt - 1;
v.wr_addr := r.wr_addr + r.wr_addr_incr;
v.wdata := tloi.a_data;
end if;
vmsto.w_valid := '1';
vmsto.w_data := r.wdata;
vmsto.w_strb := r.wmask;
when others =>
end case;
case r.rstate is
when rwait_acq =>
if vmsto.ar_valid = '1' and r.wstate = wwait_acq then
v.rd_addr := tloi.a_address;
v.rd_addr_incr := XSizeToBytes(conv_integer(wb_xsize));
v.rd_beat_cnt := conv_integer(tloi.a_size(3 downto 2));
v.rd_xsize := wb_xsize;
v.rd_xact_id := tloi.a_source;
if msti.ar_ready = '1' then
v.rstate := reading;
end if;
vmsto.ar_bits := functionAxi4MetaData(tloi.a_address, v.rd_beat_cnt, wb_xsize);
vmsto.ar_id(2 downto 0) := tloi.a_source;
vmsto.ar_id(CFG_ROCKET_ID_BITS-1 downto 3) := (others => '0');
vtlio.a_ready := tloi.a_valid and msti.ar_ready;
end if;
when reading =>
next_ena := tloi.d_ready and msti.r_valid;
if next_ena = '1' and r.rd_xact_id = msti.r_id(2 downto 0) then
v.rd_beat_cnt := r.rd_beat_cnt - 1;
v.rd_addr := r.rd_addr + r.rd_addr_incr;
if r.rd_beat_cnt = 0 then
v.rstate := rwait_acq;
end if;
end if;
vmsto.r_ready := tloi.d_ready;
when others =>
end case;
if r.rstate = reading then
if r.rd_xact_id = msti.r_id(2 downto 0) then
vtlio.d_valid := msti.r_valid;
else
vtlio.d_valid := '0';
end if;
vtlio.d_size := "0110";
vtlio.d_addr_lo := r.rd_addr(5 downto 3);--!! depends on AXI_DATA_WIDTH
vtlio.d_source := r.rd_xact_id;
--vtlio.grant_bits_g_type := r.rd_g_type;
vtlio.d_data := msti.r_data;
elsif r.wstate = writting then
vtlio.d_valid := msti.w_ready;
vtlio.d_addr_lo := r.wr_addr(5 downto 3);--!! depends on AXI_DATA_WIDTH
vtlio.d_source := r.wr_xact_id;
--vtlio.grant_bits_g_type := r.wr_g_type;
--vtlio.grant_bits_data := (others => '0');
end if;
rin <= v;
tlio <= vtlio;
msto <= vmsto;
end process;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.rstate <= rwait_acq;
r.wstate <= wwait_acq;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
library verilog;
use verilog.vl_types.all;
entity FinalProject is
port(
Clk : in vl_logic;
Reset : in vl_logic;
HEX0 : out vl_logic_vector(6 downto 0);
HEX1 : out vl_logic_vector(6 downto 0);
HEX2 : out vl_logic_vector(6 downto 0);
HEX3 : out vl_logic_vector(6 downto 0);
HEX4 : out vl_logic_vector(6 downto 0);
HEX5 : out vl_logic_vector(6 downto 0);
HEX6 : out vl_logic_vector(6 downto 0);
HEX7 : out vl_logic_vector(6 downto 0);
LEDG : out vl_logic_vector(8 downto 0);
LEDR : out vl_logic_vector(17 downto 0);
Red : out vl_logic_vector(7 downto 0);
Green : out vl_logic_vector(7 downto 0);
Blue : out vl_logic_vector(7 downto 0);
VGA_clk : out vl_logic;
sync : out vl_logic;
blank : out vl_logic;
vs : out vl_logic;
hs : out vl_logic;
OTG_DATA : inout vl_logic_vector(15 downto 0);
OTG_ADDR : out vl_logic_vector(1 downto 0);
OTG_CS_N : out vl_logic;
OTG_RD_N : out vl_logic;
OTG_WR_N : out vl_logic;
OTG_RST_N : out vl_logic;
OTG_INT : in vl_logic;
sdram_wire_addr : out vl_logic_vector(12 downto 0);
sdram_wire_dq : inout vl_logic_vector(31 downto 0);
sdram_wire_ba : out vl_logic_vector(1 downto 0);
sdram_wire_dqm : out vl_logic_vector(3 downto 0);
sdram_wire_ras_n: out vl_logic;
sdram_wire_cas_n: out vl_logic;
sdram_wire_cke : out vl_logic;
sdram_wire_we_n : out vl_logic;
sdram_wire_cs_n : out vl_logic;
sdram_clk : out vl_logic
);
end FinalProject;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 1;
constant CFG_AHB_MONERR : integer := 1;
constant CFG_AHB_MONWAR : integer := 1;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#02007A#;
constant CFG_ETH_ENL : integer := 16#CC0001#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (200);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (512);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
|
-- $Id: bp_rs232_2l4l_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_2l4l_iob - syn
-- Description: iob's for internal + external rs232, with select
--
-- Dependencies: bp_rs232_2line_iob
-- bp_rs232_4line_iob
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.2.2 fix mistake in tx and rts relay
-- 2011-08-07 404 1.2.1 add RELAY generic and a relay stage towards IOB's
-- 2011-08-06 403 1.2 add pipeline flops; add RESET signal
-- 2011-07-09 391 1.1 moved and renamed to bpgen
-- 2011-07-02 387 1.0.1 use bp_rs232_[24]line_iob now
-- 2010-04-17 278 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end bp_rs232_2l4l_iob;
architecture syn of bp_rs232_2l4l_iob is
signal RXD0 : slbit := '0';
signal RXD1 : slbit := '0';
signal CTS1_N : slbit := '0';
signal R_RXD : slbit := '1';
signal R_CTS_N : slbit := '0';
signal R_TXD0 : slbit := '1';
signal R_TXD1 : slbit := '1';
signal R_RTS1_N : slbit := '0';
signal RR_RXD0 : slbit := '1';
signal RR_TXD0 : slbit := '1';
signal RR_RXD1 : slbit := '1';
signal RR_TXD1 : slbit := '1';
signal RR_CTS1_N : slbit := '0';
signal RR_RTS1_N : slbit := '0';
begin
-- On Digilent Atlys bords the IOBs for P0 and P1 are on diagonally opposide
-- corners of the die, which causes very long (7-8ns) routing delays to a LUT
-- in the middle. The RELAY generic allows to add 'relay flops' between IOB
-- flops and the mux implented in proc_regs_mux.
--
-- The data flow is
-- iob-flop relay-flop if-flop port
-- RXD0 -> RR_RXD0 -> R_RXD -> RXD
-- TXD0 <- RR_TXD0 <- R_TXD0 <- TXD
-- RXD1 -> RR_RXD1 -> R_RXD -> RXD
-- TXD1 <- RR_TXD1 <- R_TXD1 <- TXD
-- CTS1_N -> RR_CTS1_N -> R_CTS_N -> CTS
-- RTS1_N <- RR_RTS1_N <- R_RTS1_N <- RTS
P0 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD0,
TXD => RR_TXD0,
I_RXD => I_RXD0,
O_TXD => O_TXD0
);
P1 : bp_rs232_4line_iob
port map (
CLK => CLK,
RXD => RXD1,
TXD => RR_TXD1,
CTS_N => CTS1_N,
RTS_N => RR_RTS1_N,
I_RXD => I_RXD1,
O_TXD => O_TXD1,
I_CTS_N => I_CTS1_N,
O_RTS_N => O_RTS1_N
);
DORELAY : if RELAY generate
proc_regs_pipe: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
RR_RXD0 <= '1';
RR_TXD0 <= '1';
RR_RXD1 <= '1';
RR_TXD1 <= '1';
RR_CTS1_N <= '0';
RR_RTS1_N <= '0';
else
RR_RXD0 <= RXD0;
RR_TXD0 <= R_TXD0;
RR_RXD1 <= RXD1;
RR_TXD1 <= R_TXD1;
RR_CTS1_N <= CTS1_N;
RR_RTS1_N <= R_RTS1_N;
end if;
end if;
end process proc_regs_pipe;
end generate DORELAY;
NORELAY : if not RELAY generate
RR_RXD0 <= RXD0;
RR_TXD0 <= R_TXD0;
RR_RXD1 <= RXD1;
RR_TXD1 <= R_TXD1;
RR_CTS1_N <= CTS1_N;
RR_RTS1_N <= R_RTS1_N;
end generate NORELAY;
proc_regs_mux: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_RXD <= '1';
R_CTS_N <= '0';
R_TXD0 <= '1';
R_TXD1 <= '1';
R_RTS1_N <= '0';
else
if SEL = '0' then -- use 2-line rs232, no flow cntl
R_RXD <= RR_RXD0; -- get port 0 inputs
R_CTS_N <= '0';
R_TXD0 <= TXD; -- set port 0 output
R_TXD1 <= '1'; -- port 1 outputs to idle state
R_RTS1_N <= '0';
else -- otherwise use 4-line rs232
R_RXD <= RR_RXD1; -- get port 1 inputs
R_CTS_N <= RR_CTS1_N;
R_TXD0 <= '1'; -- port 0 output to idle state
R_TXD1 <= TXD; -- set port 1 outputs
R_RTS1_N <= RTS_N;
end if;
end if;
end if;
end process proc_regs_mux;
RXD <= R_RXD;
CTS_N <= R_CTS_N;
end syn;
|
-- Ejercicio 1(a)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.txt_util.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_Reg_32b IS
END TB_Reg_32b;
ARCHITECTURE behavior OF TB_Reg_32b IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Reg_32b
PORT(
D : IN std_logic_vector(31 downto 0);
CLK : IN std_logic;
LOAD : IN std_logic;
RST : IN std_logic;
O : BUFFER std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(31 downto 0) := (others => '0');
signal CLK : std_logic := '0';
signal LOAD : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal O : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Reg_32b PORT MAP (
D => D,
CLK => CLK,
LOAD => LOAD,
RST => RST,
O => O
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- check initial status
wait for 6 ns;
-- hold reset state for 5 ns.
RST <= '1';
LOAD <= '0';
D <= x"FAFAFAFA";
wait for 5 ns;
RST <= '0';
wait for 15 ns;
LOAD <= '1';
wait for 20 ns;
D <= x"51617181";
wait for 15 ns;
LOAD <= '0';
wait;
end process;
corr_proc: process(CLK)
variable theTime : time;
begin
theTime := now;
-- report time'image(theTime);
if theTime=10000 ps then
assert (O=x"00000000")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
if theTime=40000 ps then
assert (O=x"FAFAFAFA")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
if theTime=60000 ps then
assert (O=x"51617181")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
if theTime=75000 ps then
assert (O=x"51617181")
report "Resultado erroneo a los " & time'image(theTime) & " O=" & str(O)
severity ERROR;
end if;
end process;
END;
|
entity implicit is
end entity;
architecture test of implicit is
signal x : integer;
begin
process is
begin
assert x'delayed = 4; -- OK
assert x'delayed(1 ns) = 5; -- OK
assert x'delayed(5) = 1; -- Error
assert x'stable; -- OK
assert x'stable(1 ns); -- OK
--assert x'delayed'stable(2 ns); -- OK
assert x'transaction = '1'; -- OK
assert x'quiet; -- OK
assert x'quiet(5 ns); -- OK
end process;
end architecture;
|
entity implicit is
end entity;
architecture test of implicit is
signal x : integer;
begin
process is
begin
assert x'delayed = 4; -- OK
assert x'delayed(1 ns) = 5; -- OK
assert x'delayed(5) = 1; -- Error
assert x'stable; -- OK
assert x'stable(1 ns); -- OK
--assert x'delayed'stable(2 ns); -- OK
assert x'transaction = '1'; -- OK
assert x'quiet; -- OK
assert x'quiet(5 ns); -- OK
end process;
end architecture;
|
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