content stringlengths 1 1.04M ⌀ |
|---|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and b... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex6_jed is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(7 downto 0)
);
end ex6_jed;
architecture behaviour of ex6_jed is
constant s1: std_logic_vector(2 downto 0) := "000"... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.picpkg.all;
entity datapath is
Port ( clk,reset : in STD_LOGIC;
instr10 : in STD_LOGIC_VECTOR(10 downto 0);
writedata : out std_logic_vector(7 downto 0);
readdata : in std_logic_vector(7 downto 0);
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.10.2017 19:54:01
-- Design Name:
-- Module Name: get_mark_points - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
-- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : general_purpose_register_bank
-- Date : 07/07/2016
--
-- Description : Bank of 32 general purpose registers
--
-- ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------
-- Project: FE65-P2 addon
-- Author: Timon Heim (timon.heim@cern.ch)
-- Description: Attaches to serial port and controls FE65-P2 adapter
-- Dependencies: -
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
l... |
--------------------------------------------
-- Project: FE65-P2 addon
-- Author: Timon Heim (timon.heim@cern.ch)
-- Description: Attaches to serial port and controls FE65-P2 adapter
-- Dependencies: -
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
l... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted prov... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted prov... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted prov... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted prov... |
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) event handling
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted prov... |
--Led Display
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED_DISP IS
PORT( CLK_DISP :IN STD_LOGIC;
DATA_IN_1 :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN_2 :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN_3 :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA2... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity axi_dynclk is
generic (
-- Users to add parameters here
kRefClkFreqHz : natural := 100_000_000;
kVersionMajor : natural := 1;
kVersionMin... |
-------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:16:06 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_ALU.vhd 2653 2018-06-05 18:14:10Z gary.mups $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner ... |
----------------------------------------------------------------------------------
-- Module Name: test_source_3840_2160_YCC_422_ch2 - Behavioral
--
-- Description: Generate a valid DisplayPort symbol stream for testing. In this
-- case a 3840x2160 @ 30p grey screen.
-- Timings:
-- YCC 422, 8 ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for sine wav... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for sine wav... |
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
... |
--------------------------------------------------------------------------------
-- MIPS I CPU - Wishbone Master --
--------------------------------------------------------------------------------
-- ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in s... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fetch_register is
Port ( mem_addr : in STD_LOGIC_VECTOR(5 downto 0);
mem_amount : in STD_LOGIC_VECTOR(4 downto 0);
--reg_val_lower : ou... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ba
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !... |
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report """""";
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report """""";
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report """""";
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report """""";
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report """""";
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2to1 is
generic(
DATA_WIDTH : natural := 32
);
Port (
SEL : in STD_LOGIC;
A, B : in STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
X : out STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0)
);
end mux2to1;
architecture behavioral of mux2to1 is
b... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library WORK;
use WORK.all;
entity c_multiplier is
generic
(
width : integer := 4
);
port
(
input1 : std_logic_vector((width - 1) downto 0);
input2 : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ADDMPCoreAndMemory is
PORT (
in0 : IN std_logic_vector(31 DOWNTO 0);
in1 : IN std_logic_vector(31 DOWNTO 0);
out0 : OUT std_logic_vector(31 DOWNTO 0);
out1 : OUT std_logic_vector(31 DOWNTO 0);
frame_pointer : IN... |
library ieee ;
use ieee.std_logic_1164.all;
entity test_load is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
sot_in : in std_ulogic;
dat_o : out std_ulogic_vector(0 to 2559)
);
end test_lo... |
library ieee ;
use ieee.std_logic_1164.all;
entity test_load is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
sot_in : in std_ulogic;
dat_o : out std_ulogic_vector(0 to 2559)
);
end test_lo... |
entity e is
end entity;
architecture a of e is
signal x : integer := -3 * 4 + 2;
type t is range -5 to 11 - 3;
constant c : integer := +4 + 1;
signal y : t;
type int_array is array (integer range <>) of integer;
constant a1 : int_array(1 to 5) := (1, 2, 3, 4, 5);
constant a2 : int_array(1 t... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Author: Varun Nagpal
-- Net Id: vxn180010
-- VLSI Design Homework 1
-- 3rd Sept, 2018
--
-- Design: Testbench for the Generic Nth order (L = N+1 taps) Transposed Direct-form FIR-filter
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity seven_segment_ctrl is
port (
clk_i : in std_logic;
num_i : in std_logic_vector(15 downto 0);
an_o : out std_logic_vector(7 downto 0);
c_o : out std_logic_vector(7 downto 0)
);
end entity;
architectu... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity tc3 is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tc3 is
signal clk : std_logic;
signal tg : std_logic;
begin
process (clk) is
begin
if falling_edge(clk) and (tg) then
null;
end if;
end process;
end behav;
|
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_jtag_debug_module_wrapper is
port(
MonDReg : in vl_logic_vector(31 downto 0);
break_readreg : in vl_logic_vector(31 downto 0);
clk : in vl_logic;
dbrk_hit0_latch : in vl_logic;
... |
entity tb_forloop2 is
end tb_forloop2;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_forloop2 is
signal vin : std_logic_vector (7 downto 0);
signal vout : std_logic_vector (3 downto 0);
signal clk : std_logic;
signal b : std_logic;
signal c : std_logic;
signal z : std_logic;
begin
... |
--------------------------------------------------------------------------------------
-- _ _ _____ _ _____ _____ _____ _____ _ _____ _ __
-- | | / / / _ \ | | |_ _| | ____| | _ \ | ___| | | / _ \ | | / /
-- | | / / | | | | | | | | | |__ | | |... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--NOTE: the "diff" input comes from the output of the add_sub module.
--the way the opcodes are defined, the output is always the difference
--of A and B if the user is requesting a comparison operation. Otherwise,
--the output of this module will technically be undefined/w... |
{{define "basicFB"}}-- This file has been automatically generated by goFB and should not be edited by hand
-- Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
-- VHDL support is EXPERIMENTAL ONLY
{{$block := index .Blocks .BlockIndex}}{{$blocks := .Blocks}}{{$basicFB := $block.BasicFB}}
-- This... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
-------------------------------------------------------------------------------
-- Title : TIE-50206, Bonus 5
-- Project :
-------------------------------------------------------------------------------
-- File : piano.vhd
-- Author : Jonas Nikula, Tuomas Huuki
-- Company : TUT
-- Created : 10.2... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.xtcpkg.all;
use work.txt_util.all;
entity tracer is
generic (
trace_file: string := "trace.txt"
);
port (
clk: in std_logic;
dbgi: in execute_debug_ty... |
architecture RTL of ENT is begin end architecture RTL;
architecture RTL
of
ENT is
begin
end;
architecture RTL
-- Some domment
of ENT is
begin
end;
architecture RTL--some comment
of ENT is
begin
end;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
termi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:34:18 10/20/2014
-- Design Name:
-- Module Name: filter - arc1
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- ... |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later ver... |
component ghrd_10as066n2_issp_0 is
port (
source_clk : in std_logic := 'X'; -- clk
source : out std_logic_vector(2 downto 0) -- source
);
end component ghrd_10as066n2_issp_0;
u0 : component ghrd_10as066n2_issp_0
port map (
source_clk => CONNECTED_TO_source_clk, -- sour... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
entity bounds28 is
end entity;
architecture test of bounds28 is
signal n : integer;
begin
main: process is
variable t : delay_length;
begin
n <= 1;
wait for 1 ns;
t := n * ms; -- OK
n <= -5;
wait for 1 ns;
t := n * fs; ... |
-- Ian Roth
-- ECE 8455
-- VGA module, final project
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY VGA IS
PORT(
VGA_CLK, VGA_BLANK_N, VGA_HS, VGA_VS, start :OUT STD_LOGIC;
clk, rst :IN STD_LOGIC
);
END ENTITY VGA;
ARCHITECTURE Behavior OF VGA IS
SIGNAL Hcount :UNSIGNED(10 downto ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
entity GPIO is
generic (BitWidth: integer);
port ( IO_sel: in std_logic;
IO: inout std_logic_vector (BitWidth-1 downto 0);
WrtData: in std_logic_vector (BitWidth-1 downto 0);
RdData: out ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
------------------------------------------------------------------------------
-- Stuff for handling the ZUnit configuration(s)
--
-- Project :
-- File : $Id: configPkg.vhd 218 2005-01-13 17:02:10Z plessl $
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Christian Plessl <plessl@tik.e... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNGITJD4MB is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNGITJD4MB is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... |
--------------------------------------------------------------------------------
-- PS2 Keyboard Controller --
--------------------------------------------------------------------------------
-- The controller does not distinguish extended and normal keys. Most of the ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
-- $Id: sn_4x7segctl.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either vers... |
-- $Id: sn_4x7segctl.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either vers... |
entity cover1 is
end entity;
architecture test of cover1 is
signal s : integer;
begin
process is
variable v : integer;
begin
v := 1;
s <= 2;
wait for 1 ns;
if s = 2 or s > 10 then
v := 3;
else
v := 2;
end if;
while v >... |
entity cover1 is
end entity;
architecture test of cover1 is
signal s : integer;
begin
process is
variable v : integer;
begin
v := 1;
s <= 2;
wait for 1 ns;
if s = 2 or s > 10 then
v := 3;
else
v := 2;
end if;
while v >... |
entity cover1 is
end entity;
architecture test of cover1 is
signal s : integer;
begin
process is
variable v : integer;
begin
v := 1;
s <= 2;
wait for 1 ns;
if s = 2 or s > 10 then
v := 3;
else
v := 2;
end if;
while v >... |
entity cover1 is
end entity;
architecture test of cover1 is
signal s : integer;
begin
process is
variable v : integer;
begin
v := 1;
s <= 2;
wait for 1 ns;
if s = 2 or s > 10 then
v := 3;
else
v := 2;
end if;
while v >... |
entity cover1 is
end entity;
architecture test of cover1 is
signal s : integer;
begin
process is
variable v : integer;
begin
v := 1;
s <= 2;
wait for 1 ns;
if s = 2 or s > 10 then
v := 3;
else
v := 2;
end if;
while v >... |
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : eth_crc32.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-11-04... |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief TileLink-to-AXI4 bridge implementation.
--------------------------------------------------------... |
library verilog;
use verilog.vl_types.all;
entity FinalProject is
port(
Clk : in vl_logic;
Reset : in vl_logic;
HEX0 : out vl_logic_vector(6 downto 0);
HEX1 : out vl_logic_vector(6 downto 0);
HEX2 : out v... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License a... |
-- $Id: bp_rs232_2l4l_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either... |
-- Ejercicio 1(a)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.txt_util.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_Reg_32b IS
END TB_Reg_32b;
ARCHITECTURE behavior OF TB_Reg_32b IS
-- Component D... |
entity implicit is
end entity;
architecture test of implicit is
signal x : integer;
begin
process is
begin
assert x'delayed = 4; -- OK
assert x'delayed(1 ns) = 5; -- OK
assert x'delayed(5) = 1; -- Error
assert x'stable; -- OK
asse... |
entity implicit is
end entity;
architecture test of implicit is
signal x : integer;
begin
process is
begin
assert x'delayed = 4; -- OK
assert x'delayed(1 ns) = 5; -- OK
assert x'delayed(5) = 1; -- Error
assert x'stable; -- OK
asse... |
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