content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.work14_pkg.all;
entity work14_comp is
generic (
max_out_val : natural := 3;
sample_parm : string := "test");
port (
clk_i : in std_logic;
val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0));
end work14_comp;
architecture rtl of work14_comp is
begin -- rtl
foo : process(clk_i)
begin
if rising_edge(clk_i) then
val <= std_logic_vector(to_unsigned(max_out_val, val'length));
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.work14_pkg.all;
entity work14_comp is
generic (
max_out_val : natural := 3;
sample_parm : string := "test");
port (
clk_i : in std_logic;
val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0));
end work14_comp;
architecture rtl of work14_comp is
begin -- rtl
foo : process(clk_i)
begin
if rising_edge(clk_i) then
val <= std_logic_vector(to_unsigned(max_out_val, val'length));
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.work14_pkg.all;
entity work14_comp is
generic (
max_out_val : natural := 3;
sample_parm : string := "test");
port (
clk_i : in std_logic;
val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0));
end work14_comp;
architecture rtl of work14_comp is
begin -- rtl
foo : process(clk_i)
begin
if rising_edge(clk_i) then
val <= std_logic_vector(to_unsigned(max_out_val, val'length));
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.work14_pkg.all;
entity work14_comp is
generic (
max_out_val : natural := 3;
sample_parm : string := "test");
port (
clk_i : in std_logic;
val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0));
end work14_comp;
architecture rtl of work14_comp is
begin -- rtl
foo : process(clk_i)
begin
if rising_edge(clk_i) then
val <= std_logic_vector(to_unsigned(max_out_val, val'length));
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cordic_lib.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
entity cordic_tb is
generic(
N_BITS_COORD : integer := 32 --- REVISAR
);
end;
architecture cordic_tb_arq of cordic_tb is
signal clk_i : std_logic := '1';
signal ang : t_float := CERO;
signal x, y, z : t_coordenada := CERO;
signal vec_i, vec_o : t_vec;
begin
clk_i <= not clk_i after 5 ns;
ang <= PI_PF/4 after 49 ns, PI_PF/2 after 100 ns, 3*PI_PF/4 after 150 ns, PI_PF after 200 ns, 3*PI_PF/2 after 250 ns, -PI_PF/2 after 300 ns, 2*PI_PF after 350 ns, to_float(0.5) after 400 ns;
x <= to_float(1);
y <= to_float(2);
z <= to_float(3);
vec_i(1) <= x;
vec_i(2) <= y;
process(vec_i, ang)
begin
vec_o <= cordic(vec_i, ang);
end process;
process(clk_i, vec_o)
begin
if rising_edge(clk_i) then
report "pos x: " & integer'image(to_integer(to_signed(vec_o(1)*(1000),32)))
& " pos y: " & integer'image(to_integer(to_signed(vec_o(2)*(1000),32)))
severity note;
end if;
end process;
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
mH3JSh9mN1LPkECnfxE8VCJliLqIxHcAFYbRmckL5A/uFjYhAcbv6bQaYDqk3eInlu1rLP9E/+rS
txgq+T7Svg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Xw6OU4bw35JOUgpOWp8M5aL1inH3He/xpnrQ1qqgFioESnp+NJnGxOaQfRxoZJJGxD9D08Mv7KBR
IAXlCdeS6YmM/dlaDAKhES4JcFLmOd/Wfaoc1sd0iWVJr0ZI3BAOHNyv4x6p1PdHt1ZcGmUt+mhb
rfjk2UacUzG9lzSZ5pM=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
t8ajoA/WZ0yHzG0hw4pLCxirnNCnG1FAGb9zg/hVOXMzFVg1yFuEsv+hipTNKt5yidiJfOy+05Hu
NliiIIkLktbRYQ5jYm7kbdUW9yv5GV6tlgGcWv1sII4L1Sd09dv2LuaUw8qFXSHGxpR8xzYRW/T8
0T8SCaVBwaAaJ/S8rrGH4UmwZbLNl85IF0pG2fGXX+WFmOJDqCZbcD3/ERAH4UtovGPR7HmAe882
J07gCTsTj4A0QyQmFtJsxuMZUwC7k15dR6Rvbbt9r5/VJCRZ+Gju5Jg0xMbEPc5jla34iZiybFpr
tGqWVndJvZBELKwhKC+klBgJWW2MFHTzYGltYw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
O7KsvPEcGB91JL4rsqVqri5v7TLsdpq954crsAqu4xLLmmhKdHZ4em1YhpWeRtWpNtrK2jsq1MSQ
dMuXWVtxfBEl5jPoKiqIuRsCR64Qd0wRxlPr++vpRo/cLvvfrezAgYl9pdL34jwiW6ryP5/qckSX
WvzKwzSnvfnFLVBvhlI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
o6Cfc7yHrPAjusJ5drAgeCRmetHuqtT43xVcyPxrvPUoyE7xB0GzPattDomJCT5y1Lcy88poQeyz
jpTWDiHVRMBJGZxu98JNYCeYkM9XRkLgz3s+eHk4GZoSArLaBV3m4W3lIgIacDB/dweUdChjF/9n
xPEmxloXxGKMCgxtg6nlVRdviKRw3fHgnbszRK4p0Ede9tKtHO6XKPj00fA+PLETM1WzaBiFhM48
5vSc7JXosxdhdsDULL+YUhjfzIEMK+sZM3EbiRXhk7gGOdtMJfE5yn1LpmntO9U2E24RKPZlBxHo
9XgIGIugg+QSb3PobK1vgX2WPx6z/cFKSH398g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9232)
`protect data_block
NKzVdD+yHBjLPIRWPQsHtoINUefM/uWzWk6oR2l24/3fON0zvK24AY6ZJt/l8kwRJcB73W2GeRY5
AuqyYqi2ooKLmM3+62dVXlIza71U2Q+25wH5h+i0SRTm3cuUrJAz0OfHllzM0PGDDiZFKoe4d3t9
vmip+F/3Gwt5hnD2nUkkGsEFt+GGea59nCui3fy+UKQ/nsn7tAAoaN2dFnQCZuZBwzN8f3375ctv
A5qQ2zc0umlPe/l/Hg6JSZqqamteNu4dVabYEsiH1wzW2Uzf92nyXJGH71c8Y5yHDpMwhY2Jbxdq
6/yDbEvaQGiod19gY4kOTfX4cHZ2a7N9nvUT8JEnxYkkRsitP9vP4GXWAEdSQgdQAHdlwZfn6WFS
kh6MY2YxH9PW16XL0YqXk6i0ouLn5ZoY6x8u4gyRPzCfCVnz2uTLSGXoMpjmetW1R5lTU9l+4xaX
EBPP78VkulBgF1sOHIdZhUhG4hrQ40vNWrkovu28YS06iUn8IXWGx+GJbO/l4DORBovYL3MKFhDR
59ZtJM6hH6u7K4cOdFKJdc8+ISBJChJNsdrHqO9U1YeV5zkwKWfoZ+/OiPBe+KAjeseq5MY/Z2dT
+L22g+YvguOAqml9Tscw6uAgKIvG5S8vIKnHs9ZluFQU3RP9P+B3z6Y2dLkxvlTTdGKjLd0MReo5
hZVRiU5FpyLKgXQe5NcR5oYwLxq479abZCYvAWuPXRl+hF59AO0wIlVInAkwduv7Y9kmaqodt9Rs
/5ltT7XWDyJPd0E+XAWS5qiOwBmSLy8D52HcbI6ep3qA1SsOL9S3HeVJLqFHJexVPDMLOwxEsoUg
oK2bde6p9JAmCtiAPP4QpWVpbETY5dpfckcBdYWJlhxvc2ARE+ykZtMRflsCdyVQcDB0Tv/tE63z
ejQjqyAC1gurm7yaVuCZi98aoGmCpvM1oP8tf+ssCi/6z5WWM6n8CayU8JIOSS/JVWItB66P0U+L
z6RvJr7xPMEPp5KQRsaLmWSIcr7r/YqIebEKXEkrKt54qA4+tPegDaFfQpFGIsyj9hjWL7IFE7gJ
ReBdbg11IqCGV+JIx0TVsDVSdCantpzsrT1KjNwjF4GWrTYeHWW71NTuivmgDv2OHQpZ1SKjgBvE
MDxRMp6lFUmPO2W8JDkDnDaDmz8oybvlnYVmyoJAV/AZG81t6q8Qh1JulXmq4J0IiyqSzjxuMdyG
R6FaNkX+O/IHyKYKHgJZ1DwAR2Qzazi1YPc5pfwr9WKNicD1+hguYp3ZwI4MhSPFV+n2yjJE356e
8TN6szXkS+2sko8lEDagRJKW+KwypvaIAJCn6ksaAUxZB0GaEzPOqJJ9oqG4eOlAah0eHJAlBOnL
mAZkGJbx5d63auPr8FqIgRgBet6l3FAb2d+AcWJ9Mm261Z0ZQ6Po37JUGTvWnTe8DCtX0fZYuyCG
8yxUOqD82USdpxQ9SAPgCz1FV3XgSyOQ9kHrnQGXcyWBtpeit5JEV307UOGxaRov643wkKzu/6hq
LVm0xmvunIkLPgL2QMMFig8JcRKbwWNeMylUyvJ+XyxIHzVlIJI5ZIrMDzccO7lC1Con7WcLuMcn
G/PkDEEcLEf1bBUZH5yevNyyY7pf5aPyYbC3QZC3FEJmCbZ4Vpp+sbfT+akhFjl0bJSd6U6biREQ
Qxc4zuevSArry30FQMVPCJUlPflOVRGIreO++iqBWGbS8DR06kXvidC2OGTl9gJ8rr943fCOH0Pm
gnwZJDX0FuEQwx4Sr0N4oM2wJky7eMI0OkPcphU061HDqmULUlD+NbLv9aq5n/cX7bL9uuQ45ojf
mTebTHwbfYEz+ydEzFh5qawbKaIhWyPHKlH5FdoaD9pU1yLlO31CEtd/+UGmGFl8AvX0bN5S4z3D
aAU06tx7jmyRsaWgOaipa1hUUAxbpXn9I0Cna0q7LcPI9HrAR9SzvSD6Q5wZtkSJFeVGuLE6DjZt
18ortBo1/TKZuEqyzO9I2SUqFivprzXni6XCD+qmaFkj1mjzaA4G4xe5T+vYvg501Vv5MuVfdnZB
7ysmCdjxdY3w3Z9SB5aYdUSvayiDa2jf4TIOwD8la2LeV8XVVk0CJsGXy030/bTDWqYwaLs+/D7v
zqwO8Dc9rvLmdNc/+JB36s/6M12/yN91cY3RQIRvQsC/kLonhrPPVV1ZmVvKCdKSFIFYzgA7TtxH
vj90Irrq10AJa4jkBs2Jm9f10MIJPhgHFWtd2t5FuCBpybjODi2ML2bS/F9E3IB2ePE8Z0KtxNVY
B2BVUyoFOZoRLr78KgnkCCB+WhkCu9DEb1oex/S9lZUjjb9XyR6W1lu18rtH6rordIEbhkzb70RB
kltejYAeg0tMyWeii/EmQz2ZMtiN/hKQyaa+XtZ//JlnzcJQznEKrwz4plDkx5n6UgVzeBzRD/EH
v0oUsgcd0x/PkHQkWP7peH7eQe6mi0v61+lWhAhcoiIb9b0BHSPdmzpHO+4P2dUfweoocM8f0MIw
UG/yjgs8R7rvBqlg7RmN+ttuS8R3zQxmBMoNXLUm6PQstcLhcuKrvA6OQws5A+z0GjUAQhqo0DcG
GebgUDObokKSmsFs6/zz4w/Hpkqg9M8o/5NO6txbtc3i3HIl5p7fYe7E35DMc3ljY03wFqxskfeV
0eudCUFsrCtbcASXNkRo9LBbeRFg6FJzCmNy2fg4Xq82Fw9IxaXQjxcxsVHhEzSDj9jzYLj/GiRj
djLsi8lAaBptRjvpldvZPk/R/Zm9KQtnUNpWn8ZkuUzH9+Ozfs6ZEB8t40WOYp2eAo8Ye8lkdiaB
bDKxzKdZ26sR4KcqHM0JuqsSk2wzQeEXpTDmWliRrbG/xe71+aCPAKNwCVaIlTRnLKVx2sqQBtqG
6HMEvSqz5O6B+yXJha8iLdBShjRR03zGnvJxhlKglJHw5libO+a0GR3Hekp3sW8wqnJ570HKzxPl
Dn2QtP1GoGSDUbS/HQuci2z/ELCNhjdNy9Kk6Y6Eu60phVT6vswsqDE90FVXhACuJB0ejT1TopQy
LTxZkiOjkTPFJLEaGHeZIRwsFpMeAh3phY3Is2YVbN8AVFoy8TPsNtHrDFbqpSOeD1fzIPvvqcJh
p80Cmr8DHh4D4zrAwkWp1l/0Kecu7XZw8HK/HYa/C70ufwfGwoNtlbIWJkg9frY8Vku7tgZMs45M
QoPKCNDbF0X0SZyWtF5CjZBXVaUoFw7P8Zf0sI3SviKNrxXDUBs6gJbGrHuzDViKdSCPGSr3bp/y
l/xd/mxpgLbSx00teAfkB/Z35ewiy3jpI8AeMXN5X7wkWokcwaOwkbX+EbJ3nAwm8TsXRqYncySM
AN1V+VtfAY5J78glnBQSliuv5WUyA+wlzKEBhCNRmEOqRlSCAlmvifplHZVcCn8qM9Dp4jDtzXdH
AJeYJW2GdcObb13XeCS25FRQZrQLT7sxXMheTIxjWSB80XDayh42zGZzgMV+tMDEMvQSlvUNL7da
h6OxIPb2BBhUBwg8lAe+mU2tWotBB3ecZomT7o4qJH2Ih7c2+Z4rUsljI/JZ7hHrxrNFtZArWg82
plNOnulEe7YJFfs3tGegSXpY9jhteLUrwcOWPpWMcepeOoUlPWD2JMZ4gbs0gUfLbGOezL1v3SvV
uBuow42RrBfd49GV9pFGuhQ8AMsMu+WNNAhpdnb1lz9UtkiLrQXooBQuQe0eRy0fIqsN3JzJ3rs1
f5v/2UYK8AktvzGMMk4ppKTwB58wl0UVzD+fnGOW/5YLub7v/caFSxiE6cE+tpg+9Q4n4AKz7xU6
BoCKZWo4zVKVZQx8wvLin19lCHoAhnUU9zozehHpVlC0y+Vgv0ZHX803oAU5uViLG++vRKiOVLg1
qKbha8GiylUrni6z3Z8e5e02B6DqlPpFsBAsOXKddcT5lJM8ys2HLzxBlGAVKGl/YU53fE3XLJji
bvXU6dYfQOPsgwT2eCSwepKMv5hFtpxJgdx+suR/TxWvNctGAo3V8RouTywQl1p+83I8cpID7G+P
dOKJurPt3omRYmPDF35XxmbPOudrsv02PoulR8FiOH0qMugWJFbchJ+FZ2yRKCcs/QCXzkM3SUJK
/lwrXvMpJPvr9P+9OvcD/rLhsMVMV4X4QM3PCJ3f80RColsMniP/cqdR6wvP4/2rtVfU9RbOgOBt
+1BkQwHHaLduyJZgLJs5WNvUgnakavUgVcRDLap6cCKHSp2lFYv693LYkUvG1KZWbDV9FgnnWYra
DSNCtQHaYssePdVVgrmGVnXeMbAgkG0AjOf/q3Gv9ZBwt84jediiN5Z8hICQlxSXlPSqP7bPfg9c
zuEOh6xQWwPwoq62/d884ujMEBPEVAUp/kcahCtx9mBfpjpQyUHCuM6ETBl5OEvRCMnjXaYE/auy
nWUY2xUDhnZnxz/mL4sSiVzk0D8M9wjRPm3igdRsf0eHHxIOTtZZkfI0oo3Rs6G50cPvpk0qGZHv
Fyn9P1ki+yu/hRROJiM0/Am5H3g06/80XIQ/O990XguhmSWjEX5lzDcm8w/tYcLQ8Nf55sVyQCFa
ClrQLOrnKS70oI6Ne1UVAhVVNsn633T1kYS2S/JfNCMRWhIg7IOl9ARtFP6WVwAa7X2cpUjzsMMC
6gCV+daGLkKs6DQdAG3QSaRlKMIvA8eCyehx5UC+K+G0IpbMJc7kA9omZpJF8Hu1iqn9dGw6JGcg
iZARkYZoOeZODDx7/aEyAys29MmWwiF1P46sLyLhgFJnfxwZk8F0MyYFVlCHAVEOOlJFnTizHOPz
od57nT+LQeLHLkBhTs6djo4vlkW0rIJKT2vEtxjj+PoGYDmByjyX1mQdm4w8GM9jtlXH6g7WCWVi
kwhQ8mLIXVfbBS34AT4kl+plkbWqXV4xVfY+g4xACNsWdufqJBzTkpWn0lrIMY+cOa6ghcqqR+EZ
oTs2SHyh4AT8inQr8A05EX7JjLhxVoXohITvFPc+h1KoPOAdhQ6FoLw/sYpU51nbwC88hjtDXij6
5V1kC/7SCXM8Gr2fJINT2MAJFkohb2nlxLvdgOn4ILAiHJL6sgYr3DFbzkQ3Uj5fPSTWsDIVk4FO
W+RjrF+88MVKiXkn0sDPrkKS+p5B5Ax3yd1VWf6nI3TUkHvJq9fvzsGp5AcxXGb3k4Haw2pRUHqu
3zX5XRRQZv3E0iv2tkMBQFlnjlLU6HJmIEEiMTAMfxPuGQr+UFFlgKJ13a13pRtv4yuQvZ4bV/28
NOD8GK9ME/rIrkxkc0ONYh6XqjGwvVvv9SXpwznmSYeXfnt45QizvF0wDEmJFqHlDRtqp/hrAfp0
R4YPq545j+lV5rUVWZuEu0LvU7Q0Jdc7p3FYa5pAAskYqS6i3xONQaPWGrZtWer8OAt7QUEYy5uW
FHL6XiOds8/YRtiAlmpzpnHNdHb4pv7oj2wN1j61xiKYUIpCcNBvcgHaMkJLmuaubVDCFniruXdq
L3wsfra+N3z9rzNlKS7SgAacTM/lnKhoNpdlKuGguZqwTaPZvMINQIx1e/0o1EsBlk6Vo3BfncaP
z3NBJv1m6Ci+YnGx1v9RBANzuE0eevy5DQpAaq+RUYkOCe/IkADiupnWHUdWlu7GCrPFQhE4SaH+
AtyfcGv77wnwT8gnBk3eWKMjxvhvPReJKNbQ0/Z+nr8zCZ8MEpfkuSrcc6plfAUereCA0rxYZ1Mk
Nt6lLrEophuAv64BVg5+ChaUh5VT9rMQY9SunHfpx2AiVAaPhAHf2b0Iz7HGOi4HdTgXGCwTIr6Y
bUJ7qQFuMLLY1oEZfooaX02f2YFiMgeUygOXSeGIaws/GVB9dNNHUJBY/OCd8SblbP42ApSmikkq
2nMA/UFhUIdusqVS1FM4C4fafMUMdK8nO1gCxxQd6SCRolpYJaClsCtYsMv8fClMBYyAGyFLeZJH
llh4PV4SrJnxWMN5E7qgc3kucP7rOxXcSkZMqr6LRHVtZ+LsULoYYiFcKXXUyXcW+SnXnFQfKukd
ffM+VlpOzcOIYzFqGqaPPxkkxUQ2R2rQPgH+v3Mze7WdUKQ/FwagNTl4yDwET9MXgEoKRUhCucnb
D378IUpc6auLVNEiOdMVN1W5vt6mUFgh1PDU6gklUGyp01aiPblK3M5Z518eRv/Z+HXqioKhNa9q
Ux+Jj/i6zZy0vhmDXvFVWskAsbJPmKbG1URso3s5Zlc4v5C1ppXwVxUCrF8IrL1O7jvmLIsiruch
g1ZFNImeRA3gkpYJ11ffQTJCJ/epq3OinOhwSqcmNfj6jjk/UCdoMKS1uB3L072xQWJWVe1eWHE8
ZzKJnK1/NGLFgYANfnH+amsjL3oXCnUxXzMBQJWkSGSBVYn8wkIgG0E1iipFcC6AHcGqlwblrP/i
BxMiGmxnTkx/+WpUZnQKbAShZxrUuPmPEg6WhgXA7NKsNbFxERDzpQ3CSt66fnVc6yhMRW2LaXyj
nYBkiWNM+aaG/KYDnuhTa84GA7KjKEPnRWxx+HQryyOtBCm7ZdFA32g4PzqFsb55i2PonYOE1ZKC
ccoMeO5B5Ldg6Ex78oT5KeSm2YqAYEjqq+G8TtLvLPlksXCmiGmE3/nqx76XCRKPlurFQas4IjZH
dgAQTqlWxOQyXLF1zTLuZupN6DLDYvjWDNiuDgaP+JovKb+WY+/lzBmvkXmFarzQEGORnQWcJ+W/
E25nK+kEyPxN5e8eHaj7OjpyzC1F8p7JM4T0uGWCIEcLia4foLjk+FGzCsSu57nFJxbioADu8U4r
4fCXnPxT1K0Q94UsnEhq9DplbwYOxggAubw46YPjfsdtqEe2OU6z3lMrvXftj2hgkfzBpffBirrE
rm0frOx3hIp7I5mQyCbdM1TaS8lY6cj0uwiJd4UMsenUriWrj+m7GNAEe6pk+TubABFM1ljFNfpm
TCIyvxtPY3SV2UXVC1ZahFj6oz6xa/RrNog5CG3kYlu6Ao+GkXvuaeBAugFzYEBj5am9rjwTqLQq
ffrwKfzLwCxDa+w8C20HGYnOeMDsrMyT5ECgRUPco2MFQO5jIzg93QCqdzYxFiy7jFTWJGnwRKvm
n3roBqXVY1iNde5iZfU8b/QJjGQ6CnT7QjRcjgnmzkdND8s/BCNsPvzASfHLNu/EHWKZqu1HLp6i
520ghw0RrZLlRCKdSGHTLekrpeF5Rod84j9kmY5FTdZvjA3VSNjop4g9Yy0XbRPdmb1fG1sEGtAG
Pvz2FtH0siTluj6ASk8PSe0j8oVhe0mNtjcImwUGnS6tGx6J6AZIxn/0phUsMLRjulvQC2RNHDxT
p9yKkcJaQR92P2YA71QGx4eytn3Mtx9JgLZWlrQTBhwtXa/lhZg4aRY6PAULWUtF0lOIlGauD2ny
liYV3HWuTM50EP1C2EqhkfrlkFGPZpkin83UgRTbvzgPQLOuHwzqjPxoHz7Py1rReY/x5xFVvDze
B7nDJVFk8E8kt8FvoRNuLebhSsArrUF6Eve5LsRkRUI7+730GxzdXxdLmi5PqwAfwzcHx6bZTPDl
vprGZxjcO6gK06AVfEVKQqIaBAdj99hJWKZ+10ju/FoK64tWgrlMj8C+jR2EHpR0lbyULzv7dnll
+Q+n4RsUzhLyiF25gB66bdVgxRCrCQYW3fgnys+UYDYRDMN7H7jVtUZHPp7ODvtlhn3U88BRyV/t
ZU5g2lm1IUB/+udpKIz/H+I1+W04CDkWQHZbMfSb0GSThwcuTebQO2izzz9vb0XrLpoHYM+ynV1P
UYmSHzFMvhU9Ea/JtakLOSMwAwovuOpFa8VhnWhY9eAZd/i1twl9wp+Y2oZBjmTddZqKoMEv3Mb/
c0z1gDHSg3scWh9gnFdhkm/6wXSCNKYbOL/7juK1EqaelwUKaWxxAdxbFY20+QuyRWsCrU4+x3WH
3U3j8/viRs9HrGJ67elwucNhKU4NeMHe3L4Sgilt6Mz1XfxSapcQQflSI2r/A0FhufMMpBQSdzDC
9rcF9CUMUSIxmydZcfSsgeedETICgXQLnhzUFT/uuEqEsKqoD5d3KCI6tTAn3IzCA9r1jvbR4eP9
HYNd9oDIW+YSJ1jZCBt3qwdqmM+oKJEGe3IGIguk1RHZfHZa1VwTuPbIS+uvjlsgI9FLoSouJSLN
YOcO4T5Of0EYTTi+yuJCcIZbLgNI9FUJvhpVkmesISDPRXI8ncf3ElGVypX69dsT2uITCA9TJ3pb
lFBFlbgH7GQdKnc+ijwDZ0XpKx99QkGM5U7Ca4MHB0GA0ezlS9HEKKAnLA6QCpfDzJcXPxDRGCZG
oh8Z6skDNCqEacyFl09oXhuyMUBoi/N+GbQXawzCzXIR5RNJYZKce2mFeP+MVkzMaHN0nXiP4gcM
T4EDzymvdbJse10RpYnVDkEK2MyO6G5Wcn6hW3izykGwSO7Vw1PNa1yk/wQOysamLmfedQRmsU5K
5CAe20ExNoYydHEg/tbuJZfsHB59O5JxkPmTz+rK8sj0cc3p+/kSJEFRpWROfcxeurH9cGN9q6ep
lom7ZGxHMGOp6l2QXAaYLcNKgi708l6yO/Hbs6FwHbjdudV6G8kMUkl9y9oZvU/8obHzypGXtO7l
DPDj8I2nM9dbvrYHPfj6+Al508Q5cLGQeRM6clPEciG7UgolecexoTcli9TjiZ9E8hDiu5qPvp0P
3vAlC0LvwcWhFieUz78P/JRb4qry1XmspKuWjf5TX8hSo9LSES/V9GAv4lbNCdGl3bskjQywTUPL
ZNI0tEAzb4VFWxc3FZse7my+/L/6X0wwq2351O5fRl1t24L4N/ZdDKf55HqGddN8bnCRhvn7vkit
LYJhiT9RASOaUS+MWg54mSULSeJgUZ+xYjdOYp/qwbQfszHBCSAlFVdALnuoe6h5bGx3vezz0Wyq
rYHeEvOlUk9Crt41sncKBprCMur2MhGO/kRwGQ2LfOdECX/6+AoV3j6gpopQSLBxoEhqf5oIPL8Q
S6lnGiQTmYdyUbvrUcpF9h8fnLIPBeaRuRdHDljrck65nrl3OnfajqZKnHbYfw076oFtnxsbMYqI
Yud5kwmZ47ch5rg6CXyikZ2R1qeksHxrs79fw0G8kkPr1JuZdsu+gmiGYrYz8B06u99GhuZ6KUyH
Ws7FvTa/bV6TLsLGiXuVxd8J5/uJi092RVgX9++/h3BBUHtpZYEWgHol3l/WFHgrBZxV/oskFAH3
d8ewFHr86Oq4w2Snf/57twnuEqFIgZ62I3YjVvkHkMZBI/DAt4VH42fMfK/xJBb3nGr9qAITHakw
tEK9L/uBUBqDedOwH2qccHVYJGKnOF+34x6GA7zMIuLKUnvgx3AJnHSfU1VwUi94JCYiPI1mdxTj
mZ79+Cgm59owmXgMUT4V7FFxRZbqV73g/lrDnsI1VJfpbllvmIfX68/IDSJ7wTsr4eo7DsWJ+hfF
pzeRWMue4sgq50j33acw5GzMGTU1IHu9QStgA38Llea48Ud+e5FOlqUQyGJoNoaYEuTWo2tLFCV+
WLU0N7RW3vUsd77+dmiFX2fLyTjnXJwxEo3KPDJzY/mzLG/pAKiqJZ0f15p3c+Asj0RhhBfe2lhM
AKghiiM1PuzcKlqIzevdTD825je7sWlKcohgdkr8byLB6Sy1Azlj3exvIxsUsLflLCRS3DoWIWsp
Trir9qjxm6Ew+mMl6KdYxwos8OlMerLlG/7coB+8u8swzoH4B+Pwxb5BLtcWMkflgwx3nUAgAUPs
n0Pr8BglhCzYGLiER7zt/9s7MI5/LhyR81EfIlgbvGTtkh1zkve+75KFrrEB0rf4kICHLjKbnofj
fHn0rAQUGEg1MC7uKQdHDk2+j2p5QWRrBeiwm+hPiAbC6AlIbpZZojpu722Om11gH5Z2kmPfUIoj
ezDB5ukI0CC0ee++4G9o2i076/N8tyXg4uzX4/Q/M4MukMgS2a82TfQN+Zuw00K41uY/KRFoDPI5
lg+NNgsMsMoC/72uAjDUHUy6gyRTS6QgarR20w64LFeUUEas9vlVBSDVQz1ls6XNYyYsB3hxqGJ7
oxFNbOgdM7H5Y/NUSJcKyHz49sHYF0u6+fL7advdw3NYYVLEOdnGqQVQwTE61gbVi2lNThSreEKd
/pLxzfvGNHdNVN/lj2x80XxogRin74hf3A5T9yb9R9TPR48ijB7y7+8c7zJM3GyfoXL437v1HUpT
v8OFFgHnbWFUd7d3QwmQtEH/rZb2pSermvChxBJUaJBnQpEIjUt50j++sm1FY1zhl2nfADnGW5jB
OP0NVhn6ZsZ8glMe2tDX0iJDLWTdTgu7qipzRXHli9K9XDN6+SkmJ38wp06vsp5wOA481D2LhfyT
MeoiR4MPhM2ExBypCNT5lgyqPASQqpfS6jkI4sXLP/v06lqbiQbh9fNeLRSxaoLFsGaKLykLtrvQ
N1l4Dr+K09zYYS+HrahXnAXTgGUDdoMVUYZO2R9LTcKQKOmPm7FUmyM0z8UWHEQXBcicWL8D//e/
unvdCk97iIpJ5afVQALW23RTMwcytjHnGLjf66D/msnUzvJWH2pFx8qDVTc8cdQHAdNuztAODjG/
j7MhRopqiJ4eJydHxcaW8duyWFsYbdq84VfWJemvA+OS+Q37CGOp2HlBNlcA2o8N8jviBLY5wgwu
MHTZXKzjn+0i1PiEs9XbF5/LkOXUmcwrQHI34oQJgdw4pdMmKzn2KrkKIzrwDhufLjQ1tam0JCxK
/bBQT9LTUSjalcPUkz87PQx8tbaNKcJZeYWqLPabW7/v22xC3dpe7LJBu4btEnIsVO6ik131J2N8
/1zyj0ijHeiNI4FZw67kbCCIOqaPf+9Vo4b6oYTt4pYqj70s2a0aoPZzKgl7rUEp93D+BkKTD/Bm
en1ZpWdJlfuSWD77kN/tcW34ZNE+B+rMAU8KPqWbIyGD3yXI93JMn06hR6OXaJvadp8u0zBUFC7w
xulqoZgc+mbdYYoTQhwa0hAuhRunzBeU6wiwdWCuD6ruB8QNlFzzH39QavpeVX7WoUjck0DjnNgZ
TLPWTo1/4ruJFWugafHYi7TKSnB2W69YmuOF8+pgZq9L/MN+rgscskP7jmKZg+pgzTvWPsq/KRdb
XcqANhFMCxh/fwuFmCf5YiGtLm7izTRanS+Qr6mbuDJm61VVz7HWIUzGIssEHVkgC7MdZ5UAQhZy
3ttMNu8QZLHpRfquICYtkPiU9bCZZJmkKMtLYxtKZ63yWK2SBo6e88sLG5/3TDOdXowmEGiENAvj
tTAIrDrJkpDkS7ysdPY7kgI8r1fNEwmGh1YeuFRBIGVqA3KUisYHJ97aEms83WXekFvApst2NHjS
KMzsEpIVGn2dzZb/aNZkBuORFsM7NGrvZOxIQSWgCfD5W/VS7ZHn1SF94qdliRmPwjwR7FHSqUkm
oKQtsqD4DzagpESpxD+PX2IxiuExDFmx0CWKJ9ZQlijUmgqALhnLXJhFBPNWMTeXtUgbI9WKimFI
jhLqGensLDkdtP+ReBBxpaT7Lcb5yUPd3Bf1qXsDfY5eAkW/xbn/RIyNpSffhdjpUZEO8Ox1ILea
6P6tJBm3I2bsl6qcM+caQGRYjIqZtT1xHZ8vuOfv3UsCd+mHq2K4Ja9Sk3L76VAUJFXYkQPpabVV
enktzccg8cvmZczwQqhCkwJ+ndAWajBEXaB05UgwkKzI/u7ZtkvbakzI5L6E5okPuvVvTRcwKcYm
LnsGKvlj56dNUZPoBmTlwYecCArUyNmieoaNESR8M0QkL5HK36nsTE4XBcQbfERI8bk17etZPJPL
8VaWicfAKu/XcCvzd5npGEe9mlQaH4ylRLACtp7896w1XUU1H0+NiliYo3Znkhn7gB060A8txhan
3l600Z/KvOpNXgP454dzeFo+Gs+bj80IppEq/kOGwIDT9b4mrycG1tXlyGvEoc5WPT/jRDlsmJNm
+dFsvsVZBrKBbEaswt/cm5IIWJwmr4GpEjRxIxI9ssGl8mHojoC879sVickOtiSow77cpehY+prg
Km4NcsvcKzeU2yOKSymDeWSUkEtlRKaLLgsK6iCdCQ3evo0D9Ik1Ba87U21KZgfVlbDuidoVlYbk
aZvh4Yyk+RJj6pKs3U4vZ9IWypLSJUx4Ece8An63Qas9orkXbmoW3nhe8hVlszTs95ua3uyOvtQO
JN6uHyPlYtQ4wiBpxUciI5bNc1TJvuLikgzZ/ATkW/bS9LJHBaXP+Uvl7NVrmi1RIKKscN2ppycD
suPYOblsS3nZlVfBXCZUJPh9yRWYPqrnjgh/V/2BdzzRBlWhQwFLRxMk/b1Rj6acq+UkSUo6aw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
mH3JSh9mN1LPkECnfxE8VCJliLqIxHcAFYbRmckL5A/uFjYhAcbv6bQaYDqk3eInlu1rLP9E/+rS
txgq+T7Svg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Xw6OU4bw35JOUgpOWp8M5aL1inH3He/xpnrQ1qqgFioESnp+NJnGxOaQfRxoZJJGxD9D08Mv7KBR
IAXlCdeS6YmM/dlaDAKhES4JcFLmOd/Wfaoc1sd0iWVJr0ZI3BAOHNyv4x6p1PdHt1ZcGmUt+mhb
rfjk2UacUzG9lzSZ5pM=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
t8ajoA/WZ0yHzG0hw4pLCxirnNCnG1FAGb9zg/hVOXMzFVg1yFuEsv+hipTNKt5yidiJfOy+05Hu
NliiIIkLktbRYQ5jYm7kbdUW9yv5GV6tlgGcWv1sII4L1Sd09dv2LuaUw8qFXSHGxpR8xzYRW/T8
0T8SCaVBwaAaJ/S8rrGH4UmwZbLNl85IF0pG2fGXX+WFmOJDqCZbcD3/ERAH4UtovGPR7HmAe882
J07gCTsTj4A0QyQmFtJsxuMZUwC7k15dR6Rvbbt9r5/VJCRZ+Gju5Jg0xMbEPc5jla34iZiybFpr
tGqWVndJvZBELKwhKC+klBgJWW2MFHTzYGltYw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
O7KsvPEcGB91JL4rsqVqri5v7TLsdpq954crsAqu4xLLmmhKdHZ4em1YhpWeRtWpNtrK2jsq1MSQ
dMuXWVtxfBEl5jPoKiqIuRsCR64Qd0wRxlPr++vpRo/cLvvfrezAgYl9pdL34jwiW6ryP5/qckSX
WvzKwzSnvfnFLVBvhlI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
o6Cfc7yHrPAjusJ5drAgeCRmetHuqtT43xVcyPxrvPUoyE7xB0GzPattDomJCT5y1Lcy88poQeyz
jpTWDiHVRMBJGZxu98JNYCeYkM9XRkLgz3s+eHk4GZoSArLaBV3m4W3lIgIacDB/dweUdChjF/9n
xPEmxloXxGKMCgxtg6nlVRdviKRw3fHgnbszRK4p0Ede9tKtHO6XKPj00fA+PLETM1WzaBiFhM48
5vSc7JXosxdhdsDULL+YUhjfzIEMK+sZM3EbiRXhk7gGOdtMJfE5yn1LpmntO9U2E24RKPZlBxHo
9XgIGIugg+QSb3PobK1vgX2WPx6z/cFKSH398g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9232)
`protect data_block
NKzVdD+yHBjLPIRWPQsHtoINUefM/uWzWk6oR2l24/3fON0zvK24AY6ZJt/l8kwRJcB73W2GeRY5
AuqyYqi2ooKLmM3+62dVXlIza71U2Q+25wH5h+i0SRTm3cuUrJAz0OfHllzM0PGDDiZFKoe4d3t9
vmip+F/3Gwt5hnD2nUkkGsEFt+GGea59nCui3fy+UKQ/nsn7tAAoaN2dFnQCZuZBwzN8f3375ctv
A5qQ2zc0umlPe/l/Hg6JSZqqamteNu4dVabYEsiH1wzW2Uzf92nyXJGH71c8Y5yHDpMwhY2Jbxdq
6/yDbEvaQGiod19gY4kOTfX4cHZ2a7N9nvUT8JEnxYkkRsitP9vP4GXWAEdSQgdQAHdlwZfn6WFS
kh6MY2YxH9PW16XL0YqXk6i0ouLn5ZoY6x8u4gyRPzCfCVnz2uTLSGXoMpjmetW1R5lTU9l+4xaX
EBPP78VkulBgF1sOHIdZhUhG4hrQ40vNWrkovu28YS06iUn8IXWGx+GJbO/l4DORBovYL3MKFhDR
59ZtJM6hH6u7K4cOdFKJdc8+ISBJChJNsdrHqO9U1YeV5zkwKWfoZ+/OiPBe+KAjeseq5MY/Z2dT
+L22g+YvguOAqml9Tscw6uAgKIvG5S8vIKnHs9ZluFQU3RP9P+B3z6Y2dLkxvlTTdGKjLd0MReo5
hZVRiU5FpyLKgXQe5NcR5oYwLxq479abZCYvAWuPXRl+hF59AO0wIlVInAkwduv7Y9kmaqodt9Rs
/5ltT7XWDyJPd0E+XAWS5qiOwBmSLy8D52HcbI6ep3qA1SsOL9S3HeVJLqFHJexVPDMLOwxEsoUg
oK2bde6p9JAmCtiAPP4QpWVpbETY5dpfckcBdYWJlhxvc2ARE+ykZtMRflsCdyVQcDB0Tv/tE63z
ejQjqyAC1gurm7yaVuCZi98aoGmCpvM1oP8tf+ssCi/6z5WWM6n8CayU8JIOSS/JVWItB66P0U+L
z6RvJr7xPMEPp5KQRsaLmWSIcr7r/YqIebEKXEkrKt54qA4+tPegDaFfQpFGIsyj9hjWL7IFE7gJ
ReBdbg11IqCGV+JIx0TVsDVSdCantpzsrT1KjNwjF4GWrTYeHWW71NTuivmgDv2OHQpZ1SKjgBvE
MDxRMp6lFUmPO2W8JDkDnDaDmz8oybvlnYVmyoJAV/AZG81t6q8Qh1JulXmq4J0IiyqSzjxuMdyG
R6FaNkX+O/IHyKYKHgJZ1DwAR2Qzazi1YPc5pfwr9WKNicD1+hguYp3ZwI4MhSPFV+n2yjJE356e
8TN6szXkS+2sko8lEDagRJKW+KwypvaIAJCn6ksaAUxZB0GaEzPOqJJ9oqG4eOlAah0eHJAlBOnL
mAZkGJbx5d63auPr8FqIgRgBet6l3FAb2d+AcWJ9Mm261Z0ZQ6Po37JUGTvWnTe8DCtX0fZYuyCG
8yxUOqD82USdpxQ9SAPgCz1FV3XgSyOQ9kHrnQGXcyWBtpeit5JEV307UOGxaRov643wkKzu/6hq
LVm0xmvunIkLPgL2QMMFig8JcRKbwWNeMylUyvJ+XyxIHzVlIJI5ZIrMDzccO7lC1Con7WcLuMcn
G/PkDEEcLEf1bBUZH5yevNyyY7pf5aPyYbC3QZC3FEJmCbZ4Vpp+sbfT+akhFjl0bJSd6U6biREQ
Qxc4zuevSArry30FQMVPCJUlPflOVRGIreO++iqBWGbS8DR06kXvidC2OGTl9gJ8rr943fCOH0Pm
gnwZJDX0FuEQwx4Sr0N4oM2wJky7eMI0OkPcphU061HDqmULUlD+NbLv9aq5n/cX7bL9uuQ45ojf
mTebTHwbfYEz+ydEzFh5qawbKaIhWyPHKlH5FdoaD9pU1yLlO31CEtd/+UGmGFl8AvX0bN5S4z3D
aAU06tx7jmyRsaWgOaipa1hUUAxbpXn9I0Cna0q7LcPI9HrAR9SzvSD6Q5wZtkSJFeVGuLE6DjZt
18ortBo1/TKZuEqyzO9I2SUqFivprzXni6XCD+qmaFkj1mjzaA4G4xe5T+vYvg501Vv5MuVfdnZB
7ysmCdjxdY3w3Z9SB5aYdUSvayiDa2jf4TIOwD8la2LeV8XVVk0CJsGXy030/bTDWqYwaLs+/D7v
zqwO8Dc9rvLmdNc/+JB36s/6M12/yN91cY3RQIRvQsC/kLonhrPPVV1ZmVvKCdKSFIFYzgA7TtxH
vj90Irrq10AJa4jkBs2Jm9f10MIJPhgHFWtd2t5FuCBpybjODi2ML2bS/F9E3IB2ePE8Z0KtxNVY
B2BVUyoFOZoRLr78KgnkCCB+WhkCu9DEb1oex/S9lZUjjb9XyR6W1lu18rtH6rordIEbhkzb70RB
kltejYAeg0tMyWeii/EmQz2ZMtiN/hKQyaa+XtZ//JlnzcJQznEKrwz4plDkx5n6UgVzeBzRD/EH
v0oUsgcd0x/PkHQkWP7peH7eQe6mi0v61+lWhAhcoiIb9b0BHSPdmzpHO+4P2dUfweoocM8f0MIw
UG/yjgs8R7rvBqlg7RmN+ttuS8R3zQxmBMoNXLUm6PQstcLhcuKrvA6OQws5A+z0GjUAQhqo0DcG
GebgUDObokKSmsFs6/zz4w/Hpkqg9M8o/5NO6txbtc3i3HIl5p7fYe7E35DMc3ljY03wFqxskfeV
0eudCUFsrCtbcASXNkRo9LBbeRFg6FJzCmNy2fg4Xq82Fw9IxaXQjxcxsVHhEzSDj9jzYLj/GiRj
djLsi8lAaBptRjvpldvZPk/R/Zm9KQtnUNpWn8ZkuUzH9+Ozfs6ZEB8t40WOYp2eAo8Ye8lkdiaB
bDKxzKdZ26sR4KcqHM0JuqsSk2wzQeEXpTDmWliRrbG/xe71+aCPAKNwCVaIlTRnLKVx2sqQBtqG
6HMEvSqz5O6B+yXJha8iLdBShjRR03zGnvJxhlKglJHw5libO+a0GR3Hekp3sW8wqnJ570HKzxPl
Dn2QtP1GoGSDUbS/HQuci2z/ELCNhjdNy9Kk6Y6Eu60phVT6vswsqDE90FVXhACuJB0ejT1TopQy
LTxZkiOjkTPFJLEaGHeZIRwsFpMeAh3phY3Is2YVbN8AVFoy8TPsNtHrDFbqpSOeD1fzIPvvqcJh
p80Cmr8DHh4D4zrAwkWp1l/0Kecu7XZw8HK/HYa/C70ufwfGwoNtlbIWJkg9frY8Vku7tgZMs45M
QoPKCNDbF0X0SZyWtF5CjZBXVaUoFw7P8Zf0sI3SviKNrxXDUBs6gJbGrHuzDViKdSCPGSr3bp/y
l/xd/mxpgLbSx00teAfkB/Z35ewiy3jpI8AeMXN5X7wkWokcwaOwkbX+EbJ3nAwm8TsXRqYncySM
AN1V+VtfAY5J78glnBQSliuv5WUyA+wlzKEBhCNRmEOqRlSCAlmvifplHZVcCn8qM9Dp4jDtzXdH
AJeYJW2GdcObb13XeCS25FRQZrQLT7sxXMheTIxjWSB80XDayh42zGZzgMV+tMDEMvQSlvUNL7da
h6OxIPb2BBhUBwg8lAe+mU2tWotBB3ecZomT7o4qJH2Ih7c2+Z4rUsljI/JZ7hHrxrNFtZArWg82
plNOnulEe7YJFfs3tGegSXpY9jhteLUrwcOWPpWMcepeOoUlPWD2JMZ4gbs0gUfLbGOezL1v3SvV
uBuow42RrBfd49GV9pFGuhQ8AMsMu+WNNAhpdnb1lz9UtkiLrQXooBQuQe0eRy0fIqsN3JzJ3rs1
f5v/2UYK8AktvzGMMk4ppKTwB58wl0UVzD+fnGOW/5YLub7v/caFSxiE6cE+tpg+9Q4n4AKz7xU6
BoCKZWo4zVKVZQx8wvLin19lCHoAhnUU9zozehHpVlC0y+Vgv0ZHX803oAU5uViLG++vRKiOVLg1
qKbha8GiylUrni6z3Z8e5e02B6DqlPpFsBAsOXKddcT5lJM8ys2HLzxBlGAVKGl/YU53fE3XLJji
bvXU6dYfQOPsgwT2eCSwepKMv5hFtpxJgdx+suR/TxWvNctGAo3V8RouTywQl1p+83I8cpID7G+P
dOKJurPt3omRYmPDF35XxmbPOudrsv02PoulR8FiOH0qMugWJFbchJ+FZ2yRKCcs/QCXzkM3SUJK
/lwrXvMpJPvr9P+9OvcD/rLhsMVMV4X4QM3PCJ3f80RColsMniP/cqdR6wvP4/2rtVfU9RbOgOBt
+1BkQwHHaLduyJZgLJs5WNvUgnakavUgVcRDLap6cCKHSp2lFYv693LYkUvG1KZWbDV9FgnnWYra
DSNCtQHaYssePdVVgrmGVnXeMbAgkG0AjOf/q3Gv9ZBwt84jediiN5Z8hICQlxSXlPSqP7bPfg9c
zuEOh6xQWwPwoq62/d884ujMEBPEVAUp/kcahCtx9mBfpjpQyUHCuM6ETBl5OEvRCMnjXaYE/auy
nWUY2xUDhnZnxz/mL4sSiVzk0D8M9wjRPm3igdRsf0eHHxIOTtZZkfI0oo3Rs6G50cPvpk0qGZHv
Fyn9P1ki+yu/hRROJiM0/Am5H3g06/80XIQ/O990XguhmSWjEX5lzDcm8w/tYcLQ8Nf55sVyQCFa
ClrQLOrnKS70oI6Ne1UVAhVVNsn633T1kYS2S/JfNCMRWhIg7IOl9ARtFP6WVwAa7X2cpUjzsMMC
6gCV+daGLkKs6DQdAG3QSaRlKMIvA8eCyehx5UC+K+G0IpbMJc7kA9omZpJF8Hu1iqn9dGw6JGcg
iZARkYZoOeZODDx7/aEyAys29MmWwiF1P46sLyLhgFJnfxwZk8F0MyYFVlCHAVEOOlJFnTizHOPz
od57nT+LQeLHLkBhTs6djo4vlkW0rIJKT2vEtxjj+PoGYDmByjyX1mQdm4w8GM9jtlXH6g7WCWVi
kwhQ8mLIXVfbBS34AT4kl+plkbWqXV4xVfY+g4xACNsWdufqJBzTkpWn0lrIMY+cOa6ghcqqR+EZ
oTs2SHyh4AT8inQr8A05EX7JjLhxVoXohITvFPc+h1KoPOAdhQ6FoLw/sYpU51nbwC88hjtDXij6
5V1kC/7SCXM8Gr2fJINT2MAJFkohb2nlxLvdgOn4ILAiHJL6sgYr3DFbzkQ3Uj5fPSTWsDIVk4FO
W+RjrF+88MVKiXkn0sDPrkKS+p5B5Ax3yd1VWf6nI3TUkHvJq9fvzsGp5AcxXGb3k4Haw2pRUHqu
3zX5XRRQZv3E0iv2tkMBQFlnjlLU6HJmIEEiMTAMfxPuGQr+UFFlgKJ13a13pRtv4yuQvZ4bV/28
NOD8GK9ME/rIrkxkc0ONYh6XqjGwvVvv9SXpwznmSYeXfnt45QizvF0wDEmJFqHlDRtqp/hrAfp0
R4YPq545j+lV5rUVWZuEu0LvU7Q0Jdc7p3FYa5pAAskYqS6i3xONQaPWGrZtWer8OAt7QUEYy5uW
FHL6XiOds8/YRtiAlmpzpnHNdHb4pv7oj2wN1j61xiKYUIpCcNBvcgHaMkJLmuaubVDCFniruXdq
L3wsfra+N3z9rzNlKS7SgAacTM/lnKhoNpdlKuGguZqwTaPZvMINQIx1e/0o1EsBlk6Vo3BfncaP
z3NBJv1m6Ci+YnGx1v9RBANzuE0eevy5DQpAaq+RUYkOCe/IkADiupnWHUdWlu7GCrPFQhE4SaH+
AtyfcGv77wnwT8gnBk3eWKMjxvhvPReJKNbQ0/Z+nr8zCZ8MEpfkuSrcc6plfAUereCA0rxYZ1Mk
Nt6lLrEophuAv64BVg5+ChaUh5VT9rMQY9SunHfpx2AiVAaPhAHf2b0Iz7HGOi4HdTgXGCwTIr6Y
bUJ7qQFuMLLY1oEZfooaX02f2YFiMgeUygOXSeGIaws/GVB9dNNHUJBY/OCd8SblbP42ApSmikkq
2nMA/UFhUIdusqVS1FM4C4fafMUMdK8nO1gCxxQd6SCRolpYJaClsCtYsMv8fClMBYyAGyFLeZJH
llh4PV4SrJnxWMN5E7qgc3kucP7rOxXcSkZMqr6LRHVtZ+LsULoYYiFcKXXUyXcW+SnXnFQfKukd
ffM+VlpOzcOIYzFqGqaPPxkkxUQ2R2rQPgH+v3Mze7WdUKQ/FwagNTl4yDwET9MXgEoKRUhCucnb
D378IUpc6auLVNEiOdMVN1W5vt6mUFgh1PDU6gklUGyp01aiPblK3M5Z518eRv/Z+HXqioKhNa9q
Ux+Jj/i6zZy0vhmDXvFVWskAsbJPmKbG1URso3s5Zlc4v5C1ppXwVxUCrF8IrL1O7jvmLIsiruch
g1ZFNImeRA3gkpYJ11ffQTJCJ/epq3OinOhwSqcmNfj6jjk/UCdoMKS1uB3L072xQWJWVe1eWHE8
ZzKJnK1/NGLFgYANfnH+amsjL3oXCnUxXzMBQJWkSGSBVYn8wkIgG0E1iipFcC6AHcGqlwblrP/i
BxMiGmxnTkx/+WpUZnQKbAShZxrUuPmPEg6WhgXA7NKsNbFxERDzpQ3CSt66fnVc6yhMRW2LaXyj
nYBkiWNM+aaG/KYDnuhTa84GA7KjKEPnRWxx+HQryyOtBCm7ZdFA32g4PzqFsb55i2PonYOE1ZKC
ccoMeO5B5Ldg6Ex78oT5KeSm2YqAYEjqq+G8TtLvLPlksXCmiGmE3/nqx76XCRKPlurFQas4IjZH
dgAQTqlWxOQyXLF1zTLuZupN6DLDYvjWDNiuDgaP+JovKb+WY+/lzBmvkXmFarzQEGORnQWcJ+W/
E25nK+kEyPxN5e8eHaj7OjpyzC1F8p7JM4T0uGWCIEcLia4foLjk+FGzCsSu57nFJxbioADu8U4r
4fCXnPxT1K0Q94UsnEhq9DplbwYOxggAubw46YPjfsdtqEe2OU6z3lMrvXftj2hgkfzBpffBirrE
rm0frOx3hIp7I5mQyCbdM1TaS8lY6cj0uwiJd4UMsenUriWrj+m7GNAEe6pk+TubABFM1ljFNfpm
TCIyvxtPY3SV2UXVC1ZahFj6oz6xa/RrNog5CG3kYlu6Ao+GkXvuaeBAugFzYEBj5am9rjwTqLQq
ffrwKfzLwCxDa+w8C20HGYnOeMDsrMyT5ECgRUPco2MFQO5jIzg93QCqdzYxFiy7jFTWJGnwRKvm
n3roBqXVY1iNde5iZfU8b/QJjGQ6CnT7QjRcjgnmzkdND8s/BCNsPvzASfHLNu/EHWKZqu1HLp6i
520ghw0RrZLlRCKdSGHTLekrpeF5Rod84j9kmY5FTdZvjA3VSNjop4g9Yy0XbRPdmb1fG1sEGtAG
Pvz2FtH0siTluj6ASk8PSe0j8oVhe0mNtjcImwUGnS6tGx6J6AZIxn/0phUsMLRjulvQC2RNHDxT
p9yKkcJaQR92P2YA71QGx4eytn3Mtx9JgLZWlrQTBhwtXa/lhZg4aRY6PAULWUtF0lOIlGauD2ny
liYV3HWuTM50EP1C2EqhkfrlkFGPZpkin83UgRTbvzgPQLOuHwzqjPxoHz7Py1rReY/x5xFVvDze
B7nDJVFk8E8kt8FvoRNuLebhSsArrUF6Eve5LsRkRUI7+730GxzdXxdLmi5PqwAfwzcHx6bZTPDl
vprGZxjcO6gK06AVfEVKQqIaBAdj99hJWKZ+10ju/FoK64tWgrlMj8C+jR2EHpR0lbyULzv7dnll
+Q+n4RsUzhLyiF25gB66bdVgxRCrCQYW3fgnys+UYDYRDMN7H7jVtUZHPp7ODvtlhn3U88BRyV/t
ZU5g2lm1IUB/+udpKIz/H+I1+W04CDkWQHZbMfSb0GSThwcuTebQO2izzz9vb0XrLpoHYM+ynV1P
UYmSHzFMvhU9Ea/JtakLOSMwAwovuOpFa8VhnWhY9eAZd/i1twl9wp+Y2oZBjmTddZqKoMEv3Mb/
c0z1gDHSg3scWh9gnFdhkm/6wXSCNKYbOL/7juK1EqaelwUKaWxxAdxbFY20+QuyRWsCrU4+x3WH
3U3j8/viRs9HrGJ67elwucNhKU4NeMHe3L4Sgilt6Mz1XfxSapcQQflSI2r/A0FhufMMpBQSdzDC
9rcF9CUMUSIxmydZcfSsgeedETICgXQLnhzUFT/uuEqEsKqoD5d3KCI6tTAn3IzCA9r1jvbR4eP9
HYNd9oDIW+YSJ1jZCBt3qwdqmM+oKJEGe3IGIguk1RHZfHZa1VwTuPbIS+uvjlsgI9FLoSouJSLN
YOcO4T5Of0EYTTi+yuJCcIZbLgNI9FUJvhpVkmesISDPRXI8ncf3ElGVypX69dsT2uITCA9TJ3pb
lFBFlbgH7GQdKnc+ijwDZ0XpKx99QkGM5U7Ca4MHB0GA0ezlS9HEKKAnLA6QCpfDzJcXPxDRGCZG
oh8Z6skDNCqEacyFl09oXhuyMUBoi/N+GbQXawzCzXIR5RNJYZKce2mFeP+MVkzMaHN0nXiP4gcM
T4EDzymvdbJse10RpYnVDkEK2MyO6G5Wcn6hW3izykGwSO7Vw1PNa1yk/wQOysamLmfedQRmsU5K
5CAe20ExNoYydHEg/tbuJZfsHB59O5JxkPmTz+rK8sj0cc3p+/kSJEFRpWROfcxeurH9cGN9q6ep
lom7ZGxHMGOp6l2QXAaYLcNKgi708l6yO/Hbs6FwHbjdudV6G8kMUkl9y9oZvU/8obHzypGXtO7l
DPDj8I2nM9dbvrYHPfj6+Al508Q5cLGQeRM6clPEciG7UgolecexoTcli9TjiZ9E8hDiu5qPvp0P
3vAlC0LvwcWhFieUz78P/JRb4qry1XmspKuWjf5TX8hSo9LSES/V9GAv4lbNCdGl3bskjQywTUPL
ZNI0tEAzb4VFWxc3FZse7my+/L/6X0wwq2351O5fRl1t24L4N/ZdDKf55HqGddN8bnCRhvn7vkit
LYJhiT9RASOaUS+MWg54mSULSeJgUZ+xYjdOYp/qwbQfszHBCSAlFVdALnuoe6h5bGx3vezz0Wyq
rYHeEvOlUk9Crt41sncKBprCMur2MhGO/kRwGQ2LfOdECX/6+AoV3j6gpopQSLBxoEhqf5oIPL8Q
S6lnGiQTmYdyUbvrUcpF9h8fnLIPBeaRuRdHDljrck65nrl3OnfajqZKnHbYfw076oFtnxsbMYqI
Yud5kwmZ47ch5rg6CXyikZ2R1qeksHxrs79fw0G8kkPr1JuZdsu+gmiGYrYz8B06u99GhuZ6KUyH
Ws7FvTa/bV6TLsLGiXuVxd8J5/uJi092RVgX9++/h3BBUHtpZYEWgHol3l/WFHgrBZxV/oskFAH3
d8ewFHr86Oq4w2Snf/57twnuEqFIgZ62I3YjVvkHkMZBI/DAt4VH42fMfK/xJBb3nGr9qAITHakw
tEK9L/uBUBqDedOwH2qccHVYJGKnOF+34x6GA7zMIuLKUnvgx3AJnHSfU1VwUi94JCYiPI1mdxTj
mZ79+Cgm59owmXgMUT4V7FFxRZbqV73g/lrDnsI1VJfpbllvmIfX68/IDSJ7wTsr4eo7DsWJ+hfF
pzeRWMue4sgq50j33acw5GzMGTU1IHu9QStgA38Llea48Ud+e5FOlqUQyGJoNoaYEuTWo2tLFCV+
WLU0N7RW3vUsd77+dmiFX2fLyTjnXJwxEo3KPDJzY/mzLG/pAKiqJZ0f15p3c+Asj0RhhBfe2lhM
AKghiiM1PuzcKlqIzevdTD825je7sWlKcohgdkr8byLB6Sy1Azlj3exvIxsUsLflLCRS3DoWIWsp
Trir9qjxm6Ew+mMl6KdYxwos8OlMerLlG/7coB+8u8swzoH4B+Pwxb5BLtcWMkflgwx3nUAgAUPs
n0Pr8BglhCzYGLiER7zt/9s7MI5/LhyR81EfIlgbvGTtkh1zkve+75KFrrEB0rf4kICHLjKbnofj
fHn0rAQUGEg1MC7uKQdHDk2+j2p5QWRrBeiwm+hPiAbC6AlIbpZZojpu722Om11gH5Z2kmPfUIoj
ezDB5ukI0CC0ee++4G9o2i076/N8tyXg4uzX4/Q/M4MukMgS2a82TfQN+Zuw00K41uY/KRFoDPI5
lg+NNgsMsMoC/72uAjDUHUy6gyRTS6QgarR20w64LFeUUEas9vlVBSDVQz1ls6XNYyYsB3hxqGJ7
oxFNbOgdM7H5Y/NUSJcKyHz49sHYF0u6+fL7advdw3NYYVLEOdnGqQVQwTE61gbVi2lNThSreEKd
/pLxzfvGNHdNVN/lj2x80XxogRin74hf3A5T9yb9R9TPR48ijB7y7+8c7zJM3GyfoXL437v1HUpT
v8OFFgHnbWFUd7d3QwmQtEH/rZb2pSermvChxBJUaJBnQpEIjUt50j++sm1FY1zhl2nfADnGW5jB
OP0NVhn6ZsZ8glMe2tDX0iJDLWTdTgu7qipzRXHli9K9XDN6+SkmJ38wp06vsp5wOA481D2LhfyT
MeoiR4MPhM2ExBypCNT5lgyqPASQqpfS6jkI4sXLP/v06lqbiQbh9fNeLRSxaoLFsGaKLykLtrvQ
N1l4Dr+K09zYYS+HrahXnAXTgGUDdoMVUYZO2R9LTcKQKOmPm7FUmyM0z8UWHEQXBcicWL8D//e/
unvdCk97iIpJ5afVQALW23RTMwcytjHnGLjf66D/msnUzvJWH2pFx8qDVTc8cdQHAdNuztAODjG/
j7MhRopqiJ4eJydHxcaW8duyWFsYbdq84VfWJemvA+OS+Q37CGOp2HlBNlcA2o8N8jviBLY5wgwu
MHTZXKzjn+0i1PiEs9XbF5/LkOXUmcwrQHI34oQJgdw4pdMmKzn2KrkKIzrwDhufLjQ1tam0JCxK
/bBQT9LTUSjalcPUkz87PQx8tbaNKcJZeYWqLPabW7/v22xC3dpe7LJBu4btEnIsVO6ik131J2N8
/1zyj0ijHeiNI4FZw67kbCCIOqaPf+9Vo4b6oYTt4pYqj70s2a0aoPZzKgl7rUEp93D+BkKTD/Bm
en1ZpWdJlfuSWD77kN/tcW34ZNE+B+rMAU8KPqWbIyGD3yXI93JMn06hR6OXaJvadp8u0zBUFC7w
xulqoZgc+mbdYYoTQhwa0hAuhRunzBeU6wiwdWCuD6ruB8QNlFzzH39QavpeVX7WoUjck0DjnNgZ
TLPWTo1/4ruJFWugafHYi7TKSnB2W69YmuOF8+pgZq9L/MN+rgscskP7jmKZg+pgzTvWPsq/KRdb
XcqANhFMCxh/fwuFmCf5YiGtLm7izTRanS+Qr6mbuDJm61VVz7HWIUzGIssEHVkgC7MdZ5UAQhZy
3ttMNu8QZLHpRfquICYtkPiU9bCZZJmkKMtLYxtKZ63yWK2SBo6e88sLG5/3TDOdXowmEGiENAvj
tTAIrDrJkpDkS7ysdPY7kgI8r1fNEwmGh1YeuFRBIGVqA3KUisYHJ97aEms83WXekFvApst2NHjS
KMzsEpIVGn2dzZb/aNZkBuORFsM7NGrvZOxIQSWgCfD5W/VS7ZHn1SF94qdliRmPwjwR7FHSqUkm
oKQtsqD4DzagpESpxD+PX2IxiuExDFmx0CWKJ9ZQlijUmgqALhnLXJhFBPNWMTeXtUgbI9WKimFI
jhLqGensLDkdtP+ReBBxpaT7Lcb5yUPd3Bf1qXsDfY5eAkW/xbn/RIyNpSffhdjpUZEO8Ox1ILea
6P6tJBm3I2bsl6qcM+caQGRYjIqZtT1xHZ8vuOfv3UsCd+mHq2K4Ja9Sk3L76VAUJFXYkQPpabVV
enktzccg8cvmZczwQqhCkwJ+ndAWajBEXaB05UgwkKzI/u7ZtkvbakzI5L6E5okPuvVvTRcwKcYm
LnsGKvlj56dNUZPoBmTlwYecCArUyNmieoaNESR8M0QkL5HK36nsTE4XBcQbfERI8bk17etZPJPL
8VaWicfAKu/XcCvzd5npGEe9mlQaH4ylRLACtp7896w1XUU1H0+NiliYo3Znkhn7gB060A8txhan
3l600Z/KvOpNXgP454dzeFo+Gs+bj80IppEq/kOGwIDT9b4mrycG1tXlyGvEoc5WPT/jRDlsmJNm
+dFsvsVZBrKBbEaswt/cm5IIWJwmr4GpEjRxIxI9ssGl8mHojoC879sVickOtiSow77cpehY+prg
Km4NcsvcKzeU2yOKSymDeWSUkEtlRKaLLgsK6iCdCQ3evo0D9Ik1Ba87U21KZgfVlbDuidoVlYbk
aZvh4Yyk+RJj6pKs3U4vZ9IWypLSJUx4Ece8An63Qas9orkXbmoW3nhe8hVlszTs95ua3uyOvtQO
JN6uHyPlYtQ4wiBpxUciI5bNc1TJvuLikgzZ/ATkW/bS9LJHBaXP+Uvl7NVrmi1RIKKscN2ppycD
suPYOblsS3nZlVfBXCZUJPh9yRWYPqrnjgh/V/2BdzzRBlWhQwFLRxMk/b1Rj6acq+UkSUo6aw==
`protect end_protected
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Fri Jul 8 09:01:52 2016
-- Host : jalapeno running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim {/home/hhassan/git/GateKeeper/FPGA
-- Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/pcie_recv_fifo_sim_netlist.vhdl}
-- Design : pcie_recv_fifo
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7vx690tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_blk_mem_gen_prim_wrapper is
port (
D : out STD_LOGIC_VECTOR ( 71 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
srst : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 71 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end pcie_recv_fifo_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of pcie_recv_fifo_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 6) => \gc0.count_d1_reg[8]\(8 downto 0),
ADDRARDADDR(5 downto 0) => B"111111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 6) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ADDRBWRADDR(5 downto 0) => B"111111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 24) => din(70 downto 63),
DIBDI(23 downto 16) => din(61 downto 54),
DIBDI(15 downto 8) => din(52 downto 45),
DIBDI(7 downto 0) => din(43 downto 36),
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3) => din(71),
DIPBDIP(2) => din(62),
DIPBDIP(1) => din(53),
DIPBDIP(0) => din(44),
DOADO(31 downto 24) => D(34 downto 27),
DOADO(23 downto 16) => D(25 downto 18),
DOADO(15 downto 8) => D(16 downto 9),
DOADO(7 downto 0) => D(7 downto 0),
DOBDO(31 downto 24) => D(70 downto 63),
DOBDO(23 downto 16) => D(61 downto 54),
DOBDO(15 downto 8) => D(52 downto 45),
DOBDO(7 downto 0) => D(43 downto 36),
DOPADOP(3) => D(35),
DOPADOP(2) => D(26),
DOPADOP(1) => D(17),
DOPADOP(0) => D(8),
DOPBDOP(3) => D(71),
DOPBDOP(2) => D(62),
DOPBDOP(1) => D(53),
DOPBDOP(0) => D(44),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => tmp_ram_rd_en,
ENBWREN => ram_full_fb_i_reg(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => srst,
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7) => ram_full_fb_i_reg(0),
WEBWE(6) => ram_full_fb_i_reg(0),
WEBWE(5) => ram_full_fb_i_reg(0),
WEBWE(4) => ram_full_fb_i_reg(0),
WEBWE(3) => ram_full_fb_i_reg(0),
WEBWE(2) => ram_full_fb_i_reg(0),
WEBWE(1) => ram_full_fb_i_reg(0),
WEBWE(0) => ram_full_fb_i_reg(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \pcie_recv_fifo_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 55 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
srst : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 55 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \pcie_recv_fifo_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \pcie_recv_fifo_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \pcie_recv_fifo_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_61\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_69\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 6) => \gc0.count_d1_reg[8]\(8 downto 0),
ADDRARDADDR(5 downto 0) => B"111111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 6) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ADDRBWRADDR(5 downto 0) => B"111111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30 downto 24) => din(27 downto 21),
DIADI(23) => '0',
DIADI(22 downto 16) => din(20 downto 14),
DIADI(15) => '0',
DIADI(14 downto 8) => din(13 downto 7),
DIADI(7) => '0',
DIADI(6 downto 0) => din(6 downto 0),
DIBDI(31) => '0',
DIBDI(30 downto 24) => din(55 downto 49),
DIBDI(23) => '0',
DIBDI(22 downto 16) => din(48 downto 42),
DIBDI(15) => '0',
DIBDI(14 downto 8) => din(41 downto 35),
DIBDI(7) => '0',
DIBDI(6 downto 0) => din(34 downto 28),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_21\,
DOADO(30 downto 24) => D(27 downto 21),
DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_29\,
DOADO(22 downto 16) => D(20 downto 14),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37\,
DOADO(14 downto 8) => D(13 downto 7),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45\,
DOADO(6 downto 0) => D(6 downto 0),
DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53\,
DOBDO(30 downto 24) => D(55 downto 49),
DOBDO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_61\,
DOBDO(22 downto 16) => D(48 downto 42),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_69\,
DOBDO(14 downto 8) => D(41 downto 35),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_77\,
DOBDO(6 downto 0) => D(34 downto 28),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\,
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => tmp_ram_rd_en,
ENBWREN => ram_full_fb_i_reg(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => srst,
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7) => ram_full_fb_i_reg(0),
WEBWE(6) => ram_full_fb_i_reg(0),
WEBWE(5) => ram_full_fb_i_reg(0),
WEBWE(4) => ram_full_fb_i_reg(0),
WEBWE(3) => ram_full_fb_i_reg(0),
WEBWE(2) => ram_full_fb_i_reg(0),
WEBWE(1) => ram_full_fb_i_reg(0),
WEBWE(0) => ram_full_fb_i_reg(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_compare is
port (
ram_full_i : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
srst : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_compare : entity is "compare";
end pcie_recv_fifo_compare;
architecture STRUCTURE of pcie_recv_fifo_compare is
signal comp0 : STD_LOGIC;
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_d1_reg[8]\(0)
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0707070703000000"
)
port map (
I0 => comp0,
I1 => E(0),
I2 => srst,
I3 => comp1,
I4 => wr_en,
I5 => p_1_out,
O => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_compare_0 : entity is "compare";
end pcie_recv_fifo_compare_0;
architecture STRUCTURE of pcie_recv_fifo_compare_0 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_compare_1 is
port (
ram_empty_fb_i : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
p_2_out : in STD_LOGIC;
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_compare_1 : entity is "compare";
end pcie_recv_fifo_compare_1;
architecture STRUCTURE of pcie_recv_fifo_compare_1 is
signal comp0 : STD_LOGIC;
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFAF2F2FAFAF2F2"
)
port map (
I0 => p_2_out,
I1 => comp0,
I2 => srst,
I3 => E(0),
I4 => ram_full_fb_i_reg,
I5 => comp1,
O => ram_empty_fb_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_compare_2 is
port (
comp1 : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_compare_2 : entity is "compare";
end pcie_recv_fifo_compare_2;
architecture STRUCTURE of pcie_recv_fifo_compare_2 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => \gcc0.gc0.count_d1_reg[6]\(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_full_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_rd_bin_cntr : entity is "rd_bin_cntr";
end pcie_recv_fifo_rd_bin_cntr;
architecture STRUCTURE of pcie_recv_fifo_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 8 to 8 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair3";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8 downto 0);
Q(7 downto 0) <= \^q\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \gc0.count[8]_i_2_n_0\,
I1 => \^q\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[8]_i_2_n_0\,
I2 => \^q\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[8]_i_2_n_0\,
I2 => \^q\(6),
I3 => rd_pntr_plus1(8),
O => plusOp(8)
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
R => srst
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
R => srst
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
R => srst
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
R => srst
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
R => srst
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
R => srst
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
R => srst
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
R => srst
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => rd_pntr_plus1(8),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8),
R => srst
);
\gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
Q => \^q\(0),
S => srst
);
\gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(1),
Q => \^q\(1),
R => srst
);
\gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(2),
Q => \^q\(2),
R => srst
);
\gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(3),
Q => \^q\(3),
R => srst
);
\gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(4),
Q => \^q\(4),
R => srst
);
\gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(5),
Q => \^q\(5),
R => srst
);
\gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(6),
Q => \^q\(6),
R => srst
);
\gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(7),
Q => \^q\(7),
R => srst
);
\gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(8),
Q => rd_pntr_plus1(8),
R => srst
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I1 => \gcc0.gc0.count_reg[8]\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I3 => \gcc0.gc0.count_reg[8]\(1),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
I1 => \gcc0.gc0.count_reg[8]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
I3 => \gcc0.gc0.count_reg[8]\(3),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
I1 => \gcc0.gc0.count_reg[8]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
I3 => \gcc0.gc0.count_reg[8]\(5),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
I1 => \gcc0.gc0.count_reg[8]\(6),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
I3 => \gcc0.gc0.count_reg[8]\(7),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => ram_full_i_reg(0)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => v1_reg_0(0)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8),
I1 => \gcc0.gc0.count_reg[8]\(8),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_rd_fwft is
port (
empty : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_bm.dout_i_reg[127]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
p_2_out : in STD_LOGIC;
rd_en : in STD_LOGIC;
srst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_rd_fwft : entity is "rd_fwft";
end pcie_recv_fifo_rd_fwft;
architecture STRUCTURE of pcie_recv_fifo_rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_fb_reg_n_0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state[0]_i_1_n_0\ : STD_LOGIC;
signal \gpregsm1.curr_fwft_state[1]_i_1_n_0\ : STD_LOGIC;
signal \gpregsm1.curr_fwft_state_reg_n_0_[1]\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair0";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair1";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF4555"
)
port map (
I0 => p_2_out,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I4 => srst,
O => tmp_ram_rd_en
);
empty_fwft_fb_reg: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_fb,
Q => empty_fwft_fb_reg_n_0,
R => '0'
);
empty_fwft_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FAF0FFF8"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => srst,
I3 => empty_fwft_fb_reg_n_0,
I4 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => empty_fwft_fb
);
empty_fwft_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_fb,
Q => empty,
R => '0'
);
\gc0.count_d1[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0B0F"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => p_2_out,
I3 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => E(0)
);
\goreg_bm.dout_i[127]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => \goreg_bm.dout_i_reg[127]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00F2"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I3 => srst,
O => \gpregsm1.curr_fwft_state[0]_i_1_n_0\
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002F0F"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => p_2_out,
I3 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I4 => srst,
O => \gpregsm1.curr_fwft_state[1]_i_1_n_0\
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \gpregsm1.curr_fwft_state[0]_i_1_n_0\,
Q => curr_fwft_state(0),
R => '0'
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \gpregsm1.curr_fwft_state[1]_i_1_n_0\,
Q => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_reset_blk_ramfifo is
port (
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end pcie_recv_fifo_reset_blk_ramfifo;
architecture STRUCTURE of pcie_recv_fifo_reset_blk_ramfifo is
signal inverted_reset : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
begin
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => inverted_reset,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => inverted_reset,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => inverted_reset
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_wr_bin_cntr : entity is "wr_bin_cntr";
end pcie_recv_fifo_wr_bin_cntr;
architecture STRUCTURE of pcie_recv_fifo_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gcc0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair6";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8 downto 0);
Q(8 downto 0) <= \^q\(8 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \gcc0.gc0.count[8]_i_2_n_0\,
I1 => \^q\(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^q\(6),
I1 => \gcc0.gc0.count[8]_i_2_n_0\,
I2 => \^q\(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \^q\(7),
I1 => \gcc0.gc0.count[8]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gcc0.gc0.count[8]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
R => srst
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
R => srst
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
R => srst
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
R => srst
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
R => srst
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
R => srst
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
R => srst
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
R => srst
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(8),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8),
R => srst
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
Q => \^q\(0),
S => srst
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(1),
Q => \^q\(1),
R => srst
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(2),
Q => \^q\(2),
R => srst
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(3),
Q => \^q\(3),
R => srst
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(4),
Q => \^q\(4),
R => srst
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(5),
Q => \^q\(5),
R => srst
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(6),
Q => \^q\(6),
R => srst
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(7),
Q => \^q\(7),
R => srst
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(8),
Q => \^q\(8),
R => srst
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I1 => \gc0.count_d1_reg[7]\(1),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I3 => \gc0.count_d1_reg[7]\(0),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I1 => \gc0.count_d1_reg[7]\(1),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I3 => \gc0.count_d1_reg[7]\(0),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I1 => \gc0.count_reg[7]\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I3 => \gc0.count_reg[7]\(1),
O => ram_empty_fb_i_reg(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
I1 => \gc0.count_d1_reg[7]\(3),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
I3 => \gc0.count_d1_reg[7]\(2),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
I1 => \gc0.count_d1_reg[7]\(3),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
I3 => \gc0.count_d1_reg[7]\(2),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
I1 => \gc0.count_reg[7]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
I3 => \gc0.count_reg[7]\(3),
O => ram_empty_fb_i_reg(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
I1 => \gc0.count_d1_reg[7]\(5),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
I3 => \gc0.count_d1_reg[7]\(4),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
I1 => \gc0.count_d1_reg[7]\(5),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
I3 => \gc0.count_d1_reg[7]\(4),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
I1 => \gc0.count_reg[7]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
I3 => \gc0.count_reg[7]\(5),
O => ram_empty_fb_i_reg(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
I1 => \gc0.count_d1_reg[7]\(7),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
I3 => \gc0.count_d1_reg[7]\(6),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
I1 => \gc0.count_d1_reg[7]\(7),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
I3 => \gc0.count_d1_reg[7]\(6),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
I1 => \gc0.count_reg[7]\(6),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
I3 => \gc0.count_reg[7]\(7),
O => ram_empty_fb_i_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_blk_mem_gen_prim_width is
port (
D : out STD_LOGIC_VECTOR ( 71 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
srst : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 71 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end pcie_recv_fifo_blk_mem_gen_prim_width;
architecture STRUCTURE of pcie_recv_fifo_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.pcie_recv_fifo_blk_mem_gen_prim_wrapper
port map (
D(71 downto 0) => D(71 downto 0),
clk => clk,
din(71 downto 0) => din(71 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \pcie_recv_fifo_blk_mem_gen_prim_width__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 55 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
srst : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 55 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \pcie_recv_fifo_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \pcie_recv_fifo_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \pcie_recv_fifo_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\pcie_recv_fifo_blk_mem_gen_prim_wrapper__parameterized0\
port map (
D(55 downto 0) => D(55 downto 0),
clk => clk,
din(55 downto 0) => din(55 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_rd_status_flags_ss is
port (
p_2_out : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_rd_status_flags_ss : entity is "rd_status_flags_ss";
end pcie_recv_fifo_rd_status_flags_ss;
architecture STRUCTURE of pcie_recv_fifo_rd_status_flags_ss is
signal comp1 : STD_LOGIC;
signal \^p_2_out\ : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
p_2_out <= \^p_2_out\;
c1: entity work.pcie_recv_fifo_compare_1
port map (
E(0) => E(0),
comp1 => comp1,
\gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]\,
p_2_out => \^p_2_out\,
ram_empty_fb_i => ram_empty_fb_i,
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0)
);
c2: entity work.pcie_recv_fifo_compare_2
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[6]\(3 downto 0) => \gcc0.gc0.count_d1_reg[6]\(3 downto 0),
v1_reg(0) => v1_reg(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i,
Q => \^p_2_out\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_wr_status_flags_ss is
port (
full : out STD_LOGIC;
\gcc0.gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
srst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_wr_status_flags_ss : entity is "wr_status_flags_ss";
end pcie_recv_fifo_wr_status_flags_ss;
architecture STRUCTURE of pcie_recv_fifo_wr_status_flags_ss is
signal comp1 : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal ram_full_i : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => p_1_out,
O => \gcc0.gc0.count_reg[0]\(0)
);
c0: entity work.pcie_recv_fifo_compare
port map (
E(0) => E(0),
comp1 => comp1,
\gc0.count_d1_reg[8]\(0) => \gc0.count_d1_reg[8]\(0),
p_1_out => p_1_out,
ram_full_i => ram_full_i,
srst => srst,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
wr_en => wr_en
);
c1: entity work.pcie_recv_fifo_compare_0
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => p_1_out,
I1 => wr_en,
O => ram_empty_fb_i_reg
);
ram_full_fb_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => ram_full_i,
Q => p_1_out,
R => '0'
);
ram_full_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => ram_full_i,
Q => full,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_blk_mem_gen_generic_cstr is
port (
D : out STD_LOGIC_VECTOR ( 127 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
srst : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end pcie_recv_fifo_blk_mem_gen_generic_cstr;
architecture STRUCTURE of pcie_recv_fifo_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.pcie_recv_fifo_blk_mem_gen_prim_width
port map (
D(71 downto 0) => D(71 downto 0),
clk => clk,
din(71 downto 0) => din(71 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[1].ram.r\: entity work.\pcie_recv_fifo_blk_mem_gen_prim_width__parameterized0\
port map (
D(55 downto 0) => D(127 downto 72),
clk => clk,
din(55 downto 0) => din(127 downto 72),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_rd_logic is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
\goreg_bm.dout_i_reg[127]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_full_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
srst : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_rd_logic : entity is "rd_logic";
end pcie_recv_fifo_rd_logic;
architecture STRUCTURE of pcie_recv_fifo_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 to 4 );
signal p_2_out : STD_LOGIC;
signal rpntr_n_24 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.rfwft\: entity work.pcie_recv_fifo_rd_fwft
port map (
E(0) => \^e\(0),
clk => clk,
empty => empty,
\goreg_bm.dout_i_reg[127]\(0) => \goreg_bm.dout_i_reg[127]\(0),
p_2_out => p_2_out,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\grss.rsts\: entity work.pcie_recv_fifo_rd_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
\gc0.count_d1_reg[8]\ => rpntr_n_24,
\gcc0.gc0.count_d1_reg[6]\(3 downto 0) => \gcc0.gc0.count_d1_reg[6]\(3 downto 0),
p_2_out => p_2_out,
ram_full_fb_i_reg => ram_full_fb_i_reg,
srst => srst,
v1_reg(0) => \c2/v1_reg\(4),
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0)
);
rpntr: entity work.pcie_recv_fifo_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0),
E(0) => \^e\(0),
Q(7 downto 0) => Q(7 downto 0),
clk => clk,
\gcc0.gc0.count_d1_reg[8]\(0) => \gcc0.gc0.count_d1_reg[8]\(0),
\gcc0.gc0.count_reg[8]\(8 downto 0) => \gcc0.gc0.count_reg[8]\(8 downto 0),
ram_empty_fb_i_reg => rpntr_n_24,
ram_full_i_reg(0) => ram_full_i_reg(0),
srst => srst,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(0) => \c2/v1_reg\(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_wr_logic is
port (
full : out STD_LOGIC;
\gcc0.gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
srst : in STD_LOGIC;
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_wr_logic : entity is "wr_logic";
end pcie_recv_fifo_wr_logic;
architecture STRUCTURE of pcie_recv_fifo_wr_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gcc0.gc0.count_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gcc0.gc0.count_reg[0]\(0) <= \^gcc0.gc0.count_reg[0]\(0);
\gwss.wsts\: entity work.pcie_recv_fifo_wr_status_flags_ss
port map (
E(0) => E(0),
clk => clk,
full => full,
\gc0.count_d1_reg[8]\(0) => \gc0.count_d1_reg[8]\(0),
\gcc0.gc0.count_reg[0]\(0) => \^gcc0.gc0.count_reg[0]\(0),
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
srst => srst,
v1_reg(3 downto 0) => \c0/v1_reg\(3 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0),
wr_en => wr_en
);
wpntr: entity work.pcie_recv_fifo_wr_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0),
E(0) => \^gcc0.gc0.count_reg[0]\(0),
Q(8 downto 0) => Q(8 downto 0),
clk => clk,
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gc0.count_reg[7]\(7 downto 0) => \gc0.count_reg[7]\(7 downto 0),
ram_empty_fb_i_reg(3 downto 0) => ram_empty_fb_i_reg_0(3 downto 0),
srst => srst,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
v1_reg_0(3 downto 0) => \c0/v1_reg\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_blk_mem_gen_top is
port (
D : out STD_LOGIC_VECTOR ( 127 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
srst : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_blk_mem_gen_top : entity is "blk_mem_gen_top";
end pcie_recv_fifo_blk_mem_gen_top;
architecture STRUCTURE of pcie_recv_fifo_blk_mem_gen_top is
begin
\valid.cstr\: entity work.pcie_recv_fifo_blk_mem_gen_generic_cstr
port map (
D(127 downto 0) => D(127 downto 0),
clk => clk,
din(127 downto 0) => din(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_blk_mem_gen_v8_3_1_synth is
port (
D : out STD_LOGIC_VECTOR ( 127 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
srst : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end pcie_recv_fifo_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of pcie_recv_fifo_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.pcie_recv_fifo_blk_mem_gen_top
port map (
D(127 downto 0) => D(127 downto 0),
clk => clk,
din(127 downto 0) => din(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_blk_mem_gen_v8_3_1 is
port (
D : out STD_LOGIC_VECTOR ( 127 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
srst : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
end pcie_recv_fifo_blk_mem_gen_v8_3_1;
architecture STRUCTURE of pcie_recv_fifo_blk_mem_gen_v8_3_1 is
begin
inst_blk_mem_gen: entity work.pcie_recv_fifo_blk_mem_gen_v8_3_1_synth
port map (
D(127 downto 0) => D(127 downto 0),
clk => clk,
din(127 downto 0) => din(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_memory is
port (
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
srst : in STD_LOGIC;
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_memory : entity is "memory";
end pcie_recv_fifo_memory;
architecture STRUCTURE of pcie_recv_fifo_memory is
signal doutb : STD_LOGIC_VECTOR ( 127 downto 0 );
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.pcie_recv_fifo_blk_mem_gen_v8_3_1
port map (
D(127 downto 0) => doutb(127 downto 0),
clk => clk,
din(127 downto 0) => din(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(0),
Q => dout(0),
R => srst
);
\goreg_bm.dout_i_reg[100]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(100),
Q => dout(100),
R => srst
);
\goreg_bm.dout_i_reg[101]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(101),
Q => dout(101),
R => srst
);
\goreg_bm.dout_i_reg[102]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(102),
Q => dout(102),
R => srst
);
\goreg_bm.dout_i_reg[103]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(103),
Q => dout(103),
R => srst
);
\goreg_bm.dout_i_reg[104]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(104),
Q => dout(104),
R => srst
);
\goreg_bm.dout_i_reg[105]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(105),
Q => dout(105),
R => srst
);
\goreg_bm.dout_i_reg[106]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(106),
Q => dout(106),
R => srst
);
\goreg_bm.dout_i_reg[107]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(107),
Q => dout(107),
R => srst
);
\goreg_bm.dout_i_reg[108]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(108),
Q => dout(108),
R => srst
);
\goreg_bm.dout_i_reg[109]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(109),
Q => dout(109),
R => srst
);
\goreg_bm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(10),
Q => dout(10),
R => srst
);
\goreg_bm.dout_i_reg[110]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(110),
Q => dout(110),
R => srst
);
\goreg_bm.dout_i_reg[111]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(111),
Q => dout(111),
R => srst
);
\goreg_bm.dout_i_reg[112]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(112),
Q => dout(112),
R => srst
);
\goreg_bm.dout_i_reg[113]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(113),
Q => dout(113),
R => srst
);
\goreg_bm.dout_i_reg[114]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(114),
Q => dout(114),
R => srst
);
\goreg_bm.dout_i_reg[115]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(115),
Q => dout(115),
R => srst
);
\goreg_bm.dout_i_reg[116]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(116),
Q => dout(116),
R => srst
);
\goreg_bm.dout_i_reg[117]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(117),
Q => dout(117),
R => srst
);
\goreg_bm.dout_i_reg[118]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(118),
Q => dout(118),
R => srst
);
\goreg_bm.dout_i_reg[119]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(119),
Q => dout(119),
R => srst
);
\goreg_bm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(11),
Q => dout(11),
R => srst
);
\goreg_bm.dout_i_reg[120]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(120),
Q => dout(120),
R => srst
);
\goreg_bm.dout_i_reg[121]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(121),
Q => dout(121),
R => srst
);
\goreg_bm.dout_i_reg[122]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(122),
Q => dout(122),
R => srst
);
\goreg_bm.dout_i_reg[123]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(123),
Q => dout(123),
R => srst
);
\goreg_bm.dout_i_reg[124]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(124),
Q => dout(124),
R => srst
);
\goreg_bm.dout_i_reg[125]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(125),
Q => dout(125),
R => srst
);
\goreg_bm.dout_i_reg[126]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(126),
Q => dout(126),
R => srst
);
\goreg_bm.dout_i_reg[127]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(127),
Q => dout(127),
R => srst
);
\goreg_bm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(12),
Q => dout(12),
R => srst
);
\goreg_bm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(13),
Q => dout(13),
R => srst
);
\goreg_bm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(14),
Q => dout(14),
R => srst
);
\goreg_bm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(15),
Q => dout(15),
R => srst
);
\goreg_bm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(16),
Q => dout(16),
R => srst
);
\goreg_bm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(17),
Q => dout(17),
R => srst
);
\goreg_bm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(18),
Q => dout(18),
R => srst
);
\goreg_bm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(19),
Q => dout(19),
R => srst
);
\goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(1),
Q => dout(1),
R => srst
);
\goreg_bm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(20),
Q => dout(20),
R => srst
);
\goreg_bm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(21),
Q => dout(21),
R => srst
);
\goreg_bm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(22),
Q => dout(22),
R => srst
);
\goreg_bm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(23),
Q => dout(23),
R => srst
);
\goreg_bm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(24),
Q => dout(24),
R => srst
);
\goreg_bm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(25),
Q => dout(25),
R => srst
);
\goreg_bm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(26),
Q => dout(26),
R => srst
);
\goreg_bm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(27),
Q => dout(27),
R => srst
);
\goreg_bm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(28),
Q => dout(28),
R => srst
);
\goreg_bm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(29),
Q => dout(29),
R => srst
);
\goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(2),
Q => dout(2),
R => srst
);
\goreg_bm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(30),
Q => dout(30),
R => srst
);
\goreg_bm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(31),
Q => dout(31),
R => srst
);
\goreg_bm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(32),
Q => dout(32),
R => srst
);
\goreg_bm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(33),
Q => dout(33),
R => srst
);
\goreg_bm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(34),
Q => dout(34),
R => srst
);
\goreg_bm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(35),
Q => dout(35),
R => srst
);
\goreg_bm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(36),
Q => dout(36),
R => srst
);
\goreg_bm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(37),
Q => dout(37),
R => srst
);
\goreg_bm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(38),
Q => dout(38),
R => srst
);
\goreg_bm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(39),
Q => dout(39),
R => srst
);
\goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(3),
Q => dout(3),
R => srst
);
\goreg_bm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(40),
Q => dout(40),
R => srst
);
\goreg_bm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(41),
Q => dout(41),
R => srst
);
\goreg_bm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(42),
Q => dout(42),
R => srst
);
\goreg_bm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(43),
Q => dout(43),
R => srst
);
\goreg_bm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(44),
Q => dout(44),
R => srst
);
\goreg_bm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(45),
Q => dout(45),
R => srst
);
\goreg_bm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(46),
Q => dout(46),
R => srst
);
\goreg_bm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(47),
Q => dout(47),
R => srst
);
\goreg_bm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(48),
Q => dout(48),
R => srst
);
\goreg_bm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(49),
Q => dout(49),
R => srst
);
\goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(4),
Q => dout(4),
R => srst
);
\goreg_bm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(50),
Q => dout(50),
R => srst
);
\goreg_bm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(51),
Q => dout(51),
R => srst
);
\goreg_bm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(52),
Q => dout(52),
R => srst
);
\goreg_bm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(53),
Q => dout(53),
R => srst
);
\goreg_bm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(54),
Q => dout(54),
R => srst
);
\goreg_bm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(55),
Q => dout(55),
R => srst
);
\goreg_bm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(56),
Q => dout(56),
R => srst
);
\goreg_bm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(57),
Q => dout(57),
R => srst
);
\goreg_bm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(58),
Q => dout(58),
R => srst
);
\goreg_bm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(59),
Q => dout(59),
R => srst
);
\goreg_bm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(5),
Q => dout(5),
R => srst
);
\goreg_bm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(60),
Q => dout(60),
R => srst
);
\goreg_bm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(61),
Q => dout(61),
R => srst
);
\goreg_bm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(62),
Q => dout(62),
R => srst
);
\goreg_bm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(63),
Q => dout(63),
R => srst
);
\goreg_bm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(64),
Q => dout(64),
R => srst
);
\goreg_bm.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(65),
Q => dout(65),
R => srst
);
\goreg_bm.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(66),
Q => dout(66),
R => srst
);
\goreg_bm.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(67),
Q => dout(67),
R => srst
);
\goreg_bm.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(68),
Q => dout(68),
R => srst
);
\goreg_bm.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(69),
Q => dout(69),
R => srst
);
\goreg_bm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(6),
Q => dout(6),
R => srst
);
\goreg_bm.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(70),
Q => dout(70),
R => srst
);
\goreg_bm.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(71),
Q => dout(71),
R => srst
);
\goreg_bm.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(72),
Q => dout(72),
R => srst
);
\goreg_bm.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(73),
Q => dout(73),
R => srst
);
\goreg_bm.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(74),
Q => dout(74),
R => srst
);
\goreg_bm.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(75),
Q => dout(75),
R => srst
);
\goreg_bm.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(76),
Q => dout(76),
R => srst
);
\goreg_bm.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(77),
Q => dout(77),
R => srst
);
\goreg_bm.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(78),
Q => dout(78),
R => srst
);
\goreg_bm.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(79),
Q => dout(79),
R => srst
);
\goreg_bm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(7),
Q => dout(7),
R => srst
);
\goreg_bm.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(80),
Q => dout(80),
R => srst
);
\goreg_bm.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(81),
Q => dout(81),
R => srst
);
\goreg_bm.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(82),
Q => dout(82),
R => srst
);
\goreg_bm.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(83),
Q => dout(83),
R => srst
);
\goreg_bm.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(84),
Q => dout(84),
R => srst
);
\goreg_bm.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(85),
Q => dout(85),
R => srst
);
\goreg_bm.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(86),
Q => dout(86),
R => srst
);
\goreg_bm.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(87),
Q => dout(87),
R => srst
);
\goreg_bm.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(88),
Q => dout(88),
R => srst
);
\goreg_bm.dout_i_reg[89]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(89),
Q => dout(89),
R => srst
);
\goreg_bm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(8),
Q => dout(8),
R => srst
);
\goreg_bm.dout_i_reg[90]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(90),
Q => dout(90),
R => srst
);
\goreg_bm.dout_i_reg[91]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(91),
Q => dout(91),
R => srst
);
\goreg_bm.dout_i_reg[92]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(92),
Q => dout(92),
R => srst
);
\goreg_bm.dout_i_reg[93]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(93),
Q => dout(93),
R => srst
);
\goreg_bm.dout_i_reg[94]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(94),
Q => dout(94),
R => srst
);
\goreg_bm.dout_i_reg[95]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(95),
Q => dout(95),
R => srst
);
\goreg_bm.dout_i_reg[96]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(96),
Q => dout(96),
R => srst
);
\goreg_bm.dout_i_reg[97]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(97),
Q => dout(97),
R => srst
);
\goreg_bm.dout_i_reg[98]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(98),
Q => dout(98),
R => srst
);
\goreg_bm.dout_i_reg[99]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(99),
Q => dout(99),
R => srst
);
\goreg_bm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => doutb(9),
Q => dout(9),
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_fifo_generator_ramfifo is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end pcie_recv_fifo_fifo_generator_ramfifo;
architecture STRUCTURE of pcie_recv_fifo_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \grss.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gwss.wsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_10_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_16_out : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.pcie_recv_fifo_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => p_0_out(8 downto 0),
E(0) => p_6_out,
Q(7 downto 0) => rd_pntr_plus1(7 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[6]\(3 downto 0) => \grss.rsts/c2/v1_reg\(3 downto 0),
\gcc0.gc0.count_d1_reg[8]\(0) => p_10_out(8),
\gcc0.gc0.count_reg[8]\(8 downto 0) => p_11_out(8 downto 0),
\goreg_bm.dout_i_reg[127]\(0) => p_5_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
ram_full_i_reg(0) => \grss.rsts/c1/v1_reg\(4),
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => \gwss.wsts/c1/v1_reg\(4 downto 0),
v1_reg_0(3 downto 0) => \grss.rsts/c1/v1_reg\(3 downto 0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.pcie_recv_fifo_wr_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => p_10_out(8 downto 0),
E(0) => p_6_out,
Q(8 downto 0) => p_11_out(8 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[7]\(7 downto 0) => p_0_out(7 downto 0),
\gc0.count_d1_reg[8]\(0) => \grss.rsts/c1/v1_reg\(4),
\gc0.count_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
\gcc0.gc0.count_reg[0]\(0) => p_16_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
ram_empty_fb_i_reg_0(3 downto 0) => \grss.rsts/c2/v1_reg\(3 downto 0),
srst => srst,
v1_reg(3 downto 0) => \grss.rsts/c1/v1_reg\(3 downto 0),
v1_reg_0(4 downto 0) => \gwss.wsts/c1/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.pcie_recv_fifo_memory
port map (
E(0) => p_5_out,
clk => clk,
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => p_0_out(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => p_10_out(8 downto 0),
ram_full_fb_i_reg(0) => p_16_out,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_fifo_generator_top is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_fifo_generator_top : entity is "fifo_generator_top";
end pcie_recv_fifo_fifo_generator_top;
architecture STRUCTURE of pcie_recv_fifo_fifo_generator_top is
begin
\grf.rf\: entity work.pcie_recv_fifo_fifo_generator_ramfifo
port map (
clk => clk,
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_fifo_generator_v13_0_1_synth is
port (
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_aclk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_fifo_generator_v13_0_1_synth : entity is "fifo_generator_v13_0_1_synth";
end pcie_recv_fifo_fifo_generator_v13_0_1_synth;
architecture STRUCTURE of pcie_recv_fifo_fifo_generator_v13_0_1_synth is
begin
\gconvfifo.rf\: entity work.pcie_recv_fifo_fifo_generator_top
port map (
clk => clk,
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
\reset_gen_cc.rstblk_cc\: entity work.pcie_recv_fifo_reset_blk_ramfifo
port map (
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo_fifo_generator_v13_0_1 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 128;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 128;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is "virtex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 511;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 510;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of pcie_recv_fifo_fifo_generator_v13_0_1 : entity is "fifo_generator_v13_0_1";
end pcie_recv_fifo_fifo_generator_v13_0_1;
architecture STRUCTURE of pcie_recv_fifo_fifo_generator_v13_0_1 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.pcie_recv_fifo_fifo_generator_v13_0_1_synth
port map (
clk => clk,
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pcie_recv_fifo is
port (
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of pcie_recv_fifo : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of pcie_recv_fifo : entity is "pcie_recv_fifo,fifo_generator_v13_0_1,{}";
attribute core_generation_info : string;
attribute core_generation_info of pcie_recv_fifo : entity is "pcie_recv_fifo,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=128,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=128,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=511,C_PROG_FULL_THRESH_NEGATE_VAL=510,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of pcie_recv_fifo : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of pcie_recv_fifo : entity is "fifo_generator_v13_0_1,Vivado 2015.4";
end pcie_recv_fifo;
architecture STRUCTURE of pcie_recv_fifo is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 128;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 128;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "virtex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 511;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 510;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.pcie_recv_fifo_fifo_generator_v13_0_1
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(8 downto 0) => B"000000000",
prog_empty_thresh_assert(8 downto 0) => B"000000000",
prog_empty_thresh_negate(8 downto 0) => B"000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(8 downto 0) => B"000000000",
prog_full_thresh_assert(8 downto 0) => B"000000000",
prog_full_thresh_negate(8 downto 0) => B"000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => srst,
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc172.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00172ent IS
END c04s03b03x01p03n02i00172ent;
ARCHITECTURE c04s03b03x01p03n02i00172arch OF c04s03b03x01p03n02i00172ent IS
signal Data : integer;
alias SIGN2 : integer is Data; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
Data <= 100 after 50 ns;
wait for 50 ns;
assert NOT( SIGN2 = 100 )
report "***PASSED TEST: c04s03b03x01p03n02i00172" severity NOTE;
assert ( SIGN2 = 100 )
report "***FAILED TEST: c04s03b03x01p03n02i00172 - The base type of the name being defined by the declaration is the same as the base type of the subtype indication test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00172arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc172.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00172ent IS
END c04s03b03x01p03n02i00172ent;
ARCHITECTURE c04s03b03x01p03n02i00172arch OF c04s03b03x01p03n02i00172ent IS
signal Data : integer;
alias SIGN2 : integer is Data; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
Data <= 100 after 50 ns;
wait for 50 ns;
assert NOT( SIGN2 = 100 )
report "***PASSED TEST: c04s03b03x01p03n02i00172" severity NOTE;
assert ( SIGN2 = 100 )
report "***FAILED TEST: c04s03b03x01p03n02i00172 - The base type of the name being defined by the declaration is the same as the base type of the subtype indication test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00172arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc172.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00172ent IS
END c04s03b03x01p03n02i00172ent;
ARCHITECTURE c04s03b03x01p03n02i00172arch OF c04s03b03x01p03n02i00172ent IS
signal Data : integer;
alias SIGN2 : integer is Data; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
Data <= 100 after 50 ns;
wait for 50 ns;
assert NOT( SIGN2 = 100 )
report "***PASSED TEST: c04s03b03x01p03n02i00172" severity NOTE;
assert ( SIGN2 = 100 )
report "***FAILED TEST: c04s03b03x01p03n02i00172 - The base type of the name being defined by the declaration is the same as the base type of the subtype indication test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00172arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ELnJu6Vo0SI9GKpLvbyZsjxQDyRCBDXnwaI+OVt2A28orBT2jmAlQ4HKnfhVOxQ1HVQoM1tdoooV
yiFYqb+nOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
d595STmd5mP1KOtLaMHlwcurqj2ROaQRJTJ9JyLXkWbDy08rIse8hZd1A6jKM9XRFjiJTfchVgGL
HyQgFFro8kkxi3kcFfMYMrjfgmsBmzvIt0iZgRYFd8xpBrZcxlEz0jGB9JrVJlc9kFtlsuthla4/
XeEPM/M4NQ1NW0i4bUI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
aCiwj/c6RBs2QYQzQfbPjqMfXZi7CBiAoY3ecZ+BXROFvW1foaeKNmymX3/NbqLmwI+aVfcBuWfM
82qMdBughbvY91TNnmd20fs4X9sRAfMMNXm+STuoU0CGS15RLE8mCvB6FK40VuhV3DuBowJpCwhu
qttGfdt4FzOaiqM9YJVY++rI01UEPJcY9Dzu4Kb6BFrZEeWJ3iKows5wz9Aqt+78q6jzGFkn5R7D
JYSXM48tEmgrz8rcCJtB9+hr80LrADRvsyaBnwj/1YzlLziNHfDtnwH8Av66LZCCbg39v0BLA/1E
MyWY7eN5kcBSao+3m8Oo1qva1poQUc0UPcoR2Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
rt8qeqigKmHwNHNLDxKbJcBQ9QDjdSevpojXqtzOPOHihRQJ4iBxigwNdpHstCOFVBMqIX82UPZK
l5Z3voAz3pFaYq7dr6oHiV7oq2E0rQM5Uxhnfh46Zli/JIaRIpWf8EncPdKldj2Uf0AHq4/QV7y3
XqpPRbNfHQDneXeaciU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
lg1zM5+6ggCKkgN3qoxCvPMtnbR0lY9lPu4zV4wzZcs+UL0W1Cg00gE/3G329vCSQVnp5DAgqrYF
es9zj02SoPbANFlroyCxQjvn6Mf7ymspo+yMZhpWKlCutMCGBCKG6yQvEkkOWmJ1a/jofMJXUStD
P5832qeWGes85Bq1B9G9RJF00xScbF9hcS/9D3oCqiqCAHxxSC7iLsa2pqMcYRqQZG+qNYT6voBG
fplyLOfpmy0SbXo5116wxuki/c2xyUWMwOY5ZZScyTqrkXLycHyLaxvyh2vne5p5V5Q073iE+Nua
YsJxRHqAz8BYbH/Qqr41Ph21S2M4ldPL/JaM3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5904)
`protect data_block
lqHYkpxMxolz7h2fUWZoITda5XUgseMfPJZ/qQ9hmk7NApiNxHPZ4WI5cHcShW19oa8bTx2b9T7h
QmQlusU7GKx6vqF/E8Wg4FDyViOa/z9Ds1oPXmAq0H6lT44QOq8LuP/HaYu8vQF6KMEabMq7EGLv
GMpQlnkgTbW+AxVDtL0wXNwCy4Bon307HXof0rtzMdq6OjyPovXPty2n07/66jgTk+B/xyzM3s81
hn+O36UUs+bqcaHPXcCKgEISoJkU39rzEeLQt6besKGC5wCPuqPLeVmcIdhEI9uMJe6eg3JSr4a5
/qYJFo0EkTgcmIsmzYARCzfHx0SyNTWujPkHb/PCFMGKTnqcFgN2HMHPNTsFnuf5MkGSOgwUrYgT
bWLMhxf6nYs5W4UpN9HAVWIY6nPWC4eftdMIBy9gAXwdNcPODK0Ipyhnd/uKWQFezz/+yCMNrNxV
6Gm8Ou+Uz23QNGIJLWSGZdVW+gQ7U1gy22swp9zT2gF594fKdctmNTlC9mJPHtGgqN5PSv4O//aB
TA6bR5xxkdTYiZViNln8Z+bViIJTWFT5shOmWpB1f/Z4dZA9Ixy2KwebZgjZBozNeP37KHTbPegT
7sj4k0aTgTnrpyld9rD+j9VvSsvJ7aq3hMZhkFWe6cWs2sPvgbzooYVcubHZ3U/CmXtWjkyJchtS
fnQlZ/3xkBIPfqcSuQ289HiYNnteKjf9K7rkWqlnvO01JY9qiT5O0YVhD6GYvRKVXWqHol9YFCrU
SH/eOPVm/9Xu1itpykoEzifaUa5Ysn4ZWtWWQxkMrieKws8qdqXvducgmd2Rj3/XPNlDzH/NK5c9
hQv7jfolot5IuDB3Iq1ZhlxhkyVl23foQFHRHFU15OQqgwB0AMj9kS/GaIbCW4CNw3Tinky2BGw9
L5EklzroGQASOYKSJryx6jr2gfLLfiIqmlasMCiI2qTs8V6iCp2hkv9SXyJUHA6wz7q5JC4rrMyv
0W1tsN3ydEtVV49f3wknJDjvcgW6djeYV99rJGVSnHlT2J4pk1ar/QHSsxChrvb9IMUO1Y8PmgND
uovfx7KmHnX9RXLSltLEVrt5vzrN+XPE7z1p4G06tJfLQAx9mH4WMF6YrYXq35fY1hU0GpRi9m81
ko0Jxt44IgkaIvO35s4aUVfLnpQlLOk/OGjQn5qt6lxkLHHBdoG4yHnLFMTztLa1l7UAOir60mUX
FbIW+emCbFWcN4Igrtn7w+uLEE2XcxGldX1dhnG/EWHVEJiiGr+6T2SnXRnIgydVOO3kEMVxOZhv
Oh4LyckyfkAzeYXTYqKjODe1mvWOZ1fGlWSXcg9rEoBpCbOMm5cloI8MUlDxaZZH+rlFjNodnrp0
PQm70hcE4SgHyWkOjCMBl65Mu4MlevhvEMfoBamNZpSstDSrT06hvuCisrwBo43X8eGMa+5yCUDP
ZayODX7DnD3KkP+XJlyAV7sgk7jF6V3zcaDBn+MxQU0eAQ9z1FEj1EzAewS6dIWLtLrod+A7/bOZ
5czEHQV89Dz8wlNpve+FLx7AbP25Vx3REVtbiA1xyU1aybvwUx28+pk9JJFqWVD/XDPw9LJrynnB
S9QN6Bup292/kdy4AfJQpPKi0UQFmnQ+oyWmUxt7l5n1IELTPDpFGvflrIiJHyaoMIOyDRjrjPjP
/b4XoSHBcA+lWmTVqtpRZfRWHmOAmAPqE5pYctmkZWJmH97luj9X2f4JVukPYR6kQEePA1zCMyo5
9GixlBbLH1Xya6dObifa2M6gv957qWzcTT6bcbHZSoB++aNoobDz7mltUbG0ZdffBVYB7lYl7VnW
qmOYDndPaVeG5inxUNO6olVfEzssiWnhg8O/AScJwcVsUhpNjrx6dUSgz97wit7jdYngLiZsymqH
UAiQn4PzFuUEh7lvPCsdbm2q3Fsfeb1feX46wknSzyBge88/AuXI1gIGc8+iDEs4IADGHESFjq1j
YGlmxw1hgTnVL9F4S/zxDFmVuh2WZvGraeORhJK2I8V/k1wblr1mbuNO9fFze08Fv52kyBHXR8R9
uGB5gLe7NH99POEQv1gzHm6plGypakT0k2xkfVwdsNiMmoxeedgEiLzDIJon76xnU/CsFSlAIGVq
h+uOTSD75K623k3Tb3wq1kVlUkkNjVDYifbEJg6QuRLUCVZvWyhQ/4+GgH0ki6pMiqOq0KI4sgNU
aTIwfyCDMaJtRzT6xpXNrOfXIjX+Cl+L3pl0i+oEmwEd8dVZ30Q3PiG0cqCWYE5T7cfcZUIOwApv
biTWgrrgb2It7VF+qH7M2VLJ6u/jlpjvMH5RQTEyZ2c7xukwJ7AaGv8HBINWfFEeK9yx+fAn3+pJ
Kl1SpQWmIonXH49TwUBp0W8WabnYYBeNTR7MZrsI5/DsZ+A5F4OCqfqgYOd2TY2YgLGg+uUUFRhn
SEDSBGuFRIYb4nFRI2fDm21Hx0ajGwFmI88su2t/vv7hqJ0oumLZhFY6iXHLvvfwqQcI63y+w4a4
TBLx5W/0vJTlOa71xabH5Vj7Exfy7Rxr1IfDnMDF4+VVzDPpp3ePgP9TeLcUdJFegLM0eQrqTswi
Xrt0oUMONZ4sTlRT6VMDs3R91atbwidnsI2ggzxEqLhuNy9+vK48RgbbKvJ5KDEqPbKpqwv+HaFw
EJ0mni7vqgd6gV4ZLBDieXsdD5kY5WMCjylcguAZopKLx7TUbUaO9XySQPe3lsy17o/Ym3SUFoKT
W/uQH3MQ0uSiGQPjOWzbnEhC2sz+N7O9x4FZAQQGMQ47hIKvYnuyfa3hL3a2xNoFwd3wmt2AWt0i
rsV3iNtmcpT4EK83RUrWFbBa2dGy/fF62H/3aw0lQncrHjYDJY6bMJBmjJYWOpSQovAcraoz7XbU
O5u1bCCElNFTLQ4cFFCEoICSMuhNlGeaM8/WkoJmWzbabB9XvHGhGwbtEIYnfc86CP9UCgNPc27t
USzOrGNyNc15Ma57H+H7JSitM+faHSzkaTMEENICBgYKTZZLROlm3Z7AOybwIaN63YhOxEEYJkge
MtsHAwrDXhS3HWsFVsoE3IfGrK1oA85Bvh2DRHUbdvpDdXOk3CmmWkPVF6f3r4U1C0SLd+Gct4gA
k7Z2VfI9+aBZEStqc1vh7aaWWOHAqnRaMN3t4GHGpBt+ggiaKnPyTM6THCwfX82ye2ZeMALLQkX4
+wzSzOdvsKf0WdzApGM0jZRXpN7kCJvA5UxuEDNUo0GU+TonzxQKcs9zESwAkkm9BqZNdUk9I2JX
YPQk7iI/3Ha09pdDaOTVSq/o9amleD/kQnJgSXTHkgYLceKOLQtr1ea08SSDXxc35LDC0XYaRA7X
oo2wVDhb9EhZK0OXI4YzdTFFuRPe5+0s8rXJBznBcA52nGj5xVv1fjk0XvQADGwsxYsf1+WjJKJ+
7Gu8d8EoDPjvlddPuQL1LlZEv5bWyMF0zskDkvGiAMRMHPe+NGx6F4WJBi5JovBzXjrk9TgcGMWc
M35il3oBpcyChQ/qvRenH0RpAM+VFjWjPQUIRkeeb3XNoceo2ThrMXjRWUjOoBA0+iVwEJluhlaf
O7EAnWgWk8IHtLqmhsXtoGxX812mqbL/ZgFcenpKlrvphg55geKC5VS0rcLWJ2BQU8l1v/o+pJQx
aGrGvVIYtE8YlCOgALb1L0dW0KpJKrkR+jdn++KWlVhEE+W4VlW/xnfIGD8V1JBdV4ZnDIuBBQL4
m/arsdwwPOxjJpT7bcqzMXiJu6T0Qs9YQOPUlQEuhtyRYPkBeUpNJB/uigrGEWAWJN23eXfa1iO+
nAFWSW6NiTNsbEXXPTCOYRaR/IRGO4OOKHPY/X1xbW7aNLcuXrwhFArJcOfTiMBLKPVTuI02h/mS
Q5CniEBEy32Kz0Sw+1s6SeY6nuyrHwZ8gDrdnf94TTxYJ/z57oTr3hRAKeESBfbebsniAVArERd+
eJ/snCcWWt0gwJnGu50OlGn0IbfakFdRvXWfKFDeSmfTSAWT2epgQ8mneU1ZwgL3fhzyB0Q+cIfR
nn9n2yy/HiaF//UFErfpTp+rVEBS1XtXBNECMcehp1ozqxu5DdsNQlkrx4ME6OJ+2FeN+k4eE+VA
GQce9tVui6yvaT1I0cJwkwDDytaTdLK76ro+0bRzBpbP//l8am4xukJIwSc7tCgF8FCvcfvppN/C
0d1LlGBDw9Lw3H6+Ly/Q7gf3Qgg1ZnTtq5QdFwrgDf8rF4Vpqtsj9WWJczsOWgv9uNjbyZA12Oor
7MjgdRRMGXTxgeMe11HApsCBsd7Q3UGQNm+u8xfU+FveytaW6K0v00cIE2W6TqtARuMXi/B98YcD
ZdySNa4RWMMLkW6jS6gEbU8bttC0PO6doiJO+Pv1+JFlxWDKTRpjXZKPmdwXHYpOphIsy+kWI9zI
wtwzLkybOPfIx6xPsze4bY1lDVhvK+9kIN2B1mXgtH48MoERTQbFnqkvajzaJnN6IBnwGJVDOnrl
zhgF1W5eobSqBH53+QVt8fOFAq6bPb3mGrjfFssgFS0HeVnR1P9Gnx4D8OwUj4T0M4ka7scwVMtz
BgtWUhP1f89RscxRpMwzBmdt8r7jPQT1qwWS2Ae/ezhgA5RazD7wbsvZMi/qgmeExRGaYDK0keqy
v8xGBrgZQ+VwTxBkC4j1KgVqRmlicMVF3T2ih6fIVek1RtutzEwpXaXqxNTqlmH7IlIFcbf41Vl5
fpneTlpXdCbWAKO8K0GKQWLCiw/JV4YXvu/eVxfp5eU9cdS0uzCuoZ79x7s7OR6Ia75mznTwB3IX
sTaamKspTmYHW7SFuYIF9g+Iz/Iyk788d6Lufw4r9bfPYqdBnN3XLvSJvb2rz3I0zsiUjNn7xBG5
/IkPU+tCakS0fUJiwTfmVq0/Qu5neXl8gNkBx9gLWdUUHUqxymV1z5Nm8eIU90gOx6irY8sRBui3
hndkc9jyghwDnMBzufvUoJdnG4dsIe555vMhp9WodE/CYCGB8LLwhQn88PkO0N3+ijxNbfplmpc3
Glq621qieDez1abEtngireC0WdRg5qwjVbpZiBybD1vxOm1wb16rb+JbkbLfrnNAuJMS8x+2XyGU
jGWUJhUikpTFG8ibGXxZ7hytO+575FE/g3YVBhLkNIynWIzdO+h0XUSnJhn+Okd/h2vb4nnrWZKC
uxEPDujSBqtk6nQNYhvKfp1bBwFgOt2Ojq/bjZJLJ3OnnqisIUxaETDl04qLhBdJTNYROqBHsVKA
olswnFmRAgfHj0gvzprDAMKI1WrTZ9Qhi+dasMkN582DGIiSYWLxEZkHQZ9gOhOwnJdZY6zFnnNz
rmGvGR1tccKH9ISBmm1QAN7+RbBt1yVU2b8tEvyRx+ezcOS4UedUm06e5MaiJ1MIgb0Hh/pWHpZV
yc/6rghD6cQvgV63NFHXGgnG6JR1vcj/kQsvWj5BQFvYaZe/vFBG5iAwE1dMNpQXBlManQAChtsB
h7EPAF6v3/ldXSMcFvhp8tX5XnNJqWLRPhAwvci+oDj2aG3DhRf662AImwzl6mFFN04eDTKRQaKN
rPAK948jebaRaxWqOfJzNGWTZvSnsHwUGusvqnz37b4cJQA9uVUl2nZOaKmzqRW+nrksqhlOcW6w
8KDAIF4pKmHMjJGYv9uGkhc5TWqlLPkY4mjA2oXNPuqfYGpGnSYHkbpA/dmnYP3cp9Ci2umK+kqW
bXc3d/slRVf20/9KtXZKZbNRPXY0Ir38X0rryr2m/YRPf1YqLl+kk8qSN554qhnA3BwkaRZ5U+7r
3MXrFw41tQxNzPGmZVu6wvqq62/8IblKpQJdLTXbGzyAggdlwNihRFBOAnCgz72rC47XfvOy5muO
DGVn74GcC4MV4fu7GZcltlMNkd4xFOk4L+nz+zQWQhqApjCQSJBdNOQJ6qbipPbWTX6LAQhq1DIy
Bum5VWytfElpPbLtVLYuf78PJBXITDufi9b7oKa81VcpJ1vjvQ0ccUwOrRHRRsOgAGFd8Mpd77jh
TrNh2psD3OEd8nl3wj1lO7FrGivsIh871QFgs5IGYauI4JI6TP9cV9klsIdQeILLbVFqdn9sBMy5
JHJxbWYzvECyxJdxsqgdtOZezjPtIVyG5ihcHSpRE+l98IDgFrPZ7FymD6Tu4B7GZAZU4DNkQ4tS
SScDeEpZl5QkC6QuX7cEU4O8GsAjeKMTgu+DdemXzQFtrRJG0QQM2aHeCBUHHtSaikd6V8tyQzut
HGia9zcKfgLhTgG8QPQudrNfRl0CKTEFBFaR2DGYYyFOQLXxSnIOUIEgx/zDP4Cs/PxX3k6IdWJK
L48iR9JU/4HyH8LrhM1VdtFDNwop+HVRsb4PuHfoPvh3gCW0nAOi5aEC1xvo5It4XmLB4U+fLNIp
Vz5qlF7BcznJfTBXWKmYPfYZKcDEm+M0Ha+ocb4LE24+SopkBd/WtZyYTZpT2zBG+3Xs6bGK793w
11Am0S6i+Tz4Dc1avYM0NEutti5GDi0fKAE9ZhpLH3C04pAQTWVrSUYtB6xvNNsTEQktT1585vEq
P1yWuPyptXe5EzsR5bMtsK23sKlNfb9+GsGM9nmlouVnNIMkXDzsg1jwTNIfSBdHLGe2kR6hfv0r
fwJf35ucx8cFdEf2prPjPAZfE/8xa3Xe+gRmXCGHIqWmUBHbDunbAJv+s5Fwh6nIP1Pt7ZzZ/GeG
Qg+jXJCSuk9T1MgckEqbOvGuDiAE+uQ0YXQ7dIrE2gvg71d3nuwP9v5QtKAlb65PVFJhepkG/DbS
ZSirO+HO6FqupYfGSe7c2DtuVAml21LcOJFtYY0/xhoxBd/7hia+5XiP2iQf0Xvgf0Kf6AQqZpV5
/9JdEHvGcUjL09Vm5LrK4Spc9RJMGW29VpENph/RIjQNhw6KkztZyuUmOG0OoiAVE4dqSQ416BX7
69RJ/QEP8LvdqEw4x6Q+0imgsDVVIdIi4gWOZ0eIjIQ49iL9RQapUG3blLxERuvQ40tthjcJPYGH
+m1KUxFxPExdOAJDHH/RfIXQYI2q/6+fcZGs+IUrb8JvzO7TjvQeerDGx3yqBH4tBghLHxBQ6m8T
Okrsgum8l4kvMu9rh8sY2VjFJBBkQzLo+CovwV3K1E8cCcy2rsfLfNcAYMRdluq3zY8ELvsk7BWO
IOyG1fK5tq4VdkPhcsCn2zRfYNbw1Pj+s61YLlVIfD+IezBJAhw90KRX1uEhZOIytDKjCfu/y3Yb
T8jqAG6qFP1554qsNlbSZIm2DlQ46lCuwcs2UQlJe3y7Np4xmZiT4ciJ2WR1TM2I7jj0xfVuHOVF
Lhr6HGznaVI4TGhjuxuf7W5YilR3RvVlHBQckHGcPH0CFabesC2ObRKkv01F8grikTK13yOeMK2c
S5AE66uNG8N+57E8yWWwgcU+aqt3G9nB0UWCUdpC9tdpN3sXB3DoNHJ1JDdsHlouyLJZO9pyIsD2
Sldl14WBv8JdSQ+XwgEqFAQ9da/Ho9pOlMfFUSFvLa87JLUfWgKle9zbtX1PjeGFmZNILSlxwrax
F+U2vNX+BW0VBpEFcCD8Q7Hel1EJ1/brN3JdoWxpfP+S+W/zo2pvfEJ8MUkz7CnCtSHFU57Cq1vO
vPYzp0TJRMXEqw9FDxmf10fAl75X6Zf65+EKxRpUoQKh1BnF1+uwhm5ZouI6WhC2xbWNHbR5Qjm/
xZ2wt4CsmUcrA9eZA7P06/HG/cHHWj6x/UzuMnuxkBXnmi3UkcpZa5Rl6u4eY0pO2o4PozCcuZUr
GWTBs6pw3oRPHecsvkzzaSvHbAkIkPibdDLhQxe2azyyNSpx+VdUOodtviZPhiiYRa6f1pdg/t+y
3rz+lPb0h+Zhd+A8qW4UNhqzdD6LPHTc5cbeIpzvIzHN
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ELnJu6Vo0SI9GKpLvbyZsjxQDyRCBDXnwaI+OVt2A28orBT2jmAlQ4HKnfhVOxQ1HVQoM1tdoooV
yiFYqb+nOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
d595STmd5mP1KOtLaMHlwcurqj2ROaQRJTJ9JyLXkWbDy08rIse8hZd1A6jKM9XRFjiJTfchVgGL
HyQgFFro8kkxi3kcFfMYMrjfgmsBmzvIt0iZgRYFd8xpBrZcxlEz0jGB9JrVJlc9kFtlsuthla4/
XeEPM/M4NQ1NW0i4bUI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
aCiwj/c6RBs2QYQzQfbPjqMfXZi7CBiAoY3ecZ+BXROFvW1foaeKNmymX3/NbqLmwI+aVfcBuWfM
82qMdBughbvY91TNnmd20fs4X9sRAfMMNXm+STuoU0CGS15RLE8mCvB6FK40VuhV3DuBowJpCwhu
qttGfdt4FzOaiqM9YJVY++rI01UEPJcY9Dzu4Kb6BFrZEeWJ3iKows5wz9Aqt+78q6jzGFkn5R7D
JYSXM48tEmgrz8rcCJtB9+hr80LrADRvsyaBnwj/1YzlLziNHfDtnwH8Av66LZCCbg39v0BLA/1E
MyWY7eN5kcBSao+3m8Oo1qva1poQUc0UPcoR2Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
rt8qeqigKmHwNHNLDxKbJcBQ9QDjdSevpojXqtzOPOHihRQJ4iBxigwNdpHstCOFVBMqIX82UPZK
l5Z3voAz3pFaYq7dr6oHiV7oq2E0rQM5Uxhnfh46Zli/JIaRIpWf8EncPdKldj2Uf0AHq4/QV7y3
XqpPRbNfHQDneXeaciU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
lg1zM5+6ggCKkgN3qoxCvPMtnbR0lY9lPu4zV4wzZcs+UL0W1Cg00gE/3G329vCSQVnp5DAgqrYF
es9zj02SoPbANFlroyCxQjvn6Mf7ymspo+yMZhpWKlCutMCGBCKG6yQvEkkOWmJ1a/jofMJXUStD
P5832qeWGes85Bq1B9G9RJF00xScbF9hcS/9D3oCqiqCAHxxSC7iLsa2pqMcYRqQZG+qNYT6voBG
fplyLOfpmy0SbXo5116wxuki/c2xyUWMwOY5ZZScyTqrkXLycHyLaxvyh2vne5p5V5Q073iE+Nua
YsJxRHqAz8BYbH/Qqr41Ph21S2M4ldPL/JaM3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5904)
`protect data_block
lqHYkpxMxolz7h2fUWZoITda5XUgseMfPJZ/qQ9hmk7NApiNxHPZ4WI5cHcShW19oa8bTx2b9T7h
QmQlusU7GKx6vqF/E8Wg4FDyViOa/z9Ds1oPXmAq0H6lT44QOq8LuP/HaYu8vQF6KMEabMq7EGLv
GMpQlnkgTbW+AxVDtL0wXNwCy4Bon307HXof0rtzMdq6OjyPovXPty2n07/66jgTk+B/xyzM3s81
hn+O36UUs+bqcaHPXcCKgEISoJkU39rzEeLQt6besKGC5wCPuqPLeVmcIdhEI9uMJe6eg3JSr4a5
/qYJFo0EkTgcmIsmzYARCzfHx0SyNTWujPkHb/PCFMGKTnqcFgN2HMHPNTsFnuf5MkGSOgwUrYgT
bWLMhxf6nYs5W4UpN9HAVWIY6nPWC4eftdMIBy9gAXwdNcPODK0Ipyhnd/uKWQFezz/+yCMNrNxV
6Gm8Ou+Uz23QNGIJLWSGZdVW+gQ7U1gy22swp9zT2gF594fKdctmNTlC9mJPHtGgqN5PSv4O//aB
TA6bR5xxkdTYiZViNln8Z+bViIJTWFT5shOmWpB1f/Z4dZA9Ixy2KwebZgjZBozNeP37KHTbPegT
7sj4k0aTgTnrpyld9rD+j9VvSsvJ7aq3hMZhkFWe6cWs2sPvgbzooYVcubHZ3U/CmXtWjkyJchtS
fnQlZ/3xkBIPfqcSuQ289HiYNnteKjf9K7rkWqlnvO01JY9qiT5O0YVhD6GYvRKVXWqHol9YFCrU
SH/eOPVm/9Xu1itpykoEzifaUa5Ysn4ZWtWWQxkMrieKws8qdqXvducgmd2Rj3/XPNlDzH/NK5c9
hQv7jfolot5IuDB3Iq1ZhlxhkyVl23foQFHRHFU15OQqgwB0AMj9kS/GaIbCW4CNw3Tinky2BGw9
L5EklzroGQASOYKSJryx6jr2gfLLfiIqmlasMCiI2qTs8V6iCp2hkv9SXyJUHA6wz7q5JC4rrMyv
0W1tsN3ydEtVV49f3wknJDjvcgW6djeYV99rJGVSnHlT2J4pk1ar/QHSsxChrvb9IMUO1Y8PmgND
uovfx7KmHnX9RXLSltLEVrt5vzrN+XPE7z1p4G06tJfLQAx9mH4WMF6YrYXq35fY1hU0GpRi9m81
ko0Jxt44IgkaIvO35s4aUVfLnpQlLOk/OGjQn5qt6lxkLHHBdoG4yHnLFMTztLa1l7UAOir60mUX
FbIW+emCbFWcN4Igrtn7w+uLEE2XcxGldX1dhnG/EWHVEJiiGr+6T2SnXRnIgydVOO3kEMVxOZhv
Oh4LyckyfkAzeYXTYqKjODe1mvWOZ1fGlWSXcg9rEoBpCbOMm5cloI8MUlDxaZZH+rlFjNodnrp0
PQm70hcE4SgHyWkOjCMBl65Mu4MlevhvEMfoBamNZpSstDSrT06hvuCisrwBo43X8eGMa+5yCUDP
ZayODX7DnD3KkP+XJlyAV7sgk7jF6V3zcaDBn+MxQU0eAQ9z1FEj1EzAewS6dIWLtLrod+A7/bOZ
5czEHQV89Dz8wlNpve+FLx7AbP25Vx3REVtbiA1xyU1aybvwUx28+pk9JJFqWVD/XDPw9LJrynnB
S9QN6Bup292/kdy4AfJQpPKi0UQFmnQ+oyWmUxt7l5n1IELTPDpFGvflrIiJHyaoMIOyDRjrjPjP
/b4XoSHBcA+lWmTVqtpRZfRWHmOAmAPqE5pYctmkZWJmH97luj9X2f4JVukPYR6kQEePA1zCMyo5
9GixlBbLH1Xya6dObifa2M6gv957qWzcTT6bcbHZSoB++aNoobDz7mltUbG0ZdffBVYB7lYl7VnW
qmOYDndPaVeG5inxUNO6olVfEzssiWnhg8O/AScJwcVsUhpNjrx6dUSgz97wit7jdYngLiZsymqH
UAiQn4PzFuUEh7lvPCsdbm2q3Fsfeb1feX46wknSzyBge88/AuXI1gIGc8+iDEs4IADGHESFjq1j
YGlmxw1hgTnVL9F4S/zxDFmVuh2WZvGraeORhJK2I8V/k1wblr1mbuNO9fFze08Fv52kyBHXR8R9
uGB5gLe7NH99POEQv1gzHm6plGypakT0k2xkfVwdsNiMmoxeedgEiLzDIJon76xnU/CsFSlAIGVq
h+uOTSD75K623k3Tb3wq1kVlUkkNjVDYifbEJg6QuRLUCVZvWyhQ/4+GgH0ki6pMiqOq0KI4sgNU
aTIwfyCDMaJtRzT6xpXNrOfXIjX+Cl+L3pl0i+oEmwEd8dVZ30Q3PiG0cqCWYE5T7cfcZUIOwApv
biTWgrrgb2It7VF+qH7M2VLJ6u/jlpjvMH5RQTEyZ2c7xukwJ7AaGv8HBINWfFEeK9yx+fAn3+pJ
Kl1SpQWmIonXH49TwUBp0W8WabnYYBeNTR7MZrsI5/DsZ+A5F4OCqfqgYOd2TY2YgLGg+uUUFRhn
SEDSBGuFRIYb4nFRI2fDm21Hx0ajGwFmI88su2t/vv7hqJ0oumLZhFY6iXHLvvfwqQcI63y+w4a4
TBLx5W/0vJTlOa71xabH5Vj7Exfy7Rxr1IfDnMDF4+VVzDPpp3ePgP9TeLcUdJFegLM0eQrqTswi
Xrt0oUMONZ4sTlRT6VMDs3R91atbwidnsI2ggzxEqLhuNy9+vK48RgbbKvJ5KDEqPbKpqwv+HaFw
EJ0mni7vqgd6gV4ZLBDieXsdD5kY5WMCjylcguAZopKLx7TUbUaO9XySQPe3lsy17o/Ym3SUFoKT
W/uQH3MQ0uSiGQPjOWzbnEhC2sz+N7O9x4FZAQQGMQ47hIKvYnuyfa3hL3a2xNoFwd3wmt2AWt0i
rsV3iNtmcpT4EK83RUrWFbBa2dGy/fF62H/3aw0lQncrHjYDJY6bMJBmjJYWOpSQovAcraoz7XbU
O5u1bCCElNFTLQ4cFFCEoICSMuhNlGeaM8/WkoJmWzbabB9XvHGhGwbtEIYnfc86CP9UCgNPc27t
USzOrGNyNc15Ma57H+H7JSitM+faHSzkaTMEENICBgYKTZZLROlm3Z7AOybwIaN63YhOxEEYJkge
MtsHAwrDXhS3HWsFVsoE3IfGrK1oA85Bvh2DRHUbdvpDdXOk3CmmWkPVF6f3r4U1C0SLd+Gct4gA
k7Z2VfI9+aBZEStqc1vh7aaWWOHAqnRaMN3t4GHGpBt+ggiaKnPyTM6THCwfX82ye2ZeMALLQkX4
+wzSzOdvsKf0WdzApGM0jZRXpN7kCJvA5UxuEDNUo0GU+TonzxQKcs9zESwAkkm9BqZNdUk9I2JX
YPQk7iI/3Ha09pdDaOTVSq/o9amleD/kQnJgSXTHkgYLceKOLQtr1ea08SSDXxc35LDC0XYaRA7X
oo2wVDhb9EhZK0OXI4YzdTFFuRPe5+0s8rXJBznBcA52nGj5xVv1fjk0XvQADGwsxYsf1+WjJKJ+
7Gu8d8EoDPjvlddPuQL1LlZEv5bWyMF0zskDkvGiAMRMHPe+NGx6F4WJBi5JovBzXjrk9TgcGMWc
M35il3oBpcyChQ/qvRenH0RpAM+VFjWjPQUIRkeeb3XNoceo2ThrMXjRWUjOoBA0+iVwEJluhlaf
O7EAnWgWk8IHtLqmhsXtoGxX812mqbL/ZgFcenpKlrvphg55geKC5VS0rcLWJ2BQU8l1v/o+pJQx
aGrGvVIYtE8YlCOgALb1L0dW0KpJKrkR+jdn++KWlVhEE+W4VlW/xnfIGD8V1JBdV4ZnDIuBBQL4
m/arsdwwPOxjJpT7bcqzMXiJu6T0Qs9YQOPUlQEuhtyRYPkBeUpNJB/uigrGEWAWJN23eXfa1iO+
nAFWSW6NiTNsbEXXPTCOYRaR/IRGO4OOKHPY/X1xbW7aNLcuXrwhFArJcOfTiMBLKPVTuI02h/mS
Q5CniEBEy32Kz0Sw+1s6SeY6nuyrHwZ8gDrdnf94TTxYJ/z57oTr3hRAKeESBfbebsniAVArERd+
eJ/snCcWWt0gwJnGu50OlGn0IbfakFdRvXWfKFDeSmfTSAWT2epgQ8mneU1ZwgL3fhzyB0Q+cIfR
nn9n2yy/HiaF//UFErfpTp+rVEBS1XtXBNECMcehp1ozqxu5DdsNQlkrx4ME6OJ+2FeN+k4eE+VA
GQce9tVui6yvaT1I0cJwkwDDytaTdLK76ro+0bRzBpbP//l8am4xukJIwSc7tCgF8FCvcfvppN/C
0d1LlGBDw9Lw3H6+Ly/Q7gf3Qgg1ZnTtq5QdFwrgDf8rF4Vpqtsj9WWJczsOWgv9uNjbyZA12Oor
7MjgdRRMGXTxgeMe11HApsCBsd7Q3UGQNm+u8xfU+FveytaW6K0v00cIE2W6TqtARuMXi/B98YcD
ZdySNa4RWMMLkW6jS6gEbU8bttC0PO6doiJO+Pv1+JFlxWDKTRpjXZKPmdwXHYpOphIsy+kWI9zI
wtwzLkybOPfIx6xPsze4bY1lDVhvK+9kIN2B1mXgtH48MoERTQbFnqkvajzaJnN6IBnwGJVDOnrl
zhgF1W5eobSqBH53+QVt8fOFAq6bPb3mGrjfFssgFS0HeVnR1P9Gnx4D8OwUj4T0M4ka7scwVMtz
BgtWUhP1f89RscxRpMwzBmdt8r7jPQT1qwWS2Ae/ezhgA5RazD7wbsvZMi/qgmeExRGaYDK0keqy
v8xGBrgZQ+VwTxBkC4j1KgVqRmlicMVF3T2ih6fIVek1RtutzEwpXaXqxNTqlmH7IlIFcbf41Vl5
fpneTlpXdCbWAKO8K0GKQWLCiw/JV4YXvu/eVxfp5eU9cdS0uzCuoZ79x7s7OR6Ia75mznTwB3IX
sTaamKspTmYHW7SFuYIF9g+Iz/Iyk788d6Lufw4r9bfPYqdBnN3XLvSJvb2rz3I0zsiUjNn7xBG5
/IkPU+tCakS0fUJiwTfmVq0/Qu5neXl8gNkBx9gLWdUUHUqxymV1z5Nm8eIU90gOx6irY8sRBui3
hndkc9jyghwDnMBzufvUoJdnG4dsIe555vMhp9WodE/CYCGB8LLwhQn88PkO0N3+ijxNbfplmpc3
Glq621qieDez1abEtngireC0WdRg5qwjVbpZiBybD1vxOm1wb16rb+JbkbLfrnNAuJMS8x+2XyGU
jGWUJhUikpTFG8ibGXxZ7hytO+575FE/g3YVBhLkNIynWIzdO+h0XUSnJhn+Okd/h2vb4nnrWZKC
uxEPDujSBqtk6nQNYhvKfp1bBwFgOt2Ojq/bjZJLJ3OnnqisIUxaETDl04qLhBdJTNYROqBHsVKA
olswnFmRAgfHj0gvzprDAMKI1WrTZ9Qhi+dasMkN582DGIiSYWLxEZkHQZ9gOhOwnJdZY6zFnnNz
rmGvGR1tccKH9ISBmm1QAN7+RbBt1yVU2b8tEvyRx+ezcOS4UedUm06e5MaiJ1MIgb0Hh/pWHpZV
yc/6rghD6cQvgV63NFHXGgnG6JR1vcj/kQsvWj5BQFvYaZe/vFBG5iAwE1dMNpQXBlManQAChtsB
h7EPAF6v3/ldXSMcFvhp8tX5XnNJqWLRPhAwvci+oDj2aG3DhRf662AImwzl6mFFN04eDTKRQaKN
rPAK948jebaRaxWqOfJzNGWTZvSnsHwUGusvqnz37b4cJQA9uVUl2nZOaKmzqRW+nrksqhlOcW6w
8KDAIF4pKmHMjJGYv9uGkhc5TWqlLPkY4mjA2oXNPuqfYGpGnSYHkbpA/dmnYP3cp9Ci2umK+kqW
bXc3d/slRVf20/9KtXZKZbNRPXY0Ir38X0rryr2m/YRPf1YqLl+kk8qSN554qhnA3BwkaRZ5U+7r
3MXrFw41tQxNzPGmZVu6wvqq62/8IblKpQJdLTXbGzyAggdlwNihRFBOAnCgz72rC47XfvOy5muO
DGVn74GcC4MV4fu7GZcltlMNkd4xFOk4L+nz+zQWQhqApjCQSJBdNOQJ6qbipPbWTX6LAQhq1DIy
Bum5VWytfElpPbLtVLYuf78PJBXITDufi9b7oKa81VcpJ1vjvQ0ccUwOrRHRRsOgAGFd8Mpd77jh
TrNh2psD3OEd8nl3wj1lO7FrGivsIh871QFgs5IGYauI4JI6TP9cV9klsIdQeILLbVFqdn9sBMy5
JHJxbWYzvECyxJdxsqgdtOZezjPtIVyG5ihcHSpRE+l98IDgFrPZ7FymD6Tu4B7GZAZU4DNkQ4tS
SScDeEpZl5QkC6QuX7cEU4O8GsAjeKMTgu+DdemXzQFtrRJG0QQM2aHeCBUHHtSaikd6V8tyQzut
HGia9zcKfgLhTgG8QPQudrNfRl0CKTEFBFaR2DGYYyFOQLXxSnIOUIEgx/zDP4Cs/PxX3k6IdWJK
L48iR9JU/4HyH8LrhM1VdtFDNwop+HVRsb4PuHfoPvh3gCW0nAOi5aEC1xvo5It4XmLB4U+fLNIp
Vz5qlF7BcznJfTBXWKmYPfYZKcDEm+M0Ha+ocb4LE24+SopkBd/WtZyYTZpT2zBG+3Xs6bGK793w
11Am0S6i+Tz4Dc1avYM0NEutti5GDi0fKAE9ZhpLH3C04pAQTWVrSUYtB6xvNNsTEQktT1585vEq
P1yWuPyptXe5EzsR5bMtsK23sKlNfb9+GsGM9nmlouVnNIMkXDzsg1jwTNIfSBdHLGe2kR6hfv0r
fwJf35ucx8cFdEf2prPjPAZfE/8xa3Xe+gRmXCGHIqWmUBHbDunbAJv+s5Fwh6nIP1Pt7ZzZ/GeG
Qg+jXJCSuk9T1MgckEqbOvGuDiAE+uQ0YXQ7dIrE2gvg71d3nuwP9v5QtKAlb65PVFJhepkG/DbS
ZSirO+HO6FqupYfGSe7c2DtuVAml21LcOJFtYY0/xhoxBd/7hia+5XiP2iQf0Xvgf0Kf6AQqZpV5
/9JdEHvGcUjL09Vm5LrK4Spc9RJMGW29VpENph/RIjQNhw6KkztZyuUmOG0OoiAVE4dqSQ416BX7
69RJ/QEP8LvdqEw4x6Q+0imgsDVVIdIi4gWOZ0eIjIQ49iL9RQapUG3blLxERuvQ40tthjcJPYGH
+m1KUxFxPExdOAJDHH/RfIXQYI2q/6+fcZGs+IUrb8JvzO7TjvQeerDGx3yqBH4tBghLHxBQ6m8T
Okrsgum8l4kvMu9rh8sY2VjFJBBkQzLo+CovwV3K1E8cCcy2rsfLfNcAYMRdluq3zY8ELvsk7BWO
IOyG1fK5tq4VdkPhcsCn2zRfYNbw1Pj+s61YLlVIfD+IezBJAhw90KRX1uEhZOIytDKjCfu/y3Yb
T8jqAG6qFP1554qsNlbSZIm2DlQ46lCuwcs2UQlJe3y7Np4xmZiT4ciJ2WR1TM2I7jj0xfVuHOVF
Lhr6HGznaVI4TGhjuxuf7W5YilR3RvVlHBQckHGcPH0CFabesC2ObRKkv01F8grikTK13yOeMK2c
S5AE66uNG8N+57E8yWWwgcU+aqt3G9nB0UWCUdpC9tdpN3sXB3DoNHJ1JDdsHlouyLJZO9pyIsD2
Sldl14WBv8JdSQ+XwgEqFAQ9da/Ho9pOlMfFUSFvLa87JLUfWgKle9zbtX1PjeGFmZNILSlxwrax
F+U2vNX+BW0VBpEFcCD8Q7Hel1EJ1/brN3JdoWxpfP+S+W/zo2pvfEJ8MUkz7CnCtSHFU57Cq1vO
vPYzp0TJRMXEqw9FDxmf10fAl75X6Zf65+EKxRpUoQKh1BnF1+uwhm5ZouI6WhC2xbWNHbR5Qjm/
xZ2wt4CsmUcrA9eZA7P06/HG/cHHWj6x/UzuMnuxkBXnmi3UkcpZa5Rl6u4eY0pO2o4PozCcuZUr
GWTBs6pw3oRPHecsvkzzaSvHbAkIkPibdDLhQxe2azyyNSpx+VdUOodtviZPhiiYRa6f1pdg/t+y
3rz+lPb0h+Zhd+A8qW4UNhqzdD6LPHTc5cbeIpzvIzHN
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ELnJu6Vo0SI9GKpLvbyZsjxQDyRCBDXnwaI+OVt2A28orBT2jmAlQ4HKnfhVOxQ1HVQoM1tdoooV
yiFYqb+nOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
d595STmd5mP1KOtLaMHlwcurqj2ROaQRJTJ9JyLXkWbDy08rIse8hZd1A6jKM9XRFjiJTfchVgGL
HyQgFFro8kkxi3kcFfMYMrjfgmsBmzvIt0iZgRYFd8xpBrZcxlEz0jGB9JrVJlc9kFtlsuthla4/
XeEPM/M4NQ1NW0i4bUI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
aCiwj/c6RBs2QYQzQfbPjqMfXZi7CBiAoY3ecZ+BXROFvW1foaeKNmymX3/NbqLmwI+aVfcBuWfM
82qMdBughbvY91TNnmd20fs4X9sRAfMMNXm+STuoU0CGS15RLE8mCvB6FK40VuhV3DuBowJpCwhu
qttGfdt4FzOaiqM9YJVY++rI01UEPJcY9Dzu4Kb6BFrZEeWJ3iKows5wz9Aqt+78q6jzGFkn5R7D
JYSXM48tEmgrz8rcCJtB9+hr80LrADRvsyaBnwj/1YzlLziNHfDtnwH8Av66LZCCbg39v0BLA/1E
MyWY7eN5kcBSao+3m8Oo1qva1poQUc0UPcoR2Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
rt8qeqigKmHwNHNLDxKbJcBQ9QDjdSevpojXqtzOPOHihRQJ4iBxigwNdpHstCOFVBMqIX82UPZK
l5Z3voAz3pFaYq7dr6oHiV7oq2E0rQM5Uxhnfh46Zli/JIaRIpWf8EncPdKldj2Uf0AHq4/QV7y3
XqpPRbNfHQDneXeaciU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
lg1zM5+6ggCKkgN3qoxCvPMtnbR0lY9lPu4zV4wzZcs+UL0W1Cg00gE/3G329vCSQVnp5DAgqrYF
es9zj02SoPbANFlroyCxQjvn6Mf7ymspo+yMZhpWKlCutMCGBCKG6yQvEkkOWmJ1a/jofMJXUStD
P5832qeWGes85Bq1B9G9RJF00xScbF9hcS/9D3oCqiqCAHxxSC7iLsa2pqMcYRqQZG+qNYT6voBG
fplyLOfpmy0SbXo5116wxuki/c2xyUWMwOY5ZZScyTqrkXLycHyLaxvyh2vne5p5V5Q073iE+Nua
YsJxRHqAz8BYbH/Qqr41Ph21S2M4ldPL/JaM3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5904)
`protect data_block
lqHYkpxMxolz7h2fUWZoITda5XUgseMfPJZ/qQ9hmk7NApiNxHPZ4WI5cHcShW19oa8bTx2b9T7h
QmQlusU7GKx6vqF/E8Wg4FDyViOa/z9Ds1oPXmAq0H6lT44QOq8LuP/HaYu8vQF6KMEabMq7EGLv
GMpQlnkgTbW+AxVDtL0wXNwCy4Bon307HXof0rtzMdq6OjyPovXPty2n07/66jgTk+B/xyzM3s81
hn+O36UUs+bqcaHPXcCKgEISoJkU39rzEeLQt6besKGC5wCPuqPLeVmcIdhEI9uMJe6eg3JSr4a5
/qYJFo0EkTgcmIsmzYARCzfHx0SyNTWujPkHb/PCFMGKTnqcFgN2HMHPNTsFnuf5MkGSOgwUrYgT
bWLMhxf6nYs5W4UpN9HAVWIY6nPWC4eftdMIBy9gAXwdNcPODK0Ipyhnd/uKWQFezz/+yCMNrNxV
6Gm8Ou+Uz23QNGIJLWSGZdVW+gQ7U1gy22swp9zT2gF594fKdctmNTlC9mJPHtGgqN5PSv4O//aB
TA6bR5xxkdTYiZViNln8Z+bViIJTWFT5shOmWpB1f/Z4dZA9Ixy2KwebZgjZBozNeP37KHTbPegT
7sj4k0aTgTnrpyld9rD+j9VvSsvJ7aq3hMZhkFWe6cWs2sPvgbzooYVcubHZ3U/CmXtWjkyJchtS
fnQlZ/3xkBIPfqcSuQ289HiYNnteKjf9K7rkWqlnvO01JY9qiT5O0YVhD6GYvRKVXWqHol9YFCrU
SH/eOPVm/9Xu1itpykoEzifaUa5Ysn4ZWtWWQxkMrieKws8qdqXvducgmd2Rj3/XPNlDzH/NK5c9
hQv7jfolot5IuDB3Iq1ZhlxhkyVl23foQFHRHFU15OQqgwB0AMj9kS/GaIbCW4CNw3Tinky2BGw9
L5EklzroGQASOYKSJryx6jr2gfLLfiIqmlasMCiI2qTs8V6iCp2hkv9SXyJUHA6wz7q5JC4rrMyv
0W1tsN3ydEtVV49f3wknJDjvcgW6djeYV99rJGVSnHlT2J4pk1ar/QHSsxChrvb9IMUO1Y8PmgND
uovfx7KmHnX9RXLSltLEVrt5vzrN+XPE7z1p4G06tJfLQAx9mH4WMF6YrYXq35fY1hU0GpRi9m81
ko0Jxt44IgkaIvO35s4aUVfLnpQlLOk/OGjQn5qt6lxkLHHBdoG4yHnLFMTztLa1l7UAOir60mUX
FbIW+emCbFWcN4Igrtn7w+uLEE2XcxGldX1dhnG/EWHVEJiiGr+6T2SnXRnIgydVOO3kEMVxOZhv
Oh4LyckyfkAzeYXTYqKjODe1mvWOZ1fGlWSXcg9rEoBpCbOMm5cloI8MUlDxaZZH+rlFjNodnrp0
PQm70hcE4SgHyWkOjCMBl65Mu4MlevhvEMfoBamNZpSstDSrT06hvuCisrwBo43X8eGMa+5yCUDP
ZayODX7DnD3KkP+XJlyAV7sgk7jF6V3zcaDBn+MxQU0eAQ9z1FEj1EzAewS6dIWLtLrod+A7/bOZ
5czEHQV89Dz8wlNpve+FLx7AbP25Vx3REVtbiA1xyU1aybvwUx28+pk9JJFqWVD/XDPw9LJrynnB
S9QN6Bup292/kdy4AfJQpPKi0UQFmnQ+oyWmUxt7l5n1IELTPDpFGvflrIiJHyaoMIOyDRjrjPjP
/b4XoSHBcA+lWmTVqtpRZfRWHmOAmAPqE5pYctmkZWJmH97luj9X2f4JVukPYR6kQEePA1zCMyo5
9GixlBbLH1Xya6dObifa2M6gv957qWzcTT6bcbHZSoB++aNoobDz7mltUbG0ZdffBVYB7lYl7VnW
qmOYDndPaVeG5inxUNO6olVfEzssiWnhg8O/AScJwcVsUhpNjrx6dUSgz97wit7jdYngLiZsymqH
UAiQn4PzFuUEh7lvPCsdbm2q3Fsfeb1feX46wknSzyBge88/AuXI1gIGc8+iDEs4IADGHESFjq1j
YGlmxw1hgTnVL9F4S/zxDFmVuh2WZvGraeORhJK2I8V/k1wblr1mbuNO9fFze08Fv52kyBHXR8R9
uGB5gLe7NH99POEQv1gzHm6plGypakT0k2xkfVwdsNiMmoxeedgEiLzDIJon76xnU/CsFSlAIGVq
h+uOTSD75K623k3Tb3wq1kVlUkkNjVDYifbEJg6QuRLUCVZvWyhQ/4+GgH0ki6pMiqOq0KI4sgNU
aTIwfyCDMaJtRzT6xpXNrOfXIjX+Cl+L3pl0i+oEmwEd8dVZ30Q3PiG0cqCWYE5T7cfcZUIOwApv
biTWgrrgb2It7VF+qH7M2VLJ6u/jlpjvMH5RQTEyZ2c7xukwJ7AaGv8HBINWfFEeK9yx+fAn3+pJ
Kl1SpQWmIonXH49TwUBp0W8WabnYYBeNTR7MZrsI5/DsZ+A5F4OCqfqgYOd2TY2YgLGg+uUUFRhn
SEDSBGuFRIYb4nFRI2fDm21Hx0ajGwFmI88su2t/vv7hqJ0oumLZhFY6iXHLvvfwqQcI63y+w4a4
TBLx5W/0vJTlOa71xabH5Vj7Exfy7Rxr1IfDnMDF4+VVzDPpp3ePgP9TeLcUdJFegLM0eQrqTswi
Xrt0oUMONZ4sTlRT6VMDs3R91atbwidnsI2ggzxEqLhuNy9+vK48RgbbKvJ5KDEqPbKpqwv+HaFw
EJ0mni7vqgd6gV4ZLBDieXsdD5kY5WMCjylcguAZopKLx7TUbUaO9XySQPe3lsy17o/Ym3SUFoKT
W/uQH3MQ0uSiGQPjOWzbnEhC2sz+N7O9x4FZAQQGMQ47hIKvYnuyfa3hL3a2xNoFwd3wmt2AWt0i
rsV3iNtmcpT4EK83RUrWFbBa2dGy/fF62H/3aw0lQncrHjYDJY6bMJBmjJYWOpSQovAcraoz7XbU
O5u1bCCElNFTLQ4cFFCEoICSMuhNlGeaM8/WkoJmWzbabB9XvHGhGwbtEIYnfc86CP9UCgNPc27t
USzOrGNyNc15Ma57H+H7JSitM+faHSzkaTMEENICBgYKTZZLROlm3Z7AOybwIaN63YhOxEEYJkge
MtsHAwrDXhS3HWsFVsoE3IfGrK1oA85Bvh2DRHUbdvpDdXOk3CmmWkPVF6f3r4U1C0SLd+Gct4gA
k7Z2VfI9+aBZEStqc1vh7aaWWOHAqnRaMN3t4GHGpBt+ggiaKnPyTM6THCwfX82ye2ZeMALLQkX4
+wzSzOdvsKf0WdzApGM0jZRXpN7kCJvA5UxuEDNUo0GU+TonzxQKcs9zESwAkkm9BqZNdUk9I2JX
YPQk7iI/3Ha09pdDaOTVSq/o9amleD/kQnJgSXTHkgYLceKOLQtr1ea08SSDXxc35LDC0XYaRA7X
oo2wVDhb9EhZK0OXI4YzdTFFuRPe5+0s8rXJBznBcA52nGj5xVv1fjk0XvQADGwsxYsf1+WjJKJ+
7Gu8d8EoDPjvlddPuQL1LlZEv5bWyMF0zskDkvGiAMRMHPe+NGx6F4WJBi5JovBzXjrk9TgcGMWc
M35il3oBpcyChQ/qvRenH0RpAM+VFjWjPQUIRkeeb3XNoceo2ThrMXjRWUjOoBA0+iVwEJluhlaf
O7EAnWgWk8IHtLqmhsXtoGxX812mqbL/ZgFcenpKlrvphg55geKC5VS0rcLWJ2BQU8l1v/o+pJQx
aGrGvVIYtE8YlCOgALb1L0dW0KpJKrkR+jdn++KWlVhEE+W4VlW/xnfIGD8V1JBdV4ZnDIuBBQL4
m/arsdwwPOxjJpT7bcqzMXiJu6T0Qs9YQOPUlQEuhtyRYPkBeUpNJB/uigrGEWAWJN23eXfa1iO+
nAFWSW6NiTNsbEXXPTCOYRaR/IRGO4OOKHPY/X1xbW7aNLcuXrwhFArJcOfTiMBLKPVTuI02h/mS
Q5CniEBEy32Kz0Sw+1s6SeY6nuyrHwZ8gDrdnf94TTxYJ/z57oTr3hRAKeESBfbebsniAVArERd+
eJ/snCcWWt0gwJnGu50OlGn0IbfakFdRvXWfKFDeSmfTSAWT2epgQ8mneU1ZwgL3fhzyB0Q+cIfR
nn9n2yy/HiaF//UFErfpTp+rVEBS1XtXBNECMcehp1ozqxu5DdsNQlkrx4ME6OJ+2FeN+k4eE+VA
GQce9tVui6yvaT1I0cJwkwDDytaTdLK76ro+0bRzBpbP//l8am4xukJIwSc7tCgF8FCvcfvppN/C
0d1LlGBDw9Lw3H6+Ly/Q7gf3Qgg1ZnTtq5QdFwrgDf8rF4Vpqtsj9WWJczsOWgv9uNjbyZA12Oor
7MjgdRRMGXTxgeMe11HApsCBsd7Q3UGQNm+u8xfU+FveytaW6K0v00cIE2W6TqtARuMXi/B98YcD
ZdySNa4RWMMLkW6jS6gEbU8bttC0PO6doiJO+Pv1+JFlxWDKTRpjXZKPmdwXHYpOphIsy+kWI9zI
wtwzLkybOPfIx6xPsze4bY1lDVhvK+9kIN2B1mXgtH48MoERTQbFnqkvajzaJnN6IBnwGJVDOnrl
zhgF1W5eobSqBH53+QVt8fOFAq6bPb3mGrjfFssgFS0HeVnR1P9Gnx4D8OwUj4T0M4ka7scwVMtz
BgtWUhP1f89RscxRpMwzBmdt8r7jPQT1qwWS2Ae/ezhgA5RazD7wbsvZMi/qgmeExRGaYDK0keqy
v8xGBrgZQ+VwTxBkC4j1KgVqRmlicMVF3T2ih6fIVek1RtutzEwpXaXqxNTqlmH7IlIFcbf41Vl5
fpneTlpXdCbWAKO8K0GKQWLCiw/JV4YXvu/eVxfp5eU9cdS0uzCuoZ79x7s7OR6Ia75mznTwB3IX
sTaamKspTmYHW7SFuYIF9g+Iz/Iyk788d6Lufw4r9bfPYqdBnN3XLvSJvb2rz3I0zsiUjNn7xBG5
/IkPU+tCakS0fUJiwTfmVq0/Qu5neXl8gNkBx9gLWdUUHUqxymV1z5Nm8eIU90gOx6irY8sRBui3
hndkc9jyghwDnMBzufvUoJdnG4dsIe555vMhp9WodE/CYCGB8LLwhQn88PkO0N3+ijxNbfplmpc3
Glq621qieDez1abEtngireC0WdRg5qwjVbpZiBybD1vxOm1wb16rb+JbkbLfrnNAuJMS8x+2XyGU
jGWUJhUikpTFG8ibGXxZ7hytO+575FE/g3YVBhLkNIynWIzdO+h0XUSnJhn+Okd/h2vb4nnrWZKC
uxEPDujSBqtk6nQNYhvKfp1bBwFgOt2Ojq/bjZJLJ3OnnqisIUxaETDl04qLhBdJTNYROqBHsVKA
olswnFmRAgfHj0gvzprDAMKI1WrTZ9Qhi+dasMkN582DGIiSYWLxEZkHQZ9gOhOwnJdZY6zFnnNz
rmGvGR1tccKH9ISBmm1QAN7+RbBt1yVU2b8tEvyRx+ezcOS4UedUm06e5MaiJ1MIgb0Hh/pWHpZV
yc/6rghD6cQvgV63NFHXGgnG6JR1vcj/kQsvWj5BQFvYaZe/vFBG5iAwE1dMNpQXBlManQAChtsB
h7EPAF6v3/ldXSMcFvhp8tX5XnNJqWLRPhAwvci+oDj2aG3DhRf662AImwzl6mFFN04eDTKRQaKN
rPAK948jebaRaxWqOfJzNGWTZvSnsHwUGusvqnz37b4cJQA9uVUl2nZOaKmzqRW+nrksqhlOcW6w
8KDAIF4pKmHMjJGYv9uGkhc5TWqlLPkY4mjA2oXNPuqfYGpGnSYHkbpA/dmnYP3cp9Ci2umK+kqW
bXc3d/slRVf20/9KtXZKZbNRPXY0Ir38X0rryr2m/YRPf1YqLl+kk8qSN554qhnA3BwkaRZ5U+7r
3MXrFw41tQxNzPGmZVu6wvqq62/8IblKpQJdLTXbGzyAggdlwNihRFBOAnCgz72rC47XfvOy5muO
DGVn74GcC4MV4fu7GZcltlMNkd4xFOk4L+nz+zQWQhqApjCQSJBdNOQJ6qbipPbWTX6LAQhq1DIy
Bum5VWytfElpPbLtVLYuf78PJBXITDufi9b7oKa81VcpJ1vjvQ0ccUwOrRHRRsOgAGFd8Mpd77jh
TrNh2psD3OEd8nl3wj1lO7FrGivsIh871QFgs5IGYauI4JI6TP9cV9klsIdQeILLbVFqdn9sBMy5
JHJxbWYzvECyxJdxsqgdtOZezjPtIVyG5ihcHSpRE+l98IDgFrPZ7FymD6Tu4B7GZAZU4DNkQ4tS
SScDeEpZl5QkC6QuX7cEU4O8GsAjeKMTgu+DdemXzQFtrRJG0QQM2aHeCBUHHtSaikd6V8tyQzut
HGia9zcKfgLhTgG8QPQudrNfRl0CKTEFBFaR2DGYYyFOQLXxSnIOUIEgx/zDP4Cs/PxX3k6IdWJK
L48iR9JU/4HyH8LrhM1VdtFDNwop+HVRsb4PuHfoPvh3gCW0nAOi5aEC1xvo5It4XmLB4U+fLNIp
Vz5qlF7BcznJfTBXWKmYPfYZKcDEm+M0Ha+ocb4LE24+SopkBd/WtZyYTZpT2zBG+3Xs6bGK793w
11Am0S6i+Tz4Dc1avYM0NEutti5GDi0fKAE9ZhpLH3C04pAQTWVrSUYtB6xvNNsTEQktT1585vEq
P1yWuPyptXe5EzsR5bMtsK23sKlNfb9+GsGM9nmlouVnNIMkXDzsg1jwTNIfSBdHLGe2kR6hfv0r
fwJf35ucx8cFdEf2prPjPAZfE/8xa3Xe+gRmXCGHIqWmUBHbDunbAJv+s5Fwh6nIP1Pt7ZzZ/GeG
Qg+jXJCSuk9T1MgckEqbOvGuDiAE+uQ0YXQ7dIrE2gvg71d3nuwP9v5QtKAlb65PVFJhepkG/DbS
ZSirO+HO6FqupYfGSe7c2DtuVAml21LcOJFtYY0/xhoxBd/7hia+5XiP2iQf0Xvgf0Kf6AQqZpV5
/9JdEHvGcUjL09Vm5LrK4Spc9RJMGW29VpENph/RIjQNhw6KkztZyuUmOG0OoiAVE4dqSQ416BX7
69RJ/QEP8LvdqEw4x6Q+0imgsDVVIdIi4gWOZ0eIjIQ49iL9RQapUG3blLxERuvQ40tthjcJPYGH
+m1KUxFxPExdOAJDHH/RfIXQYI2q/6+fcZGs+IUrb8JvzO7TjvQeerDGx3yqBH4tBghLHxBQ6m8T
Okrsgum8l4kvMu9rh8sY2VjFJBBkQzLo+CovwV3K1E8cCcy2rsfLfNcAYMRdluq3zY8ELvsk7BWO
IOyG1fK5tq4VdkPhcsCn2zRfYNbw1Pj+s61YLlVIfD+IezBJAhw90KRX1uEhZOIytDKjCfu/y3Yb
T8jqAG6qFP1554qsNlbSZIm2DlQ46lCuwcs2UQlJe3y7Np4xmZiT4ciJ2WR1TM2I7jj0xfVuHOVF
Lhr6HGznaVI4TGhjuxuf7W5YilR3RvVlHBQckHGcPH0CFabesC2ObRKkv01F8grikTK13yOeMK2c
S5AE66uNG8N+57E8yWWwgcU+aqt3G9nB0UWCUdpC9tdpN3sXB3DoNHJ1JDdsHlouyLJZO9pyIsD2
Sldl14WBv8JdSQ+XwgEqFAQ9da/Ho9pOlMfFUSFvLa87JLUfWgKle9zbtX1PjeGFmZNILSlxwrax
F+U2vNX+BW0VBpEFcCD8Q7Hel1EJ1/brN3JdoWxpfP+S+W/zo2pvfEJ8MUkz7CnCtSHFU57Cq1vO
vPYzp0TJRMXEqw9FDxmf10fAl75X6Zf65+EKxRpUoQKh1BnF1+uwhm5ZouI6WhC2xbWNHbR5Qjm/
xZ2wt4CsmUcrA9eZA7P06/HG/cHHWj6x/UzuMnuxkBXnmi3UkcpZa5Rl6u4eY0pO2o4PozCcuZUr
GWTBs6pw3oRPHecsvkzzaSvHbAkIkPibdDLhQxe2azyyNSpx+VdUOodtviZPhiiYRa6f1pdg/t+y
3rz+lPb0h+Zhd+A8qW4UNhqzdD6LPHTc5cbeIpzvIzHN
`protect end_protected
|
entity tb_top is
end tb_top;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_top is
signal clk : std_logic;
signal x, y : std_logic_vector (1 downto 0);
signal data : std_logic_vector (3 downto 0);
begin
dut: entity work.top
port map (clk, x, y, data);
process
procedure pulse is
begin
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end pulse;
begin
clk <= '0';
x <= "00";
y <= "00";
pulse;
assert data = "0001" severity failure;
x <= "10";
pulse;
assert data = "1110" severity failure;
y <= "01";
pulse;
assert data = "1101" severity failure;
x <= "10";
y <= "11";
pulse;
assert data = "0111" severity failure;
wait;
end process;
end behav;
|
-------------------------------------------------------------------------------
-- axi_vdma_fsync_gen
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_fsync_gen.vhd
-- Description: This entity generates the frame sync for vdma operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_fsync_gen is
generic (
C_USE_FSYNC : integer range 0 to 1 := 0;
-- Specifies DMA oeration synchronized to frame sync input
-- 0 = Free running
-- 1 = Fsync synchronous
ENABLE_FLUSH_ON_MM2S_FSYNC : integer range 0 to 1 := 0 ;
ENABLE_FLUSH_ON_S2MM_FSYNC : integer range 0 to 1 := 0 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 0 ;
C_INCLUDE_MM2S : integer range 0 to 1 := 0 ;
C_SOF_ENABLE : integer range 0 to 1 := 0
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Frame Count Enable Support --
valid_video_prmtrs : in std_logic ; --
valid_frame_sync_cmb : in std_logic ; --
frmcnt_ioc : in std_logic ; --
dmacr_frmcnt_enbl : in std_logic ; --
dmasr_frmcnt_status : in std_logic_vector(7 downto 0) ; --
mask_fsync_out : out std_logic ; --
--
-- VDMA status for free run (C_USE_FSYNC = 0) --
run_stop : in std_logic ; --
all_idle : in std_logic ; --
parameter_update : in std_logic ; --
--
-- Frame Sync Sources (C_USE_FSYNC = 1) --
fsync : in std_logic ; --
tuser_fsync : in std_logic ; --
othrchnl_fsync : in std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
--
-- Sync out for VDMA logic --
frame_sync : out std_logic ; --
--
-- Sync / Update out top level for Video IP --
frame_sync_out : out std_logic ; --
prmtr_update : out std_logic --
);
end axi_vdma_fsync_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_fsync_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant FRAME_COUNT_ONE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(1,8));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- No Signals Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Generate Free Run Mode (Internal Frame Sync)
-------------------------------------------------------------------------------
GEN_FREE_RUN_MODE : if C_USE_FSYNC = 0 generate
-- For internal fsync generation
signal all_idle_d1 : std_logic := '0';
signal all_idle_d2 : std_logic := '0';
signal all_idle_re : std_logic := '0';
-- For internal fsync and fsync out
signal frame_sync_aligned : std_logic := '0';
signal frame_sync_i : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- Register all idle for use in creating rising edge pulse
REG_IDLE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
-- On reset clear flag
if(prmry_resetn = '0')then
all_idle_d1 <= '0';
all_idle_d2 <= '0';
-- Otherwise pass idle state through to gen re pulse
else
all_idle_d1 <= all_idle;
all_idle_d2 <= all_idle_d1;
end if;
end if;
end process REG_IDLE;
all_idle_re <= all_idle_d1 and not all_idle_d2;
-- Register frame sync source to shift all processes started
-- by fsync 1 clock later in time. This allows initial FrameDelay
-- and resulting calculation to be registered before
-- being latched by frame_sync.
REG_FSYNC_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_i <= '0';
else
frame_sync_i <= all_idle_re and run_stop;
end if;
end if;
end process REG_FSYNC_PROCESS;
-- Pass out for internal use (secondary clock domain)
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FREE_RUN_MODE;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_MM2S_NO_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_MM2S = 1 and (ENABLE_FLUSH_ON_MM2S_FSYNC = 0 or C_SOF_ENABLE = 0)) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
---- end generate GEN_FSYNC_NO_SOF;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_MM2S_NO_SOF;
GEN_FSYNC_MODE_MM2S_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_MM2S = 1 and ENABLE_FLUSH_ON_MM2S_FSYNC = 1 and C_SOF_ENABLE = 1) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
frame_sync_i <= fsync;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_MM2S_SOF;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_S2MM_NON_FLUSH : if (C_USE_FSYNC = 1 and C_INCLUDE_S2MM = 1 and ENABLE_FLUSH_ON_S2MM_FSYNC = 0) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- generate fsync from tuser
GEN_FSYNC_FOR_SOF : if C_SOF_ENABLE = 1 generate
begin
-- frame_sync_i <= tuser_fsync and run_stop;
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync,
tuser_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when "10" => -- tuser fsync (used only by s2mm)
frame_sync_i <= tuser_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
end generate GEN_FSYNC_FOR_SOF;
-- generate fsync from fsync
GEN_FSYNC_NO_SOF : if C_SOF_ENABLE = 0 generate
begin
-- Internal fsync on fe for vdma if running
--frame_sync_i <= fsync and run_stop;
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
end generate GEN_FSYNC_NO_SOF;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_S2MM_NON_FLUSH;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_S2MM_FLUSH_NON_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_S2MM = 1 and ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and C_SOF_ENABLE = 0) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_S2MM_FLUSH_NON_SOF;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_S2MM_FLUSH_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_S2MM = 1 and ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and C_SOF_ENABLE = 1) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
frame_sync_i <= fsync;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_S2MM_FLUSH_SOF;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_fsync_gen
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_fsync_gen.vhd
-- Description: This entity generates the frame sync for vdma operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_fsync_gen is
generic (
C_USE_FSYNC : integer range 0 to 1 := 0;
-- Specifies DMA oeration synchronized to frame sync input
-- 0 = Free running
-- 1 = Fsync synchronous
ENABLE_FLUSH_ON_MM2S_FSYNC : integer range 0 to 1 := 0 ;
ENABLE_FLUSH_ON_S2MM_FSYNC : integer range 0 to 1 := 0 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 0 ;
C_INCLUDE_MM2S : integer range 0 to 1 := 0 ;
C_SOF_ENABLE : integer range 0 to 1 := 0
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Frame Count Enable Support --
valid_video_prmtrs : in std_logic ; --
valid_frame_sync_cmb : in std_logic ; --
frmcnt_ioc : in std_logic ; --
dmacr_frmcnt_enbl : in std_logic ; --
dmasr_frmcnt_status : in std_logic_vector(7 downto 0) ; --
mask_fsync_out : out std_logic ; --
--
-- VDMA status for free run (C_USE_FSYNC = 0) --
run_stop : in std_logic ; --
all_idle : in std_logic ; --
parameter_update : in std_logic ; --
--
-- Frame Sync Sources (C_USE_FSYNC = 1) --
fsync : in std_logic ; --
tuser_fsync : in std_logic ; --
othrchnl_fsync : in std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
--
-- Sync out for VDMA logic --
frame_sync : out std_logic ; --
--
-- Sync / Update out top level for Video IP --
frame_sync_out : out std_logic ; --
prmtr_update : out std_logic --
);
end axi_vdma_fsync_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_fsync_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant FRAME_COUNT_ONE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(1,8));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- No Signals Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Generate Free Run Mode (Internal Frame Sync)
-------------------------------------------------------------------------------
GEN_FREE_RUN_MODE : if C_USE_FSYNC = 0 generate
-- For internal fsync generation
signal all_idle_d1 : std_logic := '0';
signal all_idle_d2 : std_logic := '0';
signal all_idle_re : std_logic := '0';
-- For internal fsync and fsync out
signal frame_sync_aligned : std_logic := '0';
signal frame_sync_i : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- Register all idle for use in creating rising edge pulse
REG_IDLE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
-- On reset clear flag
if(prmry_resetn = '0')then
all_idle_d1 <= '0';
all_idle_d2 <= '0';
-- Otherwise pass idle state through to gen re pulse
else
all_idle_d1 <= all_idle;
all_idle_d2 <= all_idle_d1;
end if;
end if;
end process REG_IDLE;
all_idle_re <= all_idle_d1 and not all_idle_d2;
-- Register frame sync source to shift all processes started
-- by fsync 1 clock later in time. This allows initial FrameDelay
-- and resulting calculation to be registered before
-- being latched by frame_sync.
REG_FSYNC_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_i <= '0';
else
frame_sync_i <= all_idle_re and run_stop;
end if;
end if;
end process REG_FSYNC_PROCESS;
-- Pass out for internal use (secondary clock domain)
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FREE_RUN_MODE;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_MM2S_NO_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_MM2S = 1 and (ENABLE_FLUSH_ON_MM2S_FSYNC = 0 or C_SOF_ENABLE = 0)) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
---- end generate GEN_FSYNC_NO_SOF;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_MM2S_NO_SOF;
GEN_FSYNC_MODE_MM2S_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_MM2S = 1 and ENABLE_FLUSH_ON_MM2S_FSYNC = 1 and C_SOF_ENABLE = 1) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
frame_sync_i <= fsync;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_MM2S_SOF;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_S2MM_NON_FLUSH : if (C_USE_FSYNC = 1 and C_INCLUDE_S2MM = 1 and ENABLE_FLUSH_ON_S2MM_FSYNC = 0) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- generate fsync from tuser
GEN_FSYNC_FOR_SOF : if C_SOF_ENABLE = 1 generate
begin
-- frame_sync_i <= tuser_fsync and run_stop;
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync,
tuser_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when "10" => -- tuser fsync (used only by s2mm)
frame_sync_i <= tuser_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
end generate GEN_FSYNC_FOR_SOF;
-- generate fsync from fsync
GEN_FSYNC_NO_SOF : if C_SOF_ENABLE = 0 generate
begin
-- Internal fsync on fe for vdma if running
--frame_sync_i <= fsync and run_stop;
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
end generate GEN_FSYNC_NO_SOF;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_S2MM_NON_FLUSH;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_S2MM_FLUSH_NON_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_S2MM = 1 and ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and C_SOF_ENABLE = 0) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_S2MM_FLUSH_NON_SOF;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_S2MM_FLUSH_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_S2MM = 1 and ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and C_SOF_ENABLE = 1) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
frame_sync_i <= fsync;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_S2MM_FLUSH_SOF;
end implementation;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Virtex-7 MIG.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.all;
use gaisler.ahb2mig_7series_pkg.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library std;
use std.textio.all;
entity ahb2mig_7series is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end ;
architecture rtl of ahb2mig_7series is
type bstate_type is (idle, start, read_cmd, read_data, read_wait, read_output, write_cmd, write_burst);
constant maxburst : integer := 8;
constant maxmigcmds : integer := nbrmaxmigcmds(AHBDW);
constant wrsteps : integer := log2(32);
constant wrmask : integer := log2(32/8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIG_7SERIES, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIG_7SERIES, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd : std_logic_vector(2 downto 0);
cmd_en : std_logic;
wr_en : std_logic;
wr_end : std_logic;
cmd_count : unsigned(31 downto 0);
wr_count : unsigned(31 downto 0);
rd_count : unsigned(31 downto 0);
hready : std_logic;
hwrite : std_logic;
hwdata_burst : std_logic_vector(512*maxmigcmds-1 downto 0);
mask_burst : std_logic_vector(64*maxmigcmds-1 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(31 downto 0);
haddr_start : std_logic_vector(31 downto 0);
haddr_offset : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
int_buffer : unsigned(512*maxmigcmds-1 downto 0);
rd_buffer : unsigned(512*maxmigcmds-1 downto 0);
wdf_data_buffer : std_logic_vector(511 downto 0);
wdf_mask_buffer : std_logic_vector(63 downto 0);
migcommands : integer;
nxt : std_logic;
end record;
type mig_in_type is record
app_addr : std_logic_vector(27 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
app_wdf_data : std_logic_vector(511 downto 0);
app_wdf_end : std_logic;
app_wdf_mask : std_logic_vector(63 downto 0);
app_wdf_wren : std_logic;
end record;
type mig_out_type is record
app_rd_data : std_logic_vector(511 downto 0);
app_rd_data_end : std_logic;
app_rd_data_valid : std_logic;
app_rdy : std_logic;
app_wdf_rdy : std_logic;
end record;
signal rin, r, rnxt, rnxtin : reg_type;
signal migin : mig_in_type;
signal migout,migoutraw : mig_out_type;
signal debug : std_logic := '0';
signal size_to_watch : std_logic_vector(2 downto 0) := HSIZE_4WORD;
component mig is
port (
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
app_addr : in std_logic_vector(27 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(511 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(63 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(511 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig;
component mig_interface_model is
port (
app_addr : in std_logic_vector(27 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(511 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(63 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(511 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig_interface_model;
begin
comb: process( rst_n_syn, r, rin, ahbsi, migout )
-- Design temp variables
variable v,vnxt : reg_type;
variable writedata : std_logic_vector(255 downto 0);
variable wmask : std_logic_vector(AHBDW/4-1 downto 0);
variable shift_steps : natural;
variable hrdata_shift_steps : natural;
variable steps_write : unsigned(31 downto 0);
variable shift_steps_write : natural;
variable shift_steps_write_mask : natural;
variable startaddress : unsigned(v.haddr'length-1 downto 0);
variable start_address : std_logic_vector(v.haddr'length-1 downto 0);
variable step_offset : unsigned(steps_write'length-1 downto 0);
variable haddr_offset : unsigned(steps_write'length-1 downto 0);
begin
-- Make all register visible for the statemachine
v := r; vnxt := rnxt;
-- workout the start address in AHB2MIG buffer based upon
startaddress := resize(unsigned(unsigned(ahbsi.haddr(ahbsi.haddr'left-3 downto 8)) & "00000"),startaddress'length);
-- Adjust offset in memory buffer
startaddress := resize(startaddress + unsigned(unsigned(ahbsi.haddr(7 downto 6))&"000"),startaddress'length);
start_address := std_logic_vector(startaddress);
-- Workout local offset to be able to adust for warp-around
haddr_offset := unsigned(r.haddr_start) - unsigned(unsigned(r.haddr_offset(r.haddr_offset'length-1 downto 6))&"000000");
step_offset := resize(unsigned(haddr_offset(7 downto 6)&"0000"),step_offset'length);
-- Fetch AMBA Commands
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready and not ahbsi.htrans(0)) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
vnxt.cmd_count:= (others => '0');
vnxt.wr_count := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.hrdata := (others => '0');
-- Clear old pointers and MIG command signals
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
-- Hold info regarding transaction and execute
vnxt.hburst := ahbsi.hburst;
vnxt.hwrite := ahbsi.hwrite;
vnxt.hsize := ahbsi.hsize;
vnxt.hmaster := ahbsi.hmaster;
vnxt.hready := '0';
vnxt.htrans := ahbsi.htrans;
vnxt.bstate := start;
vnxt.haddr := start_address;
vnxt.haddr_start := ahbsi.haddr;
vnxt.haddr_offset := ahbsi.haddr;
vnxt.cmd(2 downto 0) := (others => '0');
vnxt.cmd(0) := not ahbsi.hwrite;
if (r.bstate = idle) then vnxt.nxt := '0'; else vnxt.nxt := '1'; end if;
-- Clear some old stuff
vnxt.int_buffer := (others => '0');
vnxt.rd_buffer := (others => '0');
vnxt.wdf_data_buffer := (others => '0');
vnxt.wdf_mask_buffer := (others => '0');
end if;
case r.bstate is
when idle =>
-- Clear old pointers and MIG command signals
v.cmd := (others => '0');
v.cmd_en := '0';
v.wr_en := '0';
v.wr_end := '0';
v.hready := '1';
v.hwrite := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.rd_count := (others => '0');
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hready := '1';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.wr_count := (others => '0');
vnxt.cmd_count := (others => '0');
-- Check if this is a single or burst transfer (and not a BUSY transfer)
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
-- Hold info regarding transaction and execute
v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
v.htrans := ahbsi.htrans;
v.bstate := start;
v.haddr := start_address;
v.haddr_start := ahbsi.haddr;
v.haddr_offset := ahbsi.haddr;
v.cmd := (others => '0');
v.cmd(0) := not ahbsi.hwrite;
end if;
when start =>
v.migcommands := nbrmigcmds(r.hwrite,r.hsize,ahbsi.htrans,step_offset,AHBDW);
-- Check if a write command shall be issued to the DDR3 memory
if r.hwrite = '1' then
wmask := (others => '0');
writedata := (others => '0');
if ((ahbsi.htrans /= HTRANS_SEQ) or ((ahbsi.htrans = HTRANS_SEQ) and (r.rd_count > 0) and (r.rd_count <= maxburst))) then
-- work out how many steps we need to shift the input
steps_write := ahbselectdatanoreplicastep(r.haddr_start(7 downto 2),r.hsize(2 downto 0)) + step_offset;
shift_steps_write := to_integer(shift_left(steps_write,wrsteps));
shift_steps_write_mask := to_integer(shift_left(steps_write,wrmask));
-- generate mask for complete burst (only need to use addr[3:0])
wmask := ahbselectdatanoreplicamask(r.haddr_start(6 downto 0),r.hsize(2 downto 0));
v.mask_burst := r.mask_burst or std_logic_vector(shift_left(resize(unsigned(wmask), r.mask_burst'length),shift_steps_write_mask));
-- fetch all wdata before write to memory can begin (only supports upto 128bits i.e. addr[4:0]
writedata(AHBDW-1 downto 0) := ahbselectdatanoreplica(ahbsi.hwdata(AHBDW-1 downto 0),r.haddr_start(4 downto 0),r.hsize(2 downto 0));
v.hwdata_burst := r.hwdata_burst or std_logic_vector(shift_left(resize(unsigned(writedata),v.hwdata_burst'length),shift_steps_write));
v.haddr_start := ahbsi.haddr;
end if;
-- Check if this is a cont burst longer than internal buffer
if (ahbsi.htrans = HTRANS_SEQ) then
if (r.rd_count < maxburst-1) then
v.hready := '1';
else
v.hready := '0';
end if;
if (r.rd_count >= maxburst) then
if (r.htrans = HTRANS_SEQ) then
v.bstate := write_cmd;
end if;
v.htrans := ahbsi.htrans;
end if;
else
v.bstate := write_cmd;
v.htrans := ahbsi.htrans;
end if;
-- Else issue a read command when ready
else
if migout.app_rdy = '1' and migout.app_wdf_rdy = '1' then
v.cmd := "001";
v.bstate := read_cmd;
v.htrans := ahbsi.htrans;
v.cmd_count := to_unsigned(0,v.cmd_count'length);
end if;
end if;
when write_cmd =>
-- Check if burst has ended due to max size burst
if (ahbsi.htrans /= HTRANS_SEQ) then
v.htrans := (others => '0');
end if;
-- Stop when addr and write command is accepted by mig
if (r.wr_count >= r.migcommands) and (r.cmd_count >= r.migcommands) then
if (r.htrans /= HTRANS_SEQ) then
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
else
v.bstate := idle;
end if;
else -- Cont burst and work out new offset for next write command
v.bstate := write_burst;
v.hready := '1';
end if;
end if;
when write_burst =>
v.bstate := start;
v.hready := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
end if;
when read_cmd =>
v.hready := '0';
v.rd_count := (others => '0');
-- stop when read command is accepted ny mig.
if (r.cmd_count >= r.migcommands) then
v.bstate := read_data;
--v.int_buffer := (others => '0');
end if;
when read_data =>
-- We are not ready yet so issue a read command to the memory controller
v.hready := '0';
-- If read data is valid store data in buffers
if (migout.app_rd_data_valid = '1') then
v.rd_count := r.rd_count + 1;
-- Viviado seems to misinterpet the following shift construct and
-- therefore changed to a if-else statement
--v.int_buffer := r.int_buffer or shift_left( resize(unsigned(migout.app_rd_data),r.int_buffer'length),
-- to_integer(shift_left(r.rd_count,9)));
if (r.rd_count = 0) then
v.int_buffer(511 downto 0) := unsigned(migout.app_rd_data);
elsif (r.rd_count = 1) then
v.int_buffer(1023 downto 512) := unsigned(migout.app_rd_data);
elsif (AHBDW > 64) then
if (r.rd_count = 2) then
v.int_buffer(1535 downto 1024) := unsigned(migout.app_rd_data);
else
v.int_buffer(2047 downto 1536) := unsigned(migout.app_rd_data);
end if;
end if;
end if;
if (r.rd_count >= r.migcommands) then
v.rd_buffer := r.int_buffer;
v.bstate := read_output;
v.rd_count := to_unsigned(0,v.rd_count'length);
end if;
when read_output =>
-- Data is fetched from memory and ready to be transfered
v.hready := '1';
-- uses the "wr_count" signal to keep track of number of bytes output'd to AHB
-- Select correct 32bit/64bit/128bit to output
v.hrdata := ahbselectdatanoreplicaoutput(r.haddr_start(7 downto 0),r.wr_count,r.hsize,r.rd_buffer,r.wr_count,true);
-- Count number of bytes send
v.wr_count := r.wr_count + 1;
-- Check if this was the last transaction
if (r.wr_count >= maxburst-1) then
v.bstate := read_wait;
end if;
-- Check if transfer was interrupted or no burst
if (ahbsi.htrans = HTRANS_IDLE) or ((ahbsi.htrans = HTRANS_NONSEQ) and (r.wr_count < maxburst)) then
v.bstate := read_wait;
v.wr_count := (others => '0');
v.rd_count := (others => '0');
v.cmd_count := (others => '0');
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
end if;
end if;
when read_wait =>
if ((r.wr_count >= maxburst) and (ahbsi.htrans = HTRANS_SEQ)) then
v.hready := '0';
v.bstate := start;
v.haddr_start := ahbsi.haddr;
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
else
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
else
v.bstate := idle;
v.hready := '1';
end if;
end if;
when others =>
v.bstate := idle;
end case;
if ((ahbsi.htrans /= HTRANS_SEQ) and (r.bstate = start)) then
v.hready := '0';
end if;
if rst_n_syn = '0' then
v.bstate := idle; v.hready := '1'; v.cmd_en := '0'; v.wr_en := '0'; v.wr_end := '0';
--v.wdf_mask_buffer := (others => '0'); v.wdf_data_buffer := (others => '0'); v.haddr := (others => '0');
end if;
rin <= v;
rnxtin <= vnxt;
end process;
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= ahbdrivedata(r.hrdata);
migin.app_addr <= r.haddr(27 downto 2) & "00";
migin.app_cmd <= r.cmd;
migin.app_en <= r.cmd_en;
migin.app_wdf_data <= r.wdf_data_buffer;
migin.app_wdf_end <= r.wr_end;
migin.app_wdf_mask <= r.wdf_mask_buffer;
migin.app_wdf_wren <= r.wr_en;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
-- Copy variables into registers (Default values)
r <= rin;
rnxt <= rnxtin;
-- add extra pipe-stage for read data
migout <= migoutraw;
-- IDLE Clear
if ((r.bstate = idle) or (r.bstate = read_wait)) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
if (r.bstate = write_burst) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= to_unsigned(1,r.rd_count'length);
end if;
-- Read AHB write data
if (r.bstate = start) and (r.hwrite = '1') then
r.rd_count <= r.rd_count + 1;
end if;
-- Write command repsonse
if r.bstate = write_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
if (r.wr_count < 1 ) then
r.wr_en <= '1';
r.wr_end <= '1';
r.wdf_mask_buffer <= not r.mask_burst(63 downto 0);
r.wdf_data_buffer <= r.hwdata_burst(511 downto 0);
end if;
if (migoutraw.app_wdf_rdy = '1') and (r.wr_en = '1' ) then
if (r.wr_count = 0) then
r.wdf_mask_buffer <= not r.mask_burst(127 downto 64);
r.wdf_data_buffer <= r.hwdata_burst(1023 downto 512);
elsif (AHBDW > 64) then
if (r.wr_count = 1) then
r.wdf_mask_buffer <= not r.mask_burst(191 downto 128);
r.wdf_data_buffer <= r.hwdata_burst(1535 downto 1024);
else
r.wdf_mask_buffer <= not r.mask_burst(255 downto 192);
r.wdf_data_buffer <= r.hwdata_burst(2047 downto 1536);
end if;
else
r.wdf_mask_buffer <= not r.mask_burst(127 downto 64);
r.wdf_data_buffer <= r.hwdata_burst(1023 downto 512);
end if;
r.wr_count <= r.wr_count + 1;
if (r.wr_count >= r.migcommands - 1) then
r.wr_en <= '0';
r.wr_end <= '0';
end if;
end if;
end if;
-- Burst Write Wait
if r.bstate = write_burst then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
-- Read command repsonse
if r.bstate = read_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
end if;
end if;
end process;
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
MCB_inst : mig
port map (
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
clk_ref_i => clk_ref_i,
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
MCB_model_inst : mig_interface_model
port map (
-- user interface signals
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_reset_n <= '1';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_cs_n <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
end generate gen_mig_model;
end;
|
-- NEED RESULT: ARCH00177.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00177: One inertial transaction occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00177
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00177(ARCH00177)
-- ENT00177_Test_Bench(ARCH00177_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00177 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00177 ;
--
architecture ARCH00177 of ENT00177 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00177.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00177" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00177" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00177" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00177" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00177" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
--
end ARCH00177 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00177_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00177_Test_Bench ;
--
architecture ARCH00177_Test_Bench of ENT00177_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00177 ( ARCH00177 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
) ;
end block L1 ;
end ARCH00177_Test_Bench ;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 20:25:56 06/03/2011
-- Design Name:
-- Module Name: IP_complete - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implements complete IP stack with ARP and MAC
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IP_complete is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
clk_in_p : in std_logic; -- 200MHz clock input from board
clk_in_n : in std_logic;
clk_out : out std_logic;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- GMII Interface
phy_resetn : out std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
gmii_col : in std_logic;
gmii_crs : in std_logic;
mii_tx_clk : in std_logic
);
end IP_complete;
architecture structural of IP_complete is
------------------------------------------------------------------------------
-- Component Declaration for the IP layer
------------------------------------------------------------------------------
COMPONENT IP_complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for the MAC layer
------------------------------------------------------------------------------
component mac_layer_v2_1
port (
-- System controls
------------------
glbl_rst : in std_logic; -- asynchronous reset
mac_reset : in std_logic; -- reset mac layer
clk_in_p : in std_logic; -- 200MHz clock input from board
clk_in_n : in std_logic;
-- MAC Transmitter (AXI-S) Interface
---------------------------------------------
mac_tx_clock : out std_logic; -- data sampled on rising edge
mac_tx_tdata : in std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : in std_logic; -- tdata is valid
mac_tx_tready : out std_logic; -- mac is ready to accept data
mac_tx_tlast : in std_logic; -- indicates last byte of frame
-- MAC Receiver (AXI-S) Interface
------------------------------------------
mac_rx_clock : out std_logic; -- data valid on rising edge
mac_rx_tdata : out std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : out std_logic; -- indicates tdata is valid
mac_rx_tready : in std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : out std_logic; -- indicates last byte of the trame
-- GMII Interface
-----------------
phy_resetn : out std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
gmii_col : in std_logic;
gmii_crs : in std_logic;
mii_tx_clk : in std_logic
);
end component;
---------------------------
-- Signals
---------------------------
-- MAC RX bus
signal mac_rx_clock : std_logic;
signal mac_rx_tdata : std_logic_vector (7 downto 0);
signal mac_rx_tvalid : std_logic;
signal mac_rx_tready : std_logic;
signal mac_rx_tlast : std_logic;
-- MAC TX bus
signal mac_tx_clock : std_logic;
signal mac_tx_tdata : std_logic_vector (7 downto 0);
signal mac_tx_tvalid : std_logic;
signal mac_tx_tready : std_logic;
signal mac_tx_tlast : std_logic;
-- control signals
signal mac_tx_tready_int : std_logic;
signal mac_tx_granted_int : std_logic;
begin
clk_out <= mac_rx_clock;
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_layer : IP_complete_nomac
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
PORT MAP (
-- IP Layer signals
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
-- system signals
rx_clk => mac_rx_clock,
tx_clk => mac_rx_clock,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
control => control,
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
-- MAC Transmitter
mac_tx_tready => mac_tx_tready_int,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tfirst => open,
mac_tx_tlast => mac_tx_tlast,
mac_tx_tdata => mac_tx_tdata,
-- MAC Receiver
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
------------------------------------------------------------------------------
-- Instantiate the MAC layer
------------------------------------------------------------------------------
mac_block : mac_layer_v2_1
Port map(
-- System controls
------------------
glbl_rst => reset,
mac_reset => '0',
clk_in_p => clk_in_p,
clk_in_n => clk_in_n,
-- MAC Transmitter (AXI-S) Interface
---------------------------------------------
mac_tx_clock => mac_tx_clock,
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready_int,
mac_tx_tlast => mac_tx_tlast,
-- MAC Receiver (AXI-S) Interface
------------------------------------------
mac_rx_clock => mac_rx_clock,
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast,
-- GMII Interface
-----------------
phy_resetn => phy_resetn,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
gmii_col => gmii_col,
gmii_crs => gmii_crs,
mii_tx_clk => mii_tx_clk
);
end structural;
|
entity issue188 is
end entity;
architecture test of issue188 is
type ft is file of boolean;
function file_func return boolean is
file f : ft; -- Error
variable b : boolean;
begin
read(f, b);
return b;
end function;
impure function file_func_impure return boolean is
file f : ft; -- OK
variable b : boolean;
begin
read(f, b);
return b;
end function;
file f : ft;
function file_func2 return boolean is
variable b : boolean;
begin
read(f, b); -- Error
return b;
end function;
procedure read_b(b : out boolean) is
begin
read(f, b);
end procedure;
procedure call_read_b(b : out boolean) is
begin
read_b(b);
end procedure;
function call_call_read_b return boolean is
variable b : boolean;
begin
call_read_b(b); -- Error
return b;
end procedure;
shared variable x : integer;
procedure update_x is
begin
x := 2;
end procedure;
function call_update_x return boolean is
begin
update_x;
return true;
end procedure;
begin
end architecture;
|
entity issue188 is
end entity;
architecture test of issue188 is
type ft is file of boolean;
function file_func return boolean is
file f : ft; -- Error
variable b : boolean;
begin
read(f, b);
return b;
end function;
impure function file_func_impure return boolean is
file f : ft; -- OK
variable b : boolean;
begin
read(f, b);
return b;
end function;
file f : ft;
function file_func2 return boolean is
variable b : boolean;
begin
read(f, b); -- Error
return b;
end function;
procedure read_b(b : out boolean) is
begin
read(f, b);
end procedure;
procedure call_read_b(b : out boolean) is
begin
read_b(b);
end procedure;
function call_call_read_b return boolean is
variable b : boolean;
begin
call_read_b(b); -- Error
return b;
end procedure;
shared variable x : integer;
procedure update_x is
begin
x := 2;
end procedure;
function call_update_x return boolean is
begin
update_x;
return true;
end procedure;
begin
end architecture;
|
entity issue188 is
end entity;
architecture test of issue188 is
type ft is file of boolean;
function file_func return boolean is
file f : ft; -- Error
variable b : boolean;
begin
read(f, b);
return b;
end function;
impure function file_func_impure return boolean is
file f : ft; -- OK
variable b : boolean;
begin
read(f, b);
return b;
end function;
file f : ft;
function file_func2 return boolean is
variable b : boolean;
begin
read(f, b); -- Error
return b;
end function;
procedure read_b(b : out boolean) is
begin
read(f, b);
end procedure;
procedure call_read_b(b : out boolean) is
begin
read_b(b);
end procedure;
function call_call_read_b return boolean is
variable b : boolean;
begin
call_read_b(b); -- Error
return b;
end procedure;
shared variable x : integer;
procedure update_x is
begin
x := 2;
end procedure;
function call_update_x return boolean is
begin
update_x;
return true;
end procedure;
begin
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1885.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01885ent IS
END c07s01b00x00p08n01i01885ent;
ARCHITECTURE c07s01b00x00p08n01i01885arch OF c07s01b00x00p08n01i01885ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
BEGIN
TESTING : PROCESS
BEGIN
obus <= (0 => TESTING, others => 5) after 5 ns; -- process label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01885 - Process labels are not permitted as primaries in a element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01885arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1885.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01885ent IS
END c07s01b00x00p08n01i01885ent;
ARCHITECTURE c07s01b00x00p08n01i01885arch OF c07s01b00x00p08n01i01885ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
BEGIN
TESTING : PROCESS
BEGIN
obus <= (0 => TESTING, others => 5) after 5 ns; -- process label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01885 - Process labels are not permitted as primaries in a element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01885arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1885.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01885ent IS
END c07s01b00x00p08n01i01885ent;
ARCHITECTURE c07s01b00x00p08n01i01885arch OF c07s01b00x00p08n01i01885ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
BEGIN
TESTING : PROCESS
BEGIN
obus <= (0 => TESTING, others => 5) after 5 ns; -- process label illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01885 - Process labels are not permitted as primaries in a element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01885arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1837.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01837ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of small_int;
END c07s01b00x00p08n01i01837ent;
ARCHITECTURE c07s01b00x00p08n01i01837arch OF c07s01b00x00p08n01i01837ent IS
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_bus(0) <= small_int(c07s01b00x00p08n01i01837ent) after 5 ns; -- entity name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01837 - Entity name are not permitted as primaries in a type conversion expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01837arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1837.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01837ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of small_int;
END c07s01b00x00p08n01i01837ent;
ARCHITECTURE c07s01b00x00p08n01i01837arch OF c07s01b00x00p08n01i01837ent IS
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_bus(0) <= small_int(c07s01b00x00p08n01i01837ent) after 5 ns; -- entity name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01837 - Entity name are not permitted as primaries in a type conversion expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01837arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1837.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01837ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of small_int;
END c07s01b00x00p08n01i01837ent;
ARCHITECTURE c07s01b00x00p08n01i01837arch OF c07s01b00x00p08n01i01837ent IS
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_bus(0) <= small_int(c07s01b00x00p08n01i01837ent) after 5 ns; -- entity name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01837 - Entity name are not permitted as primaries in a type conversion expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01837arch;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:37 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_lms_pcore_0_0_stub.vhdl
-- Design : ip_design_lms_pcore_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
IPCORE_CLK : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_RVALID : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "IPCORE_CLK,IPCORE_RESETN,AXI4_Lite_ACLK,AXI4_Lite_ARESETN,AXI4_Lite_AWADDR[15:0],AXI4_Lite_AWVALID,AXI4_Lite_WDATA[31:0],AXI4_Lite_WSTRB[3:0],AXI4_Lite_WVALID,AXI4_Lite_BREADY,AXI4_Lite_ARADDR[15:0],AXI4_Lite_ARVALID,AXI4_Lite_RREADY,AXI4_Lite_AWREADY,AXI4_Lite_WREADY,AXI4_Lite_BRESP[1:0],AXI4_Lite_BVALID,AXI4_Lite_ARREADY,AXI4_Lite_RDATA[31:0],AXI4_Lite_RRESP[1:0],AXI4_Lite_RVALID";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "lms_pcore,Vivado 2017.3";
begin
end;
|
------------------------------------------------------
-- i2c_core.vhd - I2C core V2 logic
------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.4 alpha
-- History :
-- 20-mar-2002 CG 0.1 initial alpha release
-- 22-mar-2002 CG 0.2 complete rewrite
-- 27-mar-2002 CG 0.3 minor corrections
-- 02-apr-2002 CG 0.4 sync. of outputs
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_core is
port(
-- I2C signals
sda_in : in std_logic;
scl_in : in std_logic;
sda_out : out std_logic;
scl_out : out std_logic;
-- interface signals
clk : in std_logic;
rst : in std_logic;
sclk : in std_logic;
ack_in : in std_logic;
ack_out : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
cmd_start : in std_logic;
cmd_stop : in std_logic;
cmd_read : in std_logic;
cmd_write : in std_logic;
cmd_done_ack : in std_logic;
cmd_done : out std_logic;
busy : out std_logic
-- debug signals
-- state : out std_logic_vector(5 downto 0)
);
end i2c_core;
architecture behavorial of i2c_core is
type state_type is (
s_Reset, s_Idle, s_Done, s_DoneAck,
s_Start_A, s_Start_B, s_Start_C, s_Start_D,
s_Stop_A, s_Stop_B, s_Stop_C,
s_Rd_A, s_Rd_B, s_Rd_C, s_Rd_D, s_Rd_E, s_Rd_F,
s_RdAck_A, s_RdAck_B, s_RdAck_C, s_RdAck_D, s_RdAck_E,
s_Wr_A, s_Wr_B, s_Wr_C, s_Wr_D, s_Wr_E,
s_WrAck_A, s_WrAck_B, s_WrAck_C, s_WrAck_D
);
-- data output register
signal i_dout_ld : std_logic;
signal i_dout : std_logic_vector(7 downto 0);
-- ack output register
signal i_ack_out_ld : std_logic;
signal i_ack_out : std_logic;
-- data input bit
signal i_data_in : std_logic;
-- bit counter
signal i_ctr : unsigned(2 downto 0);
signal i_ctr_incr : std_logic;
signal i_ctr_clr : std_logic;
signal p_state : state_type;
signal n_state : state_type;
signal i_scl_out : std_logic;
signal i_sda_out : std_logic;
signal i_sclk_en : std_logic;
signal i_cmd_done : std_logic;
signal i_cmd_go : std_logic;
signal i_busy : std_logic;
begin
-- syncronize output signals
output_sync : process(clk, rst)
begin
if (rst = '1') then
scl_out <= '1';
sda_out <= '1';
data_out <= (others => '0');
ack_out <= '0';
busy <= '0';
cmd_done <= '0';
elsif (rising_edge(clk)) then
scl_out <= i_scl_out;
sda_out <= i_sda_out;
data_out <= i_dout;
ack_out <= i_ack_out;
busy <= i_busy;
cmd_done <= i_cmd_done;
end if;
end process output_sync;
-- select current bit
data_input_selector : process(i_ctr, data_in)
begin
case i_ctr is
when "000" => i_data_in <= data_in(7);
when "001" => i_data_in <= data_in(6);
when "010" => i_data_in <= data_in(5);
when "011" => i_data_in <= data_in(4);
when "100" => i_data_in <= data_in(3);
when "101" => i_data_in <= data_in(2);
when "110" => i_data_in <= data_in(1);
when "111" => i_data_in <= data_in(0);
when others => null;
end case;
end process data_input_selector;
-- indicate start of command
i_cmd_go <= (cmd_read OR cmd_write) AND NOT i_busy;
-- i2c bit counter
counter : process(clk, rst)
begin
if (rst = '1') then
i_ctr <= (others => '0');
elsif (rising_edge(clk)) then
if (i_ctr_clr = '1') then
i_ctr <= (others => '0');
elsif (i_ctr_incr = '1') then
i_ctr <= i_ctr + 1;
end if;
end if;
end process counter;
-- data output register
dout_reg : process(clk, rst)
begin
if (rst = '1') then
i_dout <= (others => '0');
elsif (rising_edge(clk)) then
if (i_dout_ld = '1') then
case i_ctr is
when "000" => i_dout(7) <= sda_in;
when "001" => i_dout(6) <= sda_in;
when "010" => i_dout(5) <= sda_in;
when "011" => i_dout(4) <= sda_in;
when "100" => i_dout(3) <= sda_in;
when "101" => i_dout(2) <= sda_in;
when "110" => i_dout(1) <= sda_in;
when "111" => i_dout(0) <= sda_in;
when others => null;
end case;
end if;
end if;
end process dout_reg;
-- ack bit output register
ack_out_reg : process(clk, rst)
begin
if (rst = '1') then
i_ack_out <= '0';
elsif (rising_edge(clk)) then
if (i_ack_out_ld = '1') then
i_ack_out <= sda_in;
end if;
end if;
end process ack_out_reg;
-- i2c send / receive byte
i2c_sync : process(rst, clk)
begin
if (rst = '1') then
p_state <= s_Reset;
elsif (rising_edge(clk)) then
if ((sclk = '1' and i_sclk_en = '1') or i_sclk_en = '0') then
p_state <= n_state;
end if;
end if;
end process i2c_sync;
i2c_comb : process(p_state, sda_in, scl_in, i_cmd_go, i_ctr, ack_in, i_data_in, cmd_start, cmd_stop, cmd_write, cmd_read, cmd_done_ack)
begin
n_state <= p_state;
--n_state <= p_state;
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
--i_dout_ld <= '0';
--i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
--state <= "111111";
case p_state is
when s_Reset =>
--state <= "000000";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Idle;
when s_Idle =>
--state <= "000001";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '1';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (i_cmd_go = '1') then
if (cmd_start = '1') then
-- do a START
n_state <= s_Start_A;
elsif (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
end if;
when s_Start_A =>
--state <= "001000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= scl_in;
n_state <= s_Start_B;
when s_Start_B =>
--state <= "001001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Start_C;
when s_Start_C =>
--state <= "001010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Start_D;
when s_Start_D =>
--state <= "001011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
if (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
when s_Rd_A =>
--state <= "010000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_B;
when s_Rd_B =>
--state <= "010001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_C;
when s_Rd_C =>
--state <= "010010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '1';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_D;
when s_Rd_D =>
--state <= "010011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_E;
when s_Rd_E =>
--state <= "010100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKOUT
n_state <= s_WrAck_A;
else
-- increment bit counter
n_state <= s_Rd_F;
end if;
when s_Rd_F =>
--state <= "010101";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_A;
when s_WrAck_A =>
--state <= "011000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
n_state <= s_WrAck_B;
when s_WrAck_B =>
--state <= "011001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_C;
when s_WrAck_C =>
--state <= "011010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_D;
when s_WrAck_D =>
--state <= "011011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
-- do a STOP ?
if (cmd_stop = '1') then
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Wr_A =>
--state <= "100000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_B;
when s_Wr_B =>
--state <= "100001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_C;
when s_Wr_C =>
--state <= "100010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_D;
when s_Wr_D =>
--state <= "100011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKIN
n_state <= s_RdAck_A;
else
-- increment bit counter
n_state <= s_Wr_E;
end if;
when s_Wr_E =>
--state <= "100100";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_A;
when s_RdAck_A =>
--state <= "101000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_RdAck_B;
when s_RdAck_B =>
--state <= "101001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_C;
when s_RdAck_C =>
--state <= "101010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '1';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_D;
when s_RdAck_D =>
--state <= "101011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_E;
when s_RdAck_E =>
--state <= "101100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (cmd_stop = '1') then
-- do a STOP
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Stop_A =>
--state <= "111000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
n_state <= s_Stop_B;
when s_Stop_B =>
--state <= "111001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Stop_C;
when s_Stop_C =>
--state <= "111010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Done;
when s_Done =>
--state <= "000010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
n_state <= s_DoneAck;
when s_DoneAck =>
--state <= "000011";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (cmd_done_ack = '1') then
n_state <= s_Idle;
end if;
end case;
end process i2c_comb;
end behavorial;
|
------------------------------------------------------
-- i2c_core.vhd - I2C core V2 logic
------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.4 alpha
-- History :
-- 20-mar-2002 CG 0.1 initial alpha release
-- 22-mar-2002 CG 0.2 complete rewrite
-- 27-mar-2002 CG 0.3 minor corrections
-- 02-apr-2002 CG 0.4 sync. of outputs
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_core is
port(
-- I2C signals
sda_in : in std_logic;
scl_in : in std_logic;
sda_out : out std_logic;
scl_out : out std_logic;
-- interface signals
clk : in std_logic;
rst : in std_logic;
sclk : in std_logic;
ack_in : in std_logic;
ack_out : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
cmd_start : in std_logic;
cmd_stop : in std_logic;
cmd_read : in std_logic;
cmd_write : in std_logic;
cmd_done_ack : in std_logic;
cmd_done : out std_logic;
busy : out std_logic
-- debug signals
-- state : out std_logic_vector(5 downto 0)
);
end i2c_core;
architecture behavorial of i2c_core is
type state_type is (
s_Reset, s_Idle, s_Done, s_DoneAck,
s_Start_A, s_Start_B, s_Start_C, s_Start_D,
s_Stop_A, s_Stop_B, s_Stop_C,
s_Rd_A, s_Rd_B, s_Rd_C, s_Rd_D, s_Rd_E, s_Rd_F,
s_RdAck_A, s_RdAck_B, s_RdAck_C, s_RdAck_D, s_RdAck_E,
s_Wr_A, s_Wr_B, s_Wr_C, s_Wr_D, s_Wr_E,
s_WrAck_A, s_WrAck_B, s_WrAck_C, s_WrAck_D
);
-- data output register
signal i_dout_ld : std_logic;
signal i_dout : std_logic_vector(7 downto 0);
-- ack output register
signal i_ack_out_ld : std_logic;
signal i_ack_out : std_logic;
-- data input bit
signal i_data_in : std_logic;
-- bit counter
signal i_ctr : unsigned(2 downto 0);
signal i_ctr_incr : std_logic;
signal i_ctr_clr : std_logic;
signal p_state : state_type;
signal n_state : state_type;
signal i_scl_out : std_logic;
signal i_sda_out : std_logic;
signal i_sclk_en : std_logic;
signal i_cmd_done : std_logic;
signal i_cmd_go : std_logic;
signal i_busy : std_logic;
begin
-- syncronize output signals
output_sync : process(clk, rst)
begin
if (rst = '1') then
scl_out <= '1';
sda_out <= '1';
data_out <= (others => '0');
ack_out <= '0';
busy <= '0';
cmd_done <= '0';
elsif (rising_edge(clk)) then
scl_out <= i_scl_out;
sda_out <= i_sda_out;
data_out <= i_dout;
ack_out <= i_ack_out;
busy <= i_busy;
cmd_done <= i_cmd_done;
end if;
end process output_sync;
-- select current bit
data_input_selector : process(i_ctr, data_in)
begin
case i_ctr is
when "000" => i_data_in <= data_in(7);
when "001" => i_data_in <= data_in(6);
when "010" => i_data_in <= data_in(5);
when "011" => i_data_in <= data_in(4);
when "100" => i_data_in <= data_in(3);
when "101" => i_data_in <= data_in(2);
when "110" => i_data_in <= data_in(1);
when "111" => i_data_in <= data_in(0);
when others => null;
end case;
end process data_input_selector;
-- indicate start of command
i_cmd_go <= (cmd_read OR cmd_write) AND NOT i_busy;
-- i2c bit counter
counter : process(clk, rst)
begin
if (rst = '1') then
i_ctr <= (others => '0');
elsif (rising_edge(clk)) then
if (i_ctr_clr = '1') then
i_ctr <= (others => '0');
elsif (i_ctr_incr = '1') then
i_ctr <= i_ctr + 1;
end if;
end if;
end process counter;
-- data output register
dout_reg : process(clk, rst)
begin
if (rst = '1') then
i_dout <= (others => '0');
elsif (rising_edge(clk)) then
if (i_dout_ld = '1') then
case i_ctr is
when "000" => i_dout(7) <= sda_in;
when "001" => i_dout(6) <= sda_in;
when "010" => i_dout(5) <= sda_in;
when "011" => i_dout(4) <= sda_in;
when "100" => i_dout(3) <= sda_in;
when "101" => i_dout(2) <= sda_in;
when "110" => i_dout(1) <= sda_in;
when "111" => i_dout(0) <= sda_in;
when others => null;
end case;
end if;
end if;
end process dout_reg;
-- ack bit output register
ack_out_reg : process(clk, rst)
begin
if (rst = '1') then
i_ack_out <= '0';
elsif (rising_edge(clk)) then
if (i_ack_out_ld = '1') then
i_ack_out <= sda_in;
end if;
end if;
end process ack_out_reg;
-- i2c send / receive byte
i2c_sync : process(rst, clk)
begin
if (rst = '1') then
p_state <= s_Reset;
elsif (rising_edge(clk)) then
if ((sclk = '1' and i_sclk_en = '1') or i_sclk_en = '0') then
p_state <= n_state;
end if;
end if;
end process i2c_sync;
i2c_comb : process(p_state, sda_in, scl_in, i_cmd_go, i_ctr, ack_in, i_data_in, cmd_start, cmd_stop, cmd_write, cmd_read, cmd_done_ack)
begin
n_state <= p_state;
--n_state <= p_state;
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
--i_dout_ld <= '0';
--i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
--state <= "111111";
case p_state is
when s_Reset =>
--state <= "000000";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Idle;
when s_Idle =>
--state <= "000001";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '1';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (i_cmd_go = '1') then
if (cmd_start = '1') then
-- do a START
n_state <= s_Start_A;
elsif (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
end if;
when s_Start_A =>
--state <= "001000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= scl_in;
n_state <= s_Start_B;
when s_Start_B =>
--state <= "001001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Start_C;
when s_Start_C =>
--state <= "001010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Start_D;
when s_Start_D =>
--state <= "001011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
if (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
when s_Rd_A =>
--state <= "010000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_B;
when s_Rd_B =>
--state <= "010001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_C;
when s_Rd_C =>
--state <= "010010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '1';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_D;
when s_Rd_D =>
--state <= "010011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_E;
when s_Rd_E =>
--state <= "010100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKOUT
n_state <= s_WrAck_A;
else
-- increment bit counter
n_state <= s_Rd_F;
end if;
when s_Rd_F =>
--state <= "010101";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_A;
when s_WrAck_A =>
--state <= "011000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
n_state <= s_WrAck_B;
when s_WrAck_B =>
--state <= "011001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_C;
when s_WrAck_C =>
--state <= "011010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_D;
when s_WrAck_D =>
--state <= "011011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
-- do a STOP ?
if (cmd_stop = '1') then
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Wr_A =>
--state <= "100000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_B;
when s_Wr_B =>
--state <= "100001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_C;
when s_Wr_C =>
--state <= "100010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_D;
when s_Wr_D =>
--state <= "100011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKIN
n_state <= s_RdAck_A;
else
-- increment bit counter
n_state <= s_Wr_E;
end if;
when s_Wr_E =>
--state <= "100100";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_A;
when s_RdAck_A =>
--state <= "101000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_RdAck_B;
when s_RdAck_B =>
--state <= "101001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_C;
when s_RdAck_C =>
--state <= "101010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '1';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_D;
when s_RdAck_D =>
--state <= "101011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_E;
when s_RdAck_E =>
--state <= "101100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (cmd_stop = '1') then
-- do a STOP
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Stop_A =>
--state <= "111000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
n_state <= s_Stop_B;
when s_Stop_B =>
--state <= "111001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Stop_C;
when s_Stop_C =>
--state <= "111010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Done;
when s_Done =>
--state <= "000010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
n_state <= s_DoneAck;
when s_DoneAck =>
--state <= "000011";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (cmd_done_ack = '1') then
n_state <= s_Idle;
end if;
end case;
end process i2c_comb;
end behavorial;
|
------------------------------------------------------
-- i2c_core.vhd - I2C core V2 logic
------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.4 alpha
-- History :
-- 20-mar-2002 CG 0.1 initial alpha release
-- 22-mar-2002 CG 0.2 complete rewrite
-- 27-mar-2002 CG 0.3 minor corrections
-- 02-apr-2002 CG 0.4 sync. of outputs
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_core is
port(
-- I2C signals
sda_in : in std_logic;
scl_in : in std_logic;
sda_out : out std_logic;
scl_out : out std_logic;
-- interface signals
clk : in std_logic;
rst : in std_logic;
sclk : in std_logic;
ack_in : in std_logic;
ack_out : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
cmd_start : in std_logic;
cmd_stop : in std_logic;
cmd_read : in std_logic;
cmd_write : in std_logic;
cmd_done_ack : in std_logic;
cmd_done : out std_logic;
busy : out std_logic
-- debug signals
-- state : out std_logic_vector(5 downto 0)
);
end i2c_core;
architecture behavorial of i2c_core is
type state_type is (
s_Reset, s_Idle, s_Done, s_DoneAck,
s_Start_A, s_Start_B, s_Start_C, s_Start_D,
s_Stop_A, s_Stop_B, s_Stop_C,
s_Rd_A, s_Rd_B, s_Rd_C, s_Rd_D, s_Rd_E, s_Rd_F,
s_RdAck_A, s_RdAck_B, s_RdAck_C, s_RdAck_D, s_RdAck_E,
s_Wr_A, s_Wr_B, s_Wr_C, s_Wr_D, s_Wr_E,
s_WrAck_A, s_WrAck_B, s_WrAck_C, s_WrAck_D
);
-- data output register
signal i_dout_ld : std_logic;
signal i_dout : std_logic_vector(7 downto 0);
-- ack output register
signal i_ack_out_ld : std_logic;
signal i_ack_out : std_logic;
-- data input bit
signal i_data_in : std_logic;
-- bit counter
signal i_ctr : unsigned(2 downto 0);
signal i_ctr_incr : std_logic;
signal i_ctr_clr : std_logic;
signal p_state : state_type;
signal n_state : state_type;
signal i_scl_out : std_logic;
signal i_sda_out : std_logic;
signal i_sclk_en : std_logic;
signal i_cmd_done : std_logic;
signal i_cmd_go : std_logic;
signal i_busy : std_logic;
begin
-- syncronize output signals
output_sync : process(clk, rst)
begin
if (rst = '1') then
scl_out <= '1';
sda_out <= '1';
data_out <= (others => '0');
ack_out <= '0';
busy <= '0';
cmd_done <= '0';
elsif (rising_edge(clk)) then
scl_out <= i_scl_out;
sda_out <= i_sda_out;
data_out <= i_dout;
ack_out <= i_ack_out;
busy <= i_busy;
cmd_done <= i_cmd_done;
end if;
end process output_sync;
-- select current bit
data_input_selector : process(i_ctr, data_in)
begin
case i_ctr is
when "000" => i_data_in <= data_in(7);
when "001" => i_data_in <= data_in(6);
when "010" => i_data_in <= data_in(5);
when "011" => i_data_in <= data_in(4);
when "100" => i_data_in <= data_in(3);
when "101" => i_data_in <= data_in(2);
when "110" => i_data_in <= data_in(1);
when "111" => i_data_in <= data_in(0);
when others => null;
end case;
end process data_input_selector;
-- indicate start of command
i_cmd_go <= (cmd_read OR cmd_write) AND NOT i_busy;
-- i2c bit counter
counter : process(clk, rst)
begin
if (rst = '1') then
i_ctr <= (others => '0');
elsif (rising_edge(clk)) then
if (i_ctr_clr = '1') then
i_ctr <= (others => '0');
elsif (i_ctr_incr = '1') then
i_ctr <= i_ctr + 1;
end if;
end if;
end process counter;
-- data output register
dout_reg : process(clk, rst)
begin
if (rst = '1') then
i_dout <= (others => '0');
elsif (rising_edge(clk)) then
if (i_dout_ld = '1') then
case i_ctr is
when "000" => i_dout(7) <= sda_in;
when "001" => i_dout(6) <= sda_in;
when "010" => i_dout(5) <= sda_in;
when "011" => i_dout(4) <= sda_in;
when "100" => i_dout(3) <= sda_in;
when "101" => i_dout(2) <= sda_in;
when "110" => i_dout(1) <= sda_in;
when "111" => i_dout(0) <= sda_in;
when others => null;
end case;
end if;
end if;
end process dout_reg;
-- ack bit output register
ack_out_reg : process(clk, rst)
begin
if (rst = '1') then
i_ack_out <= '0';
elsif (rising_edge(clk)) then
if (i_ack_out_ld = '1') then
i_ack_out <= sda_in;
end if;
end if;
end process ack_out_reg;
-- i2c send / receive byte
i2c_sync : process(rst, clk)
begin
if (rst = '1') then
p_state <= s_Reset;
elsif (rising_edge(clk)) then
if ((sclk = '1' and i_sclk_en = '1') or i_sclk_en = '0') then
p_state <= n_state;
end if;
end if;
end process i2c_sync;
i2c_comb : process(p_state, sda_in, scl_in, i_cmd_go, i_ctr, ack_in, i_data_in, cmd_start, cmd_stop, cmd_write, cmd_read, cmd_done_ack)
begin
n_state <= p_state;
--n_state <= p_state;
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
--i_dout_ld <= '0';
--i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
--state <= "111111";
case p_state is
when s_Reset =>
--state <= "000000";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Idle;
when s_Idle =>
--state <= "000001";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '1';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (i_cmd_go = '1') then
if (cmd_start = '1') then
-- do a START
n_state <= s_Start_A;
elsif (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
end if;
when s_Start_A =>
--state <= "001000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= scl_in;
n_state <= s_Start_B;
when s_Start_B =>
--state <= "001001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Start_C;
when s_Start_C =>
--state <= "001010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Start_D;
when s_Start_D =>
--state <= "001011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
if (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
when s_Rd_A =>
--state <= "010000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_B;
when s_Rd_B =>
--state <= "010001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_C;
when s_Rd_C =>
--state <= "010010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '1';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_D;
when s_Rd_D =>
--state <= "010011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_E;
when s_Rd_E =>
--state <= "010100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKOUT
n_state <= s_WrAck_A;
else
-- increment bit counter
n_state <= s_Rd_F;
end if;
when s_Rd_F =>
--state <= "010101";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_A;
when s_WrAck_A =>
--state <= "011000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
n_state <= s_WrAck_B;
when s_WrAck_B =>
--state <= "011001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_C;
when s_WrAck_C =>
--state <= "011010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_D;
when s_WrAck_D =>
--state <= "011011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
-- do a STOP ?
if (cmd_stop = '1') then
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Wr_A =>
--state <= "100000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_B;
when s_Wr_B =>
--state <= "100001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_C;
when s_Wr_C =>
--state <= "100010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_D;
when s_Wr_D =>
--state <= "100011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKIN
n_state <= s_RdAck_A;
else
-- increment bit counter
n_state <= s_Wr_E;
end if;
when s_Wr_E =>
--state <= "100100";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_A;
when s_RdAck_A =>
--state <= "101000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_RdAck_B;
when s_RdAck_B =>
--state <= "101001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_C;
when s_RdAck_C =>
--state <= "101010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '1';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_D;
when s_RdAck_D =>
--state <= "101011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_E;
when s_RdAck_E =>
--state <= "101100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (cmd_stop = '1') then
-- do a STOP
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Stop_A =>
--state <= "111000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
n_state <= s_Stop_B;
when s_Stop_B =>
--state <= "111001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Stop_C;
when s_Stop_C =>
--state <= "111010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Done;
when s_Done =>
--state <= "000010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
n_state <= s_DoneAck;
when s_DoneAck =>
--state <= "000011";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (cmd_done_ack = '1') then
n_state <= s_Idle;
end if;
end case;
end process i2c_comb;
end behavorial;
|
------------------------------------------------------
-- i2c_core.vhd - I2C core V2 logic
------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.4 alpha
-- History :
-- 20-mar-2002 CG 0.1 initial alpha release
-- 22-mar-2002 CG 0.2 complete rewrite
-- 27-mar-2002 CG 0.3 minor corrections
-- 02-apr-2002 CG 0.4 sync. of outputs
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_core is
port(
-- I2C signals
sda_in : in std_logic;
scl_in : in std_logic;
sda_out : out std_logic;
scl_out : out std_logic;
-- interface signals
clk : in std_logic;
rst : in std_logic;
sclk : in std_logic;
ack_in : in std_logic;
ack_out : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
cmd_start : in std_logic;
cmd_stop : in std_logic;
cmd_read : in std_logic;
cmd_write : in std_logic;
cmd_done_ack : in std_logic;
cmd_done : out std_logic;
busy : out std_logic
-- debug signals
-- state : out std_logic_vector(5 downto 0)
);
end i2c_core;
architecture behavorial of i2c_core is
type state_type is (
s_Reset, s_Idle, s_Done, s_DoneAck,
s_Start_A, s_Start_B, s_Start_C, s_Start_D,
s_Stop_A, s_Stop_B, s_Stop_C,
s_Rd_A, s_Rd_B, s_Rd_C, s_Rd_D, s_Rd_E, s_Rd_F,
s_RdAck_A, s_RdAck_B, s_RdAck_C, s_RdAck_D, s_RdAck_E,
s_Wr_A, s_Wr_B, s_Wr_C, s_Wr_D, s_Wr_E,
s_WrAck_A, s_WrAck_B, s_WrAck_C, s_WrAck_D
);
-- data output register
signal i_dout_ld : std_logic;
signal i_dout : std_logic_vector(7 downto 0);
-- ack output register
signal i_ack_out_ld : std_logic;
signal i_ack_out : std_logic;
-- data input bit
signal i_data_in : std_logic;
-- bit counter
signal i_ctr : unsigned(2 downto 0);
signal i_ctr_incr : std_logic;
signal i_ctr_clr : std_logic;
signal p_state : state_type;
signal n_state : state_type;
signal i_scl_out : std_logic;
signal i_sda_out : std_logic;
signal i_sclk_en : std_logic;
signal i_cmd_done : std_logic;
signal i_cmd_go : std_logic;
signal i_busy : std_logic;
begin
-- syncronize output signals
output_sync : process(clk, rst)
begin
if (rst = '1') then
scl_out <= '1';
sda_out <= '1';
data_out <= (others => '0');
ack_out <= '0';
busy <= '0';
cmd_done <= '0';
elsif (rising_edge(clk)) then
scl_out <= i_scl_out;
sda_out <= i_sda_out;
data_out <= i_dout;
ack_out <= i_ack_out;
busy <= i_busy;
cmd_done <= i_cmd_done;
end if;
end process output_sync;
-- select current bit
data_input_selector : process(i_ctr, data_in)
begin
case i_ctr is
when "000" => i_data_in <= data_in(7);
when "001" => i_data_in <= data_in(6);
when "010" => i_data_in <= data_in(5);
when "011" => i_data_in <= data_in(4);
when "100" => i_data_in <= data_in(3);
when "101" => i_data_in <= data_in(2);
when "110" => i_data_in <= data_in(1);
when "111" => i_data_in <= data_in(0);
when others => null;
end case;
end process data_input_selector;
-- indicate start of command
i_cmd_go <= (cmd_read OR cmd_write) AND NOT i_busy;
-- i2c bit counter
counter : process(clk, rst)
begin
if (rst = '1') then
i_ctr <= (others => '0');
elsif (rising_edge(clk)) then
if (i_ctr_clr = '1') then
i_ctr <= (others => '0');
elsif (i_ctr_incr = '1') then
i_ctr <= i_ctr + 1;
end if;
end if;
end process counter;
-- data output register
dout_reg : process(clk, rst)
begin
if (rst = '1') then
i_dout <= (others => '0');
elsif (rising_edge(clk)) then
if (i_dout_ld = '1') then
case i_ctr is
when "000" => i_dout(7) <= sda_in;
when "001" => i_dout(6) <= sda_in;
when "010" => i_dout(5) <= sda_in;
when "011" => i_dout(4) <= sda_in;
when "100" => i_dout(3) <= sda_in;
when "101" => i_dout(2) <= sda_in;
when "110" => i_dout(1) <= sda_in;
when "111" => i_dout(0) <= sda_in;
when others => null;
end case;
end if;
end if;
end process dout_reg;
-- ack bit output register
ack_out_reg : process(clk, rst)
begin
if (rst = '1') then
i_ack_out <= '0';
elsif (rising_edge(clk)) then
if (i_ack_out_ld = '1') then
i_ack_out <= sda_in;
end if;
end if;
end process ack_out_reg;
-- i2c send / receive byte
i2c_sync : process(rst, clk)
begin
if (rst = '1') then
p_state <= s_Reset;
elsif (rising_edge(clk)) then
if ((sclk = '1' and i_sclk_en = '1') or i_sclk_en = '0') then
p_state <= n_state;
end if;
end if;
end process i2c_sync;
i2c_comb : process(p_state, sda_in, scl_in, i_cmd_go, i_ctr, ack_in, i_data_in, cmd_start, cmd_stop, cmd_write, cmd_read, cmd_done_ack)
begin
n_state <= p_state;
--n_state <= p_state;
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
--i_dout_ld <= '0';
--i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
--state <= "111111";
case p_state is
when s_Reset =>
--state <= "000000";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Idle;
when s_Idle =>
--state <= "000001";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '1';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (i_cmd_go = '1') then
if (cmd_start = '1') then
-- do a START
n_state <= s_Start_A;
elsif (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
end if;
when s_Start_A =>
--state <= "001000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= scl_in;
n_state <= s_Start_B;
when s_Start_B =>
--state <= "001001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Start_C;
when s_Start_C =>
--state <= "001010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Start_D;
when s_Start_D =>
--state <= "001011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
if (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
when s_Rd_A =>
--state <= "010000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_B;
when s_Rd_B =>
--state <= "010001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_C;
when s_Rd_C =>
--state <= "010010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '1';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_D;
when s_Rd_D =>
--state <= "010011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_E;
when s_Rd_E =>
--state <= "010100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKOUT
n_state <= s_WrAck_A;
else
-- increment bit counter
n_state <= s_Rd_F;
end if;
when s_Rd_F =>
--state <= "010101";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_A;
when s_WrAck_A =>
--state <= "011000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
n_state <= s_WrAck_B;
when s_WrAck_B =>
--state <= "011001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_C;
when s_WrAck_C =>
--state <= "011010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_D;
when s_WrAck_D =>
--state <= "011011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
-- do a STOP ?
if (cmd_stop = '1') then
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Wr_A =>
--state <= "100000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_B;
when s_Wr_B =>
--state <= "100001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_C;
when s_Wr_C =>
--state <= "100010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_D;
when s_Wr_D =>
--state <= "100011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKIN
n_state <= s_RdAck_A;
else
-- increment bit counter
n_state <= s_Wr_E;
end if;
when s_Wr_E =>
--state <= "100100";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_A;
when s_RdAck_A =>
--state <= "101000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_RdAck_B;
when s_RdAck_B =>
--state <= "101001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_C;
when s_RdAck_C =>
--state <= "101010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '1';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_D;
when s_RdAck_D =>
--state <= "101011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_E;
when s_RdAck_E =>
--state <= "101100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (cmd_stop = '1') then
-- do a STOP
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Stop_A =>
--state <= "111000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
n_state <= s_Stop_B;
when s_Stop_B =>
--state <= "111001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Stop_C;
when s_Stop_C =>
--state <= "111010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Done;
when s_Done =>
--state <= "000010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
n_state <= s_DoneAck;
when s_DoneAck =>
--state <= "000011";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (cmd_done_ack = '1') then
n_state <= s_Idle;
end if;
end case;
end process i2c_comb;
end behavorial;
|
------------------------------------------------------
-- i2c_core.vhd - I2C core V2 logic
------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.4 alpha
-- History :
-- 20-mar-2002 CG 0.1 initial alpha release
-- 22-mar-2002 CG 0.2 complete rewrite
-- 27-mar-2002 CG 0.3 minor corrections
-- 02-apr-2002 CG 0.4 sync. of outputs
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_core is
port(
-- I2C signals
sda_in : in std_logic;
scl_in : in std_logic;
sda_out : out std_logic;
scl_out : out std_logic;
-- interface signals
clk : in std_logic;
rst : in std_logic;
sclk : in std_logic;
ack_in : in std_logic;
ack_out : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
cmd_start : in std_logic;
cmd_stop : in std_logic;
cmd_read : in std_logic;
cmd_write : in std_logic;
cmd_done_ack : in std_logic;
cmd_done : out std_logic;
busy : out std_logic
-- debug signals
-- state : out std_logic_vector(5 downto 0)
);
end i2c_core;
architecture behavorial of i2c_core is
type state_type is (
s_Reset, s_Idle, s_Done, s_DoneAck,
s_Start_A, s_Start_B, s_Start_C, s_Start_D,
s_Stop_A, s_Stop_B, s_Stop_C,
s_Rd_A, s_Rd_B, s_Rd_C, s_Rd_D, s_Rd_E, s_Rd_F,
s_RdAck_A, s_RdAck_B, s_RdAck_C, s_RdAck_D, s_RdAck_E,
s_Wr_A, s_Wr_B, s_Wr_C, s_Wr_D, s_Wr_E,
s_WrAck_A, s_WrAck_B, s_WrAck_C, s_WrAck_D
);
-- data output register
signal i_dout_ld : std_logic;
signal i_dout : std_logic_vector(7 downto 0);
-- ack output register
signal i_ack_out_ld : std_logic;
signal i_ack_out : std_logic;
-- data input bit
signal i_data_in : std_logic;
-- bit counter
signal i_ctr : unsigned(2 downto 0);
signal i_ctr_incr : std_logic;
signal i_ctr_clr : std_logic;
signal p_state : state_type;
signal n_state : state_type;
signal i_scl_out : std_logic;
signal i_sda_out : std_logic;
signal i_sclk_en : std_logic;
signal i_cmd_done : std_logic;
signal i_cmd_go : std_logic;
signal i_busy : std_logic;
begin
-- syncronize output signals
output_sync : process(clk, rst)
begin
if (rst = '1') then
scl_out <= '1';
sda_out <= '1';
data_out <= (others => '0');
ack_out <= '0';
busy <= '0';
cmd_done <= '0';
elsif (rising_edge(clk)) then
scl_out <= i_scl_out;
sda_out <= i_sda_out;
data_out <= i_dout;
ack_out <= i_ack_out;
busy <= i_busy;
cmd_done <= i_cmd_done;
end if;
end process output_sync;
-- select current bit
data_input_selector : process(i_ctr, data_in)
begin
case i_ctr is
when "000" => i_data_in <= data_in(7);
when "001" => i_data_in <= data_in(6);
when "010" => i_data_in <= data_in(5);
when "011" => i_data_in <= data_in(4);
when "100" => i_data_in <= data_in(3);
when "101" => i_data_in <= data_in(2);
when "110" => i_data_in <= data_in(1);
when "111" => i_data_in <= data_in(0);
when others => null;
end case;
end process data_input_selector;
-- indicate start of command
i_cmd_go <= (cmd_read OR cmd_write) AND NOT i_busy;
-- i2c bit counter
counter : process(clk, rst)
begin
if (rst = '1') then
i_ctr <= (others => '0');
elsif (rising_edge(clk)) then
if (i_ctr_clr = '1') then
i_ctr <= (others => '0');
elsif (i_ctr_incr = '1') then
i_ctr <= i_ctr + 1;
end if;
end if;
end process counter;
-- data output register
dout_reg : process(clk, rst)
begin
if (rst = '1') then
i_dout <= (others => '0');
elsif (rising_edge(clk)) then
if (i_dout_ld = '1') then
case i_ctr is
when "000" => i_dout(7) <= sda_in;
when "001" => i_dout(6) <= sda_in;
when "010" => i_dout(5) <= sda_in;
when "011" => i_dout(4) <= sda_in;
when "100" => i_dout(3) <= sda_in;
when "101" => i_dout(2) <= sda_in;
when "110" => i_dout(1) <= sda_in;
when "111" => i_dout(0) <= sda_in;
when others => null;
end case;
end if;
end if;
end process dout_reg;
-- ack bit output register
ack_out_reg : process(clk, rst)
begin
if (rst = '1') then
i_ack_out <= '0';
elsif (rising_edge(clk)) then
if (i_ack_out_ld = '1') then
i_ack_out <= sda_in;
end if;
end if;
end process ack_out_reg;
-- i2c send / receive byte
i2c_sync : process(rst, clk)
begin
if (rst = '1') then
p_state <= s_Reset;
elsif (rising_edge(clk)) then
if ((sclk = '1' and i_sclk_en = '1') or i_sclk_en = '0') then
p_state <= n_state;
end if;
end if;
end process i2c_sync;
i2c_comb : process(p_state, sda_in, scl_in, i_cmd_go, i_ctr, ack_in, i_data_in, cmd_start, cmd_stop, cmd_write, cmd_read, cmd_done_ack)
begin
n_state <= p_state;
--n_state <= p_state;
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
--i_dout_ld <= '0';
--i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
--state <= "111111";
case p_state is
when s_Reset =>
--state <= "000000";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Idle;
when s_Idle =>
--state <= "000001";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '1';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (i_cmd_go = '1') then
if (cmd_start = '1') then
-- do a START
n_state <= s_Start_A;
elsif (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
end if;
when s_Start_A =>
--state <= "001000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= scl_in;
n_state <= s_Start_B;
when s_Start_B =>
--state <= "001001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Start_C;
when s_Start_C =>
--state <= "001010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Start_D;
when s_Start_D =>
--state <= "001011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
if (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
when s_Rd_A =>
--state <= "010000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_B;
when s_Rd_B =>
--state <= "010001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_C;
when s_Rd_C =>
--state <= "010010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '1';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_D;
when s_Rd_D =>
--state <= "010011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_E;
when s_Rd_E =>
--state <= "010100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKOUT
n_state <= s_WrAck_A;
else
-- increment bit counter
n_state <= s_Rd_F;
end if;
when s_Rd_F =>
--state <= "010101";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_A;
when s_WrAck_A =>
--state <= "011000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
n_state <= s_WrAck_B;
when s_WrAck_B =>
--state <= "011001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_C;
when s_WrAck_C =>
--state <= "011010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_D;
when s_WrAck_D =>
--state <= "011011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
-- do a STOP ?
if (cmd_stop = '1') then
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Wr_A =>
--state <= "100000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_B;
when s_Wr_B =>
--state <= "100001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_C;
when s_Wr_C =>
--state <= "100010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_D;
when s_Wr_D =>
--state <= "100011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKIN
n_state <= s_RdAck_A;
else
-- increment bit counter
n_state <= s_Wr_E;
end if;
when s_Wr_E =>
--state <= "100100";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_A;
when s_RdAck_A =>
--state <= "101000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_RdAck_B;
when s_RdAck_B =>
--state <= "101001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_C;
when s_RdAck_C =>
--state <= "101010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '1';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_D;
when s_RdAck_D =>
--state <= "101011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_E;
when s_RdAck_E =>
--state <= "101100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (cmd_stop = '1') then
-- do a STOP
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Stop_A =>
--state <= "111000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
n_state <= s_Stop_B;
when s_Stop_B =>
--state <= "111001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Stop_C;
when s_Stop_C =>
--state <= "111010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Done;
when s_Done =>
--state <= "000010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
n_state <= s_DoneAck;
when s_DoneAck =>
--state <= "000011";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (cmd_done_ack = '1') then
n_state <= s_Idle;
end if;
end case;
end process i2c_comb;
end behavorial;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity RegisterFile is
Port ( rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
DtoWrite : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0));
end RegisterFile;
architecture syn of RegisterFile is
type ram_type is array (0 to 39) of std_logic_vector (31 downto 0);
signal RAM: ram_type:= ( others => "00000000000000000000000000000000");
begin
RAM(0)<="00000000000000000000000000000000" ;
process (rs1, rs2, rd, dtowrite, rst,RAM)
begin
if rst = '1' then
RAM <=( others => "00000000000000000000000000000000");
crs1 <= "00000000000000000000000000000000" ;
crs2 <="00000000000000000000000000000000" ;
else
crs1 <= RAM(conv_integer(rs1)) ;
crs2 <= RAM(conv_integer(rs2)) ;
if rd /= "00000" then
RAM(conv_integer(rd)) <= DtoWrite;
end if;
end if;
end process;
end syn;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/16/2016 11:02:41 AM
-- Design Name:
-- Module Name: projeto2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity projeto2 is
-- Port ( );
end projeto2;
architecture Behavioral of projeto2 is
begin
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: sparc_disas
-- File: sparc_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.testlib.print;
use std.textio.all;
package sparc_disas is
function tostf(v:std_logic_vector) return string;
procedure print_insn(ndx: integer; pc, op, res : std_logic_vector(31 downto 0);
valid, trap, wr : boolean;
rex: boolean := false);
procedure print_fpinsn(ndx: integer; pc, op : std_logic_vector(31 downto 0);
res : std_logic_vector(63 downto 0);
dpres, valid, trap, wr : boolean);
function ins2st(pc, op : std_logic_vector(31 downto 0); rex: boolean := false) return string;
end;
package body sparc_disas is
type base_type is (hex, dec);
subtype nibble is std_logic_vector(3 downto 0);
type pc_op_type is record
pc, op : std_logic_vector(31 downto 0);
end record;
function tostd(v:std_logic_vector) return string;
function tosth(v:std_logic_vector) return string;
function tostrd(n:integer) return string;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
type carr is array (0 to 9) of character;
constant darr : carr := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
function tostd(v:std_logic_vector) return string is
variable s : string(1 to 2);
variable val : integer;
begin
val := conv_integer(v); s(1) := darr(val / 10); s(2) := darr(val mod 10);
return(s);
end;
function tosth(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return(s);
end;
function tostf(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return("0x" & s);
end;
function tostrd(n:integer) return string is
variable len : integer := 0;
variable tmp : string(10 downto 1);
variable v : integer := n;
begin
for i in 0 to 9 loop
tmp(i+1) := darr(v mod 10);
if tmp(i+1) /= '0' then
len := i;
end if;
v := v/10;
end loop;
return(tmp(len+1 downto 1));
end;
function ireg2st(v : std_logic_vector) return string is
variable ctmp : character;
variable reg : std_logic_vector(4 downto 0);
begin
reg := v;
case reg(4 downto 3) is
when "00" => ctmp := 'g'; when "01" => ctmp := 'o';
when "10" => ctmp := 'l'; when "11" => ctmp := 'i';
when others => ctmp := 'X';
end case;
if v(4 downto 0) = "11110" then return("%fp");
elsif v(4 downto 0) = "01110" then return("%sp");
else return('%' & ctmp & tost('0' & reg(2 downto 0))); end if;
end;
function simm13dec(insn : pc_op_type; base : base_type; merge : boolean) return string is
variable simm : std_logic_vector(12 downto 0) := insn.op(12 downto 0);
variable rs1 : std_logic_vector(4 downto 0) := insn.op(18 downto 14);
variable i : std_ulogic := insn.op(13);
variable sig : character;
variable fill : std_logic_vector(31 downto 13) := (others => simm(12));
begin
if i = '0' then
return("");
else
if (simm(12) = '1') and (base = dec) then
sig := '-'; simm := (not simm) + 1;
else
sig := '+';
end if;
if base = dec then
if merge then
if rs1 = "00000" then
return(tost(simm));
else
return(sig & tost(simm));
end if;
else
if rs1 = "00000" then
return(tost(simm));
else
if sig = '-' then
return(", " & sig & tost(simm));
else
return(", " & tost(simm));
end if;
end if;
end if;
else
if rs1 = "00000" then
if simm(12) = '1' then return(tost(fill & simm));
else return(tost(simm)); end if;
else
if simm(12) = '1' then return(", " & tost(fill & simm));
else return(", " & tost(simm)); end if;
end if;
end if;
end if;
end;
function freg2(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs2) &
", %f" & tostd(rd));
end;
function creg3(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%c" & tostd(rs1) & ", %c" & tostd(rs2) & ", %c" & tostd(rd));
end;
function freg3(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2) & ", %f" & tostd(rd));
end;
function fregc(insn : pc_op_type) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2));
end;
function regimm(insn : pc_op_type; base : base_type; merge : boolean) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
i := insn.op(13);
if i = '0' then
if (rs1 = "00000") then
if (rs2 = "00000") then return("0");
else return(ireg2st(rs2)); end if;
else
if (rs2 = "00000") then return(ireg2st(rs1));
elsif merge then return(ireg2st(rs1) & " + " & ireg2st(rs2));
else return(ireg2st(rs1) & ", " & ireg2st(rs2)); end if;
end if;
else
if (rs1 = "00000") then return(simm13dec(insn, base, merge));
elsif insn.op(12 downto 0) = "0000000000000" then return(ireg2st(rs1));
else return(ireg2st(rs1) & simm13dec(insn, base, merge)); end if;
end if;
end;
function regres(insn : pc_op_type; base : base_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rd := insn.op(29 downto 25);
return(regimm(insn, base,false) & ", " & ireg2st(rd ));
end;
function branchop(insn : pc_op_type) return string is
variable slice : std_logic_vector(28 downto 25);
begin
slice := insn.op(28 downto 25);
case slice is
when "0000" => return("n");
when "0001" => return("e");
when "0010" => return("le");
when "0011" => return("l");
when "0100" => return("leu");
when "0101" => return("cs");
when "0110" => return("neg");
when "0111" => return("vs");
when "1000" => return("a");
when "1001" => return("ne");
when "1010" => return("g");
when "1011" => return("ge");
when "1100" => return("gu");
when "1101" => return("cc");
when "1110" => return("pos");
when "1111" => return("vc");
when others => return("XXX");
end case;
end;
function fbranchop(insn : pc_op_type) return string is
variable slice : std_logic_vector(28 downto 25);
begin
slice := insn.op(28 downto 25);
case slice is
when "0000" => return("n");
when "0001" => return("ne");
when "0010" => return("lg");
when "0011" => return("ul");
when "0100" => return("l");
when "0101" => return("ug");
when "0110" => return("g");
when "0111" => return("u");
when "1000" => return("a");
when "1001" => return("e");
when "1010" => return("ue");
when "1011" => return("ge");
when "1100" => return("uge");
when "1101" => return("le");
when "1110" => return("ule");
when "1111" => return("o");
when others => return("XXX");
end case;
end;
function ldparcp(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%c" & tost(rd));
end;
function ldparf(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%f" & tostd(rd));
end;
function ldpar(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & ireg2st(rd));
end;
function ldpara(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)) & ", " & ireg2st(rd));
end;
function ldpara_cas(insn : pc_op_type; rs1, rs2, rd : std_logic_vector; base : base_type) return string is
begin
return("[" & ireg2st(rs1) & "]" & " " & tost(insn.op(12 downto 5)) & ", " &
ireg2st(rs2) & ", " & ireg2st(rd));
end;
function stparc(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
if rd = "00000" then
return("[" & regimm(insn,dec,true) & "]");
else
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]");
end if;
end;
function stparcp(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("%c" & tost(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stparf(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("%f" & tostd(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpar(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpara(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)));
end;
function ins2st(pc, op : std_logic_vector(31 downto 0); rex: boolean := false) return string is
constant STMAX : natural := 9;
constant bl2 : string(1 to 2) := (others => ' ');
constant bb : string(1 to 4) := (others => ' ');
variable op1 : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opf : std_logic_vector(8 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable addr : std_logic_vector(31 downto 0);
variable annul : std_ulogic;
variable i : std_ulogic;
variable simm : std_logic_vector(12 downto 0);
variable insn : pc_op_type;
variable bbr : string(1 to 4);
begin
op1 := op(31 downto 30);
op2 := op(24 downto 22);
op3 := op(24 downto 19);
opf := op(13 downto 5);
cond := op(28 downto 25);
annul := op(29);
rs1 := op(18 downto 14);
rs2 := op(4 downto 0);
rd := op(29 downto 25);
i := op(13);
simm := op(12 downto 0);
insn.op := op;
insn.pc := pc;
if rex then bbr:=" R "; else bbr:=bb; end if;
case op1 is
when CALL =>
addr := pc + (op(29 downto 0) & "00");
return(tostf(pc) & bbr & "call" & bl2 & tost(addr));
when FMT2 =>
case op2 is
when SETHI =>
if rd = "00000" then
return(tostf(pc) & bbr & "nop");
else
return(tostf(pc) & bbr & "sethi" & bl2 & "%hi(" &
tost(op(21 downto 0) & "0000000000") & "), " & ireg2st(rd));
end if;
when BICC | FBFCC =>
addr(31 downto 24) := (others => '0');
addr(1 downto 0) := (others => '0');
addr(23 downto 2) := op(21 downto 0);
if addr(23) = '1' then
addr(31 downto 24) := (others => '1');
else
addr(31 downto 24) := (others => '0');
end if;
addr := addr + pc;
if op2 = BICC then
if op(29) = '1' then
return(tostf(pc) & bbr & 'b' & branchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(pc) & bbr & 'b' & branchop(insn) & bl2 &
tost(addr));
end if;
else
if op(29) = '1' then
return(tostf(pc) & bbr & "fb" & fbranchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(pc) & bbr & "fb" & fbranchop(insn) & bl2 &
tost(addr));
end if;
end if;
-- when CBCCC => cptrap := '1';
when others => return(tostf(pc) & bbr & "unimp");
end case;
when FMT3 =>
case op3 is
when IAND => return(tostf(pc) & bbr & "and" & bl2 & regres(insn,hex));
when IADD =>
if (i='0' and simm(12)='1') then
insn.op(13):='1';
return (tostf(pc) & bbr & "addrex" & bl2 & regres(insn,dec));
end if;
return(tostf(pc) & bbr & "add" & bl2 & regres(insn,dec));
when IOR =>
if ((i = '0') and (rs1 = "00000") and (rs2 = "00000")) then
return(tostf(pc) & bbr & "clr" & bl2 & ireg2st(rd));
elsif ((i = '1') and (simm = "0000000000000")) or (rs1 = "00000") then
return(tostf(pc) & bbr & "mov" & bl2 & regres(insn,hex));
else
return(tostf(pc) & bbr & "or " & bl2 & regres(insn,hex));
end if;
when IXOR => return(tostf(pc) & bbr & "xor" & bl2 & regres(insn,hex));
when ISUB => return(tostf(pc) & bbr & "sub" & bl2 & regres(insn,dec));
when ANDN => return(tostf(pc) & bbr & "andn" & bl2 & regres(insn,hex));
when ORN => return(tostf(pc) & bbr & "orn" & bl2 & regres(insn,hex));
when IXNOR =>
if ((i = '0') and ((rs1 = rd) or (rs2 = "00000"))) then
return(tostf(pc) & bbr & "not" & bl2 & ireg2st(rd));
else
return(tostf(pc) & bbr & "xnor" & bl2 & ireg2st(rd));
end if;
when ADDX => return(tostf(pc) & bbr & "addx" & bl2 & regres(insn,dec));
when SUBX => return(tostf(pc) & bbr & "subx" & bl2 & regres(insn,dec));
when ADDCC => return(tostf(pc) & bbr & "addcc" & bl2 & regres(insn,dec));
when ANDCC => return(tostf(pc) & bbr & "andcc" & bl2 & regres(insn,hex));
when ORCC => return(tostf(pc) & bbr & "orcc" & bl2 & regres(insn,hex));
when XORCC => return(tostf(pc) & bbr & "xorcc" & bl2 & regres(insn,hex));
when SUBCC => return(tostf(pc) & bbr & "subcc" & bl2 & regres(insn,dec));
when ANDNCC => return(tostf(pc) & bbr & "andncc" & bl2 & regres(insn,hex));
when ORNCC => return(tostf(pc) & bbr & "orncc" & bl2 & regres(insn,hex));
when XNORCC => return(tostf(pc) & bbr & "xnorcc" & bl2 & regres(insn,hex));
when ADDXCC => return(tostf(pc) & bbr & "addxcc" & bl2 & regres(insn,hex));
when UMAC => return(tostf(pc) & bbr & "umac" & bl2 & regres(insn,dec));
when SMAC => return(tostf(pc) & bbr & "smac" & bl2 & regres(insn,dec));
when UMUL => return(tostf(pc) & bbr & "umul" & bl2 & regres(insn,dec));
when SMUL => return(tostf(pc) & bbr & "smul" & bl2 & regres(insn,dec));
when UMULCC => return(tostf(pc) & bbr & "umulcc" & bl2 & regres(insn,dec));
when SMULCC => return(tostf(pc) & bbr & "smulcc" & bl2 & regres(insn,dec));
when SUBXCC => return(tostf(pc) & bbr & "subxcc" & bl2 & regres(insn,dec));
when UDIV => return(tostf(pc) & bbr & "udiv" & bl2 & regres(insn,dec));
when SDIV => return(tostf(pc) & bbr & "sdiv" & bl2 & regres(insn,dec));
when UDIVCC => return(tostf(pc) & bbr & "udivcc" & bl2 & regres(insn,dec));
when SDIVCC => return(tostf(pc) & bbr & "sdivcc" & bl2 & regres(insn,dec));
when TADDCC => return(tostf(pc) & bbr & "taddcc" & bl2 & regres(insn,dec));
when TSUBCC => return(tostf(pc) & bbr & "tsubcc" & bl2 & regres(insn,dec));
when TADDCCTV => return(tostf(pc) & bbr & "taddcctv" & bl2 & regres(insn,dec));
when TSUBCCTV => return(tostf(pc) & bbr & "tsubcctv" & bl2 & regres(insn,dec));
when MULSCC => return(tostf(pc) & bbr & "mulscc" & bl2 & regres(insn,dec));
when ISLL => return(tostf(pc) & bbr & "sll" & bl2 & regres(insn,dec));
when ISRL => return(tostf(pc) & bbr & "srl" & bl2 & regres(insn,dec));
when ISRA => return(tostf(pc) & bbr & "sra" & bl2 & regres(insn,dec));
when RDY =>
if rs1 /= "00000" then
return(tostf(pc) & bbr & "mov" & bl2 & "%asr" &
tostd(rs1) & ", " & ireg2st(rd));
else
return(tostf(pc) & bbr & "mov" & bl2 & "%y, " & ireg2st(rd));
end if;
when RDPSR => return(tostf(pc) & bbr & "mov" & bl2 & "%psr, " & ireg2st(rd));
when RDWIM => return(tostf(pc) & bbr & "mov" & bl2 & "%wim, " & ireg2st(rd));
when RDTBR => return(tostf(pc) & bbr & "mov" & bl2 & "%tbr, " & ireg2st(rd));
when WRY =>
if (rs1 = "00000") or (rs2 = "00000") then
if rd /= "00000" then
return(tostf(pc) & bbr & "mov" & bl2
& regimm(insn,hex,false) & ", %asr" & tostd(rd));
else
return(tostf(pc) & bbr & "mov" & bl2 & regimm(insn,hex,false) & ", %y");
end if;
else
if rd /= "00000" then
return(tostf(pc) & bbr & "wr " & bl2 & "%asr"
& regimm(insn,hex,false) & ", %asr" & tostd(rd));
else
return(tostf(pc) & bbr & "wr " & bl2 & regimm(insn,hex,false) & ", %y");
end if;
end if;
when WRPSR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bbr & "mov" & bl2 & regimm(insn,hex,false) & ", %psr");
else
return(tostf(pc) & bbr & "wr " & bl2 & regimm(insn,hex,false) & ", %psr");
end if;
when WRWIM =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bbr & "mov" & bl2 & regimm(insn,hex,false) & ", %wim");
else
return(tostf(pc) & bbr & "wr " & bl2 & regimm(insn,hex,false) & ", %wim");
end if;
when WRTBR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bbr & "mov" & bl2 & regimm(insn,hex,false) & ", %tbr");
else
return(tostf(pc) & bbr & "wr " & bl2 & regimm(insn,hex,false) & ", %tbr");
end if;
when JMPL =>
if (rd = "00000") then
if (i = '1') and (simm = "0000000001000") then
if (rs1 = "11111") then return(tostf(pc) & bbr & "ret");
elsif (rs1 = "01111") then return(tostf(pc) & bbr & "retl");
else return(tostf(pc) & bbr & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else return(tostf(pc) & bbr & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else return(tostf(pc) & bbr & "jmpl" & bl2 & regres(insn,dec));
end if;
when TICC =>
return(tostf(pc) & bbr & 't' & branchop(insn) & bl2 & regimm(insn,hex,false));
when FLUSH =>
return(tostf(pc) & bbr & "flush" & bl2 & regimm(insn,hex,false));
when RETT =>
return(tostf(pc) & bbr & "rett" & bl2 & regimm(insn,dec,true));
when RESTORE =>
if (rd = "00000") then
return(tostf(pc) & bbr & "restore");
else
return(tostf(pc) & bbr & "restore" & bl2 & regres(insn,hex));
end if;
when SAVE =>
if (i='0' and simm(12)='1') then
insn.op(13):='1';
return (tostf(pc) & bbr & "saverex" & bl2 & regres(insn,dec));
elsif (rd = "00000") then return(tostf(pc) & bbr & "save");
else return(tostf(pc) & bbr & "save" & bl2 & regres(insn,dec)); end if;
when FPOP1 =>
case opf is
when FITOS => return(tostf(pc) & bbr & "fitos" & bl2 & freg2(insn));
when FITOD => return(tostf(pc) & bbr & "fitod" & bl2 & freg2(insn));
when FSTOI => return(tostf(pc) & bbr & "fstoi" & bl2 & freg2(insn));
when FDTOI => return(tostf(pc) & bbr & "fdtoi" & bl2 & freg2(insn));
when FSTOD => return(tostf(pc) & bbr & "fstod" & bl2 & freg2(insn));
when FDTOS => return(tostf(pc) & bbr & "fdtos" & bl2 & freg2(insn));
when FMOVS => return(tostf(pc) & bbr & "fmovs" & bl2 & freg2(insn));
when FNEGS => return(tostf(pc) & bbr & "fnegs" & bl2 & freg2(insn));
when FABSS => return(tostf(pc) & bbr & "fabss" & bl2 & freg2(insn));
when FSQRTS => return(tostf(pc) & bbr & "fsqrts" & bl2 & freg2(insn));
when FSQRTD => return(tostf(pc) & bbr & "fsqrtd" & bl2 & freg2(insn));
when FADDS => return(tostf(pc) & bbr & "fadds" & bl2 & freg3(insn));
when FADDD => return(tostf(pc) & bbr & "faddd" & bl2 & freg3(insn));
when FSUBS => return(tostf(pc) & bbr & "fsubs" & bl2 & freg3(insn));
when FSUBD => return(tostf(pc) & bbr & "fsubd" & bl2 & freg3(insn));
when FMULS => return(tostf(pc) & bbr & "fmuls" & bl2 & freg3(insn));
when FMULD => return(tostf(pc) & bbr & "fmuld" & bl2 & freg3(insn));
when FSMULD => return(tostf(pc) & bbr & "fsmuld" & bl2 & freg3(insn));
when FDIVS => return(tostf(pc) & bbr & "fdivs" & bl2 & freg3(insn));
when FDIVD => return(tostf(pc) & bbr & "fdivd" & bl2 & freg3(insn));
when others => return(tostf(pc) & bbr & "unknown FOP1: " & tost(op));
end case;
when FPOP2 =>
case opf is
when FCMPS => return(tostf(pc) & bbr & "fcmps" & bl2 & fregc(insn));
when FCMPD => return(tostf(pc) & bbr & "fcmpd" & bl2 & fregc(insn));
when FCMPES => return(tostf(pc) & bbr & "fcmpes" & bl2 & fregc(insn));
when FCMPED => return(tostf(pc) & bbr & "fcmped" & bl2 & fregc(insn));
when others => return(tostf(pc) & bbr & "unknown FOP2: " & tost(insn.op));
end case;
when CPOP1 =>
return(tostf(pc) & bbr & "cpop1" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when CPOP2 =>
return(tostf(pc) & bbr & "cpop2" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when others => return(tostf(pc) & bbr & "unknown opcode: " & tost(insn.op));
end case;
when LDST =>
case op3 is
when STC =>
return(tostf(pc) & bbr & "st" & bl2 & stparcp(insn, rd, dec));
when STF =>
return(tostf(pc) & bbr & "st" & bl2 & stparf(insn, rd, dec));
when ST =>
if rd = "00000" then
return(tostf(pc) & bbr & "clr" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bbr & "st" & bl2 & stpar(insn, rd, dec));
end if;
when STB =>
if rd = "00000" then
return(tostf(pc) & bbr & "clrb" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bbr & "stb" & bl2 & stpar(insn, rd, dec));
end if;
when STH =>
if rd = "00000" then
return(tostf(pc) & bbr & "clrh" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bbr & "sth" & bl2 & stpar(insn, rd, dec));
end if;
when STDC =>
return(tostf(pc) & bbr & "std" & bl2 & stparcp(insn, rd, dec));
when STDF =>
return(tostf(pc) & bbr & "std" & bl2 & stparf(insn, rd, dec));
when STCSR =>
return(tostf(pc) & bbr & "st" & bl2 & "%csr, [" & regimm(insn,dec,true) & "]");
when STFSR =>
return(tostf(pc) & bbr & "st" & bl2 & "%fsr, [" & regimm(insn,dec,true) & "]");
when STDCQ =>
return(tostf(pc) & bbr & "std" & bl2 & "%cq, [" & regimm(insn,dec,true) & "]");
when STDFQ =>
return(tostf(pc) & bbr & "std" & bl2 & "%fq, [" & regimm(insn,dec,true) & "]");
when ISTD =>
return(tostf(pc) & bbr & "std" & bl2 & stpar(insn, rd, dec));
when STA =>
return(tostf(pc) & bbr & "sta" & bl2 & stpara(insn, rd, dec));
when STBA =>
return(tostf(pc) & bbr & "stba" & bl2 & stpara(insn, rd, dec));
when STHA =>
return(tostf(pc) & bbr & "stha" & bl2 & stpara(insn, rd, dec));
when STDA =>
return(tostf(pc) & bbr & "stda" & bl2 & stpara(insn, rd, dec));
when LDC =>
return(tostf(pc) & bbr & "ld" & bl2 & ldparcp(insn, rd, dec));
when LDF =>
return(tostf(pc) & bbr & "ld" & bl2 & ldparf(insn, rd, dec));
when LDCSR =>
return(tostf(pc) & bbr & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %csr");
when LDFSR =>
return(tostf(pc) & bbr & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %fsr");
when LD =>
return(tostf(pc) & bbr & "ld" & bl2 & ldpar(insn, rd, dec));
when LDUB =>
return(tostf(pc) & bbr & "ldub" & bl2 & ldpar(insn, rd, dec));
when LDUH =>
return(tostf(pc) & bbr & "lduh" & bl2 & ldpar(insn, rd, dec));
when LDDC =>
return(tostf(pc) & bbr & "ldd" & bl2 & ldparcp(insn, rd, dec));
when LDDF =>
return(tostf(pc) & bbr & "ldd" & bl2 & ldparf(insn, rd, dec));
when LDD =>
return(tostf(pc) & bbr & "ldd" & bl2 & ldpar(insn, rd, dec));
when LDSB =>
return(tostf(pc) & bbr & "ldsb" & bl2 & ldpar(insn, rd, dec));
when LDSH =>
return(tostf(pc) & bbr & "ldsh" & bl2 & ldpar(insn, rd, dec));
when LDSTUB =>
return(tostf(pc) & bbr & "ldstub" & bl2 & ldpar(insn, rd, dec));
when SWAP =>
return(tostf(pc) & bbr & "swap" & bl2 & ldpar(insn, rd, dec));
when LDA =>
return(tostf(pc) & bbr & "lda" & bl2 & ldpara(insn, rd, dec));
when LDUBA =>
return(tostf(pc) & bbr & "lduba" & bl2 & ldpara(insn, rd, dec));
when LDUHA =>
return(tostf(pc) & bbr & "lduha" & bl2 & ldpara(insn, rd, dec));
when LDDA =>
return(tostf(pc) & bbr & "ldda" & bl2 & ldpara(insn, rd, dec));
when LDSBA =>
return(tostf(pc) & bbr & "ldsba" & bl2 & ldpara(insn, rd, dec));
when LDSHA =>
return(tostf(pc) & bbr & "ldsha" & bl2 & ldpara(insn, rd, dec));
when LDSTUBA =>
return(tostf(pc) & bbr & "ldstuba" & bl2 & ldpara(insn, rd, dec));
when SWAPA =>
return(tostf(pc) & bbr & "swapa" & bl2 & ldpara(insn, rd, dec));
when CASA =>
return(tostf(pc) & bbr & "casa" & bl2 & ldpara_cas(insn, rs1, rs2, rd, dec));
when others => return(tostf(pc) & bbr & "unknown opcode: " & tost(op));
end case;
when others => return(tostf(pc) & bbr & "unknown opcode: " & tost(op));
end case;
end;
procedure print_insn(ndx: integer; pc, op, res : std_logic_vector(31 downto 0);
valid, trap, wr : boolean;
rex: boolean := false) is
begin
if valid then
if trap then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op, rex) & " (trapped)");
elsif wr then grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op, rex) & " [" & tost(res) & "]");
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op, rex)); end if;
end if;
end;
procedure print_fpinsn(ndx: integer; pc, op : std_logic_vector(31 downto 0);
res : std_logic_vector(63 downto 0);
dpres, valid, trap, wr : boolean) is
variable t : natural;
begin
if valid then
t := now / 1 ns;
if trap then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op) & " (trapped)");
elsif wr then
if dpres then grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res) & "]");
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res(63 downto 32)) & "]"); end if;
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op)); end if;
end if;
end;
end;
-- pragma translate_on
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity eth_rx_tb is
end eth_rx_tb;
architecture behav of eth_rx_tb is
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal rxd : std_logic_vector(1 downto 0) := "00";
signal crsdv : std_logic := '0';
signal q : std_logic_vector(7 downto 0);
signal q_valid : std_logic;
begin
dut : entity work.eth_rx port map(clk, rst, rxd, crsdv, q, q_valid);
rst <= '1', '0' after 100 ns;
clk <= not clk after 10 ns;
rx_test : process
variable tmp : integer;
variable tmp_v : std_logic_vector(7 downto 0);
variable l : line;
file input_file : text is in "mpeg_packet.txt";
begin
wait until falling_edge(rst);
wait until rising_edge(clk);
wait until rising_edge(clk);
-- preamble
crsdv <= '1';
rxd <= "01";
for i in 0 to 10 loop
wait until rising_edge(clk);
end loop;
-- SFD
rxd <= "11";
wait until rising_edge(clk);
while not endfile(input_file) loop
readline(input_file, l);
read(l, tmp);
tmp_v := std_logic_vector(to_unsigned(tmp, 8));
for i in 0 to 3 loop
rxd <= tmp_v(2*i + 1) & tmp_v(2*i);
wait until rising_edge(clk);
end loop;
end loop;
for i in 0 to 1 loop
crsdv <= '0';
wait until rising_edge(clk);
crsdv <= '1';
wait until rising_edge(clk);
end loop;
crsdv <= '0';
wait;
end process;
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity oscillator is
port (data : out STD_LOGIC_VECTOR(7 downto 0);
freq : in STD_LOGIC_VECTOR(15 downto 0);
waveform : in STD_LOGIC;
clk : in STD_LOGIC
);
end oscillator;
architecture behavioral of oscillator is
component sawtooth
port (data : out STD_LOGIC_VECTOR(7 downto 0);
freq : in STD_LOGIC_VECTOR(15 downto 0);
clk : in STD_LOGIC
);
end component;
signal phase : STD_LOGIC_VECTOR(7 downto 0);
begin
-- use sawtooth to get phase
phasegen: sawtooth
port map(phase, freq, clk);
-- use input to select waveform
process(clk, phase, waveform)
begin
if rising_edge(clk) then -- latched so data is stable
if waveform = '0' then
-- just using phase for raw sawtooth
data <= phase;
else
if phase(7) = '0' then -- first half of sawtooth
-- ramp up at twice the speed
data <= phase(6 downto 0) & '0';
else
-- second half, ramp down
data <= (phase(6 downto 0) xor "1111111") & '0';
end if;
end if;
end if;
end process;
end behavioral;
|
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover.vhd
-- |
-- |- axi_datamover_mm2s_omit_wrap.vhd
-- |- axi_datamover_mm2s_full_wrap.vhd
-- |- axi_datamover_mm2s_basic_wrap.vhd
-- |
-- |- axi_datamover_s2mm_omit_wrap.vhd
-- |- axi_datamover_s2mm_full_wrap.vhd
-- |- axi_datamover_s2mm_basic_wrap.vhd
--
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 6/2/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Updated Burst limit and min BTT used calculations to account for
-- the inclusion of upsizer/downsizer logic in the datapath.
-- ^^^^^^
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
-- DET 9/1/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Fixed Lint reported excesive line length for lines 404 and 530.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_mm2s_omit_wrap ;
use axi_datamover_v5_1.axi_datamover_mm2s_full_wrap ;
use axi_datamover_v5_1.axi_datamover_mm2s_basic_wrap;
use axi_datamover_v5_1.axi_datamover_s2mm_omit_wrap ;
use axi_datamover_v5_1.axi_datamover_s2mm_full_wrap ;
use axi_datamover_v5_1.axi_datamover_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_CACHE_USER : integer range 0 to 1 := 0;
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0;
C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(((8*C_ENABLE_CACHE_USER)+C_M_AXI_MM2S_ADDR_WIDTH+40)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(((8*C_ENABLE_CACHE_USER)+C_M_AXI_S2MM_ADDR_WIDTH+40)-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_datamover;
architecture implementation of axi_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
end generate GEN_MM2S_TKEEP_ENABLE1;
GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
m_axis_mm2s_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE1;
GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
end generate GEN_S2MM_TKEEP_ENABLE1;
GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_s2mm_tstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE1;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_OMIT
--
-- If Generate Description:
-- Instantiate the MM2S OMIT Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_OMIT_WRAPPER
--
-- Description:
-- Read omit Wrapper Instance
--
------------------------------------------------------------
I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_omit_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_FULL
--
-- If Generate Description:
-- Instantiate the MM2S Full Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_FULL_WRAPPER
--
-- Description:
-- Read Full Wrapper Instance
--
------------------------------------------------------------
I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_full_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_OMIT
--
-- If Generate Description:
-- Instantiate the S2MM OMIT Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_OMIT_WRAPPER
--
-- Description:
-- Write Omit Wrapper Instance
--
------------------------------------------------------------
I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_omit_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_FULL
--
-- If Generate Description:
-- Instantiate the S2MM FULL Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_FULL_WRAPPER
--
-- Description:
-- Write Full Wrapper Instance
--
------------------------------------------------------------
I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_full_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
end implementation;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created :
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
--User Port1 Interface Signals
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0) ;
p1_cmd_bl : in std_logic_vector(5 downto 0) ;
p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
-- Data Wr Port signals
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0) ;
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
--Data Rd Port signals
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0) ;
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000011";
constant C_PORT_CONFIG : string := "B32_B32_R32_R32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
constant C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
signal mcb3_zio : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_9_ddr3_s6, Coregen 13.3";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr3_s6,mig_v3_9,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR3_SDRAM, CLK_PERIOD=3000, MEMORY_PART=mt41j128m16xx-15e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=DIV6, RTT_NOM=DIV4, AUTO_SR=ENABLED, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1, INPUT_PIN_TERMINATION=EXTERN_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => mcb3_dram_reset_n,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '1',
p1_cmd_clk => p1_cmd_clk,
p1_cmd_en => p1_cmd_en,
p1_cmd_instr => p1_cmd_instr,
p1_cmd_bl => p1_cmd_bl,
p1_cmd_byte_addr => p1_cmd_byte_addr,
p1_cmd_empty => p1_cmd_empty,
p1_cmd_full => p1_cmd_full,
p1_wr_clk => p1_wr_clk,
p1_wr_en => p1_wr_en,
p1_wr_mask => p1_wr_mask,
p1_wr_data => p1_wr_data,
p1_wr_full => p1_wr_full,
p1_wr_empty => p1_wr_empty,
p1_wr_count => p1_wr_count,
p1_wr_underrun => p1_wr_underrun,
p1_wr_error => p1_wr_error,
p1_rd_clk => p1_rd_clk,
p1_rd_en => p1_rd_en,
p1_rd_data => p1_rd_data,
p1_rd_full => p1_rd_full,
p1_rd_empty => p1_rd_empty,
p1_rd_count => p1_rd_count,
p1_rd_overflow => p1_rd_overflow,
p1_rd_error => p1_rd_error,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created :
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
--User Port1 Interface Signals
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0) ;
p1_cmd_bl : in std_logic_vector(5 downto 0) ;
p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
-- Data Wr Port signals
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0) ;
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
--Data Rd Port signals
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0) ;
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000011";
constant C_PORT_CONFIG : string := "B32_B32_R32_R32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
constant C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
signal mcb3_zio : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_9_ddr3_s6, Coregen 13.3";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr3_s6,mig_v3_9,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR3_SDRAM, CLK_PERIOD=3000, MEMORY_PART=mt41j128m16xx-15e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=DIV6, RTT_NOM=DIV4, AUTO_SR=ENABLED, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1, INPUT_PIN_TERMINATION=EXTERN_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => mcb3_dram_reset_n,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '1',
p1_cmd_clk => p1_cmd_clk,
p1_cmd_en => p1_cmd_en,
p1_cmd_instr => p1_cmd_instr,
p1_cmd_bl => p1_cmd_bl,
p1_cmd_byte_addr => p1_cmd_byte_addr,
p1_cmd_empty => p1_cmd_empty,
p1_cmd_full => p1_cmd_full,
p1_wr_clk => p1_wr_clk,
p1_wr_en => p1_wr_en,
p1_wr_mask => p1_wr_mask,
p1_wr_data => p1_wr_data,
p1_wr_full => p1_wr_full,
p1_wr_empty => p1_wr_empty,
p1_wr_count => p1_wr_count,
p1_wr_underrun => p1_wr_underrun,
p1_wr_error => p1_wr_error,
p1_rd_clk => p1_rd_clk,
p1_rd_en => p1_rd_en,
p1_rd_data => p1_rd_data,
p1_rd_full => p1_rd_full,
p1_rd_empty => p1_rd_empty,
p1_rd_count => p1_rd_count,
p1_rd_overflow => p1_rd_overflow,
p1_rd_error => p1_rd_error,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created :
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
--User Port1 Interface Signals
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0) ;
p1_cmd_bl : in std_logic_vector(5 downto 0) ;
p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
-- Data Wr Port signals
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0) ;
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
--Data Rd Port signals
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0) ;
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000011";
constant C_PORT_CONFIG : string := "B32_B32_R32_R32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
constant C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
signal mcb3_zio : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_9_ddr3_s6, Coregen 13.3";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr3_s6,mig_v3_9,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR3_SDRAM, CLK_PERIOD=3000, MEMORY_PART=mt41j128m16xx-15e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=DIV6, RTT_NOM=DIV4, AUTO_SR=ENABLED, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1, INPUT_PIN_TERMINATION=EXTERN_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => mcb3_dram_reset_n,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '1',
p1_cmd_clk => p1_cmd_clk,
p1_cmd_en => p1_cmd_en,
p1_cmd_instr => p1_cmd_instr,
p1_cmd_bl => p1_cmd_bl,
p1_cmd_byte_addr => p1_cmd_byte_addr,
p1_cmd_empty => p1_cmd_empty,
p1_cmd_full => p1_cmd_full,
p1_wr_clk => p1_wr_clk,
p1_wr_en => p1_wr_en,
p1_wr_mask => p1_wr_mask,
p1_wr_data => p1_wr_data,
p1_wr_full => p1_wr_full,
p1_wr_empty => p1_wr_empty,
p1_wr_count => p1_wr_count,
p1_wr_underrun => p1_wr_underrun,
p1_wr_error => p1_wr_error,
p1_rd_clk => p1_rd_clk,
p1_rd_en => p1_rd_en,
p1_rd_data => p1_rd_data,
p1_rd_full => p1_rd_full,
p1_rd_empty => p1_rd_empty,
p1_rd_count => p1_rd_count,
p1_rd_overflow => p1_rd_overflow,
p1_rd_error => p1_rd_error,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created :
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
--User Port1 Interface Signals
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0) ;
p1_cmd_bl : in std_logic_vector(5 downto 0) ;
p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
-- Data Wr Port signals
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0) ;
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
--Data Rd Port signals
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0) ;
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000011";
constant C_PORT_CONFIG : string := "B32_B32_R32_R32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
constant C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
signal mcb3_zio : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_9_ddr3_s6, Coregen 13.3";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr3_s6,mig_v3_9,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR3_SDRAM, CLK_PERIOD=3000, MEMORY_PART=mt41j128m16xx-15e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=DIV6, RTT_NOM=DIV4, AUTO_SR=ENABLED, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1, INPUT_PIN_TERMINATION=EXTERN_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => mcb3_dram_reset_n,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '1',
p1_cmd_clk => p1_cmd_clk,
p1_cmd_en => p1_cmd_en,
p1_cmd_instr => p1_cmd_instr,
p1_cmd_bl => p1_cmd_bl,
p1_cmd_byte_addr => p1_cmd_byte_addr,
p1_cmd_empty => p1_cmd_empty,
p1_cmd_full => p1_cmd_full,
p1_wr_clk => p1_wr_clk,
p1_wr_en => p1_wr_en,
p1_wr_mask => p1_wr_mask,
p1_wr_data => p1_wr_data,
p1_wr_full => p1_wr_full,
p1_wr_empty => p1_wr_empty,
p1_wr_count => p1_wr_count,
p1_wr_underrun => p1_wr_underrun,
p1_wr_error => p1_wr_error,
p1_rd_clk => p1_rd_clk,
p1_rd_en => p1_rd_en,
p1_rd_data => p1_rd_data,
p1_rd_full => p1_rd_full,
p1_rd_empty => p1_rd_empty,
p1_rd_count => p1_rd_count,
p1_rd_overflow => p1_rd_overflow,
p1_rd_error => p1_rd_error,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ssrctrl_net
-- file: ssrctrl_net.vhd
-- Description: Wrapper for SSRAM controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ssrctrl_net is
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end entity ssrctrl_net;
architecture rtl of ssrctrl_net is
component ssrctrl_unisim
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
begin
xil : if ((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)) and bus16=1 generate
ssrctrlxil: ssrctrl_unisim
port map(
rst => rst,
clk => clk,
n_ahbsi_hsel => n_ahbsi_hsel,
n_ahbsi_haddr => n_ahbsi_haddr,
n_ahbsi_hwrite => n_ahbsi_hwrite,
n_ahbsi_htrans => n_ahbsi_htrans,
n_ahbsi_hsize => n_ahbsi_hsize,
n_ahbsi_hburst => n_ahbsi_hburst,
n_ahbsi_hwdata => n_ahbsi_hwdata,
n_ahbsi_hprot => n_ahbsi_hprot,
n_ahbsi_hready => n_ahbsi_hready,
n_ahbsi_hmaster => n_ahbsi_hmaster,
n_ahbsi_hmastlock => n_ahbsi_hmastlock,
n_ahbsi_hmbsel => n_ahbsi_hmbsel,
n_ahbsi_hcache => n_ahbsi_hcache,
n_ahbsi_hirq => n_ahbsi_hirq,
n_ahbso_hready => n_ahbso_hready,
n_ahbso_hresp => n_ahbso_hresp,
n_ahbso_hrdata => n_ahbso_hrdata,
n_ahbso_hsplit => n_ahbso_hsplit,
n_ahbso_hcache => n_ahbso_hcache,
n_ahbso_hirq => n_ahbso_hirq,
n_apbi_psel => n_apbi_psel,
n_apbi_penable => n_apbi_penable,
n_apbi_paddr => n_apbi_paddr,
n_apbi_pwrite => n_apbi_pwrite,
n_apbi_pwdata => n_apbi_pwdata,
n_apbi_pirq => n_apbi_pirq,
n_apbo_prdata => n_apbo_prdata,
n_apbo_pirq => n_apbo_pirq,
n_sri_data => n_sri_data,
n_sri_brdyn => n_sri_brdyn,
n_sri_bexcn => n_sri_bexcn,
n_sri_writen => n_sri_writen,
n_sri_wrn => n_sri_wrn,
n_sri_bwidth => n_sri_bwidth,
n_sri_sd => n_sri_sd,
n_sri_cb => n_sri_cb,
n_sri_scb => n_sri_scb,
n_sri_edac => n_sri_edac,
n_sro_address => n_sro_address,
n_sro_data => n_sro_data,
n_sro_sddata => n_sro_sddata,
n_sro_ramsn => n_sro_ramsn,
n_sro_ramoen => n_sro_ramoen,
n_sro_ramn => n_sro_ramn,
n_sro_romn => n_sro_romn,
n_sro_mben => n_sro_mben,
n_sro_iosn => n_sro_iosn,
n_sro_romsn => n_sro_romsn,
n_sro_oen => n_sro_oen,
n_sro_writen => n_sro_writen,
n_sro_wrn => n_sro_wrn,
n_sro_bdrive => n_sro_bdrive,
n_sro_vbdrive => n_sro_vbdrive,
n_sro_svbdrive => n_sro_svbdrive,
n_sro_read => n_sro_read,
n_sro_sa => n_sro_sa,
n_sro_cb => n_sro_cb,
n_sro_scb => n_sro_scb,
n_sro_vcdrive => n_sro_vcdrive,
n_sro_svcdrive => n_sro_svcdrive,
n_sro_ce => n_sro_ce);
end generate;
-- pragma translate_off
nonet : if not (((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)))
generate
err : process
begin
assert False report "ERROR : No ssrctrl netlist available for this technology!"
severity Failure;
wait;
end process;
end generate;
nobus16 : if not ( bus16=1 )
generate
err : process
begin
assert False report "ERROR : 16-bit PROM bus option not selected for ssrctrl netlist!"
severity Failure;
wait;
end process;
end generate;
-- pragma translate_on
end architecture; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ssrctrl_net
-- file: ssrctrl_net.vhd
-- Description: Wrapper for SSRAM controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ssrctrl_net is
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end entity ssrctrl_net;
architecture rtl of ssrctrl_net is
component ssrctrl_unisim
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
begin
xil : if ((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)) and bus16=1 generate
ssrctrlxil: ssrctrl_unisim
port map(
rst => rst,
clk => clk,
n_ahbsi_hsel => n_ahbsi_hsel,
n_ahbsi_haddr => n_ahbsi_haddr,
n_ahbsi_hwrite => n_ahbsi_hwrite,
n_ahbsi_htrans => n_ahbsi_htrans,
n_ahbsi_hsize => n_ahbsi_hsize,
n_ahbsi_hburst => n_ahbsi_hburst,
n_ahbsi_hwdata => n_ahbsi_hwdata,
n_ahbsi_hprot => n_ahbsi_hprot,
n_ahbsi_hready => n_ahbsi_hready,
n_ahbsi_hmaster => n_ahbsi_hmaster,
n_ahbsi_hmastlock => n_ahbsi_hmastlock,
n_ahbsi_hmbsel => n_ahbsi_hmbsel,
n_ahbsi_hcache => n_ahbsi_hcache,
n_ahbsi_hirq => n_ahbsi_hirq,
n_ahbso_hready => n_ahbso_hready,
n_ahbso_hresp => n_ahbso_hresp,
n_ahbso_hrdata => n_ahbso_hrdata,
n_ahbso_hsplit => n_ahbso_hsplit,
n_ahbso_hcache => n_ahbso_hcache,
n_ahbso_hirq => n_ahbso_hirq,
n_apbi_psel => n_apbi_psel,
n_apbi_penable => n_apbi_penable,
n_apbi_paddr => n_apbi_paddr,
n_apbi_pwrite => n_apbi_pwrite,
n_apbi_pwdata => n_apbi_pwdata,
n_apbi_pirq => n_apbi_pirq,
n_apbo_prdata => n_apbo_prdata,
n_apbo_pirq => n_apbo_pirq,
n_sri_data => n_sri_data,
n_sri_brdyn => n_sri_brdyn,
n_sri_bexcn => n_sri_bexcn,
n_sri_writen => n_sri_writen,
n_sri_wrn => n_sri_wrn,
n_sri_bwidth => n_sri_bwidth,
n_sri_sd => n_sri_sd,
n_sri_cb => n_sri_cb,
n_sri_scb => n_sri_scb,
n_sri_edac => n_sri_edac,
n_sro_address => n_sro_address,
n_sro_data => n_sro_data,
n_sro_sddata => n_sro_sddata,
n_sro_ramsn => n_sro_ramsn,
n_sro_ramoen => n_sro_ramoen,
n_sro_ramn => n_sro_ramn,
n_sro_romn => n_sro_romn,
n_sro_mben => n_sro_mben,
n_sro_iosn => n_sro_iosn,
n_sro_romsn => n_sro_romsn,
n_sro_oen => n_sro_oen,
n_sro_writen => n_sro_writen,
n_sro_wrn => n_sro_wrn,
n_sro_bdrive => n_sro_bdrive,
n_sro_vbdrive => n_sro_vbdrive,
n_sro_svbdrive => n_sro_svbdrive,
n_sro_read => n_sro_read,
n_sro_sa => n_sro_sa,
n_sro_cb => n_sro_cb,
n_sro_scb => n_sro_scb,
n_sro_vcdrive => n_sro_vcdrive,
n_sro_svcdrive => n_sro_svcdrive,
n_sro_ce => n_sro_ce);
end generate;
-- pragma translate_off
nonet : if not (((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)))
generate
err : process
begin
assert False report "ERROR : No ssrctrl netlist available for this technology!"
severity Failure;
wait;
end process;
end generate;
nobus16 : if not ( bus16=1 )
generate
err : process
begin
assert False report "ERROR : 16-bit PROM bus option not selected for ssrctrl netlist!"
severity Failure;
wait;
end process;
end generate;
-- pragma translate_on
end architecture; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1112.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01112ent IS
END c06s05b00x00p03n01i01112ent;
ARCHITECTURE c06s05b00x00p03n01i01112arch OF c06s05b00x00p03n01i01112ent IS
BEGIN
TESTING: PROCESS
subtype FIVE is INTEGER range 1 to 5;
subtype THREE is INTEGER range 1 to 3;
subtype ONE is INTEGER range 1 to 1;
type A0 is array (INTEGER range <>) of BOOLEAN;
subtype A1 is A0 (FIVE);
subtype A2 is A0 (ONE);
subtype A3 is A0 (THREE);
subtype A5 is A0 (FIVE);
variable V2: A2;
variable V3: A3;
BEGIN
V3 := A5'(others=>TRUE) (2 to 4);
-- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01112 - Prefix of a slice name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01112arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1112.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01112ent IS
END c06s05b00x00p03n01i01112ent;
ARCHITECTURE c06s05b00x00p03n01i01112arch OF c06s05b00x00p03n01i01112ent IS
BEGIN
TESTING: PROCESS
subtype FIVE is INTEGER range 1 to 5;
subtype THREE is INTEGER range 1 to 3;
subtype ONE is INTEGER range 1 to 1;
type A0 is array (INTEGER range <>) of BOOLEAN;
subtype A1 is A0 (FIVE);
subtype A2 is A0 (ONE);
subtype A3 is A0 (THREE);
subtype A5 is A0 (FIVE);
variable V2: A2;
variable V3: A3;
BEGIN
V3 := A5'(others=>TRUE) (2 to 4);
-- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01112 - Prefix of a slice name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01112arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1112.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01112ent IS
END c06s05b00x00p03n01i01112ent;
ARCHITECTURE c06s05b00x00p03n01i01112arch OF c06s05b00x00p03n01i01112ent IS
BEGIN
TESTING: PROCESS
subtype FIVE is INTEGER range 1 to 5;
subtype THREE is INTEGER range 1 to 3;
subtype ONE is INTEGER range 1 to 1;
type A0 is array (INTEGER range <>) of BOOLEAN;
subtype A1 is A0 (FIVE);
subtype A2 is A0 (ONE);
subtype A3 is A0 (THREE);
subtype A5 is A0 (FIVE);
variable V2: A2;
variable V3: A3;
BEGIN
V3 := A5'(others=>TRUE) (2 to 4);
-- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01112 - Prefix of a slice name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01112arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.io_bus_pkg.all;
entity update_io is
generic (
g_remote : boolean := true );
port (
clock : in std_logic := '0'; -- clock.clk
reset : in std_logic := '0'; -- reset.reset
slow_clock : in std_logic;
slow_reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
flash_selck : out std_logic;
flash_sel : out std_logic );
end entity update_io;
architecture rtl of update_io is
component update_remote_update_0 is
port (
busy : out std_logic; -- busy
data_out : out std_logic_vector(28 downto 0); -- data_out
param : in std_logic_vector(2 downto 0) := (others => 'X'); -- param
read_param : in std_logic := 'X'; -- read_param
reconfig : in std_logic := 'X'; -- reconfig
reset_timer : in std_logic := 'X'; -- reset_timer
read_source : in std_logic_vector(1 downto 0) := (others => 'X'); -- read_source
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X' -- reset
);
end component update_remote_update_0;
signal busy : std_logic; -- busy
signal data_out : std_logic_vector(28 downto 0); -- data_out
signal param : std_logic_vector(2 downto 0) := (others => '0'); -- param
signal read_param : std_logic := '0'; -- read_param
signal reconfig : std_logic := '0'; -- reconfig
signal reset_timer : std_logic := '0'; -- reset_timer
signal read_source : std_logic_vector(1 downto 0) := (others => '0'); -- read_source
signal flash_sel_i : std_logic;
signal flash_selck_i : std_logic;
signal slow_req : t_io_req;
signal slow_resp : t_io_resp;
begin
i_bridge: entity work.io_bus_bridge2
generic map (
g_addr_width => 4
)
port map(
clock_a => clock,
reset_a => reset,
req_a => io_req,
resp_a => io_resp,
clock_b => slow_clock,
reset_b => slow_reset,
req_b => slow_req,
resp_b => slow_resp );
r_remote: if g_remote generate
remote_update_0 : component update_remote_update_0
port map (
busy => busy, -- busy.busy
data_out => data_out, -- data_out.data_out
param => param, -- param.param
read_param => read_param, -- read_param.read_param
reconfig => reconfig, -- reconfig.reconfig
reset_timer => reset_timer, -- reset_timer.reset_timer
read_source => read_source, -- read_source.read_source
clock => slow_clock, -- clock.clk
reset => slow_reset -- reset.reset
);
end generate;
process(slow_clock)
variable local : unsigned(3 downto 0);
begin
if rising_edge(slow_clock) then
local := slow_req.address(3 downto 0);
slow_resp <= c_io_resp_init;
read_param <= '0';
if slow_req.read = '1' then
slow_resp.ack <= '1';
case local is
when X"0" =>
slow_resp.data <= data_out(7 downto 0);
when X"1" =>
slow_resp.data <= data_out(15 downto 8);
when X"2" =>
slow_resp.data <= data_out(23 downto 16);
when X"3" =>
slow_resp.data <= "000" & data_out(28 downto 24);
when X"5" =>
slow_resp.data(0) <= busy;
when X"6" =>
slow_resp.data(0) <= reconfig;
when X"8"|X"9" =>
slow_resp.data(0) <= flash_selck_i;
when X"A"|X"B" =>
slow_resp.data(0) <= flash_sel_i;
when others =>
null;
end case;
end if;
if slow_req.write = '1' then
slow_resp.ack <= '1';
case local is
when X"4" =>
param <= slow_req.data(param'range);
read_source <= slow_req.data(5 downto 4);
read_param <= '1';
when X"6" =>
if slow_req.data = X"BE" then
reconfig <= '1';
end if;
when X"8" =>
flash_selck_i <= '0';
when X"9" =>
flash_selck_i <= '1';
when X"A" =>
flash_sel_i <= '0';
when X"B" =>
flash_sel_i <= '1';
when others =>
null;
end case;
end if;
if slow_reset = '1' then
read_source <= (others => '0');
reconfig <= '0';
param <= (others => '0');
flash_selck_i <= '0';
flash_sel_i <= '0';
end if;
end if;
end process;
flash_selck <= flash_selck_i;
flash_sel <= flash_sel_i;
end architecture rtl; -- of update
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2442.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02442ent IS
type a_index is range 0 to 15;
type a_bus is array (a_index range <>) of bit;
END c07s03b02x02p01n01i02442ent;
ARCHITECTURE c07s03b02x02p01n01i02442arch OF c07s03b02x02p01n01i02442ent IS
signal a_sig : a_bus(a_index range 0 to 3);
BEGIN
TESTING: PROCESS
variable tmp : a_index := 0;
BEGIN
for i in a_index loop
tmp := i mod 4;
a_sig(tmp to tmp) <= 1;
if tmp >= 4 then
assert false
report "Choice index out of range."
severity note ;
exit;
end if;
end loop;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02442 - Each choice must specify values of the index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02442arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2442.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02442ent IS
type a_index is range 0 to 15;
type a_bus is array (a_index range <>) of bit;
END c07s03b02x02p01n01i02442ent;
ARCHITECTURE c07s03b02x02p01n01i02442arch OF c07s03b02x02p01n01i02442ent IS
signal a_sig : a_bus(a_index range 0 to 3);
BEGIN
TESTING: PROCESS
variable tmp : a_index := 0;
BEGIN
for i in a_index loop
tmp := i mod 4;
a_sig(tmp to tmp) <= 1;
if tmp >= 4 then
assert false
report "Choice index out of range."
severity note ;
exit;
end if;
end loop;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02442 - Each choice must specify values of the index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02442arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2442.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02442ent IS
type a_index is range 0 to 15;
type a_bus is array (a_index range <>) of bit;
END c07s03b02x02p01n01i02442ent;
ARCHITECTURE c07s03b02x02p01n01i02442arch OF c07s03b02x02p01n01i02442ent IS
signal a_sig : a_bus(a_index range 0 to 3);
BEGIN
TESTING: PROCESS
variable tmp : a_index := 0;
BEGIN
for i in a_index loop
tmp := i mod 4;
a_sig(tmp to tmp) <= 1;
if tmp >= 4 then
assert false
report "Choice index out of range."
severity note ;
exit;
end if;
end loop;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02442 - Each choice must specify values of the index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02442arch;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3);
U_INST1 : INST1
port map (
PORT_1 => w_port_1-- Comment
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1-- Comment
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1 -- Comment
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1 -- Comment
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1 -- Comment
);-- Comment2
U_INST1 : INST1
port map (
PORT_1 => w_port_1 -- Comment
);-- Comment2
U_INST1 : INST1
port map (
PORT_1 => w_port_1 -- Comment
); -- Comment2
U_INST1 : INST1
port map (
PORT_1 => w_port_1 -- Comment
); -- Comment2
end architecture ARCH;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT36.VHD ***
--*** ***
--*** Function: 36 bit Unsigned Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_rsft36;
ARCHITECTURE rtl OF fp_rsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2) AND NOT(shift(1)));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND NOT(shift(2)) AND shift(1));
levone(36) <= levzip(36) AND NOT(shift(2)) AND NOT(shift(1));
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbd: FOR k IN 33 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 21 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT36.VHD ***
--*** ***
--*** Function: 36 bit Unsigned Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_rsft36;
ARCHITECTURE rtl OF fp_rsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2) AND NOT(shift(1)));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND NOT(shift(2)) AND shift(1));
levone(36) <= levzip(36) AND NOT(shift(2)) AND NOT(shift(1));
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbd: FOR k IN 33 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 21 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT36.VHD ***
--*** ***
--*** Function: 36 bit Unsigned Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_rsft36;
ARCHITECTURE rtl OF fp_rsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2) AND NOT(shift(1)));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND NOT(shift(2)) AND shift(1));
levone(36) <= levzip(36) AND NOT(shift(2)) AND NOT(shift(1));
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbd: FOR k IN 33 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 21 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT36.VHD ***
--*** ***
--*** Function: 36 bit Unsigned Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_rsft36;
ARCHITECTURE rtl OF fp_rsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2) AND NOT(shift(1)));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND NOT(shift(2)) AND shift(1));
levone(36) <= levzip(36) AND NOT(shift(2)) AND NOT(shift(1));
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbd: FOR k IN 33 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 21 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT36.VHD ***
--*** ***
--*** Function: 36 bit Unsigned Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_rsft36;
ARCHITECTURE rtl OF fp_rsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2) AND NOT(shift(1)));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND NOT(shift(2)) AND shift(1));
levone(36) <= levzip(36) AND NOT(shift(2)) AND NOT(shift(1));
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbd: FOR k IN 33 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 21 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT36.VHD ***
--*** ***
--*** Function: 36 bit Unsigned Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_rsft36;
ARCHITECTURE rtl OF fp_rsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2) AND NOT(shift(1)));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND NOT(shift(2)) AND shift(1));
levone(36) <= levzip(36) AND NOT(shift(2)) AND NOT(shift(1));
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbd: FOR k IN 33 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 21 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT36.VHD ***
--*** ***
--*** Function: 36 bit Unsigned Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_rsft36;
ARCHITECTURE rtl OF fp_rsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2) AND NOT(shift(1)));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND NOT(shift(2)) AND shift(1));
levone(36) <= levzip(36) AND NOT(shift(2)) AND NOT(shift(1));
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbd: FOR k IN 33 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 21 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT36.VHD ***
--*** ***
--*** Function: 36 bit Unsigned Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_rsft36;
ARCHITECTURE rtl OF fp_rsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2) AND NOT(shift(1)));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND NOT(shift(2)) AND shift(1));
levone(36) <= levzip(36) AND NOT(shift(2)) AND NOT(shift(1));
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbd: FOR k IN 33 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 21 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT36.VHD ***
--*** ***
--*** Function: 36 bit Unsigned Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_rsft36;
ARCHITECTURE rtl OF fp_rsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2) AND NOT(shift(1)));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND NOT(shift(2)) AND shift(1));
levone(36) <= levzip(36) AND NOT(shift(2)) AND NOT(shift(1));
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbd: FOR k IN 33 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 21 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT36.VHD ***
--*** ***
--*** Function: 36 bit Unsigned Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_rsft36;
ARCHITECTURE rtl OF fp_rsft36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2) AND NOT(shift(1)));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND NOT(shift(2)) AND shift(1));
levone(36) <= levzip(36) AND NOT(shift(2)) AND NOT(shift(1));
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbd: FOR k IN 33 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 21 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Provides some generic constants and types.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
package Globals is
end;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Provides some generic constants and types.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
package Globals is
end;
|
architecture rtl of fifo is
signal rd_en : std_logic;
signal wr_en : std_logic;
begin
end architecture rtl;
architecture rtl of fifo is
signal rd_en:std_logic;
signal wr_en:std_logic;
begin
end architecture rtl;
architecture rtl of fifo is
signal rd_en : std_logic;
signal wr_en : std_logic;
begin
end architecture rtl;
|
--
-- VHDL Architecture lab10_RegFile_lib.Decoder.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 23:12:41 04/ 8/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;
ENTITY Decoder IS
GENERIC( size: positive := 4); -- 16 registers available
PORT( sel: IN std_logic_vector(size-1 downto 0) := (others=>'0');
onehot: OUT std_logic_vector( (2**size)-1 downto 0 );
enable: IN std_logic);
END ENTITY Decoder;
ARCHITECTURE Behavior OF Decoder IS
BEGIN
PROCESS(sel, enable)
VARIABLE selection: natural;
VARIABLE result: std_logic_vector( (2**size)-1 downto 0 );
CONSTANT zero: std_logic_vector( (2**size)-1 downto 0 ) := (others=> '0');
BEGIN
result := zero;
IF(enable = '1') THEN
selection := to_integer( ieee.numeric_std.unsigned(sel) );
result(selection) := '1';
END IF;
onehot <= result;
END PROCESS;
END ARCHITECTURE Behavior;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmask is
generic
(mask : std_logic_vector (0 to 7));
port (d : std_logic_vector (7 downto 0);
o : out std_logic_vector (7 downto 0));
end cmask;
architecture behav of cmask is
begin
o <= d and mask;
end behav;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - FIFO
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A simple unidirectional and asynchronous FIFO.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reconos_fifo_async is
--
-- Definition of the fifo generics
--
-- C_FIFO_DATA_WIDTH - width of the data words
-- C_FIFO_ADDR_WIDTH - address width (2^C_FIFO_ADDR_WIDTH elements)
--
-- C_USE_ALMOST - enables/disables the almost signals
-- C_USE_FILLREMM - use fill/remaining signals
-- C_FIFO_AEMPTY - limit for almost empty
-- C_FIFO_AFULL - limit for almost full
--
generic (
C_FIFO_DATA_WIDTH : integer := 32;
C_FIFO_ADDR_WIDTH : integer := 2;
C_USE_ALMOST : boolean := false;
C_USE_FILL_REMM : boolean := false;
C_FIFO_AEMPTY : integer := 2;
C_FIFO_AFULL : integer := 2
);
--
-- Definition of the fifo ports
--
-- FIFO_S_Clk - clock of the slave port
-- FIFO_S_Data - data to read
-- FIFO_S_Fill - number of elements currently stored
-- FIFO_S_Empty - indicates if empty
-- FIFO_S_AEmpty - indicates if almost empty (see C_FIFO_AEMPTY)
-- FIFO_S_RE - read enable signal
--
-- FIFO_M_Clk - clock of the master port
-- FIFO_M_Data - data to write
-- FIFO_M_Remm - number of elements free to store
-- FIFO_M_Full - indicates if full
-- FIFO_M_AFull - indicates if almost full (see C_FIFO_AFULL)
-- FIFO_M_WE - write enable signal
--
-- FIFO_Rst - asynchronous reset
-- FIFO_Has_Data - interrupt signal if fifo has data
--
port (
FIFO_S_Clk : in std_logic;
FIFO_S_Data : out std_logic_vector(C_FIFO_DATA_WIDTH - 1 downto 0);
FIFO_S_Fill : out std_logic_vector(C_FIFO_ADDR_WIDTH downto 0);
FIFO_S_Empty : out std_logic;
FIFO_S_AEmpty : out std_logic;
FIFO_S_RE : in std_logic;
FIFO_M_Clk : in std_logic;
FIFO_M_Data : in std_logic_vector(C_FIFO_DATA_WIDTH - 1 downto 0);
FIFO_M_Remm : out std_logic_vector(C_FIFO_ADDR_WIDTH downto 0);
FIFO_M_Full : out std_logic;
FIFO_M_AFull : out std_logic;
FIFO_M_WE : in std_logic;
FIFO_Rst : in std_logic;
FIFO_Has_Data : out std_logic
);
end entity reconos_fifo_async;
architecture imp of reconos_fifo_async is
-- Declare port attributes for the Vivado IP Packager
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of FIFO_Has_Data: SIGNAL is "xilinx.com:signal:interrupt:1.0 FIFO_Has_Data INTERRUPT";
ATTRIBUTE X_INTERFACE_PARAMETER of FIFO_Has_Data: SIGNAL is "SENSITIVITY LEVEL_HIGH";
ATTRIBUTE X_INTERFACE_INFO of FIFO_M_Clk: SIGNAL is "xilinx.com:signal:clock:1.0 FIFO_M_Clk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of FIFO_M_Clk: SIGNAL is "ASSOCIATED_BUSIF FIFO_M";
ATTRIBUTE X_INTERFACE_INFO of FIFO_S_Clk: SIGNAL is "xilinx.com:signal:clock:1.0 FIFO_S_Clk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of FIFO_S_Clk: SIGNAL is "ASSOCIATED_BUSIF FIFO_S";
ATTRIBUTE X_INTERFACE_INFO of FIFO_Rst: SIGNAL is "xilinx.com:signal:reset:1.0 FIFO_Rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER of FIFO_Rst: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO of FIFO_M_Data: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 FIFO_M FIFO_M_Data";
ATTRIBUTE X_INTERFACE_INFO of FIFO_M_Full: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 FIFO_M FIFO_M_Full";
ATTRIBUTE X_INTERFACE_INFO of FIFO_M_WE: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 FIFO_M FIFO_M_WE";
ATTRIBUTE X_INTERFACE_INFO of FIFO_S_Data: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 FIFO_S FIFO_S_Data";
ATTRIBUTE X_INTERFACE_INFO of FIFO_S_Empty: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 FIFO_S FIFO_S_Empty";
ATTRIBUTE X_INTERFACE_INFO of FIFO_S_RE: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 FIFO_S FIFO_S_RE";
--
-- Internal constants
--
-- C_FIFO_DEPTH - number of elements to store
--
constant C_FIFO_DEPTH : integer := 2 ** C_FIFO_ADDR_WIDTH;
--
-- Internal ram to store data
--
-- The internal ram is modelled according to the XST User Guide and
-- will be synthesized as distributed ram. Block ram might be more
-- efficient use of resources but the fifo is typically rather
-- small and the block ram delay is hard to handle.
--
-- ram_type - vhdl type of the ram
-- ram - instantiation of the ram
--
type ram_type is array (0 to C_FIFO_DEPTH - 1)
of std_logic_vector(C_FIFO_DATA_WIDTH - 1 downto 0);
signal ram : ram_type;
--
-- Internal pointers used to store state
--
-- The internal counters represent the state of the fifo. The read
-- pointer always points at the active word to read and the write
-- pointer to the next free memory location. To handle full and
-- empty conditions, the counters are one bit wider than the
-- address and the extra bit is used to distinguish full and empty.
-- The counters are synchronized to the other clock domain via
-- gray code conversion and a two stage synchronizer.
--
-- rdbin, wrbin - read and write counters
-- rdgry, wrgry - gray code conversion of the binary counters
-- rdptr, wrptr - read and write pointers to address the ram
--
-- rdgry_sync0, rdgry_sync, rdbin_sync - synchronized read pointers
-- wrgry_sync0, wrgry_sync, wrbin_sync - synchronized write pointers
--
signal rdbin, wrbin : unsigned(C_FIFO_ADDR_WIDTH downto 0) := (others => '0');
signal rdgry, wrgry : unsigned(C_FIFO_ADDR_WIDTH downto 0) := (others => '0');
signal rdptr, wrptr : unsigned(C_FIFO_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal rdgry_sync0, rdgry_sync, rdbin_sync : unsigned(C_FIFO_ADDR_WIDTH downto 0) := (others => '0');
signal wrgry_sync0, wrgry_sync, wrbin_sync : unsigned(C_FIFO_ADDR_WIDTH downto 0) := (others => '0');
--
-- Synchronized signals to read or write clock
--
-- rdfill, rdremm - fill and remaining in read clock
-- wrfill, wrremm - fill and remaining in write clock
--
-- rdempty, rdaempty - empty signals in read clock
-- wrfull, wrafull - full signals in write clock
--
signal rdfill, rdremm : unsigned(C_FIFO_ADDR_WIDTH downto 0) := (others => '0');
signal wrfill, wrremm : unsigned(C_FIFO_ADDR_WIDTH downto 0) := (others => '0');
signal rdempty, rdaempty : std_logic;
signal wrfull, wrafull : std_logic;
begin
-- == Asynchronous calculations =======================================
rdptr <= rdbin(C_FIFO_ADDR_WIDTH - 1 downto 0);
wrptr <= wrbin(C_FIFO_ADDR_WIDTH - 1 downto 0);
rdfill <= wrbin_sync - rdbin;
rdremm <= C_FIFO_DEPTH - rdfill;
wrfill <= wrbin - rdbin_sync;
wrremm <= C_FIFO_DEPTH - wrfill;
rdempty <= '1' when rdfill = 0 else '0';
rdaempty <= '1' when rdfill <= C_FIFO_AEMPTY else '0';
wrfull <= '1' when wrfill = C_FIFO_DEPTH else '0';
wrafull <= '1' when wrfill >= C_FIFO_DEPTH - C_FIFO_AFULL else '0';
rdgry <= (rdbin srl 1) xor rdbin;
wrgry <= (wrbin srl 1) xor wrbin;
rdbin_sync <= (rdbin_sync srl 1) xor rdgry_sync;
wrbin_sync <= (wrbin_sync srl 1) xor wrgry_sync;
-- == Process definitions =============================================
--
-- Synchronize write counter to read clock
--
-- A two stage synchronizer to cross the different clocks
--
rd_sync : process(FIFO_S_Clk,FIFO_Rst) is
begin
if FIFO_Rst = '1' then
wrgry_sync0 <= (others => '0');
wrgry_sync <= (others => '0');
elsif rising_edge(FIFO_S_Clk) then
wrgry_sync0 <= wrgry;
wrgry_sync <= wrgry_sync0;
end if;
end process rd_sync;
--
-- Synchronize read counter to write clock
--
-- A two stage synchronizer to cross the different clocks
--
wr_sync : process(FIFO_M_Clk,FIFO_Rst) is
begin
if FIFO_Rst = '1' then
rdgry_sync0 <= (others => '0');
rdgry_sync <= (others => '0');
elsif rising_edge(FIFO_M_Clk) then
rdgry_sync0 <= rdgry;
rdgry_sync <= rdgry_sync0;
end if;
end process wr_sync;
--
-- Read process
--
-- Reading from the fifo by incrementing read counter
--
rd_proc : process(FIFO_S_Clk,FIFO_Rst) is
begin
if FIFO_Rst = '1' then
rdbin <= (others => '0');
elsif rising_edge(FIFO_S_Clk) then
if FIFO_S_RE = '1' and not rdempty = '1' then
rdbin <= rdbin + 1;
end if;
end if;
end process rd_proc;
--
-- Write process
--
-- Writing to the fifo by incrementing write counter and writing
-- data to internal ram.
--
wr_proc : process(FIFO_M_Clk,FIFO_Rst) is
begin
if FIFO_Rst = '1' then
wrbin <= (others => '0');
elsif rising_edge(FIFO_M_Clk) then
if FIFO_M_WE = '1' and not wrfull = '1' then
ram(to_integer(wrptr)) <= FIFO_M_Data;
wrbin <= wrbin + 1;
end if;
end if;
end process wr_proc;
-- == Output port assignment ==========================================
FIFO_S_Fill <= std_logic_vector(rdfill);
FIFO_S_Empty <= rdempty;
FIFO_S_AEmpty <= rdaempty;
FIFO_S_Data <= ram(to_integer(rdptr));
FIFO_M_Remm <= std_logic_vector(wrremm);
FIFO_M_Full <= wrfull;
FIFO_M_AFull <= wrafull;
FIFO_Has_Data <= not rdempty;
end architecture imp;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:48:24 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0_sim_netlist.vhdl
-- Design : system_axi_gpio_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_address_decoder is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[19]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 19 downto 0 );
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
is_read : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 19 downto 0 );
\Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_address_decoder : entity is "address_decoder";
end system_axi_gpio_0_0_address_decoder;
architecture STRUCTURE of system_axi_gpio_0_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\ : STD_LOGIC;
signal \^not_dual.gpio_data_out_reg[19]\ : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[0]\ : STD_LOGIC;
signal \^ip_irpt_enable_reg_reg[0]\ : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in_0 : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pselect_hit_i_1 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[0]_i_2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[12]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[13]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[14]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[15]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[17]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[18]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[19]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[7]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of intr2bus_rdack_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of irpt_rdack_d1_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair3";
begin
\Not_Dual.gpio_Data_Out_reg[19]\ <= \^not_dual.gpio_data_out_reg[19]\;
\ip2bus_data_i_D1_reg[0]\ <= \^ip2bus_data_i_d1_reg[0]\;
\ip_irpt_enable_reg_reg[0]\ <= \^ip_irpt_enable_reg_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => start2,
I2 => \^ip_irpt_enable_reg_reg[0]\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^ip_irpt_enable_reg_reg[0]\,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_9_out
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_9_out,
Q => p_10_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_8_out
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_8_out,
Q => p_9_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_7_out
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_7_out,
Q => \^ip2bus_data_i_d1_reg[0]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_6_out
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_6_out,
Q => p_7_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_5_out
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_5_out,
Q => p_6_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_4_out
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_4_out,
Q => p_5_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\,
Q => p_4_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
Q => p_3_in_0,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\,
Q => p_2_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_aresetn,
I1 => \^s_axi_arready\,
I2 => \^s_axi_wready\,
O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_15_out
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_15_out,
Q => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\,
Q => p_16_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_14_out
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_14_out,
Q => p_15_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_13_out
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_13_out,
Q => p_14_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_12_out
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_12_out,
Q => p_13_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_11_out
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_11_out,
Q => p_12_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_10_out
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_10_out,
Q => p_11_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_rd_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FE0000"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => ip2Bus_RdAck_intr_reg_hole_d1,
I4 => \^ip_irpt_enable_reg_reg[0]\,
O => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_wr_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_16_in,
I1 => p_2_in,
I2 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
I3 => p_14_in,
I4 => p_15_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_12_in,
I1 => p_13_in,
I2 => p_10_in,
I3 => p_11_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_5_in,
I1 => p_7_in,
I2 => p_3_in_0,
I3 => p_4_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => ip2Bus_WrAck_intr_reg_hole_d1,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => start2,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(4),
I3 => \bus2ip_addr_i_reg[8]\(5),
I4 => \bus2ip_addr_i_reg[8]\(3),
I5 => \bus2ip_addr_i_reg[8]\(2),
O => pselect_hit_i_1
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => pselect_hit_i_1,
Q => \^not_dual.gpio_data_out_reg[19]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(19),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(19),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => GPIO_DBus_i(0)
);
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(9),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(9),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\
);
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(8),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(8),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\
);
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(7),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(7),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\
);
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(6),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(6),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\
);
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(5),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(5),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\
);
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(4),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(4),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\
);
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(3),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\
);
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(2),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\
);
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(1),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\
);
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^not_dual.gpio_data_out_reg[19]\,
I1 => GPIO_xferAck_i,
I2 => bus2ip_rnw_i_reg,
I3 => gpio_xferAck_Reg,
O => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(0),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\
);
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(18),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(18),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\
);
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(17),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(17),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\
);
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(16),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(16),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\
);
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(15),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(15),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\
);
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(14),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(14),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\
);
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(13),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(13),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\
);
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(12),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(12),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\
);
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(11),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(11),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\
);
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(10),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(10),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000100"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[19]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => \Not_Dual.gpio_Data_Out_reg[0]\(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(31),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(19),
O => D(19)
);
\Not_Dual.gpio_Data_Out[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(21),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(9),
O => D(9)
);
\Not_Dual.gpio_Data_Out[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(20),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(8),
O => D(8)
);
\Not_Dual.gpio_Data_Out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(19),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(7),
O => D(7)
);
\Not_Dual.gpio_Data_Out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(18),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(6),
O => D(6)
);
\Not_Dual.gpio_Data_Out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(17),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(5),
O => D(5)
);
\Not_Dual.gpio_Data_Out[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(16),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(4),
O => D(4)
);
\Not_Dual.gpio_Data_Out[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(15),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(3),
O => D(3)
);
\Not_Dual.gpio_Data_Out[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(14),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(2),
O => D(2)
);
\Not_Dual.gpio_Data_Out[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(13),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(1),
O => D(1)
);
\Not_Dual.gpio_Data_Out[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(12),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(0),
O => D(0)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(30),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(18),
O => D(18)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(29),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(17),
O => D(17)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(28),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(16),
O => D(16)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(27),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(15),
O => D(15)
);
\Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(26),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(14),
O => D(14)
);
\Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(25),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(13),
O => D(13)
);
\Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(24),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(12),
O => D(12)
);
\Not_Dual.gpio_Data_Out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(23),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(11),
O => D(11)
);
\Not_Dual.gpio_Data_Out[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(22),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(10),
O => D(10)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF01000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[19]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => E(0)
);
intr2bus_rdack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"44444440"
)
port map (
I0 => irpt_rdack_d1,
I1 => \^ip_irpt_enable_reg_reg[0]\,
I2 => p_9_in,
I3 => \^ip2bus_data_i_d1_reg[0]\,
I4 => p_6_in,
O => intr2bus_rdack0
);
intr2bus_wrack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => irpt_wrack_d1,
O => interrupt_wrce_strb
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => p_0_in(0),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_6_in,
I4 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(1)
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEAAAAFAAAAAAA"
)
port map (
I0 => ip2bus_data(0),
I1 => p_3_in(0),
I2 => p_1_in(0),
I3 => p_6_in,
I4 => \^ip_irpt_enable_reg_reg[0]\,
I5 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(0)
);
\ip_irpt_enable_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_6_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_1_in(0),
O => \ip_irpt_enable_reg_reg[0]_0\
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(31),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_0_in(0),
O => ipif_glbl_irpt_enable_reg_reg
);
irpt_rdack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_rdack
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_wrack
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_read,
I5 => ip2bus_rdack_i_D1,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_write_reg,
I5 => ip2bus_wrack_i_D1,
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_cdc_sync is
port (
D : out STD_LOGIC_VECTOR ( 19 downto 0 );
scndry_vect_out : out STD_LOGIC_VECTOR ( 19 downto 0 );
Q : in STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_cdc_sync : entity is "cdc_sync";
end system_axi_gpio_0_0_cdc_sync;
architecture STRUCTURE of system_axi_gpio_0_0_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_10 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_11 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_12 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_13 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_14 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_15 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_16 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_17 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_18 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_19 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_8 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_9 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_10 : STD_LOGIC;
signal s_level_out_bus_d2_11 : STD_LOGIC;
signal s_level_out_bus_d2_12 : STD_LOGIC;
signal s_level_out_bus_d2_13 : STD_LOGIC;
signal s_level_out_bus_d2_14 : STD_LOGIC;
signal s_level_out_bus_d2_15 : STD_LOGIC;
signal s_level_out_bus_d2_16 : STD_LOGIC;
signal s_level_out_bus_d2_17 : STD_LOGIC;
signal s_level_out_bus_d2_18 : STD_LOGIC;
signal s_level_out_bus_d2_19 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d2_8 : STD_LOGIC;
signal s_level_out_bus_d2_9 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_10 : STD_LOGIC;
signal s_level_out_bus_d3_11 : STD_LOGIC;
signal s_level_out_bus_d3_12 : STD_LOGIC;
signal s_level_out_bus_d3_13 : STD_LOGIC;
signal s_level_out_bus_d3_14 : STD_LOGIC;
signal s_level_out_bus_d3_15 : STD_LOGIC;
signal s_level_out_bus_d3_16 : STD_LOGIC;
signal s_level_out_bus_d3_17 : STD_LOGIC;
signal s_level_out_bus_d3_18 : STD_LOGIC;
signal s_level_out_bus_d3_19 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
signal s_level_out_bus_d3_8 : STD_LOGIC;
signal s_level_out_bus_d3_9 : STD_LOGIC;
signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 19 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
scndry_vect_out(19 downto 0) <= \^scndry_vect_out\(19 downto 0);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_10,
Q => s_level_out_bus_d2_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_11,
Q => s_level_out_bus_d2_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_12,
Q => s_level_out_bus_d2_12,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_13,
Q => s_level_out_bus_d2_13,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_14,
Q => s_level_out_bus_d2_14,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_15,
Q => s_level_out_bus_d2_15,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_16,
Q => s_level_out_bus_d2_16,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_17,
Q => s_level_out_bus_d2_17,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_18,
Q => s_level_out_bus_d2_18,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_19,
Q => s_level_out_bus_d2_19,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_8,
Q => s_level_out_bus_d2_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_9,
Q => s_level_out_bus_d2_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_10,
Q => s_level_out_bus_d3_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_11,
Q => s_level_out_bus_d3_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_12,
Q => s_level_out_bus_d3_12,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_13,
Q => s_level_out_bus_d3_13,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_14,
Q => s_level_out_bus_d3_14,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_15,
Q => s_level_out_bus_d3_15,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_16,
Q => s_level_out_bus_d3_16,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_17,
Q => s_level_out_bus_d3_17,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_18,
Q => s_level_out_bus_d3_18,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_19,
Q => s_level_out_bus_d3_19,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_8,
Q => s_level_out_bus_d3_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_9,
Q => s_level_out_bus_d3_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => \^scndry_vect_out\(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_10,
Q => \^scndry_vect_out\(10),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_11,
Q => \^scndry_vect_out\(11),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_12,
Q => \^scndry_vect_out\(12),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_13,
Q => \^scndry_vect_out\(13),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_14,
Q => \^scndry_vect_out\(14),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_15,
Q => \^scndry_vect_out\(15),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_16,
Q => \^scndry_vect_out\(16),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_17,
Q => \^scndry_vect_out\(17),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_18,
Q => \^scndry_vect_out\(18),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_19,
Q => \^scndry_vect_out\(19),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => \^scndry_vect_out\(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => \^scndry_vect_out\(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => \^scndry_vect_out\(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => \^scndry_vect_out\(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => \^scndry_vect_out\(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => \^scndry_vect_out\(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => \^scndry_vect_out\(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_8,
Q => \^scndry_vect_out\(8),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_9,
Q => \^scndry_vect_out\(9),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(10),
Q => s_level_out_bus_d1_cdc_to_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(11),
Q => s_level_out_bus_d1_cdc_to_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(12),
Q => s_level_out_bus_d1_cdc_to_12,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(13),
Q => s_level_out_bus_d1_cdc_to_13,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(14),
Q => s_level_out_bus_d1_cdc_to_14,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(15),
Q => s_level_out_bus_d1_cdc_to_15,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(16),
Q => s_level_out_bus_d1_cdc_to_16,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(17),
Q => s_level_out_bus_d1_cdc_to_17,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(18),
Q => s_level_out_bus_d1_cdc_to_18,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(19),
Q => s_level_out_bus_d1_cdc_to_19,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(8),
Q => s_level_out_bus_d1_cdc_to_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(9),
Q => s_level_out_bus_d1_cdc_to_9,
R => '0'
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(19),
I1 => \^scndry_vect_out\(19),
O => D(19)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(9),
I1 => \^scndry_vect_out\(9),
O => D(9)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => \^scndry_vect_out\(8),
O => D(8)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => \^scndry_vect_out\(7),
O => D(7)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => \^scndry_vect_out\(6),
O => D(6)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => \^scndry_vect_out\(5),
O => D(5)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => \^scndry_vect_out\(4),
O => D(4)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => \^scndry_vect_out\(3),
O => D(3)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => \^scndry_vect_out\(2),
O => D(2)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => \^scndry_vect_out\(1),
O => D(1)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => \^scndry_vect_out\(0),
O => D(0)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(18),
I1 => \^scndry_vect_out\(18),
O => D(18)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(17),
I1 => \^scndry_vect_out\(17),
O => D(17)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(16),
I1 => \^scndry_vect_out\(16),
O => D(16)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(15),
I1 => \^scndry_vect_out\(15),
O => D(15)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(14),
I1 => \^scndry_vect_out\(14),
O => D(14)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(13),
I1 => \^scndry_vect_out\(13),
O => D(13)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(12),
I1 => \^scndry_vect_out\(12),
O => D(12)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(11),
I1 => \^scndry_vect_out\(11),
O => D(11)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(10),
I1 => \^scndry_vect_out\(10),
O => D(10)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
p_3_in : out STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
IP2INTC_Irpt_i : out STD_LOGIC;
ip2bus_wrack_i : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
GPIO_intr : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ : in STD_LOGIC;
p_8_in : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC;
bus2ip_rnw : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_interrupt_control : entity is "interrupt_control";
end system_axi_gpio_0_0_interrupt_control;
architecture STRUCTURE of system_axi_gpio_0_0_interrupt_control is
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\ : STD_LOGIC;
signal intr2bus_rdack : STD_LOGIC;
signal intr2bus_wrack : STD_LOGIC;
signal irpt_dly1 : STD_LOGIC;
signal irpt_dly2 : STD_LOGIC;
signal \^irpt_wrack_d1\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_1_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_3_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
irpt_wrack_d1 <= \^irpt_wrack_d1\;
p_0_in(0) <= \^p_0_in\(0);
p_1_in(0) <= \^p_1_in\(0);
p_3_in(0) <= \^p_3_in\(0);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_intr,
Q => irpt_dly1,
S => bus2ip_reset
);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_dly1,
Q => irpt_dly2,
S => bus2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F4F44FF4F4F4"
)
port map (
I0 => irpt_dly2,
I1 => irpt_dly1,
I2 => \^p_3_in\(0),
I3 => p_8_in,
I4 => s_axi_wdata(0),
I5 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^irpt_wrack_d1\,
I1 => Bus_RNW_reg,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\,
Q => \^p_3_in\(0),
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^p_3_in\(0),
I1 => \^p_1_in\(0),
I2 => \^p_0_in\(0),
O => IP2INTC_Irpt_i
);
intr2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr2bus_rdack0,
Q => intr2bus_rdack,
R => bus2ip_reset
);
intr2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => interrupt_wrce_strb,
Q => intr2bus_wrack,
R => bus2ip_reset
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FEEE"
)
port map (
I0 => ip2Bus_RdAck_intr_reg_hole,
I1 => intr2bus_rdack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"EFEE"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole,
I1 => intr2bus_wrack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_wrack_i
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\,
Q => \^p_1_in\(0),
R => bus2ip_reset
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\,
Q => \^p_0_in\(0),
R => bus2ip_reset
);
irpt_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_rdack,
Q => irpt_rdack_d1,
R => bus2ip_reset
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_wrack,
Q => \^irpt_wrack_d1\,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_GPIO_Core is
port (
ip2bus_data : out STD_LOGIC_VECTOR ( 19 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
GPIO_intr : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 19 downto 0 );
Read_Reg_Rst : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[19]_0\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[18]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[17]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[16]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[15]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[14]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[13]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[12]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[11]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[10]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[9]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[8]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[7]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[6]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[5]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[4]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[3]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[2]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[1]_0\ : in STD_LOGIC;
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_reset : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC_VECTOR ( 0 to 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 19 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_GPIO_Core : entity is "GPIO_Core";
end system_axi_gpio_0_0_GPIO_Core;
architecture STRUCTURE of system_axi_gpio_0_0_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_4_n_0\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[19]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 19 downto 0 );
signal gpio_data_in_xor : STD_LOGIC_VECTOR ( 0 to 19 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 19 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal or_ints : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_9_in : STD_LOGIC;
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
Q(19 downto 0) <= \^q\(19 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\,
I1 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[19]\,
I2 => p_17_in,
I3 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\,
I4 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_4_n_0\,
O => or_ints
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => p_12_in,
I1 => p_11_in,
I2 => p_14_in,
I3 => p_13_in,
I4 => p_15_in,
I5 => p_16_in,
O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
I1 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
I2 => p_2_in,
I3 => p_1_in,
I4 => p_3_in,
I5 => p_4_in,
O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => p_6_in,
I1 => p_5_in,
I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\,
I3 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\,
I4 => p_9_in,
I5 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\,
O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_4_n_0\
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => or_ints,
Q => GPIO_intr,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(0),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(10),
Q => p_9_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(11),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(12),
Q => p_11_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(13),
Q => p_12_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(14),
Q => p_13_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(15),
Q => p_14_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(16),
Q => p_15_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(17),
Q => p_16_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(18),
Q => p_17_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(19),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[19]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(1),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(2),
Q => p_1_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(3),
Q => p_2_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(4),
Q => p_3_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(5),
Q => p_4_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(6),
Q => p_5_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(7),
Q => p_6_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(8),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(9),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\,
R => bus2ip_reset
);
\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.system_axi_gpio_0_0_cdc_sync
port map (
D(19) => gpio_data_in_xor(0),
D(18) => gpio_data_in_xor(1),
D(17) => gpio_data_in_xor(2),
D(16) => gpio_data_in_xor(3),
D(15) => gpio_data_in_xor(4),
D(14) => gpio_data_in_xor(5),
D(13) => gpio_data_in_xor(6),
D(12) => gpio_data_in_xor(7),
D(11) => gpio_data_in_xor(8),
D(10) => gpio_data_in_xor(9),
D(9) => gpio_data_in_xor(10),
D(8) => gpio_data_in_xor(11),
D(7) => gpio_data_in_xor(12),
D(6) => gpio_data_in_xor(13),
D(5) => gpio_data_in_xor(14),
D(4) => gpio_data_in_xor(15),
D(3) => gpio_data_in_xor(16),
D(2) => gpio_data_in_xor(17),
D(1) => gpio_data_in_xor(18),
D(0) => gpio_data_in_xor(19),
Q(19 downto 0) => \^q\(19 downto 0),
gpio_io_i(19 downto 0) => gpio_io_i(19 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(19) => gpio_io_i_d2(0),
scndry_vect_out(18) => gpio_io_i_d2(1),
scndry_vect_out(17) => gpio_io_i_d2(2),
scndry_vect_out(16) => gpio_io_i_d2(3),
scndry_vect_out(15) => gpio_io_i_d2(4),
scndry_vect_out(14) => gpio_io_i_d2(5),
scndry_vect_out(13) => gpio_io_i_d2(6),
scndry_vect_out(12) => gpio_io_i_d2(7),
scndry_vect_out(11) => gpio_io_i_d2(8),
scndry_vect_out(10) => gpio_io_i_d2(9),
scndry_vect_out(9) => gpio_io_i_d2(10),
scndry_vect_out(8) => gpio_io_i_d2(11),
scndry_vect_out(7) => gpio_io_i_d2(12),
scndry_vect_out(6) => gpio_io_i_d2(13),
scndry_vect_out(5) => gpio_io_i_d2(14),
scndry_vect_out(4) => gpio_io_i_d2(15),
scndry_vect_out(3) => gpio_io_i_d2(16),
scndry_vect_out(2) => gpio_io_i_d2(17),
scndry_vect_out(1) => gpio_io_i_d2(18),
scndry_vect_out(0) => gpio_io_i_d2(19)
);
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus_i(0),
Q => ip2bus_data(19),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[10]_0\,
Q => ip2bus_data(9),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[11]_0\,
Q => ip2bus_data(8),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[12]_0\,
Q => ip2bus_data(7),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[13]_0\,
Q => ip2bus_data(6),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[14]_0\,
Q => ip2bus_data(5),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[15]_0\,
Q => ip2bus_data(4),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[16]_0\,
Q => ip2bus_data(3),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[17]_0\,
Q => ip2bus_data(2),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[18]_0\,
Q => ip2bus_data(1),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[19]_0\,
Q => ip2bus_data(0),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[1]_0\,
Q => ip2bus_data(18),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[2]_0\,
Q => ip2bus_data(17),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[3]_0\,
Q => ip2bus_data(16),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[4]_0\,
Q => ip2bus_data(15),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[5]_0\,
Q => ip2bus_data(14),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[6]_0\,
Q => ip2bus_data(13),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[7]_0\,
Q => ip2bus_data(12),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[8]_0\,
Q => ip2bus_data(11),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[9]_0\,
Q => ip2bus_data(10),
R => Read_Reg_Rst
);
\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \^q\(19),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(10),
Q => \^q\(9),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(11),
Q => \^q\(8),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(12),
Q => \^q\(7),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(13),
Q => \^q\(6),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(14),
Q => \^q\(5),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(15),
Q => \^q\(4),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(16),
Q => \^q\(3),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(17),
Q => \^q\(2),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(18),
Q => \^q\(1),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(19),
Q => \^q\(0),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \^q\(18),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \^q\(17),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \^q\(16),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(4),
Q => \^q\(15),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(5),
Q => \^q\(14),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(6),
Q => \^q\(13),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(7),
Q => \^q\(12),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(8),
Q => \^q\(11),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(9),
Q => \^q\(10),
R => '0'
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(19),
Q => gpio_io_o(19),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(9),
Q => gpio_io_o(9),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(8),
Q => gpio_io_o(8),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(7),
Q => gpio_io_o(7),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(6),
Q => gpio_io_o(6),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(5),
Q => gpio_io_o(5),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => gpio_io_o(4),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => gpio_io_o(3),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => gpio_io_o(2),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => gpio_io_o(1),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => gpio_io_o(0),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(18),
Q => gpio_io_o(18),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(17),
Q => gpio_io_o(17),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(16),
Q => gpio_io_o(16),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(15),
Q => gpio_io_o(15),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(14),
Q => gpio_io_o(14),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(13),
Q => gpio_io_o(13),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(12),
Q => gpio_io_o(12),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(11),
Q => gpio_io_o(11),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(10),
Q => gpio_io_o(10),
R => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(19),
Q => gpio_io_t(19),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(9),
Q => gpio_io_t(9),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(8),
Q => gpio_io_t(8),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(7),
Q => gpio_io_t(7),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(6),
Q => gpio_io_t(6),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(5),
Q => gpio_io_t(5),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(4),
Q => gpio_io_t(4),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(3),
Q => gpio_io_t(3),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(2),
Q => gpio_io_t(2),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(1),
Q => gpio_io_t(1),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(0),
Q => gpio_io_t(0),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(18),
Q => gpio_io_t(18),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(17),
Q => gpio_io_t(17),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(16),
Q => gpio_io_t(16),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(15),
Q => gpio_io_t(15),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(14),
Q => gpio_io_t(14),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(13),
Q => gpio_io_t(13),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(12),
Q => gpio_io_t(12),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(11),
Q => gpio_io_t(11),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(10),
Q => gpio_io_t(10),
S => bus2ip_reset
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => bus2ip_reset
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => \^gpio_xferack_reg\,
I1 => \^gpio_xferack_i\,
I2 => bus2ip_cs(0),
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_slave_attachment is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[19]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 19 downto 0 );
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 20 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 19 downto 0 );
Q : in STD_LOGIC_VECTOR ( 19 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_1\ : in STD_LOGIC_VECTOR ( 20 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_slave_attachment : entity is "slave_attachment";
end system_axi_gpio_0_0_slave_attachment;
architecture STRUCTURE of system_axi_gpio_0_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_oe_reg[0]\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 8 downto 2 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair12";
begin
\Not_Dual.gpio_OE_reg[0]\ <= \^not_dual.gpio_oe_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.system_axi_gpio_0_0_address_decoder
port map (
D(19 downto 0) => D(19 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\ => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\ => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\ => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\ => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\ => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\ => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\,
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\ => \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\,
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\ => \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\,
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\ => \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\,
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\ => \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\ => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\ => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\ => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\ => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\ => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\ => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\ => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\ => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\ => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\,
\Not_Dual.gpio_Data_In_reg[0]\(19 downto 0) => Q(19 downto 0),
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[19]\ => \Not_Dual.gpio_Data_Out_reg[19]\,
Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
\bus2ip_addr_i_reg[8]\(6) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(5) => bus2ip_addr(1),
\bus2ip_addr_i_reg[8]\(4) => bus2ip_addr(2),
\bus2ip_addr_i_reg[8]\(3) => bus2ip_addr(3),
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(4),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg => \^not_dual.gpio_oe_reg[0]\,
gpio_io_t(19 downto 0) => gpio_io_t(19 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => \ip2bus_data_i_D1_reg[0]\,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(1 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]_0\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
start2 => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(0),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(0),
O => \p_1_in__0\(2)
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(1),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(1),
O => \p_1_in__0\(3)
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(2),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \p_1_in__0\(4)
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(3),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(3),
O => \p_1_in__0\(5)
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(4),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(4),
O => \p_1_in__0\(6)
);
\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(5),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(5),
O => \p_1_in__0\(7)
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(6),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(6),
O => \p_1_in__0\(8)
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(2),
Q => bus2ip_addr(6),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(3),
Q => bus2ip_addr(5),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(4),
Q => bus2ip_addr(4),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(5),
Q => bus2ip_addr(3),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(6),
Q => bus2ip_addr(2),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(7),
Q => bus2ip_addr(1),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(8),
Q => bus2ip_addr(0),
R => bus2ip_reset
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_oe_reg[0]\,
R => bus2ip_reset
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state[1]_i_2_n_0\,
I2 => state(1),
I3 => state(0),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => bus2ip_reset
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10000000"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => s_axi_wvalid,
I3 => s_axi_awvalid,
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => state(1),
I5 => state(0),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => bus2ip_reset
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => bus2ip_reset
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(0),
Q => s_axi_rdata(0),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(10),
Q => s_axi_rdata(10),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(11),
Q => s_axi_rdata(11),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(12),
Q => s_axi_rdata(12),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(13),
Q => s_axi_rdata(13),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(14),
Q => s_axi_rdata(14),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(15),
Q => s_axi_rdata(15),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(16),
Q => s_axi_rdata(16),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(17),
Q => s_axi_rdata(17),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(18),
Q => s_axi_rdata(18),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(19),
Q => s_axi_rdata(19),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(1),
Q => s_axi_rdata(1),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(2),
Q => s_axi_rdata(2),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(20),
Q => s_axi_rdata(20),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(3),
Q => s_axi_rdata(3),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(4),
Q => s_axi_rdata(4),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(5),
Q => s_axi_rdata(5),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(6),
Q => s_axi_rdata(6),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(7),
Q => s_axi_rdata(7),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(8),
Q => s_axi_rdata(8),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(9),
Q => s_axi_rdata(9),
R => bus2ip_reset
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => bus2ip_reset
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => bus2ip_reset
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFFAACC"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_arvalid,
I2 => \state[1]_i_2_n_0\,
I3 => state(1),
I4 => state(0),
O => \p_0_out__0\(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E2E2E2ECCCCFFCC"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(1),
I2 => \state[1]_i_2_n_0\,
I3 => \state[1]_i_3_n_0\,
I4 => s_axi_arvalid,
I5 => state(0),
O => \p_0_out__0\(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(0),
Q => state(0),
R => bus2ip_reset
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(1),
Q => state(1),
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_axi_lite_ipif is
port (
p_8_in : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 19 downto 0 );
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 20 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 19 downto 0 );
Q : in STD_LOGIC_VECTOR ( 19 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_gpio_0_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_gpio_0_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_gpio_0_0_slave_attachment
port map (
D(19 downto 0) => D(19 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\ => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\ => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\ => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\ => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\ => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\ => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\,
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\ => \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\,
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\ => \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\,
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\ => \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\,
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\ => \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\ => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\ => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\ => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\ => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\ => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\ => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\ => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\ => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\ => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[19]\ => bus2ip_cs(0),
\Not_Dual.gpio_OE_reg[0]\ => bus2ip_rnw,
Q(19 downto 0) => Q(19 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_reset => bus2ip_reset,
gpio_io_t(19 downto 0) => gpio_io_t(19 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => p_8_in,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]\(1 downto 0),
\ip2bus_data_i_D1_reg[0]_1\(20 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(20 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => Bus_RNW_reg,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(20 downto 0) => s_axi_rdata(20 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 19 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_gpio_0_0_axi_gpio : entity is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of system_axi_gpio_0_0_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of system_axi_gpio_0_0_axi_gpio : entity is 20;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of system_axi_gpio_0_0_axi_gpio : entity is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_gpio_0_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_gpio_0_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of system_axi_gpio_0_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of system_axi_gpio_0_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_0_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of system_axi_gpio_0_0_axi_gpio : entity is "LOGICORE";
end system_axi_gpio_0_0_axi_gpio;
architecture STRUCTURE of system_axi_gpio_0_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_28 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_30 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_33 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_34 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_35 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_36 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_37 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_38 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_39 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_40 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_41 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_42 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_43 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_44 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_45 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_46 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_48 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_49 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_57 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_59 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_61 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_62 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 19 );
signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 12 to 12 );
signal GPIO_intr : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal IP2INTC_Irpt_i : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\ : STD_LOGIC;
signal Read_Reg_Rst : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC_VECTOR ( 1 to 1 );
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_reset_i_1_n_0 : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 19 );
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 19 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal interrupt_wrce_strb : STD_LOGIC;
signal intr2bus_rdack0 : STD_LOGIC;
signal intr_rd_ce_or_reduce : STD_LOGIC;
signal intr_wr_ce_or_reduce : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 12 to 31 );
signal ip2bus_data_i : STD_LOGIC_VECTOR ( 31 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal irpt_rdack : STD_LOGIC;
signal irpt_rdack_d1 : STD_LOGIC;
signal irpt_wrack : STD_LOGIC;
signal irpt_wrack_d1 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 31 to 31 );
signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_3_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of \INTR_CTRLR_GEN.ip2intc_irpt_reg\ : label is "INTR_LEVEL_HIGH";
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
gpio_io_t(19 downto 0) <= \^gpio_io_t\(19 downto 0);
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(31);
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19 downto 0) <= \^s_axi_rdata\(19 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.system_axi_gpio_0_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(19) => DBus_Reg(0),
D(18) => DBus_Reg(1),
D(17) => DBus_Reg(2),
D(16) => DBus_Reg(3),
D(15) => DBus_Reg(4),
D(14) => DBus_Reg(5),
D(13) => DBus_Reg(6),
D(12) => DBus_Reg(7),
D(11) => DBus_Reg(8),
D(10) => DBus_Reg(9),
D(9) => DBus_Reg(10),
D(8) => DBus_Reg(11),
D(7) => DBus_Reg(12),
D(6) => DBus_Reg(13),
D(5) => DBus_Reg(14),
D(4) => DBus_Reg(15),
D(3) => DBus_Reg(16),
D(2) => DBus_Reg(17),
D(1) => DBus_Reg(18),
D(0) => DBus_Reg(19),
E(0) => AXI_LITE_IPIF_I_n_48,
GPIO_DBus_i(0) => GPIO_DBus_i(12),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_57,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_59,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\ => AXI_LITE_IPIF_I_n_37,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\ => AXI_LITE_IPIF_I_n_36,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_35,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\ => AXI_LITE_IPIF_I_n_34,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\ => AXI_LITE_IPIF_I_n_33,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\ => AXI_LITE_IPIF_I_n_32,
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\ => AXI_LITE_IPIF_I_n_31,
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\ => AXI_LITE_IPIF_I_n_30,
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_29,
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_28,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\ => AXI_LITE_IPIF_I_n_46,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\ => AXI_LITE_IPIF_I_n_45,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\ => AXI_LITE_IPIF_I_n_44,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\ => AXI_LITE_IPIF_I_n_43,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\ => AXI_LITE_IPIF_I_n_42,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\ => AXI_LITE_IPIF_I_n_41,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\ => AXI_LITE_IPIF_I_n_40,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\ => AXI_LITE_IPIF_I_n_39,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\ => AXI_LITE_IPIF_I_n_38,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_49,
Q(19) => gpio_Data_In(0),
Q(18) => gpio_Data_In(1),
Q(17) => gpio_Data_In(2),
Q(16) => gpio_Data_In(3),
Q(15) => gpio_Data_In(4),
Q(14) => gpio_Data_In(5),
Q(13) => gpio_Data_In(6),
Q(12) => gpio_Data_In(7),
Q(11) => gpio_Data_In(8),
Q(10) => gpio_Data_In(9),
Q(9) => gpio_Data_In(10),
Q(8) => gpio_Data_In(11),
Q(7) => gpio_Data_In(12),
Q(6) => gpio_Data_In(13),
Q(5) => gpio_Data_In(14),
Q(4) => gpio_Data_In(15),
Q(3) => gpio_Data_In(16),
Q(2) => gpio_Data_In(17),
Q(1) => gpio_Data_In(18),
Q(0) => gpio_Data_In(19),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_io_t(19 downto 0) => \^gpio_io_t\(19 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(31),
\ip2bus_data_i_D1_reg[0]\(1) => p_0_out(0),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i(31),
\ip2bus_data_i_D1_reg[0]_0\(20) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]_0\(19) => ip2bus_data_i_D1(12),
\ip2bus_data_i_D1_reg[0]_0\(18) => ip2bus_data_i_D1(13),
\ip2bus_data_i_D1_reg[0]_0\(17) => ip2bus_data_i_D1(14),
\ip2bus_data_i_D1_reg[0]_0\(16) => ip2bus_data_i_D1(15),
\ip2bus_data_i_D1_reg[0]_0\(15) => ip2bus_data_i_D1(16),
\ip2bus_data_i_D1_reg[0]_0\(14) => ip2bus_data_i_D1(17),
\ip2bus_data_i_D1_reg[0]_0\(13) => ip2bus_data_i_D1(18),
\ip2bus_data_i_D1_reg[0]_0\(12) => ip2bus_data_i_D1(19),
\ip2bus_data_i_D1_reg[0]_0\(11) => ip2bus_data_i_D1(20),
\ip2bus_data_i_D1_reg[0]_0\(10) => ip2bus_data_i_D1(21),
\ip2bus_data_i_D1_reg[0]_0\(9) => ip2bus_data_i_D1(22),
\ip2bus_data_i_D1_reg[0]_0\(8) => ip2bus_data_i_D1(23),
\ip2bus_data_i_D1_reg[0]_0\(7) => ip2bus_data_i_D1(24),
\ip2bus_data_i_D1_reg[0]_0\(6) => ip2bus_data_i_D1(25),
\ip2bus_data_i_D1_reg[0]_0\(5) => ip2bus_data_i_D1(26),
\ip2bus_data_i_D1_reg[0]_0\(4) => ip2bus_data_i_D1(27),
\ip2bus_data_i_D1_reg[0]_0\(3) => ip2bus_data_i_D1(28),
\ip2bus_data_i_D1_reg[0]_0\(2) => ip2bus_data_i_D1(29),
\ip2bus_data_i_D1_reg[0]_0\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]_0\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => AXI_LITE_IPIF_I_n_61,
ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_62,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(20) => \^s_axi_rdata\(31),
s_axi_rdata(19 downto 0) => \^s_axi_rdata\(19 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I\: entity work.system_axi_gpio_0_0_interrupt_control
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ => AXI_LITE_IPIF_I_n_62,
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ => AXI_LITE_IPIF_I_n_61,
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
IP2INTC_Irpt_i => IP2INTC_Irpt_i,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole,
ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i => ip2bus_wrack_i,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(0) => s_axi_wdata(0)
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_rd_ce_or_reduce,
Q => ip2Bus_RdAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_57,
Q => ip2Bus_RdAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_wr_ce_or_reduce,
Q => ip2Bus_WrAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_59,
Q => ip2Bus_WrAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2INTC_Irpt_i,
Q => ip2intc_irpt,
R => bus2ip_reset
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
bus2ip_reset_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => bus2ip_reset_i_1_n_0
);
bus2ip_reset_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset_i_1_n_0,
Q => bus2ip_reset,
R => '0'
);
gpio_core_1: entity work.system_axi_gpio_0_0_GPIO_Core
port map (
D(19) => DBus_Reg(0),
D(18) => DBus_Reg(1),
D(17) => DBus_Reg(2),
D(16) => DBus_Reg(3),
D(15) => DBus_Reg(4),
D(14) => DBus_Reg(5),
D(13) => DBus_Reg(6),
D(12) => DBus_Reg(7),
D(11) => DBus_Reg(8),
D(10) => DBus_Reg(9),
D(9) => DBus_Reg(10),
D(8) => DBus_Reg(11),
D(7) => DBus_Reg(12),
D(6) => DBus_Reg(13),
D(5) => DBus_Reg(14),
D(4) => DBus_Reg(15),
D(3) => DBus_Reg(16),
D(2) => DBus_Reg(17),
D(1) => DBus_Reg(18),
D(0) => DBus_Reg(19),
E(0) => AXI_LITE_IPIF_I_n_49,
GPIO_DBus_i(0) => GPIO_DBus_i(12),
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.gpio_OE_reg[10]_0\ => AXI_LITE_IPIF_I_n_37,
\Not_Dual.gpio_OE_reg[11]_0\ => AXI_LITE_IPIF_I_n_36,
\Not_Dual.gpio_OE_reg[12]_0\ => AXI_LITE_IPIF_I_n_35,
\Not_Dual.gpio_OE_reg[13]_0\ => AXI_LITE_IPIF_I_n_34,
\Not_Dual.gpio_OE_reg[14]_0\ => AXI_LITE_IPIF_I_n_33,
\Not_Dual.gpio_OE_reg[15]_0\ => AXI_LITE_IPIF_I_n_32,
\Not_Dual.gpio_OE_reg[16]_0\ => AXI_LITE_IPIF_I_n_31,
\Not_Dual.gpio_OE_reg[17]_0\ => AXI_LITE_IPIF_I_n_30,
\Not_Dual.gpio_OE_reg[18]_0\ => AXI_LITE_IPIF_I_n_29,
\Not_Dual.gpio_OE_reg[19]_0\ => AXI_LITE_IPIF_I_n_28,
\Not_Dual.gpio_OE_reg[1]_0\ => AXI_LITE_IPIF_I_n_46,
\Not_Dual.gpio_OE_reg[2]_0\ => AXI_LITE_IPIF_I_n_45,
\Not_Dual.gpio_OE_reg[3]_0\ => AXI_LITE_IPIF_I_n_44,
\Not_Dual.gpio_OE_reg[4]_0\ => AXI_LITE_IPIF_I_n_43,
\Not_Dual.gpio_OE_reg[5]_0\ => AXI_LITE_IPIF_I_n_42,
\Not_Dual.gpio_OE_reg[6]_0\ => AXI_LITE_IPIF_I_n_41,
\Not_Dual.gpio_OE_reg[7]_0\ => AXI_LITE_IPIF_I_n_40,
\Not_Dual.gpio_OE_reg[8]_0\ => AXI_LITE_IPIF_I_n_39,
\Not_Dual.gpio_OE_reg[9]_0\ => AXI_LITE_IPIF_I_n_38,
Q(19) => gpio_Data_In(0),
Q(18) => gpio_Data_In(1),
Q(17) => gpio_Data_In(2),
Q(16) => gpio_Data_In(3),
Q(15) => gpio_Data_In(4),
Q(14) => gpio_Data_In(5),
Q(13) => gpio_Data_In(6),
Q(12) => gpio_Data_In(7),
Q(11) => gpio_Data_In(8),
Q(10) => gpio_Data_In(9),
Q(9) => gpio_Data_In(10),
Q(8) => gpio_Data_In(11),
Q(7) => gpio_Data_In(12),
Q(6) => gpio_Data_In(13),
Q(5) => gpio_Data_In(14),
Q(4) => gpio_Data_In(15),
Q(3) => gpio_Data_In(16),
Q(2) => gpio_Data_In(17),
Q(1) => gpio_Data_In(18),
Q(0) => gpio_Data_In(19),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_48,
gpio_io_i(19 downto 0) => gpio_io_i(19 downto 0),
gpio_io_o(19 downto 0) => gpio_io_o(19 downto 0),
gpio_io_t(19 downto 0) => \^gpio_io_t\(19 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_data(19) => ip2bus_data(12),
ip2bus_data(18) => ip2bus_data(13),
ip2bus_data(17) => ip2bus_data(14),
ip2bus_data(16) => ip2bus_data(15),
ip2bus_data(15) => ip2bus_data(16),
ip2bus_data(14) => ip2bus_data(17),
ip2bus_data(13) => ip2bus_data(18),
ip2bus_data(12) => ip2bus_data(19),
ip2bus_data(11) => ip2bus_data(20),
ip2bus_data(10) => ip2bus_data(21),
ip2bus_data(9) => ip2bus_data(22),
ip2bus_data(8) => ip2bus_data(23),
ip2bus_data(7) => ip2bus_data(24),
ip2bus_data(6) => ip2bus_data(25),
ip2bus_data(5) => ip2bus_data(26),
ip2bus_data(4) => ip2bus_data(27),
ip2bus_data(3) => ip2bus_data(28),
ip2bus_data(2) => ip2bus_data(29),
ip2bus_data(1) => ip2bus_data(30),
ip2bus_data(0) => ip2bus_data(31),
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(12),
Q => ip2bus_data_i_D1(12),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(13),
Q => ip2bus_data_i_D1(13),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(14),
Q => ip2bus_data_i_D1(14),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(15),
Q => ip2bus_data_i_D1(15),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(16),
Q => ip2bus_data_i_D1(16),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(17),
Q => ip2bus_data_i_D1(17),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(18),
Q => ip2bus_data_i_D1(18),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(19),
Q => ip2bus_data_i_D1(19),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(20),
Q => ip2bus_data_i_D1(20),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(21),
Q => ip2bus_data_i_D1(21),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(22),
Q => ip2bus_data_i_D1(22),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(23),
Q => ip2bus_data_i_D1(23),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_i(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_i,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_gpio_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_gpio_0_0 : entity is "system_axi_gpio_0_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_gpio_0_0 : entity is "axi_gpio,Vivado 2016.4";
end system_axi_gpio_0_0;
architecture STRUCTURE of system_axi_gpio_0_0 is
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 20;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.system_axi_gpio_0_0_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(19 downto 0) => gpio_io_i(19 downto 0),
gpio_io_o(19 downto 0) => gpio_io_o(19 downto 0),
gpio_io_t(19 downto 0) => gpio_io_t(19 downto 0),
ip2intc_irpt => ip2intc_irpt,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alias_extname_driving_signal is
port(
clk : in std_logic
);
end alias_extname_driving_signal;
architecture primary of alias_extname_driving_signal is
signal counter : unsigned(15 downto 0) := (others => '0');
begin
counter <= (counter + 1) when rising_edge(clk);
end architecture primary;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alias_tb is
end alias_tb;
architecture primary of alias_tb is
signal clk : std_logic := '0';
signal vector16 : unsigned(15 downto 0);
begin
clk <= not clk after 10 ns;
uut : entity work.alias_extname_driving_signal
port map(
clk => clk
);
blk: block
alias counter_alias is << signal .alias_tb.uut.counter : unsigned(15 downto 0) >>;
begin
vector16 <= counter_alias;
end block;
end architecture primary;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc158.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p19n01i00158pkg is
type rec_type is
record
a, b, c : integer;
end record;
procedure P1 (p : in rec_type; q: in integer; r: out integer);
end c04s03b02x02p19n01i00158pkg;
package body c04s03b02x02p19n01i00158pkg is
procedure P1 (p : in rec_type; q: in integer; r: out integer) is
begin
end P1;
end c04s03b02x02p19n01i00158pkg;
use work.c04s03b02x02p19n01i00158pkg.all;
ENTITY c04s03b02x02p19n01i00158ent IS
END c04s03b02x02p19n01i00158ent;
ARCHITECTURE c04s03b02x02p19n01i00158arch OF c04s03b02x02p19n01i00158ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 1;
BEGIN
P1 ((a => 1, b => 2, c => 3), q => 10, r => x); -- No_failure_here
P1 (p => (a => 1, b => 2, c => 3), q => 10, r => x); -- No_failure_here
P1 (p.a => 1, p.b => 2, p.c => 3, q => 10, r => x); -- No_failure_here
P1 (p => (1, 2, 3), q => 10, r => x); -- No_failure_here
assert FALSE
report "***PASSED TEST: c04s03b02x02p19n01i00158"
severity NOTE;
wait;
END PROCESS TESTING;
END c04s03b02x02p19n01i00158arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc158.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p19n01i00158pkg is
type rec_type is
record
a, b, c : integer;
end record;
procedure P1 (p : in rec_type; q: in integer; r: out integer);
end c04s03b02x02p19n01i00158pkg;
package body c04s03b02x02p19n01i00158pkg is
procedure P1 (p : in rec_type; q: in integer; r: out integer) is
begin
end P1;
end c04s03b02x02p19n01i00158pkg;
use work.c04s03b02x02p19n01i00158pkg.all;
ENTITY c04s03b02x02p19n01i00158ent IS
END c04s03b02x02p19n01i00158ent;
ARCHITECTURE c04s03b02x02p19n01i00158arch OF c04s03b02x02p19n01i00158ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 1;
BEGIN
P1 ((a => 1, b => 2, c => 3), q => 10, r => x); -- No_failure_here
P1 (p => (a => 1, b => 2, c => 3), q => 10, r => x); -- No_failure_here
P1 (p.a => 1, p.b => 2, p.c => 3, q => 10, r => x); -- No_failure_here
P1 (p => (1, 2, 3), q => 10, r => x); -- No_failure_here
assert FALSE
report "***PASSED TEST: c04s03b02x02p19n01i00158"
severity NOTE;
wait;
END PROCESS TESTING;
END c04s03b02x02p19n01i00158arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc158.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p19n01i00158pkg is
type rec_type is
record
a, b, c : integer;
end record;
procedure P1 (p : in rec_type; q: in integer; r: out integer);
end c04s03b02x02p19n01i00158pkg;
package body c04s03b02x02p19n01i00158pkg is
procedure P1 (p : in rec_type; q: in integer; r: out integer) is
begin
end P1;
end c04s03b02x02p19n01i00158pkg;
use work.c04s03b02x02p19n01i00158pkg.all;
ENTITY c04s03b02x02p19n01i00158ent IS
END c04s03b02x02p19n01i00158ent;
ARCHITECTURE c04s03b02x02p19n01i00158arch OF c04s03b02x02p19n01i00158ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 1;
BEGIN
P1 ((a => 1, b => 2, c => 3), q => 10, r => x); -- No_failure_here
P1 (p => (a => 1, b => 2, c => 3), q => 10, r => x); -- No_failure_here
P1 (p.a => 1, p.b => 2, p.c => 3, q => 10, r => x); -- No_failure_here
P1 (p => (1, 2, 3), q => 10, r => x); -- No_failure_here
assert FALSE
report "***PASSED TEST: c04s03b02x02p19n01i00158"
severity NOTE;
wait;
END PROCESS TESTING;
END c04s03b02x02p19n01i00158arch;
|
-- $Id: sys_conf_sim.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop_s3 (for test bench)
--
-- Dependencies: -
-- Tool versions: xst 11.4; ghdl 0.26
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-05 420 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec
-- to 60 cycles (1 usec). This affects the pulse generators (usec) and
-- mainly the autobauder. A break will be detected after 128 msec periods,
-- this in simulation after 128 usec or 6400 cycles. This is compatible with
-- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
constant sys_conf_clkdiv_usecdiv : integer := 12; -- shortened !
constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
|
-- $Id: sys_conf_sim.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop_s3 (for test bench)
--
-- Dependencies: -
-- Tool versions: xst 11.4; ghdl 0.26
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-05 420 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec
-- to 60 cycles (1 usec). This affects the pulse generators (usec) and
-- mainly the autobauder. A break will be detected after 128 msec periods,
-- this in simulation after 128 usec or 6400 cycles. This is compatible with
-- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
constant sys_conf_clkdiv_usecdiv : integer := 12; -- shortened !
constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
|
architecture RTL of FIFO is
function func1 return integer IS begin end function func1;
FUNCTION FUNC1 RETURN INTEGER IS BEGIN END FUNCTION FUNC1;
procedure proc1 Is begin end procedure proc1;
begin
end architecture RTL;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity full_adder is
port ( a, b, c_in : bit; s, c_out : out bit );
end entity full_adder;
architecture truth_table of full_adder is
begin
with bit_vector'(a, b, c_in) select
(c_out, s) <= bit_vector'("00") when "000",
bit_vector'("01") when "001",
bit_vector'("01") when "010",
bit_vector'("10") when "011",
bit_vector'("01") when "100",
bit_vector'("10") when "101",
bit_vector'("10") when "110",
bit_vector'("11") when "111";
end architecture truth_table;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity full_adder is
port ( a, b, c_in : bit; s, c_out : out bit );
end entity full_adder;
architecture truth_table of full_adder is
begin
with bit_vector'(a, b, c_in) select
(c_out, s) <= bit_vector'("00") when "000",
bit_vector'("01") when "001",
bit_vector'("01") when "010",
bit_vector'("10") when "011",
bit_vector'("01") when "100",
bit_vector'("10") when "101",
bit_vector'("10") when "110",
bit_vector'("11") when "111";
end architecture truth_table;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity full_adder is
port ( a, b, c_in : bit; s, c_out : out bit );
end entity full_adder;
architecture truth_table of full_adder is
begin
with bit_vector'(a, b, c_in) select
(c_out, s) <= bit_vector'("00") when "000",
bit_vector'("01") when "001",
bit_vector'("01") when "010",
bit_vector'("10") when "011",
bit_vector'("01") when "100",
bit_vector'("10") when "101",
bit_vector'("10") when "110",
bit_vector'("11") when "111";
end architecture truth_table;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:36 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_ov7670_controller_0_0 -prefix
-- system_ov7670_controller_0_0_ system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal taken : STD_LOGIC;
begin
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
xclk <= 'Z';
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shiftregG IS
GENERIC(N : POSITIVE := 8);
PORT(
clk,rst,set : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END ENTITY shiftregG;
Architecture behavior OF shiftregG IS
SIGNAL sint: STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN
shift : PROCESS (clk, rst, set)
BEGIN
IF rising_edge(clk) THEN
IF rst='1' THEN
sint <= (others=>'0');
ELSE
IF set = '1' THEN
sint <= din;
END IF;
END IF;
END IF;
END PROCESS shift;
dout <= sint;
END ARCHITECTURE behavior;
|
-------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity openMAC_DMAmaster is
generic(
simulate : boolean := false;
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
gen_rx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
tx_fifo_word_size_g : integer := 32;
rx_fifo_word_size_g : integer := 32;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end openMAC_DMAmaster;
architecture strct of openMAC_DMAmaster is
---- Component declarations -----
component dma_handler
generic(
dma_highadr_g : integer := 31;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_wr_clk : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_full : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_rd_clk : in std_logic;
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_rd : out std_logic;
dma_new_addr_wr : out std_logic;
dma_new_len : out std_logic;
dma_rd_err : out std_logic;
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_wr_err : out std_logic;
rx_aclr : out std_logic;
rx_wr_req : out std_logic;
tx_rd_req : out std_logic
);
end component;
component master_handler
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burst_wr_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_rd : in std_logic;
dma_new_addr_wr : in std_logic;
dma_new_len_rd : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
rx_rd_req : out std_logic;
tx_aclr : out std_logic;
tx_wr_req : out std_logic
);
end component;
---- Architecture declarations -----
--constants
constant tx_fifo_word_size_c : natural := natural(tx_fifo_word_size_g);
constant tx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(tx_fifo_word_size_c))));
constant rx_fifo_word_size_c : natural := natural(rx_fifo_word_size_g);
constant rx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(rx_fifo_word_size_c))));
---- Signal declarations used on the diagram ----
signal dma_new_addr_rd : std_logic;
signal dma_new_addr_wr : std_logic;
signal dma_new_rd_len : std_logic;
signal m_dma_new_addr_rd : std_logic;
signal m_dma_new_addr_wr : std_logic;
signal m_dma_new_rd_len : std_logic;
signal m_mac_rx_off : std_logic;
signal m_mac_tx_off : std_logic;
signal rx_aclr : std_logic;
signal rx_rd_clk : std_logic;
signal rx_rd_empty : std_logic;
signal rx_rd_full : std_logic;
signal rx_rd_req : std_logic;
signal rx_wr_clk : std_logic;
signal rx_wr_empty : std_logic;
signal rx_wr_full : std_logic;
signal rx_wr_req : std_logic;
signal rx_wr_req_s : std_logic;
signal tx_aclr : std_logic;
signal tx_rd_clk : std_logic;
signal tx_rd_empty : std_logic;
signal tx_rd_empty_s : std_logic;
signal tx_rd_empty_s_l : std_logic;
signal tx_rd_full : std_logic;
signal tx_rd_req : std_logic;
signal tx_rd_req_s : std_logic;
signal tx_rd_sel_word : std_logic;
signal tx_wr_clk : std_logic;
signal tx_wr_empty : std_logic;
signal tx_wr_full : std_logic;
signal tx_wr_req : std_logic;
signal dma_addr_trans : std_logic_vector (dma_highadr_g downto 1);
signal dma_rd_len_trans : std_logic_vector (11 downto 0);
signal rd_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rx_rd_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal rx_wr_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal tx_rd_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal tx_wr_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal wr_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal wr_data_s : std_logic_vector (fifo_data_width_g/2-1 downto 0);
begin
---- Component instantiations ----
THE_DMA_HANDLER : dma_handler
generic map (
dma_highadr_g => dma_highadr_g,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_ack_rd => dma_ack_rd,
dma_ack_wr => dma_ack_wr,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_addr_out => dma_addr_trans( dma_highadr_g downto 1 ),
dma_clk => dma_clk,
dma_new_addr_rd => dma_new_addr_rd,
dma_new_addr_wr => dma_new_addr_wr,
dma_new_len => dma_new_rd_len,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_rd_len_out => dma_rd_len_trans,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_rd,
dma_req_wr => dma_req_wr,
dma_wr_err => dma_wr_err,
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst,
rx_aclr => rx_aclr,
rx_wr_clk => rx_wr_clk,
rx_wr_empty => rx_wr_empty,
rx_wr_full => rx_wr_full,
rx_wr_req => rx_wr_req,
rx_wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_rd_clk => tx_rd_clk,
tx_rd_empty => tx_rd_empty,
tx_rd_full => tx_rd_full,
tx_rd_req => tx_rd_req,
tx_rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
THE_MASTER_HANDLER : master_handler
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
m_burst_wr_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount_width_g,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_addr_in => dma_addr_trans( dma_highadr_g downto 1 ),
dma_len_rd => dma_rd_len_trans,
dma_new_addr_rd => m_dma_new_addr_rd,
dma_new_addr_wr => m_dma_new_addr_wr,
dma_new_len_rd => m_dma_new_rd_len,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( fifo_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
mac_rx_off => m_mac_rx_off,
mac_tx_off => m_mac_tx_off,
rst => rst,
rx_rd_clk => rx_rd_clk,
rx_rd_empty => rx_rd_empty,
rx_rd_full => rx_rd_full,
rx_rd_req => rx_rd_req,
rx_rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_aclr => tx_aclr,
tx_wr_clk => tx_wr_clk,
tx_wr_empty => tx_wr_empty,
tx_wr_full => tx_wr_full,
tx_wr_req => tx_wr_req,
tx_wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
rx_rd_clk <= m_clk;
tx_rd_clk <= dma_clk;
rx_wr_clk <= dma_clk;
tx_wr_clk <= m_clk;
sync1 : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => mac_tx_off,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_mac_tx_off
);
sync2 : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => mac_rx_off,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_mac_rx_off
);
---- Generate statements ----
gen16bitFifo : if fifo_data_width_g = 16 generate
begin
txFifoGen : if gen_tx_fifo_g generate
begin
TX_FIFO_16 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => tx_fifo_word_size_c,
gSyncStages => 2,
gMemRes => "ON"
)
port map(
iAclr => tx_aclr,
iWrClk => tx_wr_clk,
iWrReq => tx_wr_req,
iWrData => m_readdata,
oWrEmpty => tx_wr_empty,
oWrFull => tx_wr_full,
oWrUsedw => tx_wr_usedw,
iRdClk => tx_rd_clk,
iRdReq => tx_rd_req,
oRdData => rd_data,
oRdEmpty => tx_rd_empty_s,
oRdFull => tx_rd_full,
oRdUsedw => tx_rd_usedw
);
tx_rd_empty_proc :
process(tx_aclr, tx_rd_clk)
begin
if tx_aclr = '1' then
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end process;
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
end generate txFifoGen;
rxFifoGen : if gen_rx_fifo_g generate
begin
RX_FIFO_16 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => rx_fifo_word_size_c,
gSyncStages => 2,
gMemRes => "ON"
)
port map(
iAclr => rx_aclr,
iWrClk => rx_wr_clk,
iWrReq => rx_wr_req,
iWrData => wr_data,
oWrEmpty => rx_wr_empty,
oWrFull => rx_wr_full,
oWrUsedw => rx_wr_usedw,
iRdClk => rx_rd_clk,
iRdReq => rx_rd_req,
oRdData => m_writedata,
oRdEmpty => rx_rd_empty,
oRdFull => rx_rd_full,
oRdUsedw => rx_rd_usedw
);
end generate rxFifoGen;
wr_data <= dma_dout;
dma_din <= rd_data;
end generate gen16bitFifo;
genRxAddrSync : if gen_rx_fifo_g generate
begin
sync4 : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => dma_new_addr_wr,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_dma_new_addr_wr
);
end generate genRxAddrSync;
genTxAddrSync : if gen_tx_fifo_g generate
begin
sync5 : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map(
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => dma_new_addr_rd,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_dma_new_addr_rd
);
sync6 : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map(
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => dma_new_rd_len,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_dma_new_rd_len
);
end generate genTxAddrSync;
gen32bitFifo : if fifo_data_width_g = 32 generate
begin
txFifoGen32 : if gen_tx_fifo_g generate
begin
TX_FIFO_32 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => tx_fifo_word_size_c,
gSyncStages => 2,
gMemRes => "ON"
)
port map(
iAclr => tx_aclr,
iWrClk => tx_wr_clk,
iWrReq => tx_wr_req,
iWrData => m_readdata,
oWrEmpty => tx_wr_empty,
oWrFull => tx_wr_full,
oWrUsedw => tx_wr_usedw,
iRdClk => tx_rd_clk,
iRdReq => tx_rd_req_s,
oRdData => rd_data,
oRdEmpty => tx_rd_empty_s,
oRdFull => tx_rd_full,
oRdUsedw => tx_rd_usedw
);
tx_rd_proc :
process (tx_rd_clk, rst)
begin
if rst = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_sel_word = '0' then
tx_rd_sel_word <= '1';
else
tx_rd_sel_word <= '0';
--workaround...
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end if;
end process;
tx_rd_req_s <= tx_rd_req when tx_rd_sel_word = '0' else '0';
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
dma_din <= rd_data(15 downto 0) when tx_rd_sel_word = '1' else
rd_data(31 downto 16);
end generate txFifoGen32;
rxFifoGen32 : if gen_rx_fifo_g generate
begin
RX_FIFO_32 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => rx_fifo_word_size_c,
gSyncStages => rx_fifo_word_size_log2_c,
gMemRes => "ON"
)
port map(
iAclr => rx_aclr,
iWrClk => rx_wr_clk,
iWrReq => rx_wr_req_s,
iWrData => wr_data,
oWrEmpty => rx_wr_empty,
oWrFull => rx_wr_full,
oWrUsedw => rx_wr_usedw,
iRdClk => rx_rd_clk,
iRdReq => rx_rd_req,
oRdData => m_writedata,
oRdEmpty => rx_rd_empty,
oRdFull => rx_rd_full,
oRdUsedw => rx_rd_usedw
);
rx_wr_proc :
process (rx_wr_clk, rst)
variable toggle : std_logic;
begin
if rst = '1' then
wr_data_s <= (others => '0');
toggle := '0';
rx_wr_req_s <= '0';
elsif rising_edge(rx_wr_clk) then
rx_wr_req_s <= '0';
if mac_rx_off = '1' then
if toggle = '1' then
rx_wr_req_s <= '1';
end if;
toggle := '0';
elsif rx_wr_req = '1' then
if toggle = '0' then
--capture data
wr_data_s <= dma_dout;
toggle := '1';
else
rx_wr_req_s <= '1';
toggle := '0';
end if;
end if;
end if;
end process;
wr_data <= dma_dout & wr_data_s;
end generate rxFifoGen32;
end generate gen32bitFifo;
end strct;
|
-- #################################################################################################
-- # << NEO430 - Data memory ("DMEM") >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_dmem is
generic (
DMEM_SIZE : natural := 2*1024 -- internal DMEM size in bytes
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic_vector(01 downto 0); -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end neo430_dmem;
architecture neo430_dmem_rtl of neo430_dmem is
-- local signals --
signal acc_en : std_ulogic;
signal rdata : std_ulogic_vector(15 downto 0);
signal rden : std_ulogic;
signal addr : integer;
-- RAM --
type dmem_file_t is array (0 to DMEM_SIZE/2-1) of std_ulogic_vector(7 downto 0);
signal dmem_file_l : dmem_file_t;
signal dmem_file_h : dmem_file_t;
-- RAM attribute to inhibit bypass-logic - Intel only! --
attribute ramstyle : string;
attribute ramstyle of dmem_file_l : signal is "no_rw_check";
attribute ramstyle of dmem_file_h : signal is "no_rw_check";
-- RAM attribute to inhibit bypass-logic - Lattice ICE40up only! --
attribute syn_ramstyle : string;
attribute syn_ramstyle of dmem_file_l : signal is "no_rw_check";
attribute syn_ramstyle of dmem_file_h : signal is "no_rw_check";
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i >= dmem_base_c) and (addr_i < std_ulogic_vector(unsigned(dmem_base_c) + DMEM_SIZE)) else '0';
addr <= to_integer(unsigned(addr_i(index_size_f(DMEM_SIZE/2) downto 1))); -- word aligned
-- Memory Access ------------------------------------------------------------
-- -----------------------------------------------------------------------------
dmem_file_access: process(clk_i)
begin
-- check max size --
if (DMEM_SIZE > dmem_max_size_c) then
assert false report "D-mem size out of range! Max 12kB!" severity error;
end if;
if rising_edge(clk_i) then
rden <= rden_i and acc_en;
if (acc_en = '1') then -- reduce switching activity when not accessed
if (wren_i(0) = '1') then -- write low byte
dmem_file_l(addr) <= data_i(07 downto 0);
end if;
rdata(07 downto 0) <= dmem_file_l(addr);
if (wren_i(1) = '1') then -- write high byte
dmem_file_h(addr) <= data_i(15 downto 8);
end if;
rdata(15 downto 8) <= dmem_file_h(addr);
end if;
end if;
end process dmem_file_access;
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
end neo430_dmem_rtl;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.