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entity implicit is
end entity;
architecture test of implicit is
signal x : integer;
begin
process is
begin
assert x'delayed = 4; -- OK
assert x'delayed(1 ns) = 5; -- OK
assert x'delayed(5) = 1; -- Error
assert x'stable; -- OK
assert x'stable(1 ns); -- OK
--assert x'delayed'stable(2 ns); -- OK
assert x'transaction = '1'; -- OK
assert x'quiet; -- OK
assert x'quiet(5 ns); -- OK
end process;
end architecture;
|
entity implicit is
end entity;
architecture test of implicit is
signal x : integer;
begin
process is
begin
assert x'delayed = 4; -- OK
assert x'delayed(1 ns) = 5; -- OK
assert x'delayed(5) = 1; -- Error
assert x'stable; -- OK
assert x'stable(1 ns); -- OK
--assert x'delayed'stable(2 ns); -- OK
assert x'transaction = '1'; -- OK
assert x'quiet; -- OK
assert x'quiet(5 ns); -- OK
end process;
end architecture;
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-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
package pp_types is
--! Type used for register addresses.
subtype register_address is std_logic_vector(4 downto 0);
--! The available ALU operations.
type alu_operation is (
ALU_AND, ALU_OR, ALU_XOR,
ALU_SLT, ALU_SLTU,
ALU_ADD, ALU_SUB,
ALU_SRL, ALU_SLL, ALU_SRA,
ALU_NOP, ALU_INVALID
);
--! Types of branches.
type branch_type is (
BRANCH_NONE, BRANCH_JUMP, BRANCH_JUMP_INDIRECT, BRANCH_CONDITIONAL, BRANCH_SRET
);
--! Source of an ALU operand.
type alu_operand_source is (
ALU_SRC_REG, ALU_SRC_IMM, ALU_SRC_SHAMT, ALU_SRC_PC, ALU_SRC_PC_NEXT, ALU_SRC_NULL, ALU_SRC_CSR
);
--! Type of memory operation:
type memory_operation_type is (
MEMOP_TYPE_NONE, MEMOP_TYPE_INVALID, MEMOP_TYPE_LOAD, MEMOP_TYPE_LOAD_UNSIGNED, MEMOP_TYPE_STORE
);
-- Determines if a memory operation is a load:
function memop_is_load(input : in memory_operation_type) return boolean;
--! Size of a memory operation:
type memory_operation_size is (
MEMOP_SIZE_BYTE, MEMOP_SIZE_HALFWORD, MEMOP_SIZE_WORD
);
--! Wishbone master output signals:
type wishbone_master_outputs is record
adr : std_logic_vector(31 downto 0);
sel : std_logic_vector( 3 downto 0);
cyc : std_logic;
stb : std_logic;
we : std_logic;
dat : std_logic_vector(31 downto 0);
end record;
--! Wishbone master input signals:
type wishbone_master_inputs is record
dat : std_logic_vector(31 downto 0);
ack : std_logic;
end record;
--! State of the currently running test:
type test_state is (TEST_IDLE, TEST_RUNNING, TEST_FAILED, TEST_PASSED);
--! Current test context:
type test_context is record
state : test_state;
number : std_logic_vector(29 downto 0);
end record;
--! Converts a test context to an std_logic_vector:
function test_context_to_std_logic(input : in test_context) return std_logic_vector;
--! Converts an std_logic_vector to a test context:
function std_logic_to_test_context(input : in std_logic_vector(31 downto 0)) return test_context;
end package pp_types;
package body pp_types is
function memop_is_load(input : in memory_operation_type) return boolean is
begin
return (input = MEMOP_TYPE_LOAD or input = MEMOP_TYPE_LOAD_UNSIGNED);
end function memop_is_load;
function test_context_to_std_logic(input : in test_context) return std_logic_vector is
variable retval : std_logic_vector(31 downto 0);
begin
case input.state is
when TEST_IDLE =>
retval(1 downto 0) := b"00";
when TEST_RUNNING =>
retval(1 downto 0) := b"01";
when TEST_FAILED =>
retval(1 downto 0) := b"10";
when TEST_PASSED =>
retval(1 downto 0) := b"11";
end case;
retval(31 downto 2) := input.number;
return retval;
end function test_context_to_std_logic;
function std_logic_to_test_context(input : in std_logic_vector(31 downto 0)) return test_context is
variable retval : test_context;
begin
case input(1 downto 0) is
when b"00" =>
retval.state := TEST_IDLE;
when b"01" =>
retval.state := TEST_RUNNING;
when b"10" =>
retval.state := TEST_FAILED;
when b"11" =>
retval.state := TEST_PASSED;
when others =>
retval.state := TEST_FAILED;
end case;
retval.number := input(31 downto 2);
return retval;
end function std_logic_to_test_context;
end package body pp_types;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function CX_GEN(current_address, network_x, network_y : integer) return integer;
procedure NI_control(network_x, network_y, frame_length, current_address, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time;
signal clk: in std_logic;
-- NI configuration
signal reserved_address : in std_logic_vector(29 downto 0); -- reserved address for sending data to VC 0
signal reserved_address_vc : in std_logic_vector(29 downto 0); -- reserved address for sending data to VC 1
signal flag_address : in std_logic_vector(29 downto 0) ; -- reserved address for the memory mapped I/O
signal counter_address : in std_logic_vector(29 downto 0);
signal reconfiguration_address : in std_logic_vector(29 downto 0); -- reserved address for reconfiguration register
-- NI signals
signal enable: out std_logic;
signal write_byte_enable: out std_logic_vector(3 downto 0);
signal address: out std_logic_vector(31 downto 2);
signal data_write: out std_logic_vector(31 downto 0);
signal data_read: in std_logic_vector(31 downto 0);
signal test: out std_logic_vector(31 downto 0));
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function CX_GEN(current_address, network_x, network_y: integer) return integer is
variable X, Y : integer := 0;
variable CN, CE, CW, CS : std_logic := '0';
variable CX : std_logic_vector(3 downto 0);
begin
X := current_address mod network_x;
Y := current_address / network_x;
if X /= 0 then
CW := '1';
end if;
if X /= network_x-1 then
CE := '1';
end if;
if Y /= 0 then
CN := '1';
end if;
if Y /= network_y-1 then
CS := '1';
end if;
CX := CS&CW&CE&CN;
return to_integer(unsigned(CX));
end CX_GEN;
procedure NI_control(network_x, network_y, frame_length, current_address, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time;
signal clk: in std_logic;
-- NI configuration
signal reserved_address : in std_logic_vector(29 downto 0);
signal reserved_address_vc : in std_logic_vector(29 downto 0);
signal flag_address : in std_logic_vector(29 downto 0) ; -- reserved address for the memory mapped I/O
signal counter_address : in std_logic_vector(29 downto 0);
signal reconfiguration_address : in std_logic_vector(29 downto 0); -- reserved address for reconfiguration register
-- NI signals
signal enable: out std_logic;
signal write_byte_enable: out std_logic_vector(3 downto 0);
signal address: out std_logic_vector(31 downto 2);
signal data_write: out std_logic_vector(31 downto 0);
signal data_read: in std_logic_vector(31 downto 0);
signal test: out std_logic_vector(31 downto 0)) is
-- variables for random functions
constant DATA_WIDTH : integer := 32;
variable seed1 :positive := current_address+1;
variable seed2 :positive := current_address+1;
variable rand : real ;
--file handling variables
variable SEND_LINEVARIABLE : line;
file SEND_FILE : text;
variable RECEIVED_LINEVARIABLE : line;
file RECEIVED_FILE : text;
-- receiving variables
variable receive_source_node, receive_destination_node, receive_packet_id, receive_counter, receive_packet_length: integer;
variable receive_source_node_vc, receive_destination_node_vc, receive_packet_id_vc, receive_counter_vc, receive_packet_length_vc: integer;
-- sending variables
variable send_destination_node, send_counter, send_id_counter: integer:= 0;
variable send_packet_length: integer:= 8;
type state_type is (Idle, Header_flit, Body_flit, Tail_flit);
variable state : state_type;
variable frame_starting_delay : integer:= 0;
variable frame_counter: integer:= 0;
variable first_packet : boolean := True;
variable vc: integer := 0; -- virtual channel selector
variable read_vc: integer := 0; -- virtual channel selector
begin
file_open(RECEIVED_FILE,"received.txt",WRITE_MODE);
file_open(SEND_FILE,"sent.txt",WRITE_MODE);
enable <= '1';
state := Idle;
send_packet_length := min_packet_size;
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - max_packet_size-1)))/100);
wait until clk'event and clk ='0';
address <= reconfiguration_address;
wait until clk'event and clk ='0';
write_byte_enable <= "1111";
data_write <= "00000000000000000000" & std_logic_vector(to_unsigned(CX_GEN(current_address, network_x, network_y), 4)) & std_logic_vector(to_unsigned(60, 8));
wait until clk'event and clk ='0';
write_byte_enable <= "0000";
data_write <= (others =>'0');
while true loop
-- read the flag status
address <= flag_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
--flag register is organized like this:
-- .-------------------------------------------------.
-- | N2P_empty | P2N_full | ...|
-- '-------------------------------------------------'
-- Note that VC 1 has higher priority to VC 0
if data_read(29) = '0' then -- N2P VC1 is not empty, can receive flit
-- set the address for VC1
address <= reserved_address_vc;
read_vc := 1;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then -- got header flit
receive_destination_node_vc := to_integer(unsigned(data_read(14 downto 8)))* network_x+to_integer(unsigned(data_read(7 downto 1)));
receive_source_node_vc :=to_integer(unsigned(data_read(21 downto 15)))* network_x+to_integer(unsigned(data_read(21 downto 15)));
receive_counter_vc := 1;
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then -- got body flit
if receive_counter_vc = 1 then
receive_packet_length_vc := to_integer(unsigned(data_read(28 downto 15)));
receive_packet_id_vc := to_integer(unsigned(data_read(14 downto 1)));
end if;
receive_counter_vc := receive_counter_vc + 1;
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then -- got tail flit
receive_counter_vc := receive_counter_vc +1;
write(RECEIVED_LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(receive_source_node_vc) & " to: " & integer'image(receive_destination_node_vc) & " length: "& integer'image(receive_packet_length_vc) & " actual length: "& integer'image(receive_counter_vc) & " id: "& integer'image(receive_packet_id_vc)& " VC: "& integer'image(read_vc));
writeline(RECEIVED_FILE, RECEIVED_LINEVARIABLE);
end if;
elsif data_read(31) = '0' then -- N2P VC0 is not empty, can receive flit
-- set the address for VC0
address <= reserved_address;
read_vc := 0;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then -- got header flit
receive_destination_node := to_integer(unsigned(data_read(14 downto 8)))* network_x+to_integer(unsigned(data_read(7 downto 1)));
receive_source_node :=to_integer(unsigned(data_read(21 downto 15)))* network_x+to_integer(unsigned(data_read(21 downto 15)));
receive_counter := 1;
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then -- got body flit
if receive_counter = 1 then
receive_packet_length := to_integer(unsigned(data_read(28 downto 15)));
receive_packet_id := to_integer(unsigned(data_read(14 downto 1)));
end if;
receive_counter := receive_counter+1;
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then -- got tail flit
receive_counter := receive_counter+1;
write(RECEIVED_LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(receive_source_node) & " to: " & integer'image(receive_destination_node) & " length: "& integer'image(receive_packet_length) & " actual length: "& integer'image(receive_counter) & " id: "& integer'image(receive_packet_id)& " VC: "& integer'image(read_vc));
writeline(RECEIVED_FILE, RECEIVED_LINEVARIABLE);
end if;
elsif data_read(30) = '0' then -- P2N is not full, can send flit
if frame_counter >= frame_starting_delay then
if state = Idle and now < finish_time then
if frame_counter < frame_starting_delay+1 then
state := Header_flit;
send_counter := send_counter+1;
-- generating the destination address
uniform(seed1, seed2, rand);
send_destination_node := integer(rand*real((network_x*network_y)-1));
while (send_destination_node = current_address) loop
uniform(seed1, seed2, rand);
send_destination_node := integer(rand*real((network_x*network_y)-1));
end loop;
uniform(seed1, seed2, rand);
vc := integer(rand*real(1));
-- this is the header flit
if vc = 1 then
address <= reserved_address_vc;
write_byte_enable <= "1111";
-- if you want to write into VC1 you should write "00000000000001" into the sender part! (since the NI sets the source address automatically, the source address field can be used for selecting VC)
data_write <= "0000" & "00000000000001" & std_logic_vector(to_unsigned(send_destination_node/network_x, 7)) & std_logic_vector(to_unsigned(send_destination_node mod network_x, 7));
else
address <= reserved_address;
write_byte_enable <= "1111";
data_write <= "0000" & "00000000000000" & std_logic_vector(to_unsigned(send_destination_node/network_x, 7)) & std_logic_vector(to_unsigned(send_destination_node mod network_x, 7));
end if;
write(SEND_LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(current_address) & " to " & integer'image(send_destination_node) & " with length: "& integer'image(send_packet_length) & " id: " & integer'image(send_id_counter) & " VC: " & integer'image(vc));
writeline(SEND_FILE, SEND_LINEVARIABLE);
else
state := Idle;
end if;
elsif state = Header_flit then
--generating the packet length
uniform(seed1, seed2, rand);
send_packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (send_packet_length < min_packet_size) then
send_packet_length:=min_packet_size;
end if;
if (send_packet_length > max_packet_size) then
send_packet_length:=max_packet_size;
end if;
if vc = 1 then
address <= reserved_address_vc;
else
address <= reserved_address;
end if;
write_byte_enable <= "1111";
-- first body flit
if first_packet = True then
data_write <= "0000" & std_logic_vector(to_unsigned(send_packet_length, 14)) & std_logic_vector(to_unsigned(send_id_counter, 14));
else
data_write <= "0000" & std_logic_vector(to_unsigned(send_packet_length, 14)) & std_logic_vector(to_unsigned(send_id_counter, 14));
end if;
send_counter := send_counter+1;
state := Body_flit;
elsif state = Body_flit then
-- rest of body flits
if vc = 1 then
address <= reserved_address_vc;
else
address <= reserved_address;
end if;
write_byte_enable <= "1111";
uniform(seed1, seed2, rand);
data_write <= "0000" & std_logic_vector(to_unsigned(integer(rand*1000.0), 28));
send_counter := send_counter+1;
if send_counter = send_packet_length-1 then
state := Tail_flit;
else
state := Body_flit;
end if;
elsif state = Tail_flit then
-- tail flit
if vc = 1 then
address <= reserved_address_vc;
else
address <= reserved_address;
end if;
write_byte_enable <= "1111";
if first_packet = True then
data_write <= "0000" & "0000000000000000000000000000";
first_packet := False;
else
uniform(seed1, seed2, rand);
data_write <= "0000" & std_logic_vector(to_unsigned(integer(rand*1000.0), 28));
end if;
send_counter := 0;
state := Idle;
-- updating the id counter!
send_id_counter := send_id_counter + 1;
if send_id_counter = 16384 then
send_id_counter := 0;
end if;
end if;
end if;
frame_counter := frame_counter + 1;
if frame_counter = frame_length then
frame_counter := 0;
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - max_packet_size)))/100);
end if;
wait until clk'event and clk ='0';
end if;
end loop;
file_close(SEND_FILE);
file_close(RECEIVED_FILE);
end NI_control;
end TB_Package;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w16_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w16_d3_A_shiftReg;
architecture rtl of fifo_w16_d3_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w16_d3_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w16_d3_A is
component fifo_w16_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w16_d3_A_shiftReg : fifo_w16_d3_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Tests initialization of records with aggregate expressions.
-- (based on the vhdl_struct_array test)
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_record_elab is
port (
i_low0: in std_logic_vector (3 downto 0);
i_high0: in std_logic_vector (3 downto 0);
i_low1: in std_logic_vector (3 downto 0);
i_high1: in std_logic_vector (3 downto 0);
o_low0: out std_logic_vector (3 downto 0);
o_high0: out std_logic_vector (3 downto 0);
o_low1: out std_logic_vector (3 downto 0);
o_high1: out std_logic_vector (3 downto 0)
);
end vhdl_record_elab;
architecture test of vhdl_record_elab is
type word is record
high: std_logic_vector (3 downto 0);
low: std_logic_vector (3 downto 0);
end record;
type dword is array (1 downto 0) of word;
signal my_dword : dword;
signal dword_a : dword;
begin
-- inputs
my_dword(0) <= (low => i_low0, high => i_high0);
-- test if you can assign values in any order
my_dword(1) <= (high => i_high1, low => i_low1);
dword_a <= (0 => (low => "0110", high => "1001"),
1 => (high => "1100", low => "0011"));
-- outputs
o_low0 <= my_dword(0).low;
o_high0 <= my_dword(0).high;
o_low1 <= my_dword(1).low;
o_high1 <= my_dword(1).high;
end test;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Tests initialization of records with aggregate expressions.
-- (based on the vhdl_struct_array test)
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_record_elab is
port (
i_low0: in std_logic_vector (3 downto 0);
i_high0: in std_logic_vector (3 downto 0);
i_low1: in std_logic_vector (3 downto 0);
i_high1: in std_logic_vector (3 downto 0);
o_low0: out std_logic_vector (3 downto 0);
o_high0: out std_logic_vector (3 downto 0);
o_low1: out std_logic_vector (3 downto 0);
o_high1: out std_logic_vector (3 downto 0)
);
end vhdl_record_elab;
architecture test of vhdl_record_elab is
type word is record
high: std_logic_vector (3 downto 0);
low: std_logic_vector (3 downto 0);
end record;
type dword is array (1 downto 0) of word;
signal my_dword : dword;
signal dword_a : dword;
begin
-- inputs
my_dword(0) <= (low => i_low0, high => i_high0);
-- test if you can assign values in any order
my_dword(1) <= (high => i_high1, low => i_low1);
dword_a <= (0 => (low => "0110", high => "1001"),
1 => (high => "1100", low => "0011"));
-- outputs
o_low0 <= my_dword(0).low;
o_high0 <= my_dword(0).high;
o_low1 <= my_dword(1).low;
o_high1 <= my_dword(1).high;
end test;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Tests initialization of records with aggregate expressions.
-- (based on the vhdl_struct_array test)
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_record_elab is
port (
i_low0: in std_logic_vector (3 downto 0);
i_high0: in std_logic_vector (3 downto 0);
i_low1: in std_logic_vector (3 downto 0);
i_high1: in std_logic_vector (3 downto 0);
o_low0: out std_logic_vector (3 downto 0);
o_high0: out std_logic_vector (3 downto 0);
o_low1: out std_logic_vector (3 downto 0);
o_high1: out std_logic_vector (3 downto 0)
);
end vhdl_record_elab;
architecture test of vhdl_record_elab is
type word is record
high: std_logic_vector (3 downto 0);
low: std_logic_vector (3 downto 0);
end record;
type dword is array (1 downto 0) of word;
signal my_dword : dword;
signal dword_a : dword;
begin
-- inputs
my_dword(0) <= (low => i_low0, high => i_high0);
-- test if you can assign values in any order
my_dword(1) <= (high => i_high1, low => i_low1);
dword_a <= (0 => (low => "0110", high => "1001"),
1 => (high => "1100", low => "0011"));
-- outputs
o_low0 <= my_dword(0).low;
o_high0 <= my_dword(0).high;
o_low1 <= my_dword(1).low;
o_high1 <= my_dword(1).high;
end test;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_1;
USE fir_compiler_v7_1.fir_compiler_v7_1;
ENTITY fir_lp_15kHz IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END fir_lp_15kHz;
ARCHITECTURE fir_lp_15kHz_arch OF fir_lp_15kHz IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_lp_15kHz_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "fir_lp_15kHz",
C_COEF_FILE => "fir_lp_15kHz.mif",
C_COEF_FILE_LINES => 64,
C_FILTER_TYPE => 0,
C_INTERP_RATE => 1,
C_DECIM_RATE => 1,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 128,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 0,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "20,20,24",
C_OPTIMIZATION => 2046,
C_DATA_PATH_WIDTHS => "16",
C_DATA_IP_PATH_WIDTHS => "16",
C_DATA_PX_PATH_WIDTHS => "16",
C_DATA_WIDTH => 16,
C_COEF_PATH_WIDTHS => "19",
C_COEF_WIDTH => 19,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "1",
C_ACCUM_PATH_WIDTHS => "41",
C_OUTPUT_WIDTH => 41,
C_OUTPUT_PATH_WIDTHS => "41",
C_ACCUM_OP_PATH_WIDTHS => "41",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 64,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 1,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 0,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 0,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 80,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 16,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 48,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END fir_lp_15kHz_arch;
|
-------------------------------------------------------------------------------
-- Title : CLock
-- Project :
-------------------------------------------------------------------------------
-- File : disp.vhd
-- Author : Daniel Sun <dcsun88osh@gmail.com>
-- Company :
-- Created : 2016-05-14
-- Last update: 2018-04-21
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Display controller
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-14 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.types_pkg.all;
entity disp is
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
disp_ena : in std_logic;
disp_page : in std_logic_vector(7 downto 0);
disp_pdm : in std_logic_vector(7 downto 0);
stat_src : in std_logic_vector(3 downto 0);
stat : in std_logic_vector(15 downto 0);
-- Display memory
sram_addr : in std_logic_vector(9 downto 0);
sram_we : in std_logic;
sram_datao : in std_logic_vector(31 downto 0);
sram_datai : out std_logic_vector(31 downto 0);
-- Time of day
cur_time : in time_ty;
-- Output to tlc59282 LED driver
disp_sclk : OUT std_logic;
disp_blank : OUT std_logic;
disp_lat : OUT std_logic;
disp_sin : OUT std_logic;
disp_status : OUT std_logic
);
end disp;
architecture rtl of disp is
component disp_sr
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
disp_data : in std_logic_vector(255 downto 0);
disp_sclk : OUT std_logic;
disp_lat : OUT std_logic;
disp_sin : OUT std_logic
);
end component;
component disp_lut
port (
rst_n : in std_logic;
clk : in std_logic;
sram_addr : in std_logic_vector(9 downto 0);
sram_we : in std_logic;
sram_datao : in std_logic_vector(31 downto 0);
sram_datai : out std_logic_vector(31 downto 0);
lut_addr : in std_logic_vector(11 downto 0);
lut_data : out std_logic_vector(7 downto 0)
);
end component;
component disp_dark
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1ppus : in std_logic;
stat_src : in std_logic_vector(3 downto 0);
stat : in std_logic_vector(15 downto 0);
disp_pdm : in std_logic_vector(7 downto 0);
disp_blank : OUT std_logic;
disp_status : OUT std_logic
);
end component;
component disp_ctl
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1ppms : in std_logic;
disp_ena : in std_logic;
disp_page : in std_logic_vector(7 downto 0);
-- Time of day
cur_time : in time_ty;
-- Block memory display buffer and lut
lut_addr : out std_logic_vector(11 downto 0);
lut_data : in std_logic_vector(7 downto 0);
-- Segment driver data
disp_data : out std_logic_vector(255 downto 0)
);
end component;
SIGNAL disp_data : std_logic_vector(255 downto 0);
SIGNAL lut_addr : std_logic_vector(11 downto 0);
SIGNAL lut_data : std_logic_vector(7 downto 0);
begin
disp_sr_i : disp_sr
port map (
rst_n => rst_n,
clk => clk,
tsc_1pps => tsc_1pps,
tsc_1ppms => tsc_1ppms,
tsc_1ppus => tsc_1ppus,
disp_data => disp_data,
disp_sclk => disp_sclk,
disp_lat => disp_lat,
disp_sin => disp_sin
);
disp_lut_i : disp_lut
port map (
rst_n => rst_n,
clk => clk,
sram_addr => sram_addr,
sram_we => sram_we,
sram_datao => sram_datao,
sram_datai => sram_datai,
lut_addr => lut_addr,
lut_data => lut_data
);
disp_dark_i : disp_dark
port map (
rst_n => rst_n,
clk => clk,
tsc_1ppus => tsc_1ppus,
stat_src => stat_src,
stat => stat,
disp_pdm => disp_pdm,
disp_blank => disp_blank,
disp_status => disp_status
);
disp_ctl_i : disp_ctl
port map (
rst_n => rst_n,
clk => clk,
tsc_1ppms => tsc_1ppms,
disp_page => disp_page,
disp_ena => disp_ena,
-- Time of day
cur_time => cur_time,
-- Block memory display buffer and lut
lut_addr => lut_addr,
lut_data => lut_data,
-- Segment driver data
disp_data => disp_data
);
end rtl;
|
-------------------------------------------------------------------------------
-- system_ilmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b.all;
entity system_ilmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
attribute x_core_info : STRING;
attribute x_core_info of system_ilmb_wrapper : entity is "lmb_v10_v2_00_b";
end system_ilmb_wrapper;
architecture STRUCTURE of system_ilmb_wrapper is
component lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer;
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_EXT_RESET_HIGH : integer
);
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end component;
begin
ilmb : lmb_v10
generic map (
C_LMB_NUM_SLAVES => 1,
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
port map (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- system_ilmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b.all;
entity system_ilmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
attribute x_core_info : STRING;
attribute x_core_info of system_ilmb_wrapper : entity is "lmb_v10_v2_00_b";
end system_ilmb_wrapper;
architecture STRUCTURE of system_ilmb_wrapper is
component lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer;
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_EXT_RESET_HIGH : integer
);
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end component;
begin
ilmb : lmb_v10
generic map (
C_LMB_NUM_SLAVES => 1,
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
port map (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
end architecture STRUCTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 21 11:24:56 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.vhdl
-- Design : ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe13 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe14 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe15 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[7:0],probe8[63:0],probe9[31:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[7:0],probe14[63:0],probe15[31:0],probe16[0:0],probe17[0:0],probe18[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ambilight is
Port ( vidclk : in STD_LOGIC;
viddata_r : in STD_LOGIC_VECTOR (7 downto 0);
viddata_g : in STD_LOGIC_VECTOR (7 downto 0);
viddata_b : in STD_LOGIC_VECTOR (7 downto 0);
hblank : in STD_LOGIC;
vblank : in STD_LOGIC;
cfgclk : in STD_LOGIC;
cfgwe : in STD_LOGIC;
cfglight : in STD_LOGIC_VECTOR (7 downto 0);
cfgcomponent : in STD_LOGIC_VECTOR (3 downto 0);
cfgdatain : in STD_LOGIC_VECTOR (7 downto 0);
cfgdataout : out STD_LOGIC_VECTOR (7 downto 0);
output : out STD_LOGIC_VECTOR(7 downto 0));
end ambilight;
architecture Behavioral of ambilight is
COMPONENT configRam
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
signal ce2 : std_logic;
signal ce4 : std_logic;
signal hblank_delayed : std_logic;
signal vblank_delayed : std_logic;
signal ravg : std_logic_vector(7 downto 0);
signal gavg : std_logic_vector(7 downto 0);
signal bavg : std_logic_vector(7 downto 0);
signal lineBufferAddr : std_logic_vector(6 downto 0);
signal lineBufferData : std_logic_vector(23 downto 0);
signal yPos : std_logic_vector(5 downto 0);
signal lineReady : std_logic;
signal configAddrA : std_logic_vector(8 downto 0);
signal configDataA : std_logic_vector(31 downto 0);
signal configWeB : std_logic_vector(0 downto 0);
signal configAddrB : std_logic_vector(8 downto 0);
signal configDataOutB : std_logic_vector(31 downto 0);
signal configDataInB : std_logic_vector(31 downto 0);
signal configDataLatched : std_logic_vector(31 downto 0);
signal resultAddr : std_logic_vector(8 downto 0);
signal resultData : std_logic_vector(31 downto 0);
signal resultLatched : std_logic_vector(31 downto 0);
signal statusLatched : std_logic_vector(7 downto 0);
signal outputStart : std_logic;
signal outputBusy : std_logic;
signal outputAddr : std_logic_vector( 7 downto 0);
signal outputData : std_logic_vector(23 downto 0);
signal driverOutput : std_logic;
begin
conf : configRam
PORT MAP (
clka => vidclk,
wea => "0",
addra => configAddrA,
dina => (others => '0'),
douta => configDataA,
clkb => cfgclk,
web => configWeB,
addrb => configAddrB,
dinb => configDataInB,
doutb => configDataOutB
);
hscale4 : entity work.hscale4 port map(vidclk, hblank, vblank, viddata_r, viddata_g, viddata_b,
hblank_delayed, vblank_delayed, ce2, ce4, ravg, gavg, bavg);
scaler : entity work.scaler port map(vidclk, ce2, hblank_delayed, vblank_delayed, ravg, gavg, bavg,
vidclk, lineBufferAddr, lineBufferData, lineReady, yPos);
lightAverager : entity work.lightAverager port map(vidclk, ce2, lineReady, yPos,
lineBufferAddr, lineBufferData,
configAddrA, configDataA,
cfgclk, resultAddr, resultData);
resultDistributor : entity work.resultDistributor port map(cfgclk, vblank,
resultAddr, resultData,
outputBusy, outputStart,
outputAddr, outputData);
ws2811Driver : entity work.ws2811Driver port map(cfgclk, outputStart, outputData, outputBusy, driverOutput);
process(cfgclk)
begin
if(rising_edge(cfgclk)) then
configDataLatched <= configDataOutB;
statusLatched <= "000000" & hblank & vblank;
if(resultAddr(7 downto 0) = cfglight) then
resultLatched <= resultData;
end if;
end if;
end process;
configWeB(0) <= cfgwe;
configAddrB <= "0" & cfglight;
--resultAddr <= "0" & cfglight;
with cfgcomponent select configDataInB <=
configDataLatched(31 downto 6) & cfgdatain(5 downto 0) when "0000",
configDataLatched(31 downto 12) & cfgdatain(5 downto 0) & configDataLatched(5 downto 0) when "0001",
configDataLatched(31 downto 18) & cfgdatain(5 downto 0) & configDataLatched(11 downto 0) when "0010",
configDataLatched(31 downto 24) & cfgdatain(5 downto 0) & configDataLatched(17 downto 0) when "0011",
configDataLatched(31 downto 28) & cfgdatain(3 downto 0) & configDataLatched(23 downto 0) when "0100",
configDataLatched(31 downto 31) & cfgdatain(2 downto 0) & configDataLatched(27 downto 0) when "0101",
configDataLatched when others;
with cfgcomponent select cfgdataout <=
"00" & configDataLatched( 5 downto 0) when "0000",
"00" & configDataLatched(11 downto 6) when "0001",
"00" & configDataLatched(17 downto 12) when "0010",
"00" & configDataLatched(23 downto 18) when "0011",
"0000" & configDataLatched(27 downto 24) when "0100",
"00000" & configDataLatched(30 downto 28) when "0101",
resultLatched( 7 downto 0) when "1000",
resultLatched(15 downto 8) when "1001",
resultLatched(23 downto 16) when "1010",
statusLatched when "1111",
(others => '0') when others;
with outputAddr select output <=
"0000000" & driverOutput when x"00",
"000000" & driverOutput & "0" when x"01",
"00000" & driverOutput & "00" when x"02",
"0000" & driverOutput & "000" when x"03",
"000" & driverOutput & "0000" when x"04",
"00" & driverOutput & "00000" when x"05",
"0" & driverOutput & "000000" when x"06",
driverOutput & "0000000" when x"07",
"00000000" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ambilight is
Port ( vidclk : in STD_LOGIC;
viddata_r : in STD_LOGIC_VECTOR (7 downto 0);
viddata_g : in STD_LOGIC_VECTOR (7 downto 0);
viddata_b : in STD_LOGIC_VECTOR (7 downto 0);
hblank : in STD_LOGIC;
vblank : in STD_LOGIC;
cfgclk : in STD_LOGIC;
cfgwe : in STD_LOGIC;
cfglight : in STD_LOGIC_VECTOR (7 downto 0);
cfgcomponent : in STD_LOGIC_VECTOR (3 downto 0);
cfgdatain : in STD_LOGIC_VECTOR (7 downto 0);
cfgdataout : out STD_LOGIC_VECTOR (7 downto 0);
output : out STD_LOGIC_VECTOR(7 downto 0));
end ambilight;
architecture Behavioral of ambilight is
COMPONENT configRam
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
signal ce2 : std_logic;
signal ce4 : std_logic;
signal hblank_delayed : std_logic;
signal vblank_delayed : std_logic;
signal ravg : std_logic_vector(7 downto 0);
signal gavg : std_logic_vector(7 downto 0);
signal bavg : std_logic_vector(7 downto 0);
signal lineBufferAddr : std_logic_vector(6 downto 0);
signal lineBufferData : std_logic_vector(23 downto 0);
signal yPos : std_logic_vector(5 downto 0);
signal lineReady : std_logic;
signal configAddrA : std_logic_vector(8 downto 0);
signal configDataA : std_logic_vector(31 downto 0);
signal configWeB : std_logic_vector(0 downto 0);
signal configAddrB : std_logic_vector(8 downto 0);
signal configDataOutB : std_logic_vector(31 downto 0);
signal configDataInB : std_logic_vector(31 downto 0);
signal configDataLatched : std_logic_vector(31 downto 0);
signal resultAddr : std_logic_vector(8 downto 0);
signal resultData : std_logic_vector(31 downto 0);
signal resultLatched : std_logic_vector(31 downto 0);
signal statusLatched : std_logic_vector(7 downto 0);
signal outputStart : std_logic;
signal outputBusy : std_logic;
signal outputAddr : std_logic_vector( 7 downto 0);
signal outputData : std_logic_vector(23 downto 0);
signal driverOutput : std_logic;
begin
conf : configRam
PORT MAP (
clka => vidclk,
wea => "0",
addra => configAddrA,
dina => (others => '0'),
douta => configDataA,
clkb => cfgclk,
web => configWeB,
addrb => configAddrB,
dinb => configDataInB,
doutb => configDataOutB
);
hscale4 : entity work.hscale4 port map(vidclk, hblank, vblank, viddata_r, viddata_g, viddata_b,
hblank_delayed, vblank_delayed, ce2, ce4, ravg, gavg, bavg);
scaler : entity work.scaler port map(vidclk, ce2, hblank_delayed, vblank_delayed, ravg, gavg, bavg,
vidclk, lineBufferAddr, lineBufferData, lineReady, yPos);
lightAverager : entity work.lightAverager port map(vidclk, ce2, lineReady, yPos,
lineBufferAddr, lineBufferData,
configAddrA, configDataA,
cfgclk, resultAddr, resultData);
resultDistributor : entity work.resultDistributor port map(cfgclk, vblank,
resultAddr, resultData,
outputBusy, outputStart,
outputAddr, outputData);
ws2811Driver : entity work.ws2811Driver port map(cfgclk, outputStart, outputData, outputBusy, driverOutput);
process(cfgclk)
begin
if(rising_edge(cfgclk)) then
configDataLatched <= configDataOutB;
statusLatched <= "000000" & hblank & vblank;
if(resultAddr(7 downto 0) = cfglight) then
resultLatched <= resultData;
end if;
end if;
end process;
configWeB(0) <= cfgwe;
configAddrB <= "0" & cfglight;
--resultAddr <= "0" & cfglight;
with cfgcomponent select configDataInB <=
configDataLatched(31 downto 6) & cfgdatain(5 downto 0) when "0000",
configDataLatched(31 downto 12) & cfgdatain(5 downto 0) & configDataLatched(5 downto 0) when "0001",
configDataLatched(31 downto 18) & cfgdatain(5 downto 0) & configDataLatched(11 downto 0) when "0010",
configDataLatched(31 downto 24) & cfgdatain(5 downto 0) & configDataLatched(17 downto 0) when "0011",
configDataLatched(31 downto 28) & cfgdatain(3 downto 0) & configDataLatched(23 downto 0) when "0100",
configDataLatched(31 downto 31) & cfgdatain(2 downto 0) & configDataLatched(27 downto 0) when "0101",
configDataLatched when others;
with cfgcomponent select cfgdataout <=
"00" & configDataLatched( 5 downto 0) when "0000",
"00" & configDataLatched(11 downto 6) when "0001",
"00" & configDataLatched(17 downto 12) when "0010",
"00" & configDataLatched(23 downto 18) when "0011",
"0000" & configDataLatched(27 downto 24) when "0100",
"00000" & configDataLatched(30 downto 28) when "0101",
resultLatched( 7 downto 0) when "1000",
resultLatched(15 downto 8) when "1001",
resultLatched(23 downto 16) when "1010",
statusLatched when "1111",
(others => '0') when others;
with outputAddr select output <=
"0000000" & driverOutput when x"00",
"000000" & driverOutput & "0" when x"01",
"00000" & driverOutput & "00" when x"02",
"0000" & driverOutput & "000" when x"03",
"000" & driverOutput & "0000" when x"04",
"00" & driverOutput & "00000" when x"05",
"0" & driverOutput & "000000" when x"06",
driverOutput & "0000000" when x"07",
"00000000" when others;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwx
-- File: grfpwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity grfpwx is
generic (fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 3 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of grfpwx is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
signal rf1rd1, rf1rd2, rf2rd1, rf2rd2, rf1wd, rf2wd : std_logic_vector(38 downto 0);
begin
x1 : if true generate
grfpw0 : grfpw_net generic map (fabtech, pclow, dsu, disas)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
rf1 : regfile_3p_l3 generic map (memtech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr,
rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2,
testin
);
rf2 : regfile_3p_l3 generic map (memtech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr,
rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2,
testin
);
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 28960)
`protect data_block
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`protect end_protected
|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect end_protected
|
-------------------------------------------------------------------------------
--
-- Title : dma_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\dma_handler.vhd
-- Generated : Wed Aug 3 13:00:54 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-11-28 V0.02 zelenkaj Added DMA observer
-- 2011-11-30 V0.03 zelenkaj Removed unnecessary ports
-- Added generic for DMA observer
-- 2011-12-02 V0.04 zelenkaj Added Dma Request Overflow
-- 2011-12-05 V0.05 zelenkaj Reduced Dma Req overflow cnt to pulse
-- Ack done if overflow occurs
-- 2011-12-23 V0.06 zelenkaj Minor change of dma_ack generation
-- 2012-04-17 V0.07 zelenkaj Added forwarding of DMA read length
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
tx_fifo_word_size_log2_g : natural := 5;
rx_fifo_word_size_log2_g : natural := 5;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
dma_req_wr : in std_logic;
dma_req_rd : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_ack_wr : out std_logic;
dma_ack_rd : out std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
tx_rd_clk : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_req : out std_logic;
rx_wr_full : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
rx_wr_req : out std_logic;
rx_aclr : out std_logic;
rx_wr_clk : in std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_new_addr_wr : out std_logic;
dma_new_addr_rd : out std_logic;
dma_new_len : out std_logic;
dma_req_overflow : in std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic
);
end dma_handler;
architecture dma_handler of dma_handler is
--clock signal
signal clk : std_logic;
--fsm
type transfer_t is (idle, first, run);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--dma signals
signal dma_ack_rd_s, dma_ack_wr_s : std_logic;
--dma observer
signal observ_rd_err, observ_wr_err : std_logic;
signal observ_rd_err_next, observ_wr_err_next : std_logic;
begin
--dma_clk, tx_rd_clk and rx_wr_clk are the same!
clk <= dma_clk; --to ease typing
rx_aclr <= rst;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_fsm <= idle;
if gen_dma_observer_g then
observ_rd_err <= '0';
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= idle;
if gen_dma_observer_g then
observ_wr_err <= '0';
end if;
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
if gen_dma_observer_g then
observ_rd_err <= observ_rd_err_next;
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
if gen_dma_observer_g then
observ_wr_err <= observ_wr_err_next;
end if;
end if;
end if;
end process;
dma_rd_len_out <= dma_rd_len; --register in openMAC.vhd!
tx_fsm_next <= idle when gen_tx_fifo_g = false else --hang here if generic disables tx handling
first when tx_fsm = idle and dma_req_rd = '1' else
run when tx_fsm = first and dma_ack_rd_s = '1' else
idle when mac_tx_off = '1' else
tx_fsm;
rx_fsm_next <= idle when gen_rx_fifo_g = false else --hang here if generic disables rx handling
first when rx_fsm = idle and dma_req_wr = '1' else
run when rx_fsm = first else
idle when mac_rx_off = '1' else
rx_fsm;
genDmaObserver : if gen_dma_observer_g generate
begin
observ_rd_err_next <= --monoflop (deassertion with rst only)
'0' when gen_tx_fifo_g = false else
'1' when dma_req_rd = '1' and dma_ack_rd_s = '0' and dma_req_overflow = '1' else
observ_rd_err;
observ_wr_err_next <= --monoflop (deassertion with rst only)
'0' when gen_rx_fifo_g = false else
'1' when dma_req_wr = '1' and dma_ack_wr_s = '0' and dma_req_overflow = '1' else
observ_wr_err;
end generate;
dma_rd_err <= observ_rd_err;
dma_wr_err <= observ_wr_err;
--acknowledge dma request (regular or overflow)
dma_ack_rd <= dma_req_rd and (dma_ack_rd_s or dma_req_overflow);
dma_ack_wr <= dma_req_wr and (dma_ack_wr_s or dma_req_overflow);
dma_new_addr_wr <= '1' when rx_fsm = first else '0';
dma_new_addr_rd <= '1' when tx_fsm = first else '0';
dma_new_len <= '1' when tx_fsm = first else '0';
process(clk, rst)
begin
if rst = '1' then
dma_addr_out <= (others => '0');
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
end if;
elsif clk = '1' and clk'event then
--if the very first address is available, store it over the whole transfer
if tx_fsm = first or rx_fsm = first then
dma_addr_out <= dma_addr;
end if;
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
--dma request, TX fifo is not empty and not yet ack'd
if dma_req_rd = '1' and tx_rd_empty = '0' and dma_ack_rd_s = '0' then
tx_rd_req <= '1'; --read from TX fifo
dma_ack_rd_s <= '1'; --ack the read request
end if;
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
--dma request, RX fifo is not full and not yet ack'd
if dma_req_wr = '1' and rx_wr_full = '0' and dma_ack_wr_s = '0' then
rx_wr_req <= '1'; --write to RX fifo
dma_ack_wr_s <= '1'; --ack the read request
end if;
end if;
end if;
end process;
end dma_handler;
|
-------------------------------------------------------------------------------
--
-- Title : dma_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\dma_handler.vhd
-- Generated : Wed Aug 3 13:00:54 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-11-28 V0.02 zelenkaj Added DMA observer
-- 2011-11-30 V0.03 zelenkaj Removed unnecessary ports
-- Added generic for DMA observer
-- 2011-12-02 V0.04 zelenkaj Added Dma Request Overflow
-- 2011-12-05 V0.05 zelenkaj Reduced Dma Req overflow cnt to pulse
-- Ack done if overflow occurs
-- 2011-12-23 V0.06 zelenkaj Minor change of dma_ack generation
-- 2012-04-17 V0.07 zelenkaj Added forwarding of DMA read length
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
tx_fifo_word_size_log2_g : natural := 5;
rx_fifo_word_size_log2_g : natural := 5;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
dma_req_wr : in std_logic;
dma_req_rd : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_ack_wr : out std_logic;
dma_ack_rd : out std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
tx_rd_clk : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_req : out std_logic;
rx_wr_full : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
rx_wr_req : out std_logic;
rx_aclr : out std_logic;
rx_wr_clk : in std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_new_addr_wr : out std_logic;
dma_new_addr_rd : out std_logic;
dma_new_len : out std_logic;
dma_req_overflow : in std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic
);
end dma_handler;
architecture dma_handler of dma_handler is
--clock signal
signal clk : std_logic;
--fsm
type transfer_t is (idle, first, run);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--dma signals
signal dma_ack_rd_s, dma_ack_wr_s : std_logic;
--dma observer
signal observ_rd_err, observ_wr_err : std_logic;
signal observ_rd_err_next, observ_wr_err_next : std_logic;
begin
--dma_clk, tx_rd_clk and rx_wr_clk are the same!
clk <= dma_clk; --to ease typing
rx_aclr <= rst;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_fsm <= idle;
if gen_dma_observer_g then
observ_rd_err <= '0';
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= idle;
if gen_dma_observer_g then
observ_wr_err <= '0';
end if;
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
if gen_dma_observer_g then
observ_rd_err <= observ_rd_err_next;
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
if gen_dma_observer_g then
observ_wr_err <= observ_wr_err_next;
end if;
end if;
end if;
end process;
dma_rd_len_out <= dma_rd_len; --register in openMAC.vhd!
tx_fsm_next <= idle when gen_tx_fifo_g = false else --hang here if generic disables tx handling
first when tx_fsm = idle and dma_req_rd = '1' else
run when tx_fsm = first and dma_ack_rd_s = '1' else
idle when mac_tx_off = '1' else
tx_fsm;
rx_fsm_next <= idle when gen_rx_fifo_g = false else --hang here if generic disables rx handling
first when rx_fsm = idle and dma_req_wr = '1' else
run when rx_fsm = first else
idle when mac_rx_off = '1' else
rx_fsm;
genDmaObserver : if gen_dma_observer_g generate
begin
observ_rd_err_next <= --monoflop (deassertion with rst only)
'0' when gen_tx_fifo_g = false else
'1' when dma_req_rd = '1' and dma_ack_rd_s = '0' and dma_req_overflow = '1' else
observ_rd_err;
observ_wr_err_next <= --monoflop (deassertion with rst only)
'0' when gen_rx_fifo_g = false else
'1' when dma_req_wr = '1' and dma_ack_wr_s = '0' and dma_req_overflow = '1' else
observ_wr_err;
end generate;
dma_rd_err <= observ_rd_err;
dma_wr_err <= observ_wr_err;
--acknowledge dma request (regular or overflow)
dma_ack_rd <= dma_req_rd and (dma_ack_rd_s or dma_req_overflow);
dma_ack_wr <= dma_req_wr and (dma_ack_wr_s or dma_req_overflow);
dma_new_addr_wr <= '1' when rx_fsm = first else '0';
dma_new_addr_rd <= '1' when tx_fsm = first else '0';
dma_new_len <= '1' when tx_fsm = first else '0';
process(clk, rst)
begin
if rst = '1' then
dma_addr_out <= (others => '0');
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
end if;
elsif clk = '1' and clk'event then
--if the very first address is available, store it over the whole transfer
if tx_fsm = first or rx_fsm = first then
dma_addr_out <= dma_addr;
end if;
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
--dma request, TX fifo is not empty and not yet ack'd
if dma_req_rd = '1' and tx_rd_empty = '0' and dma_ack_rd_s = '0' then
tx_rd_req <= '1'; --read from TX fifo
dma_ack_rd_s <= '1'; --ack the read request
end if;
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
--dma request, RX fifo is not full and not yet ack'd
if dma_req_wr = '1' and rx_wr_full = '0' and dma_ack_wr_s = '0' then
rx_wr_req <= '1'; --write to RX fifo
dma_ack_wr_s <= '1'; --ack the read request
end if;
end if;
end if;
end process;
end dma_handler;
|
-------------------------------------------------------------------------------
--
-- Title : dma_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\dma_handler.vhd
-- Generated : Wed Aug 3 13:00:54 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-11-28 V0.02 zelenkaj Added DMA observer
-- 2011-11-30 V0.03 zelenkaj Removed unnecessary ports
-- Added generic for DMA observer
-- 2011-12-02 V0.04 zelenkaj Added Dma Request Overflow
-- 2011-12-05 V0.05 zelenkaj Reduced Dma Req overflow cnt to pulse
-- Ack done if overflow occurs
-- 2011-12-23 V0.06 zelenkaj Minor change of dma_ack generation
-- 2012-04-17 V0.07 zelenkaj Added forwarding of DMA read length
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
tx_fifo_word_size_log2_g : natural := 5;
rx_fifo_word_size_log2_g : natural := 5;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
dma_req_wr : in std_logic;
dma_req_rd : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_ack_wr : out std_logic;
dma_ack_rd : out std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
tx_rd_clk : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_req : out std_logic;
rx_wr_full : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
rx_wr_req : out std_logic;
rx_aclr : out std_logic;
rx_wr_clk : in std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_new_addr_wr : out std_logic;
dma_new_addr_rd : out std_logic;
dma_new_len : out std_logic;
dma_req_overflow : in std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic
);
end dma_handler;
architecture dma_handler of dma_handler is
--clock signal
signal clk : std_logic;
--fsm
type transfer_t is (idle, first, run);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--dma signals
signal dma_ack_rd_s, dma_ack_wr_s : std_logic;
--dma observer
signal observ_rd_err, observ_wr_err : std_logic;
signal observ_rd_err_next, observ_wr_err_next : std_logic;
begin
--dma_clk, tx_rd_clk and rx_wr_clk are the same!
clk <= dma_clk; --to ease typing
rx_aclr <= rst;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_fsm <= idle;
if gen_dma_observer_g then
observ_rd_err <= '0';
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= idle;
if gen_dma_observer_g then
observ_wr_err <= '0';
end if;
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
if gen_dma_observer_g then
observ_rd_err <= observ_rd_err_next;
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
if gen_dma_observer_g then
observ_wr_err <= observ_wr_err_next;
end if;
end if;
end if;
end process;
dma_rd_len_out <= dma_rd_len; --register in openMAC.vhd!
tx_fsm_next <= idle when gen_tx_fifo_g = false else --hang here if generic disables tx handling
first when tx_fsm = idle and dma_req_rd = '1' else
run when tx_fsm = first and dma_ack_rd_s = '1' else
idle when mac_tx_off = '1' else
tx_fsm;
rx_fsm_next <= idle when gen_rx_fifo_g = false else --hang here if generic disables rx handling
first when rx_fsm = idle and dma_req_wr = '1' else
run when rx_fsm = first else
idle when mac_rx_off = '1' else
rx_fsm;
genDmaObserver : if gen_dma_observer_g generate
begin
observ_rd_err_next <= --monoflop (deassertion with rst only)
'0' when gen_tx_fifo_g = false else
'1' when dma_req_rd = '1' and dma_ack_rd_s = '0' and dma_req_overflow = '1' else
observ_rd_err;
observ_wr_err_next <= --monoflop (deassertion with rst only)
'0' when gen_rx_fifo_g = false else
'1' when dma_req_wr = '1' and dma_ack_wr_s = '0' and dma_req_overflow = '1' else
observ_wr_err;
end generate;
dma_rd_err <= observ_rd_err;
dma_wr_err <= observ_wr_err;
--acknowledge dma request (regular or overflow)
dma_ack_rd <= dma_req_rd and (dma_ack_rd_s or dma_req_overflow);
dma_ack_wr <= dma_req_wr and (dma_ack_wr_s or dma_req_overflow);
dma_new_addr_wr <= '1' when rx_fsm = first else '0';
dma_new_addr_rd <= '1' when tx_fsm = first else '0';
dma_new_len <= '1' when tx_fsm = first else '0';
process(clk, rst)
begin
if rst = '1' then
dma_addr_out <= (others => '0');
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
end if;
elsif clk = '1' and clk'event then
--if the very first address is available, store it over the whole transfer
if tx_fsm = first or rx_fsm = first then
dma_addr_out <= dma_addr;
end if;
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
--dma request, TX fifo is not empty and not yet ack'd
if dma_req_rd = '1' and tx_rd_empty = '0' and dma_ack_rd_s = '0' then
tx_rd_req <= '1'; --read from TX fifo
dma_ack_rd_s <= '1'; --ack the read request
end if;
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
--dma request, RX fifo is not full and not yet ack'd
if dma_req_wr = '1' and rx_wr_full = '0' and dma_ack_wr_s = '0' then
rx_wr_req <= '1'; --write to RX fifo
dma_ack_wr_s <= '1'; --ack the read request
end if;
end if;
end if;
end process;
end dma_handler;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity R_UC is
port(
clock : in std_logic;
reset : in std_logic;
e_s : in std_logic;
amostra : in std_logic;
finaliza_recepcao : in std_logic;
tick : in std_logic;
amostrando : out std_logic;
recebendo : out std_logic;
verificando_paridade : out std_logic;
apresentando : out std_logic;
saida_estado : out std_logic_vector(2 downto 0)
);
end R_UC;
architecture estados of unidade_controle is
type tipo_estado is (INICIAL, VERIFICA_AMOSTRA, RECEBE, VERIFICA_PARIDADE, APRESENTA);
signal estado : tipo_estado;
begin
process (clock, e_s, finaliza_recepcao)
begin
if reset = '1' then
estado <= INICIAL;
elsif clock'event and clock = '1' then
case estado is
when INICIAL =>
if e_s = '0' and tick = '1' then
estado <= VERIFICA_AMOSTRA;
else
estado <= INICIAL;
end if;
when VERIFICA_AMOSTRA =>
if e_s = '0' and amostra = '1' and tick = '1' then
estado <= RECEBE;
elsif e_s = '1' and amostra = '1' and tick = '1' then
estado <= INICIAL;
else
estado <= VERIFICA_AMOSTRA;
end if;
when RECEBE =>
if finaliza_recepcao = '1' and tick = '1' then
estado <= VERIFICA_PARIDADE;
else
estado <= RECEBE;
end if;
when VERIFICA_PARIDADE =>
estado <= APRESENTA;
when APRESENTA =>
if reset = '1' then
estado <= INICIAL;
else
estado <= APRESENTA;
end if;
end case;
end if;
end process;
process (estado)
begin
case estado is
when INICIAL =>
saida_estado <= "000";
amostrando <= '0';
recebendo <= '0';
verificando_paridade <= '0';
apresentando <= '0';
when VERIFICA_AMOSTRA =>
saida_estado <= "001";
amostrando <= '1';
recebendo <= '0';
verificando_paridade <= '0';
apresentando <= '0';
when RECEBE =>
saida_estado <= "010";
amostrando <= '0';
recebendo <= '1';
verificando_paridade <= '0';
apresentando <= '0';
when VERIFICA_PARIDADE =>
saida_estado <= "011";
amostrando <= '0';
recebendo <= '0';
verificando_paridade <= '1';
apresentando <= '0';
when APRESENTA =>
saida_estado <= "100";
amostrando <= '0';
recebendo <= '0';
verificando_paridade <= '0';
apresentando <= '1';
end case;
end process;
end estados;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- richard@asics.ws ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- richard@asics.ws ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
--
-- $Date: 2006/10/11 12:10:13 $
-- $Revision: 1.14 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_bit_ctrl.vhd,v $
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson (jan@gaisler.com):
-- * Added two start states to fulfill Set-up time for
-- repeated START condition.
-- * Modified synchronization of SCL and SDA. START and STOP detection
-- is now performed after a two stage synchronizer and is also
-- filtered.
-- * Changed evaluation order of 'slave_wait', 'en' and 'cnt' in
-- generation of clk_en signal to prevent clk_en assertion when
-- slave_wait is asserted.
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e, start_f, start_g,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal disda_oen : std_logic; -- delayed isda_oen
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic_vector(1 downto 0); -- delayed scl_oen signals
-- synchronized SCL and SDA inputs
signal sSCL, sSDA : std_logic_vector(5 downto 0);
signal clk_en, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : std_logic_vector(15 downto 0); -- clock divider counter (synthesis)
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
dscl_oen <= dscl_oen(0) & iscl_oen;
end if;
end process;
slave_wait <= dscl_oen(1) and not sSCL(1);
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif (ena = '0') then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
elsif (cnt = X"0000") then
cnt <= clk_cnt;
clk_en <= '1';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
--signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= (others => '1');
sSDA <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= (others => '1');
sSDA <= (others => '1');
else
sSCL <= sSCL(4 downto 0) & scl_i;
sSDA <= sSDA(4 downto 0) & sda_i;
end if;
end if;
end process synch_SCL_SDA;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
if sSCL(5 downto 2) = "1111" and sSDA(5 downto 2) = "1100" then
sta_condition <= '1';
else
sta_condition <= '0';
end if;
if sSCL(5 downto 2) = "1111" and sSDA(5 downto 2) = "0011" then
sto_condition <= '1';
else
sto_condition <= '0';
end if;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not sSDA(1) and disda_oen);
else
ial <= (sda_chk and not sSDA(1) and disda_oen) or
(sto_condition and not cmd_stop);
end if;
disda_oen <= isda_oen;
end if;
end if;
end process gen_al;
al <= ial;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if sSCL(3 downto 2) = "01" then
dout <= sSDA(2);
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; -- default no acknowledge
if (clk_en = '1') then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle; -- NOP command
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= start_f;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_f =>
c_state <= start_g;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_g =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- richard@asics.ws ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- richard@asics.ws ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
--
-- $Date: 2006/10/11 12:10:13 $
-- $Revision: 1.14 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_bit_ctrl.vhd,v $
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson (jan@gaisler.com):
-- * Added two start states to fulfill Set-up time for
-- repeated START condition.
-- * Modified synchronization of SCL and SDA. START and STOP detection
-- is now performed after a two stage synchronizer and is also
-- filtered.
-- * Changed evaluation order of 'slave_wait', 'en' and 'cnt' in
-- generation of clk_en signal to prevent clk_en assertion when
-- slave_wait is asserted.
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e, start_f, start_g,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal disda_oen : std_logic; -- delayed isda_oen
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic_vector(1 downto 0); -- delayed scl_oen signals
-- synchronized SCL and SDA inputs
signal sSCL, sSDA : std_logic_vector(5 downto 0);
signal clk_en, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : std_logic_vector(15 downto 0); -- clock divider counter (synthesis)
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
dscl_oen <= dscl_oen(0) & iscl_oen;
end if;
end process;
slave_wait <= dscl_oen(1) and not sSCL(1);
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif (ena = '0') then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
elsif (cnt = X"0000") then
cnt <= clk_cnt;
clk_en <= '1';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
--signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= (others => '1');
sSDA <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= (others => '1');
sSDA <= (others => '1');
else
sSCL <= sSCL(4 downto 0) & scl_i;
sSDA <= sSDA(4 downto 0) & sda_i;
end if;
end if;
end process synch_SCL_SDA;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
if sSCL(5 downto 2) = "1111" and sSDA(5 downto 2) = "1100" then
sta_condition <= '1';
else
sta_condition <= '0';
end if;
if sSCL(5 downto 2) = "1111" and sSDA(5 downto 2) = "0011" then
sto_condition <= '1';
else
sto_condition <= '0';
end if;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not sSDA(1) and disda_oen);
else
ial <= (sda_chk and not sSDA(1) and disda_oen) or
(sto_condition and not cmd_stop);
end if;
disda_oen <= isda_oen;
end if;
end if;
end process gen_al;
al <= ial;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if sSCL(3 downto 2) = "01" then
dout <= sSDA(2);
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; -- default no acknowledge
if (clk_en = '1') then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle; -- NOP command
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= start_f;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_f =>
c_state <= start_g;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_g =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grlfpwx
-- File: grlfpwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
entity grlfpwx is
generic (
tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
pipe : integer := 0;
netlist : integer := 0;
index : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of grlfpwx is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
begin
x1 : if true generate
grlfpw0 : grlfpw_net generic map (tech, pclow, dsu, disas, pipe)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
rf1 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr,
rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2,
testin
);
rf2 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr,
rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2,
testin
);
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_decoder IS
END tb_decoder;
ARCHITECTURE behavior OF tb_decoder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT decoder
PORT(
CLK : IN std_logic;
RST : IN std_logic;
code : IN std_logic_vector(1 DOWNTO 0);
action : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
led : OUT std_logic_vector(6 DOWNTO 0);
dig_ctrl : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal code : std_logic_vector(1 downto 0) := (others => '0');
signal action: std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal led : std_logic_vector(6 downto 0);
signal dig_ctrl : std_logic_vector(3 downto 0);
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: decoder PORT MAP (
CLK => CLK,
RST => RST,
code => code,
action => action,
led => led,
dig_ctrl => dig_ctrl
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- insert stimulus here
RST <= '0';
code <= "00";
action <="00";
WAIT FOR 20 ns;
code <= "01";
action <="01";
WAIT FOR 20 ns;
RST <= '1';
code <= "10";
action <="10";
WAIT FOR 20 ns;
code <= "11";
action <="11";
WAIT FOR 20 ns;
RST <= '0';
code <= "01";
action <="01";
WAIT FOR 20 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
end process;
END; |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
ch2_eof_detected : in std_logic ; --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
tail_updt : in std_logic;
tail_updt_latch : out std_logic;
ch2_updt_done : in std_logic;
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic --
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal first : std_logic;
signal eof_latch : std_logic;
signal ch2_sg_idle_int : std_logic;
attribute mark_debug of ch1_fetch_address_i : signal is "true";
attribute mark_debug of ch2_fetch_address_i : signal is "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
-- Addresses are always 16 word 32-bit aligned
ch1_fetch_address <= ch1_fetch_address_i (C_M_AXI_SG_ADDR_WIDTH-1 downto 6) & "000000";
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif((ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0'))then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
-- Addresses are always 16 word 32-bit aligned
ch2_fetch_address <= ch2_fetch_address_i (C_M_AXI_SG_ADDR_WIDTH-1 downto 6) & "000000";
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1' or ch2_eof_detected = '1')then
ch2_sg_idle <= '1';
ch2_sg_idle_int <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
ch2_sg_idle_int <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
ch2_sg_idle_int <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
-- Needed for multi channel
EOF_LATCH_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_taildesc_wren = '1' or eof_latch = '1')then -- nned to have some reset condition here
eof_latch <= '0';
elsif (ch2_sg_idle_int = '1' and ch2_updt_done = '1') then
eof_latch <= '1';
end if;
end if;
end process EOF_LATCH_PROC;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or eof_latch = '1')then -- nned to have some reset condition here
tail_updt_latch <= '0';
first <= '0';
elsif (tail_updt = '1') then
tail_updt_latch <= '0';
elsif(ch2_taildesc_wren = '1' and first = '0')then
first <= '1';
elsif(ch2_taildesc_wren = '1' and first = '1')then
tail_updt_latch <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
tail_updt_latch <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( NZVC : in STD_LOGIC_VECTOR (3 downto 0);
nCWP: in STD_LOGIC;
CLK: in STD_LOGIC;
rst: in STD_LOGIC;
CWP: out STD_LOGIC;
C : out STD_LOGIC);
end PSR;
architecture Behavioral of PSR is
signal PSRegister: std_logic_vector(4 downto 0):=(others=>'0');
begin
process(NZVC,nCWP,CLK,rst)
begin
if rst='1' then
PSRegister<=(others=>'0');
C<='0';
CWP<='0';
elsif rising_edge(CLK) then
if not(NZVC="1111") then
PSRegister(4 downto 1)<=NZVC;
end if;
PSRegister(0)<=nCWP;
CWP<=PSRegister(0);
--CWP<=nCWP;
C<=PSRegister(1);
--C<=NZVC(0);
end if;
end process;
end Behavioral;
|
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lib_pkg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lib_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end lib_pkg;
package body lib_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body lib_pkg;
|
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lib_pkg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lib_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end lib_pkg;
package body lib_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body lib_pkg;
|
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lib_pkg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lib_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end lib_pkg;
package body lib_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body lib_pkg;
|
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lib_pkg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lib_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end lib_pkg;
package body lib_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body lib_pkg;
|
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lib_pkg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lib_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end lib_pkg;
package body lib_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body lib_pkg;
|
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lib_pkg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lib_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end lib_pkg;
package body lib_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body lib_pkg;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY InstruccionMemory_tb IS
END InstruccionMemory_tb;
ARCHITECTURE behavior OF InstruccionMemory_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT InstruccionMemory
PORT(
address : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal address : std_logic_vector(31 downto 0) := (others => '0');
signal rst : std_logic := '0';
--Outputs
signal instruction : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: InstruccionMemory PORT MAP (
address => address,
rst => rst,
instruction => instruction
);
-- Stimulus process
stim_proc: process
begin
rst <= '0';
address <= "00000000000000000000000000000000";
wait for 25 ns;
address <= "00000000000000000000000000000001";
wait for 25 ns;
address <= "00000000000000000000000000000010";
wait for 25 ns;
address <= "00000000000000000000000000000011";
wait for 25 ns;
rst <= '1';
wait for 25 ns;
rst <= '0';
-- insert stimulus here
wait;
end process;
END;
|
entity alias4 is
end entity;
architecture test of alias4 is
function func(x : bit_vector(7 downto 0); k : bit_vector) return bit is
alias y : bit_vector(k'range) is x;
begin
return y(1);
end function;
begin
process is
variable x : bit_vector(7 downto 0);
begin
x := X"ab";
assert func(x, x) = '1';
wait;
end process;
end architecture;
|
entity alias4 is
end entity;
architecture test of alias4 is
function func(x : bit_vector(7 downto 0); k : bit_vector) return bit is
alias y : bit_vector(k'range) is x;
begin
return y(1);
end function;
begin
process is
variable x : bit_vector(7 downto 0);
begin
x := X"ab";
assert func(x, x) = '1';
wait;
end process;
end architecture;
|
entity alias4 is
end entity;
architecture test of alias4 is
function func(x : bit_vector(7 downto 0); k : bit_vector) return bit is
alias y : bit_vector(k'range) is x;
begin
return y(1);
end function;
begin
process is
variable x : bit_vector(7 downto 0);
begin
x := X"ab";
assert func(x, x) = '1';
wait;
end process;
end architecture;
|
entity alias4 is
end entity;
architecture test of alias4 is
function func(x : bit_vector(7 downto 0); k : bit_vector) return bit is
alias y : bit_vector(k'range) is x;
begin
return y(1);
end function;
begin
process is
variable x : bit_vector(7 downto 0);
begin
x := X"ab";
assert func(x, x) = '1';
wait;
end process;
end architecture;
|
entity alias4 is
end entity;
architecture test of alias4 is
function func(x : bit_vector(7 downto 0); k : bit_vector) return bit is
alias y : bit_vector(k'range) is x;
begin
return y(1);
end function;
begin
process is
variable x : bit_vector(7 downto 0);
begin
x := X"ab";
assert func(x, x) = '1';
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3sh
-- File: leon3sh.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
library techmap;
use techmap.gencomp.all;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libproc3.all;
use gaisler.arith.all;
--library fpu;
--use fpu.libfpu.all;
entity leon3sh is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end;
architecture rtl of leon3sh is
constant IRFBITS : integer range 6 to 10 := log2(NWINDOWS+1) + 4;
constant IREGNUM : integer := NWINDOWS * 16 + 8;
signal holdn : std_logic;
signal rfi : iregfile_in_type;
signal rfo : iregfile_out_type;
signal crami : cram_in_type;
signal cramo : cram_out_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal rst : std_ulogic;
signal fpi : fpc_in_type;
signal fpo : fpc_out_type;
signal cpi : fpc_in_type;
signal cpo : fpc_out_type;
signal rd1, rd2, wd : std_logic_vector(35 downto 0);
signal gnd, vcc : std_logic;
constant FPURFHARD : integer := 1; --1-is_fpga(memtech);
constant fpuarch : integer := fpu mod 16;
constant fpunet : integer := fpu / 16;
begin
gnd <= '0'; vcc <= '1';
-- leon3 processor core (iu, caches & mul/div)
p0 : proc3
generic map (hindex, fabtech, memtech, nwindows, dsu, fpu, v8, cp, mac,
pclow, notag, nwp, icen, irepl, isets, ilinesize, isetsize, isetlock,
dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, ilramstart, dlram, dlramsize, dlramstart, mmuen, itlbnum, dtlbnum,
tlb_type, tlb_rep, lddel, disas, tbuf, pwd, svt, rstaddr, smp, cached, 0, scantest)
port map (clk, rst, holdn, ahbi, ahbo, ahbsi, ahbso, rfi, rfo, crami, cramo,
tbi, tbo, fpi, fpo, cpi, cpo, irqi, irqo, dbgi, dbgo, gnd, clk, vcc);
-- IU register file
rf0 : regfile_3p generic map (memtech, IRFBITS, 32, 1, IREGNUM)
port map (clk, rfi.waddr(IRFBITS-1 downto 0), rfi.wdata, rfi.wren,
clk, rfi.raddr1(IRFBITS-1 downto 0), rfi.ren1, rfo.data1,
rfi.raddr2(IRFBITS-1 downto 0), rfi.ren2, rfo.data2, rfi.diag);
-- cache memory
cmem0 : cachemem
generic map (memtech, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, dlram, dlramsize, mmuen)
port map (clk, crami, cramo, clk);
-- instruction trace buffer memory
tbmem_gen : if (tbuf /= 0) generate
tbmem0 : tbufmem
generic map (tech => memtech, tbuf => tbuf)
port map (clk, tbi, tbo);
end generate;
-- FPU
fpu0 : if not ((fpuarch > 0) and (fpuarch < 8)) generate fpo.ldlock <= '0'; fpo.ccv <= '1'; fpo.holdn <= '1'; end generate;
grfpw0gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwxsh
generic map (FPURFHARD*memtech, pclow, dsu, disas, hindex)
port map (rst, clk, holdn, fpi, fpo, fpui, fpuo);
end generate;
-- 1-clock reset delay
rstreg : process(clk)
begin if rising_edge(clk) then rst <= rstn; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map (
"leon3_" & tost(hindex) & ": LEON3 SPARC V8 processor rev " & tost(LEON3_VERSION),
"leon3_" & tost(hindex) & ": icache " & tost(isets*icen) & "*" & tost(isetsize*icen) &
" kbyte, dcache " & tost(dsets*dcen) & "*" & tost(dsetsize*dcen) & " kbyte"
);
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3sh
-- File: leon3sh.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
library techmap;
use techmap.gencomp.all;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libproc3.all;
use gaisler.arith.all;
--library fpu;
--use fpu.libfpu.all;
entity leon3sh is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end;
architecture rtl of leon3sh is
constant IRFBITS : integer range 6 to 10 := log2(NWINDOWS+1) + 4;
constant IREGNUM : integer := NWINDOWS * 16 + 8;
signal holdn : std_logic;
signal rfi : iregfile_in_type;
signal rfo : iregfile_out_type;
signal crami : cram_in_type;
signal cramo : cram_out_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal rst : std_ulogic;
signal fpi : fpc_in_type;
signal fpo : fpc_out_type;
signal cpi : fpc_in_type;
signal cpo : fpc_out_type;
signal rd1, rd2, wd : std_logic_vector(35 downto 0);
signal gnd, vcc : std_logic;
constant FPURFHARD : integer := 1; --1-is_fpga(memtech);
constant fpuarch : integer := fpu mod 16;
constant fpunet : integer := fpu / 16;
begin
gnd <= '0'; vcc <= '1';
-- leon3 processor core (iu, caches & mul/div)
p0 : proc3
generic map (hindex, fabtech, memtech, nwindows, dsu, fpu, v8, cp, mac,
pclow, notag, nwp, icen, irepl, isets, ilinesize, isetsize, isetlock,
dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, ilramstart, dlram, dlramsize, dlramstart, mmuen, itlbnum, dtlbnum,
tlb_type, tlb_rep, lddel, disas, tbuf, pwd, svt, rstaddr, smp, cached, 0, scantest)
port map (clk, rst, holdn, ahbi, ahbo, ahbsi, ahbso, rfi, rfo, crami, cramo,
tbi, tbo, fpi, fpo, cpi, cpo, irqi, irqo, dbgi, dbgo, gnd, clk, vcc);
-- IU register file
rf0 : regfile_3p generic map (memtech, IRFBITS, 32, 1, IREGNUM)
port map (clk, rfi.waddr(IRFBITS-1 downto 0), rfi.wdata, rfi.wren,
clk, rfi.raddr1(IRFBITS-1 downto 0), rfi.ren1, rfo.data1,
rfi.raddr2(IRFBITS-1 downto 0), rfi.ren2, rfo.data2, rfi.diag);
-- cache memory
cmem0 : cachemem
generic map (memtech, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, dlram, dlramsize, mmuen)
port map (clk, crami, cramo, clk);
-- instruction trace buffer memory
tbmem_gen : if (tbuf /= 0) generate
tbmem0 : tbufmem
generic map (tech => memtech, tbuf => tbuf)
port map (clk, tbi, tbo);
end generate;
-- FPU
fpu0 : if not ((fpuarch > 0) and (fpuarch < 8)) generate fpo.ldlock <= '0'; fpo.ccv <= '1'; fpo.holdn <= '1'; end generate;
grfpw0gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwxsh
generic map (FPURFHARD*memtech, pclow, dsu, disas, hindex)
port map (rst, clk, holdn, fpi, fpo, fpui, fpuo);
end generate;
-- 1-clock reset delay
rstreg : process(clk)
begin if rising_edge(clk) then rst <= rstn; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map (
"leon3_" & tost(hindex) & ": LEON3 SPARC V8 processor rev " & tost(LEON3_VERSION),
"leon3_" & tost(hindex) & ": icache " & tost(isets*icen) & "*" & tost(isetsize*icen) &
" kbyte, dcache " & tost(dsets*dcen) & "*" & tost(dsetsize*dcen) & " kbyte"
);
-- pragma translate_on
end;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.idram_components.all;
use work.idram_utils.all;
entity idram is
generic (
--Port types: 0 -> AXI4Lite, 1 -> AXI3, 2 -> AXI4
INSTR_PORT_TYPE : natural range 0 to 2 := 0;
DATA_PORT_TYPE : natural range 0 to 2 := 0;
WRITE_FIRST_MODE : natural range 0 to 1 := 0;
SIZE : integer := 32768;
RAM_WIDTH : integer := 32;
ADDR_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
instr_AWID : in std_logic_vector(13 downto 0);
instr_AWADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
instr_AWLEN : in std_logic_vector(7-(4*(INSTR_PORT_TYPE mod 2)) downto 0);
instr_AWSIZE : in std_logic_vector(2 downto 0);
instr_AWBURST : in std_logic_vector(1 downto 0);
instr_AWLOCK : in std_logic_vector(1 downto 0);
instr_AWCACHE : in std_logic_vector(3 downto 0);
instr_AWPROT : in std_logic_vector(2 downto 0);
instr_AWVALID : in std_logic;
instr_AWREADY : out std_logic;
instr_WID : in std_logic_vector(13 downto 0);
instr_WDATA : in std_logic_vector(RAM_WIDTH-1 downto 0);
instr_WSTRB : in std_logic_vector((RAM_WIDTH/8)-1 downto 0);
instr_WLAST : in std_logic;
instr_WVALID : in std_logic;
instr_WREADY : out std_logic;
instr_BID : out std_logic_vector(13 downto 0);
instr_BRESP : out std_logic_vector(1 downto 0);
instr_BVALID : out std_logic;
instr_BREADY : in std_logic;
instr_ARID : in std_logic_vector(13 downto 0);
instr_ARADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
instr_ARLEN : in std_logic_vector(7-(4*(INSTR_PORT_TYPE mod 2)) downto 0);
instr_ARSIZE : in std_logic_vector(2 downto 0);
instr_ARBURST : in std_logic_vector(1 downto 0);
instr_ARLOCK : in std_logic_vector(1 downto 0);
instr_ARCACHE : in std_logic_vector(3 downto 0);
instr_ARPROT : in std_logic_vector(2 downto 0);
instr_ARVALID : in std_logic;
instr_ARREADY : out std_logic;
instr_RID : out std_logic_vector(13 downto 0);
instr_RDATA : out std_logic_vector(RAM_WIDTH-1 downto 0);
instr_RRESP : out std_logic_vector(1 downto 0);
instr_RLAST : out std_logic;
instr_RVALID : out std_logic;
instr_RREADY : in std_logic;
data_AWID : in std_logic_vector(13 downto 0);
data_AWADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_AWLEN : in std_logic_vector(7-(4*(DATA_PORT_TYPE mod 2)) downto 0);
data_AWSIZE : in std_logic_vector(2 downto 0);
data_AWBURST : in std_logic_vector(1 downto 0);
data_AWLOCK : in std_logic_vector(1 downto 0);
data_AWCACHE : in std_logic_vector(3 downto 0);
data_AWPROT : in std_logic_vector(2 downto 0);
data_AWVALID : in std_logic;
data_AWREADY : out std_logic;
data_WID : in std_logic_vector(13 downto 0);
data_WDATA : in std_logic_vector(RAM_WIDTH-1 downto 0);
data_WSTRB : in std_logic_vector((RAM_WIDTH/8)-1 downto 0);
data_WLAST : in std_logic;
data_WVALID : in std_logic;
data_WREADY : out std_logic;
data_BID : out std_logic_vector(13 downto 0);
data_BRESP : out std_logic_vector(1 downto 0);
data_BVALID : out std_logic;
data_BREADY : in std_logic;
data_ARID : in std_logic_vector(13 downto 0);
data_ARADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_ARLEN : in std_logic_vector(7-(4*(DATA_PORT_TYPE mod 2)) downto 0);
data_ARSIZE : in std_logic_vector(2 downto 0);
data_ARBURST : in std_logic_vector(1 downto 0);
data_ARLOCK : in std_logic_vector(1 downto 0);
data_ARCACHE : in std_logic_vector(3 downto 0);
data_ARPROT : in std_logic_vector(2 downto 0);
data_ARVALID : in std_logic;
data_ARREADY : out std_logic;
data_RID : out std_logic_vector(13 downto 0);
data_RDATA : out std_logic_vector(RAM_WIDTH-1 downto 0);
data_RRESP : out std_logic_vector(1 downto 0);
data_RLAST : out std_logic;
data_RVALID : out std_logic;
data_RREADY : in std_logic
);
end entity idram;
architecture rtl of idram is
constant BYTES_PER_WORD : integer := RAM_WIDTH/8;
signal address : std_logic_vector(log2(SIZE/BYTES_PER_WORD)-1 downto 0);
signal write_en : std_logic;
signal instr_AWVALID_latched : std_logic;
signal instr_AWADDR_latched : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal instr_WVALID_latched : std_logic;
signal instr_WDATA_latched : std_logic_vector(RAM_WIDTH-1 downto 0);
signal instr_WSTRB_latched : std_logic_vector((RAM_WIDTH/8)-1 downto 0);
signal instr_AWREADY_internal : std_logic;
signal instr_WREADY_internal : std_logic;
signal instr_BVALID_internal : std_logic;
signal instr_ARREADY_internal : std_logic;
signal instr_RVALID_internal : std_logic;
signal instr_address : std_logic_vector(log2(SIZE/BYTES_PER_WORD)-1 downto 0);
signal instr_read_en : std_logic;
signal instr_write_en : std_logic;
signal instr_write_data : std_logic_vector(RAM_WIDTH-1 downto 0);
signal instr_byte_sel : std_logic_vector(RAM_WIDTH/8-1 downto 0);
signal instr_en : std_logic;
signal instr_read_resp_stalled : std_logic;
signal instr_write_resp_stalled : std_logic;
signal data_AWVALID_latched : std_logic;
signal data_AWADDR_latched : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal data_WVALID_latched : std_logic;
signal data_WDATA_latched : std_logic_vector(RAM_WIDTH-1 downto 0);
signal data_WSTRB_latched : std_logic_vector((RAM_WIDTH/8)-1 downto 0);
signal data_AWREADY_internal : std_logic;
signal data_WREADY_internal : std_logic;
signal data_BVALID_internal : std_logic;
signal data_ARREADY_internal : std_logic;
signal data_RVALID_internal : std_logic;
signal data_address : std_logic_vector(log2(SIZE/BYTES_PER_WORD)-1 downto 0);
signal data_read_en : std_logic;
signal data_write_en : std_logic;
signal data_write_data : std_logic_vector(RAM_WIDTH-1 downto 0);
signal data_byte_sel : std_logic_vector(RAM_WIDTH/8-1 downto 0);
signal data_en : std_logic;
signal data_read_resp_stalled : std_logic;
signal data_write_resp_stalled : std_logic;
begin
instr_RRESP <= (others => '0');
instr_BRESP <= (others => '0');
instr_ARREADY_internal <= (not reset) and
(not instr_read_resp_stalled) and
(not instr_AWVALID_latched) and
(not instr_WVALID_latched);
instr_ARREADY <= instr_ARREADY_internal;
instr_AWREADY_internal <= (not reset) and
(not instr_write_resp_stalled) and
(not instr_AWVALID_latched);
instr_AWREADY <= instr_AWREADY_internal;
instr_WREADY_internal <= instr_AWREADY_internal;
instr_WREADY <= (not reset) and
(not instr_write_resp_stalled) and
(not instr_WVALID_latched);
instr_address <=
instr_ARADDR(instr_address'left+log2(BYTES_PER_WORD) downto log2(BYTES_PER_WORD)) when
instr_read_en = '1' else
instr_AWADDR(data_address'left+log2(BYTES_PER_WORD) downto log2(BYTES_PER_WORD)) when instr_AWVALID_latched = '0' else
instr_AWADDR_latched(data_address'left+log2(BYTES_PER_WORD) downto log2(BYTES_PER_WORD));
instr_read_en <= instr_ARVALID and instr_ARREADY_internal;
instr_write_en <= ((instr_AWVALID and instr_AWREADY_internal) or instr_AWVALID_latched) and
((instr_WVALID and instr_WREADY_internal) or instr_WVALID_latched);
instr_write_data <= instr_WDATA when instr_WVALID_latched = '0' else
instr_WDATA_latched;
instr_byte_sel <= (others => '1') when instr_read_en = '1' else
instr_WSTRB when instr_WVALID_latched = '0' else
instr_WSTRB_latched;
instr_en <= instr_write_en or instr_read_en;
instr_read_resp_stalled <= instr_RVALID_internal and (not instr_RREADY);
instr_RVALID <= instr_RVALID_internal;
instr_write_resp_stalled <= instr_BVALID_internal and (not instr_BREADY);
instr_BVALID <= instr_BVALID_internal;
data_RRESP <= (others => '0');
data_BRESP <= (others => '0');
data_ARREADY_internal <= (not reset) and
(not data_read_resp_stalled) and
(not data_AWVALID_latched) and
(not data_WVALID_latched);
data_ARREADY <= data_ARREADY_internal;
data_AWREADY_internal <= (not reset) and
(not data_write_resp_stalled) and
(not data_AWVALID_latched);
data_AWREADY <= data_AWREADY_internal;
data_WREADY_internal <= data_AWREADY_internal;
data_WREADY <= (not reset) and
(not data_write_resp_stalled) and
(not data_WVALID_latched);
data_address <=
data_ARADDR(data_address'left+log2(BYTES_PER_WORD) downto log2(BYTES_PER_WORD)) when
data_read_en = '1' else
data_AWADDR(data_address'left+log2(BYTES_PER_WORD) downto log2(BYTES_PER_WORD)) when data_AWVALID_latched = '0' else
data_AWADDR_latched(data_address'left+log2(BYTES_PER_WORD) downto log2(BYTES_PER_WORD));
data_read_en <= data_ARVALID and data_ARREADY_internal;
data_write_en <= ((data_AWVALID and data_AWREADY_internal) or data_AWVALID_latched) and
((data_WVALID and data_WREADY_internal) or data_WVALID_latched);
data_write_data <= data_WDATA when data_WVALID_latched = '0' else
data_WDATA_latched;
data_byte_sel <= (others => '1') when data_read_en = '1' else
data_WSTRB when data_WVALID_latched = '0' else
data_WSTRB_latched;
data_en <= data_write_en or data_read_en;
data_read_resp_stalled <= data_RVALID_internal and (not data_RREADY);
data_RVALID <= data_RVALID_internal;
data_write_resp_stalled <= data_BVALID_internal and (not data_BREADY);
data_BVALID <= data_BVALID_internal;
instr_port : process(clk)
begin
if rising_edge(clk) then
if instr_AWVALID = '1' and instr_AWREADY_internal = '1' then
instr_AWVALID_latched <= '1';
instr_AWADDR_latched <= instr_AWADDR;
end if;
if instr_WVALID = '1' and instr_WREADY_internal = '1' then
instr_WVALID_latched <= '1';
instr_WDATA_latched <= instr_WDATA;
instr_WSTRB_latched <= instr_WSTRB;
end if;
if instr_write_en = '1' then
instr_AWVALID_latched <= '0';
instr_WVALID_latched <= '0';
end if;
if instr_RREADY = '1' then
instr_RVALID_internal <= '0';
end if;
if instr_read_en = '1' then
instr_RVALID_internal <= '1';
instr_RID <= instr_ARID;
end if;
if instr_BREADY = '1' then
instr_BVALID_internal <= '0';
end if;
if instr_write_en = '1' then
instr_BVALID_internal <= '1';
instr_BID <= instr_AWID;
end if;
if reset = '1' then
instr_AWVALID_latched <= '0';
instr_WVALID_latched <= '0';
instr_RVALID_internal <= '0';
instr_BVALID_internal <= '0';
end if;
end if;
end process;
data_port : process(clk)
begin
if rising_edge(clk) then
if data_AWVALID = '1' and data_AWREADY_internal = '1' then
data_AWVALID_latched <= '1';
data_AWADDR_latched <= data_AWADDR;
end if;
if data_WVALID = '1' and data_WREADY_internal = '1' then
data_WVALID_latched <= '1';
data_WDATA_latched <= data_WDATA;
data_WSTRB_latched <= data_WSTRB;
end if;
if data_write_en = '1' then
data_AWVALID_latched <= '0';
data_WVALID_latched <= '0';
end if;
if data_RREADY = '1' then
data_RVALID_internal <= '0';
end if;
if data_read_en = '1' then
data_RVALID_internal <= '1';
data_RID <= data_ARID;
end if;
if data_BREADY = '1' then
data_BVALID_internal <= '0';
end if;
if data_write_en = '1' then
data_BVALID_internal <= '1';
data_BID <= data_AWID;
end if;
if reset = '1' then
data_AWVALID_latched <= '0';
data_WVALID_latched <= '0';
data_RVALID_internal <= '0';
data_BVALID_internal <= '0';
end if;
end if;
end process;
ram : component idram_behav
generic map (
RAM_DEPTH => SIZE/4,
RAM_WIDTH => RAM_WIDTH,
WRITE_FIRST => (WRITE_FIRST_MODE /= 0)
)
port map (
clk => clk,
instr_address => instr_address,
instr_data_in => instr_write_data,
instr_we => instr_write_en,
instr_en => instr_en,
instr_be => instr_byte_sel,
instr_readdata => instr_RDATA,
data_address => data_address,
data_data_in => data_write_data,
data_we => data_write_en,
data_en => data_en,
data_be => data_byte_sel,
data_readdata => data_RDATA
);
--Only valid for A4L, needs fixing for AXI3/AXI4
instr_RLAST <= '1';
data_RLAST <= '1';
end architecture rtl;
|
----------------------------------------------------------------------------------------------------
-- Reduce Test-bench
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.reduce_pkg.all;
--This module is a test-bench for simulating the reduce operation
entity tb_reduce is
end tb_reduce;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture sim of tb_reduce is
signal rst : std_logic;
signal clk : std_logic;
signal count_data : std_logic_vector(2 downto 0);
signal result_and : std_logic;
signal result_or : std_logic;
signal result_xor : std_logic;
signal result_nand : std_logic;
signal result_nor : std_logic;
signal result_xnor : std_logic;
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 30ns,
DUTY_CYCLE => 0.50)
port map( clk => clk);
--count_process
counter: process(clk, rst)
variable counter : unsigned(count_data'range) := (others => '0');
begin
if(rst = '1') then
counter := (others => '0');
else
if(rising_edge(clk)) then
counter := counter + 1;
end if;
end if;
count_data <= std_logic_vector(counter);
end process;
--UUT
reduce_and_test : reduce_and
port map(data => count_data,
result => result_and);
reduce_or_test : reduce_or
port map(data => count_data,
result => result_or);
reduce_xor_test : reduce_xor
port map(data => count_data,
result => result_xor);
reduce_nand_test : reduce_nand
port map(data => count_data,
result => result_nand);
reduce_nor_test : reduce_nor
port map(data => count_data,
result => result_nor);
reduce_xnor_test : reduce_xnor
port map(data => count_data,
result => result_xnor);
--Main Process
main: process
begin
rst <= '1';
wait for 50ns;
rst <= '0';
wait;
end process;
end sim;
|
---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * added a memory mapped register for counter value
-- * added necessary signals for the above mentioned register to the interface!
-- * COUNT_VALUE is replaced with count_value_sig which comes from the above mentioned register
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(9 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(9 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal count_value_reg_in, count_value_reg: std_logic_vector(31 downto 0);
signal old_address : std_logic_vector(31 downto 2);
signal count_value_sig : std_logic_vector(9 downto 0);
begin
-- added by siavoosh payandeh azad
update_count_value: process(count_value_reg, reg_data_write, reg_write_byte_enable, reg_address, reg_enable)begin
count_value_reg_in <= count_value_reg ;
if reg_enable = '1' and reg_address = uart_count_value_address then
if reg_write_byte_enable(0) = '1' then
count_value_reg_in(7 downto 0) <= reg_data_write(7 downto 0);
end if;
if reg_write_byte_enable(1) = '1' then
count_value_reg_in(15 downto 8) <= reg_data_write(15 downto 8);
end if;
if reg_write_byte_enable(2) = '1' then
count_value_reg_in(23 downto 16) <= reg_data_write(23 downto 16);
end if;
if reg_write_byte_enable(3) = '1' then
count_value_reg_in(31 downto 24) <= reg_data_write(31 downto 24);
end if;
end if;
end process;
process(count_value_reg, old_address) begin
if old_address = uart_count_value_address then
reg_data_read <= count_value_reg;
else
reg_data_read <= (others => 'U');
end if;
end process;
process(clk, reset, count_value_reg_in, reg_address)begin
if reset = '1' then
old_address <= (others => '0');
count_value_reg <= (others => '0');
elsif rising_edge(clk) then
old_address <= reg_address;
count_value_reg <= count_value_reg_in;
end if;
end process;
count_value_sig <= count_value_reg(9 downto 0);
-- end of updates by Siavoosh Payandeh Azad
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg,
busy_write_sig, uart_read)
-----------------------------------------------
--- MUST BE EDITED BASED ON THE FREQUENCY! ----
-----------------------------------------------
-- constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
-- "0100011110"; --33MHz/2/57600Hz = 0x11e
-- "1101100100"; --50MHz/57600Hz = 0x364
-- "0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0011011001"; --12.5MHz/57600Hz = 0xd9
-- "0000000100"; --for debug (shorten read_value_reg)
begin
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(9 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(9 downto 0);
data_save_reg <= ZERO(17 downto 0);
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(9 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
--if delay_write_reg /= COUNT_VALUE then
if delay_write_reg /= count_value_sig then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(9 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Read UART
if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read = '0' then --wait for start bit
--delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
delay_read_reg <= '0' & count_value_sig(9 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
--delay_read_reg <= COUNT_VALUE; --initialize delay
delay_read_reg <= count_value_sig; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
--if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if bits_read_reg = "0000" and delay_read_reg = count_value_sig then
if data_save_reg(8) = '0' or
(enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
--and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synthesis_off
-- uart_logger:
-- if log_file /= "UNUSED" generate
-- uart_proc: process(clk, enable_write, data_in)
-- file store_file : text open write_mode is log_file;
-- variable hex_file_line : line;
-- variable c : character;
-- variable index : natural;
-- variable line_length : natural := 0;
-- begin
-- if rising_edge(clk) and busy_write_sig = '0' then
-- if enable_write = '1' then
-- index := conv_integer(data_in(6 downto 0));
-- if index /= 10 then
-- c := character'val(index);
-- write(hex_file_line, c);
-- line_length := line_length + 1;
-- end if;
-- if index = 10 or line_length >= 72 then
-- --The following line may have to be commented out for synthesis
-- writeline(store_file, hex_file_line);
-- line_length := 0;
-- end if;
-- end if; --uart_sel
-- end if; --rising_edge(clk)
-- end process; --uart_proc
-- end generate; --uart_logger
-- synthesis_on
--synthesis_off
-- uart_logger:
-- if log_file /= "UNUSED" generate
-- uart_proc: process(clk, enable_read, data_save_reg)
-- file store_file : text open write_mode is log_file;
-- variable hex_file_line : line;
-- variable c : character;
-- variable index : natural;
-- variable line_length : natural := 0;
-- begin
-- if rising_edge(clk) and enable_read = '1' then
-- if data_save_reg(8) = '1' then
-- index := conv_integer(data_save_reg(7 downto 0));
-- if index /= 10 then
-- c := character'val(index);
-- write(hex_file_line, c);
-- line_length := line_length + 1;
-- end if;
-- if index = 10 or line_length >= 72 then
----The following line may have to be commented out for synthesis
-- writeline(store_file, hex_file_line);
-- line_length := 0;
-- end if;
-- end if; --uart_sel
-- end if; --rising_edge(clk)
-- end process; --uart_proc
-- end generate; --uart_logger
----synthesis_on
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * added a memory mapped register for counter value
-- * added necessary signals for the above mentioned register to the interface!
-- * COUNT_VALUE is replaced with count_value_sig which comes from the above mentioned register
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(9 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(9 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal count_value_reg_in, count_value_reg: std_logic_vector(31 downto 0);
signal old_address : std_logic_vector(31 downto 2);
signal count_value_sig : std_logic_vector(9 downto 0);
begin
-- added by siavoosh payandeh azad
update_count_value: process(count_value_reg, reg_data_write, reg_write_byte_enable, reg_address, reg_enable)begin
count_value_reg_in <= count_value_reg ;
if reg_enable = '1' and reg_address = uart_count_value_address then
if reg_write_byte_enable(0) = '1' then
count_value_reg_in(7 downto 0) <= reg_data_write(7 downto 0);
end if;
if reg_write_byte_enable(1) = '1' then
count_value_reg_in(15 downto 8) <= reg_data_write(15 downto 8);
end if;
if reg_write_byte_enable(2) = '1' then
count_value_reg_in(23 downto 16) <= reg_data_write(23 downto 16);
end if;
if reg_write_byte_enable(3) = '1' then
count_value_reg_in(31 downto 24) <= reg_data_write(31 downto 24);
end if;
end if;
end process;
process(count_value_reg, old_address) begin
if old_address = uart_count_value_address then
reg_data_read <= count_value_reg;
else
reg_data_read <= (others => 'U');
end if;
end process;
process(clk, reset, count_value_reg_in, reg_address)begin
if reset = '1' then
old_address <= (others => '0');
count_value_reg <= (others => '0');
elsif rising_edge(clk) then
old_address <= reg_address;
count_value_reg <= count_value_reg_in;
end if;
end process;
count_value_sig <= count_value_reg(9 downto 0);
-- end of updates by Siavoosh Payandeh Azad
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg,
busy_write_sig, uart_read)
-----------------------------------------------
--- MUST BE EDITED BASED ON THE FREQUENCY! ----
-----------------------------------------------
-- constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
-- "0100011110"; --33MHz/2/57600Hz = 0x11e
-- "1101100100"; --50MHz/57600Hz = 0x364
-- "0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0011011001"; --12.5MHz/57600Hz = 0xd9
-- "0000000100"; --for debug (shorten read_value_reg)
begin
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(9 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(9 downto 0);
data_save_reg <= ZERO(17 downto 0);
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(9 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
--if delay_write_reg /= COUNT_VALUE then
if delay_write_reg /= count_value_sig then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(9 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Read UART
if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read = '0' then --wait for start bit
--delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
delay_read_reg <= '0' & count_value_sig(9 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
--delay_read_reg <= COUNT_VALUE; --initialize delay
delay_read_reg <= count_value_sig; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
--if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if bits_read_reg = "0000" and delay_read_reg = count_value_sig then
if data_save_reg(8) = '0' or
(enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
--and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synthesis_off
-- uart_logger:
-- if log_file /= "UNUSED" generate
-- uart_proc: process(clk, enable_write, data_in)
-- file store_file : text open write_mode is log_file;
-- variable hex_file_line : line;
-- variable c : character;
-- variable index : natural;
-- variable line_length : natural := 0;
-- begin
-- if rising_edge(clk) and busy_write_sig = '0' then
-- if enable_write = '1' then
-- index := conv_integer(data_in(6 downto 0));
-- if index /= 10 then
-- c := character'val(index);
-- write(hex_file_line, c);
-- line_length := line_length + 1;
-- end if;
-- if index = 10 or line_length >= 72 then
-- --The following line may have to be commented out for synthesis
-- writeline(store_file, hex_file_line);
-- line_length := 0;
-- end if;
-- end if; --uart_sel
-- end if; --rising_edge(clk)
-- end process; --uart_proc
-- end generate; --uart_logger
-- synthesis_on
--synthesis_off
-- uart_logger:
-- if log_file /= "UNUSED" generate
-- uart_proc: process(clk, enable_read, data_save_reg)
-- file store_file : text open write_mode is log_file;
-- variable hex_file_line : line;
-- variable c : character;
-- variable index : natural;
-- variable line_length : natural := 0;
-- begin
-- if rising_edge(clk) and enable_read = '1' then
-- if data_save_reg(8) = '1' then
-- index := conv_integer(data_save_reg(7 downto 0));
-- if index /= 10 then
-- c := character'val(index);
-- write(hex_file_line, c);
-- line_length := line_length + 1;
-- end if;
-- if index = 10 or line_length >= 72 then
----The following line may have to be commented out for synthesis
-- writeline(store_file, hex_file_line);
-- line_length := 0;
-- end if;
-- end if; --uart_sel
-- end if; --rising_edge(clk)
-- end process; --uart_proc
-- end generate; --uart_logger
----synthesis_on
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * added a memory mapped register for counter value
-- * added necessary signals for the above mentioned register to the interface!
-- * COUNT_VALUE is replaced with count_value_sig which comes from the above mentioned register
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(9 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(9 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal count_value_reg_in, count_value_reg: std_logic_vector(31 downto 0);
signal old_address : std_logic_vector(31 downto 2);
signal count_value_sig : std_logic_vector(9 downto 0);
begin
-- added by siavoosh payandeh azad
update_count_value: process(count_value_reg, reg_data_write, reg_write_byte_enable, reg_address, reg_enable)begin
count_value_reg_in <= count_value_reg ;
if reg_enable = '1' and reg_address = uart_count_value_address then
if reg_write_byte_enable(0) = '1' then
count_value_reg_in(7 downto 0) <= reg_data_write(7 downto 0);
end if;
if reg_write_byte_enable(1) = '1' then
count_value_reg_in(15 downto 8) <= reg_data_write(15 downto 8);
end if;
if reg_write_byte_enable(2) = '1' then
count_value_reg_in(23 downto 16) <= reg_data_write(23 downto 16);
end if;
if reg_write_byte_enable(3) = '1' then
count_value_reg_in(31 downto 24) <= reg_data_write(31 downto 24);
end if;
end if;
end process;
process(count_value_reg, old_address) begin
if old_address = uart_count_value_address then
reg_data_read <= count_value_reg;
else
reg_data_read <= (others => 'U');
end if;
end process;
process(clk, reset, count_value_reg_in, reg_address)begin
if reset = '1' then
old_address <= (others => '0');
count_value_reg <= (others => '0');
elsif rising_edge(clk) then
old_address <= reg_address;
count_value_reg <= count_value_reg_in;
end if;
end process;
count_value_sig <= count_value_reg(9 downto 0);
-- end of updates by Siavoosh Payandeh Azad
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg,
busy_write_sig, uart_read)
-----------------------------------------------
--- MUST BE EDITED BASED ON THE FREQUENCY! ----
-----------------------------------------------
-- constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
-- "0100011110"; --33MHz/2/57600Hz = 0x11e
-- "1101100100"; --50MHz/57600Hz = 0x364
-- "0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0011011001"; --12.5MHz/57600Hz = 0xd9
-- "0000000100"; --for debug (shorten read_value_reg)
begin
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(9 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(9 downto 0);
data_save_reg <= ZERO(17 downto 0);
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(9 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
--if delay_write_reg /= COUNT_VALUE then
if delay_write_reg /= count_value_sig then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(9 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Read UART
if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read = '0' then --wait for start bit
--delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
delay_read_reg <= '0' & count_value_sig(9 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
--delay_read_reg <= COUNT_VALUE; --initialize delay
delay_read_reg <= count_value_sig; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
--if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if bits_read_reg = "0000" and delay_read_reg = count_value_sig then
if data_save_reg(8) = '0' or
(enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
--and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synthesis_off
-- uart_logger:
-- if log_file /= "UNUSED" generate
-- uart_proc: process(clk, enable_write, data_in)
-- file store_file : text open write_mode is log_file;
-- variable hex_file_line : line;
-- variable c : character;
-- variable index : natural;
-- variable line_length : natural := 0;
-- begin
-- if rising_edge(clk) and busy_write_sig = '0' then
-- if enable_write = '1' then
-- index := conv_integer(data_in(6 downto 0));
-- if index /= 10 then
-- c := character'val(index);
-- write(hex_file_line, c);
-- line_length := line_length + 1;
-- end if;
-- if index = 10 or line_length >= 72 then
-- --The following line may have to be commented out for synthesis
-- writeline(store_file, hex_file_line);
-- line_length := 0;
-- end if;
-- end if; --uart_sel
-- end if; --rising_edge(clk)
-- end process; --uart_proc
-- end generate; --uart_logger
-- synthesis_on
--synthesis_off
-- uart_logger:
-- if log_file /= "UNUSED" generate
-- uart_proc: process(clk, enable_read, data_save_reg)
-- file store_file : text open write_mode is log_file;
-- variable hex_file_line : line;
-- variable c : character;
-- variable index : natural;
-- variable line_length : natural := 0;
-- begin
-- if rising_edge(clk) and enable_read = '1' then
-- if data_save_reg(8) = '1' then
-- index := conv_integer(data_save_reg(7 downto 0));
-- if index /= 10 then
-- c := character'val(index);
-- write(hex_file_line, c);
-- line_length := line_length + 1;
-- end if;
-- if index = 10 or line_length >= 72 then
----The following line may have to be commented out for synthesis
-- writeline(store_file, hex_file_line);
-- line_length := 0;
-- end if;
-- end if; --uart_sel
-- end if; --rising_edge(clk)
-- end process; --uart_proc
-- end generate; --uart_logger
----synthesis_on
end; --architecture logic
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture behavior of {{entity_name}} is
begin
end behavior;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture behavior of {{entity_name}} is
begin
end behavior;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbps2
-- File: apbps2.vhd
-- Author: Marcus Hellqvist, Jiri Gaisler
-- Modified by: Jan Andersson
-- Description: PS/2 keyboard interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity apbps2 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 0;
oepol : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end;
architecture rtl of apbps2 is
constant fifosize : integer := 16;
type rxstates is (idle,start,data,parity,stop);
type txstates is (idle,waitrequest,start,data,parity,stop,ack);
type fifotype is array(0 to fifosize-1) of std_logic_vector(7 downto 0);
type ps2_regs is record
-- status reg
data_ready : std_ulogic; -- data ready
parity_error : std_ulogic; -- parity carry out/ error bit
frame_error : std_ulogic; -- frame error when receiving
kb_inh : std_ulogic; -- keyboard inhibit
rbf : std_ulogic; -- receiver buffer full
tbf : std_ulogic; -- transmitter buffer full
rcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
tcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
-- control reg
rx_en : std_ulogic; -- receive enable
tx_en : std_ulogic; -- transmit enable
rx_irq_en : std_ulogic; -- keyboard interrupt enable
tx_irq_en : std_ulogic; -- transmit interrupt enable
-- others
tx_act : std_ulogic; -- tx active
rxdf : std_logic_vector(4 downto 0); -- rx data filter
rxcf : std_logic_vector(4 downto 0); -- rx clock filter
rx_irq : std_ulogic; -- keyboard interrupt
tx_irq : std_ulogic; -- transmit interrupt
rxfifo : fifotype; -- fifo with 16 bytes
rraddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
rwaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
rxstate : rxstates;
txfifo : fifotype; -- fifo with 16 bytes
traddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
twaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
txstate : txstates;
ps2_clk_syn : std_ulogic; -- ps2 clock synchronized
ps2_data_syn : std_ulogic; -- ps2 data synchronized
ps2_clk_fall : std_ulogic; -- ps2 clock falling edge detector
rshift : std_logic_vector(7 downto 0); -- shift register
rpar : std_ulogic; -- parity check bit
tshift : std_logic_vector(9 downto 0); -- shift register
tpar : std_ulogic; -- transmit parity bit
ps2clk : std_ulogic; -- ps2 clock
ps2data : std_ulogic; -- ps2 data
ps2clkoe : std_ulogic; -- ps2 clock output enable
ps2dataoe : std_ulogic; -- ps2 data output enable
timer : std_logic_vector(16 downto 0); -- timer
reload : std_logic_vector(16 downto 0); -- reload register
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
constant REVISION : integer := 2;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBPS2, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1);
constant INPUT : std_ulogic := conv_std_logic(oepol = 0);
signal r, rin : ps2_regs;
signal ps2_clk, ps2_data : std_ulogic;
begin
ps2_op : process(r, rst, ps2_clk, ps2_data,apbi)
variable v : ps2_regs;
variable rdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r;
rdata := (others => '0'); v.data_ready := '0'; irq := (others => '0'); irq(pirq) := r.rx_irq or r.tx_irq;
v.rx_irq := '0'; v.tx_irq := '0'; v.rbf := r.rcnt(log2x(fifosize)); v.tbf := r.tcnt(log2x(fifosize));
if r.rcnt /= rcntzero then v.data_ready := '1'; end if;
-- Synchronize and filter ps2 input
v.rxdf(0) := ps2_data; v.rxdf(4 downto 1) := r.rxdf(3 downto 0);
v.rxcf(0) := ps2_clk; v.rxcf(4 downto 1) := r.rxcf(3 downto 0);
if (r.rxdf(4) & r.rxdf(4) & r.rxdf(4) & r.rxdf(4)) = r.rxdf(3 downto 0) then
v.ps2_data_syn := r.rxdf(4);
end if;
if (r.rxcf(4) & r.rxcf(4) & r.rxcf(4) & r.rxcf(4)) = r.rxcf(3 downto 0) then
v.ps2_clk_syn := r.rxcf(4);
end if;
if (v.ps2_clk_syn /= r.ps2_clk_syn) and (v.ps2_clk_syn = '0') then
v.ps2_clk_fall := '1';
else
v.ps2_clk_fall := '0';
end if;
-- read registers
case apbi.paddr(3 downto 2) is
when "00" =>
rdata(7 downto 0) := r.rxfifo(conv_integer(r.rraddr));
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
if r.rcnt /= rcntzero then
v.rxfifo(conv_integer(r.rraddr)) := (others => '0');
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "01" =>
rdata(27 + log2x(fifosize) downto 27) := r.rcnt;
rdata(22 + log2x(fifosize) downto 22) := r.tcnt;
rdata(5 downto 0) := r.tbf & r.rbf & r.kb_inh & r.frame_error & r.parity_error & r.data_ready;
when "10" =>
rdata(3 downto 0) := r.tx_irq_en & r.rx_irq_en & r.tx_en & r.rx_en;
when others =>
if fixed = 0 then rdata(r.reload'range) := r.reload; end if;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
if r.tcnt(log2x(fifosize)) = '0' then
v.txfifo(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
v.twaddr := r.twaddr + 1; v.tcnt := r.tcnt + 1;
end if;
when "01" =>
v.kb_inh := apbi.pwdata(3);
v.frame_error := apbi.pwdata(2);
v.parity_error := apbi.pwdata(1);
when "10" =>
v.tx_irq_en := apbi.pwdata(3);
v.rx_irq_en := apbi.pwdata(2);
v.tx_en := apbi.pwdata(1);
v.rx_en := apbi.pwdata(0);
when "11" =>
if fixed = 0 then
v.reload := apbi.pwdata(r.reload'range);
end if;
when others =>
null;
end case;
end if;
case r.txstate is
when idle =>
if r.tx_en = '1' and r.tcnt /= rcntzero then
v.ps2clk := '0'; v.ps2clkoe := OUTPUT; v.tx_act := '1';
v.ps2data := '1'; v.ps2dataoe := OUTPUT; v.txstate := waitrequest;
if fixed = 1 then v.timer := conv_std_logic_vector(fKHz/10,r.timer'length);
else v.timer := r.reload; end if;
end if;
when waitrequest =>
v.timer := r.timer - 1;
if (v.timer(r.timer'left) and not r.timer(r.timer'left)) = '1' then
v.ps2data := '0'; v.txstate := start;
end if;
when start =>
v.ps2clkoe := INPUT; v.ps2clk := '1';
v.tshift := "10" & r.txfifo(conv_integer(r.traddr));
v.traddr := r.traddr + 1; v.tcnt := r.tcnt - 1;
v.tpar := '1';
v.txstate := data;
when data =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tshift(0);
v.tpar := r.tpar xor r.tshift(0);
v.tshift := '1' & r.tshift(9 downto 1);
if v.tshift = "1111111110" then v.txstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tpar; v.txstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
v.ps2data := '1'; v.txstate := ack;
end if;
when ack =>
v.ps2dataoe := INPUT;
if r.ps2_clk_fall = '1' and r.ps2_data_syn = '0'then
v.ps2data := '1'; v.ps2dataoe := OUTPUT; v.tx_irq := r.tx_irq_en;
v.txstate := idle; v.tx_act := '0';
end if;
end case;
-- receiver state machine
case r.rxstate is
when idle =>
if (r.rx_en and not r.tx_act) = '1' then
v.rshift := (others => '1'); v.rxstate := start;
end if;
when start =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '0' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rxstate := data; v.rpar := '0';
v.parity_error := '0'; v.frame_error := '0';
else v.rxstate := idle; end if;
end if;
when data =>
if r.ps2_clk_fall = '1' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rpar := r.rpar xor r.ps2_data_syn;
if r.rshift(0) = '0' then v.rxstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.parity_error := r.rpar xor (not r.ps2_data_syn);
v.rxstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '1' then
v.rx_irq := r.rx_irq_en; v.rxstate := idle;
if (r.rbf or r.parity_error) = '0' then
v.rxfifo(conv_integer(r.rwaddr)) := r.rshift(7 downto 0);
v.rwaddr := r.rwaddr + 1; v.rcnt := r.rcnt + 1;
end if;
else v.frame_error := '1'; v.rxstate := idle; end if;
end if;
end case;
-- keyboard inhibit / high impedance
if v.tx_act = '0' then
if r.rbf = '1' then
v.kb_inh := '1'; v.ps2clk := '0'; v.ps2data := '1';
v.ps2dataoe := OUTPUT; v.ps2clkoe := OUTPUT;
else
v.ps2clk := '1'; v.ps2data := '1'; v.ps2dataoe := INPUT;
v.ps2clkoe := INPUT;
end if;
end if;
if r.tx_act = '1' then
v.rxstate := idle;
end if;
-- reset operations
if rst = '0' then
v.data_ready := '0'; v.kb_inh := '0'; v.parity_error := '0';
v.frame_error := '0'; v.rx_en := '0'; v.tx_act := '0';
v.tx_en := '0'; v.rx_irq := '0'; v.tx_irq := '0';
v.ps2_clk_fall := '0'; v.ps2_clk_syn := '0'; v.ps2_data_syn := '0';
v.rshift := (others => '0'); v.rxstate := idle; v.txstate := idle;
v.rraddr := (others => '0'); v.rwaddr := (others => '0');
v.rcnt := (others => '0'); v.traddr := (others => '0');
v.twaddr := (others => '0'); v.tcnt := (others => '0');
v.tshift := (others => '0'); v.tpar := '0';
if fixed = 0 then
v.reload := conv_std_logic_vector(fKHz/10,r.reload'length);
end if;
end if;
if fixed = 1 then v.reload := (others => '0'); end if;
-- update registers
rin <= v;
-- drive outputs
apbo.prdata <= rdata;
apbo.pirq <= irq;
apbo.pindex <= pindex;
ps2o.ps2_clk_o <= r.ps2clk;
ps2o.ps2_clk_oe <= r.ps2clkoe;
ps2o.ps2_data_o <= r.ps2data;
ps2o.ps2_data_oe <= r.ps2dataoe;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
ps2_data <= to_x01(ps2i.ps2_data_i);
ps2_clk <= to_x01(ps2i.ps2_clk_i);
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbps2_" & tost(pindex) & ": APB PS2 interface rev " &
tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: test bench for the FPU core
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: jidan@gmx.net
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use std.textio.all;
use work.txt_util.all;
-- fpu operations (fpu_op_i):
-- ========================
-- 000 = add,
-- 001 = substract,
-- 010 = multiply,
-- 011 = divide,
-- 100 = square root
-- 101 = unused
-- 110 = unused
-- 111 = unused
-- Rounding Mode:
-- ==============
-- 00 = round to nearest even(default),
-- 01 = round to zero,
-- 10 = round up,
-- 11 = round down
entity tb_fpu is
end tb_fpu;
architecture rtl of tb_fpu is
component fpu
port (
clk_i : in std_logic;
opa_i : in std_logic_vector(31 downto 0);
opb_i : in std_logic_vector(31 downto 0);
fpu_op_i : in std_logic_vector(2 downto 0);
rmode_i : in std_logic_vector(1 downto 0);
output_o : out std_logic_vector(31 downto 0);
ine_o : out std_logic;
overflow_o : out std_logic;
underflow_o : out std_logic;
div_zero_o : out std_logic;
inf_o : out std_logic;
zero_o : out std_logic;
qnan_o : out std_logic;
snan_o : out std_logic;
start_i : in std_logic;
ready_o : out std_logic
);
end component;
signal clk_i : std_logic:= '1';
signal opa_i, opb_i : std_logic_vector(31 downto 0);
signal fpu_op_i : std_logic_vector(2 downto 0);
signal rmode_i : std_logic_vector(1 downto 0);
signal output_o : std_logic_vector(31 downto 0);
signal start_i, ready_o : std_logic ;
signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o: std_logic;
signal slv_out : std_logic_vector(31 downto 0);
constant CLK_PERIOD :time := 10 ns; -- period of clk period
begin
-- instantiate fpu
i_fpu: fpu port map (
clk_i => clk_i,
opa_i => opa_i,
opb_i => opb_i,
fpu_op_i => fpu_op_i,
rmode_i => rmode_i,
output_o => output_o,
ine_o => ine_o,
overflow_o => overflow_o,
underflow_o => underflow_o,
div_zero_o => div_zero_o,
inf_o => inf_o,
zero_o => zero_o,
qnan_o => qnan_o,
snan_o => snan_o,
start_i => start_i,
ready_o => ready_o);
---------------------------------------------------------------------------
-- toggle clock
---------------------------------------------------------------------------
clk_i <= not(clk_i) after 5 ns;
verify : process
--The operands and results are in Hex format. The test vectors must be placed in a strict order for the verfication to work.
file testcases_file: TEXT open read_mode is "testcases.txt"; --Name of the file containing the test cases.
variable file_line: line;
variable str_in: string(8 downto 1);
variable str_fpu_op: string(3 downto 1);
variable str_rmode: string(2 downto 1);
begin
---------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------SoftFloat test vectors (10000 test cases for each operation) --------------------------------------------------------------------
start_i <= '0';
while not endfile(testcases_file) loop
wait for CLK_PERIOD; start_i <= '1';
str_read(testcases_file,str_in);
opa_i <= strhex_to_slv(str_in);
str_read(testcases_file,str_in);
opb_i <= strhex_to_slv(str_in);
str_read(testcases_file,str_fpu_op);
fpu_op_i <= to_std_logic_vector(str_fpu_op);
str_read(testcases_file,str_rmode);
rmode_i <= to_std_logic_vector(str_rmode);
str_read(testcases_file,str_in);
slv_out <= strhex_to_slv(str_in);
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
assert output_o = slv_out
report "Error!!!"
severity failure;
str_read(testcases_file,str_in);
end loop;
-------- Boundary values-----
start_i <= '0';
-- seeeeeeeefffffffffffffffffffffff
--infinity
wait for CLK_PERIOD; start_i <= '1';
opa_i <= "01111111011111111111111111111111";
opb_i <= "01111111011111111111111111111111";
fpu_op_i <= "000";
rmode_i <= "00";
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
assert output_o="01111111100000000000000000000000"
report "Error!!!"
severity failure;
-- seeeeeeeefffffffffffffffffffffff
-- 1 x1.001 - 1x1.000 = 0x0.001
wait for CLK_PERIOD; start_i <= '1';
opa_i <= "00000000100100000000000000000000";
opb_i <= "10000000100000000000000000000000";
fpu_op_i <= "000";
rmode_i <= "00";
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
assert output_o="00000000000100000000000000000000"
report "Error!!!"
severity failure;
-- seeeeeeeefffffffffffffffffffffff
-- 10 x 1.0001 - 10 x 1.0000 =
wait for CLK_PERIOD; start_i <= '1';
opa_i <= "00000001000010000000000000000000";
opb_i <= "10000001000000000000000000000000";
fpu_op_i <= "000";
rmode_i <= "00";
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
assert output_o="00000000000100000000000000000000"
report "Error!!!"
severity failure;
-- seeeeeeeefffffffffffffffffffffff
-- -0 -0 = -0
wait for CLK_PERIOD; start_i <= '1';
opa_i <= "10000000000000000000000000000000";
opb_i <= "10000000000000000000000000000000";
fpu_op_i <= "000";
rmode_i <= "00";
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
assert output_o="10000000000000000000000000000000"
report "Error!!!"
severity failure;
-- seeeeeeeefffffffffffffffffffffff
-- 0 + x = x
wait for CLK_PERIOD; start_i <= '1';
opa_i <= "00000000000000000000000000000000";
opb_i <= "01000010001000001000000000100000";
fpu_op_i <= "000";
rmode_i <= "00";
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
assert output_o="01000010001000001000000000100000"
report "Error!!!"
severity failure;
----------------------------------------------------------------------------------------------------------------------------------------------------
assert false
report "Success!!!.......Yahoooooooooooooo"
severity failure;
wait;
end process verify;
end rtl; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity uc01 is
port(
clkuc: in std_logic ;
inACuc: in std_logic_vector ( 7 downto 0 );
FlagInstuc: inout std_logic ;
outACuc: out std_logic_vector ( 7 downto 0 );
FlagReadyuc: out std_logic );
end;
architecture uc0 of uc01 is
signal sinACuc: std_logic_vector(7 downto 0);
begin
puc: process(clkuc, inACuc, FlagInstuc)
begin
if (clkuc'event and clkuc = '1') then
if (FlagInstuc = '1') then
sinACuc <= inACuc;
outACuc <= sinACuc;
FlagReadyuc <= '1';
elsif (FlagInstuc = '0') then
FlagReadyuc <= '0';
end if;
end if;
end process puc;
end uc0;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNAGWQMRGS is
generic ( decode : string := "000000000000000000000000";
pipeline : natural := 0;
width : natural := 24);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNAGWQMRGS is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 24,
decode => "000000000000000000000000",
pipeline => 0)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNAGWQMRGS is
generic ( decode : string := "000000000000000000000000";
pipeline : natural := 0;
width : natural := 24);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNAGWQMRGS is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 24,
decode => "000000000000000000000000",
pipeline => 0)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; |
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NCEtZRCbmu5HES1IfhU=
`protect end_protected
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:40:58 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Documents/Frecuencimetroo/Frecuencimentro/divisor_tb.vhd
-- Project Name: Frecuencimentro
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Divisor
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY divisor_tb IS
END divisor_tb;
ARCHITECTURE behavior OF divisor_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Divisor
PORT(
activacion : IN std_logic;
entrada : IN std_logic_vector(0 to 31);
escala : IN std_logic_vector(0 to 9);
salida : OUT std_logic_vector(0 to 31)
);
END COMPONENT;
--Inputs
signal activacion : std_logic := '0';
signal entrada : std_logic_vector(0 to 31) := (others => '0');
signal escala : std_logic_vector(0 to 9) := (others => '0');
--Outputs
signal salida : std_logic_vector(0 to 31);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Divisor PORT MAP (
activacion => activacion,
entrada => entrada,
escala => escala,
salida => salida
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
entrada<="00000000000000000000000000000100";
escala<="0000000010";
wait for 100 ns;
activacion<='1';
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:40:58 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Documents/Frecuencimetroo/Frecuencimentro/divisor_tb.vhd
-- Project Name: Frecuencimentro
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Divisor
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY divisor_tb IS
END divisor_tb;
ARCHITECTURE behavior OF divisor_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Divisor
PORT(
activacion : IN std_logic;
entrada : IN std_logic_vector(0 to 31);
escala : IN std_logic_vector(0 to 9);
salida : OUT std_logic_vector(0 to 31)
);
END COMPONENT;
--Inputs
signal activacion : std_logic := '0';
signal entrada : std_logic_vector(0 to 31) := (others => '0');
signal escala : std_logic_vector(0 to 9) := (others => '0');
--Outputs
signal salida : std_logic_vector(0 to 31);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Divisor PORT MAP (
activacion => activacion,
entrada => entrada,
escala => escala,
salida => salida
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
entrada<="00000000000000000000000000000100";
escala<="0000000010";
wait for 100 ns;
activacion<='1';
-- insert stimulus here
wait;
end process;
END;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_ok_9_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_9_e-rtl-a.vhd,v 1.1 2006/11/22 10:40:09 wig Exp $
-- $Date: 2006/11/22 10:40:09 $
-- $Log: inst_shadow_ok_9_e-rtl-a.vhd,v $
-- Revision 1.1 2006/11/22 10:40:09 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_shadow_ok_9_e
--
architecture rtl of inst_shadow_ok_9_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity HAZARD is
port(
Rt_IF_ID : in vl_logic_vector(4 downto 0);
Rs_IF_ID : in vl_logic_vector(4 downto 0);
Rt_ID_EX : in vl_logic_vector(4 downto 0);
RtRead_IF_ID : in vl_logic;
Jump : in vl_logic;
MemRead_ID_EX : in vl_logic;
Branch : in vl_logic;
PCSrc : out vl_logic_vector(1 downto 0);
IF_ID_Stall : out vl_logic;
IF_ID_Flush : out vl_logic;
ID_EX_Stall : out vl_logic;
ID_EX_Flush : out vl_logic;
EX_MEM_Stall : out vl_logic;
EX_MEM_Flush : out vl_logic;
MEM_REG_Stall : out vl_logic;
MEM_REG_Flush : out vl_logic;
loaduse : out vl_logic
);
end HAZARD;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3s
-- File: leon3s.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3s is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end;
architecture rtl of leon3s is
signal gnd, vcc : std_logic;
signal fpuo : grfpu_out_type;
begin
gnd <= '0'; vcc <= '1';
fpuo <= grfpu_out_none;
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp)
port map (
clk => gnd,
gclk2 => clk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => open,
fpuo => fpuo,
clken => vcc);
end;
|
-- highpass_filter.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.log2;
library utils_v1_00_a;
use utils_v1_00_a.ctl_bypass;
use utils_v1_00_a.adder_tree;
entity highpass_filter is
port (
CLK : in std_logic;
CE : in std_logic;
WIN_R : in std_logic_vector(9 * 8 - 1 downto 0);
WIN_G : in std_logic_vector(9 * 8 - 1 downto 0);
WIN_B : in std_logic_vector(9 * 8 - 1 downto 0);
WIN_DE : in std_logic_vector(8 downto 0);
WIN_HS : in std_logic_vector(8 downto 0);
WIN_VS : in std_logic_vector(8 downto 0);
OUT_R : out std_logic_vector(7 downto 0);
OUT_G : out std_logic_vector(7 downto 0);
OUT_B : out std_logic_vector(7 downto 0);
OUT_DE : out std_logic;
OUT_HS : out std_logic;
OUT_VS : out std_logic
);
end entity;
architecture impl_n1_2_n1 of highpass_filter is
constant VECTOR_LENGTH : integer := 3;
constant ADDER_LEVELS_COUNT : integer := log2(VECTOR_LENGTH);
---------------------------------
subtype mapped_t is std_logic_vector(7 downto 0);
---
-- Maps the input 10 bit signed number to output 8 bit unsigned number.
-- Mapping of x:
-- x > 0: y := x / 4
-- x < 0: y := abs(x) / 4
-- x = 0: y := 127
--
-- The value x = 0 should be mapped to 127.5. It is floored down to 127.
---
function map_to_range8(a : in std_logic_vector(9 downto 0)) return mapped_t is
variable val : integer;
variable res : std_logic_vector(9 downto 0);
variable y : std_logic_vector(7 downto 0);
begin
val := conv_integer(signed(a));
res := conv_std_logic_vector(val - (-510), 10);
y := res(9 downto 2);
return y;
end function;
---------------------------------
signal mul_r : std_logic_vector(VECTOR_LENGTH * 10 - 1 downto 0);
signal mul_g : std_logic_vector(VECTOR_LENGTH * 10 - 1 downto 0);
signal mul_b : std_logic_vector(VECTOR_LENGTH * 10 - 1 downto 0);
signal sum_r : std_logic_vector(9 downto 0);
signal sum_g : std_logic_vector(9 downto 0);
signal sum_b : std_logic_vector(9 downto 0);
signal sum_ce : std_logic;
begin
mul_r( 9 downto 0) <= not("00" & WIN_R(15 downto 8)) + 1;
mul_g( 9 downto 0) <= not("00" & WIN_G(15 downto 8)) + 1;
mul_b( 9 downto 0) <= not("00" & WIN_B(15 downto 8)) + 1;
mul_r(19 downto 10) <= "0" & WIN_R(39 downto 32) & "0";
mul_g(19 downto 10) <= "0" & WIN_G(39 downto 32) & "0";
mul_b(19 downto 10) <= "0" & WIN_B(39 downto 32) & "0";
mul_r(29 downto 20) <= not("00" & WIN_R(63 downto 56)) + 1;
mul_g(29 downto 20) <= not("00" & WIN_G(63 downto 56)) + 1;
mul_b(29 downto 20) <= not("00" & WIN_B(63 downto 56)) + 1;
---------------------------------
---
-- Sum of the results
---
adder_tree_r_i : entity utils_v1_00_a.adder_tree
generic map (
INPUT_COUNT => VECTOR_LENGTH,
DATA_WIDTH => 10
)
port map (
CLK => CLK,
CE => CE,
DIN => mul_r,
DOUT => sum_r
);
adder_tree_g_i : entity utils_v1_00_a.adder_tree
generic map (
INPUT_COUNT => VECTOR_LENGTH,
DATA_WIDTH => 10
)
port map (
CLK => CLK,
CE => CE,
DIN => mul_g,
DOUT => sum_g
);
adder_tree_b_i : entity utils_v1_00_a.adder_tree
generic map (
INPUT_COUNT => VECTOR_LENGTH,
DATA_WIDTH => 10
)
port map (
CLK => CLK,
CE => CE,
DIN => mul_b,
DOUT => sum_b
);
---------------------------------
OUT_R <= map_to_range8(sum_r);
OUT_G <= map_to_range8(sum_g);
OUT_B <= map_to_range8(sum_b);
---------------------------------
ctl_bypass_i : entity utils_v1_00_a.ctl_bypass
generic map (
DWIDTH => 3,
DEPTH => ADDER_LEVELS_COUNT
)
port map (
CLK => CLK,
CE => CE,
DI(0) => WIN_DE(4),
DI(1) => WIN_HS(4),
DI(2) => WIN_VS(4),
DO(0) => OUT_DE,
DO(1) => OUT_HS,
DO(2) => OUT_VS
);
end architecture;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY datapath IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
RESETX, RESETY, incr_y, incr_x, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0); -- x0
y : OUT STD_LOGIC_VECTOR(6 downto 0);
xin : IN STD_LOGIC_VECTOR(7 downto 0); -- x1
yin : IN STD_LOGIC_VECTOR(6 downto 0);
xdone, ydone, ldone : OUT STD_LOGIC
);
END datapath;
ARCHITECTURE mixed OF datapath IS
BEGIN
PROCESS(clock, resetb)
VARIABLE x_tmp : unsigned(7 downto 0) := "00000000";
VARIABLE y_tmp : unsigned(6 downto 0) := "0000000";
VARIABLE dx : signed(8 downto 0);
VARIABLE dy : signed(7 downto 0);
VARIABLE x0 : unsigned(7 downto 0) := "01010000"; -- 80
VARIABLE y0 : unsigned(6 downto 0) := "0111100"; -- 60
VARIABLE x1 : unsigned(7 downto 0) := "01010000";
VARIABLE y1 : unsigned(6 downto 0) := "0111100";
VARIABLE sx : signed(1 downto 0);
VARIABLE sy : signed(1 downto 0);
VARIABLE error : signed(8 downto 0);
VARIABLE e2 : signed(9 downto 0);
BEGIN
IF (resetb = '0') THEN
y_tmp := "0000000";
x_tmp := "00000000";
x0 := "01010000"; -- 80
y0 := "0111100"; -- 60
x1 := "01010000"; -- 80
y1 := "0111100"; -- 60
ELSIF rising_edge(clock) THEN
--initialize line
IF (initl = '1') THEN
x0 := x1; -- 80
y0 := y1; -- 60
x1 := unsigned(xin); -- destination
y1 := unsigned(yin);
dx := to_signed(abs(to_integer(x1) - to_integer(x0)), 9);
dy := to_signed(abs(to_integer(y1) - to_integer(y0)), 8);
IF (x0 < x1) THEN
sx := to_signed(1, 2);
ELSE
sx := to_signed(-1, 2);
END IF;
IF (y0 < y1) THEN
sy := to_signed(1, 2);
ELSE
sy := to_signed(-1, 2);
END IF;
error := to_signed(to_integer(dx) - to_integer(dy), 9);
ldone <= '0';
--draw line loop
ELSIF (drawl = '1') THEN
x <= STD_LOGIC_VECTOR(x0);
y <= STD_LOGIC_VECTOR(y0);
-- Exit loop if we are at destination point
IF (x0 = x1) THEN
IF(y0 = y1) THEN
ldone <= '1';
END IF;
ELSE
e2 := signed(2*error)(9 downto 0);
IF (e2 > -dy) THEN
error := error - dy;
x0 := unsigned(signed(x0) + sx);
END IF;
IF (e2 < dx) THEN
error := error + dx;
y0 := unsigned(signed(y0) + sy);
END IF;
END IF;
--clear screen
ELSE
IF (RESETY = '1') THEN
y_tmp := "0000000";
ELSIF (INCR_Y = '1') THEN
y_tmp := y_tmp + 1;
IF (y_tmp = 119) THEN
YDONE <= '1';
ELSE
YDONE <= '0';
END IF;
END IF;
Y <= std_logic_vector(y_tmp);
IF (RESETX = '1') THEN
x_tmp := "00000000";
ELSIF (INCR_X = '1') THEN
x_tmp := x_tmp + 1;
IF (x_tmp = 159) THEN
XDONE <= '1';
ELSE
XDONE <= '0';
END IF;
END IF;
X <= std_logic_vector(x_tmp);
END IF;
END IF;
END PROCESS;
END mixed;
|
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.cpu_pack.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT cpu_engine
PORT(
clk_i : IN std_logic;
dat_i : IN std_logic_vector(7 downto 0);
rst_i : IN std_logic;
ack_i : IN std_logic;
int : IN std_logic;
dat_o : OUT std_logic_vector(7 downto 0);
adr_o : OUT std_logic_vector(15 downto 0);
cyc_o : OUT std_logic;
stb_o : OUT std_logic;
tga_o : OUT std_logic_vector(0 to 0);
we_o : OUT std_logic;
halt : OUT std_logic;
q_pc : OUT std_logic_vector(15 downto 0);
q_opc : OUT std_logic_vector(7 downto 0);
q_cat : OUT op_category;
q_imm : OUT std_logic_vector(15 downto 0);
q_cyc : OUT cycle;
q_sx : OUT std_logic_vector(1 downto 0);
q_sy : OUT std_logic_vector(3 downto 0);
q_op : OUT std_logic_vector(4 downto 0);
q_sa : OUT std_logic_vector(4 downto 0);
q_smq : OUT std_logic;
q_we_rr : OUT std_logic;
q_we_ll : OUT std_logic;
q_we_sp : OUT SP_OP;
q_rr : OUT std_logic_vector(15 downto 0);
q_ll : OUT std_logic_vector(15 downto 0);
q_sp : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
signal CLK_I : std_logic;
signal DAT_I : std_logic_vector( 7 downto 0);
signal DAT_O : std_logic_vector( 7 downto 0);
signal RST_I : std_logic;
signal ACK_I : std_logic;
signal ADR_O : std_logic_vector(15 downto 0);
signal CYC_O : std_logic;
signal STB_O : std_logic;
signal TGA_O : std_logic_vector( 0 downto 0); -- '1' if I/O
signal WE_O : std_logic;
signal INT : std_logic;
signal HALT : std_logic;
-- debug signals
--
signal Q_PC : std_logic_vector(15 downto 0);
signal Q_OPC : std_logic_vector( 7 downto 0);
signal Q_CAT : op_category;
signal Q_IMM : std_logic_vector(15 downto 0);
signal Q_CYC : cycle;
-- select signals
signal Q_SX : std_logic_vector(1 downto 0);
signal Q_SY : std_logic_vector(3 downto 0);
signal Q_OP : std_logic_vector(4 downto 0);
signal Q_SA : std_logic_vector(4 downto 0);
signal Q_SMQ : std_logic;
-- write enable/select signal
signal Q_WE_RR : std_logic;
signal Q_WE_LL : std_logic;
signal Q_WE_SP : SP_OP;
signal Q_RR : std_logic_vector(15 downto 0);
signal Q_LL : std_logic_vector(15 downto 0);
signal Q_SP : std_logic_vector(15 downto 0);
signal clk_counter : INTEGER := 0;
BEGIN
uut: cpu_engine
PORT MAP(
clk_i => clk_i,
dat_i => dat_i,
dat_o => dat_o,
rst_i => rst_i,
ack_i => ack_i,
adr_o => adr_o,
cyc_o => cyc_o,
stb_o => stb_o,
tga_o => tga_o,
we_o => we_o,
int => int,
halt => halt,
q_pc => q_pc,
q_opc => q_opc,
q_cat => q_cat,
q_imm => q_imm,
q_cyc => q_cyc,
q_sx => q_sx,
q_sy => q_sy,
q_op => q_op,
q_sa => q_sa,
q_smq => q_smq,
q_we_rr => q_we_rr,
q_we_ll => q_we_ll,
q_we_sp => q_we_sp,
q_rr => q_rr,
q_ll => q_ll,
q_sp => q_sp
);
ack_i <= stb_o;
-- *** Test Bench - User Defined Section ***
PROCESS -- clock process for CLK_I,
BEGIN
CLOCK_LOOP : LOOP
CLK_I <= transport '0';
WAIT FOR 1 ns;
CLK_I <= transport '1';
WAIT FOR 1 ns;
WAIT FOR 11 ns;
CLK_I <= transport '0';
WAIT FOR 12 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS(CLK_I)
BEGIN
if (rising_edge(CLK_I)) then
if (Q_CYC = M1) then
CLK_COUNTER <= CLK_COUNTER + 1;
end if;
if (ADR_O(0) = '0') then DAT_I <= X"44"; -- data
else DAT_I <= X"01"; -- control
end if;
case CLK_COUNTER is
when 0 => RST_I <= '1'; INT <= '0';
when 1 => RST_I <= '0';
-- when 20 => INT <= '1';
when 1000 => CLK_COUNTER <= 0;
ASSERT (FALSE) REPORT
"simulation done (no error)"
SEVERITY FAILURE;
when others =>
end case;
end if;
END PROCESS;
END;
|
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.cpu_pack.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT cpu_engine
PORT(
clk_i : IN std_logic;
dat_i : IN std_logic_vector(7 downto 0);
rst_i : IN std_logic;
ack_i : IN std_logic;
int : IN std_logic;
dat_o : OUT std_logic_vector(7 downto 0);
adr_o : OUT std_logic_vector(15 downto 0);
cyc_o : OUT std_logic;
stb_o : OUT std_logic;
tga_o : OUT std_logic_vector(0 to 0);
we_o : OUT std_logic;
halt : OUT std_logic;
q_pc : OUT std_logic_vector(15 downto 0);
q_opc : OUT std_logic_vector(7 downto 0);
q_cat : OUT op_category;
q_imm : OUT std_logic_vector(15 downto 0);
q_cyc : OUT cycle;
q_sx : OUT std_logic_vector(1 downto 0);
q_sy : OUT std_logic_vector(3 downto 0);
q_op : OUT std_logic_vector(4 downto 0);
q_sa : OUT std_logic_vector(4 downto 0);
q_smq : OUT std_logic;
q_we_rr : OUT std_logic;
q_we_ll : OUT std_logic;
q_we_sp : OUT SP_OP;
q_rr : OUT std_logic_vector(15 downto 0);
q_ll : OUT std_logic_vector(15 downto 0);
q_sp : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
signal CLK_I : std_logic;
signal DAT_I : std_logic_vector( 7 downto 0);
signal DAT_O : std_logic_vector( 7 downto 0);
signal RST_I : std_logic;
signal ACK_I : std_logic;
signal ADR_O : std_logic_vector(15 downto 0);
signal CYC_O : std_logic;
signal STB_O : std_logic;
signal TGA_O : std_logic_vector( 0 downto 0); -- '1' if I/O
signal WE_O : std_logic;
signal INT : std_logic;
signal HALT : std_logic;
-- debug signals
--
signal Q_PC : std_logic_vector(15 downto 0);
signal Q_OPC : std_logic_vector( 7 downto 0);
signal Q_CAT : op_category;
signal Q_IMM : std_logic_vector(15 downto 0);
signal Q_CYC : cycle;
-- select signals
signal Q_SX : std_logic_vector(1 downto 0);
signal Q_SY : std_logic_vector(3 downto 0);
signal Q_OP : std_logic_vector(4 downto 0);
signal Q_SA : std_logic_vector(4 downto 0);
signal Q_SMQ : std_logic;
-- write enable/select signal
signal Q_WE_RR : std_logic;
signal Q_WE_LL : std_logic;
signal Q_WE_SP : SP_OP;
signal Q_RR : std_logic_vector(15 downto 0);
signal Q_LL : std_logic_vector(15 downto 0);
signal Q_SP : std_logic_vector(15 downto 0);
signal clk_counter : INTEGER := 0;
BEGIN
uut: cpu_engine
PORT MAP(
clk_i => clk_i,
dat_i => dat_i,
dat_o => dat_o,
rst_i => rst_i,
ack_i => ack_i,
adr_o => adr_o,
cyc_o => cyc_o,
stb_o => stb_o,
tga_o => tga_o,
we_o => we_o,
int => int,
halt => halt,
q_pc => q_pc,
q_opc => q_opc,
q_cat => q_cat,
q_imm => q_imm,
q_cyc => q_cyc,
q_sx => q_sx,
q_sy => q_sy,
q_op => q_op,
q_sa => q_sa,
q_smq => q_smq,
q_we_rr => q_we_rr,
q_we_ll => q_we_ll,
q_we_sp => q_we_sp,
q_rr => q_rr,
q_ll => q_ll,
q_sp => q_sp
);
ack_i <= stb_o;
-- *** Test Bench - User Defined Section ***
PROCESS -- clock process for CLK_I,
BEGIN
CLOCK_LOOP : LOOP
CLK_I <= transport '0';
WAIT FOR 1 ns;
CLK_I <= transport '1';
WAIT FOR 1 ns;
WAIT FOR 11 ns;
CLK_I <= transport '0';
WAIT FOR 12 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS(CLK_I)
BEGIN
if (rising_edge(CLK_I)) then
if (Q_CYC = M1) then
CLK_COUNTER <= CLK_COUNTER + 1;
end if;
if (ADR_O(0) = '0') then DAT_I <= X"44"; -- data
else DAT_I <= X"01"; -- control
end if;
case CLK_COUNTER is
when 0 => RST_I <= '1'; INT <= '0';
when 1 => RST_I <= '0';
-- when 20 => INT <= '1';
when 1000 => CLK_COUNTER <= 0;
ASSERT (FALSE) REPORT
"simulation done (no error)"
SEVERITY FAILURE;
when others =>
end case;
end if;
END PROCESS;
END;
|
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.cpu_pack.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT cpu_engine
PORT(
clk_i : IN std_logic;
dat_i : IN std_logic_vector(7 downto 0);
rst_i : IN std_logic;
ack_i : IN std_logic;
int : IN std_logic;
dat_o : OUT std_logic_vector(7 downto 0);
adr_o : OUT std_logic_vector(15 downto 0);
cyc_o : OUT std_logic;
stb_o : OUT std_logic;
tga_o : OUT std_logic_vector(0 to 0);
we_o : OUT std_logic;
halt : OUT std_logic;
q_pc : OUT std_logic_vector(15 downto 0);
q_opc : OUT std_logic_vector(7 downto 0);
q_cat : OUT op_category;
q_imm : OUT std_logic_vector(15 downto 0);
q_cyc : OUT cycle;
q_sx : OUT std_logic_vector(1 downto 0);
q_sy : OUT std_logic_vector(3 downto 0);
q_op : OUT std_logic_vector(4 downto 0);
q_sa : OUT std_logic_vector(4 downto 0);
q_smq : OUT std_logic;
q_we_rr : OUT std_logic;
q_we_ll : OUT std_logic;
q_we_sp : OUT SP_OP;
q_rr : OUT std_logic_vector(15 downto 0);
q_ll : OUT std_logic_vector(15 downto 0);
q_sp : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
signal CLK_I : std_logic;
signal DAT_I : std_logic_vector( 7 downto 0);
signal DAT_O : std_logic_vector( 7 downto 0);
signal RST_I : std_logic;
signal ACK_I : std_logic;
signal ADR_O : std_logic_vector(15 downto 0);
signal CYC_O : std_logic;
signal STB_O : std_logic;
signal TGA_O : std_logic_vector( 0 downto 0); -- '1' if I/O
signal WE_O : std_logic;
signal INT : std_logic;
signal HALT : std_logic;
-- debug signals
--
signal Q_PC : std_logic_vector(15 downto 0);
signal Q_OPC : std_logic_vector( 7 downto 0);
signal Q_CAT : op_category;
signal Q_IMM : std_logic_vector(15 downto 0);
signal Q_CYC : cycle;
-- select signals
signal Q_SX : std_logic_vector(1 downto 0);
signal Q_SY : std_logic_vector(3 downto 0);
signal Q_OP : std_logic_vector(4 downto 0);
signal Q_SA : std_logic_vector(4 downto 0);
signal Q_SMQ : std_logic;
-- write enable/select signal
signal Q_WE_RR : std_logic;
signal Q_WE_LL : std_logic;
signal Q_WE_SP : SP_OP;
signal Q_RR : std_logic_vector(15 downto 0);
signal Q_LL : std_logic_vector(15 downto 0);
signal Q_SP : std_logic_vector(15 downto 0);
signal clk_counter : INTEGER := 0;
BEGIN
uut: cpu_engine
PORT MAP(
clk_i => clk_i,
dat_i => dat_i,
dat_o => dat_o,
rst_i => rst_i,
ack_i => ack_i,
adr_o => adr_o,
cyc_o => cyc_o,
stb_o => stb_o,
tga_o => tga_o,
we_o => we_o,
int => int,
halt => halt,
q_pc => q_pc,
q_opc => q_opc,
q_cat => q_cat,
q_imm => q_imm,
q_cyc => q_cyc,
q_sx => q_sx,
q_sy => q_sy,
q_op => q_op,
q_sa => q_sa,
q_smq => q_smq,
q_we_rr => q_we_rr,
q_we_ll => q_we_ll,
q_we_sp => q_we_sp,
q_rr => q_rr,
q_ll => q_ll,
q_sp => q_sp
);
ack_i <= stb_o;
-- *** Test Bench - User Defined Section ***
PROCESS -- clock process for CLK_I,
BEGIN
CLOCK_LOOP : LOOP
CLK_I <= transport '0';
WAIT FOR 1 ns;
CLK_I <= transport '1';
WAIT FOR 1 ns;
WAIT FOR 11 ns;
CLK_I <= transport '0';
WAIT FOR 12 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS(CLK_I)
BEGIN
if (rising_edge(CLK_I)) then
if (Q_CYC = M1) then
CLK_COUNTER <= CLK_COUNTER + 1;
end if;
if (ADR_O(0) = '0') then DAT_I <= X"44"; -- data
else DAT_I <= X"01"; -- control
end if;
case CLK_COUNTER is
when 0 => RST_I <= '1'; INT <= '0';
when 1 => RST_I <= '0';
-- when 20 => INT <= '1';
when 1000 => CLK_COUNTER <= 0;
ASSERT (FALSE) REPORT
"simulation done (no error)"
SEVERITY FAILURE;
when others =>
end case;
end if;
END PROCESS;
END;
|
-------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 08
-- Project :
-------------------------------------------------------------------------------
-- File : audio_ctrl.vhd
-- Author : Jonas Nikula, Tuomas Huuki
-- Company : TUT
-- Created : 11.1.2016
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Controller for Wolfson WM8731 -audio codec
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 11.01.2016 1.0 nikulaj Created
-- 12.01.2016 1.1 huukit Drafting functionality.
-- 15.01.2016 1.2 huukit Fixed a bug where the snapshot was incorrectly updated.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Define the entity.
entity audio_ctrl is
generic(
ref_clk_freq_g : integer := 18432000; -- Reference clock.
sample_rate_g : integer := 48000; -- Sample clock fs.
data_width_g : integer := 16 -- Data width.
);
port(
clk : in std_logic; -- Main clock.
rst_n : in std_logic; -- Reset, active low.
left_data_in : in std_logic_vector(data_width_g - 1 downto 0); -- Data in, left.
right_data_in : in std_logic_vector(data_width_g - 1 downto 0); -- Data in, right.
aud_bclk_out : out std_logic; -- Audio bitclock.
aud_data_out : out std_logic; -- Audio data.
aud_lrclk_out : out std_logic -- Audio bitclock L/R select.
);
end audio_ctrl;
architecture rtl of audio_ctrl is
-- Calculate contants for clock generation counters.
constant fs_c : integer := (((ref_clk_freq_g / sample_rate_g) / data_width_g) / 4) - 1;
constant lr_c : integer := (data_width_g * 2) - 1;
-- Define the width of the counters used.
constant clk_c_width_c : integer := 16;
-- Clock counters.
signal bclk_count_r : unsigned(clk_c_width_c - 1 downto 0);
signal lr_count_r : unsigned(clk_c_width_c - 1 downto 0);
-- Data and control registers.
signal left_data_ss_r : std_logic_vector(data_width_g - 1 downto 0);
signal right_data_ss_r : std_logic_vector(data_width_g - 1 downto 0);
signal aud_data_r : std_logic;
signal bclk_r : std_logic;
signal lr_r : std_logic;
begin --rtl
-- Assign registers to outputs.
aud_bclk_out <= bclk_r;
aud_lrclk_out <= lr_r;
aud_data_out <= aud_data_r;
bclock : process (clk, rst_n) -- Generates the bit and lr clocks.
begin
if(rst_n = '0') then
bclk_count_r <= to_unsigned(fs_c, bclk_count_r'length);
lr_count_r <= to_unsigned(lr_c, lr_count_r'length);
bclk_r <= '0';
lr_r <= '1';
elsif(clk'event and clk = '1') then
if(bclk_count_r = 0) then -- Handle bclk.
bclk_r <= not bclk_r; -- bclk Invert on compare.
bclk_count_r <= to_unsigned(fs_c, bclk_count_r'length); -- bclk Reset counter.
if(lr_count_r = 0) then -- Handle L/R selection.
lr_r <= not lr_r; -- L/R invert on compare.
lr_count_r <= to_unsigned(lr_c, lr_count_r'length); -- L/R reset counter.
else
lr_count_r <= lr_count_r - 1; -- L/R count down.
end if;
else
bclk_count_r <= bclk_count_r - 1; -- bclk Count down.
end if;
end if;
end process bclock;
dataload : process (clk, rst_n) -- Load and serialize the input data.
begin
if(rst_n = '0') then -- Reset clears dataregisters.
left_data_ss_r <= (others => '0');
right_data_ss_r <= (others => '0');
aud_data_r <= '0';
elsif(clk'event and clk = '1') then
if(lr_count_r = 0 and bclk_count_r = 0) then -- Store and load.
if(lr_r = '0') then -- Only store snapshot on SOF.
left_data_ss_r <= left_data_in; -- Store snapshots.
right_data_ss_r <= right_data_in;
aud_data_r <= left_data_in(lr_c / 2); -- Load first bit.
else
aud_data_r <= right_data_ss_r(lr_c/ 2); -- Load first bit.
end if;
elsif(bclk_count_r = 0 and bclk_r = '1') then -- Load next byte on falling clock.
if(lr_r = '1') then
aud_data_r <= left_data_ss_r(to_integer((lr_count_r -1 )/ 2));
else
aud_data_r <= right_data_ss_r(to_integer((lr_count_r -1)/ 2));
end if;
end if;
end if;
end process dataload;
end rtl;
|
-- Twofish_ecb_vk_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the VARIABLE KEY KAT of the twofish cipher with 128 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity vk_testbench128 is
end vk_testbench128;
architecture vk_encryption128_testbench_arch of vk_testbench128 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched128
port (
odd_in_tk128,
even_in_tk128 : in std_logic_vector(7 downto 0);
in_key_tk128 : in std_logic_vector(127 downto 0);
out_key_up_tk128,
out_key_down_tk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched128
port (
in_key_twk128 : in std_logic_vector(127 downto 0);
out_K0_twk128,
out_K1_twk128,
out_K2_twk128,
out_K3_twk128,
out_K4_twk128,
out_K5_twk128,
out_K6_twk128,
out_K7_twk128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round128
port (
in1_ter128,
in2_ter128,
in3_ter128,
in4_ter128,
in_Sfirst_ter128,
in_Ssecond_ter128,
in_key_up_ter128,
in_key_down_ter128 : in std_logic_vector(31 downto 0);
out1_ter128,
out2_ter128,
out3_ter128,
out4_ter128 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S128
port (
in_key_ts128 : in std_logic_vector(127 downto 0);
out_Sfirst_ts128,
out_Ssecond_ts128 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_vk_testvalues_128bits.txt";
FILE output_file : text is out "twofish_ecb_vk_128bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 1 to 129) return string is
variable our_text : string (1 to 3) := (others => ' ');
variable hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := (int_number - (int_number mod 100)) / 100;
our_text(1) := digit_to_char(hundreds);
our_text(2) := digit_to_char(tens);
our_text(3) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
twofish_key,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal key_up,
key_down,
Sfirst,
Ssecond,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched128
port map (
in_key_twk128 => twofish_key,
out_K0_twk128 => K0,
out_K1_twk128 => K1,
out_K2_twk128 => K2,
out_K3_twk128 => K3,
out_K4_twk128 => K4,
out_K5_twk128 => K5,
out_K6_twk128 => K6,
out_K7_twk128 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched128
port map (
odd_in_tk128 => odd_number,
even_in_tk128 => even_number,
in_key_tk128 => twofish_key,
out_key_up_tk128 => key_up,
out_key_down_tk128 => key_down
);
producing_the_Skeys: twofish_S128
port map (
in_key_ts128 => twofish_key,
out_Sfirst_ts128 => Sfirst,
out_Ssecond_ts128 => Ssecond
);
the_encryption_circuit: twofish_encryption_round128
port map (
in1_ter128 => to_round(127 downto 96),
in2_ter128 => to_round(95 downto 64),
in3_ter128 => to_round(63 downto 32),
in4_ter128 => to_round(31 downto 0),
in_Sfirst_ter128 => Sfirst,
in_Ssecond_ter128 => Ssecond,
in_key_up_ter128 => key_up,
in_key_down_ter128 => key_down,
out1_ter128 => to_encr_reg128(127 downto 96),
out2_ter128 => to_encr_reg128(95 downto 64),
out3_ter128 => to_encr_reg128(63 downto 32),
out4_ter128 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
vk_proc: process
variable key_f, -- key input from file
ct_f : line; -- ciphertext from file
variable key_v, -- key vector input
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter : integer range 1 to 129 := 1; -- counts the encryptions
variable round : integer range 1 to 16 := 1; -- holds the rounds of encryption
begin
-- plaintext stays fixed to zero
input_data <= (others => '0');
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note;
counter := counter+1;
hwrite(ct_f,output_data);
hwrite(key_f,key_v);
writeline(output_file,key_f);
writeline(output_file,ct_f);
end loop;
assert false report "***** Variable Key Known Answer Test with 128 bits key size ended succesfully! :) *****" severity failure;
end process vk_proc;
end vk_encryption128_testbench_arch;
|
------------------------------------------------------------------------------
-- Title : Wishbone BPM SWAP interface
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone interface with BPM Swap core.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-04-11 1.0 jose.berkenbrock Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- DSP Cores
use work.dsp_cores_pkg.all;
-- Register Bank
use work.bpm_swap_wbgen2_pkg.all;
entity xwb_bpm_swap is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- Input from ADC FMC board
cha_i : in std_logic_vector(15 downto 0);
chb_i : in std_logic_vector(15 downto 0);
chc_i : in std_logic_vector(15 downto 0);
chd_i : in std_logic_vector(15 downto 0);
-- Output to data processing level
cha_o : out std_logic_vector(15 downto 0);
chb_o : out std_logic_vector(15 downto 0);
chc_o : out std_logic_vector(15 downto 0);
chd_o : out std_logic_vector(15 downto 0);
mode1_o : out std_logic_vector(1 downto 0);
mode2_o : out std_logic_vector(1 downto 0);
wdw_rst_o : out std_logic; -- Reset Windowing module
wdw_sw_clk_i : in std_logic; -- Switching clock from Windowing module
wdw_use_o : out std_logic; -- Use Windowing module
wdw_dly_o : out std_logic_vector(15 downto 0); -- Delay to apply the window
-- Output to RFFE board
clk_swap_o : out std_logic;
clk_swap_en_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0)
);
end xwb_bpm_swap;
architecture rtl of xwb_bpm_swap is
begin
cmp_wb_bpm_swap : wb_bpm_swap
generic map
(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity
)
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
fs_rst_n_i => fs_rst_n_i,
fs_clk_i => fs_clk_i,
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_stall_o => wb_slv_o.stall,
-----------------------------
-- External ports
-----------------------------
-- input from ADC FMC board:
cha_i => cha_i,
chb_i => chb_i,
chc_i => chc_i,
chd_i => chd_i,
-- output to data processing level:
cha_o => cha_o,
chb_o => chb_o,
chc_o => chc_o,
chd_o => chd_o,
mode1_o => mode1_o,
mode2_o => mode2_o,
wdw_rst_o => wdw_rst_o,
wdw_sw_clk_i => wdw_sw_clk_i,
wdw_use_o => wdw_use_o,
wdw_dly_o => wdw_dly_o,
-- output to RFFE board:
clk_swap_o => clk_swap_o,
clk_swap_en_o => clk_swap_en_o,
flag1_o => flag1_o,
flag2_o => flag2_o,
ctrl1_o => ctrl1_o,
ctrl2_o => ctrl2_o
);
end rtl;
|
-- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_bidir
-- ============================================================
-- File Name: bidir_dqs_iobuf_inst.vhd
-- Megafunction Name(s):
-- altiobuf_bidir
--
-- Simulation Library Files(s):
-- stratixiii
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.0 Build 231 07/10/2008 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altiobuf_bidir CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix III" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" USE_DIFFERENTIAL_MODE="TRUE" USE_DYNAMIC_TERMINATION_CONTROL="TRUE" USE_TERMINATION_CONTROL="FALSE" datain dataio dataio_b dataout dynamicterminationcontrol dynamicterminationcontrol_b oe oe_b
--VERSION_BEGIN 8.0SP1 cbx_altiobuf_in 2008:06:02:292401 cbx_mgl 2008:06:02:292401 cbx_stratixiii 2008:06:18:296807 VERSION_END
LIBRARY stratixiii;
USE stratixiii.all;
--synthesis_resources = stratixiii_io_ibuf 1 stratixiii_io_obuf 2 stratixiii_pseudo_diff_out 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bidir_dqs_iobuf_inst_iobuf_bidir_fkv IS
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio_b : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dynamicterminationcontrol : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
dynamicterminationcontrol_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1')
);
END bidir_dqs_iobuf_inst_iobuf_bidir_fkv;
ARCHITECTURE RTL OF bidir_dqs_iobuf_inst_iobuf_bidir_fkv IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_ibufa_o : STD_LOGIC;
SIGNAL wire_obuf_ba_o : STD_LOGIC;
SIGNAL wire_obufa_o : STD_LOGIC;
SIGNAL wire_pseudo_diffa_o : STD_LOGIC;
SIGNAL wire_pseudo_diffa_obar : STD_LOGIC;
COMPONENT stratixiii_io_ibuf
GENERIC
(
bus_hold : STRING := "false";
differential_mode : STRING := "false";
lpm_type : STRING := "stratixiii_io_ibuf"
);
PORT
(
i : IN STD_LOGIC := '0';
ibar : IN STD_LOGIC := '0';
o : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_io_obuf
GENERIC
(
bus_hold : STRING := "false";
open_drain_output : STRING := "false";
shift_series_termination_control : STRING := "false";
--sim_dynamic_termination_control_is_connected : STRING := "false";
lpm_type : STRING := "stratixiii_io_obuf"
);
PORT
(
dynamicterminationcontrol : IN STD_LOGIC := '0';
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
parallelterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
seriesterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT stratixiii_pseudo_diff_out
PORT
(
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
dataio(0) <= wire_obufa_o;
dataio_b(0) <= wire_obuf_ba_o;
dataout(0) <= wire_ibufa_o;
ibufa : stratixiii_io_ibuf
GENERIC MAP (
bus_hold => "false"
)
PORT MAP (
i => dataio(0),
ibar => dataio_b(0),
o => wire_ibufa_o
);
obuf_ba : stratixiii_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
dynamicterminationcontrol => dynamicterminationcontrol_b(0),
i => wire_pseudo_diffa_obar,
o => wire_obuf_ba_o,
oe => oe_b(0)
);
obufa : stratixiii_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
dynamicterminationcontrol => dynamicterminationcontrol(0),
i => wire_pseudo_diffa_o,
o => wire_obufa_o,
oe => oe(0)
);
pseudo_diffa : stratixiii_pseudo_diff_out
PORT MAP (
i => datain(0),
o => wire_pseudo_diffa_o,
obar => wire_pseudo_diffa_obar
);
END RTL; --bidir_dqs_iobuf_inst_iobuf_bidir_fkv
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bidir_dqs_iobuf_inst IS
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dyn_term_ctrl : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dyn_term_ctrl_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio_b : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END bidir_dqs_iobuf_inst;
ARCHITECTURE RTL OF bidir_dqs_iobuf_inst IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT bidir_dqs_iobuf_inst_iobuf_bidir_fkv
PORT (
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio_b : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dynamicterminationcontrol_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dynamicterminationcontrol : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(0 DOWNTO 0);
bidir_dqs_iobuf_inst_iobuf_bidir_fkv_component : bidir_dqs_iobuf_inst_iobuf_bidir_fkv
PORT MAP (
datain => datain,
dynamicterminationcontrol_b => dyn_term_ctrl_b,
oe => oe,
oe_b => oe_b,
dynamicterminationcontrol => dyn_term_ctrl,
dataout => sub_wire0,
dataio => dataio,
dataio_b => dataio_b
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
-- Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"
-- Retrieval info: CONSTANT: use_dynamic_termination_control STRING "TRUE"
-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
-- Retrieval info: USED_PORT: dataio 0 0 1 0 BIDIR NODEFVAL "dataio[0..0]"
-- Retrieval info: USED_PORT: dataio_b 0 0 1 0 BIDIR NODEFVAL "dataio_b[0..0]"
-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
-- Retrieval info: USED_PORT: dyn_term_ctrl 0 0 1 0 INPUT NODEFVAL "dyn_term_ctrl[0..0]"
-- Retrieval info: USED_PORT: dyn_term_ctrl_b 0 0 1 0 INPUT NODEFVAL "dyn_term_ctrl_b[0..0]"
-- Retrieval info: USED_PORT: oe 0 0 1 0 INPUT NODEFVAL "oe[0..0]"
-- Retrieval info: USED_PORT: oe_b 0 0 1 0 INPUT NODEFVAL "oe_b[0..0]"
-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
-- Retrieval info: CONNECT: @dynamicterminationcontrol_b 0 0 1 0 dyn_term_ctrl_b 0 0 1 0
-- Retrieval info: CONNECT: @dynamicterminationcontrol 0 0 1 0 dyn_term_ctrl 0 0 1 0
-- Retrieval info: CONNECT: @oe 0 0 1 0 oe 0 0 1 0
-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
-- Retrieval info: CONNECT: @oe_b 0 0 1 0 oe_b 0 0 1 0
-- Retrieval info: CONNECT: dataio_b 0 0 1 0 @dataio_b 0 0 1 0
-- Retrieval info: CONNECT: dataio 0 0 1 0 @dataio 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dqs_iobuf_inst.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dqs_iobuf_inst.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dqs_iobuf_inst.cmp FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dqs_iobuf_inst.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dqs_iobuf_inst_inst.vhd FALSE FALSE
-- Retrieval info: LIB_FILE: stratixiii
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-conf-c.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_t-rtl-conf-c.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_t_rtl_conf / ent_t
--
configuration ent_t_rtl_conf of ent_t is
for rtl
-- Generated Configuration
for inst_a : ent_a
use configuration work.ent_a_rtl_conf;
end for;
for inst_b : ent_b
use configuration work.ent_b_rtl_conf;
end for;
end for;
end ent_t_rtl_conf;
--
-- End of Generated Configuration ent_t_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:06:18 10/01/2014
-- Design Name:
-- Module Name: E:/2014/Academico/OC/2014/tp2/TB_SN54LV165A.vhd
-- Project Name: tp2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SN54LV165A
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_SN54LV165A IS
END TB_SN54LV165A;
ARCHITECTURE behavior OF TB_SN54LV165A IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SN54LV165A
PORT(
CLK : IN std_logic;
CLKIN : IN std_logic;
NLOAD : IN std_logic;
SER : IN std_logic;
DIN : IN std_logic_vector(7 downto 0);
Q : OUT std_logic;
NQ : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal CLKIN : std_logic := '0';
signal NLOAD : std_logic := '0';
signal SER : std_logic := '0';
signal DIN : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal Q : std_logic;
signal NQ : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SN54LV165A PORT MAP (
CLK => CLK,
CLKIN => CLKIN,
NLOAD => NLOAD,
SER => SER,
DIN => DIN,
Q => Q,
NQ => NQ
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
nload<='1';
-- hold reset state for 20 ns.
wait for 20 ns;
-- insert stimulus here
CLKIN<='1';
SER<='0';
NLOAD<='1';
DIN<="00000000";
wait for 20 ns;
NLOAD<='0';
DIN<="11010101";
wait for 5 ns;
NLOAD<='1';
wait for 20 ns;
CLKIN<='0';
wait;
end process;
corr_proc: process(CLK)
variable theTime : time;
begin
theTime := now;
if theTime=30000 ps then
report time'image(theTime);
assert (q='0' and nq='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=45000 ps then
report time'image(theTime);
assert (q='1' and nq='0')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=90000 ps then
report time'image(theTime);
assert (q='0' and nq='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=100000 ps then
report time'image(theTime);
assert (q='1' and nq='0')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=110000 ps then
report time'image(theTime);
assert (q='0' and nq='1')
report("Salidas erroneas.")
severity ERROR;
end if;
if theTime=120000 ps then
report time'image(theTime);
assert (q='1' and nq='0')
report("Salidas erroneas.")
severity ERROR;
end if;
end process;
END;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Wed Jul 20 01:57:48 2016
-- Host : jalapeno running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub {/home/hhassan/git/GateKeeper/FPGA
-- Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_pe_fifo/shd_pe_fifo_stub.vhdl}
-- Design : shd_pe_fifo
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7vx690tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shd_pe_fifo is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end shd_pe_fifo;
architecture stub of shd_pe_fifo is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_0_1,Vivado 2015.4";
begin
end;
|
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_2;
end architecture ARCH;
|
entity mixer_tb is
end;
use work.mixer_pkg.all;
architecture behav of mixer_tb is
signal s : sample_array(0 to 127)(3 downto 0);
begin
inst : entity work.mixer generic map (sample_bits => 4)
port map(i_samples => s);
end behav;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity add_1 is
port ( d0, d1, d2, d3 : in bit;
y0, y1, y2, y3 : out bit );
end entity add_1;
architecture boolean_eqn of add_1 is
begin
y0 <= not d0 after 4 ns;
y1 <= (not d1 and d0)
or (d1 and not d0) after 4 ns;
y2 <= (not d2 and d1 and d0)
or (d2 and not (d1 and d0)) after 4 ns;
y3 <= (not d3 and d2 and d1 and d0)
or (d3 and not (d2 and d1 and d0)) after 4 ns;
end architecture boolean_eqn;
entity buf4 is
port ( a0, a1, a2, a3 : in bit;
y0, y1, y2, y3 : out bit );
end entity buf4;
architecture basic of buf4 is
begin
y0 <= a0 after 2 ns;
y1 <= a1 after 2 ns;
y2 <= a2 after 2 ns;
y3 <= a3 after 2 ns;
end architecture basic;
package counter_types is
subtype digit is bit_vector(3 downto 0);
end package counter_types;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity add_1 is
port ( d0, d1, d2, d3 : in bit;
y0, y1, y2, y3 : out bit );
end entity add_1;
architecture boolean_eqn of add_1 is
begin
y0 <= not d0 after 4 ns;
y1 <= (not d1 and d0)
or (d1 and not d0) after 4 ns;
y2 <= (not d2 and d1 and d0)
or (d2 and not (d1 and d0)) after 4 ns;
y3 <= (not d3 and d2 and d1 and d0)
or (d3 and not (d2 and d1 and d0)) after 4 ns;
end architecture boolean_eqn;
entity buf4 is
port ( a0, a1, a2, a3 : in bit;
y0, y1, y2, y3 : out bit );
end entity buf4;
architecture basic of buf4 is
begin
y0 <= a0 after 2 ns;
y1 <= a1 after 2 ns;
y2 <= a2 after 2 ns;
y3 <= a3 after 2 ns;
end architecture basic;
package counter_types is
subtype digit is bit_vector(3 downto 0);
end package counter_types;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity add_1 is
port ( d0, d1, d2, d3 : in bit;
y0, y1, y2, y3 : out bit );
end entity add_1;
architecture boolean_eqn of add_1 is
begin
y0 <= not d0 after 4 ns;
y1 <= (not d1 and d0)
or (d1 and not d0) after 4 ns;
y2 <= (not d2 and d1 and d0)
or (d2 and not (d1 and d0)) after 4 ns;
y3 <= (not d3 and d2 and d1 and d0)
or (d3 and not (d2 and d1 and d0)) after 4 ns;
end architecture boolean_eqn;
entity buf4 is
port ( a0, a1, a2, a3 : in bit;
y0, y1, y2, y3 : out bit );
end entity buf4;
architecture basic of buf4 is
begin
y0 <= a0 after 2 ns;
y1 <= a1 after 2 ns;
y2 <= a2 after 2 ns;
y3 <= a3 after 2 ns;
end architecture basic;
package counter_types is
subtype digit is bit_vector(3 downto 0);
end package counter_types;
|
-------------------------------------------------------------------------------
--
-- Title : mux4
-- Design : lab1
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\lab1\lab1\compile\mux4.vhd
-- Generated : Tue Sep 23 20:29:22 2014
-- From : c:\My_Designs\lab1\lab1\src\mux4.bde
-- By : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4 is
port(
A1 : in STD_LOGIC;
A2 : in STD_LOGIC;
B1 : in STD_LOGIC;
B2 : in STD_LOGIC;
S : in STD_LOGIC;
Aout : out STD_LOGIC;
Bout : out STD_LOGIC
);
end mux4;
architecture mux4 of mux4 is
---- Component declarations -----
component mux
port (
A : in STD_LOGIC;
B : in STD_LOGIC;
S : in STD_LOGIC;
Z : out STD_LOGIC
);
end component;
begin
---- Component instantiations ----
Mux1 : mux
port map(
A => A1,
B => A2,
S => S,
Z => Aout
);
Mux2 : mux
port map(
A => B1,
B => B2,
S => S,
Z => Bout
);
end mux4;
|
-------------------------------------------------------------------------------
--
-- Title : mux4
-- Design : lab1
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\lab1\lab1\compile\mux4.vhd
-- Generated : Tue Sep 23 20:29:22 2014
-- From : c:\My_Designs\lab1\lab1\src\mux4.bde
-- By : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4 is
port(
A1 : in STD_LOGIC;
A2 : in STD_LOGIC;
B1 : in STD_LOGIC;
B2 : in STD_LOGIC;
S : in STD_LOGIC;
Aout : out STD_LOGIC;
Bout : out STD_LOGIC
);
end mux4;
architecture mux4 of mux4 is
---- Component declarations -----
component mux
port (
A : in STD_LOGIC;
B : in STD_LOGIC;
S : in STD_LOGIC;
Z : out STD_LOGIC
);
end component;
begin
---- Component instantiations ----
Mux1 : mux
port map(
A => A1,
B => A2,
S => S,
Z => Aout
);
Mux2 : mux
port map(
A => B1,
B => B2,
S => S,
Z => Bout
);
end mux4;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity OpenRest_module is
Port (
Play_Done : in STD_LOGIC;
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Data_in : in STD_LOGIC_VECTOR (4 downto 0);
Request_Set : out STD_LOGIC;
X_out : out STD_LOGIC_VECTOR (4 downto 0);
Y_out : out STD_LOGIC_VECTOR (4 downto 0);
Data_out : out STD_LOGIC_VECTOR (4 downto 0);
Done : out STD_LOGIC
);
end OpenRest_module;
architecture Behavioral of OpenRest_module is
----------SIGNALS------------------------------------
signal x_temp: unsigned (4 downto 0) :="00001";
signal y_temp: unsigned (4 downto 0) :="00001";
signal Data_out_temp: STD_LOGIC_VECTOR (3 downto 0);
signal set_temp: STD_LOGIC:='0';
signal done_sig: STD_LOGIC:='0';
----------STATES--------------------------------------
Type State_type is
(Zero_st, InitXY_st, Wait1_st, Wait2_st, Set_st, Move_st, Done_st);
signal state:State_type:=(Zero_st);
begin
process
begin
Wait until Clk'event AND Clk='1';
If Reset='1' then-----------------------initialize!
x_temp<="00001";
y_temp<="00001";
set_temp<='0';
done_sig <= '0';
state<=Zero_st;
else
Case state is
When Zero_st=>--Zero
if (Play_Done='1') then
state<=InitXY_st;
else
state<=Zero_st;
end if;
When InitXY_st=>
----- initialize coordinates
x_temp<="00001";
y_temp<="00001";
set_temp<='0';
state <= Wait1_st;
When Wait1_st =>
set_temp <= '0';
state <= Wait2_st;
When Wait2_st =>
set_temp <= '0';
state <= Set_st;
When Set_st =>
if Data_In(4) = '0' then --- unexplored tile
if Data_In = "01111" then --- if bomb set to "surviving" cockroach(brown one)
Data_out_temp <= "1010";
x_temp <= x_temp;
y_temp <= y_temp;
set_temp <= '1';
else
Data_out_temp <= Data_In(3 downto 0);
x_temp <= x_temp;
y_temp <= y_temp;
set_temp <= '1';
end if;
end if;
state <= Move_st;
When Move_st =>--change tile
If (y_temp=20) then
if (x_temp=20) then
set_temp <= '0';
state <= Done_st;
else
set_temp <= '0';
x_temp<=x_temp+1;
y_temp<="00001";
state <= Wait1_st;
end if;
else
set_temp <= '0';
y_temp<=y_temp+1;
state <= Wait1_st;
end if;
When Done_st =>
done_sig<='1';
set_temp<='0';
state<=Done_st;
when others=>NULL;
end case;
end if;
end process;
-----------------------------
Request_set<=set_temp;
Data_out<='1'&Data_out_temp;
Done <= done_sig;
X_out <=STD_LOGIC_VECTOR(x_temp);
Y_out <=STD_LOGIC_VECTOR(y_temp);
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pixel_difference_1d is
Port ( i_clk : in STD_LOGIC;
i_reset : in STD_LOGIC;
i_R : in STD_LOGIC_VECTOR (7 downto 0);
i_G : in STD_LOGIC_VECTOR (7 downto 0);
i_B : in STD_LOGIC_VECTOR (7 downto 0);
i_framevalid : in STD_LOGIC;
i_linevalid : in STD_LOGIC;
o_focusvalue : out STD_LOGIC_VECTOR(15 downto 0);
o_dv : out STD_LOGIC
);
end pixel_difference_1d;
architecture Behavioral of pixel_difference_1d is
COMPONENT color_space_converter
PORT(
i_clk : IN std_logic;
i_reset : IN std_logic;
i_R : IN std_logic_vector(7 downto 0);
i_G : IN std_logic_vector(7 downto 0);
i_B : IN std_logic_vector(7 downto 0);
i_framevalid : IN std_logic;
i_linevalid : IN std_logic;
o_Y : OUT std_logic_vector(7 downto 0);
o_framevalid : OUT std_logic;
o_linevalid : OUT std_logic
);
END COMPONENT;
COMPONENT focus_calculation_pixel_difference_1d
PORT(
i_clk : IN std_logic;
i_reset : IN std_logic;
i_framevalid : IN std_logic;
i_linevalid : IN std_logic;
i_Y : IN std_logic_vector(7 downto 0);
o_focusvalue : OUT std_logic_vector(15 downto 0);
o_dv : OUT std_logic
);
END COMPONENT;
signal s_framevalid : STD_LOGIC;
signal s_linevalid : STD_LOGIC;
signal s_Y : STD_LOGIC_VECTOR(7 downto 0);
begin
Inst_color_space_converter: color_space_converter PORT MAP(
i_clk => i_clk,
i_reset => i_reset,
i_R => i_R,
i_G => i_G,
i_B => i_B,
i_framevalid => i_framevalid,
i_linevalid => i_linevalid,
o_Y => s_Y,
o_framevalid => s_framevalid,
o_linevalid => s_linevalid
);
Inst_focus_calculation: focus_calculation_pixel_difference_1d PORT MAP(
i_clk => i_clk,
i_reset => i_reset,
i_framevalid => s_framevalid,
i_linevalid => s_linevalid,
i_Y => s_Y,
o_focusvalue => o_focusvalue,
o_dv => o_dv
);
end Behavioral;
|
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_cmp_eq_0002
-- VHDL created on Thu Feb 15 17:01:50 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cmp_eq_0002 is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(0 downto 0); -- ufix1
clk : in std_logic;
areset : in std_logic
);
end fp_cmp_eq_0002;
architecture normal of fp_cmp_eq_0002 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid6_fpCompareTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstZeroWF_uid7_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal cstAllZWE_uid8_fpCompareTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_x_uid11_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid12_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid13_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid14_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid16_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_y_uid25_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid26_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid27_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid28_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid30_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneIsNaN_uid34_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal bothZero_uid54_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rCmp_uid57_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal r_uid58_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rPostExc_uid59_fpCompareTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal rPostExc_uid59_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal exp_x_uid9_fpCompareTest_merged_bit_select_b : STD_LOGIC_VECTOR (7 downto 0);
signal exp_x_uid9_fpCompareTest_merged_bit_select_c : STD_LOGIC_VECTOR (22 downto 0);
signal exp_y_uid23_fpCompareTest_merged_bit_select_b : STD_LOGIC_VECTOR (7 downto 0);
signal exp_y_uid23_fpCompareTest_merged_bit_select_c : STD_LOGIC_VECTOR (22 downto 0);
begin
-- GND(CONSTANT,0)
GND_q <= "0";
-- cstAllZWE_uid8_fpCompareTest(CONSTANT,7)
cstAllZWE_uid8_fpCompareTest_q <= "00000000";
-- exp_y_uid23_fpCompareTest_merged_bit_select(BITSELECT,61)@0
exp_y_uid23_fpCompareTest_merged_bit_select_b <= STD_LOGIC_VECTOR(b(30 downto 23));
exp_y_uid23_fpCompareTest_merged_bit_select_c <= STD_LOGIC_VECTOR(b(22 downto 0));
-- excZ_y_uid25_fpCompareTest(LOGICAL,24)@0
excZ_y_uid25_fpCompareTest_q <= "1" WHEN exp_y_uid23_fpCompareTest_merged_bit_select_b = cstAllZWE_uid8_fpCompareTest_q ELSE "0";
-- exp_x_uid9_fpCompareTest_merged_bit_select(BITSELECT,60)@0
exp_x_uid9_fpCompareTest_merged_bit_select_b <= STD_LOGIC_VECTOR(a(30 downto 23));
exp_x_uid9_fpCompareTest_merged_bit_select_c <= STD_LOGIC_VECTOR(a(22 downto 0));
-- excZ_x_uid11_fpCompareTest(LOGICAL,10)@0
excZ_x_uid11_fpCompareTest_q <= "1" WHEN exp_x_uid9_fpCompareTest_merged_bit_select_b = cstAllZWE_uid8_fpCompareTest_q ELSE "0";
-- bothZero_uid54_fpCompareTest(LOGICAL,53)@0
bothZero_uid54_fpCompareTest_q <= excZ_x_uid11_fpCompareTest_q and excZ_y_uid25_fpCompareTest_q;
-- rCmp_uid57_fpCompareTest(LOGICAL,56)@0
rCmp_uid57_fpCompareTest_q <= "1" WHEN a = b ELSE "0";
-- r_uid58_fpCompareTest(LOGICAL,57)@0
r_uid58_fpCompareTest_q <= rCmp_uid57_fpCompareTest_q or bothZero_uid54_fpCompareTest_q;
-- cstZeroWF_uid7_fpCompareTest(CONSTANT,6)
cstZeroWF_uid7_fpCompareTest_q <= "00000000000000000000000";
-- fracXIsZero_uid27_fpCompareTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCompareTest_q <= "1" WHEN cstZeroWF_uid7_fpCompareTest_q = exp_y_uid23_fpCompareTest_merged_bit_select_c ELSE "0";
-- fracXIsNotZero_uid28_fpCompareTest(LOGICAL,27)@0
fracXIsNotZero_uid28_fpCompareTest_q <= not (fracXIsZero_uid27_fpCompareTest_q);
-- cstAllOWE_uid6_fpCompareTest(CONSTANT,5)
cstAllOWE_uid6_fpCompareTest_q <= "11111111";
-- expXIsMax_uid26_fpCompareTest(LOGICAL,25)@0
expXIsMax_uid26_fpCompareTest_q <= "1" WHEN exp_y_uid23_fpCompareTest_merged_bit_select_b = cstAllOWE_uid6_fpCompareTest_q ELSE "0";
-- excN_y_uid30_fpCompareTest(LOGICAL,29)@0
excN_y_uid30_fpCompareTest_q <= expXIsMax_uid26_fpCompareTest_q and fracXIsNotZero_uid28_fpCompareTest_q;
-- fracXIsZero_uid13_fpCompareTest(LOGICAL,12)@0
fracXIsZero_uid13_fpCompareTest_q <= "1" WHEN cstZeroWF_uid7_fpCompareTest_q = exp_x_uid9_fpCompareTest_merged_bit_select_c ELSE "0";
-- fracXIsNotZero_uid14_fpCompareTest(LOGICAL,13)@0
fracXIsNotZero_uid14_fpCompareTest_q <= not (fracXIsZero_uid13_fpCompareTest_q);
-- expXIsMax_uid12_fpCompareTest(LOGICAL,11)@0
expXIsMax_uid12_fpCompareTest_q <= "1" WHEN exp_x_uid9_fpCompareTest_merged_bit_select_b = cstAllOWE_uid6_fpCompareTest_q ELSE "0";
-- excN_x_uid16_fpCompareTest(LOGICAL,15)@0
excN_x_uid16_fpCompareTest_q <= expXIsMax_uid12_fpCompareTest_q and fracXIsNotZero_uid14_fpCompareTest_q;
-- oneIsNaN_uid34_fpCompareTest(LOGICAL,33)@0
oneIsNaN_uid34_fpCompareTest_q <= excN_x_uid16_fpCompareTest_q or excN_y_uid30_fpCompareTest_q;
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- rPostExc_uid59_fpCompareTest(MUX,58)@0
rPostExc_uid59_fpCompareTest_s <= oneIsNaN_uid34_fpCompareTest_q;
rPostExc_uid59_fpCompareTest_combproc: PROCESS (rPostExc_uid59_fpCompareTest_s, r_uid58_fpCompareTest_q, GND_q)
BEGIN
CASE (rPostExc_uid59_fpCompareTest_s) IS
WHEN "0" => rPostExc_uid59_fpCompareTest_q <= r_uid58_fpCompareTest_q;
WHEN "1" => rPostExc_uid59_fpCompareTest_q <= GND_q;
WHEN OTHERS => rPostExc_uid59_fpCompareTest_q <= (others => '0');
END CASE;
END PROCESS;
-- xOut(GPOUT,4)@0
q <= rPostExc_uid59_fpCompareTest_q;
END normal;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Tue Aug 2 21:54:54 2016
--Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
--Command : generate_target block_design.bd
--Design : block_design
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1RQO0KS is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1RQO0KS;
architecture STRUCTURE of s00_couplers_imp_1RQO0KS is
component block_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component block_design_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : inout STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : inout STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : inout STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end block_design_axi_interconnect_0_0;
architecture STRUCTURE of block_design_axi_interconnect_0_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_ACLK_net : STD_LOGIC;
signal axi_interconnect_0_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= s00_couplers_to_axi_interconnect_0_ARVALID;
M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= s00_couplers_to_axi_interconnect_0_AWVALID;
M00_AXI_bready(0) <= s00_couplers_to_axi_interconnect_0_BREADY;
M00_AXI_rready(0) <= s00_couplers_to_axi_interconnect_0_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= s00_couplers_to_axi_interconnect_0_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_interconnect_0_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_interconnect_0_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= axi_interconnect_0_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_interconnect_0_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= axi_interconnect_0_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= axi_interconnect_0_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_interconnect_0_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_interconnect_0_to_s00_couplers_WREADY;
axi_interconnect_0_ACLK_net <= M00_ACLK;
axi_interconnect_0_ARESETN_net(0) <= M00_ARESETN(0);
axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_interconnect_0_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_interconnect_0_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_interconnect_0_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
axi_interconnect_0_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_interconnect_0_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_axi_interconnect_0_ARREADY(0) <= M00_AXI_arready(0);
s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_axi_interconnect_0_RVALID(0) <= M00_AXI_rvalid(0);
s00_couplers: entity work.s00_couplers_imp_1RQO0KS
port map (
M_ACLK => axi_interconnect_0_ACLK_net,
M_ARESETN(0) => axi_interconnect_0_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => s00_couplers_to_axi_interconnect_0_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => M00_AXI_awready(0),
M_AXI_awvalid => s00_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => s00_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => M00_AXI_bvalid(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_axi_interconnect_0_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => M00_AXI_wready(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => axi_interconnect_0_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_interconnect_0_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_interconnect_0_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => axi_interconnect_0_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => axi_interconnect_0_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_interconnect_0_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => axi_interconnect_0_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => axi_interconnect_0_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_interconnect_0_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => axi_interconnect_0_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => axi_interconnect_0_to_s00_couplers_RLAST,
S_AXI_rready => axi_interconnect_0_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_interconnect_0_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => axi_interconnect_0_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => axi_interconnect_0_to_s00_couplers_WLAST,
S_AXI_wready => axi_interconnect_0_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_interconnect_0_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design is
port (
AC_BCLK : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_I2C_scl_i : in STD_LOGIC;
AC_I2C_scl_o : out STD_LOGIC;
AC_I2C_scl_t : out STD_LOGIC;
AC_I2C_sda_i : in STD_LOGIC;
AC_I2C_sda_o : out STD_LOGIC;
AC_I2C_sda_t : out STD_LOGIC;
AC_MCLK : out STD_LOGIC;
AC_MUTE_N : out STD_LOGIC;
AC_PBLRC : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_RELRC : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_SDATA_I : in STD_LOGIC;
AC_SDATA_O : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
MIC_SPI_io0_i : in STD_LOGIC;
MIC_SPI_io0_o : out STD_LOGIC;
MIC_SPI_io0_t : out STD_LOGIC;
MIC_SPI_io1_i : in STD_LOGIC;
MIC_SPI_io1_o : out STD_LOGIC;
MIC_SPI_io1_t : out STD_LOGIC;
MIC_SPI_sck_i : in STD_LOGIC;
MIC_SPI_sck_o : out STD_LOGIC;
MIC_SPI_sck_t : out STD_LOGIC;
MIC_SPI_ss1_o : out STD_LOGIC;
MIC_SPI_ss2_o : out STD_LOGIC;
MIC_SPI_ss_i : in STD_LOGIC;
MIC_SPI_ss_o : out STD_LOGIC;
MIC_SPI_ss_t : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of block_design : entity is "block_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=block_design,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=4,numNonXlnxBlks=1,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of block_design : entity is "block_design.hwdef";
end block_design;
architecture STRUCTURE of block_design is
component block_design_axi_i2s_adi_0_0 is
port (
DATA_CLK_I : in STD_LOGIC;
BCLK_O : out STD_LOGIC_VECTOR ( 0 to 0 );
LRCLK_O : out STD_LOGIC_VECTOR ( 0 to 0 );
SDATA_O : out STD_LOGIC_VECTOR ( 0 to 0 );
SDATA_I : in STD_LOGIC_VECTOR ( 0 to 0 );
MUTEN_O : out STD_LOGIC;
DMA_REQ_TX_ACLK : in STD_LOGIC;
DMA_REQ_TX_RSTN : in STD_LOGIC;
DMA_REQ_TX_DAVALID : in STD_LOGIC;
DMA_REQ_TX_DATYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA_REQ_TX_DAREADY : out STD_LOGIC;
DMA_REQ_TX_DRVALID : out STD_LOGIC;
DMA_REQ_TX_DRTYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA_REQ_TX_DRLAST : out STD_LOGIC;
DMA_REQ_TX_DRREADY : in STD_LOGIC;
DMA_REQ_RX_ACLK : in STD_LOGIC;
DMA_REQ_RX_RSTN : in STD_LOGIC;
DMA_REQ_RX_DAVALID : in STD_LOGIC;
DMA_REQ_RX_DATYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA_REQ_RX_DAREADY : out STD_LOGIC;
DMA_REQ_RX_DRVALID : out STD_LOGIC;
DMA_REQ_RX_DRTYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA_REQ_RX_DRLAST : out STD_LOGIC;
DMA_REQ_RX_DRREADY : in STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_WREADY : inout STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : inout STD_LOGIC;
S_AXI_AWREADY : inout STD_LOGIC
);
end component block_design_axi_i2s_adi_0_0;
component block_design_processing_system7_0_0 is
port (
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component block_design_processing_system7_0_0;
component block_design_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component block_design_proc_sys_reset_0_0;
signal AC_SDATA_I_1 : STD_LOGIC;
signal ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARREADY : STD_LOGIC;
signal S00_AXI_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARVALID : STD_LOGIC;
signal S00_AXI_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWREADY : STD_LOGIC;
signal S00_AXI_1_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWVALID : STD_LOGIC;
signal S00_AXI_1_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_BREADY : STD_LOGIC;
signal S00_AXI_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_BVALID : STD_LOGIC;
signal S00_AXI_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_RLAST : STD_LOGIC;
signal S00_AXI_1_RREADY : STD_LOGIC;
signal S00_AXI_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_RVALID : STD_LOGIC;
signal S00_AXI_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_WLAST : STD_LOGIC;
signal S00_AXI_1_WREADY : STD_LOGIC;
signal S00_AXI_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_WVALID : STD_LOGIC;
signal axi_i2s_adi_0_BCLK_O : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_i2s_adi_0_DMA_RX_REQ_TLAST : STD_LOGIC;
signal axi_i2s_adi_0_DMA_RX_REQ_TREADY : STD_LOGIC;
signal axi_i2s_adi_0_DMA_RX_REQ_TUSER : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_i2s_adi_0_DMA_RX_REQ_TVALID : STD_LOGIC;
signal axi_i2s_adi_0_DMA_TX_REQ_TLAST : STD_LOGIC;
signal axi_i2s_adi_0_DMA_TX_REQ_TREADY : STD_LOGIC;
signal axi_i2s_adi_0_DMA_TX_REQ_TUSER : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_i2s_adi_0_DMA_TX_REQ_TVALID : STD_LOGIC;
signal axi_i2s_adi_0_MUTEN_O : STD_LOGIC;
signal axi_i2s_adi_0_SDATA_O : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_DMA0_ACK_TREADY : STD_LOGIC;
signal processing_system7_0_DMA0_ACK_TUSER : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_DMA0_ACK_TVALID : STD_LOGIC;
signal processing_system7_0_DMA1_ACK_TREADY : STD_LOGIC;
signal processing_system7_0_DMA1_ACK_TUSER : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_DMA1_ACK_TVALID : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_CLK2 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_I : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_O : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_T : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_I : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_O : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_T : STD_LOGIC;
signal processing_system7_0_SPI_0_IO0_I : STD_LOGIC;
signal processing_system7_0_SPI_0_IO0_O : STD_LOGIC;
signal processing_system7_0_SPI_0_IO0_T : STD_LOGIC;
signal processing_system7_0_SPI_0_IO1_I : STD_LOGIC;
signal processing_system7_0_SPI_0_IO1_O : STD_LOGIC;
signal processing_system7_0_SPI_0_IO1_T : STD_LOGIC;
signal processing_system7_0_SPI_0_SCK_I : STD_LOGIC;
signal processing_system7_0_SPI_0_SCK_O : STD_LOGIC;
signal processing_system7_0_SPI_0_SCK_T : STD_LOGIC;
signal processing_system7_0_SPI_0_SS1_O : STD_LOGIC;
signal processing_system7_0_SPI_0_SS2_O : STD_LOGIC;
signal processing_system7_0_SPI_0_SS_I : STD_LOGIC;
signal processing_system7_0_SPI_0_SS_O : STD_LOGIC;
signal processing_system7_0_SPI_0_SS_T : STD_LOGIC;
signal util_reduced_logic_1_Res : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_0_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
AC_BCLK(0) <= axi_i2s_adi_0_BCLK_O(0);
AC_I2C_scl_o <= processing_system7_0_IIC_0_SCL_O;
AC_I2C_scl_t <= processing_system7_0_IIC_0_SCL_T;
AC_I2C_sda_o <= processing_system7_0_IIC_0_SDA_O;
AC_I2C_sda_t <= processing_system7_0_IIC_0_SDA_T;
AC_MCLK <= processing_system7_0_FCLK_CLK2;
AC_MUTE_N <= axi_i2s_adi_0_MUTEN_O;
AC_PBLRC(0) <= util_reduced_logic_1_Res(0);
AC_RELRC(0) <= util_reduced_logic_1_Res(0);
AC_SDATA_I_1 <= AC_SDATA_I;
AC_SDATA_O(0) <= axi_i2s_adi_0_SDATA_O(0);
MIC_SPI_io0_o <= processing_system7_0_SPI_0_IO0_O;
MIC_SPI_io0_t <= processing_system7_0_SPI_0_IO0_T;
MIC_SPI_io1_o <= processing_system7_0_SPI_0_IO1_O;
MIC_SPI_io1_t <= processing_system7_0_SPI_0_IO1_T;
MIC_SPI_sck_o <= processing_system7_0_SPI_0_SCK_O;
MIC_SPI_sck_t <= processing_system7_0_SPI_0_SCK_T;
MIC_SPI_ss1_o <= processing_system7_0_SPI_0_SS1_O;
MIC_SPI_ss2_o <= processing_system7_0_SPI_0_SS2_O;
MIC_SPI_ss_o <= processing_system7_0_SPI_0_SS_O;
MIC_SPI_ss_t <= processing_system7_0_SPI_0_SS_T;
processing_system7_0_IIC_0_SCL_I <= AC_I2C_scl_i;
processing_system7_0_IIC_0_SDA_I <= AC_I2C_sda_i;
processing_system7_0_SPI_0_IO0_I <= MIC_SPI_io0_i;
processing_system7_0_SPI_0_IO1_I <= MIC_SPI_io1_i;
processing_system7_0_SPI_0_SCK_I <= MIC_SPI_sck_i;
processing_system7_0_SPI_0_SS_I <= MIC_SPI_ss_i;
axi_i2s_adi_0: component block_design_axi_i2s_adi_0_0
port map (
BCLK_O(0) => axi_i2s_adi_0_BCLK_O(0),
DATA_CLK_I => processing_system7_0_FCLK_CLK2,
DMA_REQ_RX_ACLK => processing_system7_0_FCLK_CLK0,
DMA_REQ_RX_DAREADY => processing_system7_0_DMA1_ACK_TREADY,
DMA_REQ_RX_DATYPE(1 downto 0) => processing_system7_0_DMA1_ACK_TUSER(1 downto 0),
DMA_REQ_RX_DAVALID => processing_system7_0_DMA1_ACK_TVALID,
DMA_REQ_RX_DRLAST => axi_i2s_adi_0_DMA_RX_REQ_TLAST,
DMA_REQ_RX_DRREADY => axi_i2s_adi_0_DMA_RX_REQ_TREADY,
DMA_REQ_RX_DRTYPE(1 downto 0) => axi_i2s_adi_0_DMA_RX_REQ_TUSER(1 downto 0),
DMA_REQ_RX_DRVALID => axi_i2s_adi_0_DMA_RX_REQ_TVALID,
DMA_REQ_RX_RSTN => proc_sys_reset_0_peripheral_aresetn(0),
DMA_REQ_TX_ACLK => processing_system7_0_FCLK_CLK0,
DMA_REQ_TX_DAREADY => processing_system7_0_DMA0_ACK_TREADY,
DMA_REQ_TX_DATYPE(1 downto 0) => processing_system7_0_DMA0_ACK_TUSER(1 downto 0),
DMA_REQ_TX_DAVALID => processing_system7_0_DMA0_ACK_TVALID,
DMA_REQ_TX_DRLAST => axi_i2s_adi_0_DMA_TX_REQ_TLAST,
DMA_REQ_TX_DRREADY => axi_i2s_adi_0_DMA_TX_REQ_TREADY,
DMA_REQ_TX_DRTYPE(1 downto 0) => axi_i2s_adi_0_DMA_TX_REQ_TUSER(1 downto 0),
DMA_REQ_TX_DRVALID => axi_i2s_adi_0_DMA_TX_REQ_TVALID,
DMA_REQ_TX_RSTN => proc_sys_reset_0_peripheral_aresetn(0),
LRCLK_O(0) => util_reduced_logic_1_Res(0),
MUTEN_O => axi_i2s_adi_0_MUTEN_O,
SDATA_I(0) => AC_SDATA_I_1,
SDATA_O(0) => axi_i2s_adi_0_SDATA_O(0),
S_AXI_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
S_AXI_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
S_AXI_ARREADY => axi_interconnect_0_M00_AXI_ARREADY,
S_AXI_ARVALID => axi_interconnect_0_M00_AXI_ARVALID(0),
S_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
S_AXI_AWREADY => axi_interconnect_0_M00_AXI_AWREADY,
S_AXI_AWVALID => axi_interconnect_0_M00_AXI_AWVALID(0),
S_AXI_BREADY => axi_interconnect_0_M00_AXI_BREADY(0),
S_AXI_BRESP(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
S_AXI_BVALID => axi_interconnect_0_M00_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
S_AXI_RREADY => axi_interconnect_0_M00_AXI_RREADY(0),
S_AXI_RRESP(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
S_AXI_RVALID => axi_interconnect_0_M00_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
S_AXI_WREADY => axi_interconnect_0_M00_AXI_WREADY,
S_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
S_AXI_WVALID => axi_interconnect_0_M00_AXI_WVALID(0)
);
axi_interconnect_0: entity work.block_design_axi_interconnect_0_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => ARESETN_1(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready(0) => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => axi_interconnect_0_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready(0) => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => axi_interconnect_0_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => axi_interconnect_0_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => axi_interconnect_0_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => axi_interconnect_0_M00_AXI_WVALID(0),
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => S00_AXI_1_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => S00_AXI_1_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => S00_AXI_1_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => S00_AXI_1_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => S00_AXI_1_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => S00_AXI_1_ARQOS(3 downto 0),
S00_AXI_arready => S00_AXI_1_ARREADY,
S00_AXI_arsize(2 downto 0) => S00_AXI_1_ARSIZE(2 downto 0),
S00_AXI_arvalid => S00_AXI_1_ARVALID,
S00_AXI_awaddr(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => S00_AXI_1_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => S00_AXI_1_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => S00_AXI_1_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => S00_AXI_1_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => S00_AXI_1_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => S00_AXI_1_AWQOS(3 downto 0),
S00_AXI_awready => S00_AXI_1_AWREADY,
S00_AXI_awsize(2 downto 0) => S00_AXI_1_AWSIZE(2 downto 0),
S00_AXI_awvalid => S00_AXI_1_AWVALID,
S00_AXI_bid(11 downto 0) => S00_AXI_1_BID(11 downto 0),
S00_AXI_bready => S00_AXI_1_BREADY,
S00_AXI_bresp(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
S00_AXI_bvalid => S00_AXI_1_BVALID,
S00_AXI_rdata(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => S00_AXI_1_RID(11 downto 0),
S00_AXI_rlast => S00_AXI_1_RLAST,
S00_AXI_rready => S00_AXI_1_RREADY,
S00_AXI_rresp(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
S00_AXI_rvalid => S00_AXI_1_RVALID,
S00_AXI_wdata(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => S00_AXI_1_WID(11 downto 0),
S00_AXI_wlast => S00_AXI_1_WLAST,
S00_AXI_wready => S00_AXI_1_WREADY,
S00_AXI_wstrb(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
S00_AXI_wvalid => S00_AXI_1_WVALID
);
proc_sys_reset_0: component block_design_proc_sys_reset_0_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => ARESETN_1(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_0_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
processing_system7_0: component block_design_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
DMA0_ACLK => processing_system7_0_FCLK_CLK0,
DMA0_DAREADY => processing_system7_0_DMA0_ACK_TREADY,
DMA0_DATYPE(1 downto 0) => processing_system7_0_DMA0_ACK_TUSER(1 downto 0),
DMA0_DAVALID => processing_system7_0_DMA0_ACK_TVALID,
DMA0_DRLAST => axi_i2s_adi_0_DMA_TX_REQ_TLAST,
DMA0_DRREADY => axi_i2s_adi_0_DMA_TX_REQ_TREADY,
DMA0_DRTYPE(1 downto 0) => axi_i2s_adi_0_DMA_TX_REQ_TUSER(1 downto 0),
DMA0_DRVALID => axi_i2s_adi_0_DMA_TX_REQ_TVALID,
DMA1_ACLK => processing_system7_0_FCLK_CLK0,
DMA1_DAREADY => processing_system7_0_DMA1_ACK_TREADY,
DMA1_DATYPE(1 downto 0) => processing_system7_0_DMA1_ACK_TUSER(1 downto 0),
DMA1_DAVALID => processing_system7_0_DMA1_ACK_TVALID,
DMA1_DRLAST => axi_i2s_adi_0_DMA_RX_REQ_TLAST,
DMA1_DRREADY => axi_i2s_adi_0_DMA_RX_REQ_TREADY,
DMA1_DRTYPE(1 downto 0) => axi_i2s_adi_0_DMA_RX_REQ_TUSER(1 downto 0),
DMA1_DRVALID => axi_i2s_adi_0_DMA_RX_REQ_TVALID,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_CLK2 => processing_system7_0_FCLK_CLK2,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
I2C0_SCL_I => processing_system7_0_IIC_0_SCL_I,
I2C0_SCL_O => processing_system7_0_IIC_0_SCL_O,
I2C0_SCL_T => processing_system7_0_IIC_0_SCL_T,
I2C0_SDA_I => processing_system7_0_IIC_0_SDA_I,
I2C0_SDA_O => processing_system7_0_IIC_0_SDA_O,
I2C0_SDA_T => processing_system7_0_IIC_0_SDA_T,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => S00_AXI_1_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => S00_AXI_1_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => S00_AXI_1_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => S00_AXI_1_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => S00_AXI_1_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => S00_AXI_1_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => S00_AXI_1_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => S00_AXI_1_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => S00_AXI_1_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => S00_AXI_1_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => S00_AXI_1_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => S00_AXI_1_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => S00_AXI_1_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => S00_AXI_1_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => S00_AXI_1_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => S00_AXI_1_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => S00_AXI_1_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => S00_AXI_1_AWVALID,
M_AXI_GP0_BID(11 downto 0) => S00_AXI_1_BID(11 downto 0),
M_AXI_GP0_BREADY => S00_AXI_1_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
M_AXI_GP0_BVALID => S00_AXI_1_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => S00_AXI_1_RID(11 downto 0),
M_AXI_GP0_RLAST => S00_AXI_1_RLAST,
M_AXI_GP0_RREADY => S00_AXI_1_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
M_AXI_GP0_RVALID => S00_AXI_1_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => S00_AXI_1_WID(11 downto 0),
M_AXI_GP0_WLAST => S00_AXI_1_WLAST,
M_AXI_GP0_WREADY => S00_AXI_1_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => S00_AXI_1_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SPI0_MISO_I => processing_system7_0_SPI_0_IO1_I,
SPI0_MISO_O => processing_system7_0_SPI_0_IO1_O,
SPI0_MISO_T => processing_system7_0_SPI_0_IO1_T,
SPI0_MOSI_I => processing_system7_0_SPI_0_IO0_I,
SPI0_MOSI_O => processing_system7_0_SPI_0_IO0_O,
SPI0_MOSI_T => processing_system7_0_SPI_0_IO0_T,
SPI0_SCLK_I => processing_system7_0_SPI_0_SCK_I,
SPI0_SCLK_O => processing_system7_0_SPI_0_SCK_O,
SPI0_SCLK_T => processing_system7_0_SPI_0_SCK_T,
SPI0_SS1_O => processing_system7_0_SPI_0_SS1_O,
SPI0_SS2_O => processing_system7_0_SPI_0_SS2_O,
SPI0_SS_I => processing_system7_0_SPI_0_SS_I,
SPI0_SS_O => processing_system7_0_SPI_0_SS_O,
SPI0_SS_T => processing_system7_0_SPI_0_SS_T
);
end STRUCTURE;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Tue Aug 2 21:54:54 2016
--Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
--Command : generate_target block_design.bd
--Design : block_design
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1RQO0KS is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1RQO0KS;
architecture STRUCTURE of s00_couplers_imp_1RQO0KS is
component block_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component block_design_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : inout STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : inout STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : inout STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end block_design_axi_interconnect_0_0;
architecture STRUCTURE of block_design_axi_interconnect_0_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_ACLK_net : STD_LOGIC;
signal axi_interconnect_0_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= s00_couplers_to_axi_interconnect_0_ARVALID;
M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= s00_couplers_to_axi_interconnect_0_AWVALID;
M00_AXI_bready(0) <= s00_couplers_to_axi_interconnect_0_BREADY;
M00_AXI_rready(0) <= s00_couplers_to_axi_interconnect_0_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= s00_couplers_to_axi_interconnect_0_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_interconnect_0_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_interconnect_0_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= axi_interconnect_0_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_interconnect_0_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= axi_interconnect_0_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= axi_interconnect_0_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_interconnect_0_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_interconnect_0_to_s00_couplers_WREADY;
axi_interconnect_0_ACLK_net <= M00_ACLK;
axi_interconnect_0_ARESETN_net(0) <= M00_ARESETN(0);
axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_interconnect_0_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_interconnect_0_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_interconnect_0_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
axi_interconnect_0_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_interconnect_0_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_axi_interconnect_0_ARREADY(0) <= M00_AXI_arready(0);
s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_axi_interconnect_0_RVALID(0) <= M00_AXI_rvalid(0);
s00_couplers: entity work.s00_couplers_imp_1RQO0KS
port map (
M_ACLK => axi_interconnect_0_ACLK_net,
M_ARESETN(0) => axi_interconnect_0_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => s00_couplers_to_axi_interconnect_0_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => M00_AXI_awready(0),
M_AXI_awvalid => s00_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => s00_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => M00_AXI_bvalid(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_axi_interconnect_0_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => M00_AXI_wready(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => axi_interconnect_0_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_interconnect_0_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_interconnect_0_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => axi_interconnect_0_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => axi_interconnect_0_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_interconnect_0_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => axi_interconnect_0_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => axi_interconnect_0_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_interconnect_0_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => axi_interconnect_0_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => axi_interconnect_0_to_s00_couplers_RLAST,
S_AXI_rready => axi_interconnect_0_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_interconnect_0_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => axi_interconnect_0_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => axi_interconnect_0_to_s00_couplers_WLAST,
S_AXI_wready => axi_interconnect_0_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_interconnect_0_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design is
port (
AC_BCLK : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_I2C_scl_i : in STD_LOGIC;
AC_I2C_scl_o : out STD_LOGIC;
AC_I2C_scl_t : out STD_LOGIC;
AC_I2C_sda_i : in STD_LOGIC;
AC_I2C_sda_o : out STD_LOGIC;
AC_I2C_sda_t : out STD_LOGIC;
AC_MCLK : out STD_LOGIC;
AC_MUTE_N : out STD_LOGIC;
AC_PBLRC : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_RELRC : out STD_LOGIC_VECTOR ( 0 to 0 );
AC_SDATA_I : in STD_LOGIC;
AC_SDATA_O : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
MIC_SPI_io0_i : in STD_LOGIC;
MIC_SPI_io0_o : out STD_LOGIC;
MIC_SPI_io0_t : out STD_LOGIC;
MIC_SPI_io1_i : in STD_LOGIC;
MIC_SPI_io1_o : out STD_LOGIC;
MIC_SPI_io1_t : out STD_LOGIC;
MIC_SPI_sck_i : in STD_LOGIC;
MIC_SPI_sck_o : out STD_LOGIC;
MIC_SPI_sck_t : out STD_LOGIC;
MIC_SPI_ss1_o : out STD_LOGIC;
MIC_SPI_ss2_o : out STD_LOGIC;
MIC_SPI_ss_i : in STD_LOGIC;
MIC_SPI_ss_o : out STD_LOGIC;
MIC_SPI_ss_t : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of block_design : entity is "block_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=block_design,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=4,numNonXlnxBlks=1,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of block_design : entity is "block_design.hwdef";
end block_design;
architecture STRUCTURE of block_design is
component block_design_axi_i2s_adi_0_0 is
port (
DATA_CLK_I : in STD_LOGIC;
BCLK_O : out STD_LOGIC_VECTOR ( 0 to 0 );
LRCLK_O : out STD_LOGIC_VECTOR ( 0 to 0 );
SDATA_O : out STD_LOGIC_VECTOR ( 0 to 0 );
SDATA_I : in STD_LOGIC_VECTOR ( 0 to 0 );
MUTEN_O : out STD_LOGIC;
DMA_REQ_TX_ACLK : in STD_LOGIC;
DMA_REQ_TX_RSTN : in STD_LOGIC;
DMA_REQ_TX_DAVALID : in STD_LOGIC;
DMA_REQ_TX_DATYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA_REQ_TX_DAREADY : out STD_LOGIC;
DMA_REQ_TX_DRVALID : out STD_LOGIC;
DMA_REQ_TX_DRTYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA_REQ_TX_DRLAST : out STD_LOGIC;
DMA_REQ_TX_DRREADY : in STD_LOGIC;
DMA_REQ_RX_ACLK : in STD_LOGIC;
DMA_REQ_RX_RSTN : in STD_LOGIC;
DMA_REQ_RX_DAVALID : in STD_LOGIC;
DMA_REQ_RX_DATYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA_REQ_RX_DAREADY : out STD_LOGIC;
DMA_REQ_RX_DRVALID : out STD_LOGIC;
DMA_REQ_RX_DRTYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA_REQ_RX_DRLAST : out STD_LOGIC;
DMA_REQ_RX_DRREADY : in STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_WREADY : inout STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : inout STD_LOGIC;
S_AXI_AWREADY : inout STD_LOGIC
);
end component block_design_axi_i2s_adi_0_0;
component block_design_processing_system7_0_0 is
port (
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component block_design_processing_system7_0_0;
component block_design_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component block_design_proc_sys_reset_0_0;
signal AC_SDATA_I_1 : STD_LOGIC;
signal ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARREADY : STD_LOGIC;
signal S00_AXI_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARVALID : STD_LOGIC;
signal S00_AXI_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWREADY : STD_LOGIC;
signal S00_AXI_1_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWVALID : STD_LOGIC;
signal S00_AXI_1_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_BREADY : STD_LOGIC;
signal S00_AXI_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_BVALID : STD_LOGIC;
signal S00_AXI_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_RLAST : STD_LOGIC;
signal S00_AXI_1_RREADY : STD_LOGIC;
signal S00_AXI_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_RVALID : STD_LOGIC;
signal S00_AXI_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_WLAST : STD_LOGIC;
signal S00_AXI_1_WREADY : STD_LOGIC;
signal S00_AXI_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_WVALID : STD_LOGIC;
signal axi_i2s_adi_0_BCLK_O : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_i2s_adi_0_DMA_RX_REQ_TLAST : STD_LOGIC;
signal axi_i2s_adi_0_DMA_RX_REQ_TREADY : STD_LOGIC;
signal axi_i2s_adi_0_DMA_RX_REQ_TUSER : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_i2s_adi_0_DMA_RX_REQ_TVALID : STD_LOGIC;
signal axi_i2s_adi_0_DMA_TX_REQ_TLAST : STD_LOGIC;
signal axi_i2s_adi_0_DMA_TX_REQ_TREADY : STD_LOGIC;
signal axi_i2s_adi_0_DMA_TX_REQ_TUSER : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_i2s_adi_0_DMA_TX_REQ_TVALID : STD_LOGIC;
signal axi_i2s_adi_0_MUTEN_O : STD_LOGIC;
signal axi_i2s_adi_0_SDATA_O : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_DMA0_ACK_TREADY : STD_LOGIC;
signal processing_system7_0_DMA0_ACK_TUSER : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_DMA0_ACK_TVALID : STD_LOGIC;
signal processing_system7_0_DMA1_ACK_TREADY : STD_LOGIC;
signal processing_system7_0_DMA1_ACK_TUSER : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_DMA1_ACK_TVALID : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_CLK2 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_I : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_O : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_T : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_I : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_O : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_T : STD_LOGIC;
signal processing_system7_0_SPI_0_IO0_I : STD_LOGIC;
signal processing_system7_0_SPI_0_IO0_O : STD_LOGIC;
signal processing_system7_0_SPI_0_IO0_T : STD_LOGIC;
signal processing_system7_0_SPI_0_IO1_I : STD_LOGIC;
signal processing_system7_0_SPI_0_IO1_O : STD_LOGIC;
signal processing_system7_0_SPI_0_IO1_T : STD_LOGIC;
signal processing_system7_0_SPI_0_SCK_I : STD_LOGIC;
signal processing_system7_0_SPI_0_SCK_O : STD_LOGIC;
signal processing_system7_0_SPI_0_SCK_T : STD_LOGIC;
signal processing_system7_0_SPI_0_SS1_O : STD_LOGIC;
signal processing_system7_0_SPI_0_SS2_O : STD_LOGIC;
signal processing_system7_0_SPI_0_SS_I : STD_LOGIC;
signal processing_system7_0_SPI_0_SS_O : STD_LOGIC;
signal processing_system7_0_SPI_0_SS_T : STD_LOGIC;
signal util_reduced_logic_1_Res : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_0_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
AC_BCLK(0) <= axi_i2s_adi_0_BCLK_O(0);
AC_I2C_scl_o <= processing_system7_0_IIC_0_SCL_O;
AC_I2C_scl_t <= processing_system7_0_IIC_0_SCL_T;
AC_I2C_sda_o <= processing_system7_0_IIC_0_SDA_O;
AC_I2C_sda_t <= processing_system7_0_IIC_0_SDA_T;
AC_MCLK <= processing_system7_0_FCLK_CLK2;
AC_MUTE_N <= axi_i2s_adi_0_MUTEN_O;
AC_PBLRC(0) <= util_reduced_logic_1_Res(0);
AC_RELRC(0) <= util_reduced_logic_1_Res(0);
AC_SDATA_I_1 <= AC_SDATA_I;
AC_SDATA_O(0) <= axi_i2s_adi_0_SDATA_O(0);
MIC_SPI_io0_o <= processing_system7_0_SPI_0_IO0_O;
MIC_SPI_io0_t <= processing_system7_0_SPI_0_IO0_T;
MIC_SPI_io1_o <= processing_system7_0_SPI_0_IO1_O;
MIC_SPI_io1_t <= processing_system7_0_SPI_0_IO1_T;
MIC_SPI_sck_o <= processing_system7_0_SPI_0_SCK_O;
MIC_SPI_sck_t <= processing_system7_0_SPI_0_SCK_T;
MIC_SPI_ss1_o <= processing_system7_0_SPI_0_SS1_O;
MIC_SPI_ss2_o <= processing_system7_0_SPI_0_SS2_O;
MIC_SPI_ss_o <= processing_system7_0_SPI_0_SS_O;
MIC_SPI_ss_t <= processing_system7_0_SPI_0_SS_T;
processing_system7_0_IIC_0_SCL_I <= AC_I2C_scl_i;
processing_system7_0_IIC_0_SDA_I <= AC_I2C_sda_i;
processing_system7_0_SPI_0_IO0_I <= MIC_SPI_io0_i;
processing_system7_0_SPI_0_IO1_I <= MIC_SPI_io1_i;
processing_system7_0_SPI_0_SCK_I <= MIC_SPI_sck_i;
processing_system7_0_SPI_0_SS_I <= MIC_SPI_ss_i;
axi_i2s_adi_0: component block_design_axi_i2s_adi_0_0
port map (
BCLK_O(0) => axi_i2s_adi_0_BCLK_O(0),
DATA_CLK_I => processing_system7_0_FCLK_CLK2,
DMA_REQ_RX_ACLK => processing_system7_0_FCLK_CLK0,
DMA_REQ_RX_DAREADY => processing_system7_0_DMA1_ACK_TREADY,
DMA_REQ_RX_DATYPE(1 downto 0) => processing_system7_0_DMA1_ACK_TUSER(1 downto 0),
DMA_REQ_RX_DAVALID => processing_system7_0_DMA1_ACK_TVALID,
DMA_REQ_RX_DRLAST => axi_i2s_adi_0_DMA_RX_REQ_TLAST,
DMA_REQ_RX_DRREADY => axi_i2s_adi_0_DMA_RX_REQ_TREADY,
DMA_REQ_RX_DRTYPE(1 downto 0) => axi_i2s_adi_0_DMA_RX_REQ_TUSER(1 downto 0),
DMA_REQ_RX_DRVALID => axi_i2s_adi_0_DMA_RX_REQ_TVALID,
DMA_REQ_RX_RSTN => proc_sys_reset_0_peripheral_aresetn(0),
DMA_REQ_TX_ACLK => processing_system7_0_FCLK_CLK0,
DMA_REQ_TX_DAREADY => processing_system7_0_DMA0_ACK_TREADY,
DMA_REQ_TX_DATYPE(1 downto 0) => processing_system7_0_DMA0_ACK_TUSER(1 downto 0),
DMA_REQ_TX_DAVALID => processing_system7_0_DMA0_ACK_TVALID,
DMA_REQ_TX_DRLAST => axi_i2s_adi_0_DMA_TX_REQ_TLAST,
DMA_REQ_TX_DRREADY => axi_i2s_adi_0_DMA_TX_REQ_TREADY,
DMA_REQ_TX_DRTYPE(1 downto 0) => axi_i2s_adi_0_DMA_TX_REQ_TUSER(1 downto 0),
DMA_REQ_TX_DRVALID => axi_i2s_adi_0_DMA_TX_REQ_TVALID,
DMA_REQ_TX_RSTN => proc_sys_reset_0_peripheral_aresetn(0),
LRCLK_O(0) => util_reduced_logic_1_Res(0),
MUTEN_O => axi_i2s_adi_0_MUTEN_O,
SDATA_I(0) => AC_SDATA_I_1,
SDATA_O(0) => axi_i2s_adi_0_SDATA_O(0),
S_AXI_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
S_AXI_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
S_AXI_ARREADY => axi_interconnect_0_M00_AXI_ARREADY,
S_AXI_ARVALID => axi_interconnect_0_M00_AXI_ARVALID(0),
S_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
S_AXI_AWREADY => axi_interconnect_0_M00_AXI_AWREADY,
S_AXI_AWVALID => axi_interconnect_0_M00_AXI_AWVALID(0),
S_AXI_BREADY => axi_interconnect_0_M00_AXI_BREADY(0),
S_AXI_BRESP(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
S_AXI_BVALID => axi_interconnect_0_M00_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
S_AXI_RREADY => axi_interconnect_0_M00_AXI_RREADY(0),
S_AXI_RRESP(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
S_AXI_RVALID => axi_interconnect_0_M00_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
S_AXI_WREADY => axi_interconnect_0_M00_AXI_WREADY,
S_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
S_AXI_WVALID => axi_interconnect_0_M00_AXI_WVALID(0)
);
axi_interconnect_0: entity work.block_design_axi_interconnect_0_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => ARESETN_1(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready(0) => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => axi_interconnect_0_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready(0) => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => axi_interconnect_0_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => axi_interconnect_0_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => axi_interconnect_0_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => axi_interconnect_0_M00_AXI_WVALID(0),
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => S00_AXI_1_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => S00_AXI_1_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => S00_AXI_1_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => S00_AXI_1_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => S00_AXI_1_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => S00_AXI_1_ARQOS(3 downto 0),
S00_AXI_arready => S00_AXI_1_ARREADY,
S00_AXI_arsize(2 downto 0) => S00_AXI_1_ARSIZE(2 downto 0),
S00_AXI_arvalid => S00_AXI_1_ARVALID,
S00_AXI_awaddr(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => S00_AXI_1_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => S00_AXI_1_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => S00_AXI_1_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => S00_AXI_1_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => S00_AXI_1_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => S00_AXI_1_AWQOS(3 downto 0),
S00_AXI_awready => S00_AXI_1_AWREADY,
S00_AXI_awsize(2 downto 0) => S00_AXI_1_AWSIZE(2 downto 0),
S00_AXI_awvalid => S00_AXI_1_AWVALID,
S00_AXI_bid(11 downto 0) => S00_AXI_1_BID(11 downto 0),
S00_AXI_bready => S00_AXI_1_BREADY,
S00_AXI_bresp(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
S00_AXI_bvalid => S00_AXI_1_BVALID,
S00_AXI_rdata(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => S00_AXI_1_RID(11 downto 0),
S00_AXI_rlast => S00_AXI_1_RLAST,
S00_AXI_rready => S00_AXI_1_RREADY,
S00_AXI_rresp(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
S00_AXI_rvalid => S00_AXI_1_RVALID,
S00_AXI_wdata(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => S00_AXI_1_WID(11 downto 0),
S00_AXI_wlast => S00_AXI_1_WLAST,
S00_AXI_wready => S00_AXI_1_WREADY,
S00_AXI_wstrb(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
S00_AXI_wvalid => S00_AXI_1_WVALID
);
proc_sys_reset_0: component block_design_proc_sys_reset_0_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => ARESETN_1(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_0_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
processing_system7_0: component block_design_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
DMA0_ACLK => processing_system7_0_FCLK_CLK0,
DMA0_DAREADY => processing_system7_0_DMA0_ACK_TREADY,
DMA0_DATYPE(1 downto 0) => processing_system7_0_DMA0_ACK_TUSER(1 downto 0),
DMA0_DAVALID => processing_system7_0_DMA0_ACK_TVALID,
DMA0_DRLAST => axi_i2s_adi_0_DMA_TX_REQ_TLAST,
DMA0_DRREADY => axi_i2s_adi_0_DMA_TX_REQ_TREADY,
DMA0_DRTYPE(1 downto 0) => axi_i2s_adi_0_DMA_TX_REQ_TUSER(1 downto 0),
DMA0_DRVALID => axi_i2s_adi_0_DMA_TX_REQ_TVALID,
DMA1_ACLK => processing_system7_0_FCLK_CLK0,
DMA1_DAREADY => processing_system7_0_DMA1_ACK_TREADY,
DMA1_DATYPE(1 downto 0) => processing_system7_0_DMA1_ACK_TUSER(1 downto 0),
DMA1_DAVALID => processing_system7_0_DMA1_ACK_TVALID,
DMA1_DRLAST => axi_i2s_adi_0_DMA_RX_REQ_TLAST,
DMA1_DRREADY => axi_i2s_adi_0_DMA_RX_REQ_TREADY,
DMA1_DRTYPE(1 downto 0) => axi_i2s_adi_0_DMA_RX_REQ_TUSER(1 downto 0),
DMA1_DRVALID => axi_i2s_adi_0_DMA_RX_REQ_TVALID,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_CLK2 => processing_system7_0_FCLK_CLK2,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
I2C0_SCL_I => processing_system7_0_IIC_0_SCL_I,
I2C0_SCL_O => processing_system7_0_IIC_0_SCL_O,
I2C0_SCL_T => processing_system7_0_IIC_0_SCL_T,
I2C0_SDA_I => processing_system7_0_IIC_0_SDA_I,
I2C0_SDA_O => processing_system7_0_IIC_0_SDA_O,
I2C0_SDA_T => processing_system7_0_IIC_0_SDA_T,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => S00_AXI_1_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => S00_AXI_1_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => S00_AXI_1_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => S00_AXI_1_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => S00_AXI_1_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => S00_AXI_1_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => S00_AXI_1_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => S00_AXI_1_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => S00_AXI_1_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => S00_AXI_1_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => S00_AXI_1_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => S00_AXI_1_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => S00_AXI_1_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => S00_AXI_1_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => S00_AXI_1_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => S00_AXI_1_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => S00_AXI_1_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => S00_AXI_1_AWVALID,
M_AXI_GP0_BID(11 downto 0) => S00_AXI_1_BID(11 downto 0),
M_AXI_GP0_BREADY => S00_AXI_1_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
M_AXI_GP0_BVALID => S00_AXI_1_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => S00_AXI_1_RID(11 downto 0),
M_AXI_GP0_RLAST => S00_AXI_1_RLAST,
M_AXI_GP0_RREADY => S00_AXI_1_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
M_AXI_GP0_RVALID => S00_AXI_1_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => S00_AXI_1_WID(11 downto 0),
M_AXI_GP0_WLAST => S00_AXI_1_WLAST,
M_AXI_GP0_WREADY => S00_AXI_1_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => S00_AXI_1_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SPI0_MISO_I => processing_system7_0_SPI_0_IO1_I,
SPI0_MISO_O => processing_system7_0_SPI_0_IO1_O,
SPI0_MISO_T => processing_system7_0_SPI_0_IO1_T,
SPI0_MOSI_I => processing_system7_0_SPI_0_IO0_I,
SPI0_MOSI_O => processing_system7_0_SPI_0_IO0_O,
SPI0_MOSI_T => processing_system7_0_SPI_0_IO0_T,
SPI0_SCLK_I => processing_system7_0_SPI_0_SCK_I,
SPI0_SCLK_O => processing_system7_0_SPI_0_SCK_O,
SPI0_SCLK_T => processing_system7_0_SPI_0_SCK_T,
SPI0_SS1_O => processing_system7_0_SPI_0_SS1_O,
SPI0_SS2_O => processing_system7_0_SPI_0_SS2_O,
SPI0_SS_I => processing_system7_0_SPI_0_SS_I,
SPI0_SS_O => processing_system7_0_SPI_0_SS_O,
SPI0_SS_T => processing_system7_0_SPI_0_SS_T
);
end STRUCTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
-- Date : Tue Dec 13 22:50:05 2016
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- d:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/KeyboardCtrl_0/KeyboardCtrl_0_stub.vhdl
-- Design : KeyboardCtrl_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity KeyboardCtrl_0 is
Port (
key_in : out STD_LOGIC_VECTOR ( 7 downto 0 );
is_extend : out STD_LOGIC;
is_break : out STD_LOGIC;
valid : out STD_LOGIC;
err : out STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC
);
end KeyboardCtrl_0;
architecture stub of KeyboardCtrl_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "key_in[7:0],is_extend,is_break,valid,err,PS2_DATA,PS2_CLK,rst,clk";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "KeyboardCtrl,Vivado 2016.2";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
-- Date : Tue Dec 13 22:50:05 2016
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- d:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/KeyboardCtrl_0/KeyboardCtrl_0_stub.vhdl
-- Design : KeyboardCtrl_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity KeyboardCtrl_0 is
Port (
key_in : out STD_LOGIC_VECTOR ( 7 downto 0 );
is_extend : out STD_LOGIC;
is_break : out STD_LOGIC;
valid : out STD_LOGIC;
err : out STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC
);
end KeyboardCtrl_0;
architecture stub of KeyboardCtrl_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "key_in[7:0],is_extend,is_break,valid,err,PS2_DATA,PS2_CLK,rst,clk";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "KeyboardCtrl,Vivado 2016.2";
begin
end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_vga:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_vga_0_0 IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END system_zed_vga_0_0;
ARCHITECTURE system_zed_vga_0_0_arch OF system_zed_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_vga IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT zed_vga;
BEGIN
U0 : zed_vga
PORT MAP (
rgb565 => rgb565,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
END system_zed_vga_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_vga:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_vga_0_0 IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END system_zed_vga_0_0;
ARCHITECTURE system_zed_vga_0_0_arch OF system_zed_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_vga IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT zed_vga;
BEGIN
U0 : zed_vga
PORT MAP (
rgb565 => rgb565,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
END system_zed_vga_0_0_arch;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:07:02 01/05/2014
-- Design Name:
-- Module Name: G:/Project_Block_Mario/TestBench_VGA.vhd
-- Project Name: Block_Mario
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: VGA_driver
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TestBench_VGA IS
END TestBench_VGA;
ARCHITECTURE behavior OF TestBench_VGA IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT VGA_driver
PORT(
clk_25MHz : IN std_logic;
color : IN std_logic_vector(7 downto 0);
HSYNC : OUT std_logic;
VSYNC : OUT std_logic;
OutRed : OUT std_logic_vector(2 downto 0);
OutGreen : OUT std_logic_vector(2 downto 0);
OutBlue : OUT std_logic_vector(2 downto 1);
hmemc : out integer range 0 to 31; -- Bitmap x
vmemc : out integer range 0 to 23; -- Bitmap y
hbmpc : out integer range 0 to 19; -- Pixel in bitmap x
vbmpc : out integer range 0 to 19 -- Pixel in bitmap y
);
END COMPONENT;
-- Clock period definitions
constant clk_25MHz_period : time := 10 ns;
--Inputs
signal clk_25MHz : std_logic := '0';
signal color : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal HSYNC : std_logic;
signal VSYNC : std_logic;
signal OutRed : std_logic_vector(2 downto 0);
signal OutGreen : std_logic_vector(2 downto 0);
signal OutBlue : std_logic_vector(2 downto 1);
signal hmemc : integer range 0 to 31; -- Bitmap x
signal vmemc : integer range 0 to 23; -- Bitmap y
signal hbmpc : integer range 0 to 19; -- Pixel in bitmap x
signal vbmpc : integer range 0 to 19; -- Pixel in bitmap y
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: VGA_driver PORT MAP (
clk_25MHz => clk_25MHz,
color => color,
HSYNC => HSYNC,
VSYNC => VSYNC,
OutRed => OutRed,
OutGreen => OutGreen,
OutBlue => OutBlue,
hmemc => hmemc,
vmemc => vmemc,
hbmpc => hbmpc,
vbmpc => vbmpc
);
-- Clock process definitions
clk_25MHz_process :process
begin
clk_25MHz <= '0';
wait for clk_25MHz_period/2;
clk_25MHz <= '1';
wait for clk_25MHz_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- welke kleur word weergegeven is niet van belang
color <= "01010101";
-- alle stappen uit de tel cyclus afgaan om 1 scherm naar buiten te brengne
for i in 1 to 307200 loop
wait for 10 ns;
end loop;
wait;
end process;
END;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <kubakici@wp.pl>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_mem_reader IS
END tb_mem_reader;
ARCHITECTURE behavior OF tb_mem_reader IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mem_reader
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
FrameLen : IN std_logic_vector(10 downto 0);
FrameIval : IN std_logic_vector(27 downto 0);
BusPkt : OUT std_logic;
BusData : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal FrameLen : std_logic_vector(10 downto 0) := (others => '0');
signal FrameIval : std_logic_vector(27 downto 0) := (others => '0');
--Outputs
signal BusPkt : std_logic;
signal BusData : std_logic_vector(7 downto 0);
signal Clk_o : std_logic;
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
Clk_o <= transport Clk after 8 ns;
-- Instantiate the Unit Under Test (UUT)
uut: mem_reader PORT MAP (
Clk => Clk,
Rst => Rst,
FrameLen => FrameLen,
FrameIval => FrameIval,
BusPkt => BusPkt,
BusData => BusData
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
FrameLen <= b"000" & X"4c";
FrameIval <= ( 7 => '1', others => '0' );
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
--
-- File: UART RX
-- Author: Rob Baummer
--
-- Description: A 8x oversampling UART receiver from 9600 to 57600 baud. Uses
-- 1 start bit, 1 stop bit and no parity.
--------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
entity uart_rx is
port (
--System Interface
reset : in std_logic;
enable : in std_logic;
sys_clk : in std_logic;
--UART serial interface
DIN : in std_logic;
--Receiver interface
baud_en : in std_logic;
rx_byte : out std_logic_vector(7 downto 0);
rx_valid : out std_logic;
rx_frame_error : out std_logic;
rx_break : out std_logic
);
end uart_rx;
architecture behavorial of uart_rx is
signal cnt_rst : std_logic;
signal cnt_en : std_logic;
signal cnt : std_logic_vector(2 downto 0);
signal bit_cnt_en : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal data_reg: std_logic_vector(7 downto 0);
signal frame_error : std_logic;
signal frame_error_reg : std_logic;
signal valid : std_logic;
signal valid_reg : std_logic;
signal shift : std_logic;
signal shift_dly : std_logic;
signal bit_in : std_logic;
signal sample_reg : std_logic_vector(2 downto 0);
type statetype is (idle, start, data, stop, frame_err);
signal cs, ns : statetype;
begin
--RX Byte
rx_byte <= data_reg;
--Edge detection of valid signal
rx_valid <= valid and not valid_reg;
--Edge detection of frame error signal
rx_frame_error <= frame_error and not frame_error_reg;
--Sequential process for RX Statemachine
--Baud_en is used as an enable to allow state machine to operate at proper
--frequency
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' or enable = '0' then
cs <= idle;
elsif baud_en = '1' then
cs <= ns;
end if;
end if;
end process;
--Next State Combinatorial process
process (cs, cnt, bit_cnt_en, DIN)
begin
--default values for output signals
cnt_rst <= '0';
cnt_en <= '0';
bit_cnt_en <= '0';
frame_error <= '0';
valid <= '0';
shift <= '0';
case cs is
--wait for DIN = 0 which signals a start bit
when idle =>
cnt_rst <= '1';
if DIN = '0' then
ns <= start;
else
ns <= idle;
end if;
--potential start bit found, test at midpoint to verify start
when start =>
--test at midpoint of serial symbol
if cnt = "011" then
--reset 8x oversampling counter at centerpoint of start bit
cnt_rst <= '1';
--if input is a start bit DIN will still equal 0
if DIN = '0' then
ns <= data;
--false start bit, return to idle and wait for valid start
else
ns <= idle;
end if;
else
cnt_rst <= '0';
ns <= start;
end if;
--valid start found, start sampling data at midpoint of bits
when data =>
--8 counts from center of start bit is the center of a data bit
if cnt = "111" then
--shift in next serial bit
shift <= '1';
--increment bit counter
bit_cnt_en <= '1';
--if 8 bits captured start looking for stop bit
if bit_cnt = "111" then
ns <= stop;
else
ns <= data;
end if;
--wait for center of data bit
else
shift <= '0';
bit_cnt_en <= '0';
ns <= data;
end if;
--check for valid stop bit
when stop =>
--sample DIN at center of stop bit
if cnt = "111" then
--valid stop bit if DIN = '1'
if DIN = '1' then
valid <= '1';
--returning to idle allows resyncing of start bit
ns <= idle;
--generate frame error is stop bit is invalid
else
valid <= '0';
ns <= frame_err;
end if;
--wait for center of stop bit
else
valid <= '0';
ns <= stop;
end if;
--invalid stop bit found, generate frame_error
when frame_err =>
frame_error <= '1';
ns <= idle;
when others =>
ns <= idle;
end case;
end process;
--8x oversampling counter
--oversampling counter is used to determine optimal sampling time of asynchronous DIN
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' or (cnt_rst = '1' and baud_en = '1') then
cnt <= "000";
--baud_en allows counter to operate at proper baud rate
elsif baud_en = '1' then
cnt <= cnt + "001";
end if;
end if;
end process;
--bit counter
--bit counter determines how many bits have been received
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
bit_cnt <= "000";
--baud_en allows counter to operate at proper baud rate
elsif baud_en = '1' and bit_cnt_en = '1' then
bit_cnt <= bit_cnt + "001";
end if;
end if;
end process;
--sample shift register
--for majority vote around bit center to help prevent glitches causing faulty byte
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
sample_reg <= "000";
elsif baud_en = '1' then
sample_reg <= DIN & sample_reg(2 downto 1);
end if;
end if;
end process;
--Majority voter
bit_in <= (sample_reg(0) and sample_reg(1)) or (sample_reg(1) and sample_reg(2)) or (sample_reg(0) and sample_reg(2));
--shift delay register
--delay the shift by a baud_en to get the sample after the bit center
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
shift_dly <= '0';
elsif baud_en = '1' then
shift_dly <= shift;
end if;
end if;
end process;
--byte shift register
--collect the serial bits as they are received
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
data_reg <= X"00";
--capture serial bit when commanded
elsif shift_dly = '1' and baud_en = '1' then
data_reg <= bit_in & data_reg(7 downto 1);
end if;
end if;
end process;
--break detection
rx_break <= '1' when data_reg = X"00" and frame_error = '1' else '0';
--Edge detection registers
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
valid_reg <= '0';
frame_error_reg <= '0';
else
valid_reg <= valid;
frame_error_reg <= frame_error;
end if;
end if;
end process;
end behavorial;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SEUdisp30 is
Port ( disp30 : in STD_LOGIC_VECTOR (29 downto 0);
SEUdisp30 : out STD_LOGIC_VECTOR (31 downto 0));
end SEUdisp30;
architecture Behavioral of SEUdisp30 is
begin
process(disp30)
begin
if disp30(29)='1' then
SEUdisp30<="11"&disp30;
else
SEUdisp30<="00"&disp30;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 11.1
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM32to16.vhd
-- /___/ /\ Timestamp : 07/29/2010 14:42:37
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st C:\dbdev\My Dropbox\GadgetFactory\AVR8\svn\trunk\ipcore_dir\DCM32to16.xaw C:\dbdev\My Dropbox\GadgetFactory\AVR8\svn\trunk\ipcore_dir\DCM32to16
--Design Name: DCM32to16
--Device: xc3s250e-4vq100
--
-- Module DCM32to16
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 3.43 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM32to16 is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic);
end DCM32to16;
architecture BEHAVIORAL of DCM32to16 is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 16,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 11.1
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM32to16.vhd
-- /___/ /\ Timestamp : 07/29/2010 14:42:37
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st C:\dbdev\My Dropbox\GadgetFactory\AVR8\svn\trunk\ipcore_dir\DCM32to16.xaw C:\dbdev\My Dropbox\GadgetFactory\AVR8\svn\trunk\ipcore_dir\DCM32to16
--Design Name: DCM32to16
--Device: xc3s250e-4vq100
--
-- Module DCM32to16
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 3.43 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM32to16 is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic);
end DCM32to16;
architecture BEHAVIORAL of DCM32to16 is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 16,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 11.1
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM32to16.vhd
-- /___/ /\ Timestamp : 07/29/2010 14:42:37
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st C:\dbdev\My Dropbox\GadgetFactory\AVR8\svn\trunk\ipcore_dir\DCM32to16.xaw C:\dbdev\My Dropbox\GadgetFactory\AVR8\svn\trunk\ipcore_dir\DCM32to16
--Design Name: DCM32to16
--Device: xc3s250e-4vq100
--
-- Module DCM32to16
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 3.43 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM32to16 is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic);
end DCM32to16;
architecture BEHAVIORAL of DCM32to16 is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 16,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc155.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p16n02i00155pkg is
procedure P1 (a: in integer; b: out integer);
end c04s03b02x02p16n02i00155pkg;
package body c04s03b02x02p16n02i00155pkg is
procedure P1 (a: in integer; b: out integer) is
begin
b := a;
end;
end c04s03b02x02p16n02i00155pkg;
use work.c04s03b02x02p16n02i00155pkg.all;
ENTITY c04s03b02x02p16n02i00155ent IS
END c04s03b02x02p16n02i00155ent;
ARCHITECTURE c04s03b02x02p16n02i00155arch OF c04s03b02x02p16n02i00155ent IS
BEGIN
TESTING: PROCESS
variable x : real := 1.0;
BEGIN
P1 (10, b => x); -- Failure_here
-- b and x have different types
assert FALSE
report "***FAILED TEST: c04s03b02x02p16n02i00155 - Type mis-match during procedure call."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p16n02i00155arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc155.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p16n02i00155pkg is
procedure P1 (a: in integer; b: out integer);
end c04s03b02x02p16n02i00155pkg;
package body c04s03b02x02p16n02i00155pkg is
procedure P1 (a: in integer; b: out integer) is
begin
b := a;
end;
end c04s03b02x02p16n02i00155pkg;
use work.c04s03b02x02p16n02i00155pkg.all;
ENTITY c04s03b02x02p16n02i00155ent IS
END c04s03b02x02p16n02i00155ent;
ARCHITECTURE c04s03b02x02p16n02i00155arch OF c04s03b02x02p16n02i00155ent IS
BEGIN
TESTING: PROCESS
variable x : real := 1.0;
BEGIN
P1 (10, b => x); -- Failure_here
-- b and x have different types
assert FALSE
report "***FAILED TEST: c04s03b02x02p16n02i00155 - Type mis-match during procedure call."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p16n02i00155arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc155.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p16n02i00155pkg is
procedure P1 (a: in integer; b: out integer);
end c04s03b02x02p16n02i00155pkg;
package body c04s03b02x02p16n02i00155pkg is
procedure P1 (a: in integer; b: out integer) is
begin
b := a;
end;
end c04s03b02x02p16n02i00155pkg;
use work.c04s03b02x02p16n02i00155pkg.all;
ENTITY c04s03b02x02p16n02i00155ent IS
END c04s03b02x02p16n02i00155ent;
ARCHITECTURE c04s03b02x02p16n02i00155arch OF c04s03b02x02p16n02i00155ent IS
BEGIN
TESTING: PROCESS
variable x : real := 1.0;
BEGIN
P1 (10, b => x); -- Failure_here
-- b and x have different types
assert FALSE
report "***FAILED TEST: c04s03b02x02p16n02i00155 - Type mis-match during procedure call."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p16n02i00155arch;
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