content stringlengths 1 1.04M ⌀ |
|---|
entity implicit is
end entity;
architecture test of implicit is
signal x : integer;
begin
process is
begin
assert x'delayed = 4; -- OK
assert x'delayed(1 ns) = 5; -- OK
assert x'delayed(5) = 1; -- Error
assert x'stable; -- OK
asse... |
entity implicit is
end entity;
architecture test of implicit is
signal x : integer;
begin
process is
begin
assert x'delayed = 4; -- OK
assert x'delayed(1 ns) = 5; -- OK
assert x'delayed(5) = 1; -- Error
assert x'stable; -- OK
asse... |
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
package pp_types is
--! Type used for register addresses.
subtype ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function CX_GEN(current_address, network_x, network_y : integer) return in... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use I... |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-------------------------------------------------------------------------------
-- Title : CLock
-- Project :
-------------------------------------------------------------------------------
-- File : disp.vhd
-- Author : Daniel Sun <dcsun88osh@gmail.com>
-- Company :
-- Created : 2016-05-14
-... |
-------------------------------------------------------------------------------
-- system_ilmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b... |
-------------------------------------------------------------------------------
-- system_ilmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 21 11:24:56 2017
-- Host : vldmr-PC running 64-bit Service ... |
----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free ... |
----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
--
-- Title : dma_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\dma_handler.vhd
-- Generated :... |
-------------------------------------------------------------------------------
--
-- Title : dma_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\dma_handler.vhd
-- Generated :... |
-------------------------------------------------------------------------------
--
-- Title : dma_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\dma_handler.vhd
-- Generated :... |
library IEEE;
use IEEE.std_logic_1164.all;
entity R_UC is
port(
clock : in std_logic;
reset : in std_logic;
e_s : in std_logic;
amostra : in std_logic;
finaliza_recepcao : in std_logic;
tick : in std_logic;
amostrando ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_decoder IS
END tb_decoder;
ARCHITECTURE behavior OF tb_decoder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT decoder
PORT(
CLK : IN std_logic;
RST : IN std_logic;
code : IN std_logic_vector... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( NZVC : in STD_LOGIC_VECTOR (3 downto 0);
nCWP: in STD_LOGIC;
CLK: in STD_LOGIC;
rst: in STD_LOGIC;
CWP: out STD_LOGIC;
C : out STD_LOGIC);
end PSR;
architecture Behavioral of PSR is
signal PSRegister: s... |
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY InstruccionMemory_tb IS
END InstruccionMemory_tb;
ARCHITECTURE behavior OF InstruccionMemory_tb IS
-- Component Decla... |
entity alias4 is
end entity;
architecture test of alias4 is
function func(x : bit_vector(7 downto 0); k : bit_vector) return bit is
alias y : bit_vector(k'range) is x;
begin
return y(1);
end function;
begin
process is
variable x : bit_vector(7 downto 0);
begin
x :... |
entity alias4 is
end entity;
architecture test of alias4 is
function func(x : bit_vector(7 downto 0); k : bit_vector) return bit is
alias y : bit_vector(k'range) is x;
begin
return y(1);
end function;
begin
process is
variable x : bit_vector(7 downto 0);
begin
x :... |
entity alias4 is
end entity;
architecture test of alias4 is
function func(x : bit_vector(7 downto 0); k : bit_vector) return bit is
alias y : bit_vector(k'range) is x;
begin
return y(1);
end function;
begin
process is
variable x : bit_vector(7 downto 0);
begin
x :... |
entity alias4 is
end entity;
architecture test of alias4 is
function func(x : bit_vector(7 downto 0); k : bit_vector) return bit is
alias y : bit_vector(k'range) is x;
begin
return y(1);
end function;
begin
process is
variable x : bit_vector(7 downto 0);
begin
x :... |
entity alias4 is
end entity;
architecture test of alias4 is
function func(x : bit_vector(7 downto 0); k : bit_vector) return bit is
alias y : bit_vector(k'range) is x;
begin
return y(1);
end function;
begin
process is
variable x : bit_vector(7 downto 0);
begin
x :... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis... |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.idram_components.all;
use work.idram_utils.all;
entity idram is
generic (
--Port types: 0 -> AXI4Lite, 1 -> AXI3, 2 -> AXI4
INSTR_PORT_TYPE : natural range 0 to 2 := 0;
DATA_PORT_TYPE : natural range 0 to 2 :=... |
----------------------------------------------------------------------------------------------------
-- Reduce Test-bench
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
------------------------------------------------... |
---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author... |
---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author... |
---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture behavior of {{entity_name}} is
begin
end behavior;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture behavior of {{entity_name}} is
begin
end behavior;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: test bench for the FPU core
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity uc01 is
port(
clkuc: in std_logic ;
inACuc: in std_logic_vector ( 7 downto 0 );
FlagInstuc: inout std_logic ;
outACuc: out std_logic_vector ( 7 downto 0 );
FlagReadyuc: out std_logic );
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNAGWQMRGS is
generic ( decode : string := "000000000000000000000000";
pipelin... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNAGWQMRGS is
generic ( decode : string := "000000000000000000000000";
pipelin... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:40:58 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Documents/Frecuencimetroo/Frecuencimentro/divisor_tb.vhd
-- Project Name: Frecuencimentro
-- Target Device: ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:40:58 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Documents/Frecuencimetroo/Frecuencimentro/divisor_tb.vhd
-- Project Name: Frecuencimentro
-- Target Device: ... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_ok_9_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
library verilog;
use verilog.vl_types.all;
entity HAZARD is
port(
Rt_IF_ID : in vl_logic_vector(4 downto 0);
Rs_IF_ID : in vl_logic_vector(4 downto 0);
Rt_ID_EX : in vl_logic_vector(4 downto 0);
RtRead_IF_ID : in vl_logic;
Jump ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- highpass_filter.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.log2;
library utils_v1_00_a;
use ... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY datapath IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
RESETX, RESETY, incr_y, incr_x, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0); -- x0
y : OUT STD_LOGIC_VECTOR(6 downto... |
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design... |
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design... |
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design... |
-------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 08
-- Project :
-------------------------------------------------------------------------------
-- File : audio_ctrl.vhd
-- Author : Jonas Nikula, Tuomas Huuki
-- Company : TUT
-- Created ... |
-- Twofish_ecb_vk_testbench_128bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any late... |
------------------------------------------------------------------------------
-- Title : Wishbone BPM SWAP interface
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------... |
-- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_bidir
-- ============================================================
-- File Name: bidir_dqs_iobuf_inst.vhd
-- Megafunction Name(s):
-- altiobuf_bidir
--
-- Simulation Library Files(s):
-- stratixiii
-- ===========... |
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:06:18 10/01/2014
-- Design Name:
-- Module Name: E:/2014/Academico/OC/2014/tp2/TB_SN54LV165A.vhd
-- Project Name: tp2
-- Target Device:
-- Tool versions:
-- Description:
--
--... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Wed Jul 20 01:57:48 2016
-- Host : jalapeno running 64-bit unknown
-- C... |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= ... |
entity mixer_tb is
end;
use work.mixer_pkg.all;
architecture behav of mixer_tb is
signal s : sample_array(0 to 127)(3 downto 0);
begin
inst : entity work.mixer generic map (sample_bits => 4)
port map(i_samples => s);
end behav;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
--
-- Title : mux4
-- Design : lab1
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\lab1\lab1\compi... |
-------------------------------------------------------------------------------
--
-- Title : mux4
-- Design : lab1
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\lab1\lab1\compi... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity OpenRest_module is
Port (
Play_Done : in STD_LOGIC;
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Data_in : in STD_LOGIC_VECTOR (4 downto 0);
Request_Set : out STD_LOGIC;
X_out : out STD_LOGIC_VECTOR (4 ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pixel_difference_1d is
Port ( i_clk : in STD_LOGIC;
i_reset : in STD_LOGIC;
i_R : in STD_LOGIC_VECTOR (7 downto 0);
i_G : in STD_LOGIC_VECTOR (7 downto 0);
i_B : in STD_LOGIC_VECTOR (7 downto 0);
i_framevalid ... |
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of In... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Tue Aug 2 21:54:54 2016
--Host : andrewandrepowell2-desktop running 64-bit... |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Tue Aug 2 21:54:54 2016
--Host : andrewandrepowell2-desktop running 64-bit... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
-- Date : Tue Dec 13 22:50:05 2016
-- Host : KLight-PC running 64-bit major relea... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
-- Date : Tue Dec 13 22:50:05 2016
-- Host : KLight-PC running 64-bit major relea... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:07:02 01/05/2014
-- Design Name:
-- Module Name: G:/Project_Block_Mario/TestBench_VGA.vhd
-- Project Name: Block_Mario
-- Target Device:
-- Tool versions:
-- Description... |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful... |
--------------------------------------------------------------------------------
--
-- File: UART RX
-- Author: Rob Baummer
--
-- Description: A 8x oversampling UART receiver from 9600 to 57600 baud. Uses
-- 1 start bit, 1 stop bit and no parity.
------------------------------------------------------------------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SEUdisp30 is
Port ( disp30 : in STD_LOGIC_VECTOR (29 downto 0);
SEUdisp30 : out STD_LOGIC_VECTOR (31 downto 0));
end SEUdisp30;
architecture Behavioral of SEUdisp30 is
begin
process(disp30)
begin
if disp30(29)='1' then
SEUdisp30<="11"... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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