content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- Title : MC613
-- Project : PS2 Basic Protocol
-- Details : www.ic.unicamp.br/~corte/mc613/
-- www.computer-engineering.org/ps2protocol/
-------------------------------------------------------------------------------
-- F... |
entity test is
end;
use work.pkg;
use work.mygpkg;
architecture behav of test is
begin
assert mygpkg.test = 17;
end behav;
|
entity test is
end;
use work.pkg;
use work.mygpkg;
architecture behav of test is
begin
assert mygpkg.test = 17;
end behav;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:18:21 2017
-- Host : GILAMONSTER running 64-bit major rel... |
entity ent is
generic (str : string);
end entity;
architecture a of ent is
begin
main : process
begin
report str;
wait;
end process;
end architecture;
|
entity ent is
generic (str : string);
end entity;
architecture a of ent is
begin
main : process
begin
report str;
wait;
end process;
end architecture;
|
entity ent is
generic (str : string);
end entity;
architecture a of ent is
begin
main : process
begin
report str;
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PS2Controller is
port (Reset : in STD_LOGIC;
Clock : in STD_LOGIC;
PS2Clock : inout STD_LOGIC;
PS2Data : inout STD_LOGIC;
Send : in STD_LOGIC;
Command : in STD_LOGIC_V... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity wh_code_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(1 downto 0)
);
end wh_code_table;
architecture augh of wh_code_table is
-- Embedded RAM
type... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity wh_code_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(1 downto 0)
);
end wh_code_table;
architecture augh of wh_code_table is
-- Embedded RAM
type... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity wh_code_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(1 downto 0)
);
end wh_code_table;
architecture augh of wh_code_table is
-- Embedded RAM
type... |
-- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later v... |
-------------------------------------------------------------------------------
-- Title : Cache content memory
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : cache_data_mem.vhd
-- Author ... |
library ieee;
use ieee.std_logic_1164.all;
entity bug is
port (clk : in std_logic;
rst : in std_logic);
end entity bug;
architecture Behavioral of bug is
type rc_params is array (natural range <>) of std_logic_vector(7 downto 0);
type rc_params_array is array (natural range <>) of rc_params;
type rc... |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License... |
-------------------------------------------------------------------------------
--
-- Title : mux
-- Design : lab1
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : mux.vhd
-- Generated : Tue ... |
-------------------------------------------------------------------------------
--
-- Title : mux
-- Design : lab1
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : mux.vhd
-- Generated : Tue ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
library verilog;
use verilog.vl_types.all;
entity \register\ is
generic(
WIDTH : integer := 32;
RESET_VALUE : integer := 0
);
port(
d : in vl_logic_vector;
clk : in vl_logic;
rst_b : in vl_logic;
en... |
-- ***********************************************
-- ** PROYECTO PDUA **
-- ** Modulo: ROM **
-- ** Creacion: Julio 07 **
-- ** Revisión: Marzo 08 **
-- ** Por: MGH-CMUA-UNIANDES **
-- ***********************************************
-- De... |
--============================================================================
--!
--! \file full_adder.vhd
--!
--! \project full_adder
--!
--! \langv VHDL-2008
--!
--! \brief A full adder.
--!
--! \details -
--!
--! \bug -
--!
--! \see -
--!
--! \copyright GPLv2
--!
--! Revision history:
-... |
-------------------------------------------------------------------------------
--
-- File: tb_TestTop.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodAWG1411_Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorpo... |
-------------------------------------------------------------------------------
--
-- Testbench for the T411 system toplevel.
--
-- $Id: tb_t411-c.vhd,v 1.2 2006-05-15 21:56:02 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
--------------------------------------... |
----------------------------------------------------------------------------------
--Creado por: Juan Carlos Solar Coeto.
-- Puebla, México
-- juan.carlos.sc3@gmail.com
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
us... |
----------------------------------------------
-- Module Name: ClockController - switch --
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity ClockController is
port ( clock : in std_logic;
sw0 : in std_logic;
... |
package gol_types is
type neighbourhood_t is array (7 downto 0) of integer range 0 to 1;
end package gol_types;
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gol_types.all;
entity test_cell is
end test_cell;
architecture behavioural of test_cell is
signal clock : std_logic;... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:27:52 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-------------------------------------------------------------------------------
-- Model Title: Voltage Source - Gaussian pulse
-- Entity Name: vsrc_gaussian_pulse
-- Author: Vladimir Kolchuzhin <vladimir.kolchuzhin@ieee.org>
-- Created: 2021/01/07
-- Library: kvl in hAMSter
-----------------------------------... |
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks1@umassd.edu)
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S5... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ddrv4
--
-- Generated
-- by: wig
-- on: Wed Jul 5 07:04:19 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig ... |
entity bug is
end entity bug;
architecture bug of bug is
signal uninitialized_real:real; -- yea--this is poor coding practice
begin
process
begin
report "bug="&real'image(uninitialized_real); -- prints out initial value -1.797693134862316e308
wait for 1 ns;
uninitialized_real<=2... |
entity module is
generic(
);
end entity;
|
entity module is
generic(
);
end entity;
|
entity module is
generic(
);
end entity;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions ... |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: H.42... |
--##############################################################################
-- ion_core_tb.vhdl -- Test bench for full ION core.
--
-- Simulates the full ION core, which includes TCM and caches.
--
--------------------------------------------------------------------------------
-- KNOWN BUGS AND MISSING THINGS:
-... |
-------------------------------------------------------------------------------
-- Title : PC flow misprediciton module
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : Instruction_Mispredic... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further informati... |
-- written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity cp3_test is
port(
clock : in std_logic;
reset : in std_logic;
n_error : out std_logic;
stopped : out std_logic
);
end cp3_test;
architecture rtl of c... |
-- written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity cp3_test is
port(
clock : in std_logic;
reset : in std_logic;
n_error : out std_logic;
stopped : out std_logic
);
end cp3_test;
architecture rtl of c... |
-- written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity cp3_test is
port(
clock : in std_logic;
reset : in std_logic;
n_error : out std_logic;
stopped : out std_logic
);
end cp3_test;
architecture rtl of c... |
-- written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_tb.all;
entity cp3_test is
port(
clock : in std_logic;
reset : in std_logic;
n_error : out std_logic;
stopped : out std_logic
);
end cp3_test;
architecture rtl of c... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_ram_pulse_generator is
generic(
delay_pulse : vl_logic := Hi0;
start_delay : vl_notype
);
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logi... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_ram_pulse_generator is
generic(
delay_pulse : vl_logic := Hi0;
start_delay : vl_notype
);
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logi... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_ram_pulse_generator is
generic(
delay_pulse : vl_logic := Hi0;
start_delay : vl_notype
);
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logi... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_ram_pulse_generator is
generic(
delay_pulse : vl_logic := Hi0;
start_delay : vl_notype
);
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logi... |
library verilog;
use verilog.vl_types.all;
entity common_28nm_ram_pulse_generator is
generic(
delay_pulse : vl_logic := Hi0;
start_delay : vl_notype
);
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logi... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refe... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refe... |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refe... |
library ieee;
use ieee.std_logic_1164.all;
entity has_zero_width_port is
port(
width_one_port: out std_logic_vector(0 downto 0);
width_zero_port: out std_logic_vector(-1 downto 0)
);
end entity;
architecture arch of has_zero_width_port is
begin
width_one_port <= (others => '0');
width_zero_port <= (... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_timing is
port(
clk, rst: in std_logic;
HS, VS: out std_logic;
pixel_x, pixel_y: out std_logic_vector(9 downto 0);
last_column, last_row, blank: out std_logic
);
end vga_timing;
architecture arch of vga_timing is
signal pixel_... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
package vga_pkg is
type vga_output_signals_type is record
-- This is simply a copy of the input pixel clock used for VGA timing;
-- it is added to this record because it must be handed over to the video DAC
vga_clock_out: std_logic;
... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE work.float_types.all;
USE work.float_components.all;
USE work.float_constants.all;
USE work.sram_types.all;
USE work.sram_components.all;
USE work.lfsr_components.all;
USE work.ann_types.all;
USE work.ann_component... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_COR is
Port ( ALUaddress : in STD_LOGIC_VECTOR (31 downto 0);
PC_dis30 : in STD_LOGIC_VECTOR (31 downto 0);
PC_seu : in STD_LOGIC_VECTOR (31 downto 0);
PC_4 : in STD_LOGIC_VECTOR (4 downto 0);
PCsource : in STD_L... |
-- adsb receiver test bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity adsb_recv_tb is
end adsb_recv_tb;
architecture behav of adsb_recv_tb is
component adsb_recv
generic (
width : positive;
samp_rate : positive
);
port (
clk : in std_logic;
rst : in... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: RANDOM_GENERATOR
-- AUTHORS: Vojtěch Jeřábek <xjerab17@stud.feec.vutbr.cz>
-- LICENSE: The MIT License, ple... |
-- $Id: sramif_mig_nexys4d.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sramif_mig_nexys4d - syn
-- Descripti... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity fase2 is
port( KEY : in std_logic_vector(1 downto 0);
SW : in std_logic_vector(0 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX4 : out... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:02:39 09/28/2017
-- Design Name:
-- Module Name: C:/Users/utp/Desktop/TEMPORAL/ALU/ALU_tb.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description: ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:02:39 09/28/2017
-- Design Name:
-- Module Name: C:/Users/utp/Desktop/TEMPORAL/ALU/ALU_tb.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description: ... |
entity e is
end entity;
architecture a of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type bad1 is protected
procedure foo (x : not_her... |
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: tb_elem-sd-c.vhd,v 1.1 2005-02-08 21:09:20 arniml Exp $
--
-------------------------------------------------------------------------------
configuration tb_elem_behav_sd of tb_elem is
for behav
fo... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package types is
subtype byte_t is std_logic_vector( 7 downto 0);
subtype word_t is std_logic_vector(15 downto 0);
subtype op_t is std_logic_vector( 5 downto 0);
subtype alu_op_t is std_logic_vector( 4 downto 0);
s... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fulladder IS
port (cin, x0, y0 : IN BIT;
s0, cout : OUT BIT);
END fulladder;
ARCHITECTURE soma OF fulladder IS
BEGIN
s0 <= (x0 xor y0) xor cin;
cout <= (x0 and (y0 or cin)) or (cin and y0);
END soma; |
library work;
use work.tl_flat_memory_model_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cache_tc_1 is
end;
architecture tc of cache_tc_1 is
shared variable dram : h_mem_object;
... |
library work;
use work.tl_flat_memory_model_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cache_tc_1 is
end;
architecture tc of cache_tc_1 is
shared variable dram : h_mem_object;
... |
library work;
use work.tl_flat_memory_model_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cache_tc_1 is
end;
architecture tc of cache_tc_1 is
shared variable dram : h_mem_object;
... |
library work;
use work.tl_flat_memory_model_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cache_tc_1 is
end;
architecture tc of cache_tc_1 is
shared variable dram : h_mem_object;
... |
library work;
use work.tl_flat_memory_model_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cache_tc_1 is
end;
architecture tc of cache_tc_1 is
shared variable dram : h_mem_object;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: video_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- =============================... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR_LV is
generic (
DATA_WIDTH: integer := 11
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_... |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
begin
end block;
BLOCK_LABEL : block is
signal sig1 : std_logic;
begin
end block;
-- Violations below
BLOCK_LABEL : block is
signal sig1 : std_logic;
begin
end block;
end architecture RTL;
|
-------------------------------------------------------------------------------
--! @file aes128Pkg.vhd
--! @brief AES-128 Package
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber (mbgh@iis.ee.ethz.ch)
--! @company Integrated Systems Laboratory, ETH Zurich
--! @copyright ... |
-- NEED RESULT: ARCH00067.P1_1: Exit with a label and no condition only effects labeled loop passed
-- NEED RESULT: ARCH00067.P1_1: Exit with a label and no condition only effects labeled loop passed
-- NEED RESULT: ARCH00067.P1_1: Exit statement does not effect outer loop passed
-- NEED RESULT: ARCH00067.P1_2: Exit... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
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