content stringlengths 1 1.04M ⌀ |
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_05_19 is
end entity fg_05_19;
architecture test of fg_05_19 is
constant scheduling_delay : delay_length := 5 ns;
subtype request_type is natural range 0 to 20;
type server_status_type is (ready, busy);
signal first_priority_request,
first_normal_request,
reset_request : request_type := 0;
signal functional_request, equivalent_request : request_type;
signal priority_waiting : boolean := false;
signal server_status : server_status_type := busy;
begin
functional_scheduler : block is
port ( request : out request_type );
port map ( request => functional_request );
begin
-- code from book
scheduler :
request <= first_priority_request after scheduling_delay
when priority_waiting and server_status = ready else
first_normal_request after scheduling_delay
when not priority_waiting and server_status = ready else
unaffected
when server_status = busy else
reset_request after scheduling_delay;
-- end code from book
end block functional_scheduler;
--------------------------------------------------
equivalent_scheduler : block is
port ( request : out request_type );
port map ( request => equivalent_request );
begin
-- code from book
scheduler : process is
begin
if priority_waiting and server_status = ready then
request <= first_priority_request after scheduling_delay;
elsif not priority_waiting and server_status = ready then
request <= first_normal_request after scheduling_delay;
elsif server_status = busy then
null;
else
request <= reset_request after scheduling_delay;
end if;
wait on first_priority_request, priority_waiting, server_status,
first_normal_request, reset_request;
end process scheduler;
-- end code from book
end block equivalent_scheduler;
--------------------------------------------------
stimulus : process is
begin
first_priority_request <= 10; wait for 20 ns;
first_normal_request <= 5; wait for 20 ns;
server_status <= ready; wait for 20 ns;
server_status <= busy; wait for 20 ns;
priority_waiting <= true; wait for 20 ns;
server_status <= ready; wait for 20 ns;
first_normal_request <= 7; wait for 20 ns;
first_priority_request <= 12; wait for 20 ns;
wait;
end process stimulus;
verifier :
assert functional_request = equivalent_request
report "Functional and equivalent models give different results";
end architecture test;
|
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`protect begin_protected
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 62784)
`protect data_block
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`protect begin_protected
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|
`protect begin_protected
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 62784)
`protect data_block
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`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
entity progmem is
port(
clk : in std_logic;
addra : in std_logic_vector(11 downto 0);
ena : in std_logic;
doa : out t_data2;
dib : in t_data2;
addrb : in std_logic_vector(11 downto 0);
enb : in std_logic;
web : in std_logic_vector(1 downto 0);
dob : out t_data2
);
end progmem;
architecture Structural of progmem is
signal mem : t_data2_array(4095 downto 0);
signal di0 : t_data;
signal di1 : t_data;
begin
-- "simple" xilinx style ram with byte wide write enable...
process(web, dib)
begin
if web(1) = '1' then
di1 <= dib(15 downto 8);
else
di1 <= mem(to_integer(unsigned(addrb)))(15 downto 8);
end if;
if web(0) = '1' then
di0 <= dib(7 downto 0);
else
di0 <= mem(to_integer(unsigned(addrb)))(7 downto 0);
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if ena = '1' then
doa <= mem(to_integer(unsigned(addra)));
end if;
if enb = '1' then
mem(to_integer(unsigned(addrb))) <= di1 & di0;
dob <= mem(to_integer(unsigned(addrb)));
end if;
end if;
end process;
end Structural;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Sep 19 10:21:53 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.vhdl
-- Design : ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Arithmetic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Artithmetic Unit
-- Operations - Add, Sub, Addi
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arith_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Arith_Unit;
architecture Combinational of Arith_Unit is
signal a1, b1 : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
signal arith : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
begin
-- Give extra bit to accound for carry,overflow,negative
a1 <= '0' & A;
b1 <= '0' & B;
with OP select
arith <=
a1 + b1 when "000", -- ADD
a1 - b1 when "001", -- SUB
a1 + b1 when "101", -- ADDI
a1 + b1 when OTHERS;
CCR(3) <= arith(7); -- Negative
CCR(2) <= '1' when arith(7 downto 0) = x"0000" else '0'; -- Zero
CCR(1) <= arith(8) xor arith(7); -- Overflow
CCR(0) <= arith(8); --Carry
RESULT <= arith(7 downto 0);
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Arithmetic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Artithmetic Unit
-- Operations - Add, Sub, Addi
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arith_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Arith_Unit;
architecture Combinational of Arith_Unit is
signal a1, b1 : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
signal arith : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
begin
-- Give extra bit to accound for carry,overflow,negative
a1 <= '0' & A;
b1 <= '0' & B;
with OP select
arith <=
a1 + b1 when "000", -- ADD
a1 - b1 when "001", -- SUB
a1 + b1 when "101", -- ADDI
a1 + b1 when OTHERS;
CCR(3) <= arith(7); -- Negative
CCR(2) <= '1' when arith(7 downto 0) = x"0000" else '0'; -- Zero
CCR(1) <= arith(8) xor arith(7); -- Overflow
CCR(0) <= arith(8); --Carry
RESULT <= arith(7 downto 0);
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Arithmetic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Artithmetic Unit
-- Operations - Add, Sub, Addi
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arith_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Arith_Unit;
architecture Combinational of Arith_Unit is
signal a1, b1 : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
signal arith : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
begin
-- Give extra bit to accound for carry,overflow,negative
a1 <= '0' & A;
b1 <= '0' & B;
with OP select
arith <=
a1 + b1 when "000", -- ADD
a1 - b1 when "001", -- SUB
a1 + b1 when "101", -- ADDI
a1 + b1 when OTHERS;
CCR(3) <= arith(7); -- Negative
CCR(2) <= '1' when arith(7 downto 0) = x"0000" else '0'; -- Zero
CCR(1) <= arith(8) xor arith(7); -- Overflow
CCR(0) <= arith(8); --Carry
RESULT <= arith(7 downto 0);
end Combinational;
|
-----------------------------------------------------------------------------
-- LEON3 Terasic Sockit demonstration design
-- By Martin George
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
--library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- --DDR3--
DDR3_A : out std_logic_vector(14 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_CAS_n : out std_logic;
DDR3_CKE : out std_logic;
DDR_CK_n : out std_logic;
DDR3_CK_p : out std_logic;
DDR3_CS_n : out std_logic;
DDR3_DM : out std_logic_vector(3 downto 0);
DDR3_DQ : inout std_logic_vector(31 downto 0);
DDR3_DQS_n : inout std_logic_vector(3 downto 0);
DDR3_DQS_p : inout std_logic_vector(3 downto 0);
DDR3_ODT : out std_logic;
DDR3_RAS_n : out std_logic;
DDR3_RESET_n : out std_logic;
DDR3_RZQ : in std_logic;
DDR3_WE_n : out std_logic;
--
--
-- --FAN CONTROL--
-- FAN_CTRL : out std_logic;
--
--
---- --HPS--
HPS_CONV_USB_n : inout std_logic;
HPS_DDR3_A : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_n : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CK_n : out std_logic;
HPS_DDR3_CK_p : out std_logic;
HPS_DDR3_CS_n : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_n : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_p : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic; --output HPS_DDR3_ODT,
HPS_DDR3_RAS_n : out std_logic; --output HPS_DDR3_RAS_n,
HPS_DDR3_RESET_n : out std_logic; --output HPS_DDR3_RESET_n,
HPS_DDR3_RZQ : in std_logic; --input HPS_DDR3_RZQ,
HPS_DDR3_WE_n : out std_logic; --output
HPS_ENET_GTX_CLK : out std_logic; --output HPS_ENET_GTX_CLK,
HPS_ENET_INT_n : inout std_logic; --inout HPS_ENET_INT_n,
HPS_ENET_MDC : out std_logic; --output HPS_ENET_MDC,
HPS_ENET_MDIO : inout std_logic; --inout HPS_ENET_MDIO,
HPS_ENET_RX_CLK : in std_logic; --input HPS_ENET_RX_CLK,
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); --input [3:0] HPS_ENET_RX_DATA,
HPS_ENET_RX_DV : in std_logic; --input HPS_ENET_RX_DV,
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); --output [3:0] HPS_ENET_TX_DATA,
HPS_ENET_TX_EN : out std_logic; --output HPS_ENET_TX_EN,
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0); --inout [3:0] HPS_FLASH_DATA,
HPS_FLASH_DCLK : out std_logic; --output HPS_FLASH_DCLK,
HPS_FLASH_NCSO : out std_logic; --output HPS_FLASH_NCSO,
HPS_GSENSOR_INT : inout std_logic; --inout HPS_GSENSOR_INT,
HPS_I2C_CLK : inout std_logic; --inout HPS_I2C_CLK,
HPS_I2C_SDA : inout std_logic; --inout HPS_I2C_SDA,
-- HPS_KEY : inout std_logic_vector(3 downto 0); --inout [3:0] HPS_KEY,
HPS_LCM_BK : inout std_logic; --inout HPS_LCM_BK,
HPS_LCM_D_C : inout std_logic; --output HPS_LCM_D_C,
HPS_LCM_RST_N : inout std_logic; --output HPS_LCM_RST_N,
HPS_LCM_SPIM_CLK : out std_logic; --input HPS_LCM_SPIM_CLK,
HPS_LCM_SPIM_MOSI : out std_logic; --output HPS_LCM_SPIM_MOSI,
HPS_LCM_SPIM_SS : out std_logic; --output HPS_LCM_SPIM_SS,
HPS_LCM_SPIM_MISO : in std_logic;
HPS_LED : inout std_logic_vector(3 downto 0); --output [3:0] HPS_LED,
HPS_LTC_GPIO : inout std_logic; --inout HPS_LTC_GPIO,
HPS_SD_CLK : out std_logic; --output HPS_SD_CLK,
HPS_SD_CMD : inout std_logic; --inout HPS_SD_CMD,
HPS_SD_DATA : inout std_logic_vector(3 downto 0); --inout [3:0] HPS_SD_DATA,
HPS_SPIM_CLK : out std_logic; --output HPS_SPIM_CLK,
HPS_SPIM_MISO : in std_logic; --input HPS_SPIM_MISO,
HPS_SPIM_MOSI : out std_logic; --output HPS_SPIM_MOSI,
HPS_SPIM_SS : out std_logic; --output HPS_SPIM_SS,
-- HPS_SW : in std_logic_vector(3 downto 0); --input [3:0] HPS_SW,
HPS_UART_RX : in std_logic; --input HPS_UART_RX,
HPS_UART_TX : out std_logic; --output HPS_UART_TX,
HPS_USB_CLKOUT : in std_logic; --input HPS_USB_CLKOUT,
HPS_USB_DATA : inout std_logic_vector(7 downto 0); --inout [7:0] HPS_USB_DATA,
HPS_USB_DIR : in std_logic; --input HPS_USB_DIR,
HPS_USB_NXT : in std_logic; --input HPS_USB_NXT,
HPS_USB_STP : out std_logic; --output HPS_USB_STP,
--
-- --Audio--
-- AUD_ADCDAT : in std_logic; --input AUD_ADCDAT,
-- AUD_ADCLRCK : inout std_logic; --inout AUD_ADCLRCK,
-- AUD_BCLK : inout std_logic; --inout AUD_BCLK,
-- AUD_DACDAT : out std_logic; --output AUD_DACDAT,
-- AUD_DACLRCK : inout std_logic; --inout AUD_DACLRCK,
-- AUD_I2C_SCLK : out std_logic; --output AUD_I2C_SCLK,
-- AUD_I2C_SDAT : inout std_logic; --inout AUD_I2C_SDAT,
-- AUD_MUTE : out std_logic; --output AUD_MUTE,
-- AUD_XCK : out std_logic; --output AUD_XCK,
--
-- --HSMC--
-- HSMC_CLKIN_n : in std_logic_vector(2 downto 1); --input [2:1] HSMC_CLKIN_n,
-- HSMC_CLKIN_p : in std_logic_vector(2 downto 1); --input [2:1] HSMC_CLKIN_p,
-- HSMC_CLKOUT_n : out std_logic_vector(2 downto 1); --output [2:1] HSMC_CLKOUT_n,
-- HSMC_CLKOUT_p : out std_logic_vector(2 downto 1); --output [2:1] HSMC_CLKOUT_p,
-- HSMC_CLK_IN0 : out std_logic; --output HSMC_CLK_IN0,
-- HSMC_CLK_OUT0 : out std_logic; --output HSMC_CLK_OUT0,
-- HSMC_D : inout std_logic_vector(3 downto 0); --inout [3:0] HSMC_D,
-- HSMC_GXB_RX_p : in std_logic_vector(7 downto 0); --input [7:0] HSMC_GXB_RX_p,
-- HSMC_GXB_TX_p : out std_logic_vector(7 downto 0); --output [7:0] HSMC_GXB_TX_p,
-- HSMC_REF_CLK_p : in std_logic; --input HSMC_REF_CLK_p,
-- HSMC_RX_n : inout std_logic_vector(16 downto 0); --inout [16:0] HSMC_RX_n,
-- HSMC_RX_p : inout std_logic_vector(16 downto 0); --inout [16:0] HSMC_RX_p,
-- HSMC_SCL : out std_logic; --output HSMC_SCL,
-- HSMC_SDA : inout std_logic; --inout HSMC_SDA,
-- HSMC_TX_n : inout std_logic_vector(16 downto 0); --inout [16:0] HSMC_TX_n,
-- HSMC_TX_p : inout std_logic_vector(16 downto 0); --inout [16:0] HSMC_TX_p,
--
-- --IRDA--
-- IRDA_RXD : in std_logic; --input IRDA_RXD,
--
-- --PCIE--
-- PCIE_PERST_n : in std_logic; --input PCIE_PERST_n,
-- PCIE_WAKE_n : out std_logic; --output PCIE_WAKE_n,
--
-- --SI5338--
-- SI5338_SCL : in std_logic; --inout SI5338_SCL,
-- SI5338_SDA : in std_logic; --inout SI5338_SDA,
--
--TEMP--
-- TEMP_CS_n : out std_logic; --output TEMP_CS_n,
-- TEMP_DIN : out std_logic; --output TEMP_DIN,
-- TEMP_DOUT : in std_logic; --input TEMP_DOUT,
-- TEMP_SCLK : out std_logic; --output TEMP_SCLK,
--
-- --USB--
-- USB_B2_CLK : in std_logic; --input USB_B2_CLK,
-- USB_B2_DATA : inout std_logic_vector(7 downto 0); --inout [7:0] USB_B2_DATA,
-- USB_EMPTY : out std_logic; --output USB_EMPTY,
-- USB_FULL : out std_logic; --output USB_FULL,
-- USB_OE_n : in std_logic; --input USB_OE_n,
-- USB_RD_n : in std_logic; --input USB_RD_n,
-- USB_RESET_n : in std_logic; --input USB_RESET_n,
-- USB_SCL : inout std_logic; --inout USB_SCL,
-- USB_SDA : inout std_logic; --inout USB_SDA,
-- USB_WR_n : in std_logic; --input USB_WR_n,
--
-- --VGA--
-- VGA_B : out std_logic_vector(7 downto 0); --output [7:0] VGA_B,
-- VGA_BLANK_n : out std_logic; --output VGA_BLANK_n,
-- VGA_CLK : out std_logic; --output VGA_CLK,
-- VGA_G : out std_logic_vector(7 downto 0); --output [7:0] VGA_G,
-- VGA_HS : out std_logic; --output VGA_HS,
-- VGA_R : out std_logic_vector(7 downto 0); --output [7:0] VGA_R,
-- VGA_SYNC_n : out std_logic; --output VGA_SYNC_n,
-- VGA_VS : out std_logic; --output VGA_VS
--OSC (CLOCKS)--
OSC_50_B3B : in std_logic;
OSC_50_B4A : in std_logic;
OSC_50_B5B : in std_logic;
OSC_50_B8A : in std_logic;
--RESET--
RESET_n : in std_logic;
--KEY (PUSHBUTTONS)--
KEY : in std_logic_vector(3 downto 0);
--LED--
LED : out std_logic_vector(3 downto 0);
--SW (SWITCHES)--
SW : in std_logic_vector(3 downto 0)
);
end;
architecture rtl of leon3mp is
constant USE_AHBREP: integer := 0
--pragma translate_off
+1
--pragma translate_on
;
-- Bus indexes
constant hmi_cpu : integer := 0;
constant hmi_ahbuart : integer := hmi_cpu + CFG_NCPU;
constant hmi_ahbjtag : integer := hmi_ahbuart + CFG_AHB_UART;
constant hmi_axi2ahb : integer := hmi_ahbjtag + CFG_AHB_JTAG;
constant nahbm : integer := hmi_axi2ahb + CFG_HPS2FPGA;
constant hsi_ahbrom : integer := 0;
constant hsi_apbctrl : integer := hsi_ahbrom + CFG_AHBROMEN;
constant hsi_dsu : integer := hsi_apbctrl + 1;
constant hsi_ddr3 : integer := hsi_dsu + CFG_DSU;
constant hsi_ahb2axi : integer := hsi_ddr3 + 1;
constant hsi_ahbrep : integer := hsi_ahb2axi + CFG_FPGA2HPS;
constant nahbs : integer := hsi_ahbrep + USE_AHBREP;
constant pi_apbuart : integer := 0;
constant pi_irqmp : integer := pi_apbuart + CFG_UART1_ENABLE;
constant pi_gpt : integer := pi_irqmp + CFG_IRQ3_ENABLE;
constant pi_ahbuart : integer := pi_gpt + CFG_GPT_ENABLE;
constant napbs : integer := pi_ahbuart + CFG_AHB_UART;
signal clklock: std_ulogic;
signal clkm: std_ulogic;
signal ssclk: std_ulogic;
signal rstn: std_ulogic;
signal rstraw: std_ulogic;
signal ahbmi: ahb_mst_in_type;
signal ahbmo: ahb_mst_out_vector;
signal ahbsi: ahb_slv_in_type;
signal ahbso: ahb_slv_out_vector;
signal apbi: apb_slv_in_type;
signal apbo: apb_slv_out_vector;
signal irqi: irq_in_vector(CFG_NCPU-1 downto 0);
signal irqo: irq_out_vector(CFG_NCPU-1 downto 0);
signal dbgi: l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo: l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui: dsu_in_type;
signal dsuo: dsu_out_type;
signal gpti: gptimer_in_type;
signal sri: memory_in_type;
signal sro: memory_out_type;
signal del_addr: std_logic_vector(26 downto 1);
signal del_ce: std_logic;
signal del_bwe, del_bwa, del_bwb: std_logic_vector(1 downto 0);
signal dui, ui: uart_in_type;
signal duo, uo: uart_out_type;
signal vcc, gnd: std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
-----------------------------------------------------------------------------
-- HPS signals and component
-----------------------------------------------------------------------------
constant idsize : integer := 8;
constant lensize : integer := 4;
constant periph_addrsize : integer := 28;
type f2h_axi is record
araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
arcache : STD_LOGIC_VECTOR ( 3 downto 0 );
arid : STD_LOGIC_VECTOR ( 11 downto 0 );
arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
arlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
arqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
awqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
arready : STD_LOGIC;
arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
arvalid : STD_LOGIC;
awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
awcache : STD_LOGIC_VECTOR ( 3 downto 0 );
awid : STD_LOGIC_VECTOR ( 11 downto 0 );
awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
awlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
awready : STD_LOGIC;
awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
awvalid : STD_LOGIC;
bid : STD_LOGIC_VECTOR ( 11 downto 0 );
bready : STD_LOGIC;
bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
bvalid : STD_LOGIC;
rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
rid : STD_LOGIC_VECTOR ( 11 downto 0 );
rlast : STD_LOGIC;
rready : STD_LOGIC;
rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
rvalid : STD_LOGIC;
wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
wlast : STD_LOGIC;
wready : STD_LOGIC;
wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
wvalid : STD_LOGIC;
wid : STD_LOGIC_VECTOR ( 11 downto 0 ); --
end record;
signal h2f, f2h : f2h_axi;
component hps is
port (
clk_clk : in std_logic := 'X'; -- clk
hps_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_hps_io_qspi_inst_IO0 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO0
hps_hps_io_qspi_inst_IO1 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO1
hps_hps_io_qspi_inst_IO2 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO2
hps_hps_io_qspi_inst_IO3 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO3
hps_hps_io_qspi_inst_SS0 : out std_logic; -- hps_io_qspi_inst_SS0
hps_hps_io_qspi_inst_CLK : out std_logic; -- hps_io_qspi_inst_CLK
hps_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_hps_io_spim0_inst_CLK : out std_logic; -- hps_io_spim0_inst_CLK
hps_hps_io_spim0_inst_MOSI : out std_logic; -- hps_io_spim0_inst_MOSI
hps_hps_io_spim0_inst_MISO : in std_logic := 'X'; -- hps_io_spim0_inst_MISO
hps_hps_io_spim0_inst_SS0 : out std_logic; -- hps_io_spim0_inst_SS0
hps_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_hps_io_gpio_inst_GPIO00 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO00
hps_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40
hps_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO48
hps_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_hps_io_gpio_inst_GPIO55 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO55
hps_hps_io_gpio_inst_GPIO56 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO56
hps_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
hps_hps_io_gpio_inst_GPIO62 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO62
hps_ddr_mem_a : out std_logic_vector(14 downto 0); -- mem_a
hps_ddr_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
hps_ddr_mem_ck : out std_logic; -- mem_ck
hps_ddr_mem_ck_n : out std_logic; -- mem_ck_n
hps_ddr_mem_cke : out std_logic; -- mem_cke
hps_ddr_mem_cs_n : out std_logic; -- mem_cs_n
hps_ddr_mem_ras_n : out std_logic; -- mem_ras_n
hps_ddr_mem_cas_n : out std_logic; -- mem_cas_n
hps_ddr_mem_we_n : out std_logic; -- mem_we_n
hps_ddr_mem_reset_n : out std_logic; -- mem_reset_n
hps_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
hps_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
hps_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
hps_ddr_mem_odt : out std_logic; -- mem_odt
hps_ddr_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
hps_ddr_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
hps_f2h_axi_slave_awid : in std_logic_vector(7 downto 0) := (others => 'X'); -- awid
hps_f2h_axi_slave_awaddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- awaddr
hps_f2h_axi_slave_awlen : in std_logic_vector(3 downto 0) := (others => 'X'); -- awlen
hps_f2h_axi_slave_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize
hps_f2h_axi_slave_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst
hps_f2h_axi_slave_awlock : in std_logic_vector(1 downto 0) := (others => 'X'); -- awlock
hps_f2h_axi_slave_awcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- awcache
hps_f2h_axi_slave_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
hps_f2h_axi_slave_awvalid : in std_logic := 'X'; -- awvalid
hps_f2h_axi_slave_awready : out std_logic; -- awready
hps_f2h_axi_slave_awuser : in std_logic_vector(4 downto 0) := (others => 'X'); -- awuser
hps_f2h_axi_slave_wid : in std_logic_vector(7 downto 0) := (others => 'X'); -- wid
hps_f2h_axi_slave_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata
hps_f2h_axi_slave_wstrb : in std_logic_vector(3 downto 0) := (others => 'X'); -- wstrb
hps_f2h_axi_slave_wlast : in std_logic := 'X'; -- wlast
hps_f2h_axi_slave_wvalid : in std_logic := 'X'; -- wvalid
hps_f2h_axi_slave_wready : out std_logic; -- wready
hps_f2h_axi_slave_bid : out std_logic_vector(7 downto 0); -- bid
hps_f2h_axi_slave_bresp : out std_logic_vector(1 downto 0); -- bresp
hps_f2h_axi_slave_bvalid : out std_logic; -- bvalid
hps_f2h_axi_slave_bready : in std_logic := 'X'; -- bready
hps_f2h_axi_slave_arid : in std_logic_vector(7 downto 0) := (others => 'X'); -- arid
hps_f2h_axi_slave_araddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- araddr
hps_f2h_axi_slave_arlen : in std_logic_vector(3 downto 0) := (others => 'X'); -- arlen
hps_f2h_axi_slave_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize
hps_f2h_axi_slave_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst
hps_f2h_axi_slave_arlock : in std_logic_vector(1 downto 0) := (others => 'X'); -- arlock
hps_f2h_axi_slave_arcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- arcache
hps_f2h_axi_slave_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
hps_f2h_axi_slave_arvalid : in std_logic := 'X'; -- arvalid
hps_f2h_axi_slave_arready : out std_logic; -- arready
hps_f2h_axi_slave_aruser : in std_logic_vector(4 downto 0) := (others => 'X'); -- aruser
hps_f2h_axi_slave_rid : out std_logic_vector(7 downto 0); -- rid
hps_f2h_axi_slave_rdata : out std_logic_vector(31 downto 0); -- rdata
hps_f2h_axi_slave_rresp : out std_logic_vector(1 downto 0); -- rresp
hps_f2h_axi_slave_rlast : out std_logic; -- rlast
hps_f2h_axi_slave_rvalid : out std_logic; -- rvalid
hps_f2h_axi_slave_rready : in std_logic := 'X'; -- rready
hps_f2h_irq0_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
hps_f2h_irq1_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
hps_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(27 downto 0) := (others => 'X'); -- stm_hwevents
hps_h2f_lw_axi_master_awid : out std_logic_vector(11 downto 0); -- awid
hps_h2f_lw_axi_master_awaddr : out std_logic_vector(20 downto 0); -- awaddr
hps_h2f_lw_axi_master_awlen : out std_logic_vector(3 downto 0); -- awlen
hps_h2f_lw_axi_master_awsize : out std_logic_vector(2 downto 0); -- awsize
hps_h2f_lw_axi_master_awburst : out std_logic_vector(1 downto 0); -- awburst
hps_h2f_lw_axi_master_awlock : out std_logic_vector(1 downto 0); -- awlock
hps_h2f_lw_axi_master_awcache : out std_logic_vector(3 downto 0); -- awcache
hps_h2f_lw_axi_master_awprot : out std_logic_vector(2 downto 0); -- awprot
hps_h2f_lw_axi_master_awvalid : out std_logic; -- awvalid
hps_h2f_lw_axi_master_awready : in std_logic := 'X'; -- awready
hps_h2f_lw_axi_master_wid : out std_logic_vector(11 downto 0); -- wid
hps_h2f_lw_axi_master_wdata : out std_logic_vector(31 downto 0); -- wdata
hps_h2f_lw_axi_master_wstrb : out std_logic_vector(3 downto 0); -- wstrb
hps_h2f_lw_axi_master_wlast : out std_logic; -- wlast
hps_h2f_lw_axi_master_wvalid : out std_logic; -- wvalid
hps_h2f_lw_axi_master_wready : in std_logic := 'X'; -- wready
hps_h2f_lw_axi_master_bid : in std_logic_vector(11 downto 0) := (others => 'X'); -- bid
hps_h2f_lw_axi_master_bresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp
hps_h2f_lw_axi_master_bvalid : in std_logic := 'X'; -- bvalid
hps_h2f_lw_axi_master_bready : out std_logic; -- bready
hps_h2f_lw_axi_master_arid : out std_logic_vector(11 downto 0); -- arid
hps_h2f_lw_axi_master_araddr : out std_logic_vector(20 downto 0); -- araddr
hps_h2f_lw_axi_master_arlen : out std_logic_vector(3 downto 0); -- arlen
hps_h2f_lw_axi_master_arsize : out std_logic_vector(2 downto 0); -- arsize
hps_h2f_lw_axi_master_arburst : out std_logic_vector(1 downto 0); -- arburst
hps_h2f_lw_axi_master_arlock : out std_logic_vector(1 downto 0); -- arlock
hps_h2f_lw_axi_master_arcache : out std_logic_vector(3 downto 0); -- arcache
hps_h2f_lw_axi_master_arprot : out std_logic_vector(2 downto 0); -- arprot
hps_h2f_lw_axi_master_arvalid : out std_logic; -- arvalid
hps_h2f_lw_axi_master_arready : in std_logic := 'X'; -- arready
hps_h2f_lw_axi_master_rid : in std_logic_vector(11 downto 0) := (others => 'X'); -- rid
hps_h2f_lw_axi_master_rdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- rdata
hps_h2f_lw_axi_master_rresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp
hps_h2f_lw_axi_master_rlast : in std_logic := 'X'; -- rlast
hps_h2f_lw_axi_master_rvalid : in std_logic := 'X'; -- rvalid
hps_h2f_lw_axi_master_rready : out std_logic; -- rready
hps_h2f_reset_reset_n : out std_logic; -- reset_n
reset_reset_n : in std_logic := 'X'; -- reset_n
hps_h2f_axi_master_awid : out std_logic_vector(11 downto 0); -- awid
hps_h2f_axi_master_awaddr : out std_logic_vector(29 downto 0); -- awaddr
hps_h2f_axi_master_awlen : out std_logic_vector(3 downto 0); -- awlen
hps_h2f_axi_master_awsize : out std_logic_vector(2 downto 0); -- awsize
hps_h2f_axi_master_awburst : out std_logic_vector(1 downto 0); -- awburst
hps_h2f_axi_master_awlock : out std_logic_vector(1 downto 0); -- awlock
hps_h2f_axi_master_awcache : out std_logic_vector(3 downto 0); -- awcache
hps_h2f_axi_master_awprot : out std_logic_vector(2 downto 0); -- awprot
hps_h2f_axi_master_awvalid : out std_logic; -- awvalid
hps_h2f_axi_master_awready : in std_logic := 'X'; -- awready
hps_h2f_axi_master_wid : out std_logic_vector(11 downto 0); -- wid
hps_h2f_axi_master_wdata : out std_logic_vector(31 downto 0); -- wdata
hps_h2f_axi_master_wstrb : out std_logic_vector(3 downto 0); -- wstrb
hps_h2f_axi_master_wlast : out std_logic; -- wlast
hps_h2f_axi_master_wvalid : out std_logic; -- wvalid
hps_h2f_axi_master_wready : in std_logic := 'X'; -- wready
hps_h2f_axi_master_bid : in std_logic_vector(11 downto 0) := (others => 'X'); -- bid
hps_h2f_axi_master_bresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp
hps_h2f_axi_master_bvalid : in std_logic := 'X'; -- bvalid
hps_h2f_axi_master_bready : out std_logic; -- bready
hps_h2f_axi_master_arid : out std_logic_vector(11 downto 0); -- arid
hps_h2f_axi_master_araddr : out std_logic_vector(29 downto 0); -- araddr
hps_h2f_axi_master_arlen : out std_logic_vector(3 downto 0); -- arlen
hps_h2f_axi_master_arsize : out std_logic_vector(2 downto 0); -- arsize
hps_h2f_axi_master_arburst : out std_logic_vector(1 downto 0); -- arburst
hps_h2f_axi_master_arlock : out std_logic_vector(1 downto 0); -- arlock
hps_h2f_axi_master_arcache : out std_logic_vector(3 downto 0); -- arcache
hps_h2f_axi_master_arprot : out std_logic_vector(2 downto 0); -- arprot
hps_h2f_axi_master_arvalid : out std_logic; -- arvalid
hps_h2f_axi_master_arready : in std_logic := 'X'; -- arready
hps_h2f_axi_master_rid : in std_logic_vector(11 downto 0) := (others => 'X'); -- rid
hps_h2f_axi_master_rdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- rdata
hps_h2f_axi_master_rresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp
hps_h2f_axi_master_rlast : in std_logic := 'X'; -- rlast
hps_h2f_axi_master_rvalid : in std_logic := 'X'; -- rvalid
hps_h2f_axi_master_rready : out std_logic -- rready
);
end component hps;
--
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal hpsrst : std_logic;
signal sys_rst_n : std_logic;
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- Clocking and reset
-----------------------------------------------------------------------------
LED(1) <= not clklock;
rstgen0: if CFG_HPS_RESET = 1 generate
sys_rst_n <= RESET_n and hpsrst;
end generate;
nohps: if CFG_HPS_RESET /= 1 generate
sys_rst_n <= RESET_n;
end generate;
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clklock <= cgo.clklock;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => altera, clk_mul => 7,
clk_div => 5, sdramen => 0,
noclkfb => 0, freq => 50000)
port map (clkin => OSC_50_B3B, pciclkin => gnd, clk => clkm, clkn => open,
clk2x => open, sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo);
rstgen1: rstgen
generic map (syncrst => CFG_NOASYNC)
port map (sys_rst_n, clkm, clklock, rstn, rstraw);
-----------------------------------------------------------------------------
-- AMBA bus fabric
-----------------------------------------------------------------------------
ahbctrl0: ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN,ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
enbusmon => CFG_AHB_MON, assertwarn => CFG_AHB_MONWAR,
asserterr => CFG_AHB_MONERR, ahbtrace => CFG_AHB_DTRACE,
nahbm => nahbm, nahbs => nahbs)
port map (rstn,clkm,ahbmi,ahbmo,ahbsi,ahbso);
apbctrl0: apbctrl
generic map (hindex => hsi_apbctrl, haddr => CFG_APBADDR, nslaves => napbs)
port map (rstn,clkm,ahbsi,ahbso(hsi_apbctrl),apbi,apbo);
ahbmo(ahbmo'high downto nahbm) <= (others => ahbm_none);
ahbso(ahbso'high downto nahbs) <= (others => ahbs_none);
apbo(napbs to apbo'high) <= (others => apb_none);
-----------------------------------------------------------------------------
-- LEON3 Processor(s), DSU
-----------------------------------------------------------------------------
errorn_pad : outpad generic map (tech => padtech) port map (LED(3), dbgo(0).error);
dsubre_pad : inpad generic map (tech => padtech) port map (KEY(3), dsui.break);
LED(2) <= not dsuo.active;
dsui.enable <= '1';
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => hsi_dsu, haddr => 16#D00#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(hsi_dsu), dbgo, dbgi, dsui, dsuo);
end generate;
end generate;
noleon: if CFG_LEON3 = 0 generate
irqo <= (others => ('0',"0000",'0','0','0'));
dbgo <= (others => dbgo_none);
end generate;
nodsu : if CFG_DSU = 0 or CFG_LEON3 = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; dsuo.pwd <= (others => '0');
end generate;
-----------------------------------------------------------------------------
-- APB Slaves
-----------------------------------------------------------------------------
ua0 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart
generic map (pindex => pi_apbuart, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(pi_apbuart), ui, uo);
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => pi_irqmp, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(pi_irqmp), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
irqi(i).rst <= '1';
irqi(i).run <= '1';
irqi(i).rstvec <= (others => '0');
irqi(i).iact <= '0';
irqi(i).index <= (others => '0');
irqi(i).hrdrst <= '1';
end generate;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => pi_gpt, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(pi_gpt), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; gpti.wdogen <= '0';
end generate;
-----------------------------------------------------------------------------
-- Debug links
-----------------------------------------------------------------------------
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => hmi_ahbuart, pindex => pi_ahbuart, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(pi_ahbuart), ahbmi, ahbmo(hmi_ahbuart));
end generate;
nouah : if CFG_AHB_UART = 0 generate
duo.rtsn <= '0'; duo.txd <= '0';
duo.scaler <= (others => '0'); duo.txen <= '0';
duo.flow <= '0'; duo.rxen <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => hmi_ahbjtag, nsync => 2, versel => 0)
port map(rstn, clkm, gnd, gnd, gnd, open, ahbmi, ahbmo(hmi_ahbjtag),
open, open, open, open, open, open, open, gnd);
end generate;
-----------------------------------------------------------------------------
-- Memory controllers
-----------------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => hsi_ahbrom, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(hsi_ahbrom));
end generate;
ddr3if0: entity work.ddr3if
generic map (
hindex => hsi_ddr3,
haddr => 16#400#, hmask => 16#C00#
) port map (
pll_ref_clk => OSC_50_B5B,
global_reset_n => RESET_n,
mem_a => DDR3_A,
mem_ba => DDR3_BA,
mem_ck => DDR3_CK_p,
mem_ck_n => DDR_CK_n,
mem_cke => DDR3_CKE,
mem_reset_n => DDR3_RESET_n,
mem_cs_n => DDR3_CS_n,
mem_dm => DDR3_DM,
mem_ras_n => DDR3_RAS_n,
mem_cas_n => DDR3_CAS_n,
mem_we_n => DDR3_WE_n,
mem_dq => DDR3_DQ,
mem_dqs => DDR3_DQS_p,
mem_dqs_n => DDR3_DQS_n,
mem_odt => DDR3_ODT,
oct_rzqin => DDR3_RZQ,
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(hsi_ddr3)
);
-----------------------------------------------------------------------------
-- Hard Processor System
-----------------------------------------------------------------------------
-- FPGA2HPS Bridge
fpga2hps: if CFG_FPGA2HPS = 1 generate
ahb2axi0 : entity work.ahb2axi
generic map(
hindex => hsi_ahb2axi, haddr => 16#CF0#, hmask => 16#FF0#,
idsize => idsize, lensize => lensize, addrsize => periph_addrsize)
port map(
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(hsi_ahb2axi),
M_AXI_araddr => f2h.araddr(periph_addrsize-1 downto 0),
M_AXI_arburst(1 downto 0) => f2h.arburst(1 downto 0),
M_AXI_arcache(3 downto 0) => f2h.arcache(3 downto 0),
M_AXI_arid => f2h.arid(7 downto 0),
M_AXI_arlen => f2h.arlen,
M_AXI_arlock => f2h.arlock,
M_AXI_arprot(2 downto 0) => f2h.arprot(2 downto 0),
M_AXI_arqos => f2h.arqos,
M_AXI_arready => f2h.arready,
M_AXI_arsize(2 downto 0) => f2h.arsize(2 downto 0),
M_AXI_arvalid => f2h.arvalid,
M_AXI_awaddr => f2h.awaddr(periph_addrsize-1 downto 0),
M_AXI_awburst(1 downto 0) => f2h.awburst(1 downto 0),
M_AXI_awcache(3 downto 0) => f2h.awcache(3 downto 0),
M_AXI_awid => f2h.awid(7 downto 0),
M_AXI_awlen => f2h.awlen,
M_AXI_awlock => f2h.awlock,
M_AXI_awprot(2 downto 0) => f2h.awprot(2 downto 0),
M_AXI_awqos => f2h.awqos,
M_AXI_awready => f2h.awready,
M_AXI_awsize(2 downto 0) => f2h.awsize(2 downto 0),
M_AXI_awvalid => f2h.awvalid,
M_AXI_bid => f2h.bid(7 downto 0),
M_AXI_bready => f2h.bready,
M_AXI_bresp(1 downto 0) => f2h.bresp(1 downto 0),
M_AXI_bvalid => f2h.bvalid,
M_AXI_rdata(31 downto 0) => f2h.rdata(31 downto 0),
M_AXI_rid => f2h.rid(7 downto 0),
M_AXI_rlast => f2h.rlast,
M_AXI_rready => f2h.rready,
M_AXI_rresp(1 downto 0) => f2h.rresp(1 downto 0),
M_AXI_rvalid => f2h.rvalid,
M_AXI_wdata(31 downto 0) => f2h.wdata(31 downto 0),
M_AXI_wlast => f2h.wlast,
M_AXI_wready => f2h.wready,
M_AXI_wstrb(3 downto 0) => f2h.wstrb(3 downto 0),
M_AXI_wvalid => f2h.wvalid
);
f2h.araddr(31 downto periph_addrsize) <= (others => '1');
f2h.awaddr(31 downto periph_addrsize) <= (others => '1');
end generate;
--HPS2FPGA bridge
hps2fpga: if CFG_HPS2FPGA = 1 generate
axi2ahb : entity work.axi2ahb
generic map(
hindex => hmi_axi2ahb,
idsize => 12,
lensize => lensize,
fifo_depth => 16
)
port map(
ahb_clk => clkm,
axi_clk => clkm,
resetn => rstn,
ahbi => ahbmi,
ahbo => ahbmo(hmi_axi2ahb),
s_axi_araddr => h2f.araddr,
s_axi_arburst => h2f.arburst,
s_axi_arcache => h2f.arcache,
s_axi_arid => h2f.arid(11 downto 0),
s_axi_arlen => h2f.arlen,
s_axi_arlock => h2f.arlock,
s_axi_arprot => h2f.arprot,
s_axi_arqos => h2f.arqos,
s_axi_arready => h2f.arready,
s_axi_arsize => h2f.arsize,
s_axi_arvalid => h2f.arvalid,
s_axi_awaddr => h2f.awaddr,
s_axi_awburst => h2f.awburst,
s_axi_awcache => h2f.awcache,
s_axi_awid => h2f.awid(11 downto 0),
s_axi_awlen => h2f.awlen,
s_axi_awlock => h2f.awlock,
s_axi_awprot => h2f.awprot,
s_axi_awqos => h2f.awqos,
s_axi_awready => h2f.awready,
s_axi_awsize => h2f.awsize,
s_axi_awvalid => h2f.awvalid,
s_axi_bid => h2f.bid(11 downto 0),
s_axi_bready => h2f.bready,
s_axi_bresp => h2f.bresp,
s_axi_bvalid => h2f.bvalid,
s_axi_rdata => h2f.rdata(31 downto 0),
s_axi_rid => h2f.rid(11 downto 0),
s_axi_rlast => h2f.rlast,
s_axi_rready => h2f.rready,
s_axi_rresp => h2f.rresp,
s_axi_rvalid => h2f.rvalid,
s_axi_wdata => h2f.wdata(31 downto 0),
s_axi_wid => h2f.wid(11 downto 0),
s_axi_wlast => h2f.wlast,
s_axi_wready => h2f.wready,
s_axi_wstrb => h2f.wstrb(3 downto 0),
s_axi_wvalid => h2f.wvalid
);
h2f.araddr(31 downto 30) <= "10";
h2f.awaddr(31 downto 30) <= "10";
end generate;
hps_inst : component hps
port map (
clk_clk => clkm,
hps_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK,
hps_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0),
hps_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1),
hps_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2),
hps_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3),
hps_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0),
hps_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO,
hps_hps_io_emac1_inst_MDC => HPS_ENET_MDC,
hps_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV,
hps_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN,
hps_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK,
hps_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1),
hps_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2),
hps_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3),
hps_hps_io_qspi_inst_IO0 => HPS_FLASH_DATA(0),
hps_hps_io_qspi_inst_IO1 => HPS_FLASH_DATA(1),
hps_hps_io_qspi_inst_IO2 => HPS_FLASH_DATA(2),
hps_hps_io_qspi_inst_IO3 => HPS_FLASH_DATA(3),
hps_hps_io_qspi_inst_SS0 => HPS_FLASH_NCSO,
hps_hps_io_qspi_inst_CLK => HPS_FLASH_DCLK,
hps_hps_io_sdio_inst_CMD => HPS_SD_CMD,
hps_hps_io_sdio_inst_D0 => HPS_SD_DATA(0),
hps_hps_io_sdio_inst_D1 => HPS_SD_DATA(1),
hps_hps_io_sdio_inst_CLK => HPS_SD_CLK,
hps_hps_io_sdio_inst_D2 => HPS_SD_DATA(2),
hps_hps_io_sdio_inst_D3 => HPS_SD_DATA(3),
hps_hps_io_usb1_inst_D0 => HPS_USB_DATA(0),
hps_hps_io_usb1_inst_D1 => HPS_USB_DATA(1),
hps_hps_io_usb1_inst_D2 => HPS_USB_DATA(2),
hps_hps_io_usb1_inst_D3 => HPS_USB_DATA(3),
hps_hps_io_usb1_inst_D4 => HPS_USB_DATA(4),
hps_hps_io_usb1_inst_D5 => HPS_USB_DATA(5),
hps_hps_io_usb1_inst_D6 => HPS_USB_DATA(6),
hps_hps_io_usb1_inst_D7 => HPS_USB_DATA(7),
hps_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT,
hps_hps_io_usb1_inst_STP => HPS_USB_STP,
hps_hps_io_usb1_inst_DIR => HPS_USB_DIR,
hps_hps_io_usb1_inst_NXT => HPS_USB_NXT,
hps_hps_io_spim0_inst_CLK => HPS_SPIM_CLK,
hps_hps_io_spim0_inst_MOSI => HPS_SPIM_MOSI,
hps_hps_io_spim0_inst_MISO => HPS_SPIM_MISO,
hps_hps_io_spim0_inst_SS0 => HPS_SPIM_SS,
hps_hps_io_spim1_inst_CLK => HPS_LCM_SPIM_CLK,
hps_hps_io_spim1_inst_MOSI => HPS_LCM_SPIM_MOSI,
hps_hps_io_spim1_inst_MISO => HPS_LCM_SPIM_MISO,
hps_hps_io_spim1_inst_SS0 => HPS_LCM_SPIM_SS,
hps_hps_io_uart0_inst_RX => HPS_UART_RX,
hps_hps_io_uart0_inst_TX => HPS_UART_TX,
hps_hps_io_i2c1_inst_SDA => HPS_I2C_SDA,
hps_hps_io_i2c1_inst_SCL => HPS_I2C_CLK,
hps_hps_io_gpio_inst_GPIO00 => HPS_LTC_GPIO,
hps_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_n,
hps_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_n,
hps_hps_io_gpio_inst_GPIO40 => HPS_LCM_BK,
hps_hps_io_gpio_inst_GPIO48 => HPS_LCM_RST_N,
hps_hps_io_gpio_inst_GPIO53 => HPS_LED(0),
hps_hps_io_gpio_inst_GPIO54 => HPS_LED(1),
hps_hps_io_gpio_inst_GPIO55 => HPS_LED(2),
hps_hps_io_gpio_inst_GPIO56 => HPS_LED(3),
hps_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT,
hps_hps_io_gpio_inst_GPIO62 => HPS_LCM_D_C,
hps_ddr_mem_a => HPS_DDR3_A,
hps_ddr_mem_ba => HPS_DDR3_BA,
hps_ddr_mem_ck => HPS_DDR3_CK_p,
hps_ddr_mem_ck_n => HPS_DDR3_CK_n,
hps_ddr_mem_cke => HPS_DDR3_CKE,
hps_ddr_mem_cs_n => HPS_DDR3_CS_n,
hps_ddr_mem_ras_n => HPS_DDR3_RAS_n,
hps_ddr_mem_cas_n => HPS_DDR3_CAS_n,
hps_ddr_mem_we_n => HPS_DDR3_WE_n,
hps_ddr_mem_reset_n => HPS_DDR3_RESET_n,
hps_ddr_mem_dq => HPS_DDR3_DQ,
hps_ddr_mem_dqs => HPS_DDR3_DQS_p,
hps_ddr_mem_dqs_n => HPS_DDR3_DQS_n,
hps_ddr_mem_odt => HPS_DDR3_ODT,
hps_ddr_mem_dm => HPS_DDR3_DM,
hps_ddr_oct_rzqin => HPS_DDR3_RZQ,
hps_f2h_irq0_irq => (others => 'X'),
hps_f2h_irq1_irq => (others => 'X'),
hps_f2h_stm_hw_events_stm_hwevents => (others => 'X'),
hps_h2f_axi_master_awid => h2f.awid(11 downto 0),--er.awid
hps_h2f_axi_master_awaddr => h2f.awaddr(29 downto 0),--.awaddr
hps_h2f_axi_master_awlen => h2f.awlen,-- .awlen
hps_h2f_axi_master_awsize => h2f.awsize,--.awsize
hps_h2f_axi_master_awburst => h2f.awburst,--awburst
hps_h2f_axi_master_awlock => h2f.awlock,--.awlock
hps_h2f_axi_master_awcache => h2f.awcache,--awcache
hps_h2f_axi_master_awprot => h2f.awprot,--.awprot
hps_h2f_axi_master_awvalid => h2f.awvalid,--awvalid
hps_h2f_axi_master_awready => h2f.wready,--wready
hps_h2f_axi_master_wid => h2f.wid(11 downto 0),-- .wid
hps_h2f_axi_master_wdata => h2f.wdata(31 downto 0),-- .wdata
hps_h2f_axi_master_wstrb => h2f.wstrb(3 downto 0),-- .wstrb
hps_h2f_axi_master_wlast => h2f.wlast,-- .wlast
hps_h2f_axi_master_wvalid => h2f.wvalid,--.wvalid
hps_h2f_axi_master_wready => h2f.wready,--wready
hps_h2f_axi_master_bid => h2f.bid(11 downto 0),-- .bid
hps_h2f_axi_master_bresp => h2f.bresp,-- .bresp
hps_h2f_axi_master_bvalid => h2f.bvalid,--bvalid
hps_h2f_axi_master_bready => h2f.bready,--.bready
hps_h2f_axi_master_arid => h2f.arid(11 downto 0),-- .arid
hps_h2f_axi_master_araddr => h2f.araddr(29 downto 0),--.araddr
hps_h2f_axi_master_arlen => h2f.arlen,-- .arlen
hps_h2f_axi_master_arsize => h2f.arsize,--.arsize
hps_h2f_axi_master_arburst => h2f.arburst,--arburst
hps_h2f_axi_master_arlock => h2f.arlock,-- .arlock
hps_h2f_axi_master_arcache => h2f.arcache,--arcache
hps_h2f_axi_master_arprot => h2f.arprot,--.arprot
hps_h2f_axi_master_arvalid => h2f.arvalid,--arvalid
hps_h2f_axi_master_arready => h2f.rready,--rready
hps_h2f_axi_master_rid => h2f.rid(11 downto 0),-- .rid
hps_h2f_axi_master_rdata => h2f.rdata(31 downto 0),-- .rdata
hps_h2f_axi_master_rresp => h2f.rresp,-- .rresp
hps_h2f_axi_master_rlast => h2f.rlast,--.rlast
hps_h2f_axi_master_rvalid => h2f.rvalid,--rvalid
hps_h2f_axi_master_rready => h2f.rready, --rready
hps_h2f_lw_axi_master_awid => open,
hps_h2f_lw_axi_master_awaddr => open,
hps_h2f_lw_axi_master_awlen => open,
hps_h2f_lw_axi_master_awsize => open,
hps_h2f_lw_axi_master_awburst => open,
hps_h2f_lw_axi_master_awlock => open,
hps_h2f_lw_axi_master_awcache => open,
hps_h2f_lw_axi_master_awprot => open,
hps_h2f_lw_axi_master_awvalid => open,
hps_h2f_lw_axi_master_awready => '0',
hps_h2f_lw_axi_master_wid => open,
hps_h2f_lw_axi_master_wdata => open,
hps_h2f_lw_axi_master_wstrb => open,
hps_h2f_lw_axi_master_wlast => open,
hps_h2f_lw_axi_master_wvalid => open,
hps_h2f_lw_axi_master_wready => '0',
hps_h2f_lw_axi_master_bid => (others => '0'),
hps_h2f_lw_axi_master_bresp => (others => '0'),
hps_h2f_lw_axi_master_bvalid => '0',
hps_h2f_lw_axi_master_bready => open,
hps_h2f_lw_axi_master_arid => open,
hps_h2f_lw_axi_master_araddr => open,
hps_h2f_lw_axi_master_arlen => open,
hps_h2f_lw_axi_master_arsize => open,
hps_h2f_lw_axi_master_arburst => open,
hps_h2f_lw_axi_master_arlock => open,
hps_h2f_lw_axi_master_arcache => open,
hps_h2f_lw_axi_master_arprot => open,
hps_h2f_lw_axi_master_arvalid => open,
hps_h2f_lw_axi_master_arready => '0',
hps_h2f_lw_axi_master_rid => (others => '0'),
hps_h2f_lw_axi_master_rdata => (others => '0'),
hps_h2f_lw_axi_master_rresp => (others => '0'),
hps_h2f_lw_axi_master_rlast => '0',
hps_h2f_lw_axi_master_rvalid => '0',
hps_h2f_lw_axi_master_rready => open,
hps_h2f_reset_reset_n => hpsrst,
reset_reset_n => rstn,
hps_f2h_axi_slave_awid => f2h.awid(7 downto 0),--er.awid
hps_f2h_axi_slave_awaddr => f2h.awaddr(31 downto 0),--.awaddr
hps_f2h_axi_slave_awlen => f2h.awlen,-- .awlen
hps_f2h_axi_slave_awsize => f2h.awsize,--.awsize
hps_f2h_axi_slave_awburst => f2h.awburst,--awburst
hps_f2h_axi_slave_awlock => f2h.awlock,--.awlock
hps_f2h_axi_slave_awcache => f2h.awcache,--awcache
hps_f2h_axi_slave_awprot => f2h.awprot,--.awprot
hps_f2h_axi_slave_awvalid => f2h.awvalid,--awvalid
hps_f2h_axi_slave_awready => f2h.awready,--wready
hps_f2h_axi_slave_wid => f2h.wid(7 downto 0),-- .wid
hps_f2h_axi_slave_wdata => f2h.wdata,-- .wdata
hps_f2h_axi_slave_wstrb => f2h.wstrb,-- .wstrb
hps_f2h_axi_slave_wlast => f2h.wlast,-- .wlast
hps_f2h_axi_slave_wvalid => f2h.wvalid,--.wvalid
hps_f2h_axi_slave_wready => f2h.wready,--wready
hps_f2h_axi_slave_bid => f2h.bid(7 downto 0),-- .bid
hps_f2h_axi_slave_bresp => f2h.bresp,-- .bresp
hps_f2h_axi_slave_bvalid => f2h.bvalid,--bvalid
hps_f2h_axi_slave_bready => f2h.bready,--.bready
hps_f2h_axi_slave_arid => f2h.arid(7 downto 0),-- .arid
hps_f2h_axi_slave_araddr => f2h.araddr(31 downto 0),--.araddr
hps_f2h_axi_slave_arlen => f2h.arlen,-- .arlen
hps_f2h_axi_slave_arsize => f2h.arsize,--.arsize
hps_f2h_axi_slave_arburst => f2h.arburst,--arburst
hps_f2h_axi_slave_arlock => f2h.arlock,-- .arlock
hps_f2h_axi_slave_arcache => f2h.arcache,--arcache
hps_f2h_axi_slave_arprot => f2h.arprot,--.arprot
hps_f2h_axi_slave_arvalid => f2h.arvalid,--arvalid
hps_f2h_axi_slave_arready => f2h.arready,--rready
hps_f2h_axi_slave_rid => f2h.rid(7 downto 0),-- .rid
hps_f2h_axi_slave_rdata => f2h.rdata,-- .rdata
hps_f2h_axi_slave_rresp => f2h.rresp,-- .rresp
hps_f2h_axi_slave_rlast => f2h.rlast,--.rlast
hps_f2h_axi_slave_rvalid => f2h.rvalid,--rvalid
hps_f2h_axi_slave_rready => f2h.rready --rready
);
-----------------------------------------------------------------------------
-- Other
-----------------------------------------------------------------------------
-- pragma translate_off
rep: if USE_AHBREP/=0 generate
ahbrep0: ahbrep
generic map (hindex => hsi_ahbrep, haddr => 16#200#)
port map (rstn,clkm,ahbsi,ahbso(hsi_ahbrep));
end generate;
x : report_version
generic map (
msg1 => "LEON3 Altera Cyclone V SX SoC Terasic Sockit Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-------------------------------------------------------------------------------
--
-- T421 system toplevel.
--
-- $Id: t421-c.vhd,v 1.1 2006-06-11 13:47:24 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
configuration t421_struct_c0 of t421 is
for struct
for t420_notri_b: t420_notri
use configuration work.t420_notri_struct_c0;
end for;
end for;
end t421_struct_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1939.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01939ent IS
END c07s02b01x00p01n04i01939ent;
ARCHITECTURE c07s02b01x00p01n04i01939arch OF c07s02b01x00p01n04i01939ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a nand b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01939 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01939arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1939.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01939ent IS
END c07s02b01x00p01n04i01939ent;
ARCHITECTURE c07s02b01x00p01n04i01939arch OF c07s02b01x00p01n04i01939ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a nand b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01939 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01939arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1939.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01939ent IS
END c07s02b01x00p01n04i01939ent;
ARCHITECTURE c07s02b01x00p01n04i01939arch OF c07s02b01x00p01n04i01939ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a nand b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01939 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01939arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sbox_inv is
port (
d_in : in std_logic_vector(7 downto 0);
d_out : out std_logic_vector(7 downto 0)
);
end sbox_inv;
architecture behavioral of sbox_inv is
type sbox_lut is array(0 to 255) of std_logic_vector(7 downto 0);
constant lut : sbox_lut := (
x"52", x"09", x"6A", x"D5", x"30", x"36", x"A5", x"38", x"BF", x"40", x"A3", x"9E", x"81", x"F3", x"D7", x"FB",
x"7C", x"E3", x"39", x"82", x"9B", x"2F", x"FF", x"87", x"34", x"8E", x"43", x"44", x"C4", x"DE", x"E9", x"CB",
x"54", x"7B", x"94", x"32", x"A6", x"C2", x"23", x"3D", x"EE", x"4C", x"95", x"0B", x"42", x"FA", x"C3", x"4E",
x"08", x"2E", x"A1", x"66", x"28", x"D9", x"24", x"B2", x"76", x"5B", x"A2", x"49", x"6D", x"8B", x"D1", x"25",
x"72", x"F8", x"F6", x"64", x"86", x"68", x"98", x"16", x"D4", x"A4", x"5C", x"CC", x"5D", x"65", x"B6", x"92",
x"6C", x"70", x"48", x"50", x"FD", x"ED", x"B9", x"DA", x"5E", x"15", x"46", x"57", x"A7", x"8D", x"9D", x"84",
x"90", x"D8", x"AB", x"00", x"8C", x"BC", x"D3", x"0A", x"F7", x"E4", x"58", x"05", x"B8", x"B3", x"45", x"06",
x"D0", x"2C", x"1E", x"8F", x"CA", x"3F", x"0F", x"02", x"C1", x"AF", x"BD", x"03", x"01", x"13", x"8A", x"6B",
x"3A", x"91", x"11", x"41", x"4F", x"67", x"DC", x"EA", x"97", x"F2", x"CF", x"CE", x"F0", x"B4", x"E6", x"73",
x"96", x"AC", x"74", x"22", x"E7", x"AD", x"35", x"85", x"E2", x"F9", x"37", x"E8", x"1C", x"75", x"DF", x"6E",
x"47", x"F1", x"1A", x"71", x"1D", x"29", x"C5", x"89", x"6F", x"B7", x"62", x"0E", x"AA", x"18", x"BE", x"1B",
x"FC", x"56", x"3E", x"4B", x"C6", x"D2", x"79", x"20", x"9A", x"DB", x"C0", x"FE", x"78", x"CD", x"5A", x"F4",
x"1F", x"DD", x"A8", x"33", x"88", x"07", x"C7", x"31", x"B1", x"12", x"10", x"59", x"27", x"80", x"EC", x"5F",
x"60", x"51", x"7F", x"A9", x"19", x"B5", x"4A", x"0D", x"2D", x"E5", x"7A", x"9F", x"93", x"C9", x"9C", x"EF",
x"A0", x"E0", x"3B", x"4D", x"AE", x"2A", x"F5", x"B0", x"C8", x"EB", x"BB", x"3C", x"83", x"53", x"99", x"61",
x"17", x"2B", x"04", x"7E", x"BA", x"77", x"D6", x"26", x"E1", x"69", x"14", x"63", x"55", x"21", x"0C", x"7D"
);
begin
d_out <= lut(conv_integer(d_in(7 downto 0)));
end behavioral;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- cond_init_3.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_cond_t * cond = (hthread_cond_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- retVal = hthread_cond_init( cond, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
when STATE_4 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
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FGe01PaxBpNC8SuzQQ27qB9JiMcOZlOEWJMrc2W7/S4JEtt2UIIslGVwDmLokkXc/rTFIQMRN+dW
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IPgN6QaD3OssxrPIbJTRqmPIQ44iMcYcNhmAqE4I7KKP2GzjIf7nrdYyuerIBMPFQoykX/M3F2Ra
Sl7+q797KEO0Fk61+scqCNgd9t5uHajyuy8JF5TY/eC7YE9/xSQZuzEBxgdtoVQB3FYQgapW0fes
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Gj0853uOUxtcHOWpRb2RTUo0/9h/hzWAeMtl335UFX+aiTGzfGciHPsokDUCDxhpjo6lH/J0YMEI
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DYNKPhXGUgcx4eus5pjGaHUzMGPSGatC4q1NcdKB
`protect end_protected
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_2 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_2;
ARCHITECTURE bram_1024_2_arch OF bram_1024_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_2_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_2_arch : ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_2_arch: ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_2.mi" &
"f,C_INIT_FILE=bram_1024_2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_2.mif",
C_INIT_FILE => "bram_1024_2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_2_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_2 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_2;
ARCHITECTURE bram_1024_2_arch OF bram_1024_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_2_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_2_arch : ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_2_arch: ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_2.mi" &
"f,C_INIT_FILE=bram_1024_2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_2.mif",
C_INIT_FILE => "bram_1024_2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_2_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_2 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_2;
ARCHITECTURE bram_1024_2_arch OF bram_1024_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_2_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_2_arch : ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_2_arch: ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_2.mi" &
"f,C_INIT_FILE=bram_1024_2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_2.mif",
C_INIT_FILE => "bram_1024_2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_2_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_2 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_2;
ARCHITECTURE bram_1024_2_arch OF bram_1024_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_2_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_2_arch : ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_2_arch: ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_2.mi" &
"f,C_INIT_FILE=bram_1024_2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_2.mif",
C_INIT_FILE => "bram_1024_2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_2_arch;
|
entity staticwait is
end entity;
architecture test of staticwait is
signal x : integer;
begin
p1: process (x) is
begin
x <= 0;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
entity JumpRegMux is
port (
JumpReg: in ctrl_t;
reg1data : in addr_t;
JumpDirMux : in addr_t;
output : out addr_t
);
end entity;
architecture behav of JumpRegMux is
begin
output <= reg1data when JumpReg = '1' else JumpDirMux;
printer: process(JumpReg, reg1data, JumpDirMux)
variable output : addr_t;
begin
if JumpReg = '1' then
output := reg1data;
else
output := JumpDirMux;
end if;
printf("pc_new = %s\n", output);
end process;
end architecture behav;
|
context c1;
library ieee;
context c2;
context con1 is
library ieee;
context c3;
end context con1;
|
-- file: clk_dcm_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1 40.960 0.000 50.0 596.692 50.000
-- CLK_OUT2 8.192 0.000 50.0 200.000 50.000
--
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 8.192 0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_dcm_pll is
generic
(
CLK_MULTIPLY : integer := 5
);
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT : out std_logic;
CLK_OUT2 : out std_logic
);
end clk_dcm_pll;
architecture xilinx of clk_dcm_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_dcm_pll,clk_wiz_v3_1,{component_name=clk_dcm_pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=122.0703125,clkin2_period=122.0703125,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out2_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => CLK_MULTIPLY,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 122.0703125,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= clk_out2_internal;
clkout1_buf : BUFG
port map
(O => CLK_OUT,
I => clkfx);
clkout2_buf : BUFG
port map
(O => clk_out2_internal,
I => clk0);
CLK_OUT2 <= clk_out2_internal;
end xilinx;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.01.2014 14:32:21
-- Design Name:
-- Module Name: TB4_FileBasedTest - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TB4_FileBasedTest is
end TB4_FileBasedTest;
architecture Behavioral of TB4_FileBasedTest is
signal clk : std_logic;
constant clk_period : time := 10 ns;
signal errorDetected : std_logic := '0';
-- Signals to evaluate
--ENTRADAS
signal actualTestTotalLength : std_logic_vector(31 downto 0);
signal inputBlock : std_logic_vector(31 downto 0);
signal readInput : std_logic;
signal blockLength : std_logic_vector(1 downto 0);
signal finalBlock : std_logic;
signal start : std_logic;
signal operationID : std_logic_vector(31 downto 0);
signal seed : std_logic_vector(31 downto 0);
--SALIDAS
signal canAccept : std_logic;
signal resultReady : std_logic;
signal result : std_logic_vector(31 downto 0);
signal resultID : std_logic_vector(31 downto 0);
--RELOJ
--Salidas de depuracion
signal dataStep1_dbg : std_logic_vector(31 downto 0);
signal dataStep2_dbg : std_logic_vector(31 downto 0);
signal dataStep3_dbg : std_logic_vector(31 downto 0);
signal dataStep4_dbg : std_logic_vector(31 downto 0);
signal dataStep5_dbg : std_logic_vector(31 downto 0);
signal dataStep1_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep2_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep3_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep4_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep5_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep1_dbg : std_logic_vector(31 downto 0);
signal finalStep2_dbg : std_logic_vector(31 downto 0);
signal finalStep3_dbg : std_logic_vector(31 downto 0);
signal finalStep4_dbg : std_logic_vector(31 downto 0);
signal finalStep5_dbg : std_logic_vector(31 downto 0);
signal finalStep1_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep2_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep3_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep4_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep5_ID_dbg : std_logic_vector(31 downto 0);
signal resultsBankCounterSignal : integer := 0;
begin
seed <= simulationSeed;
uut: work.MurmurHashUtils.MurmurHash32Generator PORT MAP (
--ENTRADAS
inputBlock => inputBlock,
readInput => readInput,
blockLength => blockLength,
finalBlock => finalBlock,
start => start,
operationID => operationID,
seed => seed,
--SALIDAS
canAccept => canAccept,
resultReady => resultReady,
result => result,
resultID => resultID,
--RELOJ
clk => clk,
--Salidas de depuracion
dataStep1_dbg => dataStep1_dbg,
dataStep2_dbg => dataStep2_dbg,
dataStep3_dbg => dataStep3_dbg,
dataStep4_dbg => dataStep4_dbg,
dataStep5_dbg => dataStep5_dbg,
dataStep1_ID_dbg => dataStep1_ID_dbg,
dataStep2_ID_dbg => dataStep2_ID_dbg,
dataStep3_ID_dbg => dataStep3_ID_dbg,
dataStep4_ID_dbg => dataStep4_ID_dbg,
dataStep5_ID_dbg => dataStep5_ID_dbg,
finalStep1_dbg => finalStep1_dbg,
finalStep2_dbg => finalStep2_dbg,
finalStep3_dbg => finalStep3_dbg,
finalStep4_dbg => finalStep4_dbg,
finalStep5_dbg => finalStep5_dbg,
finalStep1_ID_dbg => finalStep1_ID_dbg,
finalStep2_ID_dbg => finalStep2_ID_dbg,
finalStep3_ID_dbg => finalStep3_ID_dbg,
finalStep4_ID_dbg => finalStep4_ID_dbg,
finalStep5_ID_dbg => finalStep5_ID_dbg
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
verification: process (clk, resultReady, result, resultsBankCounterSignal)
begin
if( rising_edge(clk) ) then
if( resultsBankCounterSignal = resultsBank'length ) then
errorDetected <= '0';
else
if (resultReady = '1') then
if( (resultsBank(resultsBankCounterSignal)/=result) ) then
errorDetected <= '1';
else
errorDetected <= '0';
end if;
resultsBankCounterSignal <= resultsBankCounterSignal+1;
else
errorDetected <= '0';
end if;
end if;
end if;
end process verification;
Test: process is
variable byteCounter : integer := 0;--contador de bytes en el bloque de datos actual
variable byteInputCounter : integer := 0;-- contador de bytes totales elidos en el testBench
variable resultsBankCounter : integer := 0;
variable actualByte : std_logic_vector(7 downto 0);-- byet actualmetne leido
variable inputBlockCurrentByte : integer :=0;
variable input : std_logic_vector(31 downto 0) := (others => '0') ;
variable startBlock : boolean := false;
variable endBlock : boolean := false;
begin
start <= '0';--que ya no lea otro dato
readInput <= '0';
operationID <= ( others => '0');
wait for clk_period*10;
while (resultsBankCounter < resultsBank'length) loop
start <= '0';--que ya no lea otro dato
readInput <= '0';
inputBlockCurrentByte := 0;
byteCounter:=0;
inputBlockCurrentByte := 0;
wait for clk_period;
start <= '1';
actualTestTotalLength <= entrysLengths(resultsBankCounter);
while(byteCounter<entrysLengths(resultsBankCounter)) loop
actualByte := dataBank(byteInputCounter);
input((inputBlockCurrentByte*8+7) downto (inputBlockCurrentByte*8)) := actualByte;
--input(7 downto 0) := actualByte;
endBlock := ((byteCounter+1)=entrysLengths(resultsBankCounter));
if ( ( (byteCounter mod 4) = 3 ) or (endBlock) ) then
finalBlock<= mh3_boolean_to_std_logic(endBlock);
inputBlock <= input;
readInput <= '1';
blockLength <= std_logic_vector( to_unsigned(byteCounter, 2) );
wait for clk_period;
start <= '0';
input := (others => '0') ;
end if;
if (endBlock) then
readInput <= '0';
wait for clk_period;
end if;
byteCounter := byteCounter+1;
byteInputCounter := byteInputCounter+1;
inputBlockCurrentByte := ( (inputBlockCurrentByte+1) mod 4);
end loop;
resultsBankCounter := resultsBankCounter+1;
--wait for clk_period;
end loop;
wait;-- Que no se repita de forma indefinida
end process Test;
end Behavioral;
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_RFDEST is
Port ( RD : in STD_LOGIC_VECTOR (5 downto 0);
RFDEST : in STD_LOGIC;
nRD : out STD_LOGIC_VECTOR (5 downto 0));
end MUX_RFDEST;
architecture Behavioral of MUX_RFDEST is
begin
process(RD,RFDEST)
begin
if RFDEST='1' then
nRD<="001111";
else
nRD<=RD;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:37:54 03/23/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet4/display_test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: header_display
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY display_test IS
END display_test;
ARCHITECTURE behavior OF display_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT header_display
PORT(
char : OUT std_logic_vector(7 downto 0);
char_we : OUT std_logic;
tx_busy : IN std_logic;
busy : IN std_logic;
clk : IN std_logic;
ram_clk : OUT std_logic;
ram_enable : OUT std_logic;
ram_address : OUT std_logic_vector(11 downto 0);
ram_output : IN std_logic_vector(7 downto 0);
start : IN std_logic;
reset : IN std_logic
);
END COMPONENT;
--Inputs
signal tx_busy : std_logic := '0';
signal busy : std_logic := '0';
signal clk : std_logic := '0';
signal ram_output : std_logic_vector(7 downto 0) := (others => '0');
signal start : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal char : std_logic_vector(7 downto 0);
signal char_we : std_logic;
signal ram_clk : std_logic;
signal ram_enable : std_logic;
signal ram_address : std_logic_vector(11 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
constant ram_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: header_display PORT MAP (
char => char,
char_we => char_we,
tx_busy => tx_busy,
busy => busy,
clk => clk,
ram_clk => ram_clk,
ram_enable => ram_enable,
ram_address => ram_address,
ram_output => ram_output,
start => start,
reset => reset
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
ram_clk_process :process
begin
ram_clk <= '0';
wait for ram_clk_period/2;
ram_clk <= '1';
wait for ram_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- Engineer: Lefteris Kyriakakis
--
-- Create Date: 06/28/2017
-- Design Name: Serial-In-Parallel-Out Shift Register
-- Module Name: S2P Parallelizer - behave
-- Target Devices: Any
----------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity byte2word is
generic (
DATA_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
shift_i : in std_logic_vector(7 downto 0);
done_o : out std_logic;
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
) ;
end byte2word;
architecture behave of byte2word is
signal shift_count : integer range 0 to 7 := 0;
signal rx_done : std_logic := '0';
signal shift_data : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
signal init_rx_ff, init_rx_ff2 : std_logic := '0';
signal rx_en : std_logic := '0';
----------------------------------
attribute shreg_extract : string;
attribute shreg_extract of shift_data : signal is "yes";
begin
init_rx_pulse: process(clk_i, en_i)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
else
init_rx_ff <= en_i;
init_rx_ff2 <= init_rx_ff;
rx_en <= not(init_rx_ff2) and init_rx_ff;
end if;
end if;
end process;
shift_in: process(clk_i, en_i, shift_i, rx_done, shift_count)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
shift_data <= (others=>'0');
else
if rx_en = '1' and rx_done='0' then
--shift_data(TX_WIDTH-1 downto 0) <= shift_i; --MSB First
--shift_data(DATA_WIDTH-1 downto TX_WIDTH) <= shift_data(DATA_WIDTH-TX_WIDTH-1 downto 0);
shift_data <= shift_data(DATA_WIDTH-8-1 downto 0) & shift_i;
end if;
end if;
end if;
end process;
count_shift: process(clk_i, en_i, shift_i, rx_done, shift_count)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
shift_count <= 0;
rx_done <= '0';
else
if rx_en = '1' and rx_done='0' then
if shift_count = to_integer(unsigned(shift_cnt_i))-1 then
rx_done <= '1';
shift_count <= 0;
else
shift_count <= shift_count + 1;
end if;
else
rx_done <= '0';
end if;
end if;
end if;
end process;
done_o <= rx_done;
data_o <= shift_data(DATA_WIDTH-1 downto 0); --align data to the requested width
end architecture ; |
-- Engineer: Lefteris Kyriakakis
--
-- Create Date: 06/28/2017
-- Design Name: Serial-In-Parallel-Out Shift Register
-- Module Name: S2P Parallelizer - behave
-- Target Devices: Any
----------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity byte2word is
generic (
DATA_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
shift_i : in std_logic_vector(7 downto 0);
done_o : out std_logic;
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
) ;
end byte2word;
architecture behave of byte2word is
signal shift_count : integer range 0 to 7 := 0;
signal rx_done : std_logic := '0';
signal shift_data : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
signal init_rx_ff, init_rx_ff2 : std_logic := '0';
signal rx_en : std_logic := '0';
----------------------------------
attribute shreg_extract : string;
attribute shreg_extract of shift_data : signal is "yes";
begin
init_rx_pulse: process(clk_i, en_i)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
else
init_rx_ff <= en_i;
init_rx_ff2 <= init_rx_ff;
rx_en <= not(init_rx_ff2) and init_rx_ff;
end if;
end if;
end process;
shift_in: process(clk_i, en_i, shift_i, rx_done, shift_count)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
shift_data <= (others=>'0');
else
if rx_en = '1' and rx_done='0' then
--shift_data(TX_WIDTH-1 downto 0) <= shift_i; --MSB First
--shift_data(DATA_WIDTH-1 downto TX_WIDTH) <= shift_data(DATA_WIDTH-TX_WIDTH-1 downto 0);
shift_data <= shift_data(DATA_WIDTH-8-1 downto 0) & shift_i;
end if;
end if;
end if;
end process;
count_shift: process(clk_i, en_i, shift_i, rx_done, shift_count)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
shift_count <= 0;
rx_done <= '0';
else
if rx_en = '1' and rx_done='0' then
if shift_count = to_integer(unsigned(shift_cnt_i))-1 then
rx_done <= '1';
shift_count <= 0;
else
shift_count <= shift_count + 1;
end if;
else
rx_done <= '0';
end if;
end if;
end if;
end process;
done_o <= rx_done;
data_o <= shift_data(DATA_WIDTH-1 downto 0); --align data to the requested width
end architecture ; |
-- Engineer: Lefteris Kyriakakis
--
-- Create Date: 06/28/2017
-- Design Name: Serial-In-Parallel-Out Shift Register
-- Module Name: S2P Parallelizer - behave
-- Target Devices: Any
----------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity byte2word is
generic (
DATA_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
shift_i : in std_logic_vector(7 downto 0);
done_o : out std_logic;
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
) ;
end byte2word;
architecture behave of byte2word is
signal shift_count : integer range 0 to 7 := 0;
signal rx_done : std_logic := '0';
signal shift_data : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
signal init_rx_ff, init_rx_ff2 : std_logic := '0';
signal rx_en : std_logic := '0';
----------------------------------
attribute shreg_extract : string;
attribute shreg_extract of shift_data : signal is "yes";
begin
init_rx_pulse: process(clk_i, en_i)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
else
init_rx_ff <= en_i;
init_rx_ff2 <= init_rx_ff;
rx_en <= not(init_rx_ff2) and init_rx_ff;
end if;
end if;
end process;
shift_in: process(clk_i, en_i, shift_i, rx_done, shift_count)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
shift_data <= (others=>'0');
else
if rx_en = '1' and rx_done='0' then
--shift_data(TX_WIDTH-1 downto 0) <= shift_i; --MSB First
--shift_data(DATA_WIDTH-1 downto TX_WIDTH) <= shift_data(DATA_WIDTH-TX_WIDTH-1 downto 0);
shift_data <= shift_data(DATA_WIDTH-8-1 downto 0) & shift_i;
end if;
end if;
end if;
end process;
count_shift: process(clk_i, en_i, shift_i, rx_done, shift_count)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
shift_count <= 0;
rx_done <= '0';
else
if rx_en = '1' and rx_done='0' then
if shift_count = to_integer(unsigned(shift_cnt_i))-1 then
rx_done <= '1';
shift_count <= 0;
else
shift_count <= shift_count + 1;
end if;
else
rx_done <= '0';
end if;
end if;
end if;
end process;
done_o <= rx_done;
data_o <= shift_data(DATA_WIDTH-1 downto 0); --align data to the requested width
end architecture ; |
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.adcad7606_4_pkg.ALL;
ENTITY adcad7606_4_rtl_tb IS
END ENTITY adcad7606_4_rtl_tb;
ARCHITECTURE sim OF adcad7606_4_rtl_tb IS
--Sumulation Parameter:
CONSTANT main_period : TIME := 8 ns; -- 125MHz
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '0';
SIGNAL values : t_value_regs;
SIGNAL sl_sclk : STD_LOGIC := '0';
SIGNAL slv_Ss : STD_LOGIC := '0';
SIGNAL sl_mosi : STD_LOGIC := '0';
SIGNAL sl_miso : STD_LOGIC := '0';
SIGNAL sl_d_out_b : STD_LOGIC := '0';
SIGNAL slv_conv_start : STD_LOGIC_VECTOR(1 DOWNTO 0):= (OTHERS => '0');
SIGNAL sl_range : STD_LOGIC := '0';
SIGNAL slv_os : STD_LOGIC_VECTOR(2 DOWNTO 0):= (OTHERS => '0');
SIGNAL sl_busy : STD_LOGIC := '0';
SIGNAL sl_first_data : STD_LOGIC := '0';
SIGNAL sl_stby_n : STD_LOGIC := '0';
SIGNAL sl_adc_reset : STD_LOGIC := '0';
SIGNAL config : t_config;
BEGIN
--create component
my_unit_under_test : adcad7606_4
GENERIC MAP(
BASE_CLK => 33000000,
SCLK_FREQUENCY => 1000000
)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
ot_values => values,
config => config,
osl_sclk => sl_sclk,
oslv_Ss => slv_Ss,
osl_mosi => sl_mosi,
isl_miso => sl_miso,
isl_d_out_b => sl_d_out_b,
oslv_conv_start => slv_conv_start,
osl_range => sl_range,
oslv_os => slv_os,
isl_busy => sl_busy,
isl_first_data => sl_first_data,
osl_stby_n => sl_stby_n,
osl_adc_reset => sl_adc_reset
);
sl_clk <= NOT sl_clk after main_period/2;
config.range_select <= '0';
config.oversampling <= (OTHERS => '0');
config.standby <= '1';
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 2*main_period;
sl_reset_n <= '1';
WAIT FOR 3000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll32.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll32 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll32;
ARCHITECTURE SYN OF pll32 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 3,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
clk1_divide_by => 3,
clk1_duty_cycle => 50,
clk1_multiply_by => 4,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 41666,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=pll32",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "32.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.17500000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll32.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll32.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll32.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll32.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll32.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll32.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll32_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: logic_mem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY logic_mem IS
PORT
(
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END logic_mem;
ARCHITECTURE SYN OF logic_mem IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => 10,
widthad_b => 10,
width_a => 16,
width_b => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
address_b => rdaddress,
clock0 => clock,
data_a => data,
wren_a => wren,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL logic_mem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL logic_mem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL logic_mem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL logic_mem.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL logic_mem_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram128
-- File: syncram128.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 128-bit syncronous 1-port ram with 32-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram128 is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0;
paren : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127+16*paren downto 0);
dataout : out std_logic_vector (127+16*paren downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncram128 is
component unisim_syncram128
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0)
);
end component;
signal dinp, doutp : std_logic_vector(143 downto 0);
signal xenable,xwrite : std_logic_vector(3 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else "0000";
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else "0000";
custominx <= (others => '0');
nocust: if syncram_has_customif(tech)=0 or has_sram128(tech)=0 or paren=1 generate
customoutx <= (others => '0');
end generate;
nopar : if paren = 0 generate
s128 : if has_sram128(tech) = 1 generate
uni : if (is_unisim(tech) = 1) generate
x0 : unisim_syncram128 generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_syncram_we generic map (abits => abits, dbits => 128)
port map(clk, address, datain, dataout, xenable, xwrite);
end generate;
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram128: " & tost(2**abits) & "x128" &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nos128 : if has_sram128(tech) = 0 generate
x0 : syncram64 generic map (tech, abits, testen, 0, custombits)
port map (clk, address, datain(127 downto 64), dataout(127 downto 64),
enable(3 downto 2), write(3 downto 2), testin
);
x1 : syncram64 generic map (tech, abits, testen, 0, custombits)
port map (clk, address, datain(63 downto 0), dataout(63 downto 0),
enable(1 downto 0), write(1 downto 0), testin
);
end generate;
end generate;
par : if paren = 1 generate
dinp <= datain(127+16*paren downto 120+16*paren) & datain(127 downto 64) &
datain(127+8*paren downto 120+8*paren) & datain(63 downto 0);
dataout <= doutp(143 downto 136) & doutp(71 downto 64) &
doutp(135 downto 72) & doutp(63-16+16*paren downto 0);
x0 : syncram64 generic map (tech, abits, testen, 1, custombits)
port map (clk, address, dinp(143 downto 72), doutp(143 downto 72),
enable(3 downto 2), write(3 downto 2), testin
);
x1 : syncram64 generic map (tech, abits, testen, 1, custombits)
port map (clk, address, dinp(71 downto 0), doutp(71 downto 0),
enable(1 downto 0), write(1 downto 0), testin
);
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: cpu_disas
-- File: cpu_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
entity cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of cpu_disas is
begin
dummy <= '1';
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1'); --and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (iindex, pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
entity fpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
wr2inst : in std_logic_vector(31 downto 0);
wr2pc : in std_logic_vector(31 downto 2);
divinst : in std_logic_vector(31 downto 0);
divpc : in std_logic_vector(31 downto 2);
dbg_wrdata: in std_logic_vector(63 downto 0);
index : in std_logic_vector(3 downto 0);
dbg_wren : in std_logic_vector(1 downto 0);
resv : in std_ulogic;
ld : in std_ulogic;
rdwr : in std_ulogic;
ccwr : in std_ulogic;
rdd : in std_ulogic;
div_valid : in std_ulogic;
holdn : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of fpu_disas is
begin
dummy <= '1';
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
if rising_edge(clk) and (rstn = '1') then
valid := ((((rdwr and not ld) or ccwr or (ld and resv)) and holdn) = '1');
print_fpinsn(0, wr2pc(31 downto 2) & "00", wr2inst, dbg_wrdata,
(rdd = '1'), valid, false, (dbg_wren /= "00"));
print_fpinsn(0, divpc(31 downto 2) & "00", divinst, dbg_wrdata,
(rdd = '1'), (div_valid and holdn) = '1', false, (dbg_wren /= "00"));
end if;
end process;
end;
-- pragma translate_on
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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xQl5sbrHKQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5088)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
GiXoB0rea1HWk3zGRZ5UdWOdwQS0YsIjSOIF1NW94llt0aPZJE8/A82cSwOPERTMFQiuyYzzNt2y
xQl5sbrHKQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
G44AJicWsQRbp+6jF04u5eg9aKSHrXoA+1aGxibesHlZ7lplKX7PgSoUjzm+IpPDOLDOFyDHDQOv
aquL4/E8RGBVQ3LKgTDl7ysgnvSjCyvJCuRRcqGw1CG/DYJHkNO1n6f4WRDzjfRFuit8IpUvr9tR
TEO0bFYFA+oalqehbzQ=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5088)
`protect data_block
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`protect begin_protected
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`protect end_protected
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.wishbonepkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
break: out std_logic;
-- STACK
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
cache_flush: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end zpu_core_extreme_icache;
architecture behave of zpu_core_extreme_icache is
component lshifter is
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 downto 0);
output: out std_logic_vector(63 downto 0);
multorshift: in std_logic
);
end component;
component zpuino_icache is
generic (
ADDRESS_HIGH: integer := 26
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
valid: out std_logic;
data: out std_logic_vector(wordSize-1 downto 0);
address: in std_logic_vector(maxAddrBit downto 0);
strobe: in std_logic;
enable: in std_logic;
stall: out std_logic;
flush: in std_logic;
-- Master wishbone interface
m_wb_ack_i: in std_logic;
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
m_wb_cyc_o: out std_logic;
m_wb_stb_o: out std_logic;
m_wb_stall_i: in std_logic;
m_wb_we_o: out std_logic
);
end component;
component zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end component;
signal cache_valid: std_logic;
signal cache_data: std_logic_vector(wordSize-1 downto 0);
signal cache_address: std_logic_vector(maxAddrBit downto 0);
signal cache_strobe: std_logic;
signal cache_enable: std_logic;
signal cache_stall: std_logic;
signal lshifter_enable: std_logic;
signal lshifter_done: std_logic;
signal lshifter_input: std_logic_vector(31 downto 0);
signal lshifter_amount: std_logic_vector(31 downto 0);
signal lshifter_output: std_logic_vector(63 downto 0);
signal lshifter_multorshift: std_logic;
signal begin_inst: std_logic;
signal trace_opcode: std_logic_vector(7 downto 0);
signal trace_pc: std_logic_vector(maxAddrBitIncIO downto 0);
signal trace_sp: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal trace_topOfStack: std_logic_vector(wordSize-1 downto 0);
signal trace_topOfStackB: std_logic_vector(wordSize-1 downto 0);
-- state machine.
type State_Type is
(
State_Execute,
State_LoadStack,
State_Loadb,
State_Loadh,
State_Resync2,
State_WaitSPB,
State_ResyncFromStoreStack,
State_Neqbranch,
State_Ashiftleft,
State_Mult,
State_MultF16
);
type DecodedOpcodeType is
(
Decoded_Nop,
Decoded_Idle,
Decoded_Im0,
Decoded_ImN,
Decoded_LoadSP,
Decoded_Dup,
Decoded_DupStackB,
Decoded_StoreSP,
Decoded_Pop,
Decoded_PopDown,
Decoded_AddSP,
Decoded_AddStackB,
Decoded_Shift,
Decoded_Emulate,
Decoded_Break,
Decoded_PushSP,
Decoded_PopPC,
Decoded_Add,
Decoded_Or,
Decoded_And,
Decoded_Load,
Decoded_Not,
Decoded_Flip,
Decoded_Store,
Decoded_PopSP,
Decoded_Interrupt,
Decoded_Neqbranch,
Decoded_Eq,
Decoded_Storeb,
Decoded_Storeh,
Decoded_Ulessthan,
Decoded_Lessthan,
Decoded_Ashiftleft,
Decoded_Ashiftright,
Decoded_Loadb,
Decoded_Loadh,
Decoded_Call,
Decoded_Mult,
Decoded_MultF16
);
constant spMaxBit: integer := stackSize_bits-1;
constant minimal_implementation: boolean := false;
subtype index is integer range 0 to 3;
signal tOpcode_sel : index;
function pc_to_cpuword(pc: unsigned) return unsigned is
variable r: unsigned(wordSize-1 downto 0);
begin
r := (others => DontCareValue);
r(maxAddrBit downto 0) := pc;
return r;
end pc_to_cpuword;
function pc_to_memaddr(pc: unsigned) return unsigned is
variable r: unsigned(maxAddrBit downto 0);
begin
r := (others => '0');
r(maxAddrBit downto minAddrBit) := pc(maxAddrBit downto minAddrBit);
return r;
end pc_to_memaddr;
-- Prefetch stage registers
type stackChangeType is (
Stack_Same,
Stack_Push,
Stack_Pop,
Stack_DualPop
);
type tosSourceType is
(
Tos_Source_PC,
Tos_Source_FetchPC,
Tos_Source_Idim0,
Tos_Source_IdimN,
Tos_Source_StackB,
Tos_Source_SP,
Tos_Source_Add,
Tos_Source_And,
Tos_Source_Or,
Tos_Source_Eq,
Tos_Source_Not,
Tos_Source_Flip,
Tos_Source_LoadSP,
Tos_Source_AddSP,
Tos_Source_AddStackB,
Tos_Source_Shift,
Tos_Source_Ulessthan,
Tos_Source_Lessthan,
Tos_Source_LSU,
Tos_Source_None
);
type decoderstate_type is (
State_Run,
State_Jump,
State_Inject,
State_InjectJump
);
type decoderegs_type is record
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opWillFreeze: std_logic; -- '1' if we know in advance this opcode will freeze pipeline
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
pcint: unsigned(maxAddrBit downto 0);
idim: std_logic;
im: std_logic;
stackOperation: stackChangeType;
spOffset: unsigned(4 downto 0);
im_emu: std_logic;
--emumode: std_logic;
break: std_logic;
state: decoderstate_type;
end record;
type prefetchregs_type is record
sp: unsigned(spMaxBit downto 2);
spnext: unsigned(spMaxBit downto 2);
valid: std_logic;
decodedOpcode: DecodedOpcodeType;
tosSource: tosSourceType;
opcode: std_logic_vector(OpCode_Size-1 downto 0);
pc: unsigned(maxAddrBit downto 0);
fetchpc: unsigned(maxAddrBit downto 0);
idim: std_logic;
break: std_logic;
load: std_logic;
opWillFreeze: std_logic;
recompute_sp: std_logic;
end record;
type exuregs_type is record
idim: std_logic;
break: std_logic;
inInterrupt:std_logic;
tos: unsigned(wordSize-1 downto 0);
tos_save: unsigned(wordSize-1 downto 0);
nos_save: unsigned(wordSize-1 downto 0);
state: State_Type;
-- Wishbone control signals (registered)
wb_cyc: std_logic;
wb_stb: std_logic;
wb_we: std_logic;
end record;
-- Registers for each stage
signal exr: exuregs_type;
signal prefr: prefetchregs_type;
signal decr: decoderegs_type;
signal pcnext: unsigned(maxAddrBit downto 0); -- Helper only. TODO: move into variable
signal sp_load: unsigned(spMaxBit downto 2); -- SP value to load, coming from EXU into PFU
signal decode_load_sp: std_logic; -- Load SP signal from EXU to PFU
signal exu_busy: std_logic; -- EXU busy ( stalls PFU )
signal pfu_busy: std_logic; -- PFU busy ( stalls DFU )
signal decode_jump: std_logic; -- Jump signal from EXU to DFU
signal jump_address: unsigned(maxAddrBit downto 0); -- Jump address from EXU to DFU
signal do_interrupt: std_logic; -- Helper.
-- Sampled signals from the opcode. Left as signals
-- in order to simulate design.
signal sampledOpcode: std_logic_vector(OpCode_Size-1 downto 0);
signal sampledDecodedOpcode: DecodedOpcodeType;
signal sampledOpWillFreeze: std_logic;
signal sampledStackOperation: stackChangeType;
signal sampledspOffset: unsigned(4 downto 0);
signal sampledTosSource: tosSourceType;
signal nos: unsigned(wordSize-1 downto 0); -- This is only a helper
signal wroteback_q: std_logic; -- TODO: get rid of this here, move to EXU regs
-- Test debug signals
signal freeze_all: std_logic := '0';
signal single_step: std_logic := '0';
-- LSU
signal lsu_req: std_logic;
signal lsu_we: std_logic;
signal lsu_busy: std_logic;
signal lsu_data_read: std_logic_vector(wordSize-1 downto 0);
signal lsu_data_write: std_logic_vector(wordSize-1 downto 0);
signal lsu_data_sel: std_logic_vector(3 downto 0);
signal lsu_address: std_logic_vector(maxAddrBitIncIO downto 0);
begin
-- Debug interface
dbg_out.pc <= std_logic_vector(prefr.pc);
dbg_out.opcode <= prefr.opcode;
--dbg_out.sp <= std_logic_vector(prefr.sp);
dbg_out.brk <= exr.break;
--dbg_out.stacka <= std_logic_vector(exr.tos);
--dbg_out.stackb <= std_logic_vector(nos);
dbg_out.idim <= prefr.idim;
shl: lshifter
port map (
clk => wb_clk_i,
rst => wb_rst_i,
enable => lshifter_enable,
done => lshifter_done,
inputA => lshifter_input,
inputB => lshifter_amount,
output => lshifter_output,
multorshift => lshifter_multorshift
);
stack_clk <= wb_clk_i;
-- synopsys translate_off
traceFileGenerate:
if Generate_Trace generate
trace_file: trace
port map (
clk => wb_clk_i,
begin_inst => begin_inst,
pc => trace_pc,
opcode => trace_opcode,
sp => trace_sp,
memA => trace_topOfStack,
memB => trace_topOfStackB,
busy => '0',--busy,
intsp => (others => 'U')
);
end generate;
-- synopsys translate_on
cache: zpuino_icache
generic map (
ADDRESS_HIGH => maxAddrBitBRAM
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
valid => cache_valid,
data => cache_data,
address => cache_address,
strobe => cache_strobe,
stall => cache_stall,
enable => cache_enable,
flush => cache_flush,
-- Master wishbone interface
m_wb_ack_i => rom_wb_ack_i,
m_wb_dat_i => rom_wb_dat_i,
m_wb_adr_o => rom_wb_adr_o,
m_wb_cyc_o => rom_wb_cyc_o,
m_wb_stb_o => rom_wb_stb_o,
m_wb_stall_i => rom_wb_stall_i
);
lsu: zpuino_lsu
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_ack_i => wb_ack_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_adr_o => wb_adr_o(maxAddrBitIncIO downto 2),
wb_cyc_o => wb_cyc_o,
wb_stb_o => wb_stb_o,
wb_sel_o => wb_sel_o,
wb_we_o => wb_we_o,
req => lsu_req,
we => lsu_we,
busy => lsu_busy,
data_read => lsu_data_read,
data_write => lsu_data_write,
data_sel => lsu_data_sel,
address => lsu_address
);
tOpcode_sel <= to_integer(decr.pcint(minAddrBit-1 downto 0));
do_interrupt <= '1' when wb_inta_i='1'
and exr.inInterrupt='0'
else '0';
decodeControl:
process(cache_data, tOpcode_sel, sp_load, decr,
do_interrupt, dbg_in.inject, dbg_in.opcode)
variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
variable localspOffset: unsigned(4 downto 0);
begin
if dbg_in.inject='1' then
tOpcode := dbg_in.opcode;
else
case (tOpcode_sel) is
when 0 => tOpcode := std_logic_vector(cache_data(31 downto 24));
when 1 => tOpcode := std_logic_vector(cache_data(23 downto 16));
when 2 => tOpcode := std_logic_vector(cache_data(15 downto 8));
when 3 => tOpcode := std_logic_vector(cache_data(7 downto 0));
when others =>
null;
end case;
end if;
sampledOpcode <= tOpcode;
sampledStackOperation <= Stack_Same;
sampledTosSource <= Tos_Source_None;
sampledOpWillFreeze <= '0';
localspOffset(4):=not tOpcode(4);
localspOffset(3 downto 0) := unsigned(tOpcode(3 downto 0));
if do_interrupt='1' and decr.im='0' then
sampledDecodedOpcode <= Decoded_Interrupt;
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_PC;
else
if (tOpcode(7 downto 7)=OpCode_Im) then
if decr.im='0' then
sampledStackOperation <= Stack_Push;
sampledTosSource <= Tos_Source_Idim0;
sampledDecodedOpcode<=Decoded_Im0;
else
sampledTosSource <= Tos_Source_IdimN;
sampledDecodedOpcode<=Decoded_ImN;
end if;
elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
sampledStackOperation <= Stack_Pop;
sampledTosSource <= Tos_Source_StackB;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Pop;
sampledTosSource <= Tos_Source_StackB;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_PopDown;
sampledTosSource <= Tos_Source_None;
else
sampledDecodedOpcode<=Decoded_StoreSP;
sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_StackB;
end if;
elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
sampledStackOperation <= Stack_Push;
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Dup;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_DupStackB;
sampledTosSource <= Tos_Source_StackB;
else
sampledDecodedOpcode<=Decoded_LoadSP;
sampledTosSource <= Tos_Source_LoadSP;
end if;
elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
-- Emulated instructions implemented in hardware
if minimal_implementation then
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
else
if (tOpcode(5 downto 0)=OpCode_Loadb) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadb;
sampledTosSource <= Tos_Source_LSU;
elsif (tOpcode(5 downto 0)=OpCode_Loadh) then
sampledStackOperation<=Stack_Same;
sampledDecodedOpcode<=Decoded_Loadh;
sampledTosSource <= Tos_Source_LSU;
elsif (tOpcode(5 downto 0)=OpCode_Neqbranch) then
sampledStackOperation<=Stack_DualPop;
sampledDecodedOpcode<=Decoded_Neqbranch;
sampledOpWillFreeze <= '1';
elsif (tOpcode(5 downto 0)=OpCode_Call) then
sampledDecodedOpcode<=Decoded_Call;
sampledStackOperation<=Stack_Same;
sampledTosSource<=Tos_Source_FetchPC;
elsif (tOpcode(5 downto 0)=OpCode_Eq) then
sampledDecodedOpcode<=Decoded_Eq;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Eq;
elsif (tOpcode(5 downto 0)=OpCode_Ulessthan) then
sampledDecodedOpcode<=Decoded_Ulessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Ulessthan;
elsif (tOpcode(5 downto 0)=OpCode_Lessthan) then
sampledDecodedOpcode<=Decoded_Lessthan;
sampledStackOperation<=Stack_Pop;
sampledTosSource<=Tos_Source_Lessthan;
elsif (tOpcode(5 downto 0)=OpCode_StoreB) then
sampledDecodedOpcode<=Decoded_StoreB;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_StoreH) then
sampledDecodedOpcode<=Decoded_StoreH;
sampledStackOperation<=Stack_DualPop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Mult) then
sampledDecodedOpcode<=Decoded_Mult;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
elsif (tOpcode(5 downto 0)=OpCode_Ashiftleft) then
sampledDecodedOpcode<=Decoded_Ashiftleft;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Emulate;
sampledStackOperation<=Stack_Push; -- will push PC
sampledTosSource <= Tos_Source_FetchPC;
end if;
end if;
elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
if localspOffset=0 then
sampledDecodedOpcode<=Decoded_Shift;
sampledTosSource <= Tos_Source_Shift;
elsif localspOffset=1 then
sampledDecodedOpcode<=Decoded_AddStackB;
sampledTosSource <= Tos_Source_AddStackB;
else
sampledDecodedOpcode<=Decoded_AddSP;
sampledTosSource <= Tos_Source_AddSP;
end if;
else
case tOpcode(3 downto 0) is
when OpCode_Break =>
sampledDecodedOpcode<=Decoded_Break;
sampledOpWillFreeze <= '1';
when OpCode_PushSP =>
sampledStackOperation <= Stack_Push;
sampledDecodedOpcode<=Decoded_PushSP;
sampledTosSource <= Tos_Source_SP;
when OpCode_PopPC =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_PopPC;
sampledTosSource <= Tos_Source_StackB;
when OpCode_Add =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Add;
sampledTosSource <= Tos_Source_Add;
when OpCode_Or =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_Or;
sampledTosSource <= Tos_Source_Or;
when OpCode_And =>
sampledStackOperation <= Stack_Pop;
sampledDecodedOpcode<=Decoded_And;
sampledTosSource <= Tos_Source_And;
when OpCode_Load =>
sampledDecodedOpcode<=Decoded_Load;
--sampledOpWillFreeze<='1';
sampledTosSource <= Tos_Source_LSU;
when OpCode_Not =>
sampledDecodedOpcode<=Decoded_Not;
sampledTosSource <= Tos_Source_Not;
when OpCode_Flip =>
sampledDecodedOpcode<=Decoded_Flip;
sampledTosSource <= Tos_Source_Flip;
when OpCode_Store =>
sampledStackOperation <= Stack_DualPop;
sampledDecodedOpcode<=Decoded_Store;
sampledOpWillFreeze<='1';
when OpCode_PopSP =>
sampledDecodedOpcode<=Decoded_PopSP;
sampledOpWillFreeze<='1';
when OpCode_NA4 =>
if enable_fmul16 then
sampledDecodedOpcode<=Decoded_MultF16;
sampledStackOperation<=Stack_Pop;
sampledOpWillFreeze<='1';
else
sampledDecodedOpcode<=Decoded_Nop;
end if;
when others =>
sampledDecodedOpcode<=Decoded_Nop;
end case;
end if;
end if;
sampledspOffset <= localspOffset;
end process;
-- Decode/Fetch unit
cache_enable <= not exu_busy;
process(decr, jump_address, decode_jump, wb_clk_i, sp_load,
sampledDecodedOpcode,sampledOpcode,decode_load_sp,
exu_busy, pfu_busy,
pcnext, cache_valid, wb_rst_i, sampledStackOperation, sampledspOffset,
sampledTosSource, prefr.recompute_sp, sampledOpWillFreeze,
dbg_in.flush, dbg_in.inject,dbg_in.injectmode,
prefr.valid, prefr.break, cache_stall
)
variable w: decoderegs_type;
begin
w := decr;
pcnext <= decr.fetchpc + 1;
cache_address(maxAddrBit downto 0) <= std_logic_vector(decr.fetchpc(maxAddrBit downto 0));
if wb_rst_i='1' then
w.pc := (others => '0');
w.pcint := (others => '0');
w.valid := '0';
w.fetchpc := (others => '0');
w.im:='0';
w.im_emu:='0';
w.state := State_Run;
w.break := '0';
cache_strobe <= DontCareValue;
else
cache_strobe <= '1';
case decr.state is
when State_Run =>
if pfu_busy='0' then
if dbg_in.injectmode='0' and decr.break='0' and cache_stall='0' then
w.fetchpc := pcnext;
end if;
-- Jump request
if decode_jump='1' then
w.valid := '0';
w.im := '0';
w.break := '0'; -- Invalidate eventual break after branch instruction
--rom_wb_cyc_o<='0';
cache_strobe<='0';
--if rom_wb_stall_i='0' then
w.fetchpc := jump_address;
--else
w.state := State_Jump;
--end if;
else
if dbg_in.injectmode='1' then --or decr.break='1' then
-- At this point we ought to push a new op into the pipeline.
-- Since we're entering inject mode, invalidate next operation,
-- but save the current IM flag.
w.im_emu := decr.im;
w.valid := '0';
--rom_wb_cti_o <= CTI_CYCLE_ENDOFBURST;
--rom_wb_cyc_o <='0';
cache_strobe <= '0';
-- Wait until no work is to be done
if prefr.valid='0' and decr.valid='0' and exu_busy='0' then
w.state := State_Inject;
w.im:='0';
end if;
if decr.break='0' then
w.pc := decr.pcint;
end if;
else
if decr.break='1' then
w.valid := '0';
else
--if exu_busy='0' then
w.valid := cache_valid;
--end if;
end if;
if cache_valid='1' then
--if exu_busy='0' then
w.im := sampledOpcode(7);
--end if;
if sampledDecodedOpcode=Decoded_Break then
w.break:='1';
end if;
end if;
if prefr.break='0' and cache_stall='0' then
w.pcint := decr.fetchpc;
w.pc := decr.pcint;
end if;
--if cache_stall='0' then
if exu_busy='0' then
w.opcode := sampledOpcode;
end if;
--end if;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
when State_Jump =>
w.valid := '0';
if cache_stall='0' then
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Run;
end if;
when State_InjectJump =>
w.valid := '0';
w.pcint := decr.fetchpc;
w.fetchpc := pcnext;
w.state := State_Inject;
when State_Inject =>
-- NOTE: disable ROM
--rom_wb_cyc_o <= '0';
if dbg_in.injectmode='0' then
w.im := decr.im_emu;
w.fetchpc := decr.pcint;
w.state := State_Run;
w.break := '0';
else
-- Handle opcode injection
-- TODO: merge this with main decode.
-- NOTE: we don't check busy here, it's up to debug unit to do it
--if pfu_busy='0' then
--w.fetchpc := pcnext;
-- Jump request
if decode_jump='1' then
w.fetchpc := jump_address;
w.valid := '0';
w.im := '0';
w.state := State_InjectJump;
else
w.valid := dbg_in.inject;
if dbg_in.inject='1' then
w.im := sampledOpcode(7);
--w.break := '0';
--w.pcint := decr.fetchpc;
w.opcode := sampledOpcode;
--w.pc := decr.pcint;
end if;
end if;
w.opWillFreeze := sampledOpWillFreeze;
w.decodedOpcode := sampledDecodedOpcode;
w.stackOperation := sampledStackOperation;
w.spOffset := sampledspOffset;
w.tosSource := sampledTosSource;
w.idim := decr.im;
end if;
--end if;
end case;
end if; -- rst
if rising_edge(wb_clk_i) then
decr <= w;
end if;
end process;
-- Prefetch/Load unit.
sp_load <= exr.tos(spMaxBit downto 2); -- Will be delayed one clock cycle
process(wb_clk_i, wb_rst_i, decr, prefr, exu_busy, decode_jump, sp_load,
decode_load_sp, dbg_in.flush)
variable w: prefetchregs_type;
variable i_op_freeze: std_logic;
begin
w := prefr;
pfu_busy<='0';
stack_b_addr <= std_logic_vector(prefr.spnext + 1);
w.recompute_sp:='0';
-- Stack
w.load := decode_load_sp;
if decode_load_sp='1' then
pfu_busy <= '1';
w.spnext := sp_load;
w.recompute_sp := '1';
else
pfu_busy <= exu_busy;
if decr.valid='1' then
if (exu_busy='0' and decode_jump='0') or prefr.recompute_sp='1' then
case decr.stackOperation is
when Stack_Push =>
w.spnext := prefr.spnext - 1;
when Stack_Pop =>
w.spnext := prefr.spnext + 1;
when Stack_DualPop =>
w.spnext := prefr.spnext + 2;
when others =>
end case;
w.sp := prefr.spnext;
end if;
end if;
end if;
case decr.decodedOpcode is
when Decoded_LoadSP | decoded_AddSP =>
stack_b_addr <= std_logic_vector(prefr.spnext + decr.spOffset);
when others =>
end case;
if decode_jump='1' then -- this is a pipeline "invalidate" flag.
w.valid := '0';
else
if dbg_in.flush='1' then
w.valid := '0';
else
if exu_busy='0' then
w.valid := decr.valid;
end if;
end if;
end if;
-- Moved op_will_freeze from decoder to here
case decr.decodedOpcode is
when Decoded_StoreSP
| Decoded_LoadB
| Decoded_Neqbranch
| Decoded_StoreB
| Decoded_Mult
| Decoded_Ashiftleft
| Decoded_Break
--| Decoded_Load
| Decoded_LoadH
| Decoded_Store
| Decoded_StoreH
| Decoded_PopSP
| Decoded_MultF16 =>
i_op_freeze := '1';
when others =>
i_op_freeze := '0';
end case;
if exu_busy='0' then
w.decodedOpcode := decr.decodedOpcode;
w.tosSource := decr.tosSource;
w.opcode := decr.opcode;
w.opWillFreeze := i_op_freeze;
w.pc := decr.pc;
w.fetchpc := decr.pcint;
w.idim := decr.idim;
w.break := decr.break;
end if;
if wb_rst_i='1' then
w.spnext := unsigned(spStart(spMaxBit downto 2));
--w.sp := unsigned(spStart(10 downto 2));
w.valid := '0';
w.idim := '0';
w.recompute_sp:='0';
end if;
if rising_edge(wb_clk_i) then
prefr <= w;
end if;
end process;
process(prefr,exr,nos)
begin
trace_pc <= (others => '0');
trace_pc(maxAddrBit downto 0) <= std_logic_vector(prefr.pc);
trace_opcode <= prefr.opcode;
trace_sp <= (others => '0');
trace_sp(spMaxBit downto 2) <= std_logic_vector(prefr.sp);
trace_topOfStack <= std_logic_vector( exr.tos );
trace_topOfStackB <= std_logic_vector( nos );
end process;
-- IO/Memory Accesses
lsu_address <= std_logic_vector(exr.tos(maxAddrBitIncIO downto 0));
--wb_cyc_o <= exr.wb_cyc;
--wb_stb_o <= exr.wb_stb;
--wb_we_o <= exr.wb_we;
--lsu_data_write <= std_logic_vector( nos );
freeze_all <= dbg_in.freeze;
process(exr, wb_inta_i, wb_clk_i, wb_rst_i, pcnext, stack_a_read,stack_b_read,
wb_ack_i, wb_dat_i, do_interrupt,exr, prefr, nos,
single_step, freeze_all, dbg_in.step, wroteback_q,lshifter_done,lshifter_output,
lsu_busy, lsu_data_read
)
variable spOffset: unsigned(4 downto 0);
variable w: exuregs_type;
variable instruction_executed: std_logic;
variable wroteback: std_logic;
variable datawrite: std_logic_vector(wordSize-1 downto 0);
variable sel: std_logic_vector(3 downto 0);
begin
w := exr;
instruction_executed := '0'; -- used for single stepping
stack_b_writeenable <= (others => '0');
stack_a_enable <= '1';
stack_b_enable <= '1';
exu_busy <= '0';
decode_jump <= '0';
jump_address <= (others => DontCareValue);
lshifter_enable <= '0';
lshifter_amount <= std_logic_vector(exr.tos_save);
lshifter_input <= std_logic_vector(exr.nos_save);
lshifter_multorshift <= '0';
poppc_inst <= '0';
begin_inst<='0';
stack_a_addr <= std_logic_vector( prefr.sp );
stack_a_writeenable <= (others => '0');
wroteback := wroteback_q;
stack_a_write <= std_logic_vector(exr.tos);
spOffset(4):=not prefr.opcode(4);
spOffset(3 downto 0) := unsigned(prefr.opcode(3 downto 0));
if wb_inta_i='0' then
w.inInterrupt := '0';
end if;
stack_b_write<=(others => DontCareValue);
if wroteback_q='1' then
nos <= unsigned(stack_a_read);
else
nos <= unsigned(stack_b_read);
end if;
decode_load_sp <= '0';
lsu_req <= '0';
lsu_we <= DontCareValue;
lsu_data_sel <= (others => DontCareValue);
lsu_data_write <= (others => DontCareValue);
case exr.state is
when State_ResyncFromStoreStack =>
exu_busy <= '1';
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_a_enable<='1';
w.state := State_Resync2;
wroteback := '0';
when State_Resync2 =>
w.tos := unsigned(stack_a_read);
instruction_executed := '1';
exu_busy <= '0';
wroteback := '0';
stack_b_enable <= '1';
w.state := State_Execute;
when State_Execute =>
instruction_executed:='0';
if prefr.valid='1' then
exu_busy <= prefr.opWillFreeze;
if freeze_all='0' or single_step='1' then
wroteback := '0';
w.nos_save := nos;
w.tos_save := exr.tos;
w.idim := prefr.idim;
w.break:= prefr.break;
begin_inst<='1';
instruction_executed := '1';
-- TOS big muxer
case prefr.tosSource is
when Tos_Source_PC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.pc;
when Tos_Source_FetchPC =>
w.tos := (others => '0');
w.tos(maxAddrBit downto 0) := prefr.fetchpc;
when Tos_Source_Idim0 =>
for i in wordSize-1 downto 7 loop
w.tos(i) := prefr.opcode(6);
end loop;
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_IdimN =>
w.tos(wordSize-1 downto 7) := exr.tos(wordSize-8 downto 0);
w.tos(6 downto 0) := unsigned(prefr.opcode(6 downto 0));
when Tos_Source_StackB =>
w.tos := nos;
when Tos_Source_SP =>
w.tos := (others => '0');
w.tos(31) := '1'; -- Stack address
w.tos(spMaxBit downto 2) := prefr.sp;
when Tos_Source_Add =>
w.tos := exr.tos + nos;
when Tos_Source_And =>
w.tos := exr.tos and nos;
when Tos_Source_Or =>
w.tos := exr.tos or nos;
when Tos_Source_Eq =>
w.tos := (others => '0');
if nos = exr.tos then
w.tos(0) := '1';
end if;
when Tos_Source_Ulessthan =>
w.tos := (others => '0');
if exr.tos < nos then
w.tos(0) := '1';
end if;
when Tos_Source_Lessthan =>
w.tos := (others => '0');
if signed(exr.tos) < signed(nos) then
w.tos(0) := '1';
end if;
when Tos_Source_Not =>
w.tos := not exr.tos;
when Tos_Source_Flip =>
for i in 0 to wordSize-1 loop
w.tos(i) := exr.tos(wordSize-1-i);
end loop;
when Tos_Source_LoadSP =>
w.tos := unsigned(stack_b_read);
when Tos_Source_AddSP =>
w.tos := w.tos + unsigned(stack_b_read);
when Tos_Source_AddStackB =>
w.tos := w.tos + nos;
when Tos_Source_Shift =>
w.tos := exr.tos + exr.tos;
when Tos_Source_LSU =>
if lsu_busy='0' then
w.tos := unsigned(lsu_data_read);
end if;
when others =>
end case;
case prefr.decodedOpcode is
when Decoded_Interrupt =>
w.inInterrupt := '1';
jump_address <= to_unsigned(32, maxAddrBit+1);
decode_jump <= '1';
stack_a_writeenable<=(others =>'1');
wroteback:='1';
stack_b_enable<= '0';
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Im0 =>
stack_a_writeenable<= (others =>'1');
wroteback:='1';
when Decoded_ImN =>
when Decoded_Nop =>
when Decoded_PopPC | Decoded_Call =>
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0);
poppc_inst <= '1';
stack_b_enable<='0';
-- Delay
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_Emulate =>
decode_jump <= '1';
jump_address <= (others => '0');
jump_address(9 downto 5) <= unsigned(prefr.opcode(4 downto 0));
stack_a_writeenable<=(others =>'1');
wroteback:='1';
when Decoded_PushSP =>
stack_a_writeenable<=(others =>'1');
wroteback:='1';
when Decoded_LoadSP =>
stack_a_writeenable <= (others =>'1');
wroteback:='1';
when Decoded_DupStackB =>
stack_a_writeenable <= (others => '1');
wroteback:='1';
when Decoded_Dup =>
stack_a_writeenable<= (others =>'1');
wroteback:='1';
when Decoded_AddSP =>
stack_a_writeenable <= (others =>'1');
when Decoded_StoreSP =>
stack_a_writeenable <= (others =>'1');
wroteback:='1';
stack_a_addr <= std_logic_vector(prefr.sp + spOffset);
instruction_executed := '0';
w.state := State_WaitSPB;
when Decoded_PopDown =>
stack_a_writeenable<=(others =>'1');
when Decoded_Pop =>
when Decoded_Ashiftleft =>
w.state := State_Ashiftleft;
when Decoded_Mult =>
w.state := State_Mult;
when Decoded_MultF16 =>
w.state := State_MultF16;
when Decoded_Store | Decoded_StoreB | Decoded_StoreH =>
if prefr.decodedOpcode=Decoded_Store then
datawrite := std_logic_vector(nos);
sel := "1111";
elsif prefr.decodedOpcode=Decoded_StoreH then
datawrite := (others => DontCareValue);
if exr.tos(1)='1' then
datawrite(15 downto 0) := std_logic_vector(nos(15 downto 0)) ;
sel := "0011";
else
datawrite(31 downto 16) := std_logic_vector(nos(15 downto 0)) ;
sel := "1100";
end if;
else
datawrite := (others => DontCareValue);
case exr.tos(1 downto 0) is
when "11" =>
datawrite(7 downto 0) := std_logic_vector(nos(7 downto 0)) ;
sel := "0001";
when "10" =>
datawrite(15 downto 8) := std_logic_vector(nos(7 downto 0)) ;
sel := "0010";
when "01" =>
datawrite(23 downto 16) := std_logic_vector(nos(7 downto 0)) ;
sel := "0100";
when "00" =>
datawrite(31 downto 24) := std_logic_vector(nos(7 downto 0)) ;
sel := "1000";
when others =>
end case;
end if;
stack_a_writeenable <=sel;
lsu_data_sel <= sel;
if exr.tos(31)='1' then
stack_a_addr <= std_logic_vector(exr.tos(spMaxBit downto 2));
stack_a_write <= datawrite;
stack_a_writeenable <= sel;
w.state := State_ResyncFromStoreStack;
else
--w.wb_we := '1';
--w.wb_cyc := '1';
--w.wb_stb := '1';
wroteback := wroteback_q; -- Keep WB
-- stack_a_enable<='0';
stack_a_enable<=not lsu_busy;
stack_a_writeenable <= (others => '0');
-- stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_a_addr <= std_logic_vector(prefr.spnext);
stack_b_enable<= not lsu_busy;
lsu_data_write <= datawrite;
instruction_executed := '0';
exu_busy <= '1';
lsu_req <= '1';
lsu_we <= '1';
if lsu_busy='0' then
wroteback := '0';
w.state := State_Resync2;
end if;
end if;
when Decoded_Load | Decoded_Loadb | Decoded_Loadh =>
--w.tos_save := exr.tos; -- Byte select
instruction_executed := '0';
wroteback := wroteback_q; -- Keep WB
if exr.tos(wordSize-1)='1' then
stack_a_addr<=std_logic_vector(exr.tos(spMaxBit downto 2));
stack_a_enable<='1';
exu_busy <= '1';
w.state := State_LoadStack;
else
exu_busy <= lsu_busy;
lsu_req <= '1';
lsu_we <= '0';
stack_a_enable <= '0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
stack_b_enable <= not lsu_busy;
if lsu_busy='0' then
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Loadh then
exu_busy<='1';
w.state:=State_Loadh;
end if;
else
wroteback := '0';
end if;
end if;
when Decoded_PopSP =>
decode_load_sp <= '1';
instruction_executed := '0';
stack_a_addr <= std_logic_vector(exr.tos(spMaxBit downto 2));
w.state := State_Resync2;
--when Decoded_Break =>
-- w.break := '1';
when Decoded_Neqbranch =>
instruction_executed := '0';
w.state := State_NeqBranch;
when others =>
end case;
else -- freeze_all
--
-- Freeze the entire pipeline.
--
exu_busy<='1';
stack_a_enable<='0';
stack_b_enable<='0';
stack_a_addr <= (others => DontCareValue);
stack_a_write <= (others => DontCareValue);
end if;
end if; -- valid
when State_Ashiftleft =>
exu_busy <= '1';
lshifter_enable <= '1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_Mult =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(31 downto 0));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_MultF16 =>
exu_busy <= '1';
lshifter_enable <= '1';
lshifter_multorshift <='1';
w.tos := unsigned(lshifter_output(47 downto 16));
if lshifter_done='1' then
exu_busy<='0';
w.state := State_Execute;
end if;
when State_WaitSPB =>
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Loadb =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1 downto 0) is
when "11" =>
w.tos(7 downto 0) := unsigned(exr.tos(7 downto 0));
when "10" =>
w.tos(7 downto 0) := unsigned(exr.tos(15 downto 8));
when "01" =>
w.tos(7 downto 0) := unsigned(exr.tos(23 downto 16));
when "00" =>
w.tos(7 downto 0) := unsigned(exr.tos(31 downto 24));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_Loadh =>
w.tos(wordSize-1 downto 8) := (others => '0');
case exr.tos_save(1) is
when '1' =>
w.tos(15 downto 0) := unsigned(exr.tos(15 downto 0));
when '0' =>
w.tos(15 downto 0) := unsigned(exr.tos(31 downto 16));
when others =>
null;
end case;
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
when State_LoadStack =>
w.tos := unsigned(stack_a_read);
if prefr.decodedOpcode=Decoded_Loadb then
exu_busy<='1';
w.state:=State_Loadb;
elsif prefr.decodedOpcode=Decoded_Loadh then
exu_busy<='1';
w.state:=State_Loadh;
else
instruction_executed:='1';
wroteback := '0';
w.state := State_Execute;
end if;
when State_NeqBranch =>
if exr.nos_save/=0 then
decode_jump <= '1';
jump_address <= exr.tos(maxAddrBit downto 0) + prefr.pc;
poppc_inst <= '1';
exu_busy <= '0';
else
exu_busy <='1';
end if;
instruction_executed := '0';
stack_a_addr <= std_logic_vector(prefr.spnext);
wroteback:='0';
w.state := State_Resync2;
when others =>
null;
end case;
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
exr.state <= State_Execute;
exr.idim <= DontCareValue;
exr.inInterrupt <= '0';
exr.break <= '0';
exr.wb_cyc <= '0';
exr.wb_stb <= '1';
wroteback_q <= '0';
else
exr <= w;
-- TODO: move wroteback_q into EXU regs
wroteback_q <= wroteback;
if exr.break='1' then
report "BREAK" severity failure;
end if;
-- Some sanity checks, to be caught in simulation
if prefr.valid='1' then
if prefr.tosSource=Tos_Source_Idim0 and prefr.idim='1' then
report "Invalid IDIM flag 0" severity error;
end if;
if prefr.tosSource=Tos_Source_IdimN and prefr.idim='0' then
report "Invalid IDIM flag 1" severity error;
end if;
end if;
end if;
end if;
end process;
single_step <= dbg_in.step;
dbg_out.valid <= '1' when prefr.valid='1' else '0';
-- Let pipeline finish
dbg_out.ready <= '1' when exr.state=state_execute
and decode_load_sp='0'
and decode_jump='0'
and decr.state = State_Inject
--and jump_q='0'
else '0';
end behave;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package local_adaptations_pkg is
-------------------------------------------------------------------------------
-- Constants for this VIP
-------------------------------------------------------------------------------
-- This constant can be smaller than C_MAX_VVC_INSTANCE_NUM but not bigger.
constant C_AVALON_ST_MAX_VVC_INSTANCE_NUM : natural := C_MAX_VVC_INSTANCE_NUM;
constant C_AVALON_ST_CHANNEL_MAX_LENGTH : natural := 8;
constant C_AVALON_ST_WORD_MAX_LENGTH : natural := 512;
constant C_AVALON_ST_DATA_MAX_WORDS : natural := 1024;
end package local_adaptations_pkg;
package body local_adaptations_pkg is
end package body local_adaptations_pkg; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sign_computer_tb is
end entity;
architecture sign_computer_tb_arq of sign_computer_tb is
signal man_1_in: std_logic_vector(15 downto 0) := (others => '0');
signal man_2_in: std_logic_vector(15 downto 0) := (others => '0');
signal sign_1_in: std_logic := '0';
signal sign_2_in: std_logic := '0';
signal man_greater_in: std_logic_vector(15 downto 0) := (others => '0');
signal pre_complemented_result: std_logic_vector(16 downto 0) := (others => '0');
signal complemented_result: std_logic_vector(16 downto 0) := (others => '0');
signal sign_out: std_logic := '0';
component sign_computer is
generic(
BITS : natural := 16
);
port(
man_1_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
man_2_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
sign_1_in: in std_logic := '0';
sign_2_in: in std_logic := '0';
man_greater_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
pre_complemented_result: in std_logic_vector(BITS downto 0) := (others => '0');
complemented_result: in std_logic_vector(BITS downto 0) := (others => '0');
sign_out: out std_logic := '0'
);
end component;
for sign_computer_0 : sign_computer use entity work.sign_computer;
begin
sign_computer_0 : sign_computer
generic map(BITS => 16)
port map(
man_1_in => man_1_in,
man_2_in => man_2_in,
sign_1_in => sign_1_in,
sign_2_in => sign_2_in,
man_greater_in => man_greater_in,
pre_complemented_result => pre_complemented_result,
complemented_result => complemented_result,
sign_out => sign_out
);
process
type pattern_type is record
m1 : std_logic_vector(15 downto 0);
m2 : std_logic_vector(15 downto 0);
s1 : std_logic;
s2 : std_logic;
mg : std_logic_vector(15 downto 0);
pcr : std_logic_vector(16 downto 0);
cr : std_logic_vector(16 downto 0);
so : std_logic;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("0000000000000000","0000000000000000",'0','0',"0000000000000000","00000000000000000","00000000000000000",'0'),
("0000000000000000","0000000000000000",'1','1',"0000000000000000","00000000000000000","00000000000000000",'1'),
("0000000000000000","1111111111111111",'0','1',"1111111111111111","00000000000000000","00000000000000000",'1'),
("0000000000000000","1111111111111111",'1','0',"1111111111111111","00000000000000000","00000000000000000",'0'),
("0000000000000000","1111111111111111",'0','1',"0000000000000000","00000000000000000","00000000000000000",'0'),
("0000000000000000","1111111111111111",'1','0',"0000000000000000","00000000000000000","00000000000000000",'1'),
("0000000000000000","1111111111111111",'0','1',"0000000000000000","00000000000000000","00000000000000000",'0'),
("0000000000000000","1111111111111111",'1','0',"0000000000000000","00000000000000000","00000000000000000",'1')
);
begin
for i in patterns'range loop
-- Set the inputs.
man_1_in <= patterns(i).m1;
man_2_in <= patterns(i).m2;
sign_1_in <= patterns(i).s1;
sign_2_in <= patterns(i).s2;
man_greater_in <= patterns(i).mg;
pre_complemented_result <= patterns(i).pcr;
complemented_result <= patterns(i).cr;
wait for 1 ms;
assert patterns(i).so = sign_out report "BAD RESULT, GOT: " & std_logic'image(sign_out);
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: pad_xilinx_gen
-- File: pad_xilinx_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Xilinx pads wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUF;
-- pragma translate_on
entity unisim_inpad is
generic (level : integer := 0; voltage : integer := x33v);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of unisim_inpad is
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUF : component is true;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
end generate;
cmos_25 : if voltage = x25v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
end generate;
cmos_18 : if voltage = x18v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS18") port map (O => o, I => pad);
end generate;
cmos_15 : if voltage = x15v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS15") port map (O => o, I => pad);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
ip : IBUF generic map (IOSTANDARD => "SSTL2_I") port map (O => o, I => pad);
end generate;
sstl2y : if level = sstl2_ii generate
ip : IBUF generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos)
and (level /= sstl2_i)and (level /= sstl2_ii) generate
ip : IBUF port map (O => o, I => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IOBUF;
-- pragma translate_on
entity unisim_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of unisim_iopad is
component IOBUF generic (
DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IOBUF : component is true;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : IOBUF generic map (IOSTANDARD => "PCI33_5")
port map (O => o, IO => pad, I => i, T => en);
end generate;
pci_3 : if voltage /= x50v generate
op : IOBUF generic map (IOSTANDARD => "PCI33_3")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos_25 : if voltage = x25v generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS25")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS25", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos_18 : if voltage = x18v generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS18")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS18", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos_15 : if voltage = x15v generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS15")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS15", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl2y : if level = sstl2_ii generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl18i : if level = sstl18_i generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl18ii : if level = sstl18_ii generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => o, IO => pad, I => i, T => en);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and (level /= sstl18_i) and (level /= sstl18_ii) generate
op : IOBUF port map (O => o, IO => pad, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUF;
-- pragma translate_on
entity unisim_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of unisim_outpad is
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of OBUF : component is true;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => i);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => i);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos0 : if level = cmos generate
cmos_3: if voltage = x33v generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos_25: if voltage = x25v generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS25")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS25", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos_18: if voltage = x18v generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS18")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS18", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos_15: if voltage = x15v generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS15")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS15", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => pad, I => i);
end generate;
sstl2y : if level = sstl2_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => pad, I => i);
end generate;
sstl18i : if level = sstl18_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => pad, I => i);
end generate;
sstl18ii : if level = sstl18_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => pad, I => i);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and
(level /= sstl18_i) and (level /= sstl18_ii) generate
op : OBUF port map (O => pad, I => i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFT;
-- pragma translate_on
entity unisim_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12);
port (pad : out std_ulogic; i, en : in std_ulogic);
end ;
architecture rtl of unisim_toutpad is
component OBUFT generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I, T : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of OBUFT : component is true;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => i, T => en);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => i, T => en);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
cmos_25 : if voltage = x25v generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS25")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS25", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
cmos_18 : if voltage = x18v generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS18")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS18", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
op : OBUFT port map (O => pad, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUF;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
entity unisim_skew_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end ;
architecture rtl of unisim_skew_outpad is
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal reset, clk0, clk0b, gnd, vcc : std_ulogic;
attribute syn_noprune : boolean;
attribute syn_noprune of OBUF : component is true;
begin
gnd <= '0'; vcc <= '1';
reset <= not rst;
dll0 : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => skew)
port map ( CLKIN => i, CLKFB => clk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => reset, CLK0 => clk0);
bufg0 : BUFG port map (I => clk0, O => clk0b);
o <= clk0b; -- output before pad
--x0 : unisim_outpad generic map (level, slew, voltage, strength) port map (pad, clk0b);
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => clk0b);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => clk0b);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => clk0b);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => clk0b);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => clk0b);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => clk0b);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => pad, I => clk0b);
end generate;
sstl2y : if level = sstl2_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => pad, I => clk0b);
end generate;
sstl18i : if level = sstl18_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => pad, I => clk0b);
end generate;
sstl18ii : if level = sstl18_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => pad, I => clk0b);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and
(level /= sstl18_i) and (level /= sstl18_ii) generate
op : OBUF port map (O => pad, I => clk0b);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFG;
use unisim.IBUF;
use unisim.BUFGMUX;
use unisim.BUFG;
-- pragma translate_on
entity unisim_clkpad is
generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0;
tech : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1'; lock : out std_ulogic);
end;
architecture rtl of unisim_clkpad is
component IBUFG generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end component;
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFR port (O : out std_logic; I, CE, CLR : in std_logic); end component;
component CLKDLL port ( CLK0 : out std_ulogic; CLK180 : out std_ulogic; CLK270 : out std_ulogic;
CLK2X : out std_ulogic; CLK90 : out std_ulogic; CLKDV : out std_ulogic;
LOCKED : out std_ulogic; CLKFB : in std_ulogic; CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component CLKDLLHF port ( CLK0 : out std_ulogic; CLK180 : out std_ulogic; CLKDV : out std_ulogic;
LOCKED : out std_ulogic; CLKFB : in std_ulogic; CLKIN : in std_ulogic; RST : in std_ulogic);
end component;
component DCM_SP
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK2X180 : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
CLKFX : out std_ulogic := '0';
CLKFX180 : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
STATUS : out std_logic_vector(7 downto 0) := "00000000";
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
DSSEN : in std_ulogic := '0';
PSCLK : in std_ulogic := '0';
PSEN : in std_ulogic := '0';
PSINCDEC : in std_ulogic := '0';
RST : in std_ulogic := '0');
end component;
signal gnd, ol, ol2, ol3 : std_ulogic;
signal rst : std_ulogic;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUFG : component is true;
attribute syn_noprune of IBUF : component is true;
begin
gnd <= '0'; rst <= not rstn;
g0 : if arch = 0 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
end generate;
cmos_25 : if voltage = x25v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
end generate;
cmos_18 : if voltage = x18v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS18") port map (O => o, I => pad);
end generate;
end generate;
sstl2 : if level = sstl2_ii generate
ip : IBUFG generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and (level /= sstl2_ii) generate
ip : IBUFG port map (O => o, I => pad);
end generate;
lock <= '1';
end generate;
g1 : if arch = 1 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
cmos0 : if level = cmos generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
ip : IBUF port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
lock <= '1';
end generate;
g2 : if arch = 2 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
cmos_25 : if voltage = x25v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS25") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
cmos_18 : if voltage = x18v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS18") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
ip : IBUFG port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
lock <= '1';
end generate;
g3 : if arch = 3 generate
ip : IBUFG port map (O => ol, I => pad);
sp6 : if tech = spartan6 generate
dll: DCM_SP
generic map (CLK_FEEDBACK => "1X")
port map (
CLK0 => ol2,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
LOCKED => lock,
PSDONE => open,
STATUS => open,
CLKFB => ol3,
CLKIN => ol,
DSSEN => gnd,
PSCLK => gnd,
PSEN => gnd,
PSINCDEC => gnd,
RST => rst);
end generate;
nsp6 : if tech /= spartan6 generate
hf0 : if hf = 0 generate
dll: CLKDLL port map(
CLK0 => ol2,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK90 => open,
CLKDV => open,
LOCKED => lock,
CLKFB => ol3,
CLKIN => ol,
RST => rst);
end generate;
hf1 : if hf = 1 generate
dll : CLKDLLHF
port map(
CLK0 => ol2,
CLK180 => open,
CLKDV => open,
LOCKED => lock,
CLKFB => ol3,
CLKIN => ol,
RST => rst);
end generate;
end generate;
bf : BUFG port map (O => ol3, I => ol2);
o <= ol3;
end generate g3;
g4 : if arch = 4 generate
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFR port map (O => o, I => ol, CE => '0', CLR => '0');
end generate;
cmos_25 : if voltage /= x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS25") port map (O => ol, I => pad);
bf : BUFR port map (O => o, I => ol, CE => '0', CLR => '0');
end generate;
end generate;
gen0 : if (level /= cmos) generate
ip : IBUF port map (O => ol, I => pad);
bf : BUFR port map (O => o, I => ol, CE => '0', CLR => '0');
end generate;
lock <= '1';
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFDS_LVDS_25;
use unisim.IBUFDS_LVDS_33;
-- pragma translate_on
entity unisim_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of unisim_inpad_ds is
component IBUFDS_LVDS_25
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFDS_LVDS_33
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFDS_LVDS_33 port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFDS_LVDS_25 port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFGDS;
use unisim.IBUFGDS_LVDS_25;
use unisim.IBUFGDS_LVDS_33;
-- pragma translate_on
entity unisim_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of unisim_clkpad_ds is
component IBUFGDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_25
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_33
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUFGDS_LVDS_25 : component is true;
attribute syn_noprune of IBUFGDS_LVDS_33 : component is true;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFGDS_LVDS_33 port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage = x25v generate
ip : IBUFGDS_LVDS_25 port map (O => o, I => padp, IB => padn);
end generate;
end generate;
xsstl : if level = sstl generate
sstl_18 : if voltage = x18v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"DIFF_SSTL18")
port map (O => o, I => padp, IB => padn);
end generate;
sstl_15 : if voltage = x15v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"DIFF_SSTL15")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if ((level /= lvds) and (level /= sstl)) generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFDS;
-- pragma translate_on
entity virtex4_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex4_inpad_ds is
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUFDS : component is true;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFGDS;
-- pragma translate_on
entity virtex4_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex4_clkpad_ds is
component IBUFGDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IBUFGDS : component is true;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage = x25v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IOBUFDS;
-- pragma translate_on
entity unisim_iopad_ds is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of unisim_iopad_ds is
component IOBUFDS generic (
CAPACITANCE : string := "DONT_CARE"; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT"; IFD_DELAY_VALUE : string := "AUTO");
port (O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic); end component;
attribute syn_noprune : boolean;
attribute syn_noprune of IOBUFDS : component is true;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
iop : IOBUFDS generic map (IOSTANDARD => "LVDS_33")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
lvds_25 : if voltage /= x33v generate
iop : IOBUFDS generic map (IOSTANDARD => "LVDS_25")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
end generate;
xsstl18_i : if level = sstl18_i generate
iop : IOBUFDS generic map (IOSTANDARD => "DIFF_SSTL18_I")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
xsstl18_ii : if level = sstl18_ii generate
iop : IOBUFDS generic map (IOSTANDARD => "DIFF_SSTL18_II")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
default : if (level /= lvds) and (level /= sstl18_i) and (level /= sstl18_ii) generate
iop : IOBUFDS generic map (IOSTANDARD => "DEFAULT")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFDS;
-- pragma translate_on
entity unisim_outpad_ds is
generic (level : integer := lvds; slew : integer := 0; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of unisim_outpad_ds is
component OBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT";
SLEW : string := "SLOW"
);
port(
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of OBUFDS : component is true;
begin
slow : if slew = 0 generate
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_33")
port map (O => padp, OB => padn, I => i);
end generate;
lvds_25 : if voltage /= x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_25")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
xsstl2_i : if level = sstl2_i generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL2_I")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl2_ii : if level = sstl2_ii generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL2_II")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_i : if level = sstl18_i generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL18_I")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_ii : if level = sstl18_ii generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL18_II")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
fast : if slew = 1 generate
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_33", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
lvds_25 : if voltage /= x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_25", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
xsstl2_i : if level = sstl2_i generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL2_I", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl2_ii : if level = sstl2_ii generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL2_II", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_i : if level = sstl18_i generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL18_I", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_ii : if level = sstl18_ii generate
op : OBUFDS generic map(IOSTANDARD => "DIFF_SSTL18_II", SLEW => "FAST")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
end;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY AxiReaderCore IS
PORT(
arRd : IN STD_LOGIC;
arVld : IN STD_LOGIC;
rRd : IN STD_LOGIC;
rVld : IN STD_LOGIC;
r_idle : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AxiReaderCore IS
TYPE rSt_t IS (rdIdle, rdData);
SIGNAL rSt : rst_t;
BEGIN
assig_process_rSt: PROCESS(arRd, arVld, rRd, rVld)
BEGIN
IF arRd = '1' THEN
IF arVld = '1' THEN
rSt <= rddata;
ELSE
rSt <= rdidle;
END IF;
ELSIF (rRd AND rVld) = '1' THEN
rSt <= rdidle;
ELSE
rSt <= rddata;
END IF;
END PROCESS;
r_idle <= '1' WHEN (rSt = rdidle) ELSE '0';
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
entity MyInv is
port ( a_inv : in std_ulogic;
x_inv : out std_ulogic);
end MyInv;
architecture A of MyInv is
begin
x_inv <= not a_inv;
end architecture A;
|
-- CODIFICADOR 7 SEGMENTOS
-- Librerias necesarias
library ieee;
use ieee.std_logic_1164.all;
ENTITY codificador7Segmentos IS
PORT (
entrada : IN INTEGER RANGE 0 TO 9;
salida : OUT STD_lOGIC_VECTOR (6 DOWNTO 0)
);
END codificador7Segmentos;
ARCHITECTURE arquitecturaCodificador7Segmentos OF codificador7Segmentos IS
BEGIN
codificacion : PROCESS (entrada)
BEGIN
CASE entrada IS
WHEN 0 => salida <= "0000001";
WHEN 1 => salida <= "1001111";
WHEN 2 => salida <= "0010010";
WHEN 3 => salida <= "0000110";
WHEN 4 => salida <= "1001100";
WHEN 5 => salida <= "0100100";
WHEN 6 => salida <= "1100000";
WHEN 7 => salida <= "0001111";
WHEN 8 => salida <= "0000000";
WHEN 9 => salida <= "0001100";
END CASE;
END PROCESS codificacion;
END arquitecturaCodificador7Segmentos; |
-- CODIFICADOR 7 SEGMENTOS
-- Librerias necesarias
library ieee;
use ieee.std_logic_1164.all;
ENTITY codificador7Segmentos IS
PORT (
entrada : IN INTEGER RANGE 0 TO 9;
salida : OUT STD_lOGIC_VECTOR (6 DOWNTO 0)
);
END codificador7Segmentos;
ARCHITECTURE arquitecturaCodificador7Segmentos OF codificador7Segmentos IS
BEGIN
codificacion : PROCESS (entrada)
BEGIN
CASE entrada IS
WHEN 0 => salida <= "0000001";
WHEN 1 => salida <= "1001111";
WHEN 2 => salida <= "0010010";
WHEN 3 => salida <= "0000110";
WHEN 4 => salida <= "1001100";
WHEN 5 => salida <= "0100100";
WHEN 6 => salida <= "1100000";
WHEN 7 => salida <= "0001111";
WHEN 8 => salida <= "0000000";
WHEN 9 => salida <= "0001100";
END CASE;
END PROCESS codificacion;
END arquitecturaCodificador7Segmentos; |
-- CODIFICADOR 7 SEGMENTOS
-- Librerias necesarias
library ieee;
use ieee.std_logic_1164.all;
ENTITY codificador7Segmentos IS
PORT (
entrada : IN INTEGER RANGE 0 TO 9;
salida : OUT STD_lOGIC_VECTOR (6 DOWNTO 0)
);
END codificador7Segmentos;
ARCHITECTURE arquitecturaCodificador7Segmentos OF codificador7Segmentos IS
BEGIN
codificacion : PROCESS (entrada)
BEGIN
CASE entrada IS
WHEN 0 => salida <= "0000001";
WHEN 1 => salida <= "1001111";
WHEN 2 => salida <= "0010010";
WHEN 3 => salida <= "0000110";
WHEN 4 => salida <= "1001100";
WHEN 5 => salida <= "0100100";
WHEN 6 => salida <= "1100000";
WHEN 7 => salida <= "0001111";
WHEN 8 => salida <= "0000000";
WHEN 9 => salida <= "0001100";
END CASE;
END PROCESS codificacion;
END arquitecturaCodificador7Segmentos; |
-- CODIFICADOR 7 SEGMENTOS
-- Librerias necesarias
library ieee;
use ieee.std_logic_1164.all;
ENTITY codificador7Segmentos IS
PORT (
entrada : IN INTEGER RANGE 0 TO 9;
salida : OUT STD_lOGIC_VECTOR (6 DOWNTO 0)
);
END codificador7Segmentos;
ARCHITECTURE arquitecturaCodificador7Segmentos OF codificador7Segmentos IS
BEGIN
codificacion : PROCESS (entrada)
BEGIN
CASE entrada IS
WHEN 0 => salida <= "0000001";
WHEN 1 => salida <= "1001111";
WHEN 2 => salida <= "0010010";
WHEN 3 => salida <= "0000110";
WHEN 4 => salida <= "1001100";
WHEN 5 => salida <= "0100100";
WHEN 6 => salida <= "1100000";
WHEN 7 => salida <= "0001111";
WHEN 8 => salida <= "0000000";
WHEN 9 => salida <= "0001100";
END CASE;
END PROCESS codificacion;
END arquitecturaCodificador7Segmentos; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:43:36 11/19/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282_19.11.2013/My_32bit2x1Mux_tb_948282.vhd
-- Project Name: Mips32_948282_19.11.2013
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: My_32bit2x1Mux_948282
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY My_32bit2x1Mux_tb_948282 IS
END My_32bit2x1Mux_tb_948282;
ARCHITECTURE behavior OF My_32bit2x1Mux_tb_948282 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT My_32bit2x1Mux_948282
PORT(
B_inv : IN std_logic;
B : IN std_logic_vector(31 downto 0);
B_comp : IN std_logic_vector(31 downto 0);
B_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal B_inv : std_logic := '0';
signal B : std_logic_vector(31 downto 0) := (others => '0');
signal B_comp : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal B_out : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: My_32bit2x1Mux_948282 PORT MAP (
B_inv => B_inv,
B => B,
B_comp => B_comp,
B_out => B_out
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
B_inv<='1';
B<="11111111111111111111111111111111";
B_comp<="00000000000000000000000000000000";
wait for 100 ns;
wait;
end process;
END;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_generator_v9_3_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_generator_v9_3_pkg.ALL;
ENTITY fifo_generator_v9_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fifo_generator_v9_3_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc734.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x00p05n01i00734ent_a is
generic (
constant gc1 : integer;
variable gc2 : natural;
signal gc3 : positive
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x00p05n01i00734ent_a;
architecture arch of c01s01b01x00p05n01i00734ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
ENTITY c01s01b01x00p05n01i00734ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x00p05n01i00734ent;
ARCHITECTURE c01s01b01x00p05n01i00734arch OF c01s01b01x00p05n01i00734ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : natural;
constant dgc3 : positive
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x00p05n01i00734ent_a
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
generic map (3,3,3)
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p05n01i00734 - The generic list in the formal generic clause defines generic constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p05n01i00734arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc734.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x00p05n01i00734ent_a is
generic (
constant gc1 : integer;
variable gc2 : natural;
signal gc3 : positive
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x00p05n01i00734ent_a;
architecture arch of c01s01b01x00p05n01i00734ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
ENTITY c01s01b01x00p05n01i00734ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x00p05n01i00734ent;
ARCHITECTURE c01s01b01x00p05n01i00734arch OF c01s01b01x00p05n01i00734ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : natural;
constant dgc3 : positive
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x00p05n01i00734ent_a
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
generic map (3,3,3)
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p05n01i00734 - The generic list in the formal generic clause defines generic constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p05n01i00734arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc734.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x00p05n01i00734ent_a is
generic (
constant gc1 : integer;
variable gc2 : natural;
signal gc3 : positive
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x00p05n01i00734ent_a;
architecture arch of c01s01b01x00p05n01i00734ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
ENTITY c01s01b01x00p05n01i00734ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x00p05n01i00734ent;
ARCHITECTURE c01s01b01x00p05n01i00734arch OF c01s01b01x00p05n01i00734ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : natural;
constant dgc3 : positive
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x00p05n01i00734ent_a
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
generic map (3,3,3)
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p05n01i00734 - The generic list in the formal generic clause defines generic constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p05n01i00734arch;
|
-- NEED RESULT: ARCH00108.P1: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00108.P2: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00108.P3: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00108: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00108: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00108: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00108: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00108: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00108: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00108
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00108)
-- ENT00108_Test_Bench(ARCH00108_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00108 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(highb).f2 after 10 ns,
c_st_rec1_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00108.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(highb).f2 after 10 ns ,
c_st_rec1_vector_1(highb).f2 after 20 ns ,
c_st_rec1_vector_2(highb).f2 after 30 ns ,
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00108" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00108" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00108" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_rec2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(highb).f2 after 10 ns,
c_st_rec2_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00108.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(highb).f2 after 10 ns ,
c_st_rec2_vector_1(highb).f2 after 20 ns ,
c_st_rec2_vector_2(highb).f2 after 30 ns ,
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00108" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00108" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00108" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_rec3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_2(highb).f2 after 10 ns,
c_st_rec3_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00108.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_2(highb).f2 after 10 ns ,
c_st_rec3_vector_1(highb).f2 after 20 ns ,
c_st_rec3_vector_2(highb).f2 after 30 ns ,
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00108" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00108" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00108" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P3 ;
--
--
end ARCH00108 ;
--
entity ENT00108_Test_Bench is
end ENT00108_Test_Bench ;
--
architecture ARCH00108_Test_Bench of ENT00108_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00108 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00108_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1183.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p02n01i01183ent IS
END c08s01b00x00p02n01i01183ent;
ARCHITECTURE c08s01b00x00p02n01i01183arch OF c08s01b00x00p02n01i01183ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
assert FALSE
report "***PASSED TEST: c08s01b00x00p02n01i01183"
severity NOTE;
wait;
assert FALSE
report "***FAILED TEST: c08s01b00x00p02n01i01183 - A wait statement with no argument"
severity ERROR;
END PROCESS TESTING;
END c08s01b00x00p02n01i01183arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1183.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p02n01i01183ent IS
END c08s01b00x00p02n01i01183ent;
ARCHITECTURE c08s01b00x00p02n01i01183arch OF c08s01b00x00p02n01i01183ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
assert FALSE
report "***PASSED TEST: c08s01b00x00p02n01i01183"
severity NOTE;
wait;
assert FALSE
report "***FAILED TEST: c08s01b00x00p02n01i01183 - A wait statement with no argument"
severity ERROR;
END PROCESS TESTING;
END c08s01b00x00p02n01i01183arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1183.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p02n01i01183ent IS
END c08s01b00x00p02n01i01183ent;
ARCHITECTURE c08s01b00x00p02n01i01183arch OF c08s01b00x00p02n01i01183ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
assert FALSE
report "***PASSED TEST: c08s01b00x00p02n01i01183"
severity NOTE;
wait;
assert FALSE
report "***FAILED TEST: c08s01b00x00p02n01i01183 - A wait statement with no argument"
severity ERROR;
END PROCESS TESTING;
END c08s01b00x00p02n01i01183arch;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 23/06/2015
--! Module Name: upstreamEpathFifoWrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.all;
--! EPATH FIFO 18 bit wide, 1K deep
entity upstreamEpathFifoWrap is
port (
rst : in std_logic;
fifoFLUSH : in std_logic;
---
wr_clk : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(17 downto 0);
---
rd_clk : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(9 downto 0);
doutRdy : out std_logic;
---
full : out std_logic;
empty : out std_logic;
prog_full : out std_logic
);
end upstreamEpathFifoWrap;
architecture Behavioral of upstreamEpathFifoWrap is
----------------------------------
----------------------------------
component fh_epath_fifo2K_18bit_wide -- IP
port (
wr_clk : in std_logic;
wr_rst : in std_logic;
rd_clk : in std_logic;
rd_rst : in std_logic;
din : in std_logic_vector(17 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(9 downto 0);
prog_full_thresh_negate : in std_logic_vector(9 downto 0);
dout : out std_logic_vector(17 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
prog_full : out std_logic
);
end component;
----------------------------------
----------------------------------
signal rd_en_s, empty_efifo, prog_full_s : std_logic;
signal OE, rst_state, byte_cnt,byte_mux_sel,byte_rdy,rd_en1,rd_en2 : std_logic := '0';
signal dout18bit : std_logic_vector(17 downto 0);
signal byte0, byte1 : std_logic_vector(9 downto 0) := "1100000000";
constant comma_byte : std_logic_vector(9 downto 0) := "1100000000";
signal byte0_code,byte1_code,word16_code : std_logic_vector(1 downto 0);
signal empty_efifo1,empty_efifo2,empty_efifo3 : std_logic;
signal wr_en_r : std_logic := '0';
signal din_r : std_logic_vector(17 downto 0) := "110000000000000000";
begin
-------------------------------------------------------------------------------------------
-- write pipeline
-------------------------------------------------------------------------------------------
process(wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
wr_en_r <= wr_en;
din_r <= din;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- FIFO - ip
-------------------------------------------------------------------------------------------
epathFIFO: fh_epath_fifo2K_18bit_wide
port map(
wr_clk => wr_clk,
wr_rst => fifoFLUSH,
rd_clk => rd_clk,
rd_rst => fifoFLUSH,
din => din_r,
wr_en => wr_en_r,
rd_en => rd_en_s,
dout => dout18bit, --18 bit
full => full,
almost_full => open, --almost_full,
empty => empty_efifo,
prog_full => prog_full_s, -- 1008/960 from 1024
prog_full_thresh_assert => std_logic_vector(to_unsigned(990, 10)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(980, 10))
);
--
-------------------------------------------------------------------------------------------
-- re pulse
-------------------------------------------------------------------------------------------
process(rd_clk,rst)
begin
if rst = '1' then
byte_cnt <= '0';
elsif rd_clk'event and rd_clk = '1' then
if rd_en = '1' then -- 1 clk trigger
byte_cnt <= not byte_cnt;
end if;
end if;
end process;
--
rd_en_s <= rd_en and (not byte_cnt) and (not empty_efifo); -- only when byte_cnt = 0
--
word16_code <= dout18bit(17 downto 16);
--
process(word16_code,empty_efifo1)
begin
if empty_efifo1 = '1' then
byte0_code <= "11";
byte1_code <= "11";
else
if word16_code = "10" then -- start of message
byte0_code <= "11";
byte1_code <= "10";
elsif word16_code = "01" then -- end of message
byte0_code <= "01";
byte1_code <= "11";
else -- "00" data
byte0_code <= empty_efifo1 & empty_efifo1;
byte1_code <= empty_efifo2 & empty_efifo2;
end if;
end if;
end process;
--
byte0 <= byte0_code & dout18bit(15 downto 8);
byte1 <= byte1_code & dout18bit(7 downto 0);
--
process(byte_cnt,byte0,byte1)
begin
if byte_cnt = '1' then
dout <= byte0;
else
dout <= byte1;
end if;
end process;
--
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
byte_rdy <= byte_cnt;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- re pulse
-------------------------------------------------------------------------------------------
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
doutRdy <= rd_en;
empty_efifo1 <= empty_efifo;
empty_efifo2 <= empty_efifo1;
empty_efifo3 <= empty_efifo2;
end if;
end process;
--
empty <= empty_efifo;-- rd_clk domain
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
rst_state <= rst or fifoFLUSH;
OE <= not rst_state;
end if;
end process;
--
prog_full <= prog_full_s and OE;
--
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity ent;
architecture arch of ent is
constant test: natural := 3;
begin
LL: if test=10 generate
begin
end;
elsif test=5 generate
begin
end;
end generate;
end architecture arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity ent;
architecture arch of ent is
constant test: natural := 3;
begin
LL: if test=10 generate
begin
end;
elsif test=5 generate
begin
end;
end generate;
end architecture arch;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
entity InstMem is
generic (BitWidth: integer;
InstructionWidth: integer);
port ( address : in std_logic_vector(BitWidth-1 downto 0);
data : out std_logic_vector(InstructionWidth-1 downto 0) );
end entity InstMem;
architecture behavioral of InstMem is
type mem is array ( 0 to InstMem_depth-1) of std_logic_vector(InstructionWidth-1 downto 0);
constant my_InstMem : mem := (
0 => "10000100000000000000000000000000011000",--Load_B_Dir
1 => "00111100000000000000000000000000000000",--OR_A_B
2 => "00011000000000000000000000000000000000",--IncA
3 => "00001100000000000000000000000000000000",--Sub_A_B
4 => "01011000000000000000000000000000000111",--JmpC 7
5 => "11111000000000000000000000000011110000",--NOP
6 => "11111000000000000000000000000000000000",--NOP
7 => "00110000000000000000000000000000000000",--RRC
8 => "00110100000000000000000000000000000000",--RLC
9 => "11111000000000000000000000000000000000",--NOP
10 => "01101100000000000000000000000000000000",--ClearC
11 => "10000000000000000000000000000000010000",--Store_A_Mem
12 => "11110000000000000000000000000000000000",--PUSH
13 => "01111000000000000000000000000000000000",--SavePC
14 => "11110000000000000000000000000000000000",--PUSH
15 => "01001100000000000000000000000000010100",--Jmp 20
16 => "11110100000000000000000000000000000000", --pop
17 => "00100100000000000000000000000000000000", --ShiftArithL
18 => "00011100000000000000000000000000000000",--DecA
19 => "11111100000000000000000000000000000000", --HALT
20 => "01111100000000000000000000000000010000",--Load_A_Mem
21 => "00111000000000000000000000000000000000",--AND
22 => "01010000000000000000000000000000011000",--JMPZ 24
23 => "11111000000000000000000000000000000000",--NOP
24 => "01101100000000000000000000000000000000",--ClearZ
25 => "00000100000000000000000000000000010000",--Add_A_Mem
26 => "00010000000000000000000000000000010000",--Sub_A_Mem
27 => "00000000000000000000000000000000000000",--ADD_A_B
28 => "00010100000000000000000000000000001100",--SUB_A_DIR C
29 => "01000100000000000000000000000000000000",--FlipA
30 => "01000000000000000000000000000000000000",--XOR_A_B
31 => "01001000000000000000000000000000000000",--NegA
32 => "00100000000000000000000000000000000000",--ShiftArithR
33 => "00101100000000000000000000000000000000",--ShiftA_L
34 => "00101000000000000000000000000000000000",--ShiftA_R
35 => "01110000000000000000000000000000000000",--ClearACC
36 => "11110100000000000000000000000000000000",--POP
37 => "00001000000000000000000000000000000011",--Add_A_Dir
38 => "01110100000000000000000000000000000000",--LoadPC
others => "00000000000000000000000000000000000000"
);
begin
process(address)begin
if to_integer(unsigned(address)) <= InstMem_depth-1 then
data <= my_InstMem(to_integer(unsigned(address)));
else
data <= (others => '0');
end if;
end process;
end architecture behavioral;
|
-- file: hex2disp.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- Solution to MC613 - Lab0X.QY.Z
--
-- A binary to 7seg display decoder (hexdecimal - from 0 to f).
library ieee ;
use ieee.std_logic_1164.all ;
entity hex2disp is
port ( num : in std_logic_vector(3 downto 0) ; -- Input value
led : out std_logic_vector(0 to 6) -- 7seg led display signal
) ;
end hex2disp ;
architecture arch of hex2disp is
begin
with num select
-- "abcdefg"
led <= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010",
"1100000" when "1011",
"0110001" when "1100",
"1000010" when "1101",
"0110000" when "1110",
"0111000" when others ;
end arch ;
|
library ieee;
use ieee.std_logic_1164.all;
entity Adder_2x16 is
port (
isSubtraction: in STD_LOGIC;
input_A, input_B: in STD_LOGIC_VECTOR(15 DOWNTO 0);
carry_out: out STD_LOGIC;
output: out STD_LOGIC_VECTOR(15 DOWNTO 0));
end Adder_2x16;
architecture skeleton of Adder_2x16 is
begin
process(input_A, input_B, isSubtraction)
variable sum, bOrNotb : STD_LOGIC_VECTOR(15 downto 0);
variable carry : STD_LOGIC;
begin
if (isSubtraction = '1') then
bOrNotb := NOT input_B;
else
bOrNotb := input_B;
end if;
carry := isSubtraction;
for i in 0 to 15 loop
sum(i) := input_A(i) xor bOrNotb(i) xor carry;
carry := (input_A(i) and bOrNotb(i)) or ((input_A(i) xor bOrNotb(i)) and carry);
end loop;
carry_out <= carry;
output <= sum;
end process;
end skeleton; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3170.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p17n01i03170ent IS
END c14s01b00x00p17n01i03170ent;
ARCHITECTURE c14s01b00x00p17n01i03170arch OF c14s01b00x00p17n01i03170ent IS
constant L : REAL := -10.0;
constant R : REAL := 10.0;
type RT1 is range L to R;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( RT1'right = RT1(R) )
report "***PASSED TEST: c14s01b00x00p17n01i03170"
severity NOTE;
assert ( RT1'right = RT1(R) )
report "***FAILED TEST: c14s01b00x00p17n01i03170 - Predefined attribute RIGHT for floating point type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p17n01i03170arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3170.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p17n01i03170ent IS
END c14s01b00x00p17n01i03170ent;
ARCHITECTURE c14s01b00x00p17n01i03170arch OF c14s01b00x00p17n01i03170ent IS
constant L : REAL := -10.0;
constant R : REAL := 10.0;
type RT1 is range L to R;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( RT1'right = RT1(R) )
report "***PASSED TEST: c14s01b00x00p17n01i03170"
severity NOTE;
assert ( RT1'right = RT1(R) )
report "***FAILED TEST: c14s01b00x00p17n01i03170 - Predefined attribute RIGHT for floating point type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p17n01i03170arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3170.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p17n01i03170ent IS
END c14s01b00x00p17n01i03170ent;
ARCHITECTURE c14s01b00x00p17n01i03170arch OF c14s01b00x00p17n01i03170ent IS
constant L : REAL := -10.0;
constant R : REAL := 10.0;
type RT1 is range L to R;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( RT1'right = RT1(R) )
report "***PASSED TEST: c14s01b00x00p17n01i03170"
severity NOTE;
assert ( RT1'right = RT1(R) )
report "***FAILED TEST: c14s01b00x00p17n01i03170 - Predefined attribute RIGHT for floating point type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p17n01i03170arch;
|
-- $Id: rlink_sp1c_fx2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp1c_fx2 - syn
-- Description: rlink_core8 + serport_1clock + fx2 combo
--
-- Dependencies: rlinklib/rlink_core8
-- serport/serport_1clock
-- rlinklib/rlink_rlbmux
-- fx2lib/fx2_2fifoctl_ic
-- rbus/rbd_rbmon
-- rbus/rb_sres_or_2
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2015-05-02 672 14.7 131013 xc6slx16-2 618 875 90 340 s 7.2 - -
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 441 903 128 637 s 8.7 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.3.1 use rbaddr_ constants
-- 2015-05-02 672 1.3 add rbd_rbmon (optional via generics)
-- 2015-04-11 666 1.2 drop ENAESC, rearrange XON handling
-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
-- 2013-04-20 509 1.0 Initial version (derived from rlink_sp1c)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
CCWIDTH : positive := 5; -- fx2 chunk counter width
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ato time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : out serport_moni_type; -- ser: monitor port
FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end entity rlink_sp1c_fx2;
architecture syn of rlink_sp1c_fx2 is
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal SER_RXDATA : slv8 := (others=>'0');
signal SER_RXVAL : slbit := '0';
signal SER_RXHOLD : slbit := '0';
signal SER_TXDATA : slv8 := (others=>'0');
signal SER_TXENA : slbit := '0';
signal SER_TXBUSY : slbit := '0';
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal RB_MREQ_M : rb_mreq_type := rb_mreq_init;
signal RB_SRES_M : rb_sres_type := rb_sres_init;
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init;
begin
CORE : rlink_core8 -- rlink master ----------------------
generic map (
BTOWIDTH => BTOWIDTH,
RTAWIDTH => RTAWIDTH,
SYSID => SYSID,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RLBMON=> ENAPIN_RLBMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
ESCXON => ENAXON,
ESCFILL => '0', -- not used in FX2 enabled boards
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_M,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock -- serport interface -----------------
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => '0', -- escaping now in rlink_core8
RXDATA => SER_RXDATA,
RXVAL => SER_RXVAL,
RXHOLD => SER_RXHOLD,
TXDATA => SER_TXDATA,
TXENA => SER_TXENA,
TXBUSY => SER_TXBUSY,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RLBMUX : rlink_rlbmux -- rlink control mux -----------------
port map (
SEL => ENAFX2,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
P0_RXDATA => SER_RXDATA,
P0_RXVAL => SER_RXVAL,
P0_RXHOLD => SER_RXHOLD,
P0_TXDATA => SER_TXDATA,
P0_TXENA => SER_TXENA,
P0_TXBUSY => SER_TXBUSY,
P1_RXDATA => FX2_RXDATA,
P1_RXVAL => FX2_RXVAL,
P1_RXHOLD => FX2_RXHOLD,
P1_TXDATA => FX2_TXDATA,
P1_TXENA => FX2_TXENA,
P1_TXBUSY => FX2_TXBUSY
);
RLB_MONI.rxval <= RLB_VAL;
RLB_MONI.rxhold <= RLB_HOLD;
RLB_MONI.txena <= RLB_ENA;
RLB_MONI.txbusy <= RLB_BUSY;
FX2CNTL : fx2_2fifoctl_ic -- FX2 interface ---------------------
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => PETOWIDTH,
CCWIDTH => CCWIDTH,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor --------------
begin
I0 : rbd_rbmon
generic map (
RB_ADDR => RBMON_RBADDR,
AWIDTH => RBMON_AWIDTH)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_RBMON,
RB_SRES_SUM => RB_SRES_M
);
end generate RBMON;
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES,
RB_SRES_2 => RB_SRES_RBMON,
RB_SRES_OR => RB_SRES_M
);
RB_MREQ <= RB_MREQ_M; -- setup output signals
end syn;
|
Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_3x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A140: buffer std_logic
);
end x25_3x;
architecture x25_3x_behav of x25_3x is
signal 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7647a,a7648a,a7649a,a7653a,a7654a,a7658a,a7659a,a7660a,a7663a,a7667a,a7668a,a7669a,a7673a,a7674a,a7678a,a7679a,a7680a,a7683a,a7687a,a7688a,a7689a,a7693a,a7694a,a7698a,a7699a,a7700a,a7703a,a7707a,a7708a,a7709a,a7713a,a7714a,a7718a,a7719a,a7720a,a7723a,a7727a,a7728a,a7729a,a7733a,a7734a,a7738a,a7739a,a7740a,a7743a,a7747a,a7748a,a7749a,a7753a,a7754a,a7758a,a7759a,a7760a,a7763a,a7767a,a7768a,a7769a,a7773a,a7774a,a7778a,a7779a,a7780a,a7783a,a7787a,a7788a,a7789a,a7793a,a7794a,a7798a,a7799a,a7800a,a7803a,a7807a,a7808a,a7809a,a7813a,a7814a,a7818a,a7819a,a7820a,a7823a,a7827a,a7828a,a7829a,a7833a,a7834a,a7838a,a7839a,a7840a,a7843a,a7847a,a7848a,a7849a,a7853a,a7854a,a7858a,a7859a,a7860a,a7863a,a7867a,a7868a,a7869a,a7873a,a7874a,a7878a,a7879a,a7880a,a7883a,a7887a,a7888a,a7889a,a7893a,a7894a,a7898a,a7899a,a7900a,a7903a,a7907a,a7908a,a7909a,a7913a,a7914a,a7918a,a7919a,a7920a,a7923a,a7927a,a7928a,a7929a,a7933a,a7934a,a7938a,a7939a,a7940a,a7943a,a7947a,a7948a,a7949a,a7953a,a7954a,a7958a,a7959a,a7960a,a7964a,a7965a,a7969a,a7970a,a7971a,a7975a,a7976a,a7980a,a7981a,a7982a,a7986a,a7987a,a7991a,a7992a,a7993a,a7997a,a7998a,a8002a,a8003a,a8004a,a8008a,a8009a,a8013a,a8014a,a8015a,a8019a,a8020a,a8024a,a8025a,a8026a,a8030a,a8031a,a8035a,a8036a,a8037a,a8041a,a8042a,a8046a,a8047a,a8048a,a8052a,a8053a,a8057a,a8058a,a8059a,a8063a,a8064a,a8068a,a8069a,a8070a,a8074a,a8075a,a8079a,a8080a,a8081a,a8085a,a8086a,a8090a,a8091a,a8092a,a8096a,a8097a,a8101a,a8102a,a8103a,a8107a,a8108a,a8112a,a8113a,a8114a,a8118a,a8119a,a8123a,a8124a,a8125a,a8129a,a8130a,a8134a,a8135a,a8136a,a8140a,a8141a,a8145a,a8146a,a8147a,a8151a,a8152a,a8156a,a8157a,a8158a,a8162a,a8163a,a8167a,a8168a,a8169a,a8173a,a8174a,a8178a,a8179a,a8180a,a8184a,a8185a,a8189a,a8190a,a8191a,a8195a,a8196a,a8200a,a8201a,a8202a,a8206a,a8207a,a8211a,a8212a,a8213a,a8217a,a8218a,a8222a,a8223a,a8224a,a8228a,a8229a,a8233a,a8234a,a8235a,a8239a,a8240a,a8244a,a8245a,a8246a,a8250a,a8251a,a8255a,a8256a,a8257a,a8261a,a8262a,a8266a,a8267a,a8268a,a8272a,a8273a,a8277a,a8278a,a8279a,a8283a,a8284a,a8288a,a8289a,a8290a,a8294a,a8295a,a8299a,a8300a,a8301a,a8305a,a8306a,a8310a,a8311a,a8312a,a8316a,a8317a,a8321a,a8322a,a8323a,a8327a,a8328a,a8332a,a8333a,a8334a,a8338a,a8339a,a8343a,a8344a,a8345a,a8349a,a8350a,a8354a,a8355a,a8356a,a8360a,a8361a,a8365a,a8366a,a8367a,a8371a,a8372a,a8376a,a8377a,a8378a,a8382a,a8383a,a8387a,a8388a,a8389a,a8393a,a8394a,a8398a,a8399a,a8400a,a8404a,a8405a,a8409a,a8410a,a8411a,a8415a,a8416a,a8420a,a8421a,a8422a,a8426a,a8427a,a8431a,a8432a,a8433a,a8437a,a8438a,a8442a,a8443a,a8444a,a8448a,a8449a,a8453a,a8454a,a8455a,a8459a,a8460a,a8464a,a8465a,a8466a,a8470a,a8471a,a8475a,a8476a,a8477a,a8481a,a8482a,a8486a,a8487a,a8488a,a8492a,a8493a,a8497a,a8498a,a8499a,a8503a,a8504a,a8508a,a8509a,a8510a,a8514a,a8515a,a8519a,a8520a,a8521a,a8525a,a8526a,a8530a,a8531a,a8532a,a8536a,a8537a,a8541a,a8542a,a8543a,a8547a,a8548a,a8552a,a8553a,a8554a,a8558a,a8559a,a8563a,a8564a,a8565a,a8569a,a8570a,a8574a,a8575a,a8576a,a8580a,a8581a,a8585a,a8586a,a8587a,a8591a,a8592a,a8596a,a8597a,a8598a,a8602a,a8603a,a8607a,a8608a,a8609a,a8613a,a8614a,a8618a,a8619a,a8620a,a8624a,a8625a,a8629a,a8630a,a8631a,a8635a,a8636a,a8640a,a8641a,a8642a,a8646a,a8647a,a8651a,a8652a,a8653a,a8657a,a8658a,a8662a,a8663a,a8664a,a8668a,a8669a,a8673a,a8674a,a8675a,a8679a,a8680a,a8684a,a8685a,a8686a,a8690a,a8691a,a8695a,a8696a,a8697a,a8701a,a8702a,a8706a,a8707a,a8708a,a8712a,a8713a,a8717a,a8718a,a8719a,a8723a,a8724a,a8728a,a8729a,a8730a,a8734a,a8735a,a8739a,a8740a,a8741a,a8745a,a8746a,a8750a,a8751a,a8752a,a8756a,a8757a,a8761a,a8762a,a8763a,a8767a,a8768a,a8772a,a8773a,a8774a,a8778a,a8779a,a8783a,a8784a,a8785a,a8789a,a8790a,a8794a,a8795a,a8796a,a8800a,a8801a,a8805a,a8806a,a8807a,a8811a,a8812a,a8816a,a8817a,a8818a,a8822a,a8823a,a8827a,a8828a,a8829a,a8833a,a8834a,a8838a,a8839a,a8840a,a8844a,a8845a,a8849a,a8850a,a8851a,a8855a,a8856a,a8860a,a8861a,a8862a,a8866a,a8867a,a8871a,a8872a,a8873a,a8877a,a8878a,a8882a,a8883a,a8884a,a8888a,a8889a,a8893a,a8894a,a8895a,a8899a,a8900a,a8904a,a8905a,a8906a,a8910a,a8911a,a8915a,a8916a,a8917a,a8921a,a8922a,a8926a,a8927a,a8928a,a8932a,a8933a,a8937a,a8938a,a8939a,a8943a,a8944a,a8948a,a8949a,a8950a,a8954a,a8955a,a8959a,a8960a,a8961a,a8965a,a8966a,a8970a,a8971a,a8972a,a8976a,a8977a,a8981a,a8982a,a8983a,a8987a,a8988a,a8992a,a8993a,a8994a,a8998a,a8999a,a9003a,a9004a,a9005a,a9009a,a9010a,a9014a,a9015a,a9016a,a9020a,a9021a,a9025a,a9026a,a9027a,a9031a,a9032a,a9036a,a9037a,a9038a,a9042a,a9043a,a9047a,a9048a,a9049a,a9053a,a9054a,a9058a,a9059a,a9060a,a9064a,a9065a,a9069a,a9070a,a9071a,a9075a,a9076a,a9080a,a9081a,a9082a,a9086a,a9087a,a9091a,a9092a,a9093a,a9097a,a9098a,a9102a,a9103a,a9104a,a9108a,a9109a,a9113a,a9114a,a9115a,a9119a,a9120a,a9124a,a9125a,a9126a,a9130a,a9131a,a9135a,a9136a,a9137a,a9141a,a9142a,a9146a,a9147a,a9148a,a9152a,a9153a,a9157a,a9158a,a9159a,a9163a,a9164a,a9168a,a9169a,a9170a,a9174a,a9175a,a9179a,a9180a,a9181a,a9185a,a9186a,a9190a,a9191a,a9192a,a9196a,a9197a,a9201a,a9202a,a9203a,a9207a,a9208a,a9212a,a9213a,a9214a,a9218a,a9219a,a9223a,a9224a,a9225a,a9229a,a9230a,a9234a,a9235a,a9236a,a9240a,a9241a,a9245a,a9246a,a9247a,a9251a,a9252a,a9256a,a9257a,a9258a,a9262a,a9263a,a9267a,a9268a,a9269a,a9273a,a9274a,a9278a,a9279a,a9280a,a9284a,a9285a,a9289a,a9290a,a9291a,a9295a,a9296a,a9300a,a9301a,a9302a,a9306a,a9307a,a9311a,a9312a,a9313a,a9317a,a9318a,a9322a,a9323a,a9324a,a9328a,a9329a,a9333a,a9334a,a9335a,a9339a,a9340a,a9344a,a9345a,a9346a,a9350a,a9351a,a9355a,a9356a,a9357a,a9361a,a9362a,a9366a,a9367a,a9368a,a9372a,a9373a,a9377a,a9378a,a9379a,a9383a,a9384a,a9387a,a9390a,a9391a,a9392a,a9396a,a9397a,a9401a,a9402a,a9403a,a9407a,a9408a,a9411a,a9414a,a9415a,a9416a,a9420a,a9421a,a9425a,a9426a,a9427a,a9431a,a9432a,a9435a,a9438a,a9439a,a9440a,a9444a,a9445a,a9449a,a9450a,a9451a,a9455a,a9456a,a9459a,a9462a,a9463a,a9464a,a9468a,a9469a,a9473a,a9474a,a9475a,a9479a,a9480a,a9483a,a9486a,a9487a,a9488a,a9492a,a9493a,a9497a,a9498a,a9499a,a9503a,a9504a,a9507a,a9510a,a9511a,a9512a,a9516a,a9517a,a9521a,a9522a,a9523a,a9527a,a9528a,a9531a,a9534a,a9535a,a9536a,a9540a,a9541a,a9545a,a9546a,a9547a,a9551a,a9552a,a9555a,a9558a,a9559a,a9560a: std_logic;
begin
A140 <=( a1312a ) or ( a875a );
a1a <=( a9560a and a9547a );
a2a <=( a9536a and a9523a );
a3a <=( a9512a and a9499a );
a4a <=( a9488a and a9475a );
a5a <=( a9464a and a9451a );
a6a <=( a9440a and a9427a );
a7a <=( a9416a and a9403a );
a8a <=( a9392a and a9379a );
a9a <=( a9368a and a9357a );
a10a <=( a9346a and a9335a );
a11a <=( a9324a and a9313a );
a12a <=( a9302a and a9291a );
a13a <=( a9280a and a9269a );
a14a <=( a9258a and a9247a );
a15a <=( a9236a and a9225a );
a16a <=( a9214a and a9203a );
a17a <=( a9192a and a9181a );
a18a <=( a9170a and a9159a );
a19a <=( a9148a and a9137a );
a20a <=( a9126a and a9115a );
a21a <=( a9104a and a9093a );
a22a <=( a9082a and a9071a );
a23a <=( a9060a and a9049a );
a24a <=( a9038a and a9027a );
a25a <=( a9016a and a9005a );
a26a <=( a8994a and a8983a );
a27a <=( a8972a and a8961a );
a28a <=( a8950a and a8939a );
a29a <=( a8928a and a8917a );
a30a <=( a8906a and a8895a );
a31a <=( a8884a and a8873a );
a32a <=( a8862a and a8851a );
a33a <=( a8840a and a8829a );
a34a <=( a8818a and a8807a );
a35a <=( a8796a and a8785a );
a36a <=( a8774a and a8763a );
a37a <=( a8752a and a8741a );
a38a <=( a8730a and a8719a );
a39a <=( a8708a and a8697a );
a40a <=( a8686a and a8675a );
a41a <=( a8664a and a8653a );
a42a <=( a8642a and a8631a );
a43a <=( a8620a and a8609a );
a44a <=( a8598a and a8587a );
a45a <=( a8576a and a8565a );
a46a <=( a8554a and a8543a );
a47a <=( a8532a and a8521a );
a48a <=( a8510a and a8499a );
a49a <=( a8488a and a8477a );
a50a <=( a8466a and a8455a );
a51a <=( a8444a and a8433a );
a52a <=( a8422a and a8411a );
a53a <=( a8400a and a8389a );
a54a <=( a8378a and a8367a );
a55a <=( a8356a and a8345a );
a56a <=( a8334a and a8323a );
a57a <=( a8312a and a8301a );
a58a <=( a8290a and a8279a );
a59a <=( a8268a and a8257a );
a60a <=( a8246a and a8235a );
a61a <=( a8224a and a8213a );
a62a <=( a8202a and a8191a );
a63a <=( a8180a and a8169a );
a64a <=( a8158a and a8147a );
a65a <=( a8136a and a8125a );
a66a <=( a8114a and a8103a );
a67a <=( a8092a and a8081a );
a68a <=( a8070a and a8059a );
a69a <=( a8048a and a8037a );
a70a <=( a8026a and a8015a );
a71a <=( a8004a and a7993a );
a72a <=( a7982a and a7971a );
a73a <=( a7960a and a7949a );
a74a <=( a7940a and a7929a );
a75a <=( a7920a and a7909a );
a76a <=( a7900a and a7889a );
a77a <=( a7880a and a7869a );
a78a <=( a7860a and a7849a );
a79a <=( a7840a and a7829a );
a80a <=( a7820a and a7809a );
a81a <=( a7800a and a7789a );
a82a <=( a7780a and a7769a );
a83a <=( a7760a and a7749a );
a84a <=( a7740a and a7729a );
a85a <=( a7720a and a7709a );
a86a <=( a7700a and a7689a );
a87a <=( a7680a and a7669a );
a88a <=( a7660a and a7649a );
a89a <=( a7640a and a7629a );
a90a <=( a7620a and a7609a );
a91a <=( a7600a and a7589a );
a92a <=( a7580a and a7569a );
a93a <=( a7560a and a7549a );
a94a <=( a7540a and a7529a );
a95a <=( a7520a and a7509a );
a96a <=( a7500a and a7489a );
a97a <=( a7480a and a7469a );
a98a <=( a7460a and a7449a );
a99a <=( a7440a and a7429a );
a100a <=( a7420a and a7409a );
a101a <=( a7400a and a7389a );
a102a <=( a7380a and a7369a );
a103a <=( a7360a and a7349a );
a104a <=( a7340a and a7329a );
a105a <=( a7320a and a7309a );
a106a <=( a7300a and a7289a );
a107a <=( a7280a and a7269a );
a108a <=( a7260a and a7249a );
a109a <=( a7240a and a7229a );
a110a <=( a7220a and a7209a );
a111a <=( a7200a and a7189a );
a112a <=( a7180a and a7169a );
a113a <=( a7160a and a7149a );
a114a <=( a7140a and a7129a );
a115a <=( a7120a and a7109a );
a116a <=( a7100a and a7089a );
a117a <=( a7080a and a7069a );
a118a <=( a7060a and a7049a );
a119a <=( a7040a and a7029a );
a120a <=( a7020a and a7009a );
a121a <=( a7000a and a6989a );
a122a <=( a6980a and a6969a );
a123a <=( a6960a and a6949a );
a124a <=( a6940a and a6929a );
a125a <=( a6920a and a6909a );
a126a <=( a6900a and a6889a );
a127a <=( a6880a and a6869a );
a128a <=( a6860a and a6849a );
a129a <=( a6840a and a6829a );
a130a <=( a6820a and a6809a );
a131a <=( a6800a and a6789a );
a132a <=( a6780a and a6769a );
a133a <=( a6760a and a6749a );
a134a <=( a6740a and a6729a );
a135a <=( a6720a and a6709a );
a136a <=( a6700a and a6689a );
a137a <=( a6680a and a6669a );
a138a <=( a6660a and a6649a );
a139a <=( a6640a and a6629a );
a140a <=( a6620a and a6609a );
a141a <=( a6600a and a6589a );
a142a <=( a6580a and a6569a );
a143a <=( a6560a and a6549a );
a144a <=( a6540a and a6529a );
a145a <=( a6520a and a6509a );
a146a <=( a6500a and a6489a );
a147a <=( a6480a and a6469a );
a148a <=( a6460a and a6449a );
a149a <=( a6440a and a6429a );
a150a <=( a6420a and a6409a );
a151a <=( a6400a and a6389a );
a152a <=( a6380a and a6369a );
a153a <=( a6360a and a6349a );
a154a <=( a6340a and a6329a );
a155a <=( a6320a and a6309a );
a156a <=( a6300a and a6289a );
a157a <=( a6280a and a6269a );
a158a <=( a6260a and a6249a );
a159a <=( a6240a and a6229a );
a160a <=( a6220a and a6209a );
a161a <=( a6200a and a6189a );
a162a <=( a6180a and a6169a );
a163a <=( a6160a and a6149a );
a164a <=( a6140a and a6129a );
a165a <=( a6120a and a6109a );
a166a <=( a6100a and a6089a );
a167a <=( a6080a and a6069a );
a168a <=( a6060a and a6049a );
a169a <=( a6040a and a6029a );
a170a <=( a6020a and a6009a );
a171a <=( a6000a and a5989a );
a172a <=( a5980a and a5969a );
a173a <=( a5960a and a5949a );
a174a <=( a5940a and a5929a );
a175a <=( a5920a and a5909a );
a176a <=( a5900a and a5889a );
a177a <=( a5880a and a5869a );
a178a <=( a5860a and a5849a );
a179a <=( a5840a and a5829a );
a180a <=( a5820a and a5809a );
a181a <=( a5800a and a5789a );
a182a <=( a5780a and a5769a );
a183a <=( a5760a and a5749a );
a184a <=( a5740a and a5729a );
a185a <=( a5720a and a5709a );
a186a <=( a5700a and a5689a );
a187a <=( a5680a and a5669a );
a188a <=( a5660a and a5649a );
a189a <=( a5640a and a5629a );
a190a <=( a5620a and a5609a );
a191a <=( a5600a and a5589a );
a192a <=( a5580a and a5569a );
a193a <=( a5560a and a5549a );
a194a <=( a5540a and a5529a );
a195a <=( a5520a and a5509a );
a196a <=( a5500a and a5489a );
a197a <=( a5480a and a5469a );
a198a <=( a5460a and a5449a );
a199a <=( a5440a and a5429a );
a200a <=( a5420a and a5409a );
a201a <=( a5400a and a5389a );
a202a <=( a5380a and a5369a );
a203a <=( a5360a and a5349a );
a204a <=( a5340a and a5329a );
a205a <=( a5320a and a5309a );
a206a <=( a5300a and a5289a );
a207a <=( a5280a and a5269a );
a208a <=( a5260a and a5249a );
a209a <=( a5240a and a5229a );
a210a <=( a5220a and a5209a );
a211a <=( a5200a and a5189a );
a212a <=( a5180a and a5169a );
a213a <=( a5160a and a5149a );
a214a <=( a5140a and a5129a );
a215a <=( a5120a and a5109a );
a216a <=( a5100a and a5089a );
a217a <=( a5080a and a5069a );
a218a <=( a5060a and a5049a );
a219a <=( a5040a and a5029a );
a220a <=( a5020a and a5009a );
a221a <=( a5000a and a4989a );
a222a <=( a4980a and a4969a );
a223a <=( a4960a and a4949a );
a224a <=( a4940a and a4929a );
a225a <=( a4920a and a4909a );
a226a <=( a4900a and a4889a );
a227a <=( a4880a and a4869a );
a228a <=( a4860a and a4849a );
a229a <=( a4840a and a4829a );
a230a <=( a4820a and a4809a );
a231a <=( a4800a and a4789a );
a232a <=( a4780a and a4769a );
a233a <=( a4760a and a4751a );
a234a <=( a4742a and a4733a );
a235a <=( a4724a and a4715a );
a236a <=( a4706a and a4697a );
a237a <=( a4688a and a4679a );
a238a <=( a4670a and a4661a );
a239a <=( a4652a and a4643a );
a240a <=( a4634a and a4625a );
a241a <=( a4616a and a4607a );
a242a <=( a4598a and a4589a );
a243a <=( a4580a and a4571a );
a244a <=( a4562a and a4553a );
a245a <=( a4544a and a4535a );
a246a <=( a4526a and a4517a );
a247a <=( a4508a and a4499a );
a248a <=( a4490a and a4481a );
a249a <=( a4472a and a4463a );
a250a <=( a4454a and a4445a );
a251a <=( a4436a and a4427a );
a252a <=( a4418a and a4409a );
a253a <=( a4400a and a4391a );
a254a <=( a4382a and a4373a );
a255a <=( a4364a and a4355a );
a256a <=( a4346a and a4337a );
a257a <=( a4328a and a4319a );
a258a <=( a4310a and a4301a );
a259a <=( a4292a and a4283a );
a260a <=( a4274a and a4265a );
a261a <=( a4256a and a4247a );
a262a <=( a4238a and a4229a );
a263a <=( a4220a and a4211a );
a264a <=( a4202a and a4193a );
a265a <=( a4184a and a4175a );
a266a <=( a4166a and a4157a );
a267a <=( a4148a and a4139a );
a268a <=( a4130a and a4121a );
a269a <=( a4112a and a4103a );
a270a <=( a4094a and a4085a );
a271a <=( a4076a and a4067a );
a272a <=( a4058a and a4049a );
a273a <=( a4040a and a4031a );
a274a <=( a4022a and a4013a );
a275a <=( a4004a and a3995a );
a276a <=( a3986a and a3977a );
a277a <=( a3968a and a3959a );
a278a <=( a3950a and a3941a );
a279a <=( a3932a and a3923a );
a280a <=( a3914a and a3905a );
a281a <=( a3896a and a3887a );
a282a <=( a3878a and a3869a );
a283a <=( a3860a and a3851a );
a284a <=( a3842a and a3833a );
a285a <=( a3824a and a3815a );
a286a <=( a3806a and a3797a );
a287a <=( a3788a and a3779a );
a288a <=( a3770a and a3761a );
a289a <=( a3752a and a3743a );
a290a <=( a3734a and a3725a );
a291a <=( a3716a and a3707a );
a292a <=( a3698a and a3689a );
a293a <=( a3680a and a3671a );
a294a <=( a3662a and a3653a );
a295a <=( a3644a and a3635a );
a296a <=( a3626a and a3617a );
a297a <=( a3608a and a3599a );
a298a <=( a3590a and a3581a );
a299a <=( a3572a and a3563a );
a300a <=( a3554a and a3545a );
a301a <=( a3536a and a3527a );
a302a <=( a3518a and a3509a );
a303a <=( a3500a and a3491a );
a304a <=( a3482a and a3473a );
a305a <=( a3464a and a3455a );
a306a <=( a3446a and a3437a );
a307a <=( a3428a and a3419a );
a308a <=( a3410a and a3401a );
a309a <=( a3392a and a3383a );
a310a <=( a3374a and a3365a );
a311a <=( a3356a and a3347a );
a312a <=( a3338a and a3329a );
a313a <=( a3320a and a3311a );
a314a <=( a3302a and a3293a );
a315a <=( a3284a and a3275a );
a316a <=( a3266a and a3257a );
a317a <=( a3248a and a3239a );
a318a <=( a3230a and a3221a );
a319a <=( a3212a and a3203a );
a320a <=( a3194a and a3185a );
a321a <=( a3176a and a3167a );
a322a <=( a3158a and a3149a );
a323a <=( a3140a and a3131a );
a324a <=( a3122a and a3113a );
a325a <=( a3104a and a3095a );
a326a <=( a3086a and a3077a );
a327a <=( a3068a and a3059a );
a328a <=( a3050a and a3041a );
a329a <=( a3032a and a3023a );
a330a <=( a3014a and a3005a );
a331a <=( a2996a and a2987a );
a332a <=( a2978a and a2969a );
a333a <=( a2960a and a2951a );
a334a <=( a2942a and a2933a );
a335a <=( a2924a and a2915a );
a336a <=( a2906a and a2897a );
a337a <=( a2888a and a2879a );
a338a <=( a2870a and a2861a );
a339a <=( a2852a and a2843a );
a340a <=( a2834a and a2825a );
a341a <=( a2816a and a2807a );
a342a <=( a2798a and a2789a );
a343a <=( a2780a and a2771a );
a344a <=( a2762a and a2753a );
a345a <=( a2744a and a2735a );
a346a <=( a2726a and a2717a );
a347a <=( a2708a and a2699a );
a348a <=( a2690a and a2681a );
a349a <=( a2672a and a2663a );
a350a <=( a2654a and a2645a );
a351a <=( a2636a and a2627a );
a352a <=( a2618a and a2609a );
a353a <=( a2600a and a2591a );
a354a <=( a2582a and a2573a );
a355a <=( a2564a and a2555a );
a356a <=( a2546a and a2537a );
a357a <=( a2528a and a2519a );
a358a <=( a2510a and a2501a );
a359a <=( a2492a and a2483a );
a360a <=( a2474a and a2465a );
a361a <=( a2456a and a2447a );
a362a <=( a2438a and a2429a );
a363a <=( a2420a and a2411a );
a364a <=( a2402a and a2393a );
a365a <=( a2384a and a2375a );
a366a <=( a2366a and a2357a );
a367a <=( a2348a and a2339a );
a368a <=( a2330a and a2321a );
a369a <=( a2312a and a2303a );
a370a <=( a2296a and a2287a );
a371a <=( a2280a and a2271a );
a372a <=( a2264a and a2255a );
a373a <=( a2248a and a2239a );
a374a <=( a2232a and a2223a );
a375a <=( a2216a and a2207a );
a376a <=( a2200a and a2191a );
a377a <=( a2184a and a2175a );
a378a <=( a2168a and a2159a );
a379a <=( a2152a and a2143a );
a380a <=( a2136a and a2127a );
a381a <=( a2120a and a2111a );
a382a <=( a2104a and a2095a );
a383a <=( a2088a and a2079a );
a384a <=( a2072a and a2063a );
a385a <=( a2056a and a2047a );
a386a <=( a2040a and a2031a );
a387a <=( a2024a and a2015a );
a388a <=( a2008a and a1999a );
a389a <=( a1992a and a1983a );
a390a <=( a1976a and a1967a );
a391a <=( a1960a and a1951a );
a392a <=( a1944a and a1935a );
a393a <=( a1928a and a1919a );
a394a <=( a1912a and a1903a );
a395a <=( a1896a and a1887a );
a396a <=( a1880a and a1871a );
a397a <=( a1864a and a1855a );
a398a <=( a1848a and a1839a );
a399a <=( a1832a and a1823a );
a400a <=( a1816a and a1807a );
a401a <=( a1800a and a1793a );
a402a <=( a1786a and a1779a );
a403a <=( a1772a and a1765a );
a404a <=( a1758a and a1751a );
a405a <=( a1744a and a1737a );
a406a <=( a1730a and a1723a );
a407a <=( a1716a and a1709a );
a408a <=( a1702a and a1695a );
a409a <=( a1688a and a1681a );
a410a <=( a1674a and a1667a );
a411a <=( a1660a and a1653a );
a412a <=( a1646a and a1639a );
a413a <=( a1632a and a1625a );
a414a <=( a1618a and a1611a );
a415a <=( a1604a and a1597a );
a416a <=( a1590a and a1583a );
a417a <=( a1576a and a1569a );
a418a <=( a1562a and a1555a );
a419a <=( a1548a and a1541a );
a420a <=( a1534a and a1527a );
a421a <=( a1520a and a1513a );
a422a <=( a1506a and a1499a );
a423a <=( a1492a and a1485a );
a424a <=( a1478a and a1471a );
a425a <=( a1464a and a1457a );
a426a <=( a1450a and a1443a );
a427a <=( a1436a and a1429a );
a428a <=( a1422a and a1415a );
a429a <=( a1408a and a1401a );
a430a <=( a1394a and a1387a );
a431a <=( a1380a and a1373a );
a432a <=( a1366a and a1359a );
a433a <=( a1352a and a1347a );
a434a <=( a1344a and a1339a );
a435a <=( a1336a and a1333a );
a436a <=( a1330a and a1327a );
a437a <=( a1324a and a1321a );
a438a <=( a1318a and a1315a );
a442a <=( a436a ) or ( a437a );
a443a <=( a438a ) or ( a442a );
a447a <=( a433a ) or ( a434a );
a448a <=( a435a ) or ( a447a );
a449a <=( a448a ) or ( a443a );
a453a <=( a430a ) or ( a431a );
a454a <=( a432a ) or ( a453a );
a457a <=( a428a ) or ( a429a );
a460a <=( a426a ) or ( a427a );
a461a <=( a460a ) or ( a457a );
a462a <=( a461a ) or ( a454a );
a463a <=( a462a ) or ( a449a );
a467a <=( a423a ) or ( a424a );
a468a <=( a425a ) or ( a467a );
a471a <=( a421a ) or ( a422a );
a474a <=( a419a ) or ( a420a );
a475a <=( a474a ) or ( a471a );
a476a <=( a475a ) or ( a468a );
a480a <=( a416a ) or ( a417a );
a481a <=( a418a ) or ( a480a );
a484a <=( a414a ) or ( a415a );
a487a <=( a412a ) or ( a413a );
a488a <=( a487a ) or ( a484a );
a489a <=( a488a ) or ( a481a );
a490a <=( a489a ) or ( a476a );
a491a <=( a490a ) or ( a463a );
a495a <=( a409a ) or ( a410a );
a496a <=( a411a ) or ( a495a );
a500a <=( a406a ) or ( a407a );
a501a <=( a408a ) or ( a500a );
a502a <=( a501a ) or ( a496a );
a506a <=( a403a ) or ( a404a );
a507a <=( a405a ) or ( a506a );
a510a <=( a401a ) or ( a402a );
a513a <=( a399a ) or ( a400a );
a514a <=( a513a ) or ( a510a );
a515a <=( a514a ) or ( a507a );
a516a <=( a515a ) or ( a502a );
a520a <=( a396a ) or ( a397a );
a521a <=( a398a ) or ( a520a );
a524a <=( a394a ) or ( a395a );
a527a <=( a392a ) or ( a393a );
a528a <=( a527a ) or ( a524a );
a529a <=( a528a ) or ( a521a );
a533a <=( a389a ) or ( a390a );
a534a <=( a391a ) or ( a533a );
a537a <=( a387a ) or ( a388a );
a540a <=( a385a ) or ( a386a );
a541a <=( a540a ) or ( a537a );
a542a <=( a541a ) or ( a534a );
a543a <=( a542a ) or ( a529a );
a544a <=( a543a ) or ( a516a );
a545a <=( a544a ) or ( a491a );
a549a <=( a382a ) or ( a383a );
a550a <=( a384a ) or ( a549a );
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a555a <=( a381a ) or ( a554a );
a556a <=( a555a ) or ( a550a );
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a564a <=( a374a ) or ( a375a );
a567a <=( a372a ) or ( a373a );
a568a <=( a567a ) or ( a564a );
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a575a <=( a371a ) or ( a574a );
a578a <=( a367a ) or ( a368a );
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a582a <=( a581a ) or ( a578a );
a583a <=( a582a ) or ( a575a );
a587a <=( a362a ) or ( a363a );
a588a <=( a364a ) or ( a587a );
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a594a <=( a358a ) or ( a359a );
a595a <=( a594a ) or ( a591a );
a596a <=( a595a ) or ( a588a );
a597a <=( a596a ) or ( a583a );
a598a <=( a597a ) or ( a570a );
a602a <=( a355a ) or ( a356a );
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a610a <=( a609a ) or ( a606a );
a611a <=( a610a ) or ( a603a );
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a616a <=( a350a ) or ( a615a );
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a624a <=( a623a ) or ( a616a );
a625a <=( a624a ) or ( a611a );
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a630a <=( a343a ) or ( a629a );
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a636a <=( a337a ) or ( a338a );
a637a <=( a636a ) or ( a633a );
a638a <=( a637a ) or ( a630a );
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a643a <=( a336a ) or ( a642a );
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a650a <=( a649a ) or ( a646a );
a651a <=( a650a ) or ( a643a );
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a653a <=( a652a ) or ( a625a );
a654a <=( a653a ) or ( a598a );
a655a <=( a654a ) or ( a545a );
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a660a <=( a329a ) or ( a659a );
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a665a <=( a326a ) or ( a664a );
a666a <=( a665a ) or ( a660a );
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a671a <=( a323a ) or ( a670a );
a674a <=( a319a ) or ( a320a );
a677a <=( a317a ) or ( a318a );
a678a <=( a677a ) or ( a674a );
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a680a <=( a679a ) or ( a666a );
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a685a <=( a316a ) or ( a684a );
a688a <=( a312a ) or ( a313a );
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a692a <=( a691a ) or ( a688a );
a693a <=( a692a ) or ( a685a );
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a698a <=( a309a ) or ( a697a );
a701a <=( a305a ) or ( a306a );
a704a <=( a303a ) or ( a304a );
a705a <=( a704a ) or ( a701a );
a706a <=( a705a ) or ( a698a );
a707a <=( a706a ) or ( a693a );
a708a <=( a707a ) or ( a680a );
a712a <=( a300a ) or ( a301a );
a713a <=( a302a ) or ( a712a );
a716a <=( a298a ) or ( a299a );
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a720a <=( a719a ) or ( a716a );
a721a <=( a720a ) or ( a713a );
a725a <=( a293a ) or ( a294a );
a726a <=( a295a ) or ( a725a );
a729a <=( a291a ) or ( a292a );
a732a <=( a289a ) or ( a290a );
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a734a <=( a733a ) or ( a726a );
a735a <=( a734a ) or ( a721a );
a739a <=( a286a ) or ( a287a );
a740a <=( a288a ) or ( a739a );
a743a <=( a284a ) or ( a285a );
a746a <=( a282a ) or ( a283a );
a747a <=( a746a ) or ( a743a );
a748a <=( a747a ) or ( a740a );
a752a <=( a279a ) or ( a280a );
a753a <=( a281a ) or ( a752a );
a756a <=( a277a ) or ( a278a );
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a760a <=( a759a ) or ( a756a );
a761a <=( a760a ) or ( a753a );
a762a <=( a761a ) or ( a748a );
a763a <=( a762a ) or ( a735a );
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a768a <=( a272a ) or ( a273a );
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a773a <=( a269a ) or ( a270a );
a774a <=( a271a ) or ( a773a );
a775a <=( a774a ) or ( a769a );
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a780a <=( a268a ) or ( a779a );
a783a <=( a264a ) or ( a265a );
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a787a <=( a786a ) or ( a783a );
a788a <=( a787a ) or ( a780a );
a789a <=( a788a ) or ( a775a );
a793a <=( a259a ) or ( a260a );
a794a <=( a261a ) or ( a793a );
a797a <=( a257a ) or ( a258a );
a800a <=( a255a ) or ( a256a );
a801a <=( a800a ) or ( a797a );
a802a <=( a801a ) or ( a794a );
a806a <=( a252a ) or ( a253a );
a807a <=( a254a ) or ( a806a );
a810a <=( a250a ) or ( a251a );
a813a <=( a248a ) or ( a249a );
a814a <=( a813a ) or ( a810a );
a815a <=( a814a ) or ( a807a );
a816a <=( a815a ) or ( a802a );
a817a <=( a816a ) or ( a789a );
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a822a <=( a247a ) or ( a821a );
a825a <=( a243a ) or ( a244a );
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a829a <=( a828a ) or ( a825a );
a830a <=( a829a ) or ( a822a );
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a835a <=( a240a ) or ( a834a );
a838a <=( a236a ) or ( a237a );
a841a <=( a234a ) or ( a235a );
a842a <=( a841a ) or ( a838a );
a843a <=( a842a ) or ( a835a );
a844a <=( a843a ) or ( a830a );
a848a <=( a231a ) or ( a232a );
a849a <=( a233a ) or ( a848a );
a852a <=( a229a ) or ( a230a );
a855a <=( a227a ) or ( a228a );
a856a <=( a855a ) or ( a852a );
a857a <=( a856a ) or ( a849a );
a861a <=( a224a ) or ( a225a );
a862a <=( a226a ) or ( a861a );
a865a <=( a222a ) or ( a223a );
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a869a <=( a868a ) or ( a865a );
a870a <=( a869a ) or ( a862a );
a871a <=( a870a ) or ( a857a );
a872a <=( a871a ) or ( a844a );
a873a <=( a872a ) or ( a817a );
a874a <=( a873a ) or ( a764a );
a875a <=( a874a ) or ( a655a );
a879a <=( a217a ) or ( a218a );
a880a <=( a219a ) or ( a879a );
a884a <=( a214a ) or ( a215a );
a885a <=( a216a ) or ( a884a );
a886a <=( a885a ) or ( a880a );
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a891a <=( a213a ) or ( a890a );
a894a <=( a209a ) or ( a210a );
a897a <=( a207a ) or ( a208a );
a898a <=( a897a ) or ( a894a );
a899a <=( a898a ) or ( a891a );
a900a <=( a899a ) or ( a886a );
a904a <=( a204a ) or ( a205a );
a905a <=( a206a ) or ( a904a );
a908a <=( a202a ) or ( a203a );
a911a <=( a200a ) or ( a201a );
a912a <=( a911a ) or ( a908a );
a913a <=( a912a ) or ( a905a );
a917a <=( a197a ) or ( a198a );
a918a <=( a199a ) or ( a917a );
a921a <=( a195a ) or ( a196a );
a924a <=( a193a ) or ( a194a );
a925a <=( a924a ) or ( a921a );
a926a <=( a925a ) or ( a918a );
a927a <=( a926a ) or ( a913a );
a928a <=( a927a ) or ( a900a );
a932a <=( a190a ) or ( a191a );
a933a <=( a192a ) or ( a932a );
a937a <=( a187a ) or ( a188a );
a938a <=( a189a ) or ( a937a );
a939a <=( a938a ) or ( a933a );
a943a <=( a184a ) or ( a185a );
a944a <=( a186a ) or ( a943a );
a947a <=( a182a ) or ( a183a );
a950a <=( a180a ) or ( a181a );
a951a <=( a950a ) or ( a947a );
a952a <=( a951a ) or ( a944a );
a953a <=( a952a ) or ( a939a );
a957a <=( a177a ) or ( a178a );
a958a <=( a179a ) or ( a957a );
a961a <=( a175a ) or ( a176a );
a964a <=( a173a ) or ( a174a );
a965a <=( a964a ) or ( a961a );
a966a <=( a965a ) or ( a958a );
a970a <=( a170a ) or ( a171a );
a971a <=( a172a ) or ( a970a );
a974a <=( a168a ) or ( a169a );
a977a <=( a166a ) or ( a167a );
a978a <=( a977a ) or ( a974a );
a979a <=( a978a ) or ( a971a );
a980a <=( a979a ) or ( a966a );
a981a <=( a980a ) or ( a953a );
a982a <=( a981a ) or ( a928a );
a986a <=( a163a ) or ( a164a );
a987a <=( a165a ) or ( a986a );
a991a <=( a160a ) or ( a161a );
a992a <=( a162a ) or ( a991a );
a993a <=( a992a ) or ( a987a );
a997a <=( a157a ) or ( a158a );
a998a <=( a159a ) or ( a997a );
a1001a <=( a155a ) or ( a156a );
a1004a <=( a153a ) or ( a154a );
a1005a <=( a1004a ) or ( a1001a );
a1006a <=( a1005a ) or ( a998a );
a1007a <=( a1006a ) or ( a993a );
a1011a <=( a150a ) or ( a151a );
a1012a <=( a152a ) or ( a1011a );
a1015a <=( a148a ) or ( a149a );
a1018a <=( a146a ) or ( a147a );
a1019a <=( a1018a ) or ( a1015a );
a1020a <=( a1019a ) or ( a1012a );
a1024a <=( a143a ) or ( a144a );
a1025a <=( a145a ) or ( a1024a );
a1028a <=( a141a ) or ( a142a );
a1031a <=( a139a ) or ( a140a );
a1032a <=( a1031a ) or ( a1028a );
a1033a <=( a1032a ) or ( a1025a );
a1034a <=( a1033a ) or ( a1020a );
a1035a <=( a1034a ) or ( a1007a );
a1039a <=( a136a ) or ( a137a );
a1040a <=( a138a ) or ( a1039a );
a1043a <=( a134a ) or ( a135a );
a1046a <=( a132a ) or ( a133a );
a1047a <=( a1046a ) or ( a1043a );
a1048a <=( a1047a ) or ( a1040a );
a1052a <=( a129a ) or ( a130a );
a1053a <=( a131a ) or ( a1052a );
a1056a <=( a127a ) or ( a128a );
a1059a <=( a125a ) or ( a126a );
a1060a <=( a1059a ) or ( a1056a );
a1061a <=( a1060a ) or ( a1053a );
a1062a <=( a1061a ) or ( a1048a );
a1066a <=( a122a ) or ( a123a );
a1067a <=( a124a ) or ( a1066a );
a1070a <=( a120a ) or ( a121a );
a1073a <=( a118a ) or ( a119a );
a1074a <=( a1073a ) or ( a1070a );
a1075a <=( a1074a ) or ( a1067a );
a1079a <=( a115a ) or ( a116a );
a1080a <=( a117a ) or ( a1079a );
a1083a <=( a113a ) or ( a114a );
a1086a <=( a111a ) or ( a112a );
a1087a <=( a1086a ) or ( a1083a );
a1088a <=( a1087a ) or ( a1080a );
a1089a <=( a1088a ) or ( a1075a );
a1090a <=( a1089a ) or ( a1062a );
a1091a <=( a1090a ) or ( a1035a );
a1092a <=( a1091a ) or ( a982a );
a1096a <=( a108a ) or ( a109a );
a1097a <=( a110a ) or ( a1096a );
a1101a <=( a105a ) or ( a106a );
a1102a <=( a107a ) or ( a1101a );
a1103a <=( a1102a ) or ( a1097a );
a1107a <=( a102a ) or ( a103a );
a1108a <=( a104a ) or ( a1107a );
a1111a <=( a100a ) or ( a101a );
a1114a <=( a98a ) or ( a99a );
a1115a <=( a1114a ) or ( a1111a );
a1116a <=( a1115a ) or ( a1108a );
a1117a <=( a1116a ) or ( a1103a );
a1121a <=( a95a ) or ( a96a );
a1122a <=( a97a ) or ( a1121a );
a1125a <=( a93a ) or ( a94a );
a1128a <=( a91a ) or ( a92a );
a1129a <=( a1128a ) or ( a1125a );
a1130a <=( a1129a ) or ( a1122a );
a1134a <=( a88a ) or ( a89a );
a1135a <=( a90a ) or ( a1134a );
a1138a <=( a86a ) or ( a87a );
a1141a <=( a84a ) or ( a85a );
a1142a <=( a1141a ) or ( a1138a );
a1143a <=( a1142a ) or ( a1135a );
a1144a <=( a1143a ) or ( a1130a );
a1145a <=( a1144a ) or ( a1117a );
a1149a <=( a81a ) or ( a82a );
a1150a <=( a83a ) or ( a1149a );
a1153a <=( a79a ) or ( a80a );
a1156a <=( a77a ) or ( a78a );
a1157a <=( a1156a ) or ( a1153a );
a1158a <=( a1157a ) or ( a1150a );
a1162a <=( a74a ) or ( a75a );
a1163a <=( a76a ) or ( a1162a );
a1166a <=( a72a ) or ( a73a );
a1169a <=( a70a ) or ( a71a );
a1170a <=( a1169a ) or ( a1166a );
a1171a <=( a1170a ) or ( a1163a );
a1172a <=( a1171a ) or ( a1158a );
a1176a <=( a67a ) or ( a68a );
a1177a <=( a69a ) or ( a1176a );
a1180a <=( a65a ) or ( a66a );
a1183a <=( a63a ) or ( a64a );
a1184a <=( a1183a ) or ( a1180a );
a1185a <=( a1184a ) or ( a1177a );
a1189a <=( a60a ) or ( a61a );
a1190a <=( a62a ) or ( a1189a );
a1193a <=( a58a ) or ( a59a );
a1196a <=( a56a ) or ( a57a );
a1197a <=( a1196a ) or ( a1193a );
a1198a <=( a1197a ) or ( a1190a );
a1199a <=( a1198a ) or ( a1185a );
a1200a <=( a1199a ) or ( a1172a );
a1201a <=( a1200a ) or ( a1145a );
a1205a <=( a53a ) or ( a54a );
a1206a <=( a55a ) or ( a1205a );
a1210a <=( a50a ) or ( a51a );
a1211a <=( a52a ) or ( a1210a );
a1212a <=( a1211a ) or ( a1206a );
a1216a <=( a47a ) or ( a48a );
a1217a <=( a49a ) or ( a1216a );
a1220a <=( a45a ) or ( a46a );
a1223a <=( a43a ) or ( a44a );
a1224a <=( a1223a ) or ( a1220a );
a1225a <=( a1224a ) or ( a1217a );
a1226a <=( a1225a ) or ( a1212a );
a1230a <=( a40a ) or ( a41a );
a1231a <=( a42a ) or ( a1230a );
a1234a <=( a38a ) or ( a39a );
a1237a <=( a36a ) or ( a37a );
a1238a <=( a1237a ) or ( a1234a );
a1239a <=( a1238a ) or ( a1231a );
a1243a <=( a33a ) or ( a34a );
a1244a <=( a35a ) or ( a1243a );
a1247a <=( a31a ) or ( a32a );
a1250a <=( a29a ) or ( a30a );
a1251a <=( a1250a ) or ( a1247a );
a1252a <=( a1251a ) or ( a1244a );
a1253a <=( a1252a ) or ( a1239a );
a1254a <=( a1253a ) or ( a1226a );
a1258a <=( a26a ) or ( a27a );
a1259a <=( a28a ) or ( a1258a );
a1262a <=( a24a ) or ( a25a );
a1265a <=( a22a ) or ( a23a );
a1266a <=( a1265a ) or ( a1262a );
a1267a <=( a1266a ) or ( a1259a );
a1271a <=( a19a ) or ( a20a );
a1272a <=( a21a ) or ( a1271a );
a1275a <=( a17a ) or ( a18a );
a1278a <=( a15a ) or ( a16a );
a1279a <=( a1278a ) or ( a1275a );
a1280a <=( a1279a ) or ( a1272a );
a1281a <=( a1280a ) or ( a1267a );
a1285a <=( a12a ) or ( a13a );
a1286a <=( a14a ) or ( a1285a );
a1289a <=( a10a ) or ( a11a );
a1292a <=( a8a ) or ( a9a );
a1293a <=( a1292a ) or ( a1289a );
a1294a <=( a1293a ) or ( a1286a );
a1298a <=( a5a ) or ( a6a );
a1299a <=( a7a ) or ( a1298a );
a1302a <=( a3a ) or ( a4a );
a1305a <=( a1a ) or ( a2a );
a1306a <=( a1305a ) or ( a1302a );
a1307a <=( a1306a ) or ( a1299a );
a1308a <=( a1307a ) or ( a1294a );
a1309a <=( a1308a ) or ( a1281a );
a1310a <=( a1309a ) or ( a1254a );
a1311a <=( a1310a ) or ( a1201a );
a1312a <=( a1311a ) or ( a1092a );
a1315a <=( A266 and (not A265) );
a1318a <=( A268 and A267 );
a1321a <=( A266 and (not A265) );
a1324a <=( A269 and A267 );
a1327a <=( (not A266) and A265 );
a1330a <=( A268 and A267 );
a1333a <=( (not A266) and A265 );
a1336a <=( A269 and A267 );
a1339a <=( A266 and (not A265) );
a1343a <=( (not A269) and (not A268) );
a1344a <=( (not A267) and a1343a );
a1347a <=( (not A266) and A265 );
a1351a <=( (not A269) and (not A268) );
a1352a <=( (not A267) and a1351a );
a1355a <=( A200 and (not A199) );
a1358a <=( A202 and A201 );
a1359a <=( a1358a and a1355a );
a1362a <=( A233 and (not A232) );
a1365a <=( A235 and A234 );
a1366a <=( a1365a and a1362a );
a1369a <=( A200 and (not A199) );
a1372a <=( A202 and A201 );
a1373a <=( a1372a and a1369a );
a1376a <=( A233 and (not A232) );
a1379a <=( A236 and A234 );
a1380a <=( a1379a and a1376a );
a1383a <=( A200 and (not A199) );
a1386a <=( A202 and A201 );
a1387a <=( a1386a and a1383a );
a1390a <=( (not A233) and A232 );
a1393a <=( A235 and A234 );
a1394a <=( a1393a and a1390a );
a1397a <=( A200 and (not A199) );
a1400a <=( A202 and A201 );
a1401a <=( a1400a and a1397a );
a1404a <=( (not A233) and A232 );
a1407a <=( A236 and A234 );
a1408a <=( a1407a and a1404a );
a1411a <=( A200 and (not A199) );
a1414a <=( A203 and A201 );
a1415a <=( a1414a and a1411a );
a1418a <=( A233 and (not A232) );
a1421a <=( A235 and A234 );
a1422a <=( a1421a and a1418a );
a1425a <=( A200 and (not A199) );
a1428a <=( A203 and A201 );
a1429a <=( a1428a and a1425a );
a1432a <=( A233 and (not A232) );
a1435a <=( A236 and A234 );
a1436a <=( a1435a and a1432a );
a1439a <=( A200 and (not A199) );
a1442a <=( A203 and A201 );
a1443a <=( a1442a and a1439a );
a1446a <=( (not A233) and A232 );
a1449a <=( A235 and A234 );
a1450a <=( a1449a and a1446a );
a1453a <=( A200 and (not A199) );
a1456a <=( A203 and A201 );
a1457a <=( a1456a and a1453a );
a1460a <=( (not A233) and A232 );
a1463a <=( A236 and A234 );
a1464a <=( a1463a and a1460a );
a1467a <=( (not A200) and A199 );
a1470a <=( A202 and A201 );
a1471a <=( a1470a and a1467a );
a1474a <=( A233 and (not A232) );
a1477a <=( A235 and A234 );
a1478a <=( a1477a and a1474a );
a1481a <=( (not A200) and A199 );
a1484a <=( A202 and A201 );
a1485a <=( a1484a and a1481a );
a1488a <=( A233 and (not A232) );
a1491a <=( A236 and A234 );
a1492a <=( a1491a and a1488a );
a1495a <=( (not A200) and A199 );
a1498a <=( A202 and A201 );
a1499a <=( a1498a and a1495a );
a1502a <=( (not A233) and A232 );
a1505a <=( A235 and A234 );
a1506a <=( a1505a and a1502a );
a1509a <=( (not A200) and A199 );
a1512a <=( A202 and A201 );
a1513a <=( a1512a and a1509a );
a1516a <=( (not A233) and A232 );
a1519a <=( A236 and A234 );
a1520a <=( a1519a and a1516a );
a1523a <=( (not A200) and A199 );
a1526a <=( A203 and A201 );
a1527a <=( a1526a and a1523a );
a1530a <=( A233 and (not A232) );
a1533a <=( A235 and A234 );
a1534a <=( a1533a and a1530a );
a1537a <=( (not A200) and A199 );
a1540a <=( A203 and A201 );
a1541a <=( a1540a and a1537a );
a1544a <=( A233 and (not A232) );
a1547a <=( A236 and A234 );
a1548a <=( a1547a and a1544a );
a1551a <=( (not A200) and A199 );
a1554a <=( A203 and A201 );
a1555a <=( a1554a and a1551a );
a1558a <=( (not A233) and A232 );
a1561a <=( A235 and A234 );
a1562a <=( a1561a and a1558a );
a1565a <=( (not A200) and A199 );
a1568a <=( A203 and A201 );
a1569a <=( a1568a and a1565a );
a1572a <=( (not A233) and A232 );
a1575a <=( A236 and A234 );
a1576a <=( a1575a and a1572a );
a1579a <=( A168 and (not A170) );
a1582a <=( (not A166) and A167 );
a1583a <=( a1582a and a1579a );
a1586a <=( A233 and (not A232) );
a1589a <=( A235 and A234 );
a1590a <=( a1589a and a1586a );
a1593a <=( A168 and (not A170) );
a1596a <=( (not A166) and A167 );
a1597a <=( a1596a and a1593a );
a1600a <=( A233 and (not A232) );
a1603a <=( A236 and A234 );
a1604a <=( a1603a and a1600a );
a1607a <=( A168 and (not A170) );
a1610a <=( (not A166) and A167 );
a1611a <=( a1610a and a1607a );
a1614a <=( (not A233) and A232 );
a1617a <=( A235 and A234 );
a1618a <=( a1617a and a1614a );
a1621a <=( A168 and (not A170) );
a1624a <=( (not A166) and A167 );
a1625a <=( a1624a and a1621a );
a1628a <=( (not A233) and A232 );
a1631a <=( A236 and A234 );
a1632a <=( a1631a and a1628a );
a1635a <=( A168 and (not A170) );
a1638a <=( A166 and (not A167) );
a1639a <=( a1638a and a1635a );
a1642a <=( A233 and (not A232) );
a1645a <=( A235 and A234 );
a1646a <=( a1645a and a1642a );
a1649a <=( A168 and (not A170) );
a1652a <=( A166 and (not A167) );
a1653a <=( a1652a and a1649a );
a1656a <=( A233 and (not A232) );
a1659a <=( A236 and A234 );
a1660a <=( a1659a and a1656a );
a1663a <=( A168 and (not A170) );
a1666a <=( A166 and (not A167) );
a1667a <=( a1666a and a1663a );
a1670a <=( (not A233) and A232 );
a1673a <=( A235 and A234 );
a1674a <=( a1673a and a1670a );
a1677a <=( A168 and (not A170) );
a1680a <=( A166 and (not A167) );
a1681a <=( a1680a and a1677a );
a1684a <=( (not A233) and A232 );
a1687a <=( A236 and A234 );
a1688a <=( a1687a and a1684a );
a1691a <=( A168 and A169 );
a1694a <=( (not A166) and A167 );
a1695a <=( a1694a and a1691a );
a1698a <=( A233 and (not A232) );
a1701a <=( A235 and A234 );
a1702a <=( a1701a and a1698a );
a1705a <=( A168 and A169 );
a1708a <=( (not A166) and A167 );
a1709a <=( a1708a and a1705a );
a1712a <=( A233 and (not A232) );
a1715a <=( A236 and A234 );
a1716a <=( a1715a and a1712a );
a1719a <=( A168 and A169 );
a1722a <=( (not A166) and A167 );
a1723a <=( a1722a and a1719a );
a1726a <=( (not A233) and A232 );
a1729a <=( A235 and A234 );
a1730a <=( a1729a and a1726a );
a1733a <=( A168 and A169 );
a1736a <=( (not A166) and A167 );
a1737a <=( a1736a and a1733a );
a1740a <=( (not A233) and A232 );
a1743a <=( A236 and A234 );
a1744a <=( a1743a and a1740a );
a1747a <=( A168 and A169 );
a1750a <=( A166 and (not A167) );
a1751a <=( a1750a and a1747a );
a1754a <=( A233 and (not A232) );
a1757a <=( A235 and A234 );
a1758a <=( a1757a and a1754a );
a1761a <=( A168 and A169 );
a1764a <=( A166 and (not A167) );
a1765a <=( a1764a and a1761a );
a1768a <=( A233 and (not A232) );
a1771a <=( A236 and A234 );
a1772a <=( a1771a and a1768a );
a1775a <=( A168 and A169 );
a1778a <=( A166 and (not A167) );
a1779a <=( a1778a and a1775a );
a1782a <=( (not A233) and A232 );
a1785a <=( A235 and A234 );
a1786a <=( a1785a and a1782a );
a1789a <=( A168 and A169 );
a1792a <=( A166 and (not A167) );
a1793a <=( a1792a and a1789a );
a1796a <=( (not A233) and A232 );
a1799a <=( A236 and A234 );
a1800a <=( a1799a and a1796a );
a1803a <=( A200 and (not A199) );
a1806a <=( A202 and A201 );
a1807a <=( a1806a and a1803a );
a1810a <=( A233 and (not A232) );
a1814a <=( (not A236) and (not A235) );
a1815a <=( (not A234) and a1814a );
a1816a <=( a1815a and a1810a );
a1819a <=( A200 and (not A199) );
a1822a <=( A202 and A201 );
a1823a <=( a1822a and a1819a );
a1826a <=( (not A233) and A232 );
a1830a <=( (not A236) and (not A235) );
a1831a <=( (not A234) and a1830a );
a1832a <=( a1831a and a1826a );
a1835a <=( A200 and (not A199) );
a1838a <=( A203 and A201 );
a1839a <=( a1838a and a1835a );
a1842a <=( A233 and (not A232) );
a1846a <=( (not A236) and (not A235) );
a1847a <=( (not A234) and a1846a );
a1848a <=( a1847a and a1842a );
a1851a <=( A200 and (not A199) );
a1854a <=( A203 and A201 );
a1855a <=( a1854a and a1851a );
a1858a <=( (not A233) and A232 );
a1862a <=( (not A236) and (not A235) );
a1863a <=( (not A234) and a1862a );
a1864a <=( a1863a and a1858a );
a1867a <=( A200 and (not A199) );
a1870a <=( (not A202) and (not A201) );
a1871a <=( a1870a and a1867a );
a1874a <=( (not A232) and (not A203) );
a1878a <=( A235 and A234 );
a1879a <=( A233 and a1878a );
a1880a <=( a1879a and a1874a );
a1883a <=( A200 and (not A199) );
a1886a <=( (not A202) and (not A201) );
a1887a <=( a1886a and a1883a );
a1890a <=( (not A232) and (not A203) );
a1894a <=( A236 and A234 );
a1895a <=( A233 and a1894a );
a1896a <=( a1895a and a1890a );
a1899a <=( A200 and (not A199) );
a1902a <=( (not A202) and (not A201) );
a1903a <=( a1902a and a1899a );
a1906a <=( A232 and (not A203) );
a1910a <=( A235 and A234 );
a1911a <=( (not A233) and a1910a );
a1912a <=( a1911a and a1906a );
a1915a <=( A200 and (not A199) );
a1918a <=( (not A202) and (not A201) );
a1919a <=( a1918a and a1915a );
a1922a <=( A232 and (not A203) );
a1926a <=( A236 and A234 );
a1927a <=( (not A233) and a1926a );
a1928a <=( a1927a and a1922a );
a1931a <=( (not A200) and A199 );
a1934a <=( A202 and A201 );
a1935a <=( a1934a and a1931a );
a1938a <=( A233 and (not A232) );
a1942a <=( (not A236) and (not A235) );
a1943a <=( (not A234) and a1942a );
a1944a <=( a1943a and a1938a );
a1947a <=( (not A200) and A199 );
a1950a <=( A202 and A201 );
a1951a <=( a1950a and a1947a );
a1954a <=( (not A233) and A232 );
a1958a <=( (not A236) and (not A235) );
a1959a <=( (not A234) and a1958a );
a1960a <=( a1959a and a1954a );
a1963a <=( (not A200) and A199 );
a1966a <=( A203 and A201 );
a1967a <=( a1966a and a1963a );
a1970a <=( A233 and (not A232) );
a1974a <=( (not A236) and (not A235) );
a1975a <=( (not A234) and a1974a );
a1976a <=( a1975a and a1970a );
a1979a <=( (not A200) and A199 );
a1982a <=( A203 and A201 );
a1983a <=( a1982a and a1979a );
a1986a <=( (not A233) and A232 );
a1990a <=( (not A236) and (not A235) );
a1991a <=( (not A234) and a1990a );
a1992a <=( a1991a and a1986a );
a1995a <=( (not A200) and A199 );
a1998a <=( (not A202) and (not A201) );
a1999a <=( a1998a and a1995a );
a2002a <=( (not A232) and (not A203) );
a2006a <=( A235 and A234 );
a2007a <=( A233 and a2006a );
a2008a <=( a2007a and a2002a );
a2011a <=( (not A200) and A199 );
a2014a <=( (not A202) and (not A201) );
a2015a <=( a2014a and a2011a );
a2018a <=( (not A232) and (not A203) );
a2022a <=( A236 and A234 );
a2023a <=( A233 and a2022a );
a2024a <=( a2023a and a2018a );
a2027a <=( (not A200) and A199 );
a2030a <=( (not A202) and (not A201) );
a2031a <=( a2030a and a2027a );
a2034a <=( A232 and (not A203) );
a2038a <=( A235 and A234 );
a2039a <=( (not A233) and a2038a );
a2040a <=( a2039a and a2034a );
a2043a <=( (not A200) and A199 );
a2046a <=( (not A202) and (not A201) );
a2047a <=( a2046a and a2043a );
a2050a <=( A232 and (not A203) );
a2054a <=( A236 and A234 );
a2055a <=( (not A233) and a2054a );
a2056a <=( a2055a and a2050a );
a2059a <=( A168 and (not A170) );
a2062a <=( (not A166) and A167 );
a2063a <=( a2062a and a2059a );
a2066a <=( A233 and (not A232) );
a2070a <=( (not A236) and (not A235) );
a2071a <=( (not A234) and a2070a );
a2072a <=( a2071a and a2066a );
a2075a <=( A168 and (not A170) );
a2078a <=( (not A166) and A167 );
a2079a <=( a2078a and a2075a );
a2082a <=( (not A233) and A232 );
a2086a <=( (not A236) and (not A235) );
a2087a <=( (not A234) and a2086a );
a2088a <=( a2087a and a2082a );
a2091a <=( A168 and (not A170) );
a2094a <=( A166 and (not A167) );
a2095a <=( a2094a and a2091a );
a2098a <=( A233 and (not A232) );
a2102a <=( (not A236) and (not A235) );
a2103a <=( (not A234) and a2102a );
a2104a <=( a2103a and a2098a );
a2107a <=( A168 and (not A170) );
a2110a <=( A166 and (not A167) );
a2111a <=( a2110a and a2107a );
a2114a <=( (not A233) and A232 );
a2118a <=( (not A236) and (not A235) );
a2119a <=( (not A234) and a2118a );
a2120a <=( a2119a and a2114a );
a2123a <=( A168 and A169 );
a2126a <=( (not A166) and A167 );
a2127a <=( a2126a and a2123a );
a2130a <=( A233 and (not A232) );
a2134a <=( (not A236) and (not A235) );
a2135a <=( (not A234) and a2134a );
a2136a <=( a2135a and a2130a );
a2139a <=( A168 and A169 );
a2142a <=( (not A166) and A167 );
a2143a <=( a2142a and a2139a );
a2146a <=( (not A233) and A232 );
a2150a <=( (not A236) and (not A235) );
a2151a <=( (not A234) and a2150a );
a2152a <=( a2151a and a2146a );
a2155a <=( A168 and A169 );
a2158a <=( A166 and (not A167) );
a2159a <=( a2158a and a2155a );
a2162a <=( A233 and (not A232) );
a2166a <=( (not A236) and (not A235) );
a2167a <=( (not A234) and a2166a );
a2168a <=( a2167a and a2162a );
a2171a <=( A168 and A169 );
a2174a <=( A166 and (not A167) );
a2175a <=( a2174a and a2171a );
a2178a <=( (not A233) and A232 );
a2182a <=( (not A236) and (not A235) );
a2183a <=( (not A234) and a2182a );
a2184a <=( a2183a and a2178a );
a2187a <=( (not A169) and A170 );
a2190a <=( A167 and (not A168) );
a2191a <=( a2190a and a2187a );
a2194a <=( (not A232) and (not A166) );
a2198a <=( A235 and A234 );
a2199a <=( A233 and a2198a );
a2200a <=( a2199a and a2194a );
a2203a <=( (not A169) and A170 );
a2206a <=( A167 and (not A168) );
a2207a <=( a2206a and a2203a );
a2210a <=( (not A232) and (not A166) );
a2214a <=( A236 and A234 );
a2215a <=( A233 and a2214a );
a2216a <=( a2215a and a2210a );
a2219a <=( (not A169) and A170 );
a2222a <=( A167 and (not A168) );
a2223a <=( a2222a and a2219a );
a2226a <=( A232 and (not A166) );
a2230a <=( A235 and A234 );
a2231a <=( (not A233) and a2230a );
a2232a <=( a2231a and a2226a );
a2235a <=( (not A169) and A170 );
a2238a <=( A167 and (not A168) );
a2239a <=( a2238a and a2235a );
a2242a <=( A232 and (not A166) );
a2246a <=( A236 and A234 );
a2247a <=( (not A233) and a2246a );
a2248a <=( a2247a and a2242a );
a2251a <=( (not A169) and A170 );
a2254a <=( (not A167) and (not A168) );
a2255a <=( a2254a and a2251a );
a2258a <=( (not A232) and A166 );
a2262a <=( A235 and A234 );
a2263a <=( A233 and a2262a );
a2264a <=( a2263a and a2258a );
a2267a <=( (not A169) and A170 );
a2270a <=( (not A167) and (not A168) );
a2271a <=( a2270a and a2267a );
a2274a <=( (not A232) and A166 );
a2278a <=( A236 and A234 );
a2279a <=( A233 and a2278a );
a2280a <=( a2279a and a2274a );
a2283a <=( (not A169) and A170 );
a2286a <=( (not A167) and (not A168) );
a2287a <=( a2286a and a2283a );
a2290a <=( A232 and A166 );
a2294a <=( A235 and A234 );
a2295a <=( (not A233) and a2294a );
a2296a <=( a2295a and a2290a );
a2299a <=( (not A169) and A170 );
a2302a <=( (not A167) and (not A168) );
a2303a <=( a2302a and a2299a );
a2306a <=( A232 and A166 );
a2310a <=( A236 and A234 );
a2311a <=( (not A233) and a2310a );
a2312a <=( a2311a and a2306a );
a2315a <=( A200 and (not A199) );
a2319a <=( (not A203) and (not A202) );
a2320a <=( (not A201) and a2319a );
a2321a <=( a2320a and a2315a );
a2324a <=( A233 and (not A232) );
a2328a <=( (not A236) and (not A235) );
a2329a <=( (not A234) and a2328a );
a2330a <=( a2329a and a2324a );
a2333a <=( A200 and (not A199) );
a2337a <=( (not A203) and (not A202) );
a2338a <=( (not A201) and a2337a );
a2339a <=( a2338a and a2333a );
a2342a <=( (not A233) and A232 );
a2346a <=( (not A236) and (not A235) );
a2347a <=( (not A234) and a2346a );
a2348a <=( a2347a and a2342a );
a2351a <=( (not A200) and A199 );
a2355a <=( (not A203) and (not A202) );
a2356a <=( (not A201) and a2355a );
a2357a <=( a2356a and a2351a );
a2360a <=( A233 and (not A232) );
a2364a <=( (not A236) and (not A235) );
a2365a <=( (not A234) and a2364a );
a2366a <=( a2365a and a2360a );
a2369a <=( (not A200) and A199 );
a2373a <=( (not A203) and (not A202) );
a2374a <=( (not A201) and a2373a );
a2375a <=( a2374a and a2369a );
a2378a <=( (not A233) and A232 );
a2382a <=( (not A236) and (not A235) );
a2383a <=( (not A234) and a2382a );
a2384a <=( a2383a and a2378a );
a2387a <=( A166 and A167 );
a2391a <=( A201 and A200 );
a2392a <=( (not A199) and a2391a );
a2393a <=( a2392a and a2387a );
a2396a <=( A298 and A202 );
a2400a <=( A301 and A300 );
a2401a <=( (not A299) and a2400a );
a2402a <=( a2401a and a2396a );
a2405a <=( A166 and A167 );
a2409a <=( A201 and A200 );
a2410a <=( (not A199) and a2409a );
a2411a <=( a2410a and a2405a );
a2414a <=( A298 and A202 );
a2418a <=( A302 and A300 );
a2419a <=( (not A299) and a2418a );
a2420a <=( a2419a and a2414a );
a2423a <=( A166 and A167 );
a2427a <=( A201 and A200 );
a2428a <=( (not A199) and a2427a );
a2429a <=( a2428a and a2423a );
a2432a <=( (not A298) and A202 );
a2436a <=( A301 and A300 );
a2437a <=( A299 and a2436a );
a2438a <=( a2437a and a2432a );
a2441a <=( A166 and A167 );
a2445a <=( A201 and A200 );
a2446a <=( (not A199) and a2445a );
a2447a <=( a2446a and a2441a );
a2450a <=( (not A298) and A202 );
a2454a <=( A302 and A300 );
a2455a <=( A299 and a2454a );
a2456a <=( a2455a and a2450a );
a2459a <=( A166 and A167 );
a2463a <=( A201 and A200 );
a2464a <=( (not A199) and a2463a );
a2465a <=( a2464a and a2459a );
a2468a <=( A298 and A203 );
a2472a <=( A301 and A300 );
a2473a <=( (not A299) and a2472a );
a2474a <=( a2473a and a2468a );
a2477a <=( A166 and A167 );
a2481a <=( A201 and A200 );
a2482a <=( (not A199) and a2481a );
a2483a <=( a2482a and a2477a );
a2486a <=( A298 and A203 );
a2490a <=( A302 and A300 );
a2491a <=( (not A299) and a2490a );
a2492a <=( a2491a and a2486a );
a2495a <=( A166 and A167 );
a2499a <=( A201 and A200 );
a2500a <=( (not A199) and a2499a );
a2501a <=( a2500a and a2495a );
a2504a <=( (not A298) and A203 );
a2508a <=( A301 and A300 );
a2509a <=( A299 and a2508a );
a2510a <=( a2509a and a2504a );
a2513a <=( A166 and A167 );
a2517a <=( A201 and A200 );
a2518a <=( (not A199) and a2517a );
a2519a <=( a2518a and a2513a );
a2522a <=( (not A298) and A203 );
a2526a <=( A302 and A300 );
a2527a <=( A299 and a2526a );
a2528a <=( a2527a and a2522a );
a2531a <=( A166 and A167 );
a2535a <=( A201 and (not A200) );
a2536a <=( A199 and a2535a );
a2537a <=( a2536a and a2531a );
a2540a <=( A298 and A202 );
a2544a <=( A301 and A300 );
a2545a <=( (not A299) and a2544a );
a2546a <=( a2545a and a2540a );
a2549a <=( A166 and A167 );
a2553a <=( A201 and (not A200) );
a2554a <=( A199 and a2553a );
a2555a <=( a2554a and a2549a );
a2558a <=( A298 and A202 );
a2562a <=( A302 and A300 );
a2563a <=( (not A299) and a2562a );
a2564a <=( a2563a and a2558a );
a2567a <=( A166 and A167 );
a2571a <=( A201 and (not A200) );
a2572a <=( A199 and a2571a );
a2573a <=( a2572a and a2567a );
a2576a <=( (not A298) and A202 );
a2580a <=( A301 and A300 );
a2581a <=( A299 and a2580a );
a2582a <=( a2581a and a2576a );
a2585a <=( A166 and A167 );
a2589a <=( A201 and (not A200) );
a2590a <=( A199 and a2589a );
a2591a <=( a2590a and a2585a );
a2594a <=( (not A298) and A202 );
a2598a <=( A302 and A300 );
a2599a <=( A299 and a2598a );
a2600a <=( a2599a and a2594a );
a2603a <=( A166 and A167 );
a2607a <=( A201 and (not A200) );
a2608a <=( A199 and a2607a );
a2609a <=( a2608a and a2603a );
a2612a <=( A298 and A203 );
a2616a <=( A301 and A300 );
a2617a <=( (not A299) and a2616a );
a2618a <=( a2617a and a2612a );
a2621a <=( A166 and A167 );
a2625a <=( A201 and (not A200) );
a2626a <=( A199 and a2625a );
a2627a <=( a2626a and a2621a );
a2630a <=( A298 and A203 );
a2634a <=( A302 and A300 );
a2635a <=( (not A299) and a2634a );
a2636a <=( a2635a and a2630a );
a2639a <=( A166 and A167 );
a2643a <=( A201 and (not A200) );
a2644a <=( A199 and a2643a );
a2645a <=( a2644a and a2639a );
a2648a <=( (not A298) and A203 );
a2652a <=( A301 and A300 );
a2653a <=( A299 and a2652a );
a2654a <=( a2653a and a2648a );
a2657a <=( A166 and A167 );
a2661a <=( A201 and (not A200) );
a2662a <=( A199 and a2661a );
a2663a <=( a2662a and a2657a );
a2666a <=( (not A298) and A203 );
a2670a <=( A302 and A300 );
a2671a <=( A299 and a2670a );
a2672a <=( a2671a and a2666a );
a2675a <=( (not A166) and (not A167) );
a2679a <=( A201 and A200 );
a2680a <=( (not A199) and a2679a );
a2681a <=( a2680a and a2675a );
a2684a <=( A298 and A202 );
a2688a <=( A301 and A300 );
a2689a <=( (not A299) and a2688a );
a2690a <=( a2689a and a2684a );
a2693a <=( (not A166) and (not A167) );
a2697a <=( A201 and A200 );
a2698a <=( (not A199) and a2697a );
a2699a <=( a2698a and a2693a );
a2702a <=( A298 and A202 );
a2706a <=( A302 and A300 );
a2707a <=( (not A299) and a2706a );
a2708a <=( a2707a and a2702a );
a2711a <=( (not A166) and (not A167) );
a2715a <=( A201 and A200 );
a2716a <=( (not A199) and a2715a );
a2717a <=( a2716a and a2711a );
a2720a <=( (not A298) and A202 );
a2724a <=( A301 and A300 );
a2725a <=( A299 and a2724a );
a2726a <=( a2725a and a2720a );
a2729a <=( (not A166) and (not A167) );
a2733a <=( A201 and A200 );
a2734a <=( (not A199) and a2733a );
a2735a <=( a2734a and a2729a );
a2738a <=( (not A298) and A202 );
a2742a <=( A302 and A300 );
a2743a <=( A299 and a2742a );
a2744a <=( a2743a and a2738a );
a2747a <=( (not A166) and (not A167) );
a2751a <=( A201 and A200 );
a2752a <=( (not A199) and a2751a );
a2753a <=( a2752a and a2747a );
a2756a <=( A298 and A203 );
a2760a <=( A301 and A300 );
a2761a <=( (not A299) and a2760a );
a2762a <=( a2761a and a2756a );
a2765a <=( (not A166) and (not A167) );
a2769a <=( A201 and A200 );
a2770a <=( (not A199) and a2769a );
a2771a <=( a2770a and a2765a );
a2774a <=( A298 and A203 );
a2778a <=( A302 and A300 );
a2779a <=( (not A299) and a2778a );
a2780a <=( a2779a and a2774a );
a2783a <=( (not A166) and (not A167) );
a2787a <=( A201 and A200 );
a2788a <=( (not A199) and a2787a );
a2789a <=( a2788a and a2783a );
a2792a <=( (not A298) and A203 );
a2796a <=( A301 and A300 );
a2797a <=( A299 and a2796a );
a2798a <=( a2797a and a2792a );
a2801a <=( (not A166) and (not A167) );
a2805a <=( A201 and A200 );
a2806a <=( (not A199) and a2805a );
a2807a <=( a2806a and a2801a );
a2810a <=( (not A298) and A203 );
a2814a <=( A302 and A300 );
a2815a <=( A299 and a2814a );
a2816a <=( a2815a and a2810a );
a2819a <=( (not A166) and (not A167) );
a2823a <=( A201 and (not A200) );
a2824a <=( A199 and a2823a );
a2825a <=( a2824a and a2819a );
a2828a <=( A298 and A202 );
a2832a <=( A301 and A300 );
a2833a <=( (not A299) and a2832a );
a2834a <=( a2833a and a2828a );
a2837a <=( (not A166) and (not A167) );
a2841a <=( A201 and (not A200) );
a2842a <=( A199 and a2841a );
a2843a <=( a2842a and a2837a );
a2846a <=( A298 and A202 );
a2850a <=( A302 and A300 );
a2851a <=( (not A299) and a2850a );
a2852a <=( a2851a and a2846a );
a2855a <=( (not A166) and (not A167) );
a2859a <=( A201 and (not A200) );
a2860a <=( A199 and a2859a );
a2861a <=( a2860a and a2855a );
a2864a <=( (not A298) and A202 );
a2868a <=( A301 and A300 );
a2869a <=( A299 and a2868a );
a2870a <=( a2869a and a2864a );
a2873a <=( (not A166) and (not A167) );
a2877a <=( A201 and (not A200) );
a2878a <=( A199 and a2877a );
a2879a <=( a2878a and a2873a );
a2882a <=( (not A298) and A202 );
a2886a <=( A302 and A300 );
a2887a <=( A299 and a2886a );
a2888a <=( a2887a and a2882a );
a2891a <=( (not A166) and (not A167) );
a2895a <=( A201 and (not A200) );
a2896a <=( A199 and a2895a );
a2897a <=( a2896a and a2891a );
a2900a <=( A298 and A203 );
a2904a <=( A301 and A300 );
a2905a <=( (not A299) and a2904a );
a2906a <=( a2905a and a2900a );
a2909a <=( (not A166) and (not A167) );
a2913a <=( A201 and (not A200) );
a2914a <=( A199 and a2913a );
a2915a <=( a2914a and a2909a );
a2918a <=( A298 and A203 );
a2922a <=( A302 and A300 );
a2923a <=( (not A299) and a2922a );
a2924a <=( a2923a and a2918a );
a2927a <=( (not A166) and (not A167) );
a2931a <=( A201 and (not A200) );
a2932a <=( A199 and a2931a );
a2933a <=( a2932a and a2927a );
a2936a <=( (not A298) and A203 );
a2940a <=( A301 and A300 );
a2941a <=( A299 and a2940a );
a2942a <=( a2941a and a2936a );
a2945a <=( (not A166) and (not A167) );
a2949a <=( A201 and (not A200) );
a2950a <=( A199 and a2949a );
a2951a <=( a2950a and a2945a );
a2954a <=( (not A298) and A203 );
a2958a <=( A302 and A300 );
a2959a <=( A299 and a2958a );
a2960a <=( a2959a and a2954a );
a2963a <=( A168 and (not A170) );
a2967a <=( (not A201) and (not A166) );
a2968a <=( A167 and a2967a );
a2969a <=( a2968a and a2963a );
a2972a <=( A298 and A202 );
a2976a <=( A301 and A300 );
a2977a <=( (not A299) and a2976a );
a2978a <=( a2977a and a2972a );
a2981a <=( A168 and (not A170) );
a2985a <=( (not A201) and (not A166) );
a2986a <=( A167 and a2985a );
a2987a <=( a2986a and a2981a );
a2990a <=( A298 and A202 );
a2994a <=( A302 and A300 );
a2995a <=( (not A299) and a2994a );
a2996a <=( a2995a and a2990a );
a2999a <=( A168 and (not A170) );
a3003a <=( (not A201) and (not A166) );
a3004a <=( A167 and a3003a );
a3005a <=( a3004a and a2999a );
a3008a <=( (not A298) and A202 );
a3012a <=( A301 and A300 );
a3013a <=( A299 and a3012a );
a3014a <=( a3013a and a3008a );
a3017a <=( A168 and (not A170) );
a3021a <=( (not A201) and (not A166) );
a3022a <=( A167 and a3021a );
a3023a <=( a3022a and a3017a );
a3026a <=( (not A298) and A202 );
a3030a <=( A302 and A300 );
a3031a <=( A299 and a3030a );
a3032a <=( a3031a and a3026a );
a3035a <=( A168 and (not A170) );
a3039a <=( (not A201) and (not A166) );
a3040a <=( A167 and a3039a );
a3041a <=( a3040a and a3035a );
a3044a <=( A298 and A203 );
a3048a <=( A301 and A300 );
a3049a <=( (not A299) and a3048a );
a3050a <=( a3049a and a3044a );
a3053a <=( A168 and (not A170) );
a3057a <=( (not A201) and (not A166) );
a3058a <=( A167 and a3057a );
a3059a <=( a3058a and a3053a );
a3062a <=( A298 and A203 );
a3066a <=( A302 and A300 );
a3067a <=( (not A299) and a3066a );
a3068a <=( a3067a and a3062a );
a3071a <=( A168 and (not A170) );
a3075a <=( (not A201) and (not A166) );
a3076a <=( A167 and a3075a );
a3077a <=( a3076a and a3071a );
a3080a <=( (not A298) and A203 );
a3084a <=( A301 and A300 );
a3085a <=( A299 and a3084a );
a3086a <=( a3085a and a3080a );
a3089a <=( A168 and (not A170) );
a3093a <=( (not A201) and (not A166) );
a3094a <=( A167 and a3093a );
a3095a <=( a3094a and a3089a );
a3098a <=( (not A298) and A203 );
a3102a <=( A302 and A300 );
a3103a <=( A299 and a3102a );
a3104a <=( a3103a and a3098a );
a3107a <=( A168 and (not A170) );
a3111a <=( A199 and (not A166) );
a3112a <=( A167 and a3111a );
a3113a <=( a3112a and a3107a );
a3116a <=( A298 and A200 );
a3120a <=( A301 and A300 );
a3121a <=( (not A299) and a3120a );
a3122a <=( a3121a and a3116a );
a3125a <=( A168 and (not A170) );
a3129a <=( A199 and (not A166) );
a3130a <=( A167 and a3129a );
a3131a <=( a3130a and a3125a );
a3134a <=( A298 and A200 );
a3138a <=( A302 and A300 );
a3139a <=( (not A299) and a3138a );
a3140a <=( a3139a and a3134a );
a3143a <=( A168 and (not A170) );
a3147a <=( A199 and (not A166) );
a3148a <=( A167 and a3147a );
a3149a <=( a3148a and a3143a );
a3152a <=( (not A298) and A200 );
a3156a <=( A301 and A300 );
a3157a <=( A299 and a3156a );
a3158a <=( a3157a and a3152a );
a3161a <=( A168 and (not A170) );
a3165a <=( A199 and (not A166) );
a3166a <=( A167 and a3165a );
a3167a <=( a3166a and a3161a );
a3170a <=( (not A298) and A200 );
a3174a <=( A302 and A300 );
a3175a <=( A299 and a3174a );
a3176a <=( a3175a and a3170a );
a3179a <=( A168 and (not A170) );
a3183a <=( (not A199) and (not A166) );
a3184a <=( A167 and a3183a );
a3185a <=( a3184a and a3179a );
a3188a <=( A298 and (not A200) );
a3192a <=( A301 and A300 );
a3193a <=( (not A299) and a3192a );
a3194a <=( a3193a and a3188a );
a3197a <=( A168 and (not A170) );
a3201a <=( (not A199) and (not A166) );
a3202a <=( A167 and a3201a );
a3203a <=( a3202a and a3197a );
a3206a <=( A298 and (not A200) );
a3210a <=( A302 and A300 );
a3211a <=( (not A299) and a3210a );
a3212a <=( a3211a and a3206a );
a3215a <=( A168 and (not A170) );
a3219a <=( (not A199) and (not A166) );
a3220a <=( A167 and a3219a );
a3221a <=( a3220a and a3215a );
a3224a <=( (not A298) and (not A200) );
a3228a <=( A301 and A300 );
a3229a <=( A299 and a3228a );
a3230a <=( a3229a and a3224a );
a3233a <=( A168 and (not A170) );
a3237a <=( (not A199) and (not A166) );
a3238a <=( A167 and a3237a );
a3239a <=( a3238a and a3233a );
a3242a <=( (not A298) and (not A200) );
a3246a <=( A302 and A300 );
a3247a <=( A299 and a3246a );
a3248a <=( a3247a and a3242a );
a3251a <=( A168 and (not A170) );
a3255a <=( (not A201) and A166 );
a3256a <=( (not A167) and a3255a );
a3257a <=( a3256a and a3251a );
a3260a <=( A298 and A202 );
a3264a <=( A301 and A300 );
a3265a <=( (not A299) and a3264a );
a3266a <=( a3265a and a3260a );
a3269a <=( A168 and (not A170) );
a3273a <=( (not A201) and A166 );
a3274a <=( (not A167) and a3273a );
a3275a <=( a3274a and a3269a );
a3278a <=( A298 and A202 );
a3282a <=( A302 and A300 );
a3283a <=( (not A299) and a3282a );
a3284a <=( a3283a and a3278a );
a3287a <=( A168 and (not A170) );
a3291a <=( (not A201) and A166 );
a3292a <=( (not A167) and a3291a );
a3293a <=( a3292a and a3287a );
a3296a <=( (not A298) and A202 );
a3300a <=( A301 and A300 );
a3301a <=( A299 and a3300a );
a3302a <=( a3301a and a3296a );
a3305a <=( A168 and (not A170) );
a3309a <=( (not A201) and A166 );
a3310a <=( (not A167) and a3309a );
a3311a <=( a3310a and a3305a );
a3314a <=( (not A298) and A202 );
a3318a <=( A302 and A300 );
a3319a <=( A299 and a3318a );
a3320a <=( a3319a and a3314a );
a3323a <=( A168 and (not A170) );
a3327a <=( (not A201) and A166 );
a3328a <=( (not A167) and a3327a );
a3329a <=( a3328a and a3323a );
a3332a <=( A298 and A203 );
a3336a <=( A301 and A300 );
a3337a <=( (not A299) and a3336a );
a3338a <=( a3337a and a3332a );
a3341a <=( A168 and (not A170) );
a3345a <=( (not A201) and A166 );
a3346a <=( (not A167) and a3345a );
a3347a <=( a3346a and a3341a );
a3350a <=( A298 and A203 );
a3354a <=( A302 and A300 );
a3355a <=( (not A299) and a3354a );
a3356a <=( a3355a and a3350a );
a3359a <=( A168 and (not A170) );
a3363a <=( (not A201) and A166 );
a3364a <=( (not A167) and a3363a );
a3365a <=( a3364a and a3359a );
a3368a <=( (not A298) and A203 );
a3372a <=( A301 and A300 );
a3373a <=( A299 and a3372a );
a3374a <=( a3373a and a3368a );
a3377a <=( A168 and (not A170) );
a3381a <=( (not A201) and A166 );
a3382a <=( (not A167) and a3381a );
a3383a <=( a3382a and a3377a );
a3386a <=( (not A298) and A203 );
a3390a <=( A302 and A300 );
a3391a <=( A299 and a3390a );
a3392a <=( a3391a and a3386a );
a3395a <=( A168 and (not A170) );
a3399a <=( A199 and A166 );
a3400a <=( (not A167) and a3399a );
a3401a <=( a3400a and a3395a );
a3404a <=( A298 and A200 );
a3408a <=( A301 and A300 );
a3409a <=( (not A299) and a3408a );
a3410a <=( a3409a and a3404a );
a3413a <=( A168 and (not A170) );
a3417a <=( A199 and A166 );
a3418a <=( (not A167) and a3417a );
a3419a <=( a3418a and a3413a );
a3422a <=( A298 and A200 );
a3426a <=( A302 and A300 );
a3427a <=( (not A299) and a3426a );
a3428a <=( a3427a and a3422a );
a3431a <=( A168 and (not A170) );
a3435a <=( A199 and A166 );
a3436a <=( (not A167) and a3435a );
a3437a <=( a3436a and a3431a );
a3440a <=( (not A298) and A200 );
a3444a <=( A301 and A300 );
a3445a <=( A299 and a3444a );
a3446a <=( a3445a and a3440a );
a3449a <=( A168 and (not A170) );
a3453a <=( A199 and A166 );
a3454a <=( (not A167) and a3453a );
a3455a <=( a3454a and a3449a );
a3458a <=( (not A298) and A200 );
a3462a <=( A302 and A300 );
a3463a <=( A299 and a3462a );
a3464a <=( a3463a and a3458a );
a3467a <=( A168 and (not A170) );
a3471a <=( (not A199) and A166 );
a3472a <=( (not A167) and a3471a );
a3473a <=( a3472a and a3467a );
a3476a <=( A298 and (not A200) );
a3480a <=( A301 and A300 );
a3481a <=( (not A299) and a3480a );
a3482a <=( a3481a and a3476a );
a3485a <=( A168 and (not A170) );
a3489a <=( (not A199) and A166 );
a3490a <=( (not A167) and a3489a );
a3491a <=( a3490a and a3485a );
a3494a <=( A298 and (not A200) );
a3498a <=( A302 and A300 );
a3499a <=( (not A299) and a3498a );
a3500a <=( a3499a and a3494a );
a3503a <=( A168 and (not A170) );
a3507a <=( (not A199) and A166 );
a3508a <=( (not A167) and a3507a );
a3509a <=( a3508a and a3503a );
a3512a <=( (not A298) and (not A200) );
a3516a <=( A301 and A300 );
a3517a <=( A299 and a3516a );
a3518a <=( a3517a and a3512a );
a3521a <=( A168 and (not A170) );
a3525a <=( (not A199) and A166 );
a3526a <=( (not A167) and a3525a );
a3527a <=( a3526a and a3521a );
a3530a <=( (not A298) and (not A200) );
a3534a <=( A302 and A300 );
a3535a <=( A299 and a3534a );
a3536a <=( a3535a and a3530a );
a3539a <=( (not A168) and (not A170) );
a3543a <=( A201 and A200 );
a3544a <=( (not A199) and a3543a );
a3545a <=( a3544a and a3539a );
a3548a <=( A298 and A202 );
a3552a <=( A301 and A300 );
a3553a <=( (not A299) and a3552a );
a3554a <=( a3553a and a3548a );
a3557a <=( (not A168) and (not A170) );
a3561a <=( A201 and A200 );
a3562a <=( (not A199) and a3561a );
a3563a <=( a3562a and a3557a );
a3566a <=( A298 and A202 );
a3570a <=( A302 and A300 );
a3571a <=( (not A299) and a3570a );
a3572a <=( a3571a and a3566a );
a3575a <=( (not A168) and (not A170) );
a3579a <=( A201 and A200 );
a3580a <=( (not A199) and a3579a );
a3581a <=( a3580a and a3575a );
a3584a <=( (not A298) and A202 );
a3588a <=( A301 and A300 );
a3589a <=( A299 and a3588a );
a3590a <=( a3589a and a3584a );
a3593a <=( (not A168) and (not A170) );
a3597a <=( A201 and A200 );
a3598a <=( (not A199) and a3597a );
a3599a <=( a3598a and a3593a );
a3602a <=( (not A298) and A202 );
a3606a <=( A302 and A300 );
a3607a <=( A299 and a3606a );
a3608a <=( a3607a and a3602a );
a3611a <=( (not A168) and (not A170) );
a3615a <=( A201 and A200 );
a3616a <=( (not A199) and a3615a );
a3617a <=( a3616a and a3611a );
a3620a <=( A298 and A203 );
a3624a <=( A301 and A300 );
a3625a <=( (not A299) and a3624a );
a3626a <=( a3625a and a3620a );
a3629a <=( (not A168) and (not A170) );
a3633a <=( A201 and A200 );
a3634a <=( (not A199) and a3633a );
a3635a <=( a3634a and a3629a );
a3638a <=( A298 and A203 );
a3642a <=( A302 and A300 );
a3643a <=( (not A299) and a3642a );
a3644a <=( a3643a and a3638a );
a3647a <=( (not A168) and (not A170) );
a3651a <=( A201 and A200 );
a3652a <=( (not A199) and a3651a );
a3653a <=( a3652a and a3647a );
a3656a <=( (not A298) and A203 );
a3660a <=( A301 and A300 );
a3661a <=( A299 and a3660a );
a3662a <=( a3661a and a3656a );
a3665a <=( (not A168) and (not A170) );
a3669a <=( A201 and A200 );
a3670a <=( (not A199) and a3669a );
a3671a <=( a3670a and a3665a );
a3674a <=( (not A298) and A203 );
a3678a <=( A302 and A300 );
a3679a <=( A299 and a3678a );
a3680a <=( a3679a and a3674a );
a3683a <=( (not A168) and (not A170) );
a3687a <=( A201 and (not A200) );
a3688a <=( A199 and a3687a );
a3689a <=( a3688a and a3683a );
a3692a <=( A298 and A202 );
a3696a <=( A301 and A300 );
a3697a <=( (not A299) and a3696a );
a3698a <=( a3697a and a3692a );
a3701a <=( (not A168) and (not A170) );
a3705a <=( A201 and (not A200) );
a3706a <=( A199 and a3705a );
a3707a <=( a3706a and a3701a );
a3710a <=( A298 and A202 );
a3714a <=( A302 and A300 );
a3715a <=( (not A299) and a3714a );
a3716a <=( a3715a and a3710a );
a3719a <=( (not A168) and (not A170) );
a3723a <=( A201 and (not A200) );
a3724a <=( A199 and a3723a );
a3725a <=( a3724a and a3719a );
a3728a <=( (not A298) and A202 );
a3732a <=( A301 and A300 );
a3733a <=( A299 and a3732a );
a3734a <=( a3733a and a3728a );
a3737a <=( (not A168) and (not A170) );
a3741a <=( A201 and (not A200) );
a3742a <=( A199 and a3741a );
a3743a <=( a3742a and a3737a );
a3746a <=( (not A298) and A202 );
a3750a <=( A302 and A300 );
a3751a <=( A299 and a3750a );
a3752a <=( a3751a and a3746a );
a3755a <=( (not A168) and (not A170) );
a3759a <=( A201 and (not A200) );
a3760a <=( A199 and a3759a );
a3761a <=( a3760a and a3755a );
a3764a <=( A298 and A203 );
a3768a <=( A301 and A300 );
a3769a <=( (not A299) and a3768a );
a3770a <=( a3769a and a3764a );
a3773a <=( (not A168) and (not A170) );
a3777a <=( A201 and (not A200) );
a3778a <=( A199 and a3777a );
a3779a <=( a3778a and a3773a );
a3782a <=( A298 and A203 );
a3786a <=( A302 and A300 );
a3787a <=( (not A299) and a3786a );
a3788a <=( a3787a and a3782a );
a3791a <=( (not A168) and (not A170) );
a3795a <=( A201 and (not A200) );
a3796a <=( A199 and a3795a );
a3797a <=( a3796a and a3791a );
a3800a <=( (not A298) and A203 );
a3804a <=( A301 and A300 );
a3805a <=( A299 and a3804a );
a3806a <=( a3805a and a3800a );
a3809a <=( (not A168) and (not A170) );
a3813a <=( A201 and (not A200) );
a3814a <=( A199 and a3813a );
a3815a <=( a3814a and a3809a );
a3818a <=( (not A298) and A203 );
a3822a <=( A302 and A300 );
a3823a <=( A299 and a3822a );
a3824a <=( a3823a and a3818a );
a3827a <=( A168 and A169 );
a3831a <=( (not A201) and (not A166) );
a3832a <=( A167 and a3831a );
a3833a <=( a3832a and a3827a );
a3836a <=( A298 and A202 );
a3840a <=( A301 and A300 );
a3841a <=( (not A299) and a3840a );
a3842a <=( a3841a and a3836a );
a3845a <=( A168 and A169 );
a3849a <=( (not A201) and (not A166) );
a3850a <=( A167 and a3849a );
a3851a <=( a3850a and a3845a );
a3854a <=( A298 and A202 );
a3858a <=( A302 and A300 );
a3859a <=( (not A299) and a3858a );
a3860a <=( a3859a and a3854a );
a3863a <=( A168 and A169 );
a3867a <=( (not A201) and (not A166) );
a3868a <=( A167 and a3867a );
a3869a <=( a3868a and a3863a );
a3872a <=( (not A298) and A202 );
a3876a <=( A301 and A300 );
a3877a <=( A299 and a3876a );
a3878a <=( a3877a and a3872a );
a3881a <=( A168 and A169 );
a3885a <=( (not A201) and (not A166) );
a3886a <=( A167 and a3885a );
a3887a <=( a3886a and a3881a );
a3890a <=( (not A298) and A202 );
a3894a <=( A302 and A300 );
a3895a <=( A299 and a3894a );
a3896a <=( a3895a and a3890a );
a3899a <=( A168 and A169 );
a3903a <=( (not A201) and (not A166) );
a3904a <=( A167 and a3903a );
a3905a <=( a3904a and a3899a );
a3908a <=( A298 and A203 );
a3912a <=( A301 and A300 );
a3913a <=( (not A299) and a3912a );
a3914a <=( a3913a and a3908a );
a3917a <=( A168 and A169 );
a3921a <=( (not A201) and (not A166) );
a3922a <=( A167 and a3921a );
a3923a <=( a3922a and a3917a );
a3926a <=( A298 and A203 );
a3930a <=( A302 and A300 );
a3931a <=( (not A299) and a3930a );
a3932a <=( a3931a and a3926a );
a3935a <=( A168 and A169 );
a3939a <=( (not A201) and (not A166) );
a3940a <=( A167 and a3939a );
a3941a <=( a3940a and a3935a );
a3944a <=( (not A298) and A203 );
a3948a <=( A301 and A300 );
a3949a <=( A299 and a3948a );
a3950a <=( a3949a and a3944a );
a3953a <=( A168 and A169 );
a3957a <=( (not A201) and (not A166) );
a3958a <=( A167 and a3957a );
a3959a <=( a3958a and a3953a );
a3962a <=( (not A298) and A203 );
a3966a <=( A302 and A300 );
a3967a <=( A299 and a3966a );
a3968a <=( a3967a and a3962a );
a3971a <=( A168 and A169 );
a3975a <=( A199 and (not A166) );
a3976a <=( A167 and a3975a );
a3977a <=( a3976a and a3971a );
a3980a <=( A298 and A200 );
a3984a <=( A301 and A300 );
a3985a <=( (not A299) and a3984a );
a3986a <=( a3985a and a3980a );
a3989a <=( A168 and A169 );
a3993a <=( A199 and (not A166) );
a3994a <=( A167 and a3993a );
a3995a <=( a3994a and a3989a );
a3998a <=( A298 and A200 );
a4002a <=( A302 and A300 );
a4003a <=( (not A299) and a4002a );
a4004a <=( a4003a and a3998a );
a4007a <=( A168 and A169 );
a4011a <=( A199 and (not A166) );
a4012a <=( A167 and a4011a );
a4013a <=( a4012a and a4007a );
a4016a <=( (not A298) and A200 );
a4020a <=( A301 and A300 );
a4021a <=( A299 and a4020a );
a4022a <=( a4021a and a4016a );
a4025a <=( A168 and A169 );
a4029a <=( A199 and (not A166) );
a4030a <=( A167 and a4029a );
a4031a <=( a4030a and a4025a );
a4034a <=( (not A298) and A200 );
a4038a <=( A302 and A300 );
a4039a <=( A299 and a4038a );
a4040a <=( a4039a and a4034a );
a4043a <=( A168 and A169 );
a4047a <=( (not A199) and (not A166) );
a4048a <=( A167 and a4047a );
a4049a <=( a4048a and a4043a );
a4052a <=( A298 and (not A200) );
a4056a <=( A301 and A300 );
a4057a <=( (not A299) and a4056a );
a4058a <=( a4057a and a4052a );
a4061a <=( A168 and A169 );
a4065a <=( (not A199) and (not A166) );
a4066a <=( A167 and a4065a );
a4067a <=( a4066a and a4061a );
a4070a <=( A298 and (not A200) );
a4074a <=( A302 and A300 );
a4075a <=( (not A299) and a4074a );
a4076a <=( a4075a and a4070a );
a4079a <=( A168 and A169 );
a4083a <=( (not A199) and (not A166) );
a4084a <=( A167 and a4083a );
a4085a <=( a4084a and a4079a );
a4088a <=( (not A298) and (not A200) );
a4092a <=( A301 and A300 );
a4093a <=( A299 and a4092a );
a4094a <=( a4093a and a4088a );
a4097a <=( A168 and A169 );
a4101a <=( (not A199) and (not A166) );
a4102a <=( A167 and a4101a );
a4103a <=( a4102a and a4097a );
a4106a <=( (not A298) and (not A200) );
a4110a <=( A302 and A300 );
a4111a <=( A299 and a4110a );
a4112a <=( a4111a and a4106a );
a4115a <=( A168 and A169 );
a4119a <=( (not A201) and A166 );
a4120a <=( (not A167) and a4119a );
a4121a <=( a4120a and a4115a );
a4124a <=( A298 and A202 );
a4128a <=( A301 and A300 );
a4129a <=( (not A299) and a4128a );
a4130a <=( a4129a and a4124a );
a4133a <=( A168 and A169 );
a4137a <=( (not A201) and A166 );
a4138a <=( (not A167) and a4137a );
a4139a <=( a4138a and a4133a );
a4142a <=( A298 and A202 );
a4146a <=( A302 and A300 );
a4147a <=( (not A299) and a4146a );
a4148a <=( a4147a and a4142a );
a4151a <=( A168 and A169 );
a4155a <=( (not A201) and A166 );
a4156a <=( (not A167) and a4155a );
a4157a <=( a4156a and a4151a );
a4160a <=( (not A298) and A202 );
a4164a <=( A301 and A300 );
a4165a <=( A299 and a4164a );
a4166a <=( a4165a and a4160a );
a4169a <=( A168 and A169 );
a4173a <=( (not A201) and A166 );
a4174a <=( (not A167) and a4173a );
a4175a <=( a4174a and a4169a );
a4178a <=( (not A298) and A202 );
a4182a <=( A302 and A300 );
a4183a <=( A299 and a4182a );
a4184a <=( a4183a and a4178a );
a4187a <=( A168 and A169 );
a4191a <=( (not A201) and A166 );
a4192a <=( (not A167) and a4191a );
a4193a <=( a4192a and a4187a );
a4196a <=( A298 and A203 );
a4200a <=( A301 and A300 );
a4201a <=( (not A299) and a4200a );
a4202a <=( a4201a and a4196a );
a4205a <=( A168 and A169 );
a4209a <=( (not A201) and A166 );
a4210a <=( (not A167) and a4209a );
a4211a <=( a4210a and a4205a );
a4214a <=( A298 and A203 );
a4218a <=( A302 and A300 );
a4219a <=( (not A299) and a4218a );
a4220a <=( a4219a and a4214a );
a4223a <=( A168 and A169 );
a4227a <=( (not A201) and A166 );
a4228a <=( (not A167) and a4227a );
a4229a <=( a4228a and a4223a );
a4232a <=( (not A298) and A203 );
a4236a <=( A301 and A300 );
a4237a <=( A299 and a4236a );
a4238a <=( a4237a and a4232a );
a4241a <=( A168 and A169 );
a4245a <=( (not A201) and A166 );
a4246a <=( (not A167) and a4245a );
a4247a <=( a4246a and a4241a );
a4250a <=( (not A298) and A203 );
a4254a <=( A302 and A300 );
a4255a <=( A299 and a4254a );
a4256a <=( a4255a and a4250a );
a4259a <=( A168 and A169 );
a4263a <=( A199 and A166 );
a4264a <=( (not A167) and a4263a );
a4265a <=( a4264a and a4259a );
a4268a <=( A298 and A200 );
a4272a <=( A301 and A300 );
a4273a <=( (not A299) and a4272a );
a4274a <=( a4273a and a4268a );
a4277a <=( A168 and A169 );
a4281a <=( A199 and A166 );
a4282a <=( (not A167) and a4281a );
a4283a <=( a4282a and a4277a );
a4286a <=( A298 and A200 );
a4290a <=( A302 and A300 );
a4291a <=( (not A299) and a4290a );
a4292a <=( a4291a and a4286a );
a4295a <=( A168 and A169 );
a4299a <=( A199 and A166 );
a4300a <=( (not A167) and a4299a );
a4301a <=( a4300a and a4295a );
a4304a <=( (not A298) and A200 );
a4308a <=( A301 and A300 );
a4309a <=( A299 and a4308a );
a4310a <=( a4309a and a4304a );
a4313a <=( A168 and A169 );
a4317a <=( A199 and A166 );
a4318a <=( (not A167) and a4317a );
a4319a <=( a4318a and a4313a );
a4322a <=( (not A298) and A200 );
a4326a <=( A302 and A300 );
a4327a <=( A299 and a4326a );
a4328a <=( a4327a and a4322a );
a4331a <=( A168 and A169 );
a4335a <=( (not A199) and A166 );
a4336a <=( (not A167) and a4335a );
a4337a <=( a4336a and a4331a );
a4340a <=( A298 and (not A200) );
a4344a <=( A301 and A300 );
a4345a <=( (not A299) and a4344a );
a4346a <=( a4345a and a4340a );
a4349a <=( A168 and A169 );
a4353a <=( (not A199) and A166 );
a4354a <=( (not A167) and a4353a );
a4355a <=( a4354a and a4349a );
a4358a <=( A298 and (not A200) );
a4362a <=( A302 and A300 );
a4363a <=( (not A299) and a4362a );
a4364a <=( a4363a and a4358a );
a4367a <=( A168 and A169 );
a4371a <=( (not A199) and A166 );
a4372a <=( (not A167) and a4371a );
a4373a <=( a4372a and a4367a );
a4376a <=( (not A298) and (not A200) );
a4380a <=( A301 and A300 );
a4381a <=( A299 and a4380a );
a4382a <=( a4381a and a4376a );
a4385a <=( A168 and A169 );
a4389a <=( (not A199) and A166 );
a4390a <=( (not A167) and a4389a );
a4391a <=( a4390a and a4385a );
a4394a <=( (not A298) and (not A200) );
a4398a <=( A302 and A300 );
a4399a <=( A299 and a4398a );
a4400a <=( a4399a and a4394a );
a4403a <=( (not A168) and A169 );
a4407a <=( A201 and A200 );
a4408a <=( (not A199) and a4407a );
a4409a <=( a4408a and a4403a );
a4412a <=( A298 and A202 );
a4416a <=( A301 and A300 );
a4417a <=( (not A299) and a4416a );
a4418a <=( a4417a and a4412a );
a4421a <=( (not A168) and A169 );
a4425a <=( A201 and A200 );
a4426a <=( (not A199) and a4425a );
a4427a <=( a4426a and a4421a );
a4430a <=( A298 and A202 );
a4434a <=( A302 and A300 );
a4435a <=( (not A299) and a4434a );
a4436a <=( a4435a and a4430a );
a4439a <=( (not A168) and A169 );
a4443a <=( A201 and A200 );
a4444a <=( (not A199) and a4443a );
a4445a <=( a4444a and a4439a );
a4448a <=( (not A298) and A202 );
a4452a <=( A301 and A300 );
a4453a <=( A299 and a4452a );
a4454a <=( a4453a and a4448a );
a4457a <=( (not A168) and A169 );
a4461a <=( A201 and A200 );
a4462a <=( (not A199) and a4461a );
a4463a <=( a4462a and a4457a );
a4466a <=( (not A298) and A202 );
a4470a <=( A302 and A300 );
a4471a <=( A299 and a4470a );
a4472a <=( a4471a and a4466a );
a4475a <=( (not A168) and A169 );
a4479a <=( A201 and A200 );
a4480a <=( (not A199) and a4479a );
a4481a <=( a4480a and a4475a );
a4484a <=( A298 and A203 );
a4488a <=( A301 and A300 );
a4489a <=( (not A299) and a4488a );
a4490a <=( a4489a and a4484a );
a4493a <=( (not A168) and A169 );
a4497a <=( A201 and A200 );
a4498a <=( (not A199) and a4497a );
a4499a <=( a4498a and a4493a );
a4502a <=( A298 and A203 );
a4506a <=( A302 and A300 );
a4507a <=( (not A299) and a4506a );
a4508a <=( a4507a and a4502a );
a4511a <=( (not A168) and A169 );
a4515a <=( A201 and A200 );
a4516a <=( (not A199) and a4515a );
a4517a <=( a4516a and a4511a );
a4520a <=( (not A298) and A203 );
a4524a <=( A301 and A300 );
a4525a <=( A299 and a4524a );
a4526a <=( a4525a and a4520a );
a4529a <=( (not A168) and A169 );
a4533a <=( A201 and A200 );
a4534a <=( (not A199) and a4533a );
a4535a <=( a4534a and a4529a );
a4538a <=( (not A298) and A203 );
a4542a <=( A302 and A300 );
a4543a <=( A299 and a4542a );
a4544a <=( a4543a and a4538a );
a4547a <=( (not A168) and A169 );
a4551a <=( A201 and (not A200) );
a4552a <=( A199 and a4551a );
a4553a <=( a4552a and a4547a );
a4556a <=( A298 and A202 );
a4560a <=( A301 and A300 );
a4561a <=( (not A299) and a4560a );
a4562a <=( a4561a and a4556a );
a4565a <=( (not A168) and A169 );
a4569a <=( A201 and (not A200) );
a4570a <=( A199 and a4569a );
a4571a <=( a4570a and a4565a );
a4574a <=( A298 and A202 );
a4578a <=( A302 and A300 );
a4579a <=( (not A299) and a4578a );
a4580a <=( a4579a and a4574a );
a4583a <=( (not A168) and A169 );
a4587a <=( A201 and (not A200) );
a4588a <=( A199 and a4587a );
a4589a <=( a4588a and a4583a );
a4592a <=( (not A298) and A202 );
a4596a <=( A301 and A300 );
a4597a <=( A299 and a4596a );
a4598a <=( a4597a and a4592a );
a4601a <=( (not A168) and A169 );
a4605a <=( A201 and (not A200) );
a4606a <=( A199 and a4605a );
a4607a <=( a4606a and a4601a );
a4610a <=( (not A298) and A202 );
a4614a <=( A302 and A300 );
a4615a <=( A299 and a4614a );
a4616a <=( a4615a and a4610a );
a4619a <=( (not A168) and A169 );
a4623a <=( A201 and (not A200) );
a4624a <=( A199 and a4623a );
a4625a <=( a4624a and a4619a );
a4628a <=( A298 and A203 );
a4632a <=( A301 and A300 );
a4633a <=( (not A299) and a4632a );
a4634a <=( a4633a and a4628a );
a4637a <=( (not A168) and A169 );
a4641a <=( A201 and (not A200) );
a4642a <=( A199 and a4641a );
a4643a <=( a4642a and a4637a );
a4646a <=( A298 and A203 );
a4650a <=( A302 and A300 );
a4651a <=( (not A299) and a4650a );
a4652a <=( a4651a and a4646a );
a4655a <=( (not A168) and A169 );
a4659a <=( A201 and (not A200) );
a4660a <=( A199 and a4659a );
a4661a <=( a4660a and a4655a );
a4664a <=( (not A298) and A203 );
a4668a <=( A301 and A300 );
a4669a <=( A299 and a4668a );
a4670a <=( a4669a and a4664a );
a4673a <=( (not A168) and A169 );
a4677a <=( A201 and (not A200) );
a4678a <=( A199 and a4677a );
a4679a <=( a4678a and a4673a );
a4682a <=( (not A298) and A203 );
a4686a <=( A302 and A300 );
a4687a <=( A299 and a4686a );
a4688a <=( a4687a and a4682a );
a4691a <=( (not A169) and A170 );
a4695a <=( (not A166) and A167 );
a4696a <=( (not A168) and a4695a );
a4697a <=( a4696a and a4691a );
a4700a <=( A233 and (not A232) );
a4704a <=( (not A236) and (not A235) );
a4705a <=( (not A234) and a4704a );
a4706a <=( a4705a and a4700a );
a4709a <=( (not A169) and A170 );
a4713a <=( (not A166) and A167 );
a4714a <=( (not A168) and a4713a );
a4715a <=( a4714a and a4709a );
a4718a <=( (not A233) and A232 );
a4722a <=( (not A236) and (not A235) );
a4723a <=( (not A234) and a4722a );
a4724a <=( a4723a and a4718a );
a4727a <=( (not A169) and A170 );
a4731a <=( A166 and (not A167) );
a4732a <=( (not A168) and a4731a );
a4733a <=( a4732a and a4727a );
a4736a <=( A233 and (not A232) );
a4740a <=( (not A236) and (not A235) );
a4741a <=( (not A234) and a4740a );
a4742a <=( a4741a and a4736a );
a4745a <=( (not A169) and A170 );
a4749a <=( A166 and (not A167) );
a4750a <=( (not A168) and a4749a );
a4751a <=( a4750a and a4745a );
a4754a <=( (not A233) and A232 );
a4758a <=( (not A236) and (not A235) );
a4759a <=( (not A234) and a4758a );
a4760a <=( a4759a and a4754a );
a4763a <=( A166 and A167 );
a4767a <=( A201 and A200 );
a4768a <=( (not A199) and a4767a );
a4769a <=( a4768a and a4763a );
a4773a <=( (not A299) and A298 );
a4774a <=( A202 and a4773a );
a4778a <=( (not A302) and (not A301) );
a4779a <=( (not A300) and a4778a );
a4780a <=( a4779a and a4774a );
a4783a <=( A166 and A167 );
a4787a <=( A201 and A200 );
a4788a <=( (not A199) and a4787a );
a4789a <=( a4788a and a4783a );
a4793a <=( A299 and (not A298) );
a4794a <=( A202 and a4793a );
a4798a <=( (not A302) and (not A301) );
a4799a <=( (not A300) and a4798a );
a4800a <=( a4799a and a4794a );
a4803a <=( A166 and A167 );
a4807a <=( A201 and A200 );
a4808a <=( (not A199) and a4807a );
a4809a <=( a4808a and a4803a );
a4813a <=( (not A299) and A298 );
a4814a <=( A203 and a4813a );
a4818a <=( (not A302) and (not A301) );
a4819a <=( (not A300) and a4818a );
a4820a <=( a4819a and a4814a );
a4823a <=( A166 and A167 );
a4827a <=( A201 and A200 );
a4828a <=( (not A199) and a4827a );
a4829a <=( a4828a and a4823a );
a4833a <=( A299 and (not A298) );
a4834a <=( A203 and a4833a );
a4838a <=( (not A302) and (not A301) );
a4839a <=( (not A300) and a4838a );
a4840a <=( a4839a and a4834a );
a4843a <=( A166 and A167 );
a4847a <=( (not A201) and A200 );
a4848a <=( (not A199) and a4847a );
a4849a <=( a4848a and a4843a );
a4853a <=( A298 and (not A203) );
a4854a <=( (not A202) and a4853a );
a4858a <=( A301 and A300 );
a4859a <=( (not A299) and a4858a );
a4860a <=( a4859a and a4854a );
a4863a <=( A166 and A167 );
a4867a <=( (not A201) and A200 );
a4868a <=( (not A199) and a4867a );
a4869a <=( a4868a and a4863a );
a4873a <=( A298 and (not A203) );
a4874a <=( (not A202) and a4873a );
a4878a <=( A302 and A300 );
a4879a <=( (not A299) and a4878a );
a4880a <=( a4879a and a4874a );
a4883a <=( A166 and A167 );
a4887a <=( (not A201) and A200 );
a4888a <=( (not A199) and a4887a );
a4889a <=( a4888a and a4883a );
a4893a <=( (not A298) and (not A203) );
a4894a <=( (not A202) and a4893a );
a4898a <=( A301 and A300 );
a4899a <=( A299 and a4898a );
a4900a <=( a4899a and a4894a );
a4903a <=( A166 and A167 );
a4907a <=( (not A201) and A200 );
a4908a <=( (not A199) and a4907a );
a4909a <=( a4908a and a4903a );
a4913a <=( (not A298) and (not A203) );
a4914a <=( (not A202) and a4913a );
a4918a <=( A302 and A300 );
a4919a <=( A299 and a4918a );
a4920a <=( a4919a and a4914a );
a4923a <=( A166 and A167 );
a4927a <=( A201 and (not A200) );
a4928a <=( A199 and a4927a );
a4929a <=( a4928a and a4923a );
a4933a <=( (not A299) and A298 );
a4934a <=( A202 and a4933a );
a4938a <=( (not A302) and (not A301) );
a4939a <=( (not A300) and a4938a );
a4940a <=( a4939a and a4934a );
a4943a <=( A166 and A167 );
a4947a <=( A201 and (not A200) );
a4948a <=( A199 and a4947a );
a4949a <=( a4948a and a4943a );
a4953a <=( A299 and (not A298) );
a4954a <=( A202 and a4953a );
a4958a <=( (not A302) and (not A301) );
a4959a <=( (not A300) and a4958a );
a4960a <=( a4959a and a4954a );
a4963a <=( A166 and A167 );
a4967a <=( A201 and (not A200) );
a4968a <=( A199 and a4967a );
a4969a <=( a4968a and a4963a );
a4973a <=( (not A299) and A298 );
a4974a <=( A203 and a4973a );
a4978a <=( (not A302) and (not A301) );
a4979a <=( (not A300) and a4978a );
a4980a <=( a4979a and a4974a );
a4983a <=( A166 and A167 );
a4987a <=( A201 and (not A200) );
a4988a <=( A199 and a4987a );
a4989a <=( a4988a and a4983a );
a4993a <=( A299 and (not A298) );
a4994a <=( A203 and a4993a );
a4998a <=( (not A302) and (not A301) );
a4999a <=( (not A300) and a4998a );
a5000a <=( a4999a and a4994a );
a5003a <=( A166 and A167 );
a5007a <=( (not A201) and (not A200) );
a5008a <=( A199 and a5007a );
a5009a <=( a5008a and a5003a );
a5013a <=( A298 and (not A203) );
a5014a <=( (not A202) and a5013a );
a5018a <=( A301 and A300 );
a5019a <=( (not A299) and a5018a );
a5020a <=( a5019a and a5014a );
a5023a <=( A166 and A167 );
a5027a <=( (not A201) and (not A200) );
a5028a <=( A199 and a5027a );
a5029a <=( a5028a and a5023a );
a5033a <=( A298 and (not A203) );
a5034a <=( (not A202) and a5033a );
a5038a <=( A302 and A300 );
a5039a <=( (not A299) and a5038a );
a5040a <=( a5039a and a5034a );
a5043a <=( A166 and A167 );
a5047a <=( (not A201) and (not A200) );
a5048a <=( A199 and a5047a );
a5049a <=( a5048a and a5043a );
a5053a <=( (not A298) and (not A203) );
a5054a <=( (not A202) and a5053a );
a5058a <=( A301 and A300 );
a5059a <=( A299 and a5058a );
a5060a <=( a5059a and a5054a );
a5063a <=( A166 and A167 );
a5067a <=( (not A201) and (not A200) );
a5068a <=( A199 and a5067a );
a5069a <=( a5068a and a5063a );
a5073a <=( (not A298) and (not A203) );
a5074a <=( (not A202) and a5073a );
a5078a <=( A302 and A300 );
a5079a <=( A299 and a5078a );
a5080a <=( a5079a and a5074a );
a5083a <=( (not A166) and (not A167) );
a5087a <=( A201 and A200 );
a5088a <=( (not A199) and a5087a );
a5089a <=( a5088a and a5083a );
a5093a <=( (not A299) and A298 );
a5094a <=( A202 and a5093a );
a5098a <=( (not A302) and (not A301) );
a5099a <=( (not A300) and a5098a );
a5100a <=( a5099a and a5094a );
a5103a <=( (not A166) and (not A167) );
a5107a <=( A201 and A200 );
a5108a <=( (not A199) and a5107a );
a5109a <=( a5108a and a5103a );
a5113a <=( A299 and (not A298) );
a5114a <=( A202 and a5113a );
a5118a <=( (not A302) and (not A301) );
a5119a <=( (not A300) and a5118a );
a5120a <=( a5119a and a5114a );
a5123a <=( (not A166) and (not A167) );
a5127a <=( A201 and A200 );
a5128a <=( (not A199) and a5127a );
a5129a <=( a5128a and a5123a );
a5133a <=( (not A299) and A298 );
a5134a <=( A203 and a5133a );
a5138a <=( (not A302) and (not A301) );
a5139a <=( (not A300) and a5138a );
a5140a <=( a5139a and a5134a );
a5143a <=( (not A166) and (not A167) );
a5147a <=( A201 and A200 );
a5148a <=( (not A199) and a5147a );
a5149a <=( a5148a and a5143a );
a5153a <=( A299 and (not A298) );
a5154a <=( A203 and a5153a );
a5158a <=( (not A302) and (not A301) );
a5159a <=( (not A300) and a5158a );
a5160a <=( a5159a and a5154a );
a5163a <=( (not A166) and (not A167) );
a5167a <=( (not A201) and A200 );
a5168a <=( (not A199) and a5167a );
a5169a <=( a5168a and a5163a );
a5173a <=( A298 and (not A203) );
a5174a <=( (not A202) and a5173a );
a5178a <=( A301 and A300 );
a5179a <=( (not A299) and a5178a );
a5180a <=( a5179a and a5174a );
a5183a <=( (not A166) and (not A167) );
a5187a <=( (not A201) and A200 );
a5188a <=( (not A199) and a5187a );
a5189a <=( a5188a and a5183a );
a5193a <=( A298 and (not A203) );
a5194a <=( (not A202) and a5193a );
a5198a <=( A302 and A300 );
a5199a <=( (not A299) and a5198a );
a5200a <=( a5199a and a5194a );
a5203a <=( (not A166) and (not A167) );
a5207a <=( (not A201) and A200 );
a5208a <=( (not A199) and a5207a );
a5209a <=( a5208a and a5203a );
a5213a <=( (not A298) and (not A203) );
a5214a <=( (not A202) and a5213a );
a5218a <=( A301 and A300 );
a5219a <=( A299 and a5218a );
a5220a <=( a5219a and a5214a );
a5223a <=( (not A166) and (not A167) );
a5227a <=( (not A201) and A200 );
a5228a <=( (not A199) and a5227a );
a5229a <=( a5228a and a5223a );
a5233a <=( (not A298) and (not A203) );
a5234a <=( (not A202) and a5233a );
a5238a <=( A302 and A300 );
a5239a <=( A299 and a5238a );
a5240a <=( a5239a and a5234a );
a5243a <=( (not A166) and (not A167) );
a5247a <=( A201 and (not A200) );
a5248a <=( A199 and a5247a );
a5249a <=( a5248a and a5243a );
a5253a <=( (not A299) and A298 );
a5254a <=( A202 and a5253a );
a5258a <=( (not A302) and (not A301) );
a5259a <=( (not A300) and a5258a );
a5260a <=( a5259a and a5254a );
a5263a <=( (not A166) and (not A167) );
a5267a <=( A201 and (not A200) );
a5268a <=( A199 and a5267a );
a5269a <=( a5268a and a5263a );
a5273a <=( A299 and (not A298) );
a5274a <=( A202 and a5273a );
a5278a <=( (not A302) and (not A301) );
a5279a <=( (not A300) and a5278a );
a5280a <=( a5279a and a5274a );
a5283a <=( (not A166) and (not A167) );
a5287a <=( A201 and (not A200) );
a5288a <=( A199 and a5287a );
a5289a <=( a5288a and a5283a );
a5293a <=( (not A299) and A298 );
a5294a <=( A203 and a5293a );
a5298a <=( (not A302) and (not A301) );
a5299a <=( (not A300) and a5298a );
a5300a <=( a5299a and a5294a );
a5303a <=( (not A166) and (not A167) );
a5307a <=( A201 and (not A200) );
a5308a <=( A199 and a5307a );
a5309a <=( a5308a and a5303a );
a5313a <=( A299 and (not A298) );
a5314a <=( A203 and a5313a );
a5318a <=( (not A302) and (not A301) );
a5319a <=( (not A300) and a5318a );
a5320a <=( a5319a and a5314a );
a5323a <=( (not A166) and (not A167) );
a5327a <=( (not A201) and (not A200) );
a5328a <=( A199 and a5327a );
a5329a <=( a5328a and a5323a );
a5333a <=( A298 and (not A203) );
a5334a <=( (not A202) and a5333a );
a5338a <=( A301 and A300 );
a5339a <=( (not A299) and a5338a );
a5340a <=( a5339a and a5334a );
a5343a <=( (not A166) and (not A167) );
a5347a <=( (not A201) and (not A200) );
a5348a <=( A199 and a5347a );
a5349a <=( a5348a and a5343a );
a5353a <=( A298 and (not A203) );
a5354a <=( (not A202) and a5353a );
a5358a <=( A302 and A300 );
a5359a <=( (not A299) and a5358a );
a5360a <=( a5359a and a5354a );
a5363a <=( (not A166) and (not A167) );
a5367a <=( (not A201) and (not A200) );
a5368a <=( A199 and a5367a );
a5369a <=( a5368a and a5363a );
a5373a <=( (not A298) and (not A203) );
a5374a <=( (not A202) and a5373a );
a5378a <=( A301 and A300 );
a5379a <=( A299 and a5378a );
a5380a <=( a5379a and a5374a );
a5383a <=( (not A166) and (not A167) );
a5387a <=( (not A201) and (not A200) );
a5388a <=( A199 and a5387a );
a5389a <=( a5388a and a5383a );
a5393a <=( (not A298) and (not A203) );
a5394a <=( (not A202) and a5393a );
a5398a <=( A302 and A300 );
a5399a <=( A299 and a5398a );
a5400a <=( a5399a and a5394a );
a5403a <=( A168 and (not A170) );
a5407a <=( A201 and (not A166) );
a5408a <=( A167 and a5407a );
a5409a <=( a5408a and a5403a );
a5413a <=( A298 and (not A203) );
a5414a <=( (not A202) and a5413a );
a5418a <=( A301 and A300 );
a5419a <=( (not A299) and a5418a );
a5420a <=( a5419a and a5414a );
a5423a <=( A168 and (not A170) );
a5427a <=( A201 and (not A166) );
a5428a <=( A167 and a5427a );
a5429a <=( a5428a and a5423a );
a5433a <=( A298 and (not A203) );
a5434a <=( (not A202) and a5433a );
a5438a <=( A302 and A300 );
a5439a <=( (not A299) and a5438a );
a5440a <=( a5439a and a5434a );
a5443a <=( A168 and (not A170) );
a5447a <=( A201 and (not A166) );
a5448a <=( A167 and a5447a );
a5449a <=( a5448a and a5443a );
a5453a <=( (not A298) and (not A203) );
a5454a <=( (not A202) and a5453a );
a5458a <=( A301 and A300 );
a5459a <=( A299 and a5458a );
a5460a <=( a5459a and a5454a );
a5463a <=( A168 and (not A170) );
a5467a <=( A201 and (not A166) );
a5468a <=( A167 and a5467a );
a5469a <=( a5468a and a5463a );
a5473a <=( (not A298) and (not A203) );
a5474a <=( (not A202) and a5473a );
a5478a <=( A302 and A300 );
a5479a <=( A299 and a5478a );
a5480a <=( a5479a and a5474a );
a5483a <=( A168 and (not A170) );
a5487a <=( (not A201) and (not A166) );
a5488a <=( A167 and a5487a );
a5489a <=( a5488a and a5483a );
a5493a <=( (not A299) and A298 );
a5494a <=( A202 and a5493a );
a5498a <=( (not A302) and (not A301) );
a5499a <=( (not A300) and a5498a );
a5500a <=( a5499a and a5494a );
a5503a <=( A168 and (not A170) );
a5507a <=( (not A201) and (not A166) );
a5508a <=( A167 and a5507a );
a5509a <=( a5508a and a5503a );
a5513a <=( A299 and (not A298) );
a5514a <=( A202 and a5513a );
a5518a <=( (not A302) and (not A301) );
a5519a <=( (not A300) and a5518a );
a5520a <=( a5519a and a5514a );
a5523a <=( A168 and (not A170) );
a5527a <=( (not A201) and (not A166) );
a5528a <=( A167 and a5527a );
a5529a <=( a5528a and a5523a );
a5533a <=( (not A299) and A298 );
a5534a <=( A203 and a5533a );
a5538a <=( (not A302) and (not A301) );
a5539a <=( (not A300) and a5538a );
a5540a <=( a5539a and a5534a );
a5543a <=( A168 and (not A170) );
a5547a <=( (not A201) and (not A166) );
a5548a <=( A167 and a5547a );
a5549a <=( a5548a and a5543a );
a5553a <=( A299 and (not A298) );
a5554a <=( A203 and a5553a );
a5558a <=( (not A302) and (not A301) );
a5559a <=( (not A300) and a5558a );
a5560a <=( a5559a and a5554a );
a5563a <=( A168 and (not A170) );
a5567a <=( A199 and (not A166) );
a5568a <=( A167 and a5567a );
a5569a <=( a5568a and a5563a );
a5573a <=( (not A299) and A298 );
a5574a <=( A200 and a5573a );
a5578a <=( (not A302) and (not A301) );
a5579a <=( (not A300) and a5578a );
a5580a <=( a5579a and a5574a );
a5583a <=( A168 and (not A170) );
a5587a <=( A199 and (not A166) );
a5588a <=( A167 and a5587a );
a5589a <=( a5588a and a5583a );
a5593a <=( A299 and (not A298) );
a5594a <=( A200 and a5593a );
a5598a <=( (not A302) and (not A301) );
a5599a <=( (not A300) and a5598a );
a5600a <=( a5599a and a5594a );
a5603a <=( A168 and (not A170) );
a5607a <=( (not A199) and (not A166) );
a5608a <=( A167 and a5607a );
a5609a <=( a5608a and a5603a );
a5613a <=( (not A299) and A298 );
a5614a <=( (not A200) and a5613a );
a5618a <=( (not A302) and (not A301) );
a5619a <=( (not A300) and a5618a );
a5620a <=( a5619a and a5614a );
a5623a <=( A168 and (not A170) );
a5627a <=( (not A199) and (not A166) );
a5628a <=( A167 and a5627a );
a5629a <=( a5628a and a5623a );
a5633a <=( A299 and (not A298) );
a5634a <=( (not A200) and a5633a );
a5638a <=( (not A302) and (not A301) );
a5639a <=( (not A300) and a5638a );
a5640a <=( a5639a and a5634a );
a5643a <=( A168 and (not A170) );
a5647a <=( A201 and A166 );
a5648a <=( (not A167) and a5647a );
a5649a <=( a5648a and a5643a );
a5653a <=( A298 and (not A203) );
a5654a <=( (not A202) and a5653a );
a5658a <=( A301 and A300 );
a5659a <=( (not A299) and a5658a );
a5660a <=( a5659a and a5654a );
a5663a <=( A168 and (not A170) );
a5667a <=( A201 and A166 );
a5668a <=( (not A167) and a5667a );
a5669a <=( a5668a and a5663a );
a5673a <=( A298 and (not A203) );
a5674a <=( (not A202) and a5673a );
a5678a <=( A302 and A300 );
a5679a <=( (not A299) and a5678a );
a5680a <=( a5679a and a5674a );
a5683a <=( A168 and (not A170) );
a5687a <=( A201 and A166 );
a5688a <=( (not A167) and a5687a );
a5689a <=( a5688a and a5683a );
a5693a <=( (not A298) and (not A203) );
a5694a <=( (not A202) and a5693a );
a5698a <=( A301 and A300 );
a5699a <=( A299 and a5698a );
a5700a <=( a5699a and a5694a );
a5703a <=( A168 and (not A170) );
a5707a <=( A201 and A166 );
a5708a <=( (not A167) and a5707a );
a5709a <=( a5708a and a5703a );
a5713a <=( (not A298) and (not A203) );
a5714a <=( (not A202) and a5713a );
a5718a <=( A302 and A300 );
a5719a <=( A299 and a5718a );
a5720a <=( a5719a and a5714a );
a5723a <=( A168 and (not A170) );
a5727a <=( (not A201) and A166 );
a5728a <=( (not A167) and a5727a );
a5729a <=( a5728a and a5723a );
a5733a <=( (not A299) and A298 );
a5734a <=( A202 and a5733a );
a5738a <=( (not A302) and (not A301) );
a5739a <=( (not A300) and a5738a );
a5740a <=( a5739a and a5734a );
a5743a <=( A168 and (not A170) );
a5747a <=( (not A201) and A166 );
a5748a <=( (not A167) and a5747a );
a5749a <=( a5748a and a5743a );
a5753a <=( A299 and (not A298) );
a5754a <=( A202 and a5753a );
a5758a <=( (not A302) and (not A301) );
a5759a <=( (not A300) and a5758a );
a5760a <=( a5759a and a5754a );
a5763a <=( A168 and (not A170) );
a5767a <=( (not A201) and A166 );
a5768a <=( (not A167) and a5767a );
a5769a <=( a5768a and a5763a );
a5773a <=( (not A299) and A298 );
a5774a <=( A203 and a5773a );
a5778a <=( (not A302) and (not A301) );
a5779a <=( (not A300) and a5778a );
a5780a <=( a5779a and a5774a );
a5783a <=( A168 and (not A170) );
a5787a <=( (not A201) and A166 );
a5788a <=( (not A167) and a5787a );
a5789a <=( a5788a and a5783a );
a5793a <=( A299 and (not A298) );
a5794a <=( A203 and a5793a );
a5798a <=( (not A302) and (not A301) );
a5799a <=( (not A300) and a5798a );
a5800a <=( a5799a and a5794a );
a5803a <=( A168 and (not A170) );
a5807a <=( A199 and A166 );
a5808a <=( (not A167) and a5807a );
a5809a <=( a5808a and a5803a );
a5813a <=( (not A299) and A298 );
a5814a <=( A200 and a5813a );
a5818a <=( (not A302) and (not A301) );
a5819a <=( (not A300) and a5818a );
a5820a <=( a5819a and a5814a );
a5823a <=( A168 and (not A170) );
a5827a <=( A199 and A166 );
a5828a <=( (not A167) and a5827a );
a5829a <=( a5828a and a5823a );
a5833a <=( A299 and (not A298) );
a5834a <=( A200 and a5833a );
a5838a <=( (not A302) and (not A301) );
a5839a <=( (not A300) and a5838a );
a5840a <=( a5839a and a5834a );
a5843a <=( A168 and (not A170) );
a5847a <=( (not A199) and A166 );
a5848a <=( (not A167) and a5847a );
a5849a <=( a5848a and a5843a );
a5853a <=( (not A299) and A298 );
a5854a <=( (not A200) and a5853a );
a5858a <=( (not A302) and (not A301) );
a5859a <=( (not A300) and a5858a );
a5860a <=( a5859a and a5854a );
a5863a <=( A168 and (not A170) );
a5867a <=( (not A199) and A166 );
a5868a <=( (not A167) and a5867a );
a5869a <=( a5868a and a5863a );
a5873a <=( A299 and (not A298) );
a5874a <=( (not A200) and a5873a );
a5878a <=( (not A302) and (not A301) );
a5879a <=( (not A300) and a5878a );
a5880a <=( a5879a and a5874a );
a5883a <=( (not A168) and (not A170) );
a5887a <=( A201 and A200 );
a5888a <=( (not A199) and a5887a );
a5889a <=( a5888a and a5883a );
a5893a <=( (not A299) and A298 );
a5894a <=( A202 and a5893a );
a5898a <=( (not A302) and (not A301) );
a5899a <=( (not A300) and a5898a );
a5900a <=( a5899a and a5894a );
a5903a <=( (not A168) and (not A170) );
a5907a <=( A201 and A200 );
a5908a <=( (not A199) and a5907a );
a5909a <=( a5908a and a5903a );
a5913a <=( A299 and (not A298) );
a5914a <=( A202 and a5913a );
a5918a <=( (not A302) and (not A301) );
a5919a <=( (not A300) and a5918a );
a5920a <=( a5919a and a5914a );
a5923a <=( (not A168) and (not A170) );
a5927a <=( A201 and A200 );
a5928a <=( (not A199) and a5927a );
a5929a <=( a5928a and a5923a );
a5933a <=( (not A299) and A298 );
a5934a <=( A203 and a5933a );
a5938a <=( (not A302) and (not A301) );
a5939a <=( (not A300) and a5938a );
a5940a <=( a5939a and a5934a );
a5943a <=( (not A168) and (not A170) );
a5947a <=( A201 and A200 );
a5948a <=( (not A199) and a5947a );
a5949a <=( a5948a and a5943a );
a5953a <=( A299 and (not A298) );
a5954a <=( A203 and a5953a );
a5958a <=( (not A302) and (not A301) );
a5959a <=( (not A300) and a5958a );
a5960a <=( a5959a and a5954a );
a5963a <=( (not A168) and (not A170) );
a5967a <=( (not A201) and A200 );
a5968a <=( (not A199) and a5967a );
a5969a <=( a5968a and a5963a );
a5973a <=( A298 and (not A203) );
a5974a <=( (not A202) and a5973a );
a5978a <=( A301 and A300 );
a5979a <=( (not A299) and a5978a );
a5980a <=( a5979a and a5974a );
a5983a <=( (not A168) and (not A170) );
a5987a <=( (not A201) and A200 );
a5988a <=( (not A199) and a5987a );
a5989a <=( a5988a and a5983a );
a5993a <=( A298 and (not A203) );
a5994a <=( (not A202) and a5993a );
a5998a <=( A302 and A300 );
a5999a <=( (not A299) and a5998a );
a6000a <=( a5999a and a5994a );
a6003a <=( (not A168) and (not A170) );
a6007a <=( (not A201) and A200 );
a6008a <=( (not A199) and a6007a );
a6009a <=( a6008a and a6003a );
a6013a <=( (not A298) and (not A203) );
a6014a <=( (not A202) and a6013a );
a6018a <=( A301 and A300 );
a6019a <=( A299 and a6018a );
a6020a <=( a6019a and a6014a );
a6023a <=( (not A168) and (not A170) );
a6027a <=( (not A201) and A200 );
a6028a <=( (not A199) and a6027a );
a6029a <=( a6028a and a6023a );
a6033a <=( (not A298) and (not A203) );
a6034a <=( (not A202) and a6033a );
a6038a <=( A302 and A300 );
a6039a <=( A299 and a6038a );
a6040a <=( a6039a and a6034a );
a6043a <=( (not A168) and (not A170) );
a6047a <=( A201 and (not A200) );
a6048a <=( A199 and a6047a );
a6049a <=( a6048a and a6043a );
a6053a <=( (not A299) and A298 );
a6054a <=( A202 and a6053a );
a6058a <=( (not A302) and (not A301) );
a6059a <=( (not A300) and a6058a );
a6060a <=( a6059a and a6054a );
a6063a <=( (not A168) and (not A170) );
a6067a <=( A201 and (not A200) );
a6068a <=( A199 and a6067a );
a6069a <=( a6068a and a6063a );
a6073a <=( A299 and (not A298) );
a6074a <=( A202 and a6073a );
a6078a <=( (not A302) and (not A301) );
a6079a <=( (not A300) and a6078a );
a6080a <=( a6079a and a6074a );
a6083a <=( (not A168) and (not A170) );
a6087a <=( A201 and (not A200) );
a6088a <=( A199 and a6087a );
a6089a <=( a6088a and a6083a );
a6093a <=( (not A299) and A298 );
a6094a <=( A203 and a6093a );
a6098a <=( (not A302) and (not A301) );
a6099a <=( (not A300) and a6098a );
a6100a <=( a6099a and a6094a );
a6103a <=( (not A168) and (not A170) );
a6107a <=( A201 and (not A200) );
a6108a <=( A199 and a6107a );
a6109a <=( a6108a and a6103a );
a6113a <=( A299 and (not A298) );
a6114a <=( A203 and a6113a );
a6118a <=( (not A302) and (not A301) );
a6119a <=( (not A300) and a6118a );
a6120a <=( a6119a and a6114a );
a6123a <=( (not A168) and (not A170) );
a6127a <=( (not A201) and (not A200) );
a6128a <=( A199 and a6127a );
a6129a <=( a6128a and a6123a );
a6133a <=( A298 and (not A203) );
a6134a <=( (not A202) and a6133a );
a6138a <=( A301 and A300 );
a6139a <=( (not A299) and a6138a );
a6140a <=( a6139a and a6134a );
a6143a <=( (not A168) and (not A170) );
a6147a <=( (not A201) and (not A200) );
a6148a <=( A199 and a6147a );
a6149a <=( a6148a and a6143a );
a6153a <=( A298 and (not A203) );
a6154a <=( (not A202) and a6153a );
a6158a <=( A302 and A300 );
a6159a <=( (not A299) and a6158a );
a6160a <=( a6159a and a6154a );
a6163a <=( (not A168) and (not A170) );
a6167a <=( (not A201) and (not A200) );
a6168a <=( A199 and a6167a );
a6169a <=( a6168a and a6163a );
a6173a <=( (not A298) and (not A203) );
a6174a <=( (not A202) and a6173a );
a6178a <=( A301 and A300 );
a6179a <=( A299 and a6178a );
a6180a <=( a6179a and a6174a );
a6183a <=( (not A168) and (not A170) );
a6187a <=( (not A201) and (not A200) );
a6188a <=( A199 and a6187a );
a6189a <=( a6188a and a6183a );
a6193a <=( (not A298) and (not A203) );
a6194a <=( (not A202) and a6193a );
a6198a <=( A302 and A300 );
a6199a <=( A299 and a6198a );
a6200a <=( a6199a and a6194a );
a6203a <=( A168 and A169 );
a6207a <=( A201 and (not A166) );
a6208a <=( A167 and a6207a );
a6209a <=( a6208a and a6203a );
a6213a <=( A298 and (not A203) );
a6214a <=( (not A202) and a6213a );
a6218a <=( A301 and A300 );
a6219a <=( (not A299) and a6218a );
a6220a <=( a6219a and a6214a );
a6223a <=( A168 and A169 );
a6227a <=( A201 and (not A166) );
a6228a <=( A167 and a6227a );
a6229a <=( a6228a and a6223a );
a6233a <=( A298 and (not A203) );
a6234a <=( (not A202) and a6233a );
a6238a <=( A302 and A300 );
a6239a <=( (not A299) and a6238a );
a6240a <=( a6239a and a6234a );
a6243a <=( A168 and A169 );
a6247a <=( A201 and (not A166) );
a6248a <=( A167 and a6247a );
a6249a <=( a6248a and a6243a );
a6253a <=( (not A298) and (not A203) );
a6254a <=( (not A202) and a6253a );
a6258a <=( A301 and A300 );
a6259a <=( A299 and a6258a );
a6260a <=( a6259a and a6254a );
a6263a <=( A168 and A169 );
a6267a <=( A201 and (not A166) );
a6268a <=( A167 and a6267a );
a6269a <=( a6268a and a6263a );
a6273a <=( (not A298) and (not A203) );
a6274a <=( (not A202) and a6273a );
a6278a <=( A302 and A300 );
a6279a <=( A299 and a6278a );
a6280a <=( a6279a and a6274a );
a6283a <=( A168 and A169 );
a6287a <=( (not A201) and (not A166) );
a6288a <=( A167 and a6287a );
a6289a <=( a6288a and a6283a );
a6293a <=( (not A299) and A298 );
a6294a <=( A202 and a6293a );
a6298a <=( (not A302) and (not A301) );
a6299a <=( (not A300) and a6298a );
a6300a <=( a6299a and a6294a );
a6303a <=( A168 and A169 );
a6307a <=( (not A201) and (not A166) );
a6308a <=( A167 and a6307a );
a6309a <=( a6308a and a6303a );
a6313a <=( A299 and (not A298) );
a6314a <=( A202 and a6313a );
a6318a <=( (not A302) and (not A301) );
a6319a <=( (not A300) and a6318a );
a6320a <=( a6319a and a6314a );
a6323a <=( A168 and A169 );
a6327a <=( (not A201) and (not A166) );
a6328a <=( A167 and a6327a );
a6329a <=( a6328a and a6323a );
a6333a <=( (not A299) and A298 );
a6334a <=( A203 and a6333a );
a6338a <=( (not A302) and (not A301) );
a6339a <=( (not A300) and a6338a );
a6340a <=( a6339a and a6334a );
a6343a <=( A168 and A169 );
a6347a <=( (not A201) and (not A166) );
a6348a <=( A167 and a6347a );
a6349a <=( a6348a and a6343a );
a6353a <=( A299 and (not A298) );
a6354a <=( A203 and a6353a );
a6358a <=( (not A302) and (not A301) );
a6359a <=( (not A300) and a6358a );
a6360a <=( a6359a and a6354a );
a6363a <=( A168 and A169 );
a6367a <=( A199 and (not A166) );
a6368a <=( A167 and a6367a );
a6369a <=( a6368a and a6363a );
a6373a <=( (not A299) and A298 );
a6374a <=( A200 and a6373a );
a6378a <=( (not A302) and (not A301) );
a6379a <=( (not A300) and a6378a );
a6380a <=( a6379a and a6374a );
a6383a <=( A168 and A169 );
a6387a <=( A199 and (not A166) );
a6388a <=( A167 and a6387a );
a6389a <=( a6388a and a6383a );
a6393a <=( A299 and (not A298) );
a6394a <=( A200 and a6393a );
a6398a <=( (not A302) and (not A301) );
a6399a <=( (not A300) and a6398a );
a6400a <=( a6399a and a6394a );
a6403a <=( A168 and A169 );
a6407a <=( (not A199) and (not A166) );
a6408a <=( A167 and a6407a );
a6409a <=( a6408a and a6403a );
a6413a <=( (not A299) and A298 );
a6414a <=( (not A200) and a6413a );
a6418a <=( (not A302) and (not A301) );
a6419a <=( (not A300) and a6418a );
a6420a <=( a6419a and a6414a );
a6423a <=( A168 and A169 );
a6427a <=( (not A199) and (not A166) );
a6428a <=( A167 and a6427a );
a6429a <=( a6428a and a6423a );
a6433a <=( A299 and (not A298) );
a6434a <=( (not A200) and a6433a );
a6438a <=( (not A302) and (not A301) );
a6439a <=( (not A300) and a6438a );
a6440a <=( a6439a and a6434a );
a6443a <=( A168 and A169 );
a6447a <=( A201 and A166 );
a6448a <=( (not A167) and a6447a );
a6449a <=( a6448a and a6443a );
a6453a <=( A298 and (not A203) );
a6454a <=( (not A202) and a6453a );
a6458a <=( A301 and A300 );
a6459a <=( (not A299) and a6458a );
a6460a <=( a6459a and a6454a );
a6463a <=( A168 and A169 );
a6467a <=( A201 and A166 );
a6468a <=( (not A167) and a6467a );
a6469a <=( a6468a and a6463a );
a6473a <=( A298 and (not A203) );
a6474a <=( (not A202) and a6473a );
a6478a <=( A302 and A300 );
a6479a <=( (not A299) and a6478a );
a6480a <=( a6479a and a6474a );
a6483a <=( A168 and A169 );
a6487a <=( A201 and A166 );
a6488a <=( (not A167) and a6487a );
a6489a <=( a6488a and a6483a );
a6493a <=( (not A298) and (not A203) );
a6494a <=( (not A202) and a6493a );
a6498a <=( A301 and A300 );
a6499a <=( A299 and a6498a );
a6500a <=( a6499a and a6494a );
a6503a <=( A168 and A169 );
a6507a <=( A201 and A166 );
a6508a <=( (not A167) and a6507a );
a6509a <=( a6508a and a6503a );
a6513a <=( (not A298) and (not A203) );
a6514a <=( (not A202) and a6513a );
a6518a <=( A302 and A300 );
a6519a <=( A299 and a6518a );
a6520a <=( a6519a and a6514a );
a6523a <=( A168 and A169 );
a6527a <=( (not A201) and A166 );
a6528a <=( (not A167) and a6527a );
a6529a <=( a6528a and a6523a );
a6533a <=( (not A299) and A298 );
a6534a <=( A202 and a6533a );
a6538a <=( (not A302) and (not A301) );
a6539a <=( (not A300) and a6538a );
a6540a <=( a6539a and a6534a );
a6543a <=( A168 and A169 );
a6547a <=( (not A201) and A166 );
a6548a <=( (not A167) and a6547a );
a6549a <=( a6548a and a6543a );
a6553a <=( A299 and (not A298) );
a6554a <=( A202 and a6553a );
a6558a <=( (not A302) and (not A301) );
a6559a <=( (not A300) and a6558a );
a6560a <=( a6559a and a6554a );
a6563a <=( A168 and A169 );
a6567a <=( (not A201) and A166 );
a6568a <=( (not A167) and a6567a );
a6569a <=( a6568a and a6563a );
a6573a <=( (not A299) and A298 );
a6574a <=( A203 and a6573a );
a6578a <=( (not A302) and (not A301) );
a6579a <=( (not A300) and a6578a );
a6580a <=( a6579a and a6574a );
a6583a <=( A168 and A169 );
a6587a <=( (not A201) and A166 );
a6588a <=( (not A167) and a6587a );
a6589a <=( a6588a and a6583a );
a6593a <=( A299 and (not A298) );
a6594a <=( A203 and a6593a );
a6598a <=( (not A302) and (not A301) );
a6599a <=( (not A300) and a6598a );
a6600a <=( a6599a and a6594a );
a6603a <=( A168 and A169 );
a6607a <=( A199 and A166 );
a6608a <=( (not A167) and a6607a );
a6609a <=( a6608a and a6603a );
a6613a <=( (not A299) and A298 );
a6614a <=( A200 and a6613a );
a6618a <=( (not A302) and (not A301) );
a6619a <=( (not A300) and a6618a );
a6620a <=( a6619a and a6614a );
a6623a <=( A168 and A169 );
a6627a <=( A199 and A166 );
a6628a <=( (not A167) and a6627a );
a6629a <=( a6628a and a6623a );
a6633a <=( A299 and (not A298) );
a6634a <=( A200 and a6633a );
a6638a <=( (not A302) and (not A301) );
a6639a <=( (not A300) and a6638a );
a6640a <=( a6639a and a6634a );
a6643a <=( A168 and A169 );
a6647a <=( (not A199) and A166 );
a6648a <=( (not A167) and a6647a );
a6649a <=( a6648a and a6643a );
a6653a <=( (not A299) and A298 );
a6654a <=( (not A200) and a6653a );
a6658a <=( (not A302) and (not A301) );
a6659a <=( (not A300) and a6658a );
a6660a <=( a6659a and a6654a );
a6663a <=( A168 and A169 );
a6667a <=( (not A199) and A166 );
a6668a <=( (not A167) and a6667a );
a6669a <=( a6668a and a6663a );
a6673a <=( A299 and (not A298) );
a6674a <=( (not A200) and a6673a );
a6678a <=( (not A302) and (not A301) );
a6679a <=( (not A300) and a6678a );
a6680a <=( a6679a and a6674a );
a6683a <=( (not A168) and A169 );
a6687a <=( A201 and A200 );
a6688a <=( (not A199) and a6687a );
a6689a <=( a6688a and a6683a );
a6693a <=( (not A299) and A298 );
a6694a <=( A202 and a6693a );
a6698a <=( (not A302) and (not A301) );
a6699a <=( (not A300) and a6698a );
a6700a <=( a6699a and a6694a );
a6703a <=( (not A168) and A169 );
a6707a <=( A201 and A200 );
a6708a <=( (not A199) and a6707a );
a6709a <=( a6708a and a6703a );
a6713a <=( A299 and (not A298) );
a6714a <=( A202 and a6713a );
a6718a <=( (not A302) and (not A301) );
a6719a <=( (not A300) and a6718a );
a6720a <=( a6719a and a6714a );
a6723a <=( (not A168) and A169 );
a6727a <=( A201 and A200 );
a6728a <=( (not A199) and a6727a );
a6729a <=( a6728a and a6723a );
a6733a <=( (not A299) and A298 );
a6734a <=( A203 and a6733a );
a6738a <=( (not A302) and (not A301) );
a6739a <=( (not A300) and a6738a );
a6740a <=( a6739a and a6734a );
a6743a <=( (not A168) and A169 );
a6747a <=( A201 and A200 );
a6748a <=( (not A199) and a6747a );
a6749a <=( a6748a and a6743a );
a6753a <=( A299 and (not A298) );
a6754a <=( A203 and a6753a );
a6758a <=( (not A302) and (not A301) );
a6759a <=( (not A300) and a6758a );
a6760a <=( a6759a and a6754a );
a6763a <=( (not A168) and A169 );
a6767a <=( (not A201) and A200 );
a6768a <=( (not A199) and a6767a );
a6769a <=( a6768a and a6763a );
a6773a <=( A298 and (not A203) );
a6774a <=( (not A202) and a6773a );
a6778a <=( A301 and A300 );
a6779a <=( (not A299) and a6778a );
a6780a <=( a6779a and a6774a );
a6783a <=( (not A168) and A169 );
a6787a <=( (not A201) and A200 );
a6788a <=( (not A199) and a6787a );
a6789a <=( a6788a and a6783a );
a6793a <=( A298 and (not A203) );
a6794a <=( (not A202) and a6793a );
a6798a <=( A302 and A300 );
a6799a <=( (not A299) and a6798a );
a6800a <=( a6799a and a6794a );
a6803a <=( (not A168) and A169 );
a6807a <=( (not A201) and A200 );
a6808a <=( (not A199) and a6807a );
a6809a <=( a6808a and a6803a );
a6813a <=( (not A298) and (not A203) );
a6814a <=( (not A202) and a6813a );
a6818a <=( A301 and A300 );
a6819a <=( A299 and a6818a );
a6820a <=( a6819a and a6814a );
a6823a <=( (not A168) and A169 );
a6827a <=( (not A201) and A200 );
a6828a <=( (not A199) and a6827a );
a6829a <=( a6828a and a6823a );
a6833a <=( (not A298) and (not A203) );
a6834a <=( (not A202) and a6833a );
a6838a <=( A302 and A300 );
a6839a <=( A299 and a6838a );
a6840a <=( a6839a and a6834a );
a6843a <=( (not A168) and A169 );
a6847a <=( A201 and (not A200) );
a6848a <=( A199 and a6847a );
a6849a <=( a6848a and a6843a );
a6853a <=( (not A299) and A298 );
a6854a <=( A202 and a6853a );
a6858a <=( (not A302) and (not A301) );
a6859a <=( (not A300) and a6858a );
a6860a <=( a6859a and a6854a );
a6863a <=( (not A168) and A169 );
a6867a <=( A201 and (not A200) );
a6868a <=( A199 and a6867a );
a6869a <=( a6868a and a6863a );
a6873a <=( A299 and (not A298) );
a6874a <=( A202 and a6873a );
a6878a <=( (not A302) and (not A301) );
a6879a <=( (not A300) and a6878a );
a6880a <=( a6879a and a6874a );
a6883a <=( (not A168) and A169 );
a6887a <=( A201 and (not A200) );
a6888a <=( A199 and a6887a );
a6889a <=( a6888a and a6883a );
a6893a <=( (not A299) and A298 );
a6894a <=( A203 and a6893a );
a6898a <=( (not A302) and (not A301) );
a6899a <=( (not A300) and a6898a );
a6900a <=( a6899a and a6894a );
a6903a <=( (not A168) and A169 );
a6907a <=( A201 and (not A200) );
a6908a <=( A199 and a6907a );
a6909a <=( a6908a and a6903a );
a6913a <=( A299 and (not A298) );
a6914a <=( A203 and a6913a );
a6918a <=( (not A302) and (not A301) );
a6919a <=( (not A300) and a6918a );
a6920a <=( a6919a and a6914a );
a6923a <=( (not A168) and A169 );
a6927a <=( (not A201) and (not A200) );
a6928a <=( A199 and a6927a );
a6929a <=( a6928a and a6923a );
a6933a <=( A298 and (not A203) );
a6934a <=( (not A202) and a6933a );
a6938a <=( A301 and A300 );
a6939a <=( (not A299) and a6938a );
a6940a <=( a6939a and a6934a );
a6943a <=( (not A168) and A169 );
a6947a <=( (not A201) and (not A200) );
a6948a <=( A199 and a6947a );
a6949a <=( a6948a and a6943a );
a6953a <=( A298 and (not A203) );
a6954a <=( (not A202) and a6953a );
a6958a <=( A302 and A300 );
a6959a <=( (not A299) and a6958a );
a6960a <=( a6959a and a6954a );
a6963a <=( (not A168) and A169 );
a6967a <=( (not A201) and (not A200) );
a6968a <=( A199 and a6967a );
a6969a <=( a6968a and a6963a );
a6973a <=( (not A298) and (not A203) );
a6974a <=( (not A202) and a6973a );
a6978a <=( A301 and A300 );
a6979a <=( A299 and a6978a );
a6980a <=( a6979a and a6974a );
a6983a <=( (not A168) and A169 );
a6987a <=( (not A201) and (not A200) );
a6988a <=( A199 and a6987a );
a6989a <=( a6988a and a6983a );
a6993a <=( (not A298) and (not A203) );
a6994a <=( (not A202) and a6993a );
a6998a <=( A302 and A300 );
a6999a <=( A299 and a6998a );
a7000a <=( a6999a and a6994a );
a7003a <=( (not A169) and A170 );
a7007a <=( A200 and (not A199) );
a7008a <=( A168 and a7007a );
a7009a <=( a7008a and a7003a );
a7013a <=( A298 and A202 );
a7014a <=( A201 and a7013a );
a7018a <=( A301 and A300 );
a7019a <=( (not A299) and a7018a );
a7020a <=( a7019a and a7014a );
a7023a <=( (not A169) and A170 );
a7027a <=( A200 and (not A199) );
a7028a <=( A168 and a7027a );
a7029a <=( a7028a and a7023a );
a7033a <=( A298 and A202 );
a7034a <=( A201 and a7033a );
a7038a <=( A302 and A300 );
a7039a <=( (not A299) and a7038a );
a7040a <=( a7039a and a7034a );
a7043a <=( (not A169) and A170 );
a7047a <=( A200 and (not A199) );
a7048a <=( A168 and a7047a );
a7049a <=( a7048a and a7043a );
a7053a <=( (not A298) and A202 );
a7054a <=( A201 and a7053a );
a7058a <=( A301 and A300 );
a7059a <=( A299 and a7058a );
a7060a <=( a7059a and a7054a );
a7063a <=( (not A169) and A170 );
a7067a <=( A200 and (not A199) );
a7068a <=( A168 and a7067a );
a7069a <=( a7068a and a7063a );
a7073a <=( (not A298) and A202 );
a7074a <=( A201 and a7073a );
a7078a <=( A302 and A300 );
a7079a <=( A299 and a7078a );
a7080a <=( a7079a and a7074a );
a7083a <=( (not A169) and A170 );
a7087a <=( A200 and (not A199) );
a7088a <=( A168 and a7087a );
a7089a <=( a7088a and a7083a );
a7093a <=( A298 and A203 );
a7094a <=( A201 and a7093a );
a7098a <=( A301 and A300 );
a7099a <=( (not A299) and a7098a );
a7100a <=( a7099a and a7094a );
a7103a <=( (not A169) and A170 );
a7107a <=( A200 and (not A199) );
a7108a <=( A168 and a7107a );
a7109a <=( a7108a and a7103a );
a7113a <=( A298 and A203 );
a7114a <=( A201 and a7113a );
a7118a <=( A302 and A300 );
a7119a <=( (not A299) and a7118a );
a7120a <=( a7119a and a7114a );
a7123a <=( (not A169) and A170 );
a7127a <=( A200 and (not A199) );
a7128a <=( A168 and a7127a );
a7129a <=( a7128a and a7123a );
a7133a <=( (not A298) and A203 );
a7134a <=( A201 and a7133a );
a7138a <=( A301 and A300 );
a7139a <=( A299 and a7138a );
a7140a <=( a7139a and a7134a );
a7143a <=( (not A169) and A170 );
a7147a <=( A200 and (not A199) );
a7148a <=( A168 and a7147a );
a7149a <=( a7148a and a7143a );
a7153a <=( (not A298) and A203 );
a7154a <=( A201 and a7153a );
a7158a <=( A302 and A300 );
a7159a <=( A299 and a7158a );
a7160a <=( a7159a and a7154a );
a7163a <=( (not A169) and A170 );
a7167a <=( (not A200) and A199 );
a7168a <=( A168 and a7167a );
a7169a <=( a7168a and a7163a );
a7173a <=( A298 and A202 );
a7174a <=( A201 and a7173a );
a7178a <=( A301 and A300 );
a7179a <=( (not A299) and a7178a );
a7180a <=( a7179a and a7174a );
a7183a <=( (not A169) and A170 );
a7187a <=( (not A200) and A199 );
a7188a <=( A168 and a7187a );
a7189a <=( a7188a and a7183a );
a7193a <=( A298 and A202 );
a7194a <=( A201 and a7193a );
a7198a <=( A302 and A300 );
a7199a <=( (not A299) and a7198a );
a7200a <=( a7199a and a7194a );
a7203a <=( (not A169) and A170 );
a7207a <=( (not A200) and A199 );
a7208a <=( A168 and a7207a );
a7209a <=( a7208a and a7203a );
a7213a <=( (not A298) and A202 );
a7214a <=( A201 and a7213a );
a7218a <=( A301 and A300 );
a7219a <=( A299 and a7218a );
a7220a <=( a7219a and a7214a );
a7223a <=( (not A169) and A170 );
a7227a <=( (not A200) and A199 );
a7228a <=( A168 and a7227a );
a7229a <=( a7228a and a7223a );
a7233a <=( (not A298) and A202 );
a7234a <=( A201 and a7233a );
a7238a <=( A302 and A300 );
a7239a <=( A299 and a7238a );
a7240a <=( a7239a and a7234a );
a7243a <=( (not A169) and A170 );
a7247a <=( (not A200) and A199 );
a7248a <=( A168 and a7247a );
a7249a <=( a7248a and a7243a );
a7253a <=( A298 and A203 );
a7254a <=( A201 and a7253a );
a7258a <=( A301 and A300 );
a7259a <=( (not A299) and a7258a );
a7260a <=( a7259a and a7254a );
a7263a <=( (not A169) and A170 );
a7267a <=( (not A200) and A199 );
a7268a <=( A168 and a7267a );
a7269a <=( a7268a and a7263a );
a7273a <=( A298 and A203 );
a7274a <=( A201 and a7273a );
a7278a <=( A302 and A300 );
a7279a <=( (not A299) and a7278a );
a7280a <=( a7279a and a7274a );
a7283a <=( (not A169) and A170 );
a7287a <=( (not A200) and A199 );
a7288a <=( A168 and a7287a );
a7289a <=( a7288a and a7283a );
a7293a <=( (not A298) and A203 );
a7294a <=( A201 and a7293a );
a7298a <=( A301 and A300 );
a7299a <=( A299 and a7298a );
a7300a <=( a7299a and a7294a );
a7303a <=( (not A169) and A170 );
a7307a <=( (not A200) and A199 );
a7308a <=( A168 and a7307a );
a7309a <=( a7308a and a7303a );
a7313a <=( (not A298) and A203 );
a7314a <=( A201 and a7313a );
a7318a <=( A302 and A300 );
a7319a <=( A299 and a7318a );
a7320a <=( a7319a and a7314a );
a7323a <=( (not A169) and A170 );
a7327a <=( (not A166) and A167 );
a7328a <=( (not A168) and a7327a );
a7329a <=( a7328a and a7323a );
a7333a <=( A298 and A202 );
a7334a <=( (not A201) and a7333a );
a7338a <=( A301 and A300 );
a7339a <=( (not A299) and a7338a );
a7340a <=( a7339a and a7334a );
a7343a <=( (not A169) and A170 );
a7347a <=( (not A166) and A167 );
a7348a <=( (not A168) and a7347a );
a7349a <=( a7348a and a7343a );
a7353a <=( A298 and A202 );
a7354a <=( (not A201) and a7353a );
a7358a <=( A302 and A300 );
a7359a <=( (not A299) and a7358a );
a7360a <=( a7359a and a7354a );
a7363a <=( (not A169) and A170 );
a7367a <=( (not A166) and A167 );
a7368a <=( (not A168) and a7367a );
a7369a <=( a7368a and a7363a );
a7373a <=( (not A298) and A202 );
a7374a <=( (not A201) and a7373a );
a7378a <=( A301 and A300 );
a7379a <=( A299 and a7378a );
a7380a <=( a7379a and a7374a );
a7383a <=( (not A169) and A170 );
a7387a <=( (not A166) and A167 );
a7388a <=( (not A168) and a7387a );
a7389a <=( a7388a and a7383a );
a7393a <=( (not A298) and A202 );
a7394a <=( (not A201) and a7393a );
a7398a <=( A302 and A300 );
a7399a <=( A299 and a7398a );
a7400a <=( a7399a and a7394a );
a7403a <=( (not A169) and A170 );
a7407a <=( (not A166) and A167 );
a7408a <=( (not A168) and a7407a );
a7409a <=( a7408a and a7403a );
a7413a <=( A298 and A203 );
a7414a <=( (not A201) and a7413a );
a7418a <=( A301 and A300 );
a7419a <=( (not A299) and a7418a );
a7420a <=( a7419a and a7414a );
a7423a <=( (not A169) and A170 );
a7427a <=( (not A166) and A167 );
a7428a <=( (not A168) and a7427a );
a7429a <=( a7428a and a7423a );
a7433a <=( A298 and A203 );
a7434a <=( (not A201) and a7433a );
a7438a <=( A302 and A300 );
a7439a <=( (not A299) and a7438a );
a7440a <=( a7439a and a7434a );
a7443a <=( (not A169) and A170 );
a7447a <=( (not A166) and A167 );
a7448a <=( (not A168) and a7447a );
a7449a <=( a7448a and a7443a );
a7453a <=( (not A298) and A203 );
a7454a <=( (not A201) and a7453a );
a7458a <=( A301 and A300 );
a7459a <=( A299 and a7458a );
a7460a <=( a7459a and a7454a );
a7463a <=( (not A169) and A170 );
a7467a <=( (not A166) and A167 );
a7468a <=( (not A168) and a7467a );
a7469a <=( a7468a and a7463a );
a7473a <=( (not A298) and A203 );
a7474a <=( (not A201) and a7473a );
a7478a <=( A302 and A300 );
a7479a <=( A299 and a7478a );
a7480a <=( a7479a and a7474a );
a7483a <=( (not A169) and A170 );
a7487a <=( (not A166) and A167 );
a7488a <=( (not A168) and a7487a );
a7489a <=( a7488a and a7483a );
a7493a <=( A298 and A200 );
a7494a <=( A199 and a7493a );
a7498a <=( A301 and A300 );
a7499a <=( (not A299) and a7498a );
a7500a <=( a7499a and a7494a );
a7503a <=( (not A169) and A170 );
a7507a <=( (not A166) and A167 );
a7508a <=( (not A168) and a7507a );
a7509a <=( a7508a and a7503a );
a7513a <=( A298 and A200 );
a7514a <=( A199 and a7513a );
a7518a <=( A302 and A300 );
a7519a <=( (not A299) and a7518a );
a7520a <=( a7519a and a7514a );
a7523a <=( (not A169) and A170 );
a7527a <=( (not A166) and A167 );
a7528a <=( (not A168) and a7527a );
a7529a <=( a7528a and a7523a );
a7533a <=( (not A298) and A200 );
a7534a <=( A199 and a7533a );
a7538a <=( A301 and A300 );
a7539a <=( A299 and a7538a );
a7540a <=( a7539a and a7534a );
a7543a <=( (not A169) and A170 );
a7547a <=( (not A166) and A167 );
a7548a <=( (not A168) and a7547a );
a7549a <=( a7548a and a7543a );
a7553a <=( (not A298) and A200 );
a7554a <=( A199 and a7553a );
a7558a <=( A302 and A300 );
a7559a <=( A299 and a7558a );
a7560a <=( a7559a and a7554a );
a7563a <=( (not A169) and A170 );
a7567a <=( (not A166) and A167 );
a7568a <=( (not A168) and a7567a );
a7569a <=( a7568a and a7563a );
a7573a <=( A298 and (not A200) );
a7574a <=( (not A199) and a7573a );
a7578a <=( A301 and A300 );
a7579a <=( (not A299) and a7578a );
a7580a <=( a7579a and a7574a );
a7583a <=( (not A169) and A170 );
a7587a <=( (not A166) and A167 );
a7588a <=( (not A168) and a7587a );
a7589a <=( a7588a and a7583a );
a7593a <=( A298 and (not A200) );
a7594a <=( (not A199) and a7593a );
a7598a <=( A302 and A300 );
a7599a <=( (not A299) and a7598a );
a7600a <=( a7599a and a7594a );
a7603a <=( (not A169) and A170 );
a7607a <=( (not A166) and A167 );
a7608a <=( (not A168) and a7607a );
a7609a <=( a7608a and a7603a );
a7613a <=( (not A298) and (not A200) );
a7614a <=( (not A199) and a7613a );
a7618a <=( A301 and A300 );
a7619a <=( A299 and a7618a );
a7620a <=( a7619a and a7614a );
a7623a <=( (not A169) and A170 );
a7627a <=( (not A166) and A167 );
a7628a <=( (not A168) and a7627a );
a7629a <=( a7628a and a7623a );
a7633a <=( (not A298) and (not A200) );
a7634a <=( (not A199) and a7633a );
a7638a <=( A302 and A300 );
a7639a <=( A299 and a7638a );
a7640a <=( a7639a and a7634a );
a7643a <=( (not A169) and A170 );
a7647a <=( A166 and (not A167) );
a7648a <=( (not A168) and a7647a );
a7649a <=( a7648a and a7643a );
a7653a <=( A298 and A202 );
a7654a <=( (not A201) and a7653a );
a7658a <=( A301 and A300 );
a7659a <=( (not A299) and a7658a );
a7660a <=( a7659a and a7654a );
a7663a <=( (not A169) and A170 );
a7667a <=( A166 and (not A167) );
a7668a <=( (not A168) and a7667a );
a7669a <=( a7668a and a7663a );
a7673a <=( A298 and A202 );
a7674a <=( (not A201) and a7673a );
a7678a <=( A302 and A300 );
a7679a <=( (not A299) and a7678a );
a7680a <=( a7679a and a7674a );
a7683a <=( (not A169) and A170 );
a7687a <=( A166 and (not A167) );
a7688a <=( (not A168) and a7687a );
a7689a <=( a7688a and a7683a );
a7693a <=( (not A298) and A202 );
a7694a <=( (not A201) and a7693a );
a7698a <=( A301 and A300 );
a7699a <=( A299 and a7698a );
a7700a <=( a7699a and a7694a );
a7703a <=( (not A169) and A170 );
a7707a <=( A166 and (not A167) );
a7708a <=( (not A168) and a7707a );
a7709a <=( a7708a and a7703a );
a7713a <=( (not A298) and A202 );
a7714a <=( (not A201) and a7713a );
a7718a <=( A302 and A300 );
a7719a <=( A299 and a7718a );
a7720a <=( a7719a and a7714a );
a7723a <=( (not A169) and A170 );
a7727a <=( A166 and (not A167) );
a7728a <=( (not A168) and a7727a );
a7729a <=( a7728a and a7723a );
a7733a <=( A298 and A203 );
a7734a <=( (not A201) and a7733a );
a7738a <=( A301 and A300 );
a7739a <=( (not A299) and a7738a );
a7740a <=( a7739a and a7734a );
a7743a <=( (not A169) and A170 );
a7747a <=( A166 and (not A167) );
a7748a <=( (not A168) and a7747a );
a7749a <=( a7748a and a7743a );
a7753a <=( A298 and A203 );
a7754a <=( (not A201) and a7753a );
a7758a <=( A302 and A300 );
a7759a <=( (not A299) and a7758a );
a7760a <=( a7759a and a7754a );
a7763a <=( (not A169) and A170 );
a7767a <=( A166 and (not A167) );
a7768a <=( (not A168) and a7767a );
a7769a <=( a7768a and a7763a );
a7773a <=( (not A298) and A203 );
a7774a <=( (not A201) and a7773a );
a7778a <=( A301 and A300 );
a7779a <=( A299 and a7778a );
a7780a <=( a7779a and a7774a );
a7783a <=( (not A169) and A170 );
a7787a <=( A166 and (not A167) );
a7788a <=( (not A168) and a7787a );
a7789a <=( a7788a and a7783a );
a7793a <=( (not A298) and A203 );
a7794a <=( (not A201) and a7793a );
a7798a <=( A302 and A300 );
a7799a <=( A299 and a7798a );
a7800a <=( a7799a and a7794a );
a7803a <=( (not A169) and A170 );
a7807a <=( A166 and (not A167) );
a7808a <=( (not A168) and a7807a );
a7809a <=( a7808a and a7803a );
a7813a <=( A298 and A200 );
a7814a <=( A199 and a7813a );
a7818a <=( A301 and A300 );
a7819a <=( (not A299) and a7818a );
a7820a <=( a7819a and a7814a );
a7823a <=( (not A169) and A170 );
a7827a <=( A166 and (not A167) );
a7828a <=( (not A168) and a7827a );
a7829a <=( a7828a and a7823a );
a7833a <=( A298 and A200 );
a7834a <=( A199 and a7833a );
a7838a <=( A302 and A300 );
a7839a <=( (not A299) and a7838a );
a7840a <=( a7839a and a7834a );
a7843a <=( (not A169) and A170 );
a7847a <=( A166 and (not A167) );
a7848a <=( (not A168) and a7847a );
a7849a <=( a7848a and a7843a );
a7853a <=( (not A298) and A200 );
a7854a <=( A199 and a7853a );
a7858a <=( A301 and A300 );
a7859a <=( A299 and a7858a );
a7860a <=( a7859a and a7854a );
a7863a <=( (not A169) and A170 );
a7867a <=( A166 and (not A167) );
a7868a <=( (not A168) and a7867a );
a7869a <=( a7868a and a7863a );
a7873a <=( (not A298) and A200 );
a7874a <=( A199 and a7873a );
a7878a <=( A302 and A300 );
a7879a <=( A299 and a7878a );
a7880a <=( a7879a and a7874a );
a7883a <=( (not A169) and A170 );
a7887a <=( A166 and (not A167) );
a7888a <=( (not A168) and a7887a );
a7889a <=( a7888a and a7883a );
a7893a <=( A298 and (not A200) );
a7894a <=( (not A199) and a7893a );
a7898a <=( A301 and A300 );
a7899a <=( (not A299) and a7898a );
a7900a <=( a7899a and a7894a );
a7903a <=( (not A169) and A170 );
a7907a <=( A166 and (not A167) );
a7908a <=( (not A168) and a7907a );
a7909a <=( a7908a and a7903a );
a7913a <=( A298 and (not A200) );
a7914a <=( (not A199) and a7913a );
a7918a <=( A302 and A300 );
a7919a <=( (not A299) and a7918a );
a7920a <=( a7919a and a7914a );
a7923a <=( (not A169) and A170 );
a7927a <=( A166 and (not A167) );
a7928a <=( (not A168) and a7927a );
a7929a <=( a7928a and a7923a );
a7933a <=( (not A298) and (not A200) );
a7934a <=( (not A199) and a7933a );
a7938a <=( A301 and A300 );
a7939a <=( A299 and a7938a );
a7940a <=( a7939a and a7934a );
a7943a <=( (not A169) and A170 );
a7947a <=( A166 and (not A167) );
a7948a <=( (not A168) and a7947a );
a7949a <=( a7948a and a7943a );
a7953a <=( (not A298) and (not A200) );
a7954a <=( (not A199) and a7953a );
a7958a <=( A302 and A300 );
a7959a <=( A299 and a7958a );
a7960a <=( a7959a and a7954a );
a7964a <=( (not A199) and A166 );
a7965a <=( A167 and a7964a );
a7969a <=( (not A202) and (not A201) );
a7970a <=( A200 and a7969a );
a7971a <=( a7970a and a7965a );
a7975a <=( (not A299) and A298 );
a7976a <=( (not A203) and a7975a );
a7980a <=( (not A302) and (not A301) );
a7981a <=( (not A300) and a7980a );
a7982a <=( a7981a and a7976a );
a7986a <=( (not A199) and A166 );
a7987a <=( A167 and a7986a );
a7991a <=( (not A202) and (not A201) );
a7992a <=( A200 and a7991a );
a7993a <=( a7992a and a7987a );
a7997a <=( A299 and (not A298) );
a7998a <=( (not A203) and a7997a );
a8002a <=( (not A302) and (not A301) );
a8003a <=( (not A300) and a8002a );
a8004a <=( a8003a and a7998a );
a8008a <=( A199 and A166 );
a8009a <=( A167 and a8008a );
a8013a <=( (not A202) and (not A201) );
a8014a <=( (not A200) and a8013a );
a8015a <=( a8014a and a8009a );
a8019a <=( (not A299) and A298 );
a8020a <=( (not A203) and a8019a );
a8024a <=( (not A302) and (not A301) );
a8025a <=( (not A300) and a8024a );
a8026a <=( a8025a and a8020a );
a8030a <=( A199 and A166 );
a8031a <=( A167 and a8030a );
a8035a <=( (not A202) and (not A201) );
a8036a <=( (not A200) and a8035a );
a8037a <=( a8036a and a8031a );
a8041a <=( A299 and (not A298) );
a8042a <=( (not A203) and a8041a );
a8046a <=( (not A302) and (not A301) );
a8047a <=( (not A300) and a8046a );
a8048a <=( a8047a and a8042a );
a8052a <=( (not A199) and (not A166) );
a8053a <=( (not A167) and a8052a );
a8057a <=( (not A202) and (not A201) );
a8058a <=( A200 and a8057a );
a8059a <=( a8058a and a8053a );
a8063a <=( (not A299) and A298 );
a8064a <=( (not A203) and a8063a );
a8068a <=( (not A302) and (not A301) );
a8069a <=( (not A300) and a8068a );
a8070a <=( a8069a and a8064a );
a8074a <=( (not A199) and (not A166) );
a8075a <=( (not A167) and a8074a );
a8079a <=( (not A202) and (not A201) );
a8080a <=( A200 and a8079a );
a8081a <=( a8080a and a8075a );
a8085a <=( A299 and (not A298) );
a8086a <=( (not A203) and a8085a );
a8090a <=( (not A302) and (not A301) );
a8091a <=( (not A300) and a8090a );
a8092a <=( a8091a and a8086a );
a8096a <=( A199 and (not A166) );
a8097a <=( (not A167) and a8096a );
a8101a <=( (not A202) and (not A201) );
a8102a <=( (not A200) and a8101a );
a8103a <=( a8102a and a8097a );
a8107a <=( (not A299) and A298 );
a8108a <=( (not A203) and a8107a );
a8112a <=( (not A302) and (not A301) );
a8113a <=( (not A300) and a8112a );
a8114a <=( a8113a and a8108a );
a8118a <=( A199 and (not A166) );
a8119a <=( (not A167) and a8118a );
a8123a <=( (not A202) and (not A201) );
a8124a <=( (not A200) and a8123a );
a8125a <=( a8124a and a8119a );
a8129a <=( A299 and (not A298) );
a8130a <=( (not A203) and a8129a );
a8134a <=( (not A302) and (not A301) );
a8135a <=( (not A300) and a8134a );
a8136a <=( a8135a and a8130a );
a8140a <=( A167 and A168 );
a8141a <=( (not A170) and a8140a );
a8145a <=( (not A202) and A201 );
a8146a <=( (not A166) and a8145a );
a8147a <=( a8146a and a8141a );
a8151a <=( (not A299) and A298 );
a8152a <=( (not A203) and a8151a );
a8156a <=( (not A302) and (not A301) );
a8157a <=( (not A300) and a8156a );
a8158a <=( a8157a and a8152a );
a8162a <=( A167 and A168 );
a8163a <=( (not A170) and a8162a );
a8167a <=( (not A202) and A201 );
a8168a <=( (not A166) and a8167a );
a8169a <=( a8168a and a8163a );
a8173a <=( A299 and (not A298) );
a8174a <=( (not A203) and a8173a );
a8178a <=( (not A302) and (not A301) );
a8179a <=( (not A300) and a8178a );
a8180a <=( a8179a and a8174a );
a8184a <=( (not A167) and A168 );
a8185a <=( (not A170) and a8184a );
a8189a <=( (not A202) and A201 );
a8190a <=( A166 and a8189a );
a8191a <=( a8190a and a8185a );
a8195a <=( (not A299) and A298 );
a8196a <=( (not A203) and a8195a );
a8200a <=( (not A302) and (not A301) );
a8201a <=( (not A300) and a8200a );
a8202a <=( a8201a and a8196a );
a8206a <=( (not A167) and A168 );
a8207a <=( (not A170) and a8206a );
a8211a <=( (not A202) and A201 );
a8212a <=( A166 and a8211a );
a8213a <=( a8212a and a8207a );
a8217a <=( A299 and (not A298) );
a8218a <=( (not A203) and a8217a );
a8222a <=( (not A302) and (not A301) );
a8223a <=( (not A300) and a8222a );
a8224a <=( a8223a and a8218a );
a8228a <=( (not A199) and (not A168) );
a8229a <=( (not A170) and a8228a );
a8233a <=( (not A202) and (not A201) );
a8234a <=( A200 and a8233a );
a8235a <=( a8234a and a8229a );
a8239a <=( (not A299) and A298 );
a8240a <=( (not A203) and a8239a );
a8244a <=( (not A302) and (not A301) );
a8245a <=( (not A300) and a8244a );
a8246a <=( a8245a and a8240a );
a8250a <=( (not A199) and (not A168) );
a8251a <=( (not A170) and a8250a );
a8255a <=( (not A202) and (not A201) );
a8256a <=( A200 and a8255a );
a8257a <=( a8256a and a8251a );
a8261a <=( A299 and (not A298) );
a8262a <=( (not A203) and a8261a );
a8266a <=( (not A302) and (not A301) );
a8267a <=( (not A300) and a8266a );
a8268a <=( a8267a and a8262a );
a8272a <=( A199 and (not A168) );
a8273a <=( (not A170) and a8272a );
a8277a <=( (not A202) and (not A201) );
a8278a <=( (not A200) and a8277a );
a8279a <=( a8278a and a8273a );
a8283a <=( (not A299) and A298 );
a8284a <=( (not A203) and a8283a );
a8288a <=( (not A302) and (not A301) );
a8289a <=( (not A300) and a8288a );
a8290a <=( a8289a and a8284a );
a8294a <=( A199 and (not A168) );
a8295a <=( (not A170) and a8294a );
a8299a <=( (not A202) and (not A201) );
a8300a <=( (not A200) and a8299a );
a8301a <=( a8300a and a8295a );
a8305a <=( A299 and (not A298) );
a8306a <=( (not A203) and a8305a );
a8310a <=( (not A302) and (not A301) );
a8311a <=( (not A300) and a8310a );
a8312a <=( a8311a and a8306a );
a8316a <=( A167 and A168 );
a8317a <=( A169 and a8316a );
a8321a <=( (not A202) and A201 );
a8322a <=( (not A166) and a8321a );
a8323a <=( a8322a and a8317a );
a8327a <=( (not A299) and A298 );
a8328a <=( (not A203) and a8327a );
a8332a <=( (not A302) and (not A301) );
a8333a <=( (not A300) and a8332a );
a8334a <=( a8333a and a8328a );
a8338a <=( A167 and A168 );
a8339a <=( A169 and a8338a );
a8343a <=( (not A202) and A201 );
a8344a <=( (not A166) and a8343a );
a8345a <=( a8344a and a8339a );
a8349a <=( A299 and (not A298) );
a8350a <=( (not A203) and a8349a );
a8354a <=( (not A302) and (not A301) );
a8355a <=( (not A300) and a8354a );
a8356a <=( a8355a and a8350a );
a8360a <=( (not A167) and A168 );
a8361a <=( A169 and a8360a );
a8365a <=( (not A202) and A201 );
a8366a <=( A166 and a8365a );
a8367a <=( a8366a and a8361a );
a8371a <=( (not A299) and A298 );
a8372a <=( (not A203) and a8371a );
a8376a <=( (not A302) and (not A301) );
a8377a <=( (not A300) and a8376a );
a8378a <=( a8377a and a8372a );
a8382a <=( (not A167) and A168 );
a8383a <=( A169 and a8382a );
a8387a <=( (not A202) and A201 );
a8388a <=( A166 and a8387a );
a8389a <=( a8388a and a8383a );
a8393a <=( A299 and (not A298) );
a8394a <=( (not A203) and a8393a );
a8398a <=( (not A302) and (not A301) );
a8399a <=( (not A300) and a8398a );
a8400a <=( a8399a and a8394a );
a8404a <=( (not A199) and (not A168) );
a8405a <=( A169 and a8404a );
a8409a <=( (not A202) and (not A201) );
a8410a <=( A200 and a8409a );
a8411a <=( a8410a and a8405a );
a8415a <=( (not A299) and A298 );
a8416a <=( (not A203) and a8415a );
a8420a <=( (not A302) and (not A301) );
a8421a <=( (not A300) and a8420a );
a8422a <=( a8421a and a8416a );
a8426a <=( (not A199) and (not A168) );
a8427a <=( A169 and a8426a );
a8431a <=( (not A202) and (not A201) );
a8432a <=( A200 and a8431a );
a8433a <=( a8432a and a8427a );
a8437a <=( A299 and (not A298) );
a8438a <=( (not A203) and a8437a );
a8442a <=( (not A302) and (not A301) );
a8443a <=( (not A300) and a8442a );
a8444a <=( a8443a and a8438a );
a8448a <=( A199 and (not A168) );
a8449a <=( A169 and a8448a );
a8453a <=( (not A202) and (not A201) );
a8454a <=( (not A200) and a8453a );
a8455a <=( a8454a and a8449a );
a8459a <=( (not A299) and A298 );
a8460a <=( (not A203) and a8459a );
a8464a <=( (not A302) and (not A301) );
a8465a <=( (not A300) and a8464a );
a8466a <=( a8465a and a8460a );
a8470a <=( A199 and (not A168) );
a8471a <=( A169 and a8470a );
a8475a <=( (not A202) and (not A201) );
a8476a <=( (not A200) and a8475a );
a8477a <=( a8476a and a8471a );
a8481a <=( A299 and (not A298) );
a8482a <=( (not A203) and a8481a );
a8486a <=( (not A302) and (not A301) );
a8487a <=( (not A300) and a8486a );
a8488a <=( a8487a and a8482a );
a8492a <=( A168 and (not A169) );
a8493a <=( A170 and a8492a );
a8497a <=( A201 and A200 );
a8498a <=( (not A199) and a8497a );
a8499a <=( a8498a and a8493a );
a8503a <=( (not A299) and A298 );
a8504a <=( A202 and a8503a );
a8508a <=( (not A302) and (not A301) );
a8509a <=( (not A300) and a8508a );
a8510a <=( a8509a and a8504a );
a8514a <=( A168 and (not A169) );
a8515a <=( A170 and a8514a );
a8519a <=( A201 and A200 );
a8520a <=( (not A199) and a8519a );
a8521a <=( a8520a and a8515a );
a8525a <=( A299 and (not A298) );
a8526a <=( A202 and a8525a );
a8530a <=( (not A302) and (not A301) );
a8531a <=( (not A300) and a8530a );
a8532a <=( a8531a and a8526a );
a8536a <=( A168 and (not A169) );
a8537a <=( A170 and a8536a );
a8541a <=( A201 and A200 );
a8542a <=( (not A199) and a8541a );
a8543a <=( a8542a and a8537a );
a8547a <=( (not A299) and A298 );
a8548a <=( A203 and a8547a );
a8552a <=( (not A302) and (not A301) );
a8553a <=( (not A300) and a8552a );
a8554a <=( a8553a and a8548a );
a8558a <=( A168 and (not A169) );
a8559a <=( A170 and a8558a );
a8563a <=( A201 and A200 );
a8564a <=( (not A199) and a8563a );
a8565a <=( a8564a and a8559a );
a8569a <=( A299 and (not A298) );
a8570a <=( A203 and a8569a );
a8574a <=( (not A302) and (not A301) );
a8575a <=( (not A300) and a8574a );
a8576a <=( a8575a and a8570a );
a8580a <=( A168 and (not A169) );
a8581a <=( A170 and a8580a );
a8585a <=( (not A201) and A200 );
a8586a <=( (not A199) and a8585a );
a8587a <=( a8586a and a8581a );
a8591a <=( A298 and (not A203) );
a8592a <=( (not A202) and a8591a );
a8596a <=( A301 and A300 );
a8597a <=( (not A299) and a8596a );
a8598a <=( a8597a and a8592a );
a8602a <=( A168 and (not A169) );
a8603a <=( A170 and a8602a );
a8607a <=( (not A201) and A200 );
a8608a <=( (not A199) and a8607a );
a8609a <=( a8608a and a8603a );
a8613a <=( A298 and (not A203) );
a8614a <=( (not A202) and a8613a );
a8618a <=( A302 and A300 );
a8619a <=( (not A299) and a8618a );
a8620a <=( a8619a and a8614a );
a8624a <=( A168 and (not A169) );
a8625a <=( A170 and a8624a );
a8629a <=( (not A201) and A200 );
a8630a <=( (not A199) and a8629a );
a8631a <=( a8630a and a8625a );
a8635a <=( (not A298) and (not A203) );
a8636a <=( (not A202) and a8635a );
a8640a <=( A301 and A300 );
a8641a <=( A299 and a8640a );
a8642a <=( a8641a and a8636a );
a8646a <=( A168 and (not A169) );
a8647a <=( A170 and a8646a );
a8651a <=( (not A201) and A200 );
a8652a <=( (not A199) and a8651a );
a8653a <=( a8652a and a8647a );
a8657a <=( (not A298) and (not A203) );
a8658a <=( (not A202) and a8657a );
a8662a <=( A302 and A300 );
a8663a <=( A299 and a8662a );
a8664a <=( a8663a and a8658a );
a8668a <=( A168 and (not A169) );
a8669a <=( A170 and a8668a );
a8673a <=( A201 and (not A200) );
a8674a <=( A199 and a8673a );
a8675a <=( a8674a and a8669a );
a8679a <=( (not A299) and A298 );
a8680a <=( A202 and a8679a );
a8684a <=( (not A302) and (not A301) );
a8685a <=( (not A300) and a8684a );
a8686a <=( a8685a and a8680a );
a8690a <=( A168 and (not A169) );
a8691a <=( A170 and a8690a );
a8695a <=( A201 and (not A200) );
a8696a <=( A199 and a8695a );
a8697a <=( a8696a and a8691a );
a8701a <=( A299 and (not A298) );
a8702a <=( A202 and a8701a );
a8706a <=( (not A302) and (not A301) );
a8707a <=( (not A300) and a8706a );
a8708a <=( a8707a and a8702a );
a8712a <=( A168 and (not A169) );
a8713a <=( A170 and a8712a );
a8717a <=( A201 and (not A200) );
a8718a <=( A199 and a8717a );
a8719a <=( a8718a and a8713a );
a8723a <=( (not A299) and A298 );
a8724a <=( A203 and a8723a );
a8728a <=( (not A302) and (not A301) );
a8729a <=( (not A300) and a8728a );
a8730a <=( a8729a and a8724a );
a8734a <=( A168 and (not A169) );
a8735a <=( A170 and a8734a );
a8739a <=( A201 and (not A200) );
a8740a <=( A199 and a8739a );
a8741a <=( a8740a and a8735a );
a8745a <=( A299 and (not A298) );
a8746a <=( A203 and a8745a );
a8750a <=( (not A302) and (not A301) );
a8751a <=( (not A300) and a8750a );
a8752a <=( a8751a and a8746a );
a8756a <=( A168 and (not A169) );
a8757a <=( A170 and a8756a );
a8761a <=( (not A201) and (not A200) );
a8762a <=( A199 and a8761a );
a8763a <=( a8762a and a8757a );
a8767a <=( A298 and (not A203) );
a8768a <=( (not A202) and a8767a );
a8772a <=( A301 and A300 );
a8773a <=( (not A299) and a8772a );
a8774a <=( a8773a and a8768a );
a8778a <=( A168 and (not A169) );
a8779a <=( A170 and a8778a );
a8783a <=( (not A201) and (not A200) );
a8784a <=( A199 and a8783a );
a8785a <=( a8784a and a8779a );
a8789a <=( A298 and (not A203) );
a8790a <=( (not A202) and a8789a );
a8794a <=( A302 and A300 );
a8795a <=( (not A299) and a8794a );
a8796a <=( a8795a and a8790a );
a8800a <=( A168 and (not A169) );
a8801a <=( A170 and a8800a );
a8805a <=( (not A201) and (not A200) );
a8806a <=( A199 and a8805a );
a8807a <=( a8806a and a8801a );
a8811a <=( (not A298) and (not A203) );
a8812a <=( (not A202) and a8811a );
a8816a <=( A301 and A300 );
a8817a <=( A299 and a8816a );
a8818a <=( a8817a and a8812a );
a8822a <=( A168 and (not A169) );
a8823a <=( A170 and a8822a );
a8827a <=( (not A201) and (not A200) );
a8828a <=( A199 and a8827a );
a8829a <=( a8828a and a8823a );
a8833a <=( (not A298) and (not A203) );
a8834a <=( (not A202) and a8833a );
a8838a <=( A302 and A300 );
a8839a <=( A299 and a8838a );
a8840a <=( a8839a and a8834a );
a8844a <=( (not A168) and (not A169) );
a8845a <=( A170 and a8844a );
a8849a <=( A201 and (not A166) );
a8850a <=( A167 and a8849a );
a8851a <=( a8850a and a8845a );
a8855a <=( A298 and (not A203) );
a8856a <=( (not A202) and a8855a );
a8860a <=( A301 and A300 );
a8861a <=( (not A299) and a8860a );
a8862a <=( a8861a and a8856a );
a8866a <=( (not A168) and (not A169) );
a8867a <=( A170 and a8866a );
a8871a <=( A201 and (not A166) );
a8872a <=( A167 and a8871a );
a8873a <=( a8872a and a8867a );
a8877a <=( A298 and (not A203) );
a8878a <=( (not A202) and a8877a );
a8882a <=( A302 and A300 );
a8883a <=( (not A299) and a8882a );
a8884a <=( a8883a and a8878a );
a8888a <=( (not A168) and (not A169) );
a8889a <=( A170 and a8888a );
a8893a <=( A201 and (not A166) );
a8894a <=( A167 and a8893a );
a8895a <=( a8894a and a8889a );
a8899a <=( (not A298) and (not A203) );
a8900a <=( (not A202) and a8899a );
a8904a <=( A301 and A300 );
a8905a <=( A299 and a8904a );
a8906a <=( a8905a and a8900a );
a8910a <=( (not A168) and (not A169) );
a8911a <=( A170 and a8910a );
a8915a <=( A201 and (not A166) );
a8916a <=( A167 and a8915a );
a8917a <=( a8916a and a8911a );
a8921a <=( (not A298) and (not A203) );
a8922a <=( (not A202) and a8921a );
a8926a <=( A302 and A300 );
a8927a <=( A299 and a8926a );
a8928a <=( a8927a and a8922a );
a8932a <=( (not A168) and (not A169) );
a8933a <=( A170 and a8932a );
a8937a <=( (not A201) and (not A166) );
a8938a <=( A167 and a8937a );
a8939a <=( a8938a and a8933a );
a8943a <=( (not A299) and A298 );
a8944a <=( A202 and a8943a );
a8948a <=( (not A302) and (not A301) );
a8949a <=( (not A300) and a8948a );
a8950a <=( a8949a and a8944a );
a8954a <=( (not A168) and (not A169) );
a8955a <=( A170 and a8954a );
a8959a <=( (not A201) and (not A166) );
a8960a <=( A167 and a8959a );
a8961a <=( a8960a and a8955a );
a8965a <=( A299 and (not A298) );
a8966a <=( A202 and a8965a );
a8970a <=( (not A302) and (not A301) );
a8971a <=( (not A300) and a8970a );
a8972a <=( a8971a and a8966a );
a8976a <=( (not A168) and (not A169) );
a8977a <=( A170 and a8976a );
a8981a <=( (not A201) and (not A166) );
a8982a <=( A167 and a8981a );
a8983a <=( a8982a and a8977a );
a8987a <=( (not A299) and A298 );
a8988a <=( A203 and a8987a );
a8992a <=( (not A302) and (not A301) );
a8993a <=( (not A300) and a8992a );
a8994a <=( a8993a and a8988a );
a8998a <=( (not A168) and (not A169) );
a8999a <=( A170 and a8998a );
a9003a <=( (not A201) and (not A166) );
a9004a <=( A167 and a9003a );
a9005a <=( a9004a and a8999a );
a9009a <=( A299 and (not A298) );
a9010a <=( A203 and a9009a );
a9014a <=( (not A302) and (not A301) );
a9015a <=( (not A300) and a9014a );
a9016a <=( a9015a and a9010a );
a9020a <=( (not A168) and (not A169) );
a9021a <=( A170 and a9020a );
a9025a <=( A199 and (not A166) );
a9026a <=( A167 and a9025a );
a9027a <=( a9026a and a9021a );
a9031a <=( (not A299) and A298 );
a9032a <=( A200 and a9031a );
a9036a <=( (not A302) and (not A301) );
a9037a <=( (not A300) and a9036a );
a9038a <=( a9037a and a9032a );
a9042a <=( (not A168) and (not A169) );
a9043a <=( A170 and a9042a );
a9047a <=( A199 and (not A166) );
a9048a <=( A167 and a9047a );
a9049a <=( a9048a and a9043a );
a9053a <=( A299 and (not A298) );
a9054a <=( A200 and a9053a );
a9058a <=( (not A302) and (not A301) );
a9059a <=( (not A300) and a9058a );
a9060a <=( a9059a and a9054a );
a9064a <=( (not A168) and (not A169) );
a9065a <=( A170 and a9064a );
a9069a <=( (not A199) and (not A166) );
a9070a <=( A167 and a9069a );
a9071a <=( a9070a and a9065a );
a9075a <=( (not A299) and A298 );
a9076a <=( (not A200) and a9075a );
a9080a <=( (not A302) and (not A301) );
a9081a <=( (not A300) and a9080a );
a9082a <=( a9081a and a9076a );
a9086a <=( (not A168) and (not A169) );
a9087a <=( A170 and a9086a );
a9091a <=( (not A199) and (not A166) );
a9092a <=( A167 and a9091a );
a9093a <=( a9092a and a9087a );
a9097a <=( A299 and (not A298) );
a9098a <=( (not A200) and a9097a );
a9102a <=( (not A302) and (not A301) );
a9103a <=( (not A300) and a9102a );
a9104a <=( a9103a and a9098a );
a9108a <=( (not A168) and (not A169) );
a9109a <=( A170 and a9108a );
a9113a <=( A201 and A166 );
a9114a <=( (not A167) and a9113a );
a9115a <=( a9114a and a9109a );
a9119a <=( A298 and (not A203) );
a9120a <=( (not A202) and a9119a );
a9124a <=( A301 and A300 );
a9125a <=( (not A299) and a9124a );
a9126a <=( a9125a and a9120a );
a9130a <=( (not A168) and (not A169) );
a9131a <=( A170 and a9130a );
a9135a <=( A201 and A166 );
a9136a <=( (not A167) and a9135a );
a9137a <=( a9136a and a9131a );
a9141a <=( A298 and (not A203) );
a9142a <=( (not A202) and a9141a );
a9146a <=( A302 and A300 );
a9147a <=( (not A299) and a9146a );
a9148a <=( a9147a and a9142a );
a9152a <=( (not A168) and (not A169) );
a9153a <=( A170 and a9152a );
a9157a <=( A201 and A166 );
a9158a <=( (not A167) and a9157a );
a9159a <=( a9158a and a9153a );
a9163a <=( (not A298) and (not A203) );
a9164a <=( (not A202) and a9163a );
a9168a <=( A301 and A300 );
a9169a <=( A299 and a9168a );
a9170a <=( a9169a and a9164a );
a9174a <=( (not A168) and (not A169) );
a9175a <=( A170 and a9174a );
a9179a <=( A201 and A166 );
a9180a <=( (not A167) and a9179a );
a9181a <=( a9180a and a9175a );
a9185a <=( (not A298) and (not A203) );
a9186a <=( (not A202) and a9185a );
a9190a <=( A302 and A300 );
a9191a <=( A299 and a9190a );
a9192a <=( a9191a and a9186a );
a9196a <=( (not A168) and (not A169) );
a9197a <=( A170 and a9196a );
a9201a <=( (not A201) and A166 );
a9202a <=( (not A167) and a9201a );
a9203a <=( a9202a and a9197a );
a9207a <=( (not A299) and A298 );
a9208a <=( A202 and a9207a );
a9212a <=( (not A302) and (not A301) );
a9213a <=( (not A300) and a9212a );
a9214a <=( a9213a and a9208a );
a9218a <=( (not A168) and (not A169) );
a9219a <=( A170 and a9218a );
a9223a <=( (not A201) and A166 );
a9224a <=( (not A167) and a9223a );
a9225a <=( a9224a and a9219a );
a9229a <=( A299 and (not A298) );
a9230a <=( A202 and a9229a );
a9234a <=( (not A302) and (not A301) );
a9235a <=( (not A300) and a9234a );
a9236a <=( a9235a and a9230a );
a9240a <=( (not A168) and (not A169) );
a9241a <=( A170 and a9240a );
a9245a <=( (not A201) and A166 );
a9246a <=( (not A167) and a9245a );
a9247a <=( a9246a and a9241a );
a9251a <=( (not A299) and A298 );
a9252a <=( A203 and a9251a );
a9256a <=( (not A302) and (not A301) );
a9257a <=( (not A300) and a9256a );
a9258a <=( a9257a and a9252a );
a9262a <=( (not A168) and (not A169) );
a9263a <=( A170 and a9262a );
a9267a <=( (not A201) and A166 );
a9268a <=( (not A167) and a9267a );
a9269a <=( a9268a and a9263a );
a9273a <=( A299 and (not A298) );
a9274a <=( A203 and a9273a );
a9278a <=( (not A302) and (not A301) );
a9279a <=( (not A300) and a9278a );
a9280a <=( a9279a and a9274a );
a9284a <=( (not A168) and (not A169) );
a9285a <=( A170 and a9284a );
a9289a <=( A199 and A166 );
a9290a <=( (not A167) and a9289a );
a9291a <=( a9290a and a9285a );
a9295a <=( (not A299) and A298 );
a9296a <=( A200 and a9295a );
a9300a <=( (not A302) and (not A301) );
a9301a <=( (not A300) and a9300a );
a9302a <=( a9301a and a9296a );
a9306a <=( (not A168) and (not A169) );
a9307a <=( A170 and a9306a );
a9311a <=( A199 and A166 );
a9312a <=( (not A167) and a9311a );
a9313a <=( a9312a and a9307a );
a9317a <=( A299 and (not A298) );
a9318a <=( A200 and a9317a );
a9322a <=( (not A302) and (not A301) );
a9323a <=( (not A300) and a9322a );
a9324a <=( a9323a and a9318a );
a9328a <=( (not A168) and (not A169) );
a9329a <=( A170 and a9328a );
a9333a <=( (not A199) and A166 );
a9334a <=( (not A167) and a9333a );
a9335a <=( a9334a and a9329a );
a9339a <=( (not A299) and A298 );
a9340a <=( (not A200) and a9339a );
a9344a <=( (not A302) and (not A301) );
a9345a <=( (not A300) and a9344a );
a9346a <=( a9345a and a9340a );
a9350a <=( (not A168) and (not A169) );
a9351a <=( A170 and a9350a );
a9355a <=( (not A199) and A166 );
a9356a <=( (not A167) and a9355a );
a9357a <=( a9356a and a9351a );
a9361a <=( A299 and (not A298) );
a9362a <=( (not A200) and a9361a );
a9366a <=( (not A302) and (not A301) );
a9367a <=( (not A300) and a9366a );
a9368a <=( a9367a and a9362a );
a9372a <=( A168 and (not A169) );
a9373a <=( A170 and a9372a );
a9377a <=( (not A201) and A200 );
a9378a <=( (not A199) and a9377a );
a9379a <=( a9378a and a9373a );
a9383a <=( A298 and (not A203) );
a9384a <=( (not A202) and a9383a );
a9387a <=( (not A300) and (not A299) );
a9390a <=( (not A302) and (not A301) );
a9391a <=( a9390a and a9387a );
a9392a <=( a9391a and a9384a );
a9396a <=( A168 and (not A169) );
a9397a <=( A170 and a9396a );
a9401a <=( (not A201) and A200 );
a9402a <=( (not A199) and a9401a );
a9403a <=( a9402a and a9397a );
a9407a <=( (not A298) and (not A203) );
a9408a <=( (not A202) and a9407a );
a9411a <=( (not A300) and A299 );
a9414a <=( (not A302) and (not A301) );
a9415a <=( a9414a and a9411a );
a9416a <=( a9415a and a9408a );
a9420a <=( A168 and (not A169) );
a9421a <=( A170 and a9420a );
a9425a <=( (not A201) and (not A200) );
a9426a <=( A199 and a9425a );
a9427a <=( a9426a and a9421a );
a9431a <=( A298 and (not A203) );
a9432a <=( (not A202) and a9431a );
a9435a <=( (not A300) and (not A299) );
a9438a <=( (not A302) and (not A301) );
a9439a <=( a9438a and a9435a );
a9440a <=( a9439a and a9432a );
a9444a <=( A168 and (not A169) );
a9445a <=( A170 and a9444a );
a9449a <=( (not A201) and (not A200) );
a9450a <=( A199 and a9449a );
a9451a <=( a9450a and a9445a );
a9455a <=( (not A298) and (not A203) );
a9456a <=( (not A202) and a9455a );
a9459a <=( (not A300) and A299 );
a9462a <=( (not A302) and (not A301) );
a9463a <=( a9462a and a9459a );
a9464a <=( a9463a and a9456a );
a9468a <=( (not A168) and (not A169) );
a9469a <=( A170 and a9468a );
a9473a <=( A201 and (not A166) );
a9474a <=( A167 and a9473a );
a9475a <=( a9474a and a9469a );
a9479a <=( A298 and (not A203) );
a9480a <=( (not A202) and a9479a );
a9483a <=( (not A300) and (not A299) );
a9486a <=( (not A302) and (not A301) );
a9487a <=( a9486a and a9483a );
a9488a <=( a9487a and a9480a );
a9492a <=( (not A168) and (not A169) );
a9493a <=( A170 and a9492a );
a9497a <=( A201 and (not A166) );
a9498a <=( A167 and a9497a );
a9499a <=( a9498a and a9493a );
a9503a <=( (not A298) and (not A203) );
a9504a <=( (not A202) and a9503a );
a9507a <=( (not A300) and A299 );
a9510a <=( (not A302) and (not A301) );
a9511a <=( a9510a and a9507a );
a9512a <=( a9511a and a9504a );
a9516a <=( (not A168) and (not A169) );
a9517a <=( A170 and a9516a );
a9521a <=( A201 and A166 );
a9522a <=( (not A167) and a9521a );
a9523a <=( a9522a and a9517a );
a9527a <=( A298 and (not A203) );
a9528a <=( (not A202) and a9527a );
a9531a <=( (not A300) and (not A299) );
a9534a <=( (not A302) and (not A301) );
a9535a <=( a9534a and a9531a );
a9536a <=( a9535a and a9528a );
a9540a <=( (not A168) and (not A169) );
a9541a <=( A170 and a9540a );
a9545a <=( A201 and A166 );
a9546a <=( (not A167) and a9545a );
a9547a <=( a9546a and a9541a );
a9551a <=( (not A298) and (not A203) );
a9552a <=( (not A202) and a9551a );
a9555a <=( (not A300) and A299 );
a9558a <=( (not A302) and (not A301) );
a9559a <=( a9558a and a9555a );
a9560a <=( a9559a and a9552a );
end x25_3x_behav;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:08:35 11/01/2015
-- Design Name:
-- Module Name: C:/Users/Colton/Desktop/Nibble_Knowledge_CPU/tb_clk_div_V2.vhd
-- Project Name: Nibble_Knowledge_CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: clock_divider_V2
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_clk_div_V2 IS
END tb_clk_div_V2;
ARCHITECTURE behavior OF tb_clk_div_V2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT clock_divider_V2
PORT(
clk : IN std_logic;
reset : IN std_logic;
clk_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal clk_out : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
--constant clk_out_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: clock_divider_V2 PORT MAP (
clk => clk,
reset => reset,
clk_out => clk_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*1000;
-- insert stimulus here
wait;
end process;
END;
|
-------------------------------------------------------------------------------
-- axi_vdma_vaddrreg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vaddrreg_mux.vhd
--
-- Description: This entity contains the mux for driving current video start
-- address to DMA Controller.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vaddrreg_mux is
generic(
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
C_ADDR_WIDTH : integer range 32 to 32 := 32
-- Start Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Current Frame Number --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Video Register Bank --
start_address_vid : in STARTADDR_ARRAY_TYPE --
(0 to C_NUM_FSTORES - 1) ; --
--
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vaddrreg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vaddrreg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal crnt_start_address_i : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d1 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d2 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal frame_number_index : integer := 0;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frame_number_index <= to_integer(unsigned(frame_number));
crnt_start_address_i <= start_address_vid(frame_number_index);
-- Pipe line for fmax (dble to allow for adjustments later if need be)
-----REG_ADDR_OUT : process(prmry_aclk)
----- begin
----- if(prmry_aclk'EVENT and prmry_aclk = '1')then
----- if(prmry_resetn = '0')then
----- crnt_start_address_d1 <= (others => '0');
----- crnt_start_address_d2 <= (others => '0');
----- else
----- crnt_start_address_d1 <= crnt_start_address_i;
----- crnt_start_address_d2 <= crnt_start_address_d1;
----- end if;
----- end if;
----- end process REG_ADDR_OUT;
-----
------crnt_start_address <= crnt_start_address_d2;
crnt_start_address <= crnt_start_address_i;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_vaddrreg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vaddrreg_mux.vhd
--
-- Description: This entity contains the mux for driving current video start
-- address to DMA Controller.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vaddrreg_mux is
generic(
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
C_ADDR_WIDTH : integer range 32 to 32 := 32
-- Start Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Current Frame Number --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Video Register Bank --
start_address_vid : in STARTADDR_ARRAY_TYPE --
(0 to C_NUM_FSTORES - 1) ; --
--
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vaddrreg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vaddrreg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal crnt_start_address_i : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d1 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d2 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal frame_number_index : integer := 0;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frame_number_index <= to_integer(unsigned(frame_number));
crnt_start_address_i <= start_address_vid(frame_number_index);
-- Pipe line for fmax (dble to allow for adjustments later if need be)
-----REG_ADDR_OUT : process(prmry_aclk)
----- begin
----- if(prmry_aclk'EVENT and prmry_aclk = '1')then
----- if(prmry_resetn = '0')then
----- crnt_start_address_d1 <= (others => '0');
----- crnt_start_address_d2 <= (others => '0');
----- else
----- crnt_start_address_d1 <= crnt_start_address_i;
----- crnt_start_address_d2 <= crnt_start_address_d1;
----- end if;
----- end if;
----- end process REG_ADDR_OUT;
-----
------crnt_start_address <= crnt_start_address_d2;
crnt_start_address <= crnt_start_address_i;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_vaddrreg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vaddrreg_mux.vhd
--
-- Description: This entity contains the mux for driving current video start
-- address to DMA Controller.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vaddrreg_mux is
generic(
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
C_ADDR_WIDTH : integer range 32 to 32 := 32
-- Start Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Current Frame Number --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Video Register Bank --
start_address_vid : in STARTADDR_ARRAY_TYPE --
(0 to C_NUM_FSTORES - 1) ; --
--
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vaddrreg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vaddrreg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal crnt_start_address_i : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d1 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d2 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal frame_number_index : integer := 0;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frame_number_index <= to_integer(unsigned(frame_number));
crnt_start_address_i <= start_address_vid(frame_number_index);
-- Pipe line for fmax (dble to allow for adjustments later if need be)
-----REG_ADDR_OUT : process(prmry_aclk)
----- begin
----- if(prmry_aclk'EVENT and prmry_aclk = '1')then
----- if(prmry_resetn = '0')then
----- crnt_start_address_d1 <= (others => '0');
----- crnt_start_address_d2 <= (others => '0');
----- else
----- crnt_start_address_d1 <= crnt_start_address_i;
----- crnt_start_address_d2 <= crnt_start_address_d1;
----- end if;
----- end if;
----- end process REG_ADDR_OUT;
-----
------crnt_start_address <= crnt_start_address_d2;
crnt_start_address <= crnt_start_address_i;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_vaddrreg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vaddrreg_mux.vhd
--
-- Description: This entity contains the mux for driving current video start
-- address to DMA Controller.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vaddrreg_mux is
generic(
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
C_ADDR_WIDTH : integer range 32 to 32 := 32
-- Start Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Current Frame Number --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Video Register Bank --
start_address_vid : in STARTADDR_ARRAY_TYPE --
(0 to C_NUM_FSTORES - 1) ; --
--
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vaddrreg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vaddrreg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal crnt_start_address_i : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d1 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
--signal crnt_start_address_d2 : std_logic_vector(C_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal frame_number_index : integer := 0;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frame_number_index <= to_integer(unsigned(frame_number));
crnt_start_address_i <= start_address_vid(frame_number_index);
-- Pipe line for fmax (dble to allow for adjustments later if need be)
-----REG_ADDR_OUT : process(prmry_aclk)
----- begin
----- if(prmry_aclk'EVENT and prmry_aclk = '1')then
----- if(prmry_resetn = '0')then
----- crnt_start_address_d1 <= (others => '0');
----- crnt_start_address_d2 <= (others => '0');
----- else
----- crnt_start_address_d1 <= crnt_start_address_i;
----- crnt_start_address_d2 <= crnt_start_address_d1;
----- end if;
----- end if;
----- end process REG_ADDR_OUT;
-----
------crnt_start_address <= crnt_start_address_d2;
crnt_start_address <= crnt_start_address_i;
end implementation;
|
----------------------------------------------------------------------------------
-- Create Date: 21:40:57 04/10/2017
-- Module Name: OR_BitABit - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OR_BitABit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0)); -- Saida
end OR_BitABit;
architecture Behavioral of OR_BitABit is
signal Zout : STD_LOGIC_VECTOR(3 downto 0);
begin
Zout(0) <= A(0) OR B(0);
Zout(1) <= A(1) OR B(1);
Zout(2) <= A(2) OR B(2);
Zout(3) <= A(3) OR B(3);
Z <= Zout;
end Behavioral;
|
-- ************************************
-- Automatically Generated FSM
-- sort_chan
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity vector_chan is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity vector_chan;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of vector_chan is
component infer_bram
generic
(
ADDRESS_BITS : integer := 32;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic_vector(0 to 3);
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic_vector(0 to 3);
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
idle,
get_en,
begin_sort,
for_loop,
halt,
extra1,
ALU,
write_back
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal swapped, swapped_next : std_logic;
signal i, i_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal n, n_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal n_new, n_new_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal e, e_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal dataA1, dataA1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataA2, dataA2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataB1, dataB1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataB2, dataB2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataC1, dataC1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataC2, dataC2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal in_Vector_A_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal in_Vector_B_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal in_Vector_C_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
Vector_A_addr0 <= in_Vector_A_addr0(2 to 31) & "00";
Vector_B_addr0 <= in_Vector_B_addr0(2 to 31) & "00";
Vector_C_addr0 <= in_Vector_C_addr0(2 to 31) & "00";
-- ************************
-- BRAM implementations
-- ************************
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
swapped_next,
i_next,
n_next,
n_new_next,
e_next,
dataA1_next,
dataA2_next,
dataB1_next,
dataB2_next,
dataC1_next,
dataC2_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
swapped <= '0';
i <= (others => '0');
n <= (others => '0');
n_new <= (others => '0');
e <= (others => '0');
dataA1 <= (others => '0');
dataA2 <= (others => '0');
dataB1 <= (others => '0');
dataB2 <= (others => '0');
dataC1 <= (others => '0');
dataC2 <= (others => '0');
current_state <= reset;
else
-- Transition to next state
swapped <= swapped_next;
i <= i_next;
n <= n_next;
n_new <= n_new_next;
e <= e_next;
dataA1 <= dataA1_next;
dataA2 <= dataA2_next;
dataB1 <= dataB1_next;
dataB2 <= dataB2_next;
dataC1 <= dataC1_next;
dataC2 <= dataC2_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
Vector_A_dOUT0,
Vector_B_dOUT0,
Vector_C_dOUT0,
chan1_channelDataOut, chan1_full, chan1_exists,
swapped,
i,
n,
n_new,
e,
dataA1,
dataA2,
dataB1,
dataB2,
dataC1,
dataC2,
current_state) is
begin
-- Default signal assignments
swapped_next <= swapped;
i_next <= i;
n_next <= n;
n_new_next <= n_new;
e_next <= e;
dataA1_next <= dataA1;
dataA2_next <= dataA2;
dataB1_next <= dataB1;
dataB2_next <= dataB2;
dataC1_next <= dataC1;
dataC2_next <= dataC2;
in_Vector_A_addr0 <= (others => '0');
Vector_A_dIN0 <= (others => '0');
Vector_A_rENA0 <= '0';
Vector_A_wENA0 <= (others => '0');
in_Vector_B_addr0 <= (others => '0');
Vector_B_dIN0 <= (others => '0');
Vector_B_rENA0 <= '0';
Vector_B_wENA0 <= (others => '0');
in_Vector_C_addr0 <= (others => '0');
Vector_C_dIN0 <= (others => '0');
Vector_C_rENA0 <= '0';
Vector_C_wENA0 <= (others => '0');
chan1_channelDataIn <= (others => '0');
chan1_channelRead <= '0';
chan1_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when ALU =>
dataC1_next <= dataA1 + dataB1;
next_state <= write_back;
when begin_sort =>
i_next <= e;
next_state <= for_loop;
when extra1 =>
dataB1_next <= Vector_B_dOUT0;
dataA1_next <= Vector_A_dOUT0;
next_state <= ALU;
when for_loop =>
if ( i >= n ) then
next_state <= halt;
elsif ( i < n ) then
in_Vector_A_addr0 <= i;
Vector_A_rENA0 <= '1';
in_Vector_B_addr0 <= i;
Vector_B_rENA0 <= '1';
next_state <= extra1;
end if;
when get_en =>
if chan1_exists = '0' then
next_state <= get_en;
elsif chan1_exists /= '0' then
e_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= begin_sort;
end if;
when halt =>
if chan1_full /= '0' then
next_state <= halt;
elsif chan1_full = '0' then
chan1_channelDataIn <= (others => '0');
chan1_channelWrite <= '1';
next_state <= idle;
end if;
when idle =>
if chan1_exists = '0' then
next_state <= idle;
elsif chan1_exists /= '0' then
n_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= get_en;
end if;
when reset =>
next_state <= idle;
when write_back =>
i_next <= i + 1;
in_Vector_C_addr0 <= i;
Vector_C_dIN0 <= dataC1;
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
next_state <= for_loop;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 32;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic_vector(0 to 3);
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic_vector(0 to 3);
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 8; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
SIGNAL BRAM_DATA : bram_storage:= ( X"00000002",X"00000008",X"00000003",X"00000005", others => (others =>'0'));
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = "1111" ) then
BRAM_DATA( conv_integer(ADDRB) ) <= DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
-- ************************************
-- Automatically Generated FSM
-- sort_chan
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity vector_chan is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity vector_chan;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of vector_chan is
component infer_bram
generic
(
ADDRESS_BITS : integer := 32;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic_vector(0 to 3);
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic_vector(0 to 3);
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
idle,
get_en,
begin_sort,
for_loop,
halt,
extra1,
ALU,
write_back
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal swapped, swapped_next : std_logic;
signal i, i_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal n, n_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal n_new, n_new_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal e, e_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal dataA1, dataA1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataA2, dataA2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataB1, dataB1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataB2, dataB2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataC1, dataC1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataC2, dataC2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal in_Vector_A_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal in_Vector_B_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal in_Vector_C_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
Vector_A_addr0 <= in_Vector_A_addr0(2 to 31) & "00";
Vector_B_addr0 <= in_Vector_B_addr0(2 to 31) & "00";
Vector_C_addr0 <= in_Vector_C_addr0(2 to 31) & "00";
-- ************************
-- BRAM implementations
-- ************************
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
swapped_next,
i_next,
n_next,
n_new_next,
e_next,
dataA1_next,
dataA2_next,
dataB1_next,
dataB2_next,
dataC1_next,
dataC2_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
swapped <= '0';
i <= (others => '0');
n <= (others => '0');
n_new <= (others => '0');
e <= (others => '0');
dataA1 <= (others => '0');
dataA2 <= (others => '0');
dataB1 <= (others => '0');
dataB2 <= (others => '0');
dataC1 <= (others => '0');
dataC2 <= (others => '0');
current_state <= reset;
else
-- Transition to next state
swapped <= swapped_next;
i <= i_next;
n <= n_next;
n_new <= n_new_next;
e <= e_next;
dataA1 <= dataA1_next;
dataA2 <= dataA2_next;
dataB1 <= dataB1_next;
dataB2 <= dataB2_next;
dataC1 <= dataC1_next;
dataC2 <= dataC2_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
Vector_A_dOUT0,
Vector_B_dOUT0,
Vector_C_dOUT0,
chan1_channelDataOut, chan1_full, chan1_exists,
swapped,
i,
n,
n_new,
e,
dataA1,
dataA2,
dataB1,
dataB2,
dataC1,
dataC2,
current_state) is
begin
-- Default signal assignments
swapped_next <= swapped;
i_next <= i;
n_next <= n;
n_new_next <= n_new;
e_next <= e;
dataA1_next <= dataA1;
dataA2_next <= dataA2;
dataB1_next <= dataB1;
dataB2_next <= dataB2;
dataC1_next <= dataC1;
dataC2_next <= dataC2;
in_Vector_A_addr0 <= (others => '0');
Vector_A_dIN0 <= (others => '0');
Vector_A_rENA0 <= '0';
Vector_A_wENA0 <= (others => '0');
in_Vector_B_addr0 <= (others => '0');
Vector_B_dIN0 <= (others => '0');
Vector_B_rENA0 <= '0';
Vector_B_wENA0 <= (others => '0');
in_Vector_C_addr0 <= (others => '0');
Vector_C_dIN0 <= (others => '0');
Vector_C_rENA0 <= '0';
Vector_C_wENA0 <= (others => '0');
chan1_channelDataIn <= (others => '0');
chan1_channelRead <= '0';
chan1_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when ALU =>
dataC1_next <= dataA1 + dataB1;
next_state <= write_back;
when begin_sort =>
i_next <= e;
next_state <= for_loop;
when extra1 =>
dataB1_next <= Vector_B_dOUT0;
dataA1_next <= Vector_A_dOUT0;
next_state <= ALU;
when for_loop =>
if ( i >= n ) then
next_state <= halt;
elsif ( i < n ) then
in_Vector_A_addr0 <= i;
Vector_A_rENA0 <= '1';
in_Vector_B_addr0 <= i;
Vector_B_rENA0 <= '1';
next_state <= extra1;
end if;
when get_en =>
if chan1_exists = '0' then
next_state <= get_en;
elsif chan1_exists /= '0' then
e_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= begin_sort;
end if;
when halt =>
if chan1_full /= '0' then
next_state <= halt;
elsif chan1_full = '0' then
chan1_channelDataIn <= (others => '0');
chan1_channelWrite <= '1';
next_state <= idle;
end if;
when idle =>
if chan1_exists = '0' then
next_state <= idle;
elsif chan1_exists /= '0' then
n_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= get_en;
end if;
when reset =>
next_state <= idle;
when write_back =>
i_next <= i + 1;
in_Vector_C_addr0 <= i;
Vector_C_dIN0 <= dataC1;
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
next_state <= for_loop;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 32;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic_vector(0 to 3);
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic_vector(0 to 3);
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 8; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
SIGNAL BRAM_DATA : bram_storage:= ( X"00000002",X"00000008",X"00000003",X"00000005", others => (others =>'0'));
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = "1111" ) then
BRAM_DATA( conv_integer(ADDRB) ) <= DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_UNSIGNED.ALL;
use IEEE.std_logic_ARITH.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
package IDROMParms is
constant NullAddr : std_logic_vector(7 downto 0) := x"00";
constant ReadIDAddr : std_logic_vector(7 downto 0) := x"01";
constant LEDAddr : std_logic_vector(7 downto 0) := x"02";
constant LEDNumRegs : std_logic_vector(7 downto 0) := x"01";
constant LEDMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
constant IDROMAddr : std_logic_vector(7 downto 0) := x"04";
constant Cookie : std_logic_vector(31 downto 0) := x"55AACAFE";
constant HostMotNameLow : std_logic_vector(31 downto 0) := x"54534F48"; -- HOST
constant HostMotNameHigh : std_logic_vector(31 downto 0) := x"32544F4D"; -- MOT2
constant BoardNameMesa : std_logic_vector(31 downto 0) := x"4153454D"; -- MESA
constant BoardName4I65 : std_logic_vector(31 downto 0) := x"35364934"; -- 4I65
constant BoardName4I68 : std_logic_vector(31 downto 0) := x"38364934"; -- 4I68
constant BoardName5I20 : std_logic_vector(31 downto 0) := x"30324935"; -- 5I20
constant BoardName5I22 : std_logic_vector(31 downto 0) := x"32324935"; -- 5I22
constant BoardName5I23 : std_logic_vector(31 downto 0) := x"33324935"; -- 5I23
constant BoardName7I43 : std_logic_vector(31 downto 0) := x"33344937"; -- 7I43
constant BoardName7I60 : std_logic_vector(31 downto 0) := x"30364937"; -- 7I60
constant IDROMOffset : std_logic_vector(31 downto 0) := x"0000"&IDROMAddr&x"00"; -- note need to change if pitch changed
constant IDROMWEnAddr : std_logic_vector(7 downto 0) := x"08";
constant IRQDivAddr : std_logic_vector(7 downto 0) := x"09";
constant IRQStatusAddr : std_logic_vector(7 downto 0) := x"0A";
constant ClearIRQAddr : std_logic_vector(7 downto 0) := x"0B";
constant IRQNumRegs : std_logic_vector(7 downto 0) := x"03";
constant IRQMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
constant WatchdogTimeAddr : std_logic_vector(7 downto 0) := x"0C";
constant WatchDogStatusAddr : std_logic_vector(7 downto 0) := x"0D";
constant WatchDogCookieAddr : std_logic_vector(7 downto 0) := x"0E";
constant WatchDogNumRegs : std_logic_vector(7 downto 0) := x"03";
constant WatchDogMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
constant PortAddr : std_logic_vector(7 downto 0) := x"10";
constant DDRAddr : std_logic_vector(7 downto 0) := x"11";
constant AltDataSrcAddr : std_logic_vector(7 downto 0) := x"12";
constant OpenDrainModeAddr : std_logic_vector(7 downto 0) := x"13";
constant OutputInvAddr : std_logic_vector(7 downto 0) := x"14";
constant IOPortNumRegs : std_logic_vector(7 downto 0) := x"05";
constant IOPortMPBitMask : std_logic_vector(31 downto 0) := x"0000001F";
constant StepGenRateAddr : std_logic_vector(7 downto 0) := x"20";
constant StepGenAccumAddr : std_logic_vector(7 downto 0) := x"21";
constant StepGenModeAddr : std_logic_vector(7 downto 0) := x"22";
constant StepGenDSUTimeAddr : std_logic_vector(7 downto 0) := x"23";
constant StepGenDHLDTimeAddr : std_logic_vector(7 downto 0) := x"24";
constant StepGenPulseATimeAddr : std_logic_vector(7 downto 0) := x"25";
constant StepGenPulseITimeAddr : std_logic_vector(7 downto 0) := x"26";
constant StepGenTableAddr : std_logic_vector(7 downto 0) := x"27";
constant StepGenTableMaxAddr : std_logic_vector(7 downto 0) := x"28";
constant StepGenBasicRateAddr : std_logic_vector(7 downto 0) := x"29";
constant StepGenNumRegs : std_logic_vector(7 downto 0) := x"0A";
constant StepGenMPBitMask : std_logic_vector(31 downto 0) := x"000001FF";
constant QCounterAddr : std_logic_vector(7 downto 0) := x"30";
constant QCounterCCRAddr : std_logic_vector(7 downto 0) := x"31";
constant TSDivAddr : std_logic_vector(7 downto 0) := x"32";
constant TSAddr : std_logic_vector(7 downto 0) := x"33";
constant QCRateAddr : std_logic_vector(7 downto 0) := x"34";
constant QCounterNumRegs : std_logic_vector(7 downto 0) := x"05";
constant QCounterMPBitMask : std_logic_vector(31 downto 0) := x"00000003";
constant MuxedQCounterAddr : std_logic_vector(7 downto 0) := x"35";
constant MuxedQCounterCCRAddr : std_logic_vector(7 downto 0) := x"36";
constant MuxedTSDivAddr : std_logic_vector(7 downto 0) := x"37";
constant MuxedTSAddr : std_logic_vector(7 downto 0) := x"38";
constant MuxedQCRateAddr : std_logic_vector(7 downto 0) := x"39";
constant MuxedQCounterNumRegs : std_logic_vector(7 downto 0) := x"05";
constant MuxedQCounterMPBitMask : std_logic_vector(31 downto 0) := x"00000003";
constant PWMValAddr : std_logic_vector(7 downto 0) := x"40";
constant PWMCRAddr : std_logic_vector(7 downto 0) := x"41";
constant PWMRateAddr : std_logic_vector(7 downto 0) := x"42";
constant PDMRateAddr : std_logic_vector(7 downto 0) := x"43";
constant PWMEnasAddr : std_logic_vector(7 downto 0) := x"44";
constant PWMNumRegs : std_logic_vector(7 downto 0) := x"05";
constant PWMMPBitMask : std_logic_vector(31 downto 0) := x"00000003";
constant SPIDataAddr : std_logic_vector(7 downto 0) := x"50";
constant SPIBitCountAddr : std_logic_vector(7 downto 0) := x"51";
constant SPIBitrateAddr : std_logic_vector(7 downto 0) := x"52";
constant SPINumRegs : std_logic_vector(7 downto 0) := x"03";
constant SPIMPBitMask : std_logic_vector(31 downto 0) := x"00000007";
constant BSPIDataAddr : std_logic_vector(7 downto 0) := x"54";
constant BSPIDescriptorAddr : std_logic_vector(7 downto 0) := x"55";
constant BSPIFIFOCountAddr : std_logic_vector(7 downto 0) := x"56";
constant BSPINumRegs : std_logic_vector(7 downto 0) := x"03";
constant BSPIMPBitMask : std_logic_vector(31 downto 0) := x"00000007";
constant UARTTDataAddr : std_logic_vector(7 downto 0) := x"60";
constant UARTTFIFOCountAddr : std_logic_vector(7 downto 0) := x"61";
constant UARTTBitrateAddr: std_logic_vector(7 downto 0) := x"62";
constant UARTTModeRegAddr : std_logic_vector(7 downto 0) := x"63";
constant UARTTNumRegs : std_logic_vector(7 downto 0) := x"04";
constant UARTTMPBitMask : std_logic_vector(31 downto 0) := x"0000000F";
constant UARTRDataAddr : std_logic_vector(7 downto 0) := x"70";
constant UARTRFIFOCountAddr : std_logic_vector(7 downto 0) := x"71";
constant UARTRBitrateAddr : std_logic_vector(7 downto 0) := x"72";
constant UARTRModeRegAddr : std_logic_vector(7 downto 0) := x"73";
constant UARTRNumRegs : std_logic_vector(7 downto 0) := x"04";
constant UARTRMPBitMask : std_logic_vector(31 downto 0) := x"0000000F";
constant TranslateRamAddr : std_logic_vector(7 downto 0) := x"78";
constant TranslateRegionAddr : std_logic_vector(7 downto 0) := x"7C";
constant TranslateNumRegs : std_logic_vector(7 downto 0) := x"04";
constant TranslateMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
constant ClockLow20: integer := 33333333; -- 5I20/4I65 low speed clock
constant ClockLow22: integer := 48000000; -- 5I22/5I23 low speed clock
constant ClockLow43: integer := 50000000; -- 7I43 low speed clock
constant ClockLow43U: integer := 33333333; -- 7I43U low speed clock
constant ClockLow68: integer := 48000000; -- 4I68 low speed clock
constant ClockHigh20: integer := 100000000; -- 5I20/4I65 high speed clock
constant ClockHigh22: integer := 96000000; -- 5I22/5I23 high speed clock
constant ClockHigh43: integer := 100000000; -- 7I43 high speed clock
constant ClockHigh43U: integer := 100000000; -- 7I43U high speed clock
constant ClockHigh68: integer := 96000000; -- 4I68 high speed clock
constant ClockLowTag: std_logic_vector(7 downto 0) := x"01";
constant ClockHighTag: std_logic_vector(7 downto 0) := x"02";
constant NullTag : std_logic_vector(7 downto 0) := x"00";
constant NullPin : std_logic_vector(7 downto 0) := x"00";
constant IRQLogicTag : std_logic_vector(7 downto 0) := x"01";
constant WatchDogTag : std_logic_vector(7 downto 0) := x"02";
constant IOPortTag : std_logic_vector(7 downto 0) := x"03";
constant QCountTag : std_logic_vector(7 downto 0) := x"04";
constant QCountQAPin : std_logic_vector(7 downto 0) := x"01";
constant QCountQBPin : std_logic_vector(7 downto 0) := x"02";
constant QCountIdxPin : std_logic_vector(7 downto 0) := x"03";
constant QCountIdxMaskPin : std_logic_vector(7 downto 0) := x"04";
constant StepGenTag : std_logic_vector(7 downto 0) := x"05";
constant StepGenStepPin : std_logic_vector(7 downto 0) := x"81";
constant StepGenDirPin : std_logic_vector(7 downto 0) := x"82";
constant StepGenTable2Pin : std_logic_vector(7 downto 0) := x"83";
constant StepGenTable3Pin : std_logic_vector(7 downto 0) := x"84";
constant StepGenTable4Pin : std_logic_vector(7 downto 0) := x"85";
constant StepGenTable5Pin : std_logic_vector(7 downto 0) := x"86";
constant StepGenTable6Pin : std_logic_vector(7 downto 0) := x"87";
constant StepGenTable7Pin : std_logic_vector(7 downto 0) := x"88";
constant PWMTag : std_logic_vector(7 downto 0) := x"06";
constant PWMAOutPin : std_logic_vector(7 downto 0) := x"81";
constant PWMBDirPin : std_logic_vector(7 downto 0) := x"82";
constant PWMCEnaPin : std_logic_vector(7 downto 0) := x"83";
constant SPITag : std_logic_vector(7 downto 0) := x"07";
constant SPIFramePin : std_logic_vector(7 downto 0) := x"81";
constant SPIOutPin : std_logic_vector(7 downto 0) := x"82";
constant SPIClkPin : std_logic_vector(7 downto 0) := x"83";
constant SPIInPin : std_logic_vector(7 downto 0) := x"04";
constant SSITag : std_logic_vector(7 downto 0) := x"08";
constant UARTTTag : std_logic_vector(7 downto 0) := x"09";
constant UTDataPin : std_logic_vector(7 downto 0) := x"81";
constant UTDrvEnPin : std_logic_vector(7 downto 0) := x"82";
constant UARTRTag : std_logic_vector(7 downto 0) := x"0A";
constant URDataPin : std_logic_vector(7 downto 0) := x"01";
constant AddrXTag : std_logic_vector(7 downto 0) := x"0B";
constant MuxedQCountTag: std_logic_vector(7 downto 0) := x"0C";
constant MuxedQCountQAPin : std_logic_vector(7 downto 0) := x"01";
constant MuxedQCountQBPin : std_logic_vector(7 downto 0) := x"02";
constant MuxedQCountIdxPin : std_logic_vector(7 downto 0) := x"03";
constant MuxedQCountIdxMaskPin : std_logic_vector(7 downto 0) := x"04";
constant MuxedQCountSelTag: std_logic_vector(7 downto 0) := x"0D";
constant MuxedQCountSel0Pin : std_logic_vector(7 downto 0) := x"81";
constant MuxedQCountSel1Pin : std_logic_vector(7 downto 0) := x"82";
constant BSPITag : std_logic_vector(7 downto 0) := x"0E";
constant BSPIFramePin : std_logic_vector(7 downto 0) := x"81";
constant BSPIOutPin : std_logic_vector(7 downto 0) := x"82";
constant BSPIClkPin : std_logic_vector(7 downto 0) := x"83";
constant BSPIInPin : std_logic_vector(7 downto 0) := x"04";
constant BSPICS0Pin : std_logic_vector(7 downto 0) := x"85";
constant BSPICS1Pin : std_logic_vector(7 downto 0) := x"86";
constant BSPICS2Pin : std_logic_vector(7 downto 0) := x"87";
constant BSPICS3Pin : std_logic_vector(7 downto 0) := x"88";
constant BSPICS4Pin : std_logic_vector(7 downto 0) := x"89";
constant BSPICS5Pin : std_logic_vector(7 downto 0) := x"8A";
constant BSPICS6Pin : std_logic_vector(7 downto 0) := x"8B";
constant BSPICS7Pin : std_logic_vector(7 downto 0) := x"8C";
constant LEDTag : std_logic_vector(7 downto 0) := x"80";
constant emptypin : std_logic_vector(31 downto 0) := x"00000000";
constant empty : std_logic_vector(31 downto 0) := x"00000000";
constant PadT : std_logic_vector(7 downto 0) := x"00";
constant MaxModules : integer := 32; -- maximum number of module types
constant MaxPins : integer := 128; -- maximum number of I/O pins (may change to 144 with 3X20)
-- would be better to change all the pindescs to records
-- but that requires reversing the byte order of the constant
-- pindesc arrays, some other day...
type PinDescRecord is -- not used yet!
record
SecPin : std_logic_vector(7 downto 0);
SecFunc : std_logic_vector(7 downto 0);
SecInst : std_logic_vector(7 downto 0);
PriFunc : std_logic_vector(7 downto 0);
end record;
type PinDescType is array(0 to MaxPins -1) of std_logic_vector(31 downto 0);
type ModuleRecord is
record
GTag : std_logic_vector(7 downto 0);
Version : std_logic_vector(7 downto 0);
Clock : std_logic_vector(7 downto 0);
NumInstances : std_logic_vector(7 downto 0);
BaseAddr : std_logic_vector(15 downto 0);
NumRegisters : std_logic_vector(7 downto 0);
Strides : std_logic_vector(7 downto 0);
MultRegs : std_logic_vector(31 downto 0);
end record;
type ModuleIDType is array(0 to MaxModules-1) of ModuleRecord;
-- These messy constants must remain until I make a script
-- to generate them based on configuration parameters
-------------------------------------------------------------------------------------------------
-- first 2 connector pinouts (7I43)
-------------------------------------------------------------------------------------------------
constant ModuleID_SV8 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(AddrXTag, x"00", ClockLowTag, x"01", TranslateRAMAddr&PadT, TranslateNumRegs, x"00", TranslateMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SV8 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_4 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"04", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(AddrXTag, x"00", ClockLowTag, x"01", TranslateRAMAddr&PadT, TranslateNumRegs, x"00", TranslateMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_4 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_6 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(AddrXTag, x"00", ClockLowTag, x"01", TranslateRAMAddr&PadT, TranslateNumRegs, x"00", TranslateMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_6 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"83",
IOPortTag & x"04" & StepGenTag & x"84",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"83",
IOPortTag & x"05" & StepGenTag & x"84",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_12 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(AddrXTag, x"00", ClockLowTag, x"01", TranslateRAMAddr&PadT, TranslateNumRegs, x"00", TranslateMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_12 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"08" & StepGenTag & x"81",
IOPortTag & x"08" & StepGenTag & x"82",
IOPortTag & x"09" & StepGenTag & x"81",
IOPortTag & x"09" & StepGenTag & x"82",
IOPortTag & x"0A" & StepGenTag & x"81",
IOPortTag & x"0A" & StepGenTag & x"82",
IOPortTag & x"0B" & StepGenTag & x"81",
IOPortTag & x"0B" & StepGenTag & x"82",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
-------------------------------------------------------------------------------------------------
-- 7I43 USB configurations with no TRAM
-------------------------------------------------------------------------------------------------
constant ModuleID_SV8NA : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SV8NA : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_4NA : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"04", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_4NA : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_6NA : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_6NA : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"83",
IOPortTag & x"04" & StepGenTag & x"84",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"83",
IOPortTag & x"05" & StepGenTag & x"84",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_12NA : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_12NA : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"08" & StepGenTag & x"81",
IOPortTag & x"08" & StepGenTag & x"82",
IOPortTag & x"09" & StepGenTag & x"81",
IOPortTag & x"09" & StepGenTag & x"82",
IOPortTag & x"0A" & StepGenTag & x"81",
IOPortTag & x"0A" & StepGenTag & x"82",
IOPortTag & x"0B" & StepGenTag & x"81",
IOPortTag & x"0B" & StepGenTag & x"82",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
-------------------------------------------------------------------------------------------------
-- 3 connector pinouts (4I65,5I20,4I68,5I23)
-------------------------------------------------------------------------------------------------
constant ModuleID_3xi30 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"0C", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"0C", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_3xi30 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"09" & QCountTag & x"02",
IOPortTag & x"09" & QCountTag & x"01",
IOPortTag & x"08" & QCountTag & x"02",
IOPortTag & x"08" & QCountTag & x"01",
IOPortTag & x"09" & QCountTag & x"03",
IOPortTag & x"08" & QCountTag & x"03",
IOPortTag & x"09" & PWMTag & x"81",
IOPortTag & x"08" & PWMTag & x"81",
IOPortTag & x"09" & PWMTag & x"82",
IOPortTag & x"08" & PWMTag & x"82",
IOPortTag & x"09" & PWMTag & x"83",
IOPortTag & x"08" & PWMTag & x"83",
IOPortTag & x"0B" & QCountTag & x"02",
IOPortTag & x"0B" & QCountTag & x"01",
IOPortTag & x"0A" & QCountTag & x"02",
IOPortTag & x"0A" & QCountTag & x"01",
IOPortTag & x"0B" & QCountTag & x"03",
IOPortTag & x"0A" & QCountTag & x"03",
IOPortTag & x"0B" & PWMTag & x"81",
IOPortTag & x"0A" & PWMTag & x"81",
IOPortTag & x"0B" & PWMTag & x"82",
IOPortTag & x"0A" & PWMTag & x"82",
IOPortTag & x"0B" & PWMTag & x"83",
IOPortTag & x"0A" & PWMTag & x"83",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST8_4 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"04", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST8_4 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_24xQCtrOnly : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"10", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_24xQCtrOnly : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"08" & QCountTag & x"01",
IOPortTag & x"08" & QCountTag & x"02",
IOPortTag & x"08" & QCountTag & x"03",
IOPortTag & x"09" & QCountTag & x"01",
IOPortTag & x"09" & QCountTag & x"02",
IOPortTag & x"09" & QCountTag & x"03",
IOPortTag & x"0A" & QCountTag & x"01",
IOPortTag & x"0A" & QCountTag & x"02",
IOPortTag & x"0A" & QCountTag & x"03",
IOPortTag & x"0B" & QCountTag & x"01",
IOPortTag & x"0B" & QCountTag & x"02",
IOPortTag & x"0B" & QCountTag & x"03",
IOPortTag & x"0C" & QCountTag & x"01",
IOPortTag & x"0C" & QCountTag & x"02",
IOPortTag & x"0C" & QCountTag & x"03",
IOPortTag & x"0D" & QCountTag & x"01",
IOPortTag & x"0D" & QCountTag & x"02",
IOPortTag & x"0D" & QCountTag & x"03",
IOPortTag & x"0E" & QCountTag & x"01",
IOPortTag & x"0E" & QCountTag & x"02",
IOPortTag & x"0E" & QCountTag & x"03",
IOPortTag & x"0F" & QCountTag & x"01",
IOPortTag & x"0F" & QCountTag & x"02",
IOPortTag & x"0F" & QCountTag & x"03",
IOPortTag & x"10" & QCountTag & x"01",
IOPortTag & x"10" & QCountTag & x"02",
IOPortTag & x"10" & QCountTag & x"03",
IOPortTag & x"11" & QCountTag & x"01",
IOPortTag & x"11" & QCountTag & x"02",
IOPortTag & x"11" & QCountTag & x"03",
IOPortTag & x"12" & QCountTag & x"01",
IOPortTag & x"12" & QCountTag & x"02",
IOPortTag & x"12" & QCountTag & x"03",
IOPortTag & x"13" & QCountTag & x"01",
IOPortTag & x"13" & QCountTag & x"02",
IOPortTag & x"13" & QCountTag & x"03",
IOPortTag & x"14" & QCountTag & x"01",
IOPortTag & x"14" & QCountTag & x"02",
IOPortTag & x"14" & QCountTag & x"03",
IOPortTag & x"15" & QCountTag & x"01",
IOPortTag & x"15" & QCountTag & x"02",
IOPortTag & x"15" & QCountTag & x"03",
IOPortTag & x"16" & QCountTag & x"01",
IOPortTag & x"16" & QCountTag & x"02",
IOPortTag & x"16" & QCountTag & x"03",
IOPortTag & x"17" & QCountTag & x"01",
IOPortTag & x"17" & QCountTag & x"02",
IOPortTag & x"17" & QCountTag & x"03",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST4_8 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"04", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST4_8 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"83",
IOPortTag & x"04" & StepGenTag & x"84",
IOPortTag & x"04" & StepGenTag & x"85",
IOPortTag & x"04" & StepGenTag & x"86",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"83",
IOPortTag & x"05" & StepGenTag & x"84",
IOPortTag & x"05" & StepGenTag & x"85",
IOPortTag & x"05" & StepGenTag & x"86",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"83",
IOPortTag & x"06" & StepGenTag & x"84",
IOPortTag & x"06" & StepGenTag & x"85",
IOPortTag & x"06" & StepGenTag & x"86",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"83",
IOPortTag & x"07" & StepGenTag & x"84",
IOPortTag & x"07" & StepGenTag & x"85",
IOPortTag & x"07" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST2_8 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"02", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST2_8 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & NullTag & x"00",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"83",
IOPortTag & x"04" & StepGenTag & x"84",
IOPortTag & x"04" & StepGenTag & x"85",
IOPortTag & x"04" & StepGenTag & x"86",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"83",
IOPortTag & x"05" & StepGenTag & x"84",
IOPortTag & x"05" & StepGenTag & x"85",
IOPortTag & x"05" & StepGenTag & x"86",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"83",
IOPortTag & x"06" & StepGenTag & x"84",
IOPortTag & x"06" & StepGenTag & x"85",
IOPortTag & x"06" & StepGenTag & x"86",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"83",
IOPortTag & x"07" & StepGenTag & x"84",
IOPortTag & x"07" & StepGenTag & x"85",
IOPortTag & x"07" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_ST12 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_ST12 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"83",
IOPortTag & x"04" & StepGenTag & x"84",
IOPortTag & x"04" & StepGenTag & x"85",
IOPortTag & x"04" & StepGenTag & x"86",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"83",
IOPortTag & x"05" & StepGenTag & x"84",
IOPortTag & x"05" & StepGenTag & x"85",
IOPortTag & x"05" & StepGenTag & x"86",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"83",
IOPortTag & x"06" & StepGenTag & x"84",
IOPortTag & x"06" & StepGenTag & x"85",
IOPortTag & x"06" & StepGenTag & x"86",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"83",
IOPortTag & x"07" & StepGenTag & x"84",
IOPortTag & x"07" & StepGenTag & x"85",
IOPortTag & x"07" & StepGenTag & x"86",
IOPortTag & x"08" & StepGenTag & x"81",
IOPortTag & x"08" & StepGenTag & x"82",
IOPortTag & x"08" & StepGenTag & x"83",
IOPortTag & x"08" & StepGenTag & x"84",
IOPortTag & x"08" & StepGenTag & x"85",
IOPortTag & x"08" & StepGenTag & x"86",
IOPortTag & x"09" & StepGenTag & x"81",
IOPortTag & x"09" & StepGenTag & x"82",
IOPortTag & x"09" & StepGenTag & x"83",
IOPortTag & x"09" & StepGenTag & x"84",
IOPortTag & x"09" & StepGenTag & x"85",
IOPortTag & x"09" & StepGenTag & x"86",
IOPortTag & x"0A" & StepGenTag & x"81",
IOPortTag & x"0A" & StepGenTag & x"82",
IOPortTag & x"0A" & StepGenTag & x"83",
IOPortTag & x"0A" & StepGenTag & x"84",
IOPortTag & x"0A" & StepGenTag & x"85",
IOPortTag & x"0A" & StepGenTag & x"86",
IOPortTag & x"0B" & StepGenTag & x"81",
IOPortTag & x"0B" & StepGenTag & x"82",
IOPortTag & x"0B" & StepGenTag & x"83",
IOPortTag & x"0B" & StepGenTag & x"84",
IOPortTag & x"0B" & StepGenTag & x"85",
IOPortTag & x"0B" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_DelftSV12 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"0C", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"0C", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_DelftSV12 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"08" & QCountTag & x"01",
IOPortTag & x"08" & QCountTag & x"02",
IOPortTag & x"08" & QCountTag & x"03",
IOPortTag & x"09" & QCountTag & x"01",
IOPortTag & x"09" & QCountTag & x"02",
IOPortTag & x"09" & QCountTag & x"03",
IOPortTag & x"0A" & QCountTag & x"01",
IOPortTag & x"0A" & QCountTag & x"02",
IOPortTag & x"0A" & QCountTag & x"03",
IOPortTag & x"0B" & QCountTag & x"01",
IOPortTag & x"0B" & QCountTag & x"02",
IOPortTag & x"0B" & QCountTag & x"03",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"08" & PWMTag & x"81",
IOPortTag & x"08" & PWMTag & x"82",
IOPortTag & x"08" & PWMTag & x"83",
IOPortTag & x"09" & PWMTag & x"81",
IOPortTag & x"09" & PWMTag & x"82",
IOPortTag & x"09" & PWMTag & x"83",
IOPortTag & x"0A" & PWMTag & x"81",
IOPortTag & x"0A" & PWMTag & x"82",
IOPortTag & x"0A" & PWMTag & x"83",
IOPortTag & x"0B" & PWMTag & x"81",
IOPortTag & x"0B" & PWMTag & x"82",
IOPortTag & x"0B" & PWMTag & x"83",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_MShaver : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"03", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"01", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"00", ClockLowTag, x"03", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_MShaver : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 00
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 02
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 04
IOPortTag & x"00" & NullTag & x"00", -- I/O 05
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 06
IOPortTag & x"00" & NullTag & x"00", -- I/O 07
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 08
IOPortTag & x"00" & NullTag & x"00", -- I/O 09
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 10
IOPortTag & x"00" & NullTag & x"00", -- I/O 11
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 12
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 13
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 14
IOPortTag & x"00" & NullTag & x"00", -- I/O 15
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 16
IOPortTag & x"00" & NullTag & x"00", -- I/O 17
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 18
IOPortTag & x"00" & NullTag & x"00", -- I/O 19
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 20
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
IOPortTag & x"00" & NullTag & x"00", -- I/O 24
IOPortTag & x"00" & NullTag & x"00", -- I/O 25
IOPortTag & x"00" & NullTag & x"00", -- I/O 26
IOPortTag & x"00" & NullTag & x"00", -- I/O 27
IOPortTag & x"00" & NullTag & x"00", -- I/O 28
IOPortTag & x"00" & NullTag & x"00", -- I/O 29
IOPortTag & x"00" & NullTag & x"00", -- I/O 30
IOPortTag & x"00" & NullTag & x"00", -- I/O 31
IOPortTag & x"00" & NullTag & x"00", -- I/O 32
IOPortTag & x"00" & NullTag & x"00", -- I/O 33
IOPortTag & x"00" & NullTag & x"00", -- I/O 34
IOPortTag & x"00" & NullTag & x"00", -- I/O 35
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
IOPortTag & x"00" & NullTag & x"00", -- I/O 37
IOPortTag & x"00" & NullTag & x"00", -- I/O 38
IOPortTag & x"00" & NullTag & x"00", -- I/O 39
IOPortTag & x"00" & NullTag & x"00", -- I/O 40
IOPortTag & x"00" & NullTag & x"00", -- I/O 41
IOPortTag & x"00" & NullTag & x"00", -- I/O 42
IOPortTag & x"00" & NullTag & x"00", -- I/O 43
IOPortTag & x"00" & NullTag & x"00", -- I/O 44
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
IOPortTag & x"00" & NullTag & x"00", -- I/O 48
IOPortTag & x"00" & NullTag & x"00", -- I/O 49
IOPortTag & x"00" & NullTag & x"00", -- I/O 50
IOPortTag & x"00" & NullTag & x"00", -- I/O 51
IOPortTag & x"00" & NullTag & x"00", -- I/O 52
IOPortTag & x"00" & NullTag & x"00", -- I/O 53
IOPortTag & x"00" & NullTag & x"00", -- I/O 54
IOPortTag & x"00" & NullTag & x"00", -- I/O 55
IOPortTag & x"00" & NullTag & x"00", -- I/O 56
IOPortTag & x"00" & NullTag & x"00", -- I/O 57
IOPortTag & x"00" & NullTag & x"00", -- I/O 58
IOPortTag & x"00" & NullTag & x"00", -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_72Pin_2x7I65 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(MuxedQcountTag, x"02", ClockLowTag, x"10", QcounterAddr&PadT, MuxedQCounterNumRegs, x"00", MuxedQCounterMPBitMask),
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
(BSPITag, x"00", ClockLowTag, x"02", BSPIDataAddr&PadT, BSPINumRegs, x"00", BSPIMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_72Pin_2x7I65 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 00
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 01
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 02
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 03
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 04
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 05
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 06
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 07
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 08
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 09
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 10
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 11
IOPortTag & x"00" & NullTag & x"00", -- I/O 12
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
IOPortTag & x"00" & BSPITag & BSPIFramePin, -- I/O 14
IOPortTag & x"00" & BSPITag & BSPIOutPin, -- I/O 15
IOPortTag & x"00" & BSPITag & BSPIClkPin, -- I/O 16
IOPortTag & x"00" & BSPITag & BSPIInPin, -- I/O 17
IOPortTag & x"00" & BSPITag & BSPICS2Pin, -- I/O 18
IOPortTag & x"00" & BSPITag & BSPICS1Pin, -- I/O 19
IOPortTag & x"00" & BSPITag & BSPICS0Pin, -- I/O 20
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 24
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 25
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 26
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 27
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 28
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 29
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 30
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 31
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 32
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 33
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 34
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 35
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
IOPortTag & x"01" & BSPITag & BSPIFramePin, -- I/O 38
IOPortTag & x"01" & BSPITag & BSPIOutPin, -- I/O 39
IOPortTag & x"01" & BSPITag & BSPIClkPin, -- I/O 40
IOPortTag & x"01" & BSPITag & BSPIInPin, -- I/O 41
IOPortTag & x"01" & BSPITag & BSPICS2Pin, -- I/O 42
IOPortTag & x"01" & BSPITag & BSPICS1Pin, -- I/O 43
IOPortTag & x"01" & BSPITag & BSPICS0Pin, -- I/O 44
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
IOPortTag & x"00" & NullTag & x"00", -- I/O 48
IOPortTag & x"00" & NullTag & x"00", -- I/O 49
IOPortTag & x"00" & NullTag & x"00", -- I/O 50
IOPortTag & x"00" & NullTag & x"00", -- I/O 51
IOPortTag & x"00" & NullTag & x"00", -- I/O 52
IOPortTag & x"00" & NullTag & x"00", -- I/O 53
IOPortTag & x"00" & NullTag & x"00", -- I/O 54
IOPortTag & x"00" & NullTag & x"00", -- I/O 55
IOPortTag & x"00" & NullTag & x"00", -- I/O 56
IOPortTag & x"00" & NullTag & x"00", -- I/O 57
IOPortTag & x"00" & NullTag & x"00", -- I/O 58
IOPortTag & x"00" & NullTag & x"00", -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST8_4IM2 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"04", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST8_4IM2 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 00
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 02
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 04
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 06
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 07
IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 08
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 09
IOPortTag & x"01" & PWMTag & PWMCEnaPin, -- I/O 10
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 11
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 12
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 14
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 16
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 18
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 19
IOPortTag & x"03" & PWMTag & PWMBDirPin, -- I/O 20
IOPortTag & x"02" & PWMTag & PWMBDirPin, -- I/O 21
IOPortTag & x"03" & PWMTag & PWMCEnaPin, -- I/O 22
IOPortTag & x"02" & PWMTag & PWMCenaPin, -- I/O 23
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 24
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 25
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 26
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 27
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 28
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 29
IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 30
IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 31
IOPortTag & x"05" & PWMTag & PWMBDirPin, -- I/O 32
IOPortTag & x"04" & PWMTag & PWMBDirPin, -- I/O 33
IOPortTag & x"05" & PWMTag & PWMCEnaPin, -- I/O 34
IOPortTag & x"04" & PWMTag & PWMCEnaPin, -- I/O 35
IOPortTag & x"07" & QCountTag & QCountQBPin, -- I/O 36
IOPortTag & x"07" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"06" & QCountTag & QCountQBPin, -- I/O 38
IOPortTag & x"06" & QCountTag & QCountQAPin, -- I/O 39
IOPortTag & x"07" & QCountTag & QCountIDXPin, -- I/O 40
IOPortTag & x"06" & QCountTag & QCountIDXPin, -- I/O 41
IOPortTag & x"07" & PWMTag & PWMAOutPin, -- I/O 42
IOPortTag & x"06" & PWMTag & PWMAOutPin, -- I/O 43
IOPortTag & x"07" & PWMTag & PWMBDirPin, -- I/O 44
IOPortTag & x"06" & PWMTag & PWMBDirPin, -- I/O 45
IOPortTag & x"07" & PWMTag & PWMCEnaPin, -- I/O 46
IOPortTag & x"06" & PWMTag & PWMCEnaPin, -- I/O 47
IOPortTag & x"00" & QCountTag & QCountIdxMaskPin, -- I/O 48
IOPortTag & x"01" & QCountTag & QCountIdxMaskPin, -- I/O 49
IOPortTag & x"02" & QCountTag & QCountIdxMaskPin, -- I/O 50
IOPortTag & x"03" & QCountTag & QCountIdxMaskPin, -- I/O 51
IOPortTag & x"04" & QCountTag & QCountIdxMaskPin, -- I/O 52
IOPortTag & x"05" & QCountTag & QCountIdxMaskPin, -- I/O 53
IOPortTag & x"06" & QCountTag & QCountIdxMaskPin, -- I/O 54
IOPortTag & x"07" & QCountTag & QCountIdxMaskPin, -- I/O 55
IOPortTag & x"00" & NullTag & x"00", -- I/O 56
IOPortTag & x"00" & NullTag & x"00", -- I/O 57
IOPortTag & x"00" & NullTag & x"00", -- I/O 58
IOPortTag & x"00" & NullTag & x"00", -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 64
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 65
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 66
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 67
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 68
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 69
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 70
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVUA8_4 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(UARTTTag, x"00", ClockLowTag, x"04", UARTTDataAddr&PadT, UARTTNumRegs, x"00", UARTTMPBitMask),
(UARTRTag, x"00", ClockLowTag, x"04", UARTRDataAddr&PadT, UARTRNumRegs, x"00", UARTRMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVUA8_4 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 00
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 02
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 04
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 06
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 07
IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 08
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 09
IOPortTag & x"01" & PWMTag & PWMCEnaPin, -- I/O 10
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 11
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 12
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 14
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 16
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 18
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 19
IOPortTag & x"03" & PWMTag & PWMBDirPin, -- I/O 20
IOPortTag & x"02" & PWMTag & PWMBDirPin, -- I/O 21
IOPortTag & x"03" & PWMTag & PWMCEnaPin, -- I/O 22
IOPortTag & x"02" & PWMTag & PWMCenaPin, -- I/O 23
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 24
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 25
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 26
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 27
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 28
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 29
IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 30
IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 31
IOPortTag & x"05" & PWMTag & PWMBDirPin, -- I/O 32
IOPortTag & x"04" & PWMTag & PWMBDirPin, -- I/O 33
IOPortTag & x"05" & PWMTag & PWMCEnaPin, -- I/O 34
IOPortTag & x"04" & PWMTag & PWMCEnaPin, -- I/O 35
IOPortTag & x"07" & QCountTag & QCountQBPin, -- I/O 36
IOPortTag & x"07" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"06" & QCountTag & QCountQBPin, -- I/O 38
IOPortTag & x"06" & QCountTag & QCountQAPin, -- I/O 39
IOPortTag & x"07" & QCountTag & QCountIDXPin, -- I/O 40
IOPortTag & x"06" & QCountTag & QCountIDXPin, -- I/O 41
IOPortTag & x"07" & PWMTag & PWMAOutPin, -- I/O 42
IOPortTag & x"06" & PWMTag & PWMAOutPin, -- I/O 43
IOPortTag & x"07" & PWMTag & PWMBDirPin, -- I/O 44
IOPortTag & x"06" & PWMTag & PWMBDirPin, -- I/O 45
IOPortTag & x"07" & PWMTag & PWMCEnaPin, -- I/O 46
IOPortTag & x"06" & PWMTag & PWMCEnaPin, -- I/O 47
IOPortTag & x"00" & UARTRTag & URDataPin, -- I/O 48
IOPortTag & x"01" & UARTRTag & URDataPin, -- I/O 49
IOPortTag & x"02" & UARTRTag & URDataPin, -- I/O 50
IOPortTag & x"03" & UARTRTag & URDataPin, -- I/O 51
IOPortTag & x"00" & UARTTTag & UTDataPin, -- I/O 52
IOPortTag & x"00" & UARTTTag & UTDrvEnPin, -- I/O 53
IOPortTag & x"01" & UARTTTag & UTDataPin, -- I/O 54
IOPortTag & x"01" & UARTTTag & UTDrvEnPin, -- I/O 55
IOPortTag & x"02" & UARTTTag & UTDataPin, -- I/O 56
IOPortTag & x"02" & UARTTTag & UTDrvEnPin, -- I/O 57
IOPortTag & x"03" & UARTTTag & UTDataPin, -- I/O 58
IOPortTag & x"03" & UARTTTag & UTDrvEnPin, -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVUA8_8 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(UARTTTag, x"00", ClockLowTag, x"08", UARTTDataAddr&PadT, UARTTNumRegs, x"00", UARTTMPBitMask),
(UARTRTag, x"00", ClockLowTag, x"08", UARTRDataAddr&PadT, UARTRNumRegs, x"00", UARTRMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVUA8_8 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 00
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 02
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 04
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 06
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 07
IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 08
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 09
IOPortTag & x"01" & PWMTag & PWMCEnaPin, -- I/O 10
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 11
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 12
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 14
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 16
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 18
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 19
IOPortTag & x"03" & PWMTag & PWMBDirPin, -- I/O 20
IOPortTag & x"02" & PWMTag & PWMBDirPin, -- I/O 21
IOPortTag & x"03" & PWMTag & PWMCEnaPin, -- I/O 22
IOPortTag & x"02" & PWMTag & PWMCenaPin, -- I/O 23
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 24
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 25
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 26
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 27
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 28
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 29
IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 30
IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 31
IOPortTag & x"05" & PWMTag & PWMBDirPin, -- I/O 32
IOPortTag & x"04" & PWMTag & PWMBDirPin, -- I/O 33
IOPortTag & x"05" & PWMTag & PWMCEnaPin, -- I/O 34
IOPortTag & x"04" & PWMTag & PWMCEnaPin, -- I/O 35
IOPortTag & x"07" & QCountTag & QCountQBPin, -- I/O 36
IOPortTag & x"07" & QCountTag & QCountQAPin, -- I/O 37
IOPortTag & x"06" & QCountTag & QCountQBPin, -- I/O 38
IOPortTag & x"06" & QCountTag & QCountQAPin, -- I/O 39
IOPortTag & x"07" & QCountTag & QCountIDXPin, -- I/O 40
IOPortTag & x"06" & QCountTag & QCountIDXPin, -- I/O 41
IOPortTag & x"07" & PWMTag & PWMAOutPin, -- I/O 42
IOPortTag & x"06" & PWMTag & PWMAOutPin, -- I/O 43
IOPortTag & x"07" & PWMTag & PWMBDirPin, -- I/O 44
IOPortTag & x"06" & PWMTag & PWMBDirPin, -- I/O 45
IOPortTag & x"07" & PWMTag & PWMCEnaPin, -- I/O 46
IOPortTag & x"06" & PWMTag & PWMCEnaPin, -- I/O 47
IOPortTag & x"00" & UARTRTag & URDataPin, -- I/O 48
IOPortTag & x"01" & UARTRTag & URDataPin, -- I/O 49
IOPortTag & x"02" & UARTRTag & URDataPin, -- I/O 50
IOPortTag & x"03" & UARTRTag & URDataPin, -- I/O 51
IOPortTag & x"00" & UARTTTag & UTDataPin, -- I/O 52
IOPortTag & x"00" & UARTTTag & UTDrvEnPin, -- I/O 53
IOPortTag & x"01" & UARTTTag & UTDataPin, -- I/O 54
IOPortTag & x"01" & UARTTTag & UTDrvEnPin, -- I/O 55
IOPortTag & x"02" & UARTTTag & UTDataPin, -- I/O 56
IOPortTag & x"02" & UARTTTag & UTDrvEnPin, -- I/O 57
IOPortTag & x"03" & UARTTTag & UTDataPin, -- I/O 58
IOPortTag & x"03" & UARTTTag & UTDrvEnPin, -- I/O 59
IOPortTag & x"04" & UARTRTag & URDataPin, -- I/O 60
IOPortTag & x"05" & UARTRTag & URDataPin, -- I/O 61
IOPortTag & x"06" & UARTRTag & URDataPin, -- I/O 62
IOPortTag & x"07" & UARTRTag & URDataPin, -- I/O 63
IOPortTag & x"04" & UARTTTag & UTDataPin, -- I/O 64
IOPortTag & x"04" & UARTTTag & UTDrvEnPin, -- I/O 65
IOPortTag & x"05" & UARTTTag & UTDataPin, -- I/O 66
IOPortTag & x"05" & UARTTTag & UTDrvEnPin, -- I/O 67
IOPortTag & x"06" & UARTTTag & UTDataPin, -- I/O 68
IOPortTag & x"06" & UARTTTag & UTDrvEnPin, -- I/O 69
IOPortTag & x"07" & UARTTTag & UTDataPin, -- I/O 70
IOPortTag & x"07" & UARTTTag & UTDrvEnPin, -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_JDosa66 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"06", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_JDosa66 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 00
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 02
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 04
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 06
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 07
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 08
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 09
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 10
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 11
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 12
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 37
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 14
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 16
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"00" & NullTag & x"00", -- I/O 18
IOPortTag & x"00" & NullTag & x"00", -- I/O 19
IOPortTag & x"00" & NullTag & x"00", -- I/O 20
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 24
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 25
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 26
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 27
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 28
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 29
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 30
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 31
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 32
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 33
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 34
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 35
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
IOPortTag & x"00" & NullTag & x"00", -- I/O 37
IOPortTag & x"00" & NullTag & x"00", -- I/O 38
IOPortTag & x"00" & NullTag & x"00", -- I/O 39
IOPortTag & x"00" & NullTag & x"00", -- I/O 40
IOPortTag & x"00" & NullTag & x"00", -- I/O 41
IOPortTag & x"00" & NullTag & x"00", -- I/O 42
IOPortTag & x"00" & NullTag & x"00", -- I/O 43
IOPortTag & x"00" & NullTag & x"00", -- I/O 44
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
IOPortTag & x"00" & NullTag & x"00", -- I/O 48
IOPortTag & x"00" & NullTag & x"00", -- I/O 49
IOPortTag & x"00" & NullTag & x"00", -- I/O 50
IOPortTag & x"00" & NullTag & x"00", -- I/O 51
IOPortTag & x"00" & NullTag & x"00", -- I/O 52
IOPortTag & x"00" & NullTag & x"00", -- I/O 53
IOPortTag & x"00" & NullTag & x"00", -- I/O 54
IOPortTag & x"00" & NullTag & x"00", -- I/O 55
IOPortTag & x"00" & NullTag & x"00", -- I/O 56
IOPortTag & x"00" & NullTag & x"00", -- I/O 57
IOPortTag & x"00" & NullTag & x"00", -- I/O 58
IOPortTag & x"00" & NullTag & x"00", -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_JDosa88 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_JDosa88 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 00
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 02
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 04
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 06
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 07
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 08
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 09
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 10
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 11
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 12
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 37
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 14
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 16
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"06" & QCountTag & QCountQAPin, -- I/O 18
IOPortTag & x"06" & QCountTag & QCountQBPin, -- I/O 19
IOPortTag & x"06" & QCountTag & QCountIDXPin, -- I/O 20
IOPortTag & x"07" & QCountTag & QCountQAPin, -- I/O 21
IOPortTag & x"07" & QCountTag & QCountQBPin, -- I/O 22
IOPortTag & x"07" & QCountTag & QCountIDXPin, -- I/O 23
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 24
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 25
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 26
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 27
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 28
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 29
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 30
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 31
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 32
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 33
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 34
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 35
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 36
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 37
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 38
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 39
IOPortTag & x"00" & NullTag & x"00", -- I/O 40
IOPortTag & x"00" & NullTag & x"00", -- I/O 41
IOPortTag & x"00" & NullTag & x"00", -- I/O 42
IOPortTag & x"00" & NullTag & x"00", -- I/O 43
IOPortTag & x"00" & NullTag & x"00", -- I/O 44
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
IOPortTag & x"00" & NullTag & x"00", -- I/O 48
IOPortTag & x"00" & NullTag & x"00", -- I/O 49
IOPortTag & x"00" & NullTag & x"00", -- I/O 50
IOPortTag & x"00" & NullTag & x"00", -- I/O 51
IOPortTag & x"00" & NullTag & x"00", -- I/O 52
IOPortTag & x"00" & NullTag & x"00", -- I/O 53
IOPortTag & x"00" & NullTag & x"00", -- I/O 54
IOPortTag & x"00" & NullTag & x"00", -- I/O 55
IOPortTag & x"00" & NullTag & x"00", -- I/O 56
IOPortTag & x"00" & NullTag & x"00", -- I/O 57
IOPortTag & x"00" & NullTag & x"00", -- I/O 58
IOPortTag & x"00" & NullTag & x"00", -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_JDosa1212 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"0C", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_JDosa1212 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 00
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 01
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 02
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 03
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 04
IOPortTag & x"01" & QCountTag & QCountIDXPin, -- I/O 05
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 06
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 07
IOPortTag & x"02" & QCountTag & QCountIDXPin, -- I/O 08
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 09
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 10
IOPortTag & x"03" & QCountTag & QCountIDXPin, -- I/O 11
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 12
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 37
IOPortTag & x"04" & QCountTag & QCountIDXPin, -- I/O 14
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 15
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 16
IOPortTag & x"05" & QCountTag & QCountIDXPin, -- I/O 17
IOPortTag & x"06" & QCountTag & QCountQAPin, -- I/O 18
IOPortTag & x"06" & QCountTag & QCountQBPin, -- I/O 19
IOPortTag & x"06" & QCountTag & QCountIDXPin, -- I/O 20
IOPortTag & x"07" & QCountTag & QCountQAPin, -- I/O 21
IOPortTag & x"07" & QCountTag & QCountQBPin, -- I/O 22
IOPortTag & x"07" & QCountTag & QCountIDXPin, -- I/O 23
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 24
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 25
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 26
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 27
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 28
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 29
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 30
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 31
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 32
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 33
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 34
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 35
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 36
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 37
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 38
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 39
IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 40
IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 41
IOPortTag & x"09" & StepGenTag & StepGenStepPin, -- I/O 42
IOPortTag & x"09" & StepGenTag & StepGenDirPin, -- I/O 43
IOPortTag & x"0A" & StepGenTag & StepGenStepPin, -- I/O 44
IOPortTag & x"0A" & StepGenTag & StepGenDirPin, -- I/O 45
IOPortTag & x"0B" & StepGenTag & StepGenStepPin, -- I/O 46
IOPortTag & x"0B" & StepGenTag & StepGenDirPin, -- I/O 47
IOPortTag & x"08" & QCountTag & QCountQAPin, -- I/O 48
IOPortTag & x"08" & QCountTag & QCountQBPin, -- I/O 49
IOPortTag & x"08" & QCountTag & QCountIDXPin, -- I/O 50
IOPortTag & x"09" & QCountTag & QCountQAPin, -- I/O 51
IOPortTag & x"09" & QCountTag & QCountQBPin, -- I/O 52
IOPortTag & x"09" & QCountTag & QCountIDXPin, -- I/O 53
IOPortTag & x"0A" & QCountTag & QCountQAPin, -- I/O 54
IOPortTag & x"0A" & QCountTag & QCountQBPin, -- I/O 55
IOPortTag & x"0A" & QCountTag & QCountIDXPin, -- I/O 56
IOPortTag & x"0B" & QCountTag & QCountQAPin, -- I/O 57
IOPortTag & x"0B" & QCountTag & QCountQBPin, -- I/O 58
IOPortTag & x"0B" & QCountTag & QCountIDXPin, -- I/O 59
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
-------------------------------------------------------------------------------------------------
-- 4 connector pinouts (5I22)
-------------------------------------------------------------------------------------------------
constant ModuleID_4xi30 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"04", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"10", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"10", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_4xi30 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"09" & QCountTag & x"02",
IOPortTag & x"09" & QCountTag & x"01",
IOPortTag & x"08" & QCountTag & x"02",
IOPortTag & x"08" & QCountTag & x"01",
IOPortTag & x"09" & QCountTag & x"03",
IOPortTag & x"08" & QCountTag & x"03",
IOPortTag & x"09" & PWMTag & x"81",
IOPortTag & x"08" & PWMTag & x"81",
IOPortTag & x"09" & PWMTag & x"82",
IOPortTag & x"08" & PWMTag & x"82",
IOPortTag & x"09" & PWMTag & x"83",
IOPortTag & x"08" & PWMTag & x"83",
IOPortTag & x"0B" & QCountTag & x"02",
IOPortTag & x"0B" & QCountTag & x"01",
IOPortTag & x"0A" & QCountTag & x"02",
IOPortTag & x"0A" & QCountTag & x"01",
IOPortTag & x"0B" & QCountTag & x"03",
IOPortTag & x"0A" & QCountTag & x"03",
IOPortTag & x"0B" & PWMTag & x"81",
IOPortTag & x"0A" & PWMTag & x"81",
IOPortTag & x"0B" & PWMTag & x"82",
IOPortTag & x"0A" & PWMTag & x"82",
IOPortTag & x"0B" & PWMTag & x"83",
IOPortTag & x"0A" & PWMTag & x"83",
IOPortTag & x"0D" & QCountTag & x"02",
IOPortTag & x"0D" & QCountTag & x"01",
IOPortTag & x"0C" & QCountTag & x"02",
IOPortTag & x"0C" & QCountTag & x"01",
IOPortTag & x"0D" & QCountTag & x"03",
IOPortTag & x"0C" & QCountTag & x"03",
IOPortTag & x"0D" & PWMTag & x"81",
IOPortTag & x"0C" & PWMTag & x"81",
IOPortTag & x"0D" & PWMTag & x"82",
IOPortTag & x"0C" & PWMTag & x"82",
IOPortTag & x"0D" & PWMTag & x"83",
IOPortTag & x"0C" & PWMTag & x"83",
IOPortTag & x"0F" & QCountTag & x"02",
IOPortTag & x"0F" & QCountTag & x"01",
IOPortTag & x"0E" & QCountTag & x"02",
IOPortTag & x"0E" & QCountTag & x"01",
IOPortTag & x"0F" & QCountTag & x"03",
IOPortTag & x"0E" & QCountTag & x"03",
IOPortTag & x"0F" & PWMTag & x"81",
IOPortTag & x"0E" & PWMTag & x"81",
IOPortTag & x"0F" & PWMTag & x"82",
IOPortTag & x"0E" & PWMTag & x"82",
IOPortTag & x"0F" & PWMTag & x"83",
IOPortTag & x"0E" & PWMTag & x"83",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST8_8 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"04", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST8_8 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"00" & StepGenTag & x"83",
IOPortTag & x"00" & StepGenTag & x"84",
IOPortTag & x"00" & StepGenTag & x"85",
IOPortTag & x"00" & StepGenTag & x"86",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"83",
IOPortTag & x"01" & StepGenTag & x"84",
IOPortTag & x"01" & StepGenTag & x"85",
IOPortTag & x"01" & StepGenTag & x"86",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"83",
IOPortTag & x"02" & StepGenTag & x"84",
IOPortTag & x"02" & StepGenTag & x"85",
IOPortTag & x"02" & StepGenTag & x"86",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"83",
IOPortTag & x"03" & StepGenTag & x"84",
IOPortTag & x"03" & StepGenTag & x"85",
IOPortTag & x"03" & StepGenTag & x"86",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"83",
IOPortTag & x"04" & StepGenTag & x"84",
IOPortTag & x"04" & StepGenTag & x"85",
IOPortTag & x"04" & StepGenTag & x"86",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"83",
IOPortTag & x"05" & StepGenTag & x"84",
IOPortTag & x"05" & StepGenTag & x"85",
IOPortTag & x"05" & StepGenTag & x"86",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"83",
IOPortTag & x"06" & StepGenTag & x"84",
IOPortTag & x"06" & StepGenTag & x"85",
IOPortTag & x"06" & StepGenTag & x"86",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"83",
IOPortTag & x"07" & StepGenTag & x"84",
IOPortTag & x"07" & StepGenTag & x"85",
IOPortTag & x"07" & StepGenTag & x"86",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVST8_24 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"04", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"18", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVST8_24 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"08" & StepGenTag & x"81",
IOPortTag & x"08" & StepGenTag & x"82",
IOPortTag & x"09" & StepGenTag & x"81",
IOPortTag & x"09" & StepGenTag & x"82",
IOPortTag & x"0A" & StepGenTag & x"81",
IOPortTag & x"0A" & StepGenTag & x"82",
IOPortTag & x"0B" & StepGenTag & x"81",
IOPortTag & x"0B" & StepGenTag & x"82",
IOPortTag & x"0C" & StepGenTag & x"81",
IOPortTag & x"0C" & StepGenTag & x"82",
IOPortTag & x"0D" & StepGenTag & x"81",
IOPortTag & x"0D" & StepGenTag & x"82",
IOPortTag & x"0E" & StepGenTag & x"81",
IOPortTag & x"0E" & StepGenTag & x"82",
IOPortTag & x"0F" & StepGenTag & x"81",
IOPortTag & x"0F" & StepGenTag & x"82",
IOPortTag & x"10" & StepGenTag & x"81",
IOPortTag & x"10" & StepGenTag & x"82",
IOPortTag & x"11" & StepGenTag & x"81",
IOPortTag & x"11" & StepGenTag & x"82",
IOPortTag & x"12" & StepGenTag & x"81",
IOPortTag & x"12" & StepGenTag & x"82",
IOPortTag & x"13" & StepGenTag & x"81",
IOPortTag & x"13" & StepGenTag & x"82",
IOPortTag & x"14" & StepGenTag & x"81",
IOPortTag & x"14" & StepGenTag & x"82",
IOPortTag & x"15" & StepGenTag & x"81",
IOPortTag & x"15" & StepGenTag & x"82",
IOPortTag & x"16" & StepGenTag & x"81",
IOPortTag & x"16" & StepGenTag & x"82",
IOPortTag & x"17" & StepGenTag & x"81",
IOPortTag & x"17" & StepGenTag & x"82",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
constant ModuleID_SVSTSP8_12_6 : ModuleIDType :=(
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
(IOPortTag, x"00", ClockLowTag, x"04", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
(QcountTag, x"02", ClockLowTag, x"08", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
(PWMTag, x"00", ClockHighTag, x"08", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
(StepGenTag, x"01", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
(SPITag, x"00", ClockLowTag, x"06", SPIDataAddr&PadT, SPINumRegs, x"00", SPIMPBitMask),
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
);
constant PinDesc_SVSTSP8_12_6 : PinDescType :=(
-- Base func sec unit sec func sec pin
IOPortTag & x"01" & QCountTag & x"02",
IOPortTag & x"01" & QCountTag & x"01",
IOPortTag & x"00" & QCountTag & x"02",
IOPortTag & x"00" & QCountTag & x"01",
IOPortTag & x"01" & QCountTag & x"03",
IOPortTag & x"00" & QCountTag & x"03",
IOPortTag & x"01" & PWMTag & x"81",
IOPortTag & x"00" & PWMTag & x"81",
IOPortTag & x"01" & PWMTag & x"82",
IOPortTag & x"00" & PWMTag & x"82",
IOPortTag & x"01" & PWMTag & x"83",
IOPortTag & x"00" & PWMTag & x"83",
IOPortTag & x"03" & QCountTag & x"02",
IOPortTag & x"03" & QCountTag & x"01",
IOPortTag & x"02" & QCountTag & x"02",
IOPortTag & x"02" & QCountTag & x"01",
IOPortTag & x"03" & QCountTag & x"03",
IOPortTag & x"02" & QCountTag & x"03",
IOPortTag & x"03" & PWMTag & x"81",
IOPortTag & x"02" & PWMTag & x"81",
IOPortTag & x"03" & PWMTag & x"82",
IOPortTag & x"02" & PWMTag & x"82",
IOPortTag & x"03" & PWMTag & x"83",
IOPortTag & x"02" & PWMTag & x"83",
IOPortTag & x"05" & QCountTag & x"02",
IOPortTag & x"05" & QCountTag & x"01",
IOPortTag & x"04" & QCountTag & x"02",
IOPortTag & x"04" & QCountTag & x"01",
IOPortTag & x"05" & QCountTag & x"03",
IOPortTag & x"04" & QCountTag & x"03",
IOPortTag & x"05" & PWMTag & x"81",
IOPortTag & x"04" & PWMTag & x"81",
IOPortTag & x"05" & PWMTag & x"82",
IOPortTag & x"04" & PWMTag & x"82",
IOPortTag & x"05" & PWMTag & x"83",
IOPortTag & x"04" & PWMTag & x"83",
IOPortTag & x"07" & QCountTag & x"02",
IOPortTag & x"07" & QCountTag & x"01",
IOPortTag & x"06" & QCountTag & x"02",
IOPortTag & x"06" & QCountTag & x"01",
IOPortTag & x"07" & QCountTag & x"03",
IOPortTag & x"06" & QCountTag & x"03",
IOPortTag & x"07" & PWMTag & x"81",
IOPortTag & x"06" & PWMTag & x"81",
IOPortTag & x"07" & PWMTag & x"82",
IOPortTag & x"06" & PWMTag & x"82",
IOPortTag & x"07" & PWMTag & x"83",
IOPortTag & x"06" & PWMTag & x"83",
IOPortTag & x"00" & StepGenTag & x"81",
IOPortTag & x"00" & StepGenTag & x"82",
IOPortTag & x"01" & StepGenTag & x"81",
IOPortTag & x"01" & StepGenTag & x"82",
IOPortTag & x"02" & StepGenTag & x"81",
IOPortTag & x"02" & StepGenTag & x"82",
IOPortTag & x"03" & StepGenTag & x"81",
IOPortTag & x"03" & StepGenTag & x"82",
IOPortTag & x"04" & StepGenTag & x"81",
IOPortTag & x"04" & StepGenTag & x"82",
IOPortTag & x"05" & StepGenTag & x"81",
IOPortTag & x"05" & StepGenTag & x"82",
IOPortTag & x"06" & StepGenTag & x"81",
IOPortTag & x"06" & StepGenTag & x"82",
IOPortTag & x"07" & StepGenTag & x"81",
IOPortTag & x"07" & StepGenTag & x"82",
IOPortTag & x"08" & StepGenTag & x"81",
IOPortTag & x"08" & StepGenTag & x"82",
IOPortTag & x"09" & StepGenTag & x"81",
IOPortTag & x"09" & StepGenTag & x"82",
IOPortTag & x"0A" & StepGenTag & x"81",
IOPortTag & x"0A" & StepGenTag & x"82",
IOPortTag & x"0B" & StepGenTag & x"81",
IOPortTag & x"0B" & StepGenTag & x"82",
IOPortTag & x"00" & SPITag & x"81",
IOPortTag & x"00" & SPITag & x"82",
IOPortTag & x"00" & SPITag & x"83",
IOPortTag & x"00" & SPITag & x"04",
IOPortTag & x"01" & SPITag & x"81",
IOPortTag & x"01" & SPITag & x"82",
IOPortTag & x"01" & SPITag & x"83",
IOPortTag & x"01" & SPITag & x"04",
IOPortTag & x"02" & SPITag & x"81",
IOPortTag & x"02" & SPITag & x"82",
IOPortTag & x"02" & SPITag & x"83",
IOPortTag & x"02" & SPITag & x"04",
IOPortTag & x"03" & SPITag & x"81",
IOPortTag & x"03" & SPITag & x"82",
IOPortTag & x"03" & SPITag & x"83",
IOPortTag & x"03" & SPITag & x"04",
IOPortTag & x"04" & SPITag & x"81",
IOPortTag & x"04" & SPITag & x"82",
IOPortTag & x"04" & SPITag & x"83",
IOPortTag & x"04" & SPITag & x"04",
IOPortTag & x"05" & SPITag & x"81",
IOPortTag & x"05" & SPITag & x"82",
IOPortTag & x"05" & SPITag & x"83",
IOPortTag & x"05" & SPITag & x"04",
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
end package IDROMParms;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:08:23 06/14/2015
-- Design Name:
-- Module Name: Blank - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Blank is
port(
-- GODIL Switches
sw1 : in std_logic;
-- GODIL LEDs
led8 : out std_logic
);
end Blank;
architecture Behavioral of Blank is
begin
led8 <= sw1;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:08:23 06/14/2015
-- Design Name:
-- Module Name: Blank - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Blank is
port(
-- GODIL Switches
sw1 : in std_logic;
-- GODIL LEDs
led8 : out std_logic
);
end Blank;
architecture Behavioral of Blank is
begin
led8 <= sw1;
end Behavioral;
|
-------------------------------------------------------------------
-- System Generator version 12.1 VHDL source file.
--
-- Copyright(C) 2010 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2010 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 12.1 VHDL source file.
--
-- Copyright(C) 2010 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2010 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic;
ce_logic: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal internal_ce_logic: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
pipelined_ce_logic: if period > 1 generate
ce_gen_logic: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec_logic(num_pipeline_regs) <= '1';
else
ce_vec_logic(num_pipeline_regs) <= '0';
end if;
end process;
ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate
ce_logic_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec_logic(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec_logic(index-1 downto index-1)
);
end generate;
internal_ce_logic <= ce_vec_logic(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
ce_bufg_inst_logic: bufg
port map (
i => internal_ce_logic(0),
o => ce_logic
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
ce_logic <= internal_ce_logic(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
ce_logic <= sysce;
end generate;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 12.1 VHDL source file.
--
-- Copyright(C) 2010 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2010 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity xland2 is
port (
a : in std_logic;
b : in std_logic;
dout : out std_logic
);
end xland2;
architecture behavior of xland2 is
begin
dout <= a and b;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
clk_1: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity plb_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
plb_ce_1: out std_logic;
plb_clk_1: out std_logic
);
end plb_clock_driver;
architecture structural of plb_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
plb_ce_1 <= xlclockdriver_1_ce;
plb_clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_i2c_controller_s6_cw is
port (
ce: in std_logic := '1';
clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
i2c_sda_i: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
xps_ce: in std_logic := '1';
xps_clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
gpio_out8_o: out std_logic_vector(7 downto 0);
i2c_scl: out std_logic;
i2c_sda_o: out std_logic;
i2c_sda_t: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic
);
end sg_i2c_controller_s6_cw;
architecture structural of sg_i2c_controller_s6_cw is
component fifo_generator_spartan6_6_1_a1065cba3626fc97
port (
din: in std_logic_vector(31 downto 0);
rd_clk: in std_logic;
rd_en: in std_logic;
rst: in std_logic;
wr_clk: in std_logic;
wr_en: in std_logic;
dout: out std_logic_vector(31 downto 0);
empty: out std_logic;
full: out std_logic;
rd_data_count: out std_logic_vector(0 downto 0);
wr_data_count: out std_logic_vector(0 downto 0)
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of fifo_generator_spartan6_6_1_a1065cba3626fc97: component is true;
attribute box_type: string;
attribute box_type of fifo_generator_spartan6_6_1_a1065cba3626fc97: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of fifo_generator_spartan6_6_1_a1065cba3626fc97: component is true;
attribute optimize_primitives of fifo_generator_spartan6_6_1_a1065cba3626fc97: component is false;
attribute dont_touch of fifo_generator_spartan6_6_1_a1065cba3626fc97: component is true;
component fifo_generator_spartan6_6_1_ba61a4be12cec537
port (
din: in std_logic_vector(31 downto 0);
rd_clk: in std_logic;
rd_en: in std_logic;
rst: in std_logic;
wr_clk: in std_logic;
wr_en: in std_logic;
dout: out std_logic_vector(31 downto 0);
empty: out std_logic;
full: out std_logic;
wr_data_count: out std_logic_vector(0 downto 0)
);
end component;
attribute syn_black_box of fifo_generator_spartan6_6_1_ba61a4be12cec537: component is true;
attribute box_type of fifo_generator_spartan6_6_1_ba61a4be12cec537: component is "black_box";
attribute syn_noprune of fifo_generator_spartan6_6_1_ba61a4be12cec537: component is true;
attribute optimize_primitives of fifo_generator_spartan6_6_1_ba61a4be12cec537: component is false;
attribute dont_touch of fifo_generator_spartan6_6_1_ba61a4be12cec537: component is true;
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal ce_1_sg_x1: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_1_sg_x1: signal is "REDUCE";
signal clkNet: std_logic;
signal clkNet_x0: std_logic;
signal clk_1_sg_x1: std_logic;
signal cmd_request_rd_en: std_logic;
signal cmd_request_wr_en: std_logic;
signal cmd_response_rd_en: std_logic;
signal cmd_response_wr_en: std_logic;
signal data_in_net: std_logic_vector(7 downto 0);
signal data_in_x0_net: std_logic_vector(31 downto 0);
signal data_in_x1_net: std_logic_vector(31 downto 0);
signal data_out_x0_net: std_logic_vector(31 downto 0);
signal data_out_x1_net: std_logic_vector(31 downto 0);
signal empty_net: std_logic;
signal empty_x0_net: std_logic;
signal en_net: std_logic;
signal from_register_data_out_net: std_logic_vector(7 downto 0);
signal from_register_data_out_net_x0: std_logic_vector(7 downto 0);
signal full_net: std_logic;
signal gpio_out8_reg_ce: std_logic;
signal i2c_scl_net: std_logic;
signal i2c_sda_i_net: std_logic;
signal i2c_sda_o_net: std_logic;
signal i2c_sda_t_net: std_logic;
signal percent_full_net: std_logic;
signal percent_full_x0_net: std_logic;
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal persistentdff_inst_x0_q: std_logic;
attribute syn_keep of persistentdff_inst_x0_q: signal is true;
attribute keep of persistentdff_inst_x0_q: signal is true;
attribute preserve_signal of persistentdff_inst_x0_q: signal is true;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_ce_1_sg_x1: std_logic;
attribute MAX_FANOUT of plb_ce_1_sg_x1: signal is "REDUCE";
signal plb_clk_1_sg_x1: std_logic;
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal re_net: std_logic;
signal re_x0_net: std_logic;
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal sl_wrdack_x2: std_logic;
signal splb_rst_net: std_logic;
signal to_fifo_full_net: std_logic;
signal to_fifo_percent_full_net: std_logic;
signal we_net: std_logic;
signal we_x0_net: std_logic;
begin
clkNet <= clk;
i2c_sda_i_net <= i2c_sda_i;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
clkNet_x0 <= xps_clk;
gpio_out8_o <= from_register_data_out_net_x0;
i2c_scl <= i2c_scl_net;
i2c_sda_o <= i2c_sda_o_net;
i2c_sda_t <= i2c_sda_t_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x2;
sl_wrdack <= sl_wrdack_x1;
cmd_request: fifo_generator_spartan6_6_1_ba61a4be12cec537
port map (
din => data_in_x0_net,
rd_clk => clk_1_sg_x1,
rd_en => cmd_request_rd_en,
rst => '0',
wr_clk => plb_clk_1_sg_x1,
wr_en => cmd_request_wr_en,
dout => data_out_x1_net,
empty => empty_x0_net,
full => full_net,
wr_data_count(0) => percent_full_x0_net
);
cmd_request_re_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x1,
b => re_x0_net,
dout => cmd_request_rd_en
);
cmd_request_we_and2_comp: entity work.xland2
port map (
a => plb_ce_1_sg_x1,
b => we_net,
dout => cmd_request_wr_en
);
cmd_response: fifo_generator_spartan6_6_1_a1065cba3626fc97
port map (
din => data_in_x1_net,
rd_clk => plb_clk_1_sg_x1,
rd_en => cmd_response_rd_en,
rst => '0',
wr_clk => clk_1_sg_x1,
wr_en => cmd_response_wr_en,
dout => data_out_x0_net,
empty => empty_net,
full => to_fifo_full_net,
rd_data_count(0) => percent_full_net,
wr_data_count(0) => to_fifo_percent_full_net
);
cmd_response_re_and2_comp: entity work.xland2
port map (
a => plb_ce_1_sg_x1,
b => re_net,
dout => cmd_response_rd_en
);
cmd_response_we_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x1,
b => we_x0_net,
dout => cmd_response_wr_en
);
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet,
ce_1 => ce_1_sg_x1,
clk_1 => clk_1_sg_x1
);
gpio_out8: entity work.synth_reg_w_init
generic map (
width => 8,
init_index => 2,
init_value => b"00000000",
latency => 1
)
port map (
ce => gpio_out8_reg_ce,
clk => plb_clk_1_sg_x1,
clr => '0',
i => data_in_net,
o => from_register_data_out_net
);
gpio_out8_ce_and2_comp: entity work.xland2
port map (
a => plb_ce_1_sg_x1,
b => en_net,
dout => gpio_out8_reg_ce
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
persistentdff_inst_x0: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_x0_q,
q => persistentdff_inst_x0_q
);
plb_clock_driver_x0: entity work.plb_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet_x0,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1
);
sg_i2c_controller_s6_x0: entity work.sg_i2c_controller_s6
port map (
ce_1 => ce_1_sg_x1,
clk_1 => clk_1_sg_x1,
data_out => from_register_data_out_net,
data_out_x0 => data_out_x0_net,
data_out_x1 => data_out_x1_net,
dout => from_register_data_out_net,
empty => empty_net,
empty_x0 => empty_x0_net,
full => full_net,
i2c_sda_i => i2c_sda_i_net,
percent_full => percent_full_net,
percent_full_x0 => percent_full_x0_net,
plb_abus => plb_abus_net,
plb_ce_1 => plb_ce_1_sg_x1,
plb_clk_1 => plb_clk_1_sg_x1,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
data_in => data_in_net,
data_in_x0 => data_in_x0_net,
data_in_x1 => data_in_x1_net,
en => en_net,
gpio_out8_o => from_register_data_out_net_x0,
i2c_scl => i2c_scl_net,
i2c_sda_o => i2c_sda_o_net,
i2c_sda_t => i2c_sda_t_net,
re => re_net,
re_x0 => re_x0_net,
sl_addrack => sl_addrack_net,
sl_rdcomp => sl_rdcomp_net,
sl_rddack => sl_rddack_net,
sl_rddbus => sl_rddbus_net,
sl_wait => sl_wait_net,
sl_wrcomp => sl_wrdack_x2,
sl_wrdack => sl_wrdack_x1,
we => we_net,
we_x0 => we_x0_net
);
end structural;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sAltrBitPropagate is
generic (
QTB : string :="on";
QTB_PRODUCT : string :="DSP Builder";
QTB_VERSION : string :="6.0"
);
port (
d : in std_logic;
r : out std_logic
);
end alt_dspbuilder_sAltrBitPropagate ;
architecture sAltrBitPropagate_Synth of alt_dspbuilder_sAltrBitPropagate is
begin
r<=d;
end sAltrBitPropagate_Synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sAltrBitPropagate is
generic (
QTB : string :="on";
QTB_PRODUCT : string :="DSP Builder";
QTB_VERSION : string :="6.0"
);
port (
d : in std_logic;
r : out std_logic
);
end alt_dspbuilder_sAltrBitPropagate ;
architecture sAltrBitPropagate_Synth of alt_dspbuilder_sAltrBitPropagate is
begin
r<=d;
end sAltrBitPropagate_Synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sAltrBitPropagate is
generic (
QTB : string :="on";
QTB_PRODUCT : string :="DSP Builder";
QTB_VERSION : string :="6.0"
);
port (
d : in std_logic;
r : out std_logic
);
end alt_dspbuilder_sAltrBitPropagate ;
architecture sAltrBitPropagate_Synth of alt_dspbuilder_sAltrBitPropagate is
begin
r<=d;
end sAltrBitPropagate_Synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sAltrBitPropagate is
generic (
QTB : string :="on";
QTB_PRODUCT : string :="DSP Builder";
QTB_VERSION : string :="6.0"
);
port (
d : in std_logic;
r : out std_logic
);
end alt_dspbuilder_sAltrBitPropagate ;
architecture sAltrBitPropagate_Synth of alt_dspbuilder_sAltrBitPropagate is
begin
r<=d;
end sAltrBitPropagate_Synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sAltrBitPropagate is
generic (
QTB : string :="on";
QTB_PRODUCT : string :="DSP Builder";
QTB_VERSION : string :="6.0"
);
port (
d : in std_logic;
r : out std_logic
);
end alt_dspbuilder_sAltrBitPropagate ;
architecture sAltrBitPropagate_Synth of alt_dspbuilder_sAltrBitPropagate is
begin
r<=d;
end sAltrBitPropagate_Synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sAltrBitPropagate is
generic (
QTB : string :="on";
QTB_PRODUCT : string :="DSP Builder";
QTB_VERSION : string :="6.0"
);
port (
d : in std_logic;
r : out std_logic
);
end alt_dspbuilder_sAltrBitPropagate ;
architecture sAltrBitPropagate_Synth of alt_dspbuilder_sAltrBitPropagate is
begin
r<=d;
end sAltrBitPropagate_Synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sAltrBitPropagate is
generic (
QTB : string :="on";
QTB_PRODUCT : string :="DSP Builder";
QTB_VERSION : string :="6.0"
);
port (
d : in std_logic;
r : out std_logic
);
end alt_dspbuilder_sAltrBitPropagate ;
architecture sAltrBitPropagate_Synth of alt_dspbuilder_sAltrBitPropagate is
begin
r<=d;
end sAltrBitPropagate_Synth;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sAltrBitPropagate is
generic (
QTB : string :="on";
QTB_PRODUCT : string :="DSP Builder";
QTB_VERSION : string :="6.0"
);
port (
d : in std_logic;
r : out std_logic
);
end alt_dspbuilder_sAltrBitPropagate ;
architecture sAltrBitPropagate_Synth of alt_dspbuilder_sAltrBitPropagate is
begin
r<=d;
end sAltrBitPropagate_Synth;
|
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