content stringlengths 1 1.04M ⌀ |
|---|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:23:21 11/20/2016
-- Design Name:
-- Module Name: Forwarding - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
library ieee;
library ieee;
-- Some comment
library ieee;
library ieee;
library ieee;
|
entity FIFO is
end entity;
entity FIFO IS
end entity;
entity FIFO Is
end entity;
|
-- generated with romgen v3.0 by MikeJ
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ipl_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data : out std_logic_vector(7 downto 0)
);
end;
architectu... |
----------------------------------------------------------------------------------------------
--
-- Input file : config_Pkg.vhd
-- Design name : config_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Fac... |
----------------------------------------------------------------------------------------------
--
-- Input file : config_Pkg.vhd
-- Design name : config_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Fac... |
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_a
--
-- Generated
-- by: wig
-- on: Wed Dec 14 12:17:36 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author... |
-- #####################################################################################
--
-- #### #### #####
-- ## ## ##
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## #... |
-- #####################################################################################
--
-- #### #### #####
-- ## ## ##
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## #... |
-- #####################################################################################
--
-- #### #### #####
-- ## ## ##
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## #... |
-- NEED RESULT: ARCH00362.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00362: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00362: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport ... |
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 28-Mar-11
-- Project : RT Video Lab 1: Exercise 1
-- Description: Testbench for 5-tap FIR filter
--------------------------------------------------------------------... |
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library work;
use work.breakout_config.all;
entity game_logic is
port( clock : in std_logic;
reset : in std_logic;
control_en : in std_logic;
control_mode : in std_logic;
control_signal ... |
-- Btrace 448
-- Square Root Unit
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee_proposed.fixed_pkg.all;
entity squareroot is
generic(int, frac: integer := 16);
port(clk: in std_logic;
input: in std_logic_vector((int+frac)... |
library ieee;
use ieee.std_logic_1164.all;
entity ex is
port (clk, en : std_ulogic;
r1: std_ulogic;
r0: out std_ulogic);
end ex;
architecture behav of ex is
begin
process(clk)
begin
if rising_edge(clk) then
if en = '1' then
r0 <= r1;
end if;
end if;
end process;... |
library ieee;
use ieee.std_logic_1164.all;
entity ex is
port (clk, en : std_ulogic;
r1: std_ulogic;
r0: out std_ulogic);
end ex;
architecture behav of ex is
begin
process(clk)
begin
if rising_edge(clk) then
if en = '1' then
r0 <= r1;
end if;
end if;
end process;... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cpu is
port(
--system interface
clk: in std_logic;
res: in std_logic;
--bus interface
address: out std_logic_vector(23 downto 0);
data_mosi: out std_logic_vector(31 downto 0);
data_mi... |
-- File: BitSelectDemo.vhd
-- Generated by MyHDL 0.10
-- Date: Wed Aug 29 14:27:57 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_010.all;
entity BitSelectDemo is
port (
Index: in unsigned(3 downto 0);
Res: out unsigned(7 downto 0... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
entity p2s_dac is
port(
a,clk,clr: in std_logic;
datain1:in std_logic_vector(15 downto 0);
ld,s_data: out std_logic);
end p2s_dac;
architecture art of p2s_dac is
begin
process(a,clk,clr)
variable I: integer;
begin
if(clr=... |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License... |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library verilog;
use verilog.vl_types.all;
entity circuitoAdicional_TB is
end circuitoAdicional_TB;
|
--pwmDC
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity pwmDC is
Port ( CLK : in STD_LOGIC;
ENABLE : in STD_LOGIC;
DUTY : in STD_LOGIC_VECTOR (3 downto 0);
pino : out STD_LOGIC_VECTOR
);
end pwmDC;
a... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SEU_Disp22 is
Port ( Disp22 : in STD_LOGIC_VECTOR (21 downto 0);
Seu_Disp22_Out : out STD_LOGIC_VECTOR (31 downto 0));
end SEU_Disp22;
architecture Behavioral of SEU_Disp22 is
begin
proc... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 -... |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.RC5_PKG.ALL;
ENTITY tb_rc5 IS
PORT (
clr, clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
enc : IN STD_LOGIC; -- Encryption or decryption?
key_vld : IN STD_LOGIC; -- Indicate the input is user key
data_vld : IN STD_... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
library ieee;
use ieee.std_logic_1164.all;
entity mod5x is
generic (
NBITS: natural := 13
);
port (
clk: in std_logic;
dividend: in std_logic_vector (NBITS - 1 downto 0);
load: in std_logic;
remzero: out std_logic
);
end entity;
architectu... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/05/16 00:35:30
-- Nombre del módulo: bin7seg - Behavioral
-- Comentarios adicionales:
-- Recibe un valor de 9 bits y lo con... |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/05/16 00:35:30
-- Nombre del módulo: bin7seg - Behavioral
-- Comentarios adicionales:
-- Recibe un valor de 9 bits y lo con... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:37:34 09/26/2017
-- Design Name:
-- Module Name: IM - Arqim
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Rev... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ADS7830 is
generic (I2C_ADR : std_logic_vector(6 downto 0) := "1001000"
);
port (
SDA : inout std_logic;
SCL : in std_logic
);
end ADS7830;
architecture RTL of ADS7830 is
constant CMD_WORD : std_logic_vector(7 downto 0) := x"8C... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_573 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_573;
architecture augh of mul_573 is
signal tmp_res : signed(... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_573 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_573;
architecture augh of mul_573 is
signal tmp_res : signed(... |
-----------------------------------------------------------------------------
-- Title : I2C_minion Testbench: noisy scl
-----------------------------------------------------------------------------
-- File : I2C_minion_TB_002_noisy_scl.vhd
-- Author : Peter Samarin <peter.samarin@gmail.com>
------------... |
library verilog;
use verilog.vl_types.all;
entity gpio is
port(
clk : in vl_logic;
reset : in vl_logic;
cs_n : in vl_logic;
as_n : in vl_logic;
rw : in vl_logic;
addr : in vl_l... |
entity FIFO is
generic (
G_WIDTH : natural := 16
);
port (
I_DATA : in std_logic_vector(G_WIDTH - 1 downto 0);
O_DATA : in std_logic_vector(G_WIDTH - 1 downto 0)
);
end entity;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: ALUwithINPUT
-- Project Name: ALUwithINPUT
-- Target Devices: Spart... |
library verilog;
use verilog.vl_types.all;
entity generic_28nm_hp_mlab_cell_impl is
generic(
logical_ram_name: string := "lutram";
logical_ram_depth: integer := 0;
logical_ram_width: integer := 0;
first_address : integer := 0;
last_address : integer := 0;
first_... |
library verilog;
use verilog.vl_types.all;
entity generic_28nm_hp_mlab_cell_impl is
generic(
logical_ram_name: string := "lutram";
logical_ram_depth: integer := 0;
logical_ram_width: integer := 0;
first_address : integer := 0;
last_address : integer := 0;
first_... |
library verilog;
use verilog.vl_types.all;
entity generic_28nm_hp_mlab_cell_impl is
generic(
logical_ram_name: string := "lutram";
logical_ram_depth: integer := 0;
logical_ram_width: integer := 0;
first_address : integer := 0;
last_address : integer := 0;
first_... |
library verilog;
use verilog.vl_types.all;
entity generic_28nm_hp_mlab_cell_impl is
generic(
logical_ram_name: string := "lutram";
logical_ram_depth: integer := 0;
logical_ram_width: integer := 0;
first_address : integer := 0;
last_address : integer := 0;
first_... |
library verilog;
use verilog.vl_types.all;
entity generic_28nm_hp_mlab_cell_impl is
generic(
logical_ram_name: string := "lutram";
logical_ram_depth: integer := 0;
logical_ram_width: integer := 0;
first_address : integer := 0;
last_address : integer := 0;
first_... |
library ieee;
use ieee.std_logic_1164.all;
entity s7 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s7;
architecture behaviour of s7 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000010"=> so<=To_StdLogicVec... |
library ieee;
use ieee.std_logic_1164.all;
entity s7 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s7;
architecture behaviour of s7 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000010"=> so<=To_StdLogicVec... |
component ghrd_10as066n2_mm_bridge_0 is
generic (
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH : integer := 1;
PIPELINE_COMMAND : integer := 1;
PIPELINE_RESPONSE : integer := 1
);
port (
clk : in std_... |
-------------------------------------------------------------------------------
--
-- Ce bloc est le wrapper dans le bus ia
--
-- Ce module transfert tous les messages (????,addrsrc,addrdest,data) venant de
-- busin.
--
-- data est stocké dans un registre
--
-- Si addrdest==MYADDR, data est transmis sur busv
-- Sinon,... |
-- $Id: dcm_sfs_unisim_s3e.vhd 534 2013-09-22 21:37:24Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, eithe... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:35:09 06/03/2015
-- Design Name:
-- Module Name: module_CPU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
-------------------------------------------------------------------------------
--! @project Unrolled (factor 4) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
/*
This file is part of fpgaNES.
fpgaNES is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
fpgaNES is distributed in the hope that it will be... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : component INST1
port map (
PORT_... |
-- $Id: tb_nexys3_fusp.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either versio... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity SYNCHRONIZER is
port (
R : out std_logic;
G : out std_logic;
B : out std_logic;
HS : out std_logic;
VS : out std_logic;
CLK : in ... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity SYNCHRONIZER is
port (
R : out std_logic;
G : out std_logic;
B : out std_logic;
HS : out std_logic;
VS : out std_logic;
CLK : in ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : cntr_tb.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-... |
library ieee;
LIBRARY ieee;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:24:09 03/13/2013
-- Design Name:
-- Module Name: /home/steven/Documenten/Codes/pcarch/MIPSmodules/Control_tb.vhd
-- Project Name: MIPSmodules
-- Target Device:
-- Tool versions:
... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This fil... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias1: electrical;
term... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
entity subprg01 is
port (a : std_logic_vector (3 downto 0);
na : out std_logic_vector (3 downto 0));
end subprg01;
architecture behav of subprg01 is
procedure neg (v : inout std_logic_vector(3 downto 0)) is
begin
v := not v;
end neg;
begin
process(A)
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.03.2014 13:25:44
-- Design Name:
-- Module Name: Eth_GMII_RXTest - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This fi... |
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