content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary infor... |
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary infor... |
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary infor... |
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary infor... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i8259 is
port (
CLK : in std_logic;
RESET : in std_logic;
A0 : in std_logic;
WR : in std_logic;
INTA : in std_logic;
INTR : out std_logic;
IRQ : in std_logic_vector(7 dow... |
library verilog;
use verilog.vl_types.all;
entity memory_pipe_arbiter is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iDATA_REQ : in vl_logic;
oDATA_LOCK : out vl_logic;
iDATA_ORDER : in vl_logic_vector(1 downto 0);
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:45:27 11/28/2012
-- Design Name:
-- Module Name: mips - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_ok_7_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- ... |
-- NEED RESULT: ARCH00590: Variable declarations - composite globally static access subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
--------------------------------------... |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: EUDET TLU interface
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Utilidad_RS232 IS
END TB_Utilidad_RS232;
ARCHITECTURE behavior OF TB_Utilidad_RS232 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Utilidad_RS232
PORT(
clk : IN std_logic;
Recibo : IN std_logic... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.std_logic_arith.all;
use WORK.CONSCTANS.ALL;
entity COUNTER is
port (
CLK : in std_logic;
RESET : in std_logic;
UP : in std_logic;
CNT_OUT : out std_logic_vector (OUTPUT_WIDTH - 1 downto 0);
TOP : out std_log... |
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------... |
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------... |
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------... |
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------... |
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------... |
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------... |
-- NEED RESULT: ARCH00568: Attribute declarations - composite static subtypes with static initial values passed
-- NEED RESULT: ARCH00568: Attribute declarations - scalar static subtypes with generic initial values failed
-------------------------------------------------------------------------------
--
-- Cop... |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
library work;
use work.pkg_6502_opcodes.all;
use work.pkg_6502_decode.all;
use work.File_IO_pkg.all;
entity tb_data_oper is
end tb_data_oper;
architecture tb of ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
library work;
use work.pkg_6502_opcodes.all;
use work.pkg_6502_decode.all;
use work.File_IO_pkg.all;
entity tb_data_oper is
end tb_data_oper;
architecture tb of ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
library work;
use work.pkg_6502_opcodes.all;
use work.pkg_6502_decode.all;
use work.File_IO_pkg.all;
entity tb_data_oper is
end tb_data_oper;
architecture tb of ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
library work;
use work.pkg_6502_opcodes.all;
use work.pkg_6502_decode.all;
use work.File_IO_pkg.all;
entity tb_data_oper is
end tb_data_oper;
architecture tb of ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
library work;
use work.pkg_6502_opcodes.all;
use work.pkg_6502_decode.all;
use work.File_IO_pkg.all;
entity tb_data_oper is
end tb_data_oper;
architecture tb of ... |
entity ent is
end ent;
architecture behav of ent is
signal s : bit;
begin
s <= not s;
end behav;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:15:05 01/29/2014
-- Design Name:
-- Module Name: FloatingPointMul23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
-------------------------------------------------------------------------------
--
-- File: ConfigADC.vhd
-- Author: Tudor Gherman, Robert Bocos
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digile... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Lice... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Lice... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Lice... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- Lice... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
G_GEN_1 => 3,... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D3_C1 is
port(
rst : in STD_LOGIC;
sel : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D3_C1;
architecture D3_C1 of D3_C1 is
begin
process(rst,clk,sel)
variable dem:integer range 0 to 9;
begin
if (rst='1') then... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
termina... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity thermometersLogic is
generic(
termNumber : natural := 128
);
port(
rsTxBusy : in std_logic;
rst : in std_logic;
clk50Mhz : in std_logic;
clk3kHz : in std_logic;
rsDataOut : out s... |
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
signal x, y, result : std_logic := '1';
begin -- only
result <= x;
result <= y;
process
begin -- process
assert x = '1' report "TEST FAILED" severity failure;
assert y = '1' report "TEST FAILED" sever... |
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
signal x, y, result : std_logic := '1';
begin -- only
result <= x;
result <= y;
process
begin -- process
assert x = '1' report "TEST FAILED" severity failure;
assert y = '1' report "TEST FAILED" sever... |
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
signal x, y, result : std_logic := '1';
begin -- only
result <= x;
result <= y;
process
begin -- process
assert x = '1' report "TEST FAILED" severity failure;
assert y = '1' report "TEST FAILED" sever... |
-- ********************************************************************/
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROV... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... |
entity tb_snum04 is
end tb_snum04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_snum04 is
signal r : boolean;
begin
cmp04_1: entity work.snum04
port map (r);
process
begin
wait for 1 ns;
assert r severity failure;
wait;
end process;
end behav;
|
-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2014, Digilent RO. All rights reserved
--
----------------------------------------------... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
entity scrambler_tb is
end entity scrambler_tb;
architecture behaviour of scrambler_tb is
constant clk_period : time := 10 ns;
signal clk, reset : std_logic;
signal en, seed : std_logic;
signal d_in, d_out : std_logic;
begin
uut: entity work.sc... |
library ieee;
use ieee.std_logic_1164.all;
entity scrambler_tb is
end entity scrambler_tb;
architecture behaviour of scrambler_tb is
constant clk_period : time := 10 ns;
signal clk, reset : std_logic;
signal en, seed : std_logic;
signal d_in, d_out : std_logic;
begin
uut: entity work.sc... |
library ieee;
use ieee.std_logic_1164.all;
entity scrambler_tb is
end entity scrambler_tb;
architecture behaviour of scrambler_tb is
constant clk_period : time := 10 ns;
signal clk, reset : std_logic;
signal en, seed : std_logic;
signal d_in, d_out : std_logic;
begin
uut: entity work.sc... |
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'value("1") = 1 report "TEST FAILED value 1" severity FAILURE;
report "TEST PASSED value 1" severity NOTE;
assert small'value("2") = 2 report "TEST FAILED value 2" severit... |
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'value("1") = 1 report "TEST FAILED value 1" severity FAILURE;
report "TEST PASSED value 1" severity NOTE;
assert small'value("2") = 2 report "TEST FAILED value 2" severit... |
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'value("1") = 1 report "TEST FAILED value 1" severity FAILURE;
report "TEST PASSED value 1" severity NOTE;
assert small'value("2") = 2 report "TEST FAILED value 2" severit... |
architecture RTL of ENT is
begin
end RTL;
architecture rtl of ENT is
begin
end rtl;
architecture Rtl of ENT is
begin
end Rtl;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
package QueueP is
generic (
type QUEUE_TYPE;
function to_string(d : in QUEUE_TYPE) return string
);
-- simple queue interface
type t_simple_queue is protected
procedure push (data : in QUEUE_TYPE);
procedure pop (data : out QUEUE_TYPE);
... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:57 2017
-- Host : DarkCube running 64-bit major re... |
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: dsp_round - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
--------------------------------------------------... |
----------------------------------------------------------------------------------
--THE FOLLOWING IS THE CODE FOR 16X 1 MEM , WHICH CAN BE USED AS OUTRAM, WHICH CAN BE
--WRITTEN AND READ ACCORDING TO THE CONDITION IN WriteEnable PIN
--
----------------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- ilmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_00_b;
use lmb_br... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You m... |
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- ... |
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
-- Violations below
type state_machine
is (idle, write, read, done);
type state_machine
is (idle, write, read, done);
begin
end architecture RTL;
|
architecture rtl of fifo is
alias designator is name;
alias designator is name;
alias designator is name;
begin
end architecture rtl;
|
architecture rtl of fifo is
-- Type attributes
signal a : something'Ascending;
signal a : something'Base;
signal a : something'High;
signal a : something'Image(x);
signal a : something'Left;
signal a : something'LeftOf(x);
signal a : something'Low;
signal a : something'Pos(x);
signal a : something... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package maxfinder_pkg is
function log2ceil(x: natural) return natural;
component maxfinder_base
generic (
N_WINDOW_LENGTH : natural;
N_OUTPUTS : natural;
N_SAMPLE_BITS : natural;
S... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity access1 is
end entity;
architecture test of access1 is
type list;
type list_ptr is access list;
type list is record
link : list_ptr;
value : integer;
end record;
procedure list_add(l : inout list_ptr; v : integer) is
variable n : list_ptr;
begin
n := n... |
entity access1 is
end entity;
architecture test of access1 is
type list;
type list_ptr is access list;
type list is record
link : list_ptr;
value : integer;
end record;
procedure list_add(l : inout list_ptr; v : integer) is
variable n : list_ptr;
begin
n := n... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: y... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: divisor10.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ================================... |
--
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, o... |
-- $Id: ibdr_rk11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
-- $Id: ibdr_rk11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee... |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee... |
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