content stringlengths 1 1.04M ⌀ |
|---|
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2006-10-27 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
-- stefana 2014-04-30 Added external trace support
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library mdm_v3_2;
use mdm_v3_2.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
entity MDM is
generic (
C_FAMILY : string := "virtex7";
C_JTAG_CHAIN : integer := 2;
C_USE_BSCAN : integer := 0;
C_USE_CONFIG_RESET : integer := 0;
C_INTERCONNECT : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_FFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"0000_0000";
C_MB_DBG_PORTS : integer := 1;
C_DBG_REG_ACCESS : integer := 0;
C_DBG_MEM_ACCESS : integer := 0;
C_USE_UART : integer := 1;
C_USE_CROSS_TRIGGER : integer := 0;
C_TRACE_OUTPUT : integer := 0;
C_TRACE_DATA_WIDTH : integer range 2 to 32 := 32;
C_TRACE_CLK_FREQ_HZ : integer := 200000000;
C_TRACE_CLK_OUT_PHASE : integer range 0 to 360 := 90;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_THREAD_ID_WIDTH : integer := 1;
C_DATA_SIZE : integer range 32 to 32 := 32;
C_M_AXIS_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXIS_ID_WIDTH : integer range 1 to 7 := 7
);
port (
-- Global signals
Config_Reset : in std_logic := '0';
Scan_Reset_Sel : in std_logic := '0';
Scan_Reset : in std_logic := '0';
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- External cross trigger signals
Trig_In_0 : in std_logic;
Trig_Ack_In_0 : out std_logic;
Trig_Out_0 : out std_logic;
Trig_Ack_Out_0 : in std_logic;
Trig_In_1 : in std_logic;
Trig_Ack_In_1 : out std_logic;
Trig_Out_1 : out std_logic;
Trig_Ack_Out_1 : in std_logic;
Trig_In_2 : in std_logic;
Trig_Ack_In_2 : out std_logic;
Trig_Out_2 : out std_logic;
Trig_Ack_Out_2 : in std_logic;
Trig_In_3 : in std_logic;
Trig_Ack_In_3 : out std_logic;
Trig_Out_3 : out std_logic;
Trig_Ack_Out_3 : in std_logic;
-- AXI slave signals
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Bus master signals
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
LMB_Data_Addr_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_0 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_0 : out std_logic;
LMB_Read_Strobe_0 : out std_logic;
LMB_Write_Strobe_0 : out std_logic;
LMB_Ready_0 : in std_logic;
LMB_Wait_0 : in std_logic;
LMB_CE_0 : in std_logic;
LMB_UE_0 : in std_logic;
LMB_Byte_Enable_0 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_1 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_1 : out std_logic;
LMB_Read_Strobe_1 : out std_logic;
LMB_Write_Strobe_1 : out std_logic;
LMB_Ready_1 : in std_logic;
LMB_Wait_1 : in std_logic;
LMB_CE_1 : in std_logic;
LMB_UE_1 : in std_logic;
LMB_Byte_Enable_1 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_2 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_2 : out std_logic;
LMB_Read_Strobe_2 : out std_logic;
LMB_Write_Strobe_2 : out std_logic;
LMB_Ready_2 : in std_logic;
LMB_Wait_2 : in std_logic;
LMB_CE_2 : in std_logic;
LMB_UE_2 : in std_logic;
LMB_Byte_Enable_2 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_3 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_3 : out std_logic;
LMB_Read_Strobe_3 : out std_logic;
LMB_Write_Strobe_3 : out std_logic;
LMB_Ready_3 : in std_logic;
LMB_Wait_3 : in std_logic;
LMB_CE_3 : in std_logic;
LMB_UE_3 : in std_logic;
LMB_Byte_Enable_3 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_4 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_4 : out std_logic;
LMB_Read_Strobe_4 : out std_logic;
LMB_Write_Strobe_4 : out std_logic;
LMB_Ready_4 : in std_logic;
LMB_Wait_4 : in std_logic;
LMB_CE_4 : in std_logic;
LMB_UE_4 : in std_logic;
LMB_Byte_Enable_4 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_5 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_5 : out std_logic;
LMB_Read_Strobe_5 : out std_logic;
LMB_Write_Strobe_5 : out std_logic;
LMB_Ready_5 : in std_logic;
LMB_Wait_5 : in std_logic;
LMB_CE_5 : in std_logic;
LMB_UE_5 : in std_logic;
LMB_Byte_Enable_5 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_6 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_6 : out std_logic;
LMB_Read_Strobe_6 : out std_logic;
LMB_Write_Strobe_6 : out std_logic;
LMB_Ready_6 : in std_logic;
LMB_Wait_6 : in std_logic;
LMB_CE_6 : in std_logic;
LMB_UE_6 : in std_logic;
LMB_Byte_Enable_6 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_7 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_7 : out std_logic;
LMB_Read_Strobe_7 : out std_logic;
LMB_Write_Strobe_7 : out std_logic;
LMB_Ready_7 : in std_logic;
LMB_Wait_7 : in std_logic;
LMB_CE_7 : in std_logic;
LMB_UE_7 : in std_logic;
LMB_Byte_Enable_7 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_8 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_8 : out std_logic;
LMB_Read_Strobe_8 : out std_logic;
LMB_Write_Strobe_8 : out std_logic;
LMB_Ready_8 : in std_logic;
LMB_Wait_8 : in std_logic;
LMB_CE_8 : in std_logic;
LMB_UE_8 : in std_logic;
LMB_Byte_Enable_8 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_9 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_9 : out std_logic;
LMB_Read_Strobe_9 : out std_logic;
LMB_Write_Strobe_9 : out std_logic;
LMB_Ready_9 : in std_logic;
LMB_Wait_9 : in std_logic;
LMB_CE_9 : in std_logic;
LMB_UE_9 : in std_logic;
LMB_Byte_Enable_9 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_10 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_10 : out std_logic;
LMB_Read_Strobe_10 : out std_logic;
LMB_Write_Strobe_10 : out std_logic;
LMB_Ready_10 : in std_logic;
LMB_Wait_10 : in std_logic;
LMB_CE_10 : in std_logic;
LMB_UE_10 : in std_logic;
LMB_Byte_Enable_10 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_11 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_11 : out std_logic;
LMB_Read_Strobe_11 : out std_logic;
LMB_Write_Strobe_11 : out std_logic;
LMB_Ready_11 : in std_logic;
LMB_Wait_11 : in std_logic;
LMB_CE_11 : in std_logic;
LMB_UE_11 : in std_logic;
LMB_Byte_Enable_11 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_12 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_12 : out std_logic;
LMB_Read_Strobe_12 : out std_logic;
LMB_Write_Strobe_12 : out std_logic;
LMB_Ready_12 : in std_logic;
LMB_Wait_12 : in std_logic;
LMB_CE_12 : in std_logic;
LMB_UE_12 : in std_logic;
LMB_Byte_Enable_12 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_13 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_13 : out std_logic;
LMB_Read_Strobe_13 : out std_logic;
LMB_Write_Strobe_13 : out std_logic;
LMB_Ready_13 : in std_logic;
LMB_Wait_13 : in std_logic;
LMB_CE_13 : in std_logic;
LMB_UE_13 : in std_logic;
LMB_Byte_Enable_13 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_14 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_14 : out std_logic;
LMB_Read_Strobe_14 : out std_logic;
LMB_Write_Strobe_14 : out std_logic;
LMB_Ready_14 : in std_logic;
LMB_Wait_14 : in std_logic;
LMB_CE_14 : in std_logic;
LMB_UE_14 : in std_logic;
LMB_Byte_Enable_14 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_15 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_15 : out std_logic;
LMB_Read_Strobe_15 : out std_logic;
LMB_Write_Strobe_15 : out std_logic;
LMB_Ready_15 : in std_logic;
LMB_Wait_15 : in std_logic;
LMB_CE_15 : in std_logic;
LMB_UE_15 : in std_logic;
LMB_Byte_Enable_15 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_16 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_16 : out std_logic;
LMB_Read_Strobe_16 : out std_logic;
LMB_Write_Strobe_16 : out std_logic;
LMB_Ready_16 : in std_logic;
LMB_Wait_16 : in std_logic;
LMB_CE_16 : in std_logic;
LMB_UE_16 : in std_logic;
LMB_Byte_Enable_16 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_17 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_17 : out std_logic;
LMB_Read_Strobe_17 : out std_logic;
LMB_Write_Strobe_17 : out std_logic;
LMB_Ready_17 : in std_logic;
LMB_Wait_17 : in std_logic;
LMB_CE_17 : in std_logic;
LMB_UE_17 : in std_logic;
LMB_Byte_Enable_17 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_18 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_18 : out std_logic;
LMB_Read_Strobe_18 : out std_logic;
LMB_Write_Strobe_18 : out std_logic;
LMB_Ready_18 : in std_logic;
LMB_Wait_18 : in std_logic;
LMB_CE_18 : in std_logic;
LMB_UE_18 : in std_logic;
LMB_Byte_Enable_18 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_19 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_19 : out std_logic;
LMB_Read_Strobe_19 : out std_logic;
LMB_Write_Strobe_19 : out std_logic;
LMB_Ready_19 : in std_logic;
LMB_Wait_19 : in std_logic;
LMB_CE_19 : in std_logic;
LMB_UE_19 : in std_logic;
LMB_Byte_Enable_19 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_20 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_20 : out std_logic;
LMB_Read_Strobe_20 : out std_logic;
LMB_Write_Strobe_20 : out std_logic;
LMB_Ready_20 : in std_logic;
LMB_Wait_20 : in std_logic;
LMB_CE_20 : in std_logic;
LMB_UE_20 : in std_logic;
LMB_Byte_Enable_20 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_21 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_21 : out std_logic;
LMB_Read_Strobe_21 : out std_logic;
LMB_Write_Strobe_21 : out std_logic;
LMB_Ready_21 : in std_logic;
LMB_Wait_21 : in std_logic;
LMB_CE_21 : in std_logic;
LMB_UE_21 : in std_logic;
LMB_Byte_Enable_21 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_22 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_22 : out std_logic;
LMB_Read_Strobe_22 : out std_logic;
LMB_Write_Strobe_22 : out std_logic;
LMB_Ready_22 : in std_logic;
LMB_Wait_22 : in std_logic;
LMB_CE_22 : in std_logic;
LMB_UE_22 : in std_logic;
LMB_Byte_Enable_22 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_23 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_23 : out std_logic;
LMB_Read_Strobe_23 : out std_logic;
LMB_Write_Strobe_23 : out std_logic;
LMB_Ready_23 : in std_logic;
LMB_Wait_23 : in std_logic;
LMB_CE_23 : in std_logic;
LMB_UE_23 : in std_logic;
LMB_Byte_Enable_23 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_24 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_24 : out std_logic;
LMB_Read_Strobe_24 : out std_logic;
LMB_Write_Strobe_24 : out std_logic;
LMB_Ready_24 : in std_logic;
LMB_Wait_24 : in std_logic;
LMB_CE_24 : in std_logic;
LMB_UE_24 : in std_logic;
LMB_Byte_Enable_24 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_25 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_25 : out std_logic;
LMB_Read_Strobe_25 : out std_logic;
LMB_Write_Strobe_25 : out std_logic;
LMB_Ready_25 : in std_logic;
LMB_Wait_25 : in std_logic;
LMB_CE_25 : in std_logic;
LMB_UE_25 : in std_logic;
LMB_Byte_Enable_25 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_26 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_26 : out std_logic;
LMB_Read_Strobe_26 : out std_logic;
LMB_Write_Strobe_26 : out std_logic;
LMB_Ready_26 : in std_logic;
LMB_Wait_26 : in std_logic;
LMB_CE_26 : in std_logic;
LMB_UE_26 : in std_logic;
LMB_Byte_Enable_26 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_27 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_27 : out std_logic;
LMB_Read_Strobe_27 : out std_logic;
LMB_Write_Strobe_27 : out std_logic;
LMB_Ready_27 : in std_logic;
LMB_Wait_27 : in std_logic;
LMB_CE_27 : in std_logic;
LMB_UE_27 : in std_logic;
LMB_Byte_Enable_27 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_28 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_28 : out std_logic;
LMB_Read_Strobe_28 : out std_logic;
LMB_Write_Strobe_28 : out std_logic;
LMB_Ready_28 : in std_logic;
LMB_Wait_28 : in std_logic;
LMB_CE_28 : in std_logic;
LMB_UE_28 : in std_logic;
LMB_Byte_Enable_28 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_29 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_29 : out std_logic;
LMB_Read_Strobe_29 : out std_logic;
LMB_Write_Strobe_29 : out std_logic;
LMB_Ready_29 : in std_logic;
LMB_Wait_29 : in std_logic;
LMB_CE_29 : in std_logic;
LMB_UE_29 : in std_logic;
LMB_Byte_Enable_29 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_30 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_30 : out std_logic;
LMB_Read_Strobe_30 : out std_logic;
LMB_Write_Strobe_30 : out std_logic;
LMB_Ready_30 : in std_logic;
LMB_Wait_30 : in std_logic;
LMB_CE_30 : in std_logic;
LMB_UE_30 : in std_logic;
LMB_Byte_Enable_30 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_31 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_31 : out std_logic;
LMB_Read_Strobe_31 : out std_logic;
LMB_Write_Strobe_31 : out std_logic;
LMB_Ready_31 : in std_logic;
LMB_Wait_31 : in std_logic;
LMB_CE_31 : in std_logic;
LMB_UE_31 : in std_logic;
LMB_Byte_Enable_31 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External BSCAN inputs
-- These signals are used when C_USE_BSCAN = 2 (EXTERNAL)
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
-- External JTAG ports
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM;
architecture IMP of MDM is
function int2std (val : integer) return std_logic is
begin -- function int2std
if (val = 0) then
return '0';
else
return '1';
end if;
end function int2std;
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0) := X"00000000";
constant C_REG_NUM_CE : integer := 4 + 4 * C_DBG_REG_ACCESS;
constant C_REG_DATA_WIDTH : integer := 8 + 24 * C_DBG_REG_ACCESS;
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) :=
(31 downto 5 => '0', 4 => int2std(C_DBG_REG_ACCESS), 3 downto 0 => '1');
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := (
-- Registers Base Address (not used)
ZEROES & C_BASEADDR,
ZEROES & (C_BASEADDR or C_S_AXI_MIN_SIZE)
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (
0 => C_REG_NUM_CE
);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
constant C_TRACE_AXI_MASTER : boolean := C_TRACE_OUTPUT = 3;
--------------------------------------------------------------------------
-- Component declarations
--------------------------------------------------------------------------
component MDM_Core
generic (
C_JTAG_CHAIN : integer;
C_USE_BSCAN : integer;
C_USE_CONFIG_RESET : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8;
C_TRACE_OUTPUT : integer;
C_TRACE_DATA_WIDTH : integer;
C_TRACE_CLK_FREQ_HZ : integer;
C_TRACE_CLK_OUT_PHASE : integer;
C_M_AXIS_DATA_WIDTH : integer;
C_M_AXIS_ID_WIDTH : integer);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
-- AXI IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_data : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_dwr_start : out std_logic;
Master_dwr_next : in std_logic;
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External Trigger Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component MDM_Core;
component bus_master is
generic (
C_M_AXI_DATA_WIDTH : natural;
C_M_AXI_THREAD_ID_WIDTH : natural;
C_M_AXI_ADDR_WIDTH : natural;
C_DATA_SIZE : natural;
C_HAS_FIFO_PORTS : boolean;
C_HAS_DIRECT_PORT : boolean
);
port (
Rd_Start : in std_logic;
Rd_Addr : in std_logic_vector(31 downto 0);
Rd_Len : in std_logic_vector(4 downto 0);
Rd_Size : in std_logic_vector(1 downto 0);
Rd_Exclusive : in std_logic;
Rd_Idle : out std_logic;
Rd_Response : out std_logic_vector(1 downto 0);
Wr_Start : in std_logic;
Wr_Addr : in std_logic_vector(31 downto 0);
Wr_Len : in std_logic_vector(4 downto 0);
Wr_Size : in std_logic_vector(1 downto 0);
Wr_Exclusive : in std_logic;
Wr_Idle : out std_logic;
Wr_Response : out std_logic_vector(1 downto 0);
Data_Rd : in std_logic;
Data_Out : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Exists : out std_logic;
Data_Wr : in std_logic;
Data_In : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Empty : out std_logic;
Direct_Wr_Addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Direct_Wr_Len : in std_logic_vector(4 downto 0);
Direct_Wr_Data : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Direct_Wr_Start : in std_logic;
Direct_Wr_Next : out std_logic;
Direct_Wr_Done : out std_logic;
Direct_Wr_Resp : out std_logic_vector(1 downto 0);
LMB_Data_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe : out std_logic;
LMB_Read_Strobe : out std_logic;
LMB_Write_Strobe : out std_logic;
LMB_Ready : in std_logic;
LMB_Wait : in std_logic;
LMB_UE : in std_logic;
LMB_Byte_Enable : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WLAST : out std_logic;
M_AXI_WDATA : out std_logic_vector(31 downto 0);
M_AXI_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end component bus_master;
--------------------------------------------------------------------------
-- Functions
--------------------------------------------------------------------------
-- Returns at least 1
function MakePos (a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
constant C_EN_WIDTH : integer := MakePos(C_MB_DBG_PORTS);
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal tdi : std_logic;
signal reset : std_logic;
signal update : std_logic;
signal capture : std_logic;
signal shift : std_logic;
signal sel : std_logic;
signal drck : std_logic;
signal tdo : std_logic;
signal drck_i : std_logic;
signal update_i : std_logic;
signal dbgreg_drck : std_logic;
signal dbgreg_update : std_logic;
signal dbgreg_select : std_logic;
signal jtag_busy : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
signal bus2ip_cs : std_logic_vector(((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal mb_debug_enabled : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal master_rd_start : std_logic;
signal master_rd_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_rd_len : std_logic_vector(4 downto 0);
signal master_rd_size : std_logic_vector(1 downto 0);
signal master_rd_excl : std_logic;
signal master_rd_idle : std_logic;
signal master_rd_resp : std_logic_vector(1 downto 0);
signal master_wr_start : std_logic;
signal master_wr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_wr_len : std_logic_vector(4 downto 0);
signal master_wr_size : std_logic_vector(1 downto 0);
signal master_wr_excl : std_logic;
signal master_wr_idle : std_logic;
signal master_wr_resp : std_logic_vector(1 downto 0);
signal master_data_rd : std_logic;
signal master_data_out : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_exists : std_logic;
signal master_data_wr : std_logic;
signal master_data_in : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_empty : std_logic;
signal master_dwr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_dwr_len : std_logic_vector(4 downto 0);
signal master_dwr_data : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_dwr_start : std_logic;
signal master_dwr_next : std_logic;
signal master_dwr_done : std_logic;
signal master_dwr_resp : std_logic_vector(1 downto 0);
signal ext_trig_in : std_logic_vector(0 to 3);
signal ext_trig_Ack_In : std_logic_vector(0 to 3);
signal ext_trig_out : std_logic_vector(0 to 3);
signal ext_trig_Ack_Out : std_logic_vector(0 to 3);
--------------------------------------------------------------------------
-- Attibute declarations
--------------------------------------------------------------------------
attribute period : string;
attribute period of update : signal is "200 ns";
attribute buffer_type : string;
attribute buffer_type of update_i : signal is "none";
attribute buffer_type of MDM_Core_I1 : label is "none";
begin -- architecture IMP
Use_E2 : if C_USE_BSCAN /= 2 generate
begin
BSCANE2_I : BSCANE2
generic map (
DISABLE_JTAG => "FALSE",
JTAG_CHAIN => C_JTAG_CHAIN)
port map (
CAPTURE => capture, -- [out std_logic]
DRCK => drck_i, -- [out std_logic]
RESET => reset, -- [out std_logic]
RUNTEST => open, -- [out std_logic]
SEL => sel, -- [out std_logic]
SHIFT => shift, -- [out std_logic]
TCK => open, -- [out std_logic]
TDI => tdi, -- [out std_logic]
TMS => open, -- [out std_logic]
UPDATE => update_i, -- [out std_logic]
TDO => tdo); -- [in std_logic]
end generate Use_E2;
Use_External : if C_USE_BSCAN = 2 generate
begin
capture <= bscan_ext_capture;
drck_i <= bscan_ext_drck;
reset <= bscan_ext_reset;
sel <= bscan_ext_sel;
shift <= bscan_ext_shift;
tdi <= bscan_ext_tdi;
update_i <= bscan_ext_update;
bscan_ext_tdo <= tdo;
end generate Use_External;
No_External : if C_USE_BSCAN /= 2 generate
begin
bscan_ext_tdo <= '0';
end generate No_External;
Use_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 1 generate
signal dbgreg_select_n : std_logic;
signal dbgreg_drck_i : std_logic;
signal dbgreg_update_i : std_logic;
signal update_set : std_logic;
signal update_reset : std_logic;
begin
dbgreg_select_n <= not dbgreg_select;
-- drck <= dbgreg_drck when dbgreg_select = '1' else drck_i;
BUFG_DRCK : BUFG
port map (
O => dbgreg_drck_i,
I => dbgreg_drck
);
BUFGCTRL_DRCK : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => drck,
CE0 => '1',
CE1 => '1',
I0 => drck_i,
I1 => dbgreg_drck_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
-- update <= dbgreg_update when dbgreg_select = '1' else update_i;
BUFG_UPDATE : BUFG
port map (
O => dbgreg_update_i,
I => dbgreg_update
);
BUFGCTRL_UPDATE : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => update,
CE0 => '1',
CE1 => '1',
I0 => update_i,
I1 => dbgreg_update_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
JTAG_Busy_Detect : process (drck_i, sel, update_set, Config_Reset)
begin
if sel = '0' or update_set = '1' or Config_Reset = '1' then
jtag_busy <= '0';
update_reset <= '1';
elsif drck_i'event and drck_i = '1' then
if sel = '1' and capture = '1' then
jtag_busy <= '1';
end if;
update_reset <= '0';
end if;
end process JTAG_Busy_Detect;
JTAG_Update_Detect : process (update_i, update_reset, Config_Reset)
begin
if update_reset = '1' or Config_Reset = '1' then
update_set <= '0';
elsif update_i'event and update_i = '1' then
update_set <= '1';
end if;
end process JTAG_Update_Detect;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 0 generate
begin
BUFG_DRCK : BUFG
port map (
O => drck,
I => drck_i
);
update <= update_i;
jtag_busy <= '0';
end generate No_Dbg_Reg_Access;
---------------------------------------------------------------------------
-- MDM core
---------------------------------------------------------------------------
MDM_Core_I1 : MDM_Core
generic map (
C_JTAG_CHAIN => C_JTAG_CHAIN, -- [integer]
C_USE_BSCAN => C_USE_BSCAN, -- [integer]
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET, -- [integer = 0]
C_BASEADDR => C_BASEADDR, -- [std_logic_vector(0 to 31)]
C_HIGHADDR => C_HIGHADDR, -- [std_logic_vector(0 to 31)]
C_MB_DBG_PORTS => C_MB_DBG_PORTS, -- [integer]
C_EN_WIDTH => C_EN_WIDTH, -- [integer]
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS, -- [integer]
C_REG_NUM_CE => C_REG_NUM_CE, -- [integer]
C_REG_DATA_WIDTH => C_REG_DATA_WIDTH, -- [integer]
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS, -- [integer]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ, -- [integer]
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH, -- [integer]
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH, -- [integer]
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER, -- [integer]
C_USE_UART => C_USE_UART, -- [integer]
C_UART_WIDTH => 8, -- [integer]
C_TRACE_OUTPUT => C_TRACE_OUTPUT, -- [integer]
C_TRACE_DATA_WIDTH => C_TRACE_DATA_WIDTH, -- [integer]
C_TRACE_CLK_FREQ_HZ => C_TRACE_CLK_FREQ_HZ, -- [integer]
C_TRACE_CLK_OUT_PHASE => C_TRACE_CLK_OUT_PHASE, -- [integer]
C_M_AXIS_DATA_WIDTH => C_M_AXIS_DATA_WIDTH, -- [integer]
C_M_AXIS_ID_WIDTH => C_M_AXIS_ID_WIDTH -- [integer]
)
port map (
-- Global signals
Config_Reset => Config_Reset, -- [in std_logic]
Scan_Reset_Sel => Scan_Reset_Sel, -- [in std_logic]
Scan_Reset => Scan_Reset, -- [in std_logic]
M_AXIS_ACLK => M_AXIS_ACLK, -- [in std_logic]
M_AXIS_ARESETN => M_AXIS_ARESETN, -- [in std_logic]
Interrupt => Interrupt, -- [out std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst, -- [out std_logic]
-- Debug Register Access signals
DbgReg_DRCK => dbgreg_drck, -- [out std_logic]
DbgReg_UPDATE => dbgreg_update, -- [out std_logic]
DbgReg_Select => dbgreg_select, -- [out std_logic]
JTAG_Busy => jtag_busy, -- [in std_logic]
-- AXI IPIC signals
bus2ip_clk => bus2ip_clk,
bus2ip_resetn => bus2ip_resetn,
bus2ip_data => bus2ip_data(C_REG_DATA_WIDTH-1 downto 0),
bus2ip_rdce => bus2ip_rdce(C_REG_NUM_CE-1 downto 0),
bus2ip_wrce => bus2ip_wrce(C_REG_NUM_CE-1 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
ip2bus_data => ip2bus_data(C_REG_DATA_WIDTH-1 downto 0),
-- Bus Master signals
MB_Debug_Enabled => mb_debug_enabled,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
Master_rd_start => master_rd_start,
Master_rd_addr => master_rd_addr,
Master_rd_len => master_rd_len,
Master_rd_size => master_rd_size,
Master_rd_excl => master_rd_excl,
Master_rd_idle => master_rd_idle,
Master_rd_resp => master_rd_resp,
Master_wr_start => master_wr_start,
Master_wr_addr => master_wr_addr,
Master_wr_len => master_wr_len,
Master_wr_size => master_wr_size,
Master_wr_excl => master_wr_excl,
Master_wr_idle => master_wr_idle,
Master_wr_resp => master_wr_resp,
Master_data_rd => master_data_rd,
Master_data_out => master_data_out,
Master_data_exists => master_data_exists,
Master_data_wr => master_data_wr,
Master_data_in => master_data_in,
Master_data_empty => master_data_empty,
Master_dwr_addr => master_dwr_addr,
Master_dwr_len => master_dwr_len,
Master_dwr_data => master_dwr_data,
Master_dwr_start => master_dwr_start,
Master_dwr_next => master_dwr_next,
Master_dwr_done => master_dwr_done,
Master_dwr_resp => master_dwr_resp,
-- JTAG signals
JTAG_TDI => tdi, -- [in std_logic]
JTAG_RESET => reset, -- [in std_logic]
UPDATE => update, -- [in std_logic]
JTAG_SHIFT => shift, -- [in std_logic]
JTAG_CAPTURE => capture, -- [in std_logic]
SEL => sel, -- [in std_logic]
DRCK => drck, -- [in std_logic]
JTAG_TDO => tdo, -- [out std_logic]
-- External Trace AXI Stream output
M_AXIS_TDATA => M_AXIS_TDATA, -- [out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0)]
M_AXIS_TID => M_AXIS_TID, -- [out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0)]
M_AXIS_TREADY => M_AXIS_TREADY, -- [in std_logic]
M_AXIS_TVALID => M_AXIS_TVALID, -- [out std_logic]
-- External Trace output
TRACE_CLK_OUT => TRACE_CLK_OUT, -- [out std_logic]
TRACE_CLK => TRACE_CLK, -- [in std_logic]
TRACE_CTL => TRACE_CTL, -- [out std_logic]
TRACE_DATA => TRACE_DATA, -- [out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0)]
-- MicroBlaze Debug Signals
Dbg_Clk_0 => Dbg_Clk_0, -- [out std_logic]
Dbg_TDI_0 => Dbg_TDI_0, -- [out std_logic]
Dbg_TDO_0 => Dbg_TDO_0, -- [in std_logic]
Dbg_Reg_En_0 => Dbg_Reg_En_0, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_0 => Dbg_Capture_0, -- [out std_logic]
Dbg_Shift_0 => Dbg_Shift_0, -- [out std_logic]
Dbg_Update_0 => Dbg_Update_0, -- [out std_logic]
Dbg_Rst_0 => Dbg_Rst_0, -- [out std_logic]
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_0 => Dbg_TrClk_0, -- [out std_logic]
Dbg_TrData_0 => Dbg_TrData_0, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_0 => Dbg_TrReady_0, -- [out std_logic]
Dbg_TrValid_0 => Dbg_TrValid_0, -- [in std_logic]
Dbg_Clk_1 => Dbg_Clk_1, -- [out std_logic]
Dbg_TDI_1 => Dbg_TDI_1, -- [out std_logic]
Dbg_TDO_1 => Dbg_TDO_1, -- [in std_logic]
Dbg_Reg_En_1 => Dbg_Reg_En_1, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_1 => Dbg_Capture_1, -- [out std_logic]
Dbg_Shift_1 => Dbg_Shift_1, -- [out std_logic]
Dbg_Update_1 => Dbg_Update_1, -- [out std_logic]
Dbg_Rst_1 => Dbg_Rst_1, -- [out std_logic]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_1 => Dbg_TrClk_1, -- [out std_logic]
Dbg_TrData_1 => Dbg_TrData_1, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_1 => Dbg_TrReady_1, -- [out std_logic]
Dbg_TrValid_1 => Dbg_TrValid_1, -- [in std_logic]
Dbg_Clk_2 => Dbg_Clk_2, -- [out std_logic]
Dbg_TDI_2 => Dbg_TDI_2, -- [out std_logic]
Dbg_TDO_2 => Dbg_TDO_2, -- [in std_logic]
Dbg_Reg_En_2 => Dbg_Reg_En_2, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_2 => Dbg_Capture_2, -- [out std_logic]
Dbg_Shift_2 => Dbg_Shift_2, -- [out std_logic]
Dbg_Update_2 => Dbg_Update_2, -- [out std_logic]
Dbg_Rst_2 => Dbg_Rst_2, -- [out std_logic]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_2 => Dbg_TrClk_2, -- [out std_logic]
Dbg_TrData_2 => Dbg_TrData_2, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_2 => Dbg_TrReady_2, -- [out std_logic]
Dbg_TrValid_2 => Dbg_TrValid_2, -- [in std_logic]
Dbg_Clk_3 => Dbg_Clk_3, -- [out std_logic]
Dbg_TDI_3 => Dbg_TDI_3, -- [out std_logic]
Dbg_TDO_3 => Dbg_TDO_3, -- [in std_logic]
Dbg_Reg_En_3 => Dbg_Reg_En_3, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_3 => Dbg_Capture_3, -- [out std_logic]
Dbg_Shift_3 => Dbg_Shift_3, -- [out std_logic]
Dbg_Update_3 => Dbg_Update_3, -- [out std_logic]
Dbg_Rst_3 => Dbg_Rst_3, -- [out std_logic]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_3 => Dbg_TrClk_3, -- [out std_logic]
Dbg_TrData_3 => Dbg_TrData_3, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_3 => Dbg_TrReady_3, -- [out std_logic]
Dbg_TrValid_3 => Dbg_TrValid_3, -- [in std_logic]
Dbg_Clk_4 => Dbg_Clk_4, -- [out std_logic]
Dbg_TDI_4 => Dbg_TDI_4, -- [out std_logic]
Dbg_TDO_4 => Dbg_TDO_4, -- [in std_logic]
Dbg_Reg_En_4 => Dbg_Reg_En_4, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_4 => Dbg_Capture_4, -- [out std_logic]
Dbg_Shift_4 => Dbg_Shift_4, -- [out std_logic]
Dbg_Update_4 => Dbg_Update_4, -- [out std_logic]
Dbg_Rst_4 => Dbg_Rst_4, -- [out std_logic]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_4 => Dbg_TrClk_4, -- [out std_logic]
Dbg_TrData_4 => Dbg_TrData_4, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_4 => Dbg_TrReady_4, -- [out std_logic]
Dbg_TrValid_4 => Dbg_TrValid_4, -- [in std_logic]
Dbg_Clk_5 => Dbg_Clk_5, -- [out std_logic]
Dbg_TDI_5 => Dbg_TDI_5, -- [out std_logic]
Dbg_TDO_5 => Dbg_TDO_5, -- [in std_logic]
Dbg_Reg_En_5 => Dbg_Reg_En_5, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_5 => Dbg_Capture_5, -- [out std_logic]
Dbg_Shift_5 => Dbg_Shift_5, -- [out std_logic]
Dbg_Update_5 => Dbg_Update_5, -- [out std_logic]
Dbg_Rst_5 => Dbg_Rst_5, -- [out std_logic]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_5 => Dbg_TrClk_5, -- [out std_logic]
Dbg_TrData_5 => Dbg_TrData_5, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_5 => Dbg_TrReady_5, -- [out std_logic]
Dbg_TrValid_5 => Dbg_TrValid_5, -- [in std_logic]
Dbg_Clk_6 => Dbg_Clk_6, -- [out std_logic]
Dbg_TDI_6 => Dbg_TDI_6, -- [out std_logic]
Dbg_TDO_6 => Dbg_TDO_6, -- [in std_logic]
Dbg_Reg_En_6 => Dbg_Reg_En_6, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_6 => Dbg_Capture_6, -- [out std_logic]
Dbg_Shift_6 => Dbg_Shift_6, -- [out std_logic]
Dbg_Update_6 => Dbg_Update_6, -- [out std_logic]
Dbg_Rst_6 => Dbg_Rst_6, -- [out std_logic]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_6 => Dbg_TrClk_6, -- [out std_logic]
Dbg_TrData_6 => Dbg_TrData_6, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_6 => Dbg_TrReady_6, -- [out std_logic]
Dbg_TrValid_6 => Dbg_TrValid_6, -- [in std_logic]
Dbg_Clk_7 => Dbg_Clk_7, -- [out std_logic]
Dbg_TDI_7 => Dbg_TDI_7, -- [out std_logic]
Dbg_TDO_7 => Dbg_TDO_7, -- [in std_logic]
Dbg_Reg_En_7 => Dbg_Reg_En_7, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_7 => Dbg_Capture_7, -- [out std_logic]
Dbg_Shift_7 => Dbg_Shift_7, -- [out std_logic]
Dbg_Update_7 => Dbg_Update_7, -- [out std_logic]
Dbg_Rst_7 => Dbg_Rst_7, -- [out std_logic]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_7 => Dbg_TrClk_7, -- [out std_logic]
Dbg_TrData_7 => Dbg_TrData_7, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_7 => Dbg_TrReady_7, -- [out std_logic]
Dbg_TrValid_7 => Dbg_TrValid_7, -- [in std_logic]
Dbg_Clk_8 => Dbg_Clk_8, -- [out std_logic]
Dbg_TDI_8 => Dbg_TDI_8, -- [out std_logic]
Dbg_TDO_8 => Dbg_TDO_8, -- [in std_logic]
Dbg_Reg_En_8 => Dbg_Reg_En_8, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_8 => Dbg_Capture_8, -- [out std_logic]
Dbg_Shift_8 => Dbg_Shift_8, -- [out std_logic]
Dbg_Update_8 => Dbg_Update_8, -- [out std_logic]
Dbg_Rst_8 => Dbg_Rst_8, -- [out std_logic]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_8 => Dbg_TrClk_8, -- [out std_logic]
Dbg_TrData_8 => Dbg_TrData_8, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_8 => Dbg_TrReady_8, -- [out std_logic]
Dbg_TrValid_8 => Dbg_TrValid_8, -- [in std_logic]
Dbg_Clk_9 => Dbg_Clk_9, -- [out std_logic]
Dbg_TDI_9 => Dbg_TDI_9, -- [out std_logic]
Dbg_TDO_9 => Dbg_TDO_9, -- [in std_logic]
Dbg_Reg_En_9 => Dbg_Reg_En_9, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_9 => Dbg_Capture_9, -- [out std_logic]
Dbg_Shift_9 => Dbg_Shift_9, -- [out std_logic]
Dbg_Update_9 => Dbg_Update_9, -- [out std_logic]
Dbg_Rst_9 => Dbg_Rst_9, -- [out std_logic]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_9 => Dbg_TrClk_9, -- [out std_logic]
Dbg_TrData_9 => Dbg_TrData_9, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_9 => Dbg_TrReady_9, -- [out std_logic]
Dbg_TrValid_9 => Dbg_TrValid_9, -- [in std_logic]
Dbg_Clk_10 => Dbg_Clk_10, -- [out std_logic]
Dbg_TDI_10 => Dbg_TDI_10, -- [out std_logic]
Dbg_TDO_10 => Dbg_TDO_10, -- [in std_logic]
Dbg_Reg_En_10 => Dbg_Reg_En_10, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_10 => Dbg_Capture_10, -- [out std_logic]
Dbg_Shift_10 => Dbg_Shift_10, -- [out std_logic]
Dbg_Update_10 => Dbg_Update_10, -- [out std_logic]
Dbg_Rst_10 => Dbg_Rst_10, -- [out std_logic]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_10 => Dbg_TrClk_10, -- [out std_logic]
Dbg_TrData_10 => Dbg_TrData_10, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_10 => Dbg_TrReady_10, -- [out std_logic]
Dbg_TrValid_10 => Dbg_TrValid_10, -- [in std_logic]
Dbg_Clk_11 => Dbg_Clk_11, -- [out std_logic]
Dbg_TDI_11 => Dbg_TDI_11, -- [out std_logic]
Dbg_TDO_11 => Dbg_TDO_11, -- [in std_logic]
Dbg_Reg_En_11 => Dbg_Reg_En_11, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_11 => Dbg_Capture_11, -- [out std_logic]
Dbg_Shift_11 => Dbg_Shift_11, -- [out std_logic]
Dbg_Update_11 => Dbg_Update_11, -- [out std_logic]
Dbg_Rst_11 => Dbg_Rst_11, -- [out std_logic]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_11 => Dbg_TrClk_11, -- [out std_logic]
Dbg_TrData_11 => Dbg_TrData_11, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_11 => Dbg_TrReady_11, -- [out std_logic]
Dbg_TrValid_11 => Dbg_TrValid_11, -- [in std_logic]
Dbg_Clk_12 => Dbg_Clk_12, -- [out std_logic]
Dbg_TDI_12 => Dbg_TDI_12, -- [out std_logic]
Dbg_TDO_12 => Dbg_TDO_12, -- [in std_logic]
Dbg_Reg_En_12 => Dbg_Reg_En_12, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_12 => Dbg_Capture_12, -- [out std_logic]
Dbg_Shift_12 => Dbg_Shift_12, -- [out std_logic]
Dbg_Update_12 => Dbg_Update_12, -- [out std_logic]
Dbg_Rst_12 => Dbg_Rst_12, -- [out std_logic]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_12 => Dbg_TrClk_12, -- [out std_logic]
Dbg_TrData_12 => Dbg_TrData_12, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_12 => Dbg_TrReady_12, -- [out std_logic]
Dbg_TrValid_12 => Dbg_TrValid_12, -- [in std_logic]
Dbg_Clk_13 => Dbg_Clk_13, -- [out std_logic]
Dbg_TDI_13 => Dbg_TDI_13, -- [out std_logic]
Dbg_TDO_13 => Dbg_TDO_13, -- [in std_logic]
Dbg_Reg_En_13 => Dbg_Reg_En_13, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_13 => Dbg_Capture_13, -- [out std_logic]
Dbg_Shift_13 => Dbg_Shift_13, -- [out std_logic]
Dbg_Update_13 => Dbg_Update_13, -- [out std_logic]
Dbg_Rst_13 => Dbg_Rst_13, -- [out std_logic]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_13 => Dbg_TrClk_13, -- [out std_logic]
Dbg_TrData_13 => Dbg_TrData_13, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_13 => Dbg_TrReady_13, -- [out std_logic]
Dbg_TrValid_13 => Dbg_TrValid_13, -- [in std_logic]
Dbg_Clk_14 => Dbg_Clk_14, -- [out std_logic]
Dbg_TDI_14 => Dbg_TDI_14, -- [out std_logic]
Dbg_TDO_14 => Dbg_TDO_14, -- [in std_logic]
Dbg_Reg_En_14 => Dbg_Reg_En_14, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_14 => Dbg_Capture_14, -- [out std_logic]
Dbg_Shift_14 => Dbg_Shift_14, -- [out std_logic]
Dbg_Update_14 => Dbg_Update_14, -- [out std_logic]
Dbg_Rst_14 => Dbg_Rst_14, -- [out std_logic]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_14 => Dbg_TrClk_14, -- [out std_logic]
Dbg_TrData_14 => Dbg_TrData_14, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_14 => Dbg_TrReady_14, -- [out std_logic]
Dbg_TrValid_14 => Dbg_TrValid_14, -- [in std_logic]
Dbg_Clk_15 => Dbg_Clk_15, -- [out std_logic]
Dbg_TDI_15 => Dbg_TDI_15, -- [out std_logic]
Dbg_TDO_15 => Dbg_TDO_15, -- [in std_logic]
Dbg_Reg_En_15 => Dbg_Reg_En_15, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_15 => Dbg_Capture_15, -- [out std_logic]
Dbg_Shift_15 => Dbg_Shift_15, -- [out std_logic]
Dbg_Update_15 => Dbg_Update_15, -- [out std_logic]
Dbg_Rst_15 => Dbg_Rst_15, -- [out std_logic]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_15 => Dbg_TrClk_15, -- [out std_logic]
Dbg_TrData_15 => Dbg_TrData_15, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_15 => Dbg_TrReady_15, -- [out std_logic]
Dbg_TrValid_15 => Dbg_TrValid_15, -- [in std_logic]
Dbg_Clk_16 => Dbg_Clk_16, -- [out std_logic]
Dbg_TDI_16 => Dbg_TDI_16, -- [out std_logic]
Dbg_TDO_16 => Dbg_TDO_16, -- [in std_logic]
Dbg_Reg_En_16 => Dbg_Reg_En_16, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_16 => Dbg_Capture_16, -- [out std_logic]
Dbg_Shift_16 => Dbg_Shift_16, -- [out std_logic]
Dbg_Update_16 => Dbg_Update_16, -- [out std_logic]
Dbg_Rst_16 => Dbg_Rst_16, -- [out std_logic]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_16 => Dbg_TrClk_16, -- [out std_logic]
Dbg_TrData_16 => Dbg_TrData_16, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_16 => Dbg_TrReady_16, -- [out std_logic]
Dbg_TrValid_16 => Dbg_TrValid_16, -- [in std_logic]
Dbg_Clk_17 => Dbg_Clk_17, -- [out std_logic]
Dbg_TDI_17 => Dbg_TDI_17, -- [out std_logic]
Dbg_TDO_17 => Dbg_TDO_17, -- [in std_logic]
Dbg_Reg_En_17 => Dbg_Reg_En_17, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_17 => Dbg_Capture_17, -- [out std_logic]
Dbg_Shift_17 => Dbg_Shift_17, -- [out std_logic]
Dbg_Update_17 => Dbg_Update_17, -- [out std_logic]
Dbg_Rst_17 => Dbg_Rst_17, -- [out std_logic]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_17 => Dbg_TrClk_17, -- [out std_logic]
Dbg_TrData_17 => Dbg_TrData_17, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_17 => Dbg_TrReady_17, -- [out std_logic]
Dbg_TrValid_17 => Dbg_TrValid_17, -- [in std_logic]
Dbg_Clk_18 => Dbg_Clk_18, -- [out std_logic]
Dbg_TDI_18 => Dbg_TDI_18, -- [out std_logic]
Dbg_TDO_18 => Dbg_TDO_18, -- [in std_logic]
Dbg_Reg_En_18 => Dbg_Reg_En_18, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_18 => Dbg_Capture_18, -- [out std_logic]
Dbg_Shift_18 => Dbg_Shift_18, -- [out std_logic]
Dbg_Update_18 => Dbg_Update_18, -- [out std_logic]
Dbg_Rst_18 => Dbg_Rst_18, -- [out std_logic]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_18 => Dbg_TrClk_18, -- [out std_logic]
Dbg_TrData_18 => Dbg_TrData_18, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_18 => Dbg_TrReady_18, -- [out std_logic]
Dbg_TrValid_18 => Dbg_TrValid_18, -- [in std_logic]
Dbg_Clk_19 => Dbg_Clk_19, -- [out std_logic]
Dbg_TDI_19 => Dbg_TDI_19, -- [out std_logic]
Dbg_TDO_19 => Dbg_TDO_19, -- [in std_logic]
Dbg_Reg_En_19 => Dbg_Reg_En_19, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_19 => Dbg_Capture_19, -- [out std_logic]
Dbg_Shift_19 => Dbg_Shift_19, -- [out std_logic]
Dbg_Update_19 => Dbg_Update_19, -- [out std_logic]
Dbg_Rst_19 => Dbg_Rst_19, -- [out std_logic]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_19 => Dbg_TrClk_19, -- [out std_logic]
Dbg_TrData_19 => Dbg_TrData_19, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_19 => Dbg_TrReady_19, -- [out std_logic]
Dbg_TrValid_19 => Dbg_TrValid_19, -- [in std_logic]
Dbg_Clk_20 => Dbg_Clk_20, -- [out std_logic]
Dbg_TDI_20 => Dbg_TDI_20, -- [out std_logic]
Dbg_TDO_20 => Dbg_TDO_20, -- [in std_logic]
Dbg_Reg_En_20 => Dbg_Reg_En_20, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_20 => Dbg_Capture_20, -- [out std_logic]
Dbg_Shift_20 => Dbg_Shift_20, -- [out std_logic]
Dbg_Update_20 => Dbg_Update_20, -- [out std_logic]
Dbg_Rst_20 => Dbg_Rst_20, -- [out std_logic]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_20 => Dbg_TrClk_20, -- [out std_logic]
Dbg_TrData_20 => Dbg_TrData_20, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_20 => Dbg_TrReady_20, -- [out std_logic]
Dbg_TrValid_20 => Dbg_TrValid_20, -- [in std_logic]
Dbg_Clk_21 => Dbg_Clk_21, -- [out std_logic]
Dbg_TDI_21 => Dbg_TDI_21, -- [out std_logic]
Dbg_TDO_21 => Dbg_TDO_21, -- [in std_logic]
Dbg_Reg_En_21 => Dbg_Reg_En_21, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_21 => Dbg_Capture_21, -- [out std_logic]
Dbg_Shift_21 => Dbg_Shift_21, -- [out std_logic]
Dbg_Update_21 => Dbg_Update_21, -- [out std_logic]
Dbg_Rst_21 => Dbg_Rst_21, -- [out std_logic]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_21 => Dbg_TrClk_21, -- [out std_logic]
Dbg_TrData_21 => Dbg_TrData_21, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_21 => Dbg_TrReady_21, -- [out std_logic]
Dbg_TrValid_21 => Dbg_TrValid_21, -- [in std_logic]
Dbg_Clk_22 => Dbg_Clk_22, -- [out std_logic]
Dbg_TDI_22 => Dbg_TDI_22, -- [out std_logic]
Dbg_TDO_22 => Dbg_TDO_22, -- [in std_logic]
Dbg_Reg_En_22 => Dbg_Reg_En_22, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_22 => Dbg_Capture_22, -- [out std_logic]
Dbg_Shift_22 => Dbg_Shift_22, -- [out std_logic]
Dbg_Update_22 => Dbg_Update_22, -- [out std_logic]
Dbg_Rst_22 => Dbg_Rst_22, -- [out std_logic]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_22 => Dbg_TrClk_22, -- [out std_logic]
Dbg_TrData_22 => Dbg_TrData_22, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_22 => Dbg_TrReady_22, -- [out std_logic]
Dbg_TrValid_22 => Dbg_TrValid_22, -- [in std_logic]
Dbg_Clk_23 => Dbg_Clk_23, -- [out std_logic]
Dbg_TDI_23 => Dbg_TDI_23, -- [out std_logic]
Dbg_TDO_23 => Dbg_TDO_23, -- [in std_logic]
Dbg_Reg_En_23 => Dbg_Reg_En_23, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_23 => Dbg_Capture_23, -- [out std_logic]
Dbg_Shift_23 => Dbg_Shift_23, -- [out std_logic]
Dbg_Update_23 => Dbg_Update_23, -- [out std_logic]
Dbg_Rst_23 => Dbg_Rst_23, -- [out std_logic]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_23 => Dbg_TrClk_23, -- [out std_logic]
Dbg_TrData_23 => Dbg_TrData_23, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_23 => Dbg_TrReady_23, -- [out std_logic]
Dbg_TrValid_23 => Dbg_TrValid_23, -- [in std_logic]
Dbg_Clk_24 => Dbg_Clk_24, -- [out std_logic]
Dbg_TDI_24 => Dbg_TDI_24, -- [out std_logic]
Dbg_TDO_24 => Dbg_TDO_24, -- [in std_logic]
Dbg_Reg_En_24 => Dbg_Reg_En_24, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_24 => Dbg_Capture_24, -- [out std_logic]
Dbg_Shift_24 => Dbg_Shift_24, -- [out std_logic]
Dbg_Update_24 => Dbg_Update_24, -- [out std_logic]
Dbg_Rst_24 => Dbg_Rst_24, -- [out std_logic]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_24 => Dbg_TrClk_24, -- [out std_logic]
Dbg_TrData_24 => Dbg_TrData_24, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_24 => Dbg_TrReady_24, -- [out std_logic]
Dbg_TrValid_24 => Dbg_TrValid_24, -- [in std_logic]
Dbg_Clk_25 => Dbg_Clk_25, -- [out std_logic]
Dbg_TDI_25 => Dbg_TDI_25, -- [out std_logic]
Dbg_TDO_25 => Dbg_TDO_25, -- [in std_logic]
Dbg_Reg_En_25 => Dbg_Reg_En_25, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_25 => Dbg_Capture_25, -- [out std_logic]
Dbg_Shift_25 => Dbg_Shift_25, -- [out std_logic]
Dbg_Update_25 => Dbg_Update_25, -- [out std_logic]
Dbg_Rst_25 => Dbg_Rst_25, -- [out std_logic]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_25 => Dbg_TrClk_25, -- [out std_logic]
Dbg_TrData_25 => Dbg_TrData_25, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_25 => Dbg_TrReady_25, -- [out std_logic]
Dbg_TrValid_25 => Dbg_TrValid_25, -- [in std_logic]
Dbg_Clk_26 => Dbg_Clk_26, -- [out std_logic]
Dbg_TDI_26 => Dbg_TDI_26, -- [out std_logic]
Dbg_TDO_26 => Dbg_TDO_26, -- [in std_logic]
Dbg_Reg_En_26 => Dbg_Reg_En_26, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_26 => Dbg_Capture_26, -- [out std_logic]
Dbg_Shift_26 => Dbg_Shift_26, -- [out std_logic]
Dbg_Update_26 => Dbg_Update_26, -- [out std_logic]
Dbg_Rst_26 => Dbg_Rst_26, -- [out std_logic]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_26 => Dbg_TrClk_26, -- [out std_logic]
Dbg_TrData_26 => Dbg_TrData_26, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_26 => Dbg_TrReady_26, -- [out std_logic]
Dbg_TrValid_26 => Dbg_TrValid_26, -- [in std_logic]
Dbg_Clk_27 => Dbg_Clk_27, -- [out std_logic]
Dbg_TDI_27 => Dbg_TDI_27, -- [out std_logic]
Dbg_TDO_27 => Dbg_TDO_27, -- [in std_logic]
Dbg_Reg_En_27 => Dbg_Reg_En_27, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_27 => Dbg_Capture_27, -- [out std_logic]
Dbg_Shift_27 => Dbg_Shift_27, -- [out std_logic]
Dbg_Update_27 => Dbg_Update_27, -- [out std_logic]
Dbg_Rst_27 => Dbg_Rst_27, -- [out std_logic]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_27 => Dbg_TrClk_27, -- [out std_logic]
Dbg_TrData_27 => Dbg_TrData_27, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_27 => Dbg_TrReady_27, -- [out std_logic]
Dbg_TrValid_27 => Dbg_TrValid_27, -- [in std_logic]
Dbg_Clk_28 => Dbg_Clk_28, -- [out std_logic]
Dbg_TDI_28 => Dbg_TDI_28, -- [out std_logic]
Dbg_TDO_28 => Dbg_TDO_28, -- [in std_logic]
Dbg_Reg_En_28 => Dbg_Reg_En_28, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_28 => Dbg_Capture_28, -- [out std_logic]
Dbg_Shift_28 => Dbg_Shift_28, -- [out std_logic]
Dbg_Update_28 => Dbg_Update_28, -- [out std_logic]
Dbg_Rst_28 => Dbg_Rst_28, -- [out std_logic]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_28 => Dbg_TrClk_28, -- [out std_logic]
Dbg_TrData_28 => Dbg_TrData_28, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_28 => Dbg_TrReady_28, -- [out std_logic]
Dbg_TrValid_28 => Dbg_TrValid_28, -- [in std_logic]
Dbg_Clk_29 => Dbg_Clk_29, -- [out std_logic]
Dbg_TDI_29 => Dbg_TDI_29, -- [out std_logic]
Dbg_TDO_29 => Dbg_TDO_29, -- [in std_logic]
Dbg_Reg_En_29 => Dbg_Reg_En_29, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_29 => Dbg_Capture_29, -- [out std_logic]
Dbg_Shift_29 => Dbg_Shift_29, -- [out std_logic]
Dbg_Update_29 => Dbg_Update_29, -- [out std_logic]
Dbg_Rst_29 => Dbg_Rst_29, -- [out std_logic]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_29 => Dbg_TrClk_29, -- [out std_logic]
Dbg_TrData_29 => Dbg_TrData_29, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_29 => Dbg_TrReady_29, -- [out std_logic]
Dbg_TrValid_29 => Dbg_TrValid_29, -- [in std_logic]
Dbg_Clk_30 => Dbg_Clk_30, -- [out std_logic]
Dbg_TDI_30 => Dbg_TDI_30, -- [out std_logic]
Dbg_TDO_30 => Dbg_TDO_30, -- [in std_logic]
Dbg_Reg_En_30 => Dbg_Reg_En_30, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_30 => Dbg_Capture_30, -- [out std_logic]
Dbg_Shift_30 => Dbg_Shift_30, -- [out std_logic]
Dbg_Update_30 => Dbg_Update_30, -- [out std_logic]
Dbg_Rst_30 => Dbg_Rst_30, -- [out std_logic]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_30 => Dbg_TrClk_30, -- [out std_logic]
Dbg_TrData_30 => Dbg_TrData_30, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_30 => Dbg_TrReady_30, -- [out std_logic]
Dbg_TrValid_30 => Dbg_TrValid_30, -- [in std_logic]
Dbg_Clk_31 => Dbg_Clk_31, -- [out std_logic]
Dbg_TDI_31 => Dbg_TDI_31, -- [out std_logic]
Dbg_TDO_31 => Dbg_TDO_31, -- [in std_logic]
Dbg_Reg_En_31 => Dbg_Reg_En_31, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_31 => Dbg_Capture_31, -- [out std_logic]
Dbg_Shift_31 => Dbg_Shift_31, -- [out std_logic]
Dbg_Update_31 => Dbg_Update_31, -- [out std_logic]
Dbg_Rst_31 => Dbg_Rst_31, -- [out std_logic]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_31 => Dbg_TrClk_31, -- [out std_logic]
Dbg_TrData_31 => Dbg_TrData_31, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_31 => Dbg_TrReady_31, -- [out std_logic]
Dbg_TrValid_31 => Dbg_TrValid_31, -- [in std_logic]
Ext_Trig_In => ext_trig_in, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => ext_trig_ack_in, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => ext_trig_out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => ext_trig_ack_out, -- [in std_logic_vector(0 to 3)]
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
ext_trig_in <= Trig_In_0 & Trig_In_1 & Trig_In_2 & Trig_In_3;
ext_trig_ack_out <= Trig_Ack_Out_0 & Trig_Ack_Out_1 & Trig_Ack_Out_2 & Trig_Ack_Out_3;
Trig_Ack_In_0 <= ext_trig_ack_in(0);
Trig_Ack_In_1 <= ext_trig_ack_in(1);
Trig_Ack_In_2 <= ext_trig_ack_in(2);
Trig_Ack_In_3 <= ext_trig_ack_in(3);
Trig_Out_0 <= ext_trig_out(0);
Trig_Out_1 <= ext_trig_out(1);
Trig_Out_2 <= ext_trig_out(2);
Trig_Out_3 <= ext_trig_out(3);
-- Bus Master port
Use_Bus_MASTER : if (C_DBG_MEM_ACCESS = 1) generate
type LMB_vec_type is array (natural range <>) of std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_addr : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_write : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_addr_strobe : std_logic;
signal lmb_read_strobe : std_logic;
signal lmb_write_strobe : std_logic;
signal lmb_ready : std_logic;
signal lmb_wait : std_logic;
signal lmb_ue : std_logic;
signal lmb_byte_enable : std_logic_vector(0 to C_DATA_SIZE / 8 - 1);
signal lmb_addr_strobe_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec : LMB_vec_type(0 to 31);
signal lmb_ready_vec : std_logic_vector(0 to 31);
signal lmb_wait_vec : std_logic_vector(0 to 31);
signal lmb_ue_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec_q : LMB_vec_type(0 to C_EN_WIDTH - 1);
signal lmb_ready_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_wait_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_ue_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => true,
C_HAS_DIRECT_PORT => C_TRACE_AXI_MASTER
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => lmb_data_addr,
LMB_Data_Read => lmb_data_read,
LMB_Data_Write => lmb_data_write,
LMB_Addr_Strobe => lmb_addr_strobe,
LMB_Read_Strobe => lmb_read_strobe,
LMB_Write_Strobe => lmb_write_strobe,
LMB_Ready => lmb_ready,
LMB_Wait => lmb_wait,
LMB_UE => lmb_ue,
LMB_Byte_Enable => lmb_byte_enable,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
Generate_LMB_Outputs : process (mb_debug_enabled, lmb_addr_strobe)
begin -- process Generate_LMB_Outputs
lmb_addr_strobe_vec <= (others => '0');
for I in 0 to C_EN_WIDTH - 1 loop
lmb_addr_strobe_vec(I) <= lmb_addr_strobe and mb_debug_enabled(I);
end loop;
end process Generate_LMB_Outputs;
LMB_Addr_Strobe_0 <= lmb_addr_strobe_vec(0);
LMB_Addr_Strobe_1 <= lmb_addr_strobe_vec(1);
LMB_Addr_Strobe_2 <= lmb_addr_strobe_vec(2);
LMB_Addr_Strobe_3 <= lmb_addr_strobe_vec(3);
LMB_Addr_Strobe_4 <= lmb_addr_strobe_vec(4);
LMB_Addr_Strobe_5 <= lmb_addr_strobe_vec(5);
LMB_Addr_Strobe_6 <= lmb_addr_strobe_vec(6);
LMB_Addr_Strobe_7 <= lmb_addr_strobe_vec(7);
LMB_Addr_Strobe_8 <= lmb_addr_strobe_vec(8);
LMB_Addr_Strobe_9 <= lmb_addr_strobe_vec(9);
LMB_Addr_Strobe_10 <= lmb_addr_strobe_vec(10);
LMB_Addr_Strobe_11 <= lmb_addr_strobe_vec(11);
LMB_Addr_Strobe_12 <= lmb_addr_strobe_vec(12);
LMB_Addr_Strobe_13 <= lmb_addr_strobe_vec(13);
LMB_Addr_Strobe_14 <= lmb_addr_strobe_vec(14);
LMB_Addr_Strobe_15 <= lmb_addr_strobe_vec(15);
LMB_Addr_Strobe_16 <= lmb_addr_strobe_vec(16);
LMB_Addr_Strobe_17 <= lmb_addr_strobe_vec(17);
LMB_Addr_Strobe_18 <= lmb_addr_strobe_vec(18);
LMB_Addr_Strobe_19 <= lmb_addr_strobe_vec(19);
LMB_Addr_Strobe_20 <= lmb_addr_strobe_vec(20);
LMB_Addr_Strobe_21 <= lmb_addr_strobe_vec(21);
LMB_Addr_Strobe_22 <= lmb_addr_strobe_vec(22);
LMB_Addr_Strobe_23 <= lmb_addr_strobe_vec(23);
LMB_Addr_Strobe_24 <= lmb_addr_strobe_vec(24);
LMB_Addr_Strobe_25 <= lmb_addr_strobe_vec(25);
LMB_Addr_Strobe_26 <= lmb_addr_strobe_vec(26);
LMB_Addr_Strobe_27 <= lmb_addr_strobe_vec(27);
LMB_Addr_Strobe_28 <= lmb_addr_strobe_vec(28);
LMB_Addr_Strobe_29 <= lmb_addr_strobe_vec(29);
LMB_Addr_Strobe_30 <= lmb_addr_strobe_vec(30);
LMB_Addr_Strobe_31 <= lmb_addr_strobe_vec(31);
LMB_Data_Addr_0 <= lmb_data_addr;
LMB_Data_Addr_1 <= lmb_data_addr;
LMB_Data_Addr_2 <= lmb_data_addr;
LMB_Data_Addr_3 <= lmb_data_addr;
LMB_Data_Addr_4 <= lmb_data_addr;
LMB_Data_Addr_5 <= lmb_data_addr;
LMB_Data_Addr_6 <= lmb_data_addr;
LMB_Data_Addr_7 <= lmb_data_addr;
LMB_Data_Addr_8 <= lmb_data_addr;
LMB_Data_Addr_9 <= lmb_data_addr;
LMB_Data_Addr_10 <= lmb_data_addr;
LMB_Data_Addr_11 <= lmb_data_addr;
LMB_Data_Addr_12 <= lmb_data_addr;
LMB_Data_Addr_13 <= lmb_data_addr;
LMB_Data_Addr_14 <= lmb_data_addr;
LMB_Data_Addr_15 <= lmb_data_addr;
LMB_Data_Addr_16 <= lmb_data_addr;
LMB_Data_Addr_17 <= lmb_data_addr;
LMB_Data_Addr_18 <= lmb_data_addr;
LMB_Data_Addr_19 <= lmb_data_addr;
LMB_Data_Addr_20 <= lmb_data_addr;
LMB_Data_Addr_21 <= lmb_data_addr;
LMB_Data_Addr_22 <= lmb_data_addr;
LMB_Data_Addr_23 <= lmb_data_addr;
LMB_Data_Addr_24 <= lmb_data_addr;
LMB_Data_Addr_25 <= lmb_data_addr;
LMB_Data_Addr_26 <= lmb_data_addr;
LMB_Data_Addr_27 <= lmb_data_addr;
LMB_Data_Addr_28 <= lmb_data_addr;
LMB_Data_Addr_29 <= lmb_data_addr;
LMB_Data_Addr_30 <= lmb_data_addr;
LMB_Data_Addr_31 <= lmb_data_addr;
LMB_Data_write_0 <= lmb_data_write;
LMB_Data_write_1 <= lmb_data_write;
LMB_Data_write_2 <= lmb_data_write;
LMB_Data_write_3 <= lmb_data_write;
LMB_Data_write_4 <= lmb_data_write;
LMB_Data_write_5 <= lmb_data_write;
LMB_Data_write_6 <= lmb_data_write;
LMB_Data_write_7 <= lmb_data_write;
LMB_Data_write_8 <= lmb_data_write;
LMB_Data_write_9 <= lmb_data_write;
LMB_Data_write_10 <= lmb_data_write;
LMB_Data_write_11 <= lmb_data_write;
LMB_Data_write_12 <= lmb_data_write;
LMB_Data_write_13 <= lmb_data_write;
LMB_Data_write_14 <= lmb_data_write;
LMB_Data_write_15 <= lmb_data_write;
LMB_Data_write_16 <= lmb_data_write;
LMB_Data_write_17 <= lmb_data_write;
LMB_Data_write_18 <= lmb_data_write;
LMB_Data_write_19 <= lmb_data_write;
LMB_Data_write_20 <= lmb_data_write;
LMB_Data_write_21 <= lmb_data_write;
LMB_Data_write_22 <= lmb_data_write;
LMB_Data_write_23 <= lmb_data_write;
LMB_Data_write_24 <= lmb_data_write;
LMB_Data_write_25 <= lmb_data_write;
LMB_Data_write_26 <= lmb_data_write;
LMB_Data_write_27 <= lmb_data_write;
LMB_Data_write_28 <= lmb_data_write;
LMB_Data_write_29 <= lmb_data_write;
LMB_Data_write_30 <= lmb_data_write;
LMB_Data_write_31 <= lmb_data_write;
LMB_Read_strobe_0 <= lmb_read_strobe;
LMB_Read_strobe_1 <= lmb_read_strobe;
LMB_Read_strobe_2 <= lmb_read_strobe;
LMB_Read_strobe_3 <= lmb_read_strobe;
LMB_Read_strobe_4 <= lmb_read_strobe;
LMB_Read_strobe_5 <= lmb_read_strobe;
LMB_Read_strobe_6 <= lmb_read_strobe;
LMB_Read_strobe_7 <= lmb_read_strobe;
LMB_Read_strobe_8 <= lmb_read_strobe;
LMB_Read_strobe_9 <= lmb_read_strobe;
LMB_Read_strobe_10 <= lmb_read_strobe;
LMB_Read_strobe_11 <= lmb_read_strobe;
LMB_Read_strobe_12 <= lmb_read_strobe;
LMB_Read_strobe_13 <= lmb_read_strobe;
LMB_Read_strobe_14 <= lmb_read_strobe;
LMB_Read_strobe_15 <= lmb_read_strobe;
LMB_Read_strobe_16 <= lmb_read_strobe;
LMB_Read_strobe_17 <= lmb_read_strobe;
LMB_Read_strobe_18 <= lmb_read_strobe;
LMB_Read_strobe_19 <= lmb_read_strobe;
LMB_Read_strobe_20 <= lmb_read_strobe;
LMB_Read_strobe_21 <= lmb_read_strobe;
LMB_Read_strobe_22 <= lmb_read_strobe;
LMB_Read_strobe_23 <= lmb_read_strobe;
LMB_Read_strobe_24 <= lmb_read_strobe;
LMB_Read_strobe_25 <= lmb_read_strobe;
LMB_Read_strobe_26 <= lmb_read_strobe;
LMB_Read_strobe_27 <= lmb_read_strobe;
LMB_Read_strobe_28 <= lmb_read_strobe;
LMB_Read_strobe_29 <= lmb_read_strobe;
LMB_Read_strobe_30 <= lmb_read_strobe;
LMB_Read_strobe_31 <= lmb_read_strobe;
LMB_Write_strobe_0 <= lmb_write_strobe;
LMB_Write_strobe_1 <= lmb_write_strobe;
LMB_Write_strobe_2 <= lmb_write_strobe;
LMB_Write_strobe_3 <= lmb_write_strobe;
LMB_Write_strobe_4 <= lmb_write_strobe;
LMB_Write_strobe_5 <= lmb_write_strobe;
LMB_Write_strobe_6 <= lmb_write_strobe;
LMB_Write_strobe_7 <= lmb_write_strobe;
LMB_Write_strobe_8 <= lmb_write_strobe;
LMB_Write_strobe_9 <= lmb_write_strobe;
LMB_Write_strobe_10 <= lmb_write_strobe;
LMB_Write_strobe_11 <= lmb_write_strobe;
LMB_Write_strobe_12 <= lmb_write_strobe;
LMB_Write_strobe_13 <= lmb_write_strobe;
LMB_Write_strobe_14 <= lmb_write_strobe;
LMB_Write_strobe_15 <= lmb_write_strobe;
LMB_Write_strobe_16 <= lmb_write_strobe;
LMB_Write_strobe_17 <= lmb_write_strobe;
LMB_Write_strobe_18 <= lmb_write_strobe;
LMB_Write_strobe_19 <= lmb_write_strobe;
LMB_Write_strobe_20 <= lmb_write_strobe;
LMB_Write_strobe_21 <= lmb_write_strobe;
LMB_Write_strobe_22 <= lmb_write_strobe;
LMB_Write_strobe_23 <= lmb_write_strobe;
LMB_Write_strobe_24 <= lmb_write_strobe;
LMB_Write_strobe_25 <= lmb_write_strobe;
LMB_Write_strobe_26 <= lmb_write_strobe;
LMB_Write_strobe_27 <= lmb_write_strobe;
LMB_Write_strobe_28 <= lmb_write_strobe;
LMB_Write_strobe_29 <= lmb_write_strobe;
LMB_Write_strobe_30 <= lmb_write_strobe;
LMB_Write_strobe_31 <= lmb_write_strobe;
LMB_Byte_enable_0 <= lmb_byte_enable;
LMB_Byte_enable_1 <= lmb_byte_enable;
LMB_Byte_enable_2 <= lmb_byte_enable;
LMB_Byte_enable_3 <= lmb_byte_enable;
LMB_Byte_enable_4 <= lmb_byte_enable;
LMB_Byte_enable_5 <= lmb_byte_enable;
LMB_Byte_enable_6 <= lmb_byte_enable;
LMB_Byte_enable_7 <= lmb_byte_enable;
LMB_Byte_enable_8 <= lmb_byte_enable;
LMB_Byte_enable_9 <= lmb_byte_enable;
LMB_Byte_enable_10 <= lmb_byte_enable;
LMB_Byte_enable_11 <= lmb_byte_enable;
LMB_Byte_enable_12 <= lmb_byte_enable;
LMB_Byte_enable_13 <= lmb_byte_enable;
LMB_Byte_enable_14 <= lmb_byte_enable;
LMB_Byte_enable_15 <= lmb_byte_enable;
LMB_Byte_enable_16 <= lmb_byte_enable;
LMB_Byte_enable_17 <= lmb_byte_enable;
LMB_Byte_enable_18 <= lmb_byte_enable;
LMB_Byte_enable_19 <= lmb_byte_enable;
LMB_Byte_enable_20 <= lmb_byte_enable;
LMB_Byte_enable_21 <= lmb_byte_enable;
LMB_Byte_enable_22 <= lmb_byte_enable;
LMB_Byte_enable_23 <= lmb_byte_enable;
LMB_Byte_enable_24 <= lmb_byte_enable;
LMB_Byte_enable_25 <= lmb_byte_enable;
LMB_Byte_enable_26 <= lmb_byte_enable;
LMB_Byte_enable_27 <= lmb_byte_enable;
LMB_Byte_enable_28 <= lmb_byte_enable;
LMB_Byte_enable_29 <= lmb_byte_enable;
LMB_Byte_enable_30 <= lmb_byte_enable;
LMB_Byte_enable_31 <= lmb_byte_enable;
Generate_LMB_Inputs : process (mb_debug_enabled, lmb_data_read_vec_q, lmb_ready_vec_q, lmb_wait_vec_q, lmb_ue_vec_q)
variable data_mask : std_logic_vector(0 to C_DATA_SIZE - 1);
variable data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
variable ready : std_logic;
variable wait_i : std_logic;
variable ue : std_logic;
begin -- process Generate_LMB_Inputs
data_read := (others => '0');
ready := '0';
wait_i := '0';
ue := '0';
for I in 0 to C_EN_WIDTH - 1 loop
data_mask := (0 to C_DATA_SIZE - 1 => mb_debug_enabled(I));
data_read := data_read or (lmb_data_read_vec_q(I) and data_mask);
ready := ready or (lmb_ready_vec_q(I) and mb_debug_enabled(I));
wait_i := wait_i or (lmb_wait_vec_q(I) and mb_debug_enabled(I));
ue := ue or (lmb_ue_vec_q(I) and mb_debug_enabled(I));
end loop;
lmb_data_read <= data_read;
lmb_ready <= ready;
lmb_wait <= wait_i;
lmb_ue <= ue;
end process Generate_LMB_Inputs;
Clock_LMB_Inputs : process (M_AXI_ACLK)
begin
if M_AXI_ACLK'event and M_AXI_ACLK = '1' then -- rising clock edge
for I in 0 to C_EN_WIDTH - 1 loop
lmb_data_read_vec_q(I) <= lmb_data_read_vec(I);
lmb_ready_vec_q(I) <= lmb_ready_vec(I);
lmb_wait_vec_q(I) <= lmb_wait_vec(I);
lmb_ue_vec_q(I) <= lmb_ue_vec(I);
end loop;
end if;
end process Clock_LMB_Inputs;
lmb_data_read_vec(0) <= LMB_Data_Read_0;
lmb_data_read_vec(1) <= LMB_Data_Read_1;
lmb_data_read_vec(2) <= LMB_Data_Read_2;
lmb_data_read_vec(3) <= LMB_Data_Read_3;
lmb_data_read_vec(4) <= LMB_Data_Read_4;
lmb_data_read_vec(5) <= LMB_Data_Read_5;
lmb_data_read_vec(6) <= LMB_Data_Read_6;
lmb_data_read_vec(7) <= LMB_Data_Read_7;
lmb_data_read_vec(8) <= LMB_Data_Read_8;
lmb_data_read_vec(9) <= LMB_Data_Read_9;
lmb_data_read_vec(10) <= LMB_Data_Read_10;
lmb_data_read_vec(11) <= LMB_Data_Read_11;
lmb_data_read_vec(12) <= LMB_Data_Read_12;
lmb_data_read_vec(13) <= LMB_Data_Read_13;
lmb_data_read_vec(14) <= LMB_Data_Read_14;
lmb_data_read_vec(15) <= LMB_Data_Read_15;
lmb_data_read_vec(16) <= LMB_Data_Read_16;
lmb_data_read_vec(17) <= LMB_Data_Read_17;
lmb_data_read_vec(18) <= LMB_Data_Read_18;
lmb_data_read_vec(19) <= LMB_Data_Read_19;
lmb_data_read_vec(20) <= LMB_Data_Read_20;
lmb_data_read_vec(21) <= LMB_Data_Read_21;
lmb_data_read_vec(22) <= LMB_Data_Read_22;
lmb_data_read_vec(23) <= LMB_Data_Read_23;
lmb_data_read_vec(24) <= LMB_Data_Read_24;
lmb_data_read_vec(25) <= LMB_Data_Read_25;
lmb_data_read_vec(26) <= LMB_Data_Read_26;
lmb_data_read_vec(27) <= LMB_Data_Read_27;
lmb_data_read_vec(28) <= LMB_Data_Read_28;
lmb_data_read_vec(29) <= LMB_Data_Read_29;
lmb_data_read_vec(30) <= LMB_Data_Read_30;
lmb_data_read_vec(31) <= LMB_Data_Read_31;
lmb_ready_vec(0) <= LMB_Ready_0;
lmb_ready_vec(1) <= LMB_Ready_1;
lmb_ready_vec(2) <= LMB_Ready_2;
lmb_ready_vec(3) <= LMB_Ready_3;
lmb_ready_vec(4) <= LMB_Ready_4;
lmb_ready_vec(5) <= LMB_Ready_5;
lmb_ready_vec(6) <= LMB_Ready_6;
lmb_ready_vec(7) <= LMB_Ready_7;
lmb_ready_vec(8) <= LMB_Ready_8;
lmb_ready_vec(9) <= LMB_Ready_9;
lmb_ready_vec(10) <= LMB_Ready_10;
lmb_ready_vec(11) <= LMB_Ready_11;
lmb_ready_vec(12) <= LMB_Ready_12;
lmb_ready_vec(13) <= LMB_Ready_13;
lmb_ready_vec(14) <= LMB_Ready_14;
lmb_ready_vec(15) <= LMB_Ready_15;
lmb_ready_vec(16) <= LMB_Ready_16;
lmb_ready_vec(17) <= LMB_Ready_17;
lmb_ready_vec(18) <= LMB_Ready_18;
lmb_ready_vec(19) <= LMB_Ready_19;
lmb_ready_vec(20) <= LMB_Ready_20;
lmb_ready_vec(21) <= LMB_Ready_21;
lmb_ready_vec(22) <= LMB_Ready_22;
lmb_ready_vec(23) <= LMB_Ready_23;
lmb_ready_vec(24) <= LMB_Ready_24;
lmb_ready_vec(25) <= LMB_Ready_25;
lmb_ready_vec(26) <= LMB_Ready_26;
lmb_ready_vec(27) <= LMB_Ready_27;
lmb_ready_vec(28) <= LMB_Ready_28;
lmb_ready_vec(29) <= LMB_Ready_29;
lmb_ready_vec(30) <= LMB_Ready_30;
lmb_ready_vec(31) <= LMB_Ready_31;
lmb_wait_vec(0) <= LMB_Wait_0;
lmb_wait_vec(1) <= LMB_Wait_1;
lmb_wait_vec(2) <= LMB_Wait_2;
lmb_wait_vec(3) <= LMB_Wait_3;
lmb_wait_vec(4) <= LMB_Wait_4;
lmb_wait_vec(5) <= LMB_Wait_5;
lmb_wait_vec(6) <= LMB_Wait_6;
lmb_wait_vec(7) <= LMB_Wait_7;
lmb_wait_vec(8) <= LMB_Wait_8;
lmb_wait_vec(9) <= LMB_Wait_9;
lmb_wait_vec(10) <= LMB_Wait_10;
lmb_wait_vec(11) <= LMB_Wait_11;
lmb_wait_vec(12) <= LMB_Wait_12;
lmb_wait_vec(13) <= LMB_Wait_13;
lmb_wait_vec(14) <= LMB_Wait_14;
lmb_wait_vec(15) <= LMB_Wait_15;
lmb_wait_vec(16) <= LMB_Wait_16;
lmb_wait_vec(17) <= LMB_Wait_17;
lmb_wait_vec(18) <= LMB_Wait_18;
lmb_wait_vec(19) <= LMB_Wait_19;
lmb_wait_vec(20) <= LMB_Wait_20;
lmb_wait_vec(21) <= LMB_Wait_21;
lmb_wait_vec(22) <= LMB_Wait_22;
lmb_wait_vec(23) <= LMB_Wait_23;
lmb_wait_vec(24) <= LMB_Wait_24;
lmb_wait_vec(25) <= LMB_Wait_25;
lmb_wait_vec(26) <= LMB_Wait_26;
lmb_wait_vec(27) <= LMB_Wait_27;
lmb_wait_vec(28) <= LMB_Wait_28;
lmb_wait_vec(29) <= LMB_Wait_29;
lmb_wait_vec(30) <= LMB_Wait_30;
lmb_wait_vec(31) <= LMB_Wait_31;
lmb_ue_vec(0) <= LMB_UE_0;
lmb_ue_vec(1) <= LMB_UE_1;
lmb_ue_vec(2) <= LMB_UE_2;
lmb_ue_vec(3) <= LMB_UE_3;
lmb_ue_vec(4) <= LMB_UE_4;
lmb_ue_vec(5) <= LMB_UE_5;
lmb_ue_vec(6) <= LMB_UE_6;
lmb_ue_vec(7) <= LMB_UE_7;
lmb_ue_vec(8) <= LMB_UE_8;
lmb_ue_vec(9) <= LMB_UE_9;
lmb_ue_vec(10) <= LMB_UE_10;
lmb_ue_vec(11) <= LMB_UE_11;
lmb_ue_vec(12) <= LMB_UE_12;
lmb_ue_vec(13) <= LMB_UE_13;
lmb_ue_vec(14) <= LMB_UE_14;
lmb_ue_vec(15) <= LMB_UE_15;
lmb_ue_vec(16) <= LMB_UE_16;
lmb_ue_vec(17) <= LMB_UE_17;
lmb_ue_vec(18) <= LMB_UE_18;
lmb_ue_vec(19) <= LMB_UE_19;
lmb_ue_vec(20) <= LMB_UE_20;
lmb_ue_vec(21) <= LMB_UE_21;
lmb_ue_vec(22) <= LMB_UE_22;
lmb_ue_vec(23) <= LMB_UE_23;
lmb_ue_vec(24) <= LMB_UE_24;
lmb_ue_vec(25) <= LMB_UE_25;
lmb_ue_vec(26) <= LMB_UE_26;
lmb_ue_vec(27) <= LMB_UE_27;
lmb_ue_vec(28) <= LMB_UE_28;
lmb_ue_vec(29) <= LMB_UE_29;
lmb_ue_vec(30) <= LMB_UE_30;
lmb_ue_vec(31) <= LMB_UE_31;
end generate Use_Bus_MASTER;
Use_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and C_TRACE_AXI_MASTER) generate
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => false,
C_HAS_DIRECT_PORT => true
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => open,
LMB_Data_Read => (others => '0'),
LMB_Data_Write => open,
LMB_Addr_Strobe => open,
LMB_Read_Strobe => open,
LMB_Write_Strobe => open,
LMB_Ready => '0',
LMB_Wait => '0',
LMB_UE => '0',
LMB_Byte_Enable => open,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
end generate Use_Bus_MASTER_AXI;
No_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and not C_TRACE_AXI_MASTER) generate
begin
master_rd_idle <= '1';
master_rd_resp <= "00";
master_wr_idle <= '1';
master_wr_resp <= "00";
master_data_out <= (others => '0');
master_data_exists <= '0';
master_data_empty <= '1';
master_dwr_next <= '0';
master_dwr_done <= '0';
master_dwr_resp <= (others => '0');
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= (others => '0');
M_AXI_AWLEN <= (others => '0');
M_AXI_AWSIZE <= (others => '0');
M_AXI_AWBURST <= (others => '0');
M_AXI_AWLOCK <= '0';
M_AXI_AWCACHE <= (others => '0');
M_AXI_AWPROT <= (others => '0');
M_AXI_AWQOS <= (others => '0');
M_AXI_AWVALID <= '0';
M_AXI_WDATA <= (others => '0');
M_AXI_WSTRB <= (others => '0');
M_AXI_WLAST <= '0';
M_AXI_WVALID <= '0';
M_AXI_BREADY <= '0';
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= (others => '0');
M_AXI_ARBURST <= (others => '0');
M_AXI_ARLOCK <= '0';
M_AXI_ARCACHE <= (others => '0');
M_AXI_ARPROT <= (others => '0');
M_AXI_ARQOS <= (others => '0');
M_AXI_ARVALID <= '0';
M_AXI_RREADY <= '0';
end generate No_Bus_MASTER_AXI;
No_Bus_MASTER_LMB : if (C_DBG_MEM_ACCESS = 0) generate
begin
LMB_Data_Addr_0 <= (others => '0');
LMB_Data_Write_0 <= (others => '0');
LMB_Addr_Strobe_0 <= '0';
LMB_Read_Strobe_0 <= '0';
LMB_Write_Strobe_0 <= '0';
LMB_Byte_Enable_0 <= (others => '0');
LMB_Data_Addr_1 <= (others => '0');
LMB_Data_Write_1 <= (others => '0');
LMB_Addr_Strobe_1 <= '0';
LMB_Read_Strobe_1 <= '0';
LMB_Write_Strobe_1 <= '0';
LMB_Byte_Enable_1 <= (others => '0');
LMB_Data_Addr_2 <= (others => '0');
LMB_Data_Write_2 <= (others => '0');
LMB_Addr_Strobe_2 <= '0';
LMB_Read_Strobe_2 <= '0';
LMB_Write_Strobe_2 <= '0';
LMB_Byte_Enable_2 <= (others => '0');
LMB_Data_Addr_3 <= (others => '0');
LMB_Data_Write_3 <= (others => '0');
LMB_Addr_Strobe_3 <= '0';
LMB_Read_Strobe_3 <= '0';
LMB_Write_Strobe_3 <= '0';
LMB_Byte_Enable_3 <= (others => '0');
LMB_Data_Addr_4 <= (others => '0');
LMB_Data_Write_4 <= (others => '0');
LMB_Addr_Strobe_4 <= '0';
LMB_Read_Strobe_4 <= '0';
LMB_Write_Strobe_4 <= '0';
LMB_Byte_Enable_4 <= (others => '0');
LMB_Data_Addr_5 <= (others => '0');
LMB_Data_Write_5 <= (others => '0');
LMB_Addr_Strobe_5 <= '0';
LMB_Read_Strobe_5 <= '0';
LMB_Write_Strobe_5 <= '0';
LMB_Byte_Enable_5 <= (others => '0');
LMB_Data_Addr_6 <= (others => '0');
LMB_Data_Write_6 <= (others => '0');
LMB_Addr_Strobe_6 <= '0';
LMB_Read_Strobe_6 <= '0';
LMB_Write_Strobe_6 <= '0';
LMB_Byte_Enable_6 <= (others => '0');
LMB_Data_Addr_7 <= (others => '0');
LMB_Data_Write_7 <= (others => '0');
LMB_Addr_Strobe_7 <= '0';
LMB_Read_Strobe_7 <= '0';
LMB_Write_Strobe_7 <= '0';
LMB_Byte_Enable_7 <= (others => '0');
LMB_Data_Addr_8 <= (others => '0');
LMB_Data_Write_8 <= (others => '0');
LMB_Addr_Strobe_8 <= '0';
LMB_Read_Strobe_8 <= '0';
LMB_Write_Strobe_8 <= '0';
LMB_Byte_Enable_8 <= (others => '0');
LMB_Data_Addr_9 <= (others => '0');
LMB_Data_Write_9 <= (others => '0');
LMB_Addr_Strobe_9 <= '0';
LMB_Read_Strobe_9 <= '0';
LMB_Write_Strobe_9 <= '0';
LMB_Byte_Enable_9 <= (others => '0');
LMB_Data_Addr_10 <= (others => '0');
LMB_Data_Write_10 <= (others => '0');
LMB_Addr_Strobe_10 <= '0';
LMB_Read_Strobe_10 <= '0';
LMB_Write_Strobe_10 <= '0';
LMB_Byte_Enable_10 <= (others => '0');
LMB_Data_Addr_11 <= (others => '0');
LMB_Data_Write_11 <= (others => '0');
LMB_Addr_Strobe_11 <= '0';
LMB_Read_Strobe_11 <= '0';
LMB_Write_Strobe_11 <= '0';
LMB_Byte_Enable_11 <= (others => '0');
LMB_Data_Addr_12 <= (others => '0');
LMB_Data_Write_12 <= (others => '0');
LMB_Addr_Strobe_12 <= '0';
LMB_Read_Strobe_12 <= '0';
LMB_Write_Strobe_12 <= '0';
LMB_Byte_Enable_12 <= (others => '0');
LMB_Data_Addr_13 <= (others => '0');
LMB_Data_Write_13 <= (others => '0');
LMB_Addr_Strobe_13 <= '0';
LMB_Read_Strobe_13 <= '0';
LMB_Write_Strobe_13 <= '0';
LMB_Byte_Enable_13 <= (others => '0');
LMB_Data_Addr_14 <= (others => '0');
LMB_Data_Write_14 <= (others => '0');
LMB_Addr_Strobe_14 <= '0';
LMB_Read_Strobe_14 <= '0';
LMB_Write_Strobe_14 <= '0';
LMB_Byte_Enable_14 <= (others => '0');
LMB_Data_Addr_15 <= (others => '0');
LMB_Data_Write_15 <= (others => '0');
LMB_Addr_Strobe_15 <= '0';
LMB_Read_Strobe_15 <= '0';
LMB_Write_Strobe_15 <= '0';
LMB_Byte_Enable_15 <= (others => '0');
LMB_Data_Addr_16 <= (others => '0');
LMB_Data_Write_16 <= (others => '0');
LMB_Addr_Strobe_16 <= '0';
LMB_Read_Strobe_16 <= '0';
LMB_Write_Strobe_16 <= '0';
LMB_Byte_Enable_16 <= (others => '0');
LMB_Data_Addr_17 <= (others => '0');
LMB_Data_Write_17 <= (others => '0');
LMB_Addr_Strobe_17 <= '0';
LMB_Read_Strobe_17 <= '0';
LMB_Write_Strobe_17 <= '0';
LMB_Byte_Enable_17 <= (others => '0');
LMB_Data_Addr_18 <= (others => '0');
LMB_Data_Write_18 <= (others => '0');
LMB_Addr_Strobe_18 <= '0';
LMB_Read_Strobe_18 <= '0';
LMB_Write_Strobe_18 <= '0';
LMB_Byte_Enable_18 <= (others => '0');
LMB_Data_Addr_19 <= (others => '0');
LMB_Data_Write_19 <= (others => '0');
LMB_Addr_Strobe_19 <= '0';
LMB_Read_Strobe_19 <= '0';
LMB_Write_Strobe_19 <= '0';
LMB_Byte_Enable_19 <= (others => '0');
LMB_Data_Addr_20 <= (others => '0');
LMB_Data_Write_20 <= (others => '0');
LMB_Addr_Strobe_20 <= '0';
LMB_Read_Strobe_20 <= '0';
LMB_Write_Strobe_20 <= '0';
LMB_Byte_Enable_20 <= (others => '0');
LMB_Data_Addr_21 <= (others => '0');
LMB_Data_Write_21 <= (others => '0');
LMB_Addr_Strobe_21 <= '0';
LMB_Read_Strobe_21 <= '0';
LMB_Write_Strobe_21 <= '0';
LMB_Byte_Enable_21 <= (others => '0');
LMB_Data_Addr_22 <= (others => '0');
LMB_Data_Write_22 <= (others => '0');
LMB_Addr_Strobe_22 <= '0';
LMB_Read_Strobe_22 <= '0';
LMB_Write_Strobe_22 <= '0';
LMB_Byte_Enable_22 <= (others => '0');
LMB_Data_Addr_23 <= (others => '0');
LMB_Data_Write_23 <= (others => '0');
LMB_Addr_Strobe_23 <= '0';
LMB_Read_Strobe_23 <= '0';
LMB_Write_Strobe_23 <= '0';
LMB_Byte_Enable_23 <= (others => '0');
LMB_Data_Addr_24 <= (others => '0');
LMB_Data_Write_24 <= (others => '0');
LMB_Addr_Strobe_24 <= '0';
LMB_Read_Strobe_24 <= '0';
LMB_Write_Strobe_24 <= '0';
LMB_Byte_Enable_24 <= (others => '0');
LMB_Data_Addr_25 <= (others => '0');
LMB_Data_Write_25 <= (others => '0');
LMB_Addr_Strobe_25 <= '0';
LMB_Read_Strobe_25 <= '0';
LMB_Write_Strobe_25 <= '0';
LMB_Byte_Enable_25 <= (others => '0');
LMB_Data_Addr_26 <= (others => '0');
LMB_Data_Write_26 <= (others => '0');
LMB_Addr_Strobe_26 <= '0';
LMB_Read_Strobe_26 <= '0';
LMB_Write_Strobe_26 <= '0';
LMB_Byte_Enable_26 <= (others => '0');
LMB_Data_Addr_27 <= (others => '0');
LMB_Data_Write_27 <= (others => '0');
LMB_Addr_Strobe_27 <= '0';
LMB_Read_Strobe_27 <= '0';
LMB_Write_Strobe_27 <= '0';
LMB_Byte_Enable_27 <= (others => '0');
LMB_Data_Addr_28 <= (others => '0');
LMB_Data_Write_28 <= (others => '0');
LMB_Addr_Strobe_28 <= '0';
LMB_Read_Strobe_28 <= '0';
LMB_Write_Strobe_28 <= '0';
LMB_Byte_Enable_28 <= (others => '0');
LMB_Data_Addr_29 <= (others => '0');
LMB_Data_Write_29 <= (others => '0');
LMB_Addr_Strobe_29 <= '0';
LMB_Read_Strobe_29 <= '0';
LMB_Write_Strobe_29 <= '0';
LMB_Byte_Enable_29 <= (others => '0');
LMB_Data_Addr_30 <= (others => '0');
LMB_Data_Write_30 <= (others => '0');
LMB_Addr_Strobe_30 <= '0';
LMB_Read_Strobe_30 <= '0';
LMB_Write_Strobe_30 <= '0';
LMB_Byte_Enable_30 <= (others => '0');
LMB_Data_Addr_31 <= (others => '0');
LMB_Data_Write_31 <= (others => '0');
LMB_Addr_Strobe_31 <= '0';
LMB_Read_Strobe_31 <= '0';
LMB_Write_Strobe_31 <= '0';
LMB_Byte_Enable_31 <= (others => '0');
end generate No_Bus_MASTER_LMB;
Use_AXI_IPIF : if (C_USE_UART = 1) or (C_DBG_REG_ACCESS = 1) generate
begin
-- ip2bus_data assignment - as core may use less than 32 bits
ip2bus_data(C_S_AXI_DATA_WIDTH-1 downto C_REG_DATA_WIDTH) <= (others => '0');
---------------------------------------------------------------------------
-- AXI lite IPIF
---------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map (
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end generate Use_AXI_IPIF;
No_AXI_IPIF : if (C_USE_UART = 0) and (C_DBG_REG_ACCESS = 0) generate
begin
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
S_AXI_BRESP <= (others => '0');
S_AXI_BVALID <= '0';
S_AXI_ARREADY <= '0';
S_AXI_RDATA <= (others => '0');
S_AXI_RRESP <= (others => '0');
S_AXI_RVALID <= '0';
bus2ip_clk <= '0';
bus2ip_resetn <= '0';
bus2ip_data <= (others => '0');
bus2ip_rdce <= (others => '0');
bus2ip_wrce <= (others => '0');
bus2ip_cs <= (others => '0');
end generate No_AXI_IPIF;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2006-10-27 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
-- stefana 2014-04-30 Added external trace support
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library mdm_v3_2;
use mdm_v3_2.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
entity MDM is
generic (
C_FAMILY : string := "virtex7";
C_JTAG_CHAIN : integer := 2;
C_USE_BSCAN : integer := 0;
C_USE_CONFIG_RESET : integer := 0;
C_INTERCONNECT : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_FFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"0000_0000";
C_MB_DBG_PORTS : integer := 1;
C_DBG_REG_ACCESS : integer := 0;
C_DBG_MEM_ACCESS : integer := 0;
C_USE_UART : integer := 1;
C_USE_CROSS_TRIGGER : integer := 0;
C_TRACE_OUTPUT : integer := 0;
C_TRACE_DATA_WIDTH : integer range 2 to 32 := 32;
C_TRACE_CLK_FREQ_HZ : integer := 200000000;
C_TRACE_CLK_OUT_PHASE : integer range 0 to 360 := 90;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_THREAD_ID_WIDTH : integer := 1;
C_DATA_SIZE : integer range 32 to 32 := 32;
C_M_AXIS_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXIS_ID_WIDTH : integer range 1 to 7 := 7
);
port (
-- Global signals
Config_Reset : in std_logic := '0';
Scan_Reset_Sel : in std_logic := '0';
Scan_Reset : in std_logic := '0';
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- External cross trigger signals
Trig_In_0 : in std_logic;
Trig_Ack_In_0 : out std_logic;
Trig_Out_0 : out std_logic;
Trig_Ack_Out_0 : in std_logic;
Trig_In_1 : in std_logic;
Trig_Ack_In_1 : out std_logic;
Trig_Out_1 : out std_logic;
Trig_Ack_Out_1 : in std_logic;
Trig_In_2 : in std_logic;
Trig_Ack_In_2 : out std_logic;
Trig_Out_2 : out std_logic;
Trig_Ack_Out_2 : in std_logic;
Trig_In_3 : in std_logic;
Trig_Ack_In_3 : out std_logic;
Trig_Out_3 : out std_logic;
Trig_Ack_Out_3 : in std_logic;
-- AXI slave signals
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Bus master signals
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
LMB_Data_Addr_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_0 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_0 : out std_logic;
LMB_Read_Strobe_0 : out std_logic;
LMB_Write_Strobe_0 : out std_logic;
LMB_Ready_0 : in std_logic;
LMB_Wait_0 : in std_logic;
LMB_CE_0 : in std_logic;
LMB_UE_0 : in std_logic;
LMB_Byte_Enable_0 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_1 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_1 : out std_logic;
LMB_Read_Strobe_1 : out std_logic;
LMB_Write_Strobe_1 : out std_logic;
LMB_Ready_1 : in std_logic;
LMB_Wait_1 : in std_logic;
LMB_CE_1 : in std_logic;
LMB_UE_1 : in std_logic;
LMB_Byte_Enable_1 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_2 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_2 : out std_logic;
LMB_Read_Strobe_2 : out std_logic;
LMB_Write_Strobe_2 : out std_logic;
LMB_Ready_2 : in std_logic;
LMB_Wait_2 : in std_logic;
LMB_CE_2 : in std_logic;
LMB_UE_2 : in std_logic;
LMB_Byte_Enable_2 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_3 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_3 : out std_logic;
LMB_Read_Strobe_3 : out std_logic;
LMB_Write_Strobe_3 : out std_logic;
LMB_Ready_3 : in std_logic;
LMB_Wait_3 : in std_logic;
LMB_CE_3 : in std_logic;
LMB_UE_3 : in std_logic;
LMB_Byte_Enable_3 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_4 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_4 : out std_logic;
LMB_Read_Strobe_4 : out std_logic;
LMB_Write_Strobe_4 : out std_logic;
LMB_Ready_4 : in std_logic;
LMB_Wait_4 : in std_logic;
LMB_CE_4 : in std_logic;
LMB_UE_4 : in std_logic;
LMB_Byte_Enable_4 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_5 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_5 : out std_logic;
LMB_Read_Strobe_5 : out std_logic;
LMB_Write_Strobe_5 : out std_logic;
LMB_Ready_5 : in std_logic;
LMB_Wait_5 : in std_logic;
LMB_CE_5 : in std_logic;
LMB_UE_5 : in std_logic;
LMB_Byte_Enable_5 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_6 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_6 : out std_logic;
LMB_Read_Strobe_6 : out std_logic;
LMB_Write_Strobe_6 : out std_logic;
LMB_Ready_6 : in std_logic;
LMB_Wait_6 : in std_logic;
LMB_CE_6 : in std_logic;
LMB_UE_6 : in std_logic;
LMB_Byte_Enable_6 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_7 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_7 : out std_logic;
LMB_Read_Strobe_7 : out std_logic;
LMB_Write_Strobe_7 : out std_logic;
LMB_Ready_7 : in std_logic;
LMB_Wait_7 : in std_logic;
LMB_CE_7 : in std_logic;
LMB_UE_7 : in std_logic;
LMB_Byte_Enable_7 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_8 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_8 : out std_logic;
LMB_Read_Strobe_8 : out std_logic;
LMB_Write_Strobe_8 : out std_logic;
LMB_Ready_8 : in std_logic;
LMB_Wait_8 : in std_logic;
LMB_CE_8 : in std_logic;
LMB_UE_8 : in std_logic;
LMB_Byte_Enable_8 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_9 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_9 : out std_logic;
LMB_Read_Strobe_9 : out std_logic;
LMB_Write_Strobe_9 : out std_logic;
LMB_Ready_9 : in std_logic;
LMB_Wait_9 : in std_logic;
LMB_CE_9 : in std_logic;
LMB_UE_9 : in std_logic;
LMB_Byte_Enable_9 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_10 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_10 : out std_logic;
LMB_Read_Strobe_10 : out std_logic;
LMB_Write_Strobe_10 : out std_logic;
LMB_Ready_10 : in std_logic;
LMB_Wait_10 : in std_logic;
LMB_CE_10 : in std_logic;
LMB_UE_10 : in std_logic;
LMB_Byte_Enable_10 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_11 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_11 : out std_logic;
LMB_Read_Strobe_11 : out std_logic;
LMB_Write_Strobe_11 : out std_logic;
LMB_Ready_11 : in std_logic;
LMB_Wait_11 : in std_logic;
LMB_CE_11 : in std_logic;
LMB_UE_11 : in std_logic;
LMB_Byte_Enable_11 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_12 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_12 : out std_logic;
LMB_Read_Strobe_12 : out std_logic;
LMB_Write_Strobe_12 : out std_logic;
LMB_Ready_12 : in std_logic;
LMB_Wait_12 : in std_logic;
LMB_CE_12 : in std_logic;
LMB_UE_12 : in std_logic;
LMB_Byte_Enable_12 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_13 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_13 : out std_logic;
LMB_Read_Strobe_13 : out std_logic;
LMB_Write_Strobe_13 : out std_logic;
LMB_Ready_13 : in std_logic;
LMB_Wait_13 : in std_logic;
LMB_CE_13 : in std_logic;
LMB_UE_13 : in std_logic;
LMB_Byte_Enable_13 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_14 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_14 : out std_logic;
LMB_Read_Strobe_14 : out std_logic;
LMB_Write_Strobe_14 : out std_logic;
LMB_Ready_14 : in std_logic;
LMB_Wait_14 : in std_logic;
LMB_CE_14 : in std_logic;
LMB_UE_14 : in std_logic;
LMB_Byte_Enable_14 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_15 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_15 : out std_logic;
LMB_Read_Strobe_15 : out std_logic;
LMB_Write_Strobe_15 : out std_logic;
LMB_Ready_15 : in std_logic;
LMB_Wait_15 : in std_logic;
LMB_CE_15 : in std_logic;
LMB_UE_15 : in std_logic;
LMB_Byte_Enable_15 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_16 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_16 : out std_logic;
LMB_Read_Strobe_16 : out std_logic;
LMB_Write_Strobe_16 : out std_logic;
LMB_Ready_16 : in std_logic;
LMB_Wait_16 : in std_logic;
LMB_CE_16 : in std_logic;
LMB_UE_16 : in std_logic;
LMB_Byte_Enable_16 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_17 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_17 : out std_logic;
LMB_Read_Strobe_17 : out std_logic;
LMB_Write_Strobe_17 : out std_logic;
LMB_Ready_17 : in std_logic;
LMB_Wait_17 : in std_logic;
LMB_CE_17 : in std_logic;
LMB_UE_17 : in std_logic;
LMB_Byte_Enable_17 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_18 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_18 : out std_logic;
LMB_Read_Strobe_18 : out std_logic;
LMB_Write_Strobe_18 : out std_logic;
LMB_Ready_18 : in std_logic;
LMB_Wait_18 : in std_logic;
LMB_CE_18 : in std_logic;
LMB_UE_18 : in std_logic;
LMB_Byte_Enable_18 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_19 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_19 : out std_logic;
LMB_Read_Strobe_19 : out std_logic;
LMB_Write_Strobe_19 : out std_logic;
LMB_Ready_19 : in std_logic;
LMB_Wait_19 : in std_logic;
LMB_CE_19 : in std_logic;
LMB_UE_19 : in std_logic;
LMB_Byte_Enable_19 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_20 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_20 : out std_logic;
LMB_Read_Strobe_20 : out std_logic;
LMB_Write_Strobe_20 : out std_logic;
LMB_Ready_20 : in std_logic;
LMB_Wait_20 : in std_logic;
LMB_CE_20 : in std_logic;
LMB_UE_20 : in std_logic;
LMB_Byte_Enable_20 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_21 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_21 : out std_logic;
LMB_Read_Strobe_21 : out std_logic;
LMB_Write_Strobe_21 : out std_logic;
LMB_Ready_21 : in std_logic;
LMB_Wait_21 : in std_logic;
LMB_CE_21 : in std_logic;
LMB_UE_21 : in std_logic;
LMB_Byte_Enable_21 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_22 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_22 : out std_logic;
LMB_Read_Strobe_22 : out std_logic;
LMB_Write_Strobe_22 : out std_logic;
LMB_Ready_22 : in std_logic;
LMB_Wait_22 : in std_logic;
LMB_CE_22 : in std_logic;
LMB_UE_22 : in std_logic;
LMB_Byte_Enable_22 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_23 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_23 : out std_logic;
LMB_Read_Strobe_23 : out std_logic;
LMB_Write_Strobe_23 : out std_logic;
LMB_Ready_23 : in std_logic;
LMB_Wait_23 : in std_logic;
LMB_CE_23 : in std_logic;
LMB_UE_23 : in std_logic;
LMB_Byte_Enable_23 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_24 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_24 : out std_logic;
LMB_Read_Strobe_24 : out std_logic;
LMB_Write_Strobe_24 : out std_logic;
LMB_Ready_24 : in std_logic;
LMB_Wait_24 : in std_logic;
LMB_CE_24 : in std_logic;
LMB_UE_24 : in std_logic;
LMB_Byte_Enable_24 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_25 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_25 : out std_logic;
LMB_Read_Strobe_25 : out std_logic;
LMB_Write_Strobe_25 : out std_logic;
LMB_Ready_25 : in std_logic;
LMB_Wait_25 : in std_logic;
LMB_CE_25 : in std_logic;
LMB_UE_25 : in std_logic;
LMB_Byte_Enable_25 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_26 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_26 : out std_logic;
LMB_Read_Strobe_26 : out std_logic;
LMB_Write_Strobe_26 : out std_logic;
LMB_Ready_26 : in std_logic;
LMB_Wait_26 : in std_logic;
LMB_CE_26 : in std_logic;
LMB_UE_26 : in std_logic;
LMB_Byte_Enable_26 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_27 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_27 : out std_logic;
LMB_Read_Strobe_27 : out std_logic;
LMB_Write_Strobe_27 : out std_logic;
LMB_Ready_27 : in std_logic;
LMB_Wait_27 : in std_logic;
LMB_CE_27 : in std_logic;
LMB_UE_27 : in std_logic;
LMB_Byte_Enable_27 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_28 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_28 : out std_logic;
LMB_Read_Strobe_28 : out std_logic;
LMB_Write_Strobe_28 : out std_logic;
LMB_Ready_28 : in std_logic;
LMB_Wait_28 : in std_logic;
LMB_CE_28 : in std_logic;
LMB_UE_28 : in std_logic;
LMB_Byte_Enable_28 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_29 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_29 : out std_logic;
LMB_Read_Strobe_29 : out std_logic;
LMB_Write_Strobe_29 : out std_logic;
LMB_Ready_29 : in std_logic;
LMB_Wait_29 : in std_logic;
LMB_CE_29 : in std_logic;
LMB_UE_29 : in std_logic;
LMB_Byte_Enable_29 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_30 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_30 : out std_logic;
LMB_Read_Strobe_30 : out std_logic;
LMB_Write_Strobe_30 : out std_logic;
LMB_Ready_30 : in std_logic;
LMB_Wait_30 : in std_logic;
LMB_CE_30 : in std_logic;
LMB_UE_30 : in std_logic;
LMB_Byte_Enable_30 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_31 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_31 : out std_logic;
LMB_Read_Strobe_31 : out std_logic;
LMB_Write_Strobe_31 : out std_logic;
LMB_Ready_31 : in std_logic;
LMB_Wait_31 : in std_logic;
LMB_CE_31 : in std_logic;
LMB_UE_31 : in std_logic;
LMB_Byte_Enable_31 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External BSCAN inputs
-- These signals are used when C_USE_BSCAN = 2 (EXTERNAL)
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
-- External JTAG ports
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM;
architecture IMP of MDM is
function int2std (val : integer) return std_logic is
begin -- function int2std
if (val = 0) then
return '0';
else
return '1';
end if;
end function int2std;
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0) := X"00000000";
constant C_REG_NUM_CE : integer := 4 + 4 * C_DBG_REG_ACCESS;
constant C_REG_DATA_WIDTH : integer := 8 + 24 * C_DBG_REG_ACCESS;
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) :=
(31 downto 5 => '0', 4 => int2std(C_DBG_REG_ACCESS), 3 downto 0 => '1');
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := (
-- Registers Base Address (not used)
ZEROES & C_BASEADDR,
ZEROES & (C_BASEADDR or C_S_AXI_MIN_SIZE)
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (
0 => C_REG_NUM_CE
);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
constant C_TRACE_AXI_MASTER : boolean := C_TRACE_OUTPUT = 3;
--------------------------------------------------------------------------
-- Component declarations
--------------------------------------------------------------------------
component MDM_Core
generic (
C_JTAG_CHAIN : integer;
C_USE_BSCAN : integer;
C_USE_CONFIG_RESET : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8;
C_TRACE_OUTPUT : integer;
C_TRACE_DATA_WIDTH : integer;
C_TRACE_CLK_FREQ_HZ : integer;
C_TRACE_CLK_OUT_PHASE : integer;
C_M_AXIS_DATA_WIDTH : integer;
C_M_AXIS_ID_WIDTH : integer);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
-- AXI IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_data : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_dwr_start : out std_logic;
Master_dwr_next : in std_logic;
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External Trigger Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component MDM_Core;
component bus_master is
generic (
C_M_AXI_DATA_WIDTH : natural;
C_M_AXI_THREAD_ID_WIDTH : natural;
C_M_AXI_ADDR_WIDTH : natural;
C_DATA_SIZE : natural;
C_HAS_FIFO_PORTS : boolean;
C_HAS_DIRECT_PORT : boolean
);
port (
Rd_Start : in std_logic;
Rd_Addr : in std_logic_vector(31 downto 0);
Rd_Len : in std_logic_vector(4 downto 0);
Rd_Size : in std_logic_vector(1 downto 0);
Rd_Exclusive : in std_logic;
Rd_Idle : out std_logic;
Rd_Response : out std_logic_vector(1 downto 0);
Wr_Start : in std_logic;
Wr_Addr : in std_logic_vector(31 downto 0);
Wr_Len : in std_logic_vector(4 downto 0);
Wr_Size : in std_logic_vector(1 downto 0);
Wr_Exclusive : in std_logic;
Wr_Idle : out std_logic;
Wr_Response : out std_logic_vector(1 downto 0);
Data_Rd : in std_logic;
Data_Out : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Exists : out std_logic;
Data_Wr : in std_logic;
Data_In : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Empty : out std_logic;
Direct_Wr_Addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Direct_Wr_Len : in std_logic_vector(4 downto 0);
Direct_Wr_Data : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Direct_Wr_Start : in std_logic;
Direct_Wr_Next : out std_logic;
Direct_Wr_Done : out std_logic;
Direct_Wr_Resp : out std_logic_vector(1 downto 0);
LMB_Data_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe : out std_logic;
LMB_Read_Strobe : out std_logic;
LMB_Write_Strobe : out std_logic;
LMB_Ready : in std_logic;
LMB_Wait : in std_logic;
LMB_UE : in std_logic;
LMB_Byte_Enable : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WLAST : out std_logic;
M_AXI_WDATA : out std_logic_vector(31 downto 0);
M_AXI_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end component bus_master;
--------------------------------------------------------------------------
-- Functions
--------------------------------------------------------------------------
-- Returns at least 1
function MakePos (a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
constant C_EN_WIDTH : integer := MakePos(C_MB_DBG_PORTS);
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal tdi : std_logic;
signal reset : std_logic;
signal update : std_logic;
signal capture : std_logic;
signal shift : std_logic;
signal sel : std_logic;
signal drck : std_logic;
signal tdo : std_logic;
signal drck_i : std_logic;
signal update_i : std_logic;
signal dbgreg_drck : std_logic;
signal dbgreg_update : std_logic;
signal dbgreg_select : std_logic;
signal jtag_busy : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
signal bus2ip_cs : std_logic_vector(((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal mb_debug_enabled : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal master_rd_start : std_logic;
signal master_rd_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_rd_len : std_logic_vector(4 downto 0);
signal master_rd_size : std_logic_vector(1 downto 0);
signal master_rd_excl : std_logic;
signal master_rd_idle : std_logic;
signal master_rd_resp : std_logic_vector(1 downto 0);
signal master_wr_start : std_logic;
signal master_wr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_wr_len : std_logic_vector(4 downto 0);
signal master_wr_size : std_logic_vector(1 downto 0);
signal master_wr_excl : std_logic;
signal master_wr_idle : std_logic;
signal master_wr_resp : std_logic_vector(1 downto 0);
signal master_data_rd : std_logic;
signal master_data_out : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_exists : std_logic;
signal master_data_wr : std_logic;
signal master_data_in : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_empty : std_logic;
signal master_dwr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_dwr_len : std_logic_vector(4 downto 0);
signal master_dwr_data : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_dwr_start : std_logic;
signal master_dwr_next : std_logic;
signal master_dwr_done : std_logic;
signal master_dwr_resp : std_logic_vector(1 downto 0);
signal ext_trig_in : std_logic_vector(0 to 3);
signal ext_trig_Ack_In : std_logic_vector(0 to 3);
signal ext_trig_out : std_logic_vector(0 to 3);
signal ext_trig_Ack_Out : std_logic_vector(0 to 3);
--------------------------------------------------------------------------
-- Attibute declarations
--------------------------------------------------------------------------
attribute period : string;
attribute period of update : signal is "200 ns";
attribute buffer_type : string;
attribute buffer_type of update_i : signal is "none";
attribute buffer_type of MDM_Core_I1 : label is "none";
begin -- architecture IMP
Use_E2 : if C_USE_BSCAN /= 2 generate
begin
BSCANE2_I : BSCANE2
generic map (
DISABLE_JTAG => "FALSE",
JTAG_CHAIN => C_JTAG_CHAIN)
port map (
CAPTURE => capture, -- [out std_logic]
DRCK => drck_i, -- [out std_logic]
RESET => reset, -- [out std_logic]
RUNTEST => open, -- [out std_logic]
SEL => sel, -- [out std_logic]
SHIFT => shift, -- [out std_logic]
TCK => open, -- [out std_logic]
TDI => tdi, -- [out std_logic]
TMS => open, -- [out std_logic]
UPDATE => update_i, -- [out std_logic]
TDO => tdo); -- [in std_logic]
end generate Use_E2;
Use_External : if C_USE_BSCAN = 2 generate
begin
capture <= bscan_ext_capture;
drck_i <= bscan_ext_drck;
reset <= bscan_ext_reset;
sel <= bscan_ext_sel;
shift <= bscan_ext_shift;
tdi <= bscan_ext_tdi;
update_i <= bscan_ext_update;
bscan_ext_tdo <= tdo;
end generate Use_External;
No_External : if C_USE_BSCAN /= 2 generate
begin
bscan_ext_tdo <= '0';
end generate No_External;
Use_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 1 generate
signal dbgreg_select_n : std_logic;
signal dbgreg_drck_i : std_logic;
signal dbgreg_update_i : std_logic;
signal update_set : std_logic;
signal update_reset : std_logic;
begin
dbgreg_select_n <= not dbgreg_select;
-- drck <= dbgreg_drck when dbgreg_select = '1' else drck_i;
BUFG_DRCK : BUFG
port map (
O => dbgreg_drck_i,
I => dbgreg_drck
);
BUFGCTRL_DRCK : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => drck,
CE0 => '1',
CE1 => '1',
I0 => drck_i,
I1 => dbgreg_drck_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
-- update <= dbgreg_update when dbgreg_select = '1' else update_i;
BUFG_UPDATE : BUFG
port map (
O => dbgreg_update_i,
I => dbgreg_update
);
BUFGCTRL_UPDATE : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => update,
CE0 => '1',
CE1 => '1',
I0 => update_i,
I1 => dbgreg_update_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
JTAG_Busy_Detect : process (drck_i, sel, update_set, Config_Reset)
begin
if sel = '0' or update_set = '1' or Config_Reset = '1' then
jtag_busy <= '0';
update_reset <= '1';
elsif drck_i'event and drck_i = '1' then
if sel = '1' and capture = '1' then
jtag_busy <= '1';
end if;
update_reset <= '0';
end if;
end process JTAG_Busy_Detect;
JTAG_Update_Detect : process (update_i, update_reset, Config_Reset)
begin
if update_reset = '1' or Config_Reset = '1' then
update_set <= '0';
elsif update_i'event and update_i = '1' then
update_set <= '1';
end if;
end process JTAG_Update_Detect;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 0 generate
begin
BUFG_DRCK : BUFG
port map (
O => drck,
I => drck_i
);
update <= update_i;
jtag_busy <= '0';
end generate No_Dbg_Reg_Access;
---------------------------------------------------------------------------
-- MDM core
---------------------------------------------------------------------------
MDM_Core_I1 : MDM_Core
generic map (
C_JTAG_CHAIN => C_JTAG_CHAIN, -- [integer]
C_USE_BSCAN => C_USE_BSCAN, -- [integer]
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET, -- [integer = 0]
C_BASEADDR => C_BASEADDR, -- [std_logic_vector(0 to 31)]
C_HIGHADDR => C_HIGHADDR, -- [std_logic_vector(0 to 31)]
C_MB_DBG_PORTS => C_MB_DBG_PORTS, -- [integer]
C_EN_WIDTH => C_EN_WIDTH, -- [integer]
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS, -- [integer]
C_REG_NUM_CE => C_REG_NUM_CE, -- [integer]
C_REG_DATA_WIDTH => C_REG_DATA_WIDTH, -- [integer]
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS, -- [integer]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ, -- [integer]
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH, -- [integer]
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH, -- [integer]
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER, -- [integer]
C_USE_UART => C_USE_UART, -- [integer]
C_UART_WIDTH => 8, -- [integer]
C_TRACE_OUTPUT => C_TRACE_OUTPUT, -- [integer]
C_TRACE_DATA_WIDTH => C_TRACE_DATA_WIDTH, -- [integer]
C_TRACE_CLK_FREQ_HZ => C_TRACE_CLK_FREQ_HZ, -- [integer]
C_TRACE_CLK_OUT_PHASE => C_TRACE_CLK_OUT_PHASE, -- [integer]
C_M_AXIS_DATA_WIDTH => C_M_AXIS_DATA_WIDTH, -- [integer]
C_M_AXIS_ID_WIDTH => C_M_AXIS_ID_WIDTH -- [integer]
)
port map (
-- Global signals
Config_Reset => Config_Reset, -- [in std_logic]
Scan_Reset_Sel => Scan_Reset_Sel, -- [in std_logic]
Scan_Reset => Scan_Reset, -- [in std_logic]
M_AXIS_ACLK => M_AXIS_ACLK, -- [in std_logic]
M_AXIS_ARESETN => M_AXIS_ARESETN, -- [in std_logic]
Interrupt => Interrupt, -- [out std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst, -- [out std_logic]
-- Debug Register Access signals
DbgReg_DRCK => dbgreg_drck, -- [out std_logic]
DbgReg_UPDATE => dbgreg_update, -- [out std_logic]
DbgReg_Select => dbgreg_select, -- [out std_logic]
JTAG_Busy => jtag_busy, -- [in std_logic]
-- AXI IPIC signals
bus2ip_clk => bus2ip_clk,
bus2ip_resetn => bus2ip_resetn,
bus2ip_data => bus2ip_data(C_REG_DATA_WIDTH-1 downto 0),
bus2ip_rdce => bus2ip_rdce(C_REG_NUM_CE-1 downto 0),
bus2ip_wrce => bus2ip_wrce(C_REG_NUM_CE-1 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
ip2bus_data => ip2bus_data(C_REG_DATA_WIDTH-1 downto 0),
-- Bus Master signals
MB_Debug_Enabled => mb_debug_enabled,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
Master_rd_start => master_rd_start,
Master_rd_addr => master_rd_addr,
Master_rd_len => master_rd_len,
Master_rd_size => master_rd_size,
Master_rd_excl => master_rd_excl,
Master_rd_idle => master_rd_idle,
Master_rd_resp => master_rd_resp,
Master_wr_start => master_wr_start,
Master_wr_addr => master_wr_addr,
Master_wr_len => master_wr_len,
Master_wr_size => master_wr_size,
Master_wr_excl => master_wr_excl,
Master_wr_idle => master_wr_idle,
Master_wr_resp => master_wr_resp,
Master_data_rd => master_data_rd,
Master_data_out => master_data_out,
Master_data_exists => master_data_exists,
Master_data_wr => master_data_wr,
Master_data_in => master_data_in,
Master_data_empty => master_data_empty,
Master_dwr_addr => master_dwr_addr,
Master_dwr_len => master_dwr_len,
Master_dwr_data => master_dwr_data,
Master_dwr_start => master_dwr_start,
Master_dwr_next => master_dwr_next,
Master_dwr_done => master_dwr_done,
Master_dwr_resp => master_dwr_resp,
-- JTAG signals
JTAG_TDI => tdi, -- [in std_logic]
JTAG_RESET => reset, -- [in std_logic]
UPDATE => update, -- [in std_logic]
JTAG_SHIFT => shift, -- [in std_logic]
JTAG_CAPTURE => capture, -- [in std_logic]
SEL => sel, -- [in std_logic]
DRCK => drck, -- [in std_logic]
JTAG_TDO => tdo, -- [out std_logic]
-- External Trace AXI Stream output
M_AXIS_TDATA => M_AXIS_TDATA, -- [out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0)]
M_AXIS_TID => M_AXIS_TID, -- [out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0)]
M_AXIS_TREADY => M_AXIS_TREADY, -- [in std_logic]
M_AXIS_TVALID => M_AXIS_TVALID, -- [out std_logic]
-- External Trace output
TRACE_CLK_OUT => TRACE_CLK_OUT, -- [out std_logic]
TRACE_CLK => TRACE_CLK, -- [in std_logic]
TRACE_CTL => TRACE_CTL, -- [out std_logic]
TRACE_DATA => TRACE_DATA, -- [out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0)]
-- MicroBlaze Debug Signals
Dbg_Clk_0 => Dbg_Clk_0, -- [out std_logic]
Dbg_TDI_0 => Dbg_TDI_0, -- [out std_logic]
Dbg_TDO_0 => Dbg_TDO_0, -- [in std_logic]
Dbg_Reg_En_0 => Dbg_Reg_En_0, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_0 => Dbg_Capture_0, -- [out std_logic]
Dbg_Shift_0 => Dbg_Shift_0, -- [out std_logic]
Dbg_Update_0 => Dbg_Update_0, -- [out std_logic]
Dbg_Rst_0 => Dbg_Rst_0, -- [out std_logic]
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_0 => Dbg_TrClk_0, -- [out std_logic]
Dbg_TrData_0 => Dbg_TrData_0, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_0 => Dbg_TrReady_0, -- [out std_logic]
Dbg_TrValid_0 => Dbg_TrValid_0, -- [in std_logic]
Dbg_Clk_1 => Dbg_Clk_1, -- [out std_logic]
Dbg_TDI_1 => Dbg_TDI_1, -- [out std_logic]
Dbg_TDO_1 => Dbg_TDO_1, -- [in std_logic]
Dbg_Reg_En_1 => Dbg_Reg_En_1, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_1 => Dbg_Capture_1, -- [out std_logic]
Dbg_Shift_1 => Dbg_Shift_1, -- [out std_logic]
Dbg_Update_1 => Dbg_Update_1, -- [out std_logic]
Dbg_Rst_1 => Dbg_Rst_1, -- [out std_logic]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_1 => Dbg_TrClk_1, -- [out std_logic]
Dbg_TrData_1 => Dbg_TrData_1, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_1 => Dbg_TrReady_1, -- [out std_logic]
Dbg_TrValid_1 => Dbg_TrValid_1, -- [in std_logic]
Dbg_Clk_2 => Dbg_Clk_2, -- [out std_logic]
Dbg_TDI_2 => Dbg_TDI_2, -- [out std_logic]
Dbg_TDO_2 => Dbg_TDO_2, -- [in std_logic]
Dbg_Reg_En_2 => Dbg_Reg_En_2, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_2 => Dbg_Capture_2, -- [out std_logic]
Dbg_Shift_2 => Dbg_Shift_2, -- [out std_logic]
Dbg_Update_2 => Dbg_Update_2, -- [out std_logic]
Dbg_Rst_2 => Dbg_Rst_2, -- [out std_logic]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_2 => Dbg_TrClk_2, -- [out std_logic]
Dbg_TrData_2 => Dbg_TrData_2, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_2 => Dbg_TrReady_2, -- [out std_logic]
Dbg_TrValid_2 => Dbg_TrValid_2, -- [in std_logic]
Dbg_Clk_3 => Dbg_Clk_3, -- [out std_logic]
Dbg_TDI_3 => Dbg_TDI_3, -- [out std_logic]
Dbg_TDO_3 => Dbg_TDO_3, -- [in std_logic]
Dbg_Reg_En_3 => Dbg_Reg_En_3, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_3 => Dbg_Capture_3, -- [out std_logic]
Dbg_Shift_3 => Dbg_Shift_3, -- [out std_logic]
Dbg_Update_3 => Dbg_Update_3, -- [out std_logic]
Dbg_Rst_3 => Dbg_Rst_3, -- [out std_logic]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_3 => Dbg_TrClk_3, -- [out std_logic]
Dbg_TrData_3 => Dbg_TrData_3, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_3 => Dbg_TrReady_3, -- [out std_logic]
Dbg_TrValid_3 => Dbg_TrValid_3, -- [in std_logic]
Dbg_Clk_4 => Dbg_Clk_4, -- [out std_logic]
Dbg_TDI_4 => Dbg_TDI_4, -- [out std_logic]
Dbg_TDO_4 => Dbg_TDO_4, -- [in std_logic]
Dbg_Reg_En_4 => Dbg_Reg_En_4, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_4 => Dbg_Capture_4, -- [out std_logic]
Dbg_Shift_4 => Dbg_Shift_4, -- [out std_logic]
Dbg_Update_4 => Dbg_Update_4, -- [out std_logic]
Dbg_Rst_4 => Dbg_Rst_4, -- [out std_logic]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_4 => Dbg_TrClk_4, -- [out std_logic]
Dbg_TrData_4 => Dbg_TrData_4, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_4 => Dbg_TrReady_4, -- [out std_logic]
Dbg_TrValid_4 => Dbg_TrValid_4, -- [in std_logic]
Dbg_Clk_5 => Dbg_Clk_5, -- [out std_logic]
Dbg_TDI_5 => Dbg_TDI_5, -- [out std_logic]
Dbg_TDO_5 => Dbg_TDO_5, -- [in std_logic]
Dbg_Reg_En_5 => Dbg_Reg_En_5, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_5 => Dbg_Capture_5, -- [out std_logic]
Dbg_Shift_5 => Dbg_Shift_5, -- [out std_logic]
Dbg_Update_5 => Dbg_Update_5, -- [out std_logic]
Dbg_Rst_5 => Dbg_Rst_5, -- [out std_logic]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_5 => Dbg_TrClk_5, -- [out std_logic]
Dbg_TrData_5 => Dbg_TrData_5, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_5 => Dbg_TrReady_5, -- [out std_logic]
Dbg_TrValid_5 => Dbg_TrValid_5, -- [in std_logic]
Dbg_Clk_6 => Dbg_Clk_6, -- [out std_logic]
Dbg_TDI_6 => Dbg_TDI_6, -- [out std_logic]
Dbg_TDO_6 => Dbg_TDO_6, -- [in std_logic]
Dbg_Reg_En_6 => Dbg_Reg_En_6, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_6 => Dbg_Capture_6, -- [out std_logic]
Dbg_Shift_6 => Dbg_Shift_6, -- [out std_logic]
Dbg_Update_6 => Dbg_Update_6, -- [out std_logic]
Dbg_Rst_6 => Dbg_Rst_6, -- [out std_logic]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_6 => Dbg_TrClk_6, -- [out std_logic]
Dbg_TrData_6 => Dbg_TrData_6, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_6 => Dbg_TrReady_6, -- [out std_logic]
Dbg_TrValid_6 => Dbg_TrValid_6, -- [in std_logic]
Dbg_Clk_7 => Dbg_Clk_7, -- [out std_logic]
Dbg_TDI_7 => Dbg_TDI_7, -- [out std_logic]
Dbg_TDO_7 => Dbg_TDO_7, -- [in std_logic]
Dbg_Reg_En_7 => Dbg_Reg_En_7, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_7 => Dbg_Capture_7, -- [out std_logic]
Dbg_Shift_7 => Dbg_Shift_7, -- [out std_logic]
Dbg_Update_7 => Dbg_Update_7, -- [out std_logic]
Dbg_Rst_7 => Dbg_Rst_7, -- [out std_logic]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_7 => Dbg_TrClk_7, -- [out std_logic]
Dbg_TrData_7 => Dbg_TrData_7, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_7 => Dbg_TrReady_7, -- [out std_logic]
Dbg_TrValid_7 => Dbg_TrValid_7, -- [in std_logic]
Dbg_Clk_8 => Dbg_Clk_8, -- [out std_logic]
Dbg_TDI_8 => Dbg_TDI_8, -- [out std_logic]
Dbg_TDO_8 => Dbg_TDO_8, -- [in std_logic]
Dbg_Reg_En_8 => Dbg_Reg_En_8, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_8 => Dbg_Capture_8, -- [out std_logic]
Dbg_Shift_8 => Dbg_Shift_8, -- [out std_logic]
Dbg_Update_8 => Dbg_Update_8, -- [out std_logic]
Dbg_Rst_8 => Dbg_Rst_8, -- [out std_logic]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_8 => Dbg_TrClk_8, -- [out std_logic]
Dbg_TrData_8 => Dbg_TrData_8, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_8 => Dbg_TrReady_8, -- [out std_logic]
Dbg_TrValid_8 => Dbg_TrValid_8, -- [in std_logic]
Dbg_Clk_9 => Dbg_Clk_9, -- [out std_logic]
Dbg_TDI_9 => Dbg_TDI_9, -- [out std_logic]
Dbg_TDO_9 => Dbg_TDO_9, -- [in std_logic]
Dbg_Reg_En_9 => Dbg_Reg_En_9, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_9 => Dbg_Capture_9, -- [out std_logic]
Dbg_Shift_9 => Dbg_Shift_9, -- [out std_logic]
Dbg_Update_9 => Dbg_Update_9, -- [out std_logic]
Dbg_Rst_9 => Dbg_Rst_9, -- [out std_logic]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_9 => Dbg_TrClk_9, -- [out std_logic]
Dbg_TrData_9 => Dbg_TrData_9, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_9 => Dbg_TrReady_9, -- [out std_logic]
Dbg_TrValid_9 => Dbg_TrValid_9, -- [in std_logic]
Dbg_Clk_10 => Dbg_Clk_10, -- [out std_logic]
Dbg_TDI_10 => Dbg_TDI_10, -- [out std_logic]
Dbg_TDO_10 => Dbg_TDO_10, -- [in std_logic]
Dbg_Reg_En_10 => Dbg_Reg_En_10, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_10 => Dbg_Capture_10, -- [out std_logic]
Dbg_Shift_10 => Dbg_Shift_10, -- [out std_logic]
Dbg_Update_10 => Dbg_Update_10, -- [out std_logic]
Dbg_Rst_10 => Dbg_Rst_10, -- [out std_logic]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_10 => Dbg_TrClk_10, -- [out std_logic]
Dbg_TrData_10 => Dbg_TrData_10, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_10 => Dbg_TrReady_10, -- [out std_logic]
Dbg_TrValid_10 => Dbg_TrValid_10, -- [in std_logic]
Dbg_Clk_11 => Dbg_Clk_11, -- [out std_logic]
Dbg_TDI_11 => Dbg_TDI_11, -- [out std_logic]
Dbg_TDO_11 => Dbg_TDO_11, -- [in std_logic]
Dbg_Reg_En_11 => Dbg_Reg_En_11, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_11 => Dbg_Capture_11, -- [out std_logic]
Dbg_Shift_11 => Dbg_Shift_11, -- [out std_logic]
Dbg_Update_11 => Dbg_Update_11, -- [out std_logic]
Dbg_Rst_11 => Dbg_Rst_11, -- [out std_logic]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_11 => Dbg_TrClk_11, -- [out std_logic]
Dbg_TrData_11 => Dbg_TrData_11, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_11 => Dbg_TrReady_11, -- [out std_logic]
Dbg_TrValid_11 => Dbg_TrValid_11, -- [in std_logic]
Dbg_Clk_12 => Dbg_Clk_12, -- [out std_logic]
Dbg_TDI_12 => Dbg_TDI_12, -- [out std_logic]
Dbg_TDO_12 => Dbg_TDO_12, -- [in std_logic]
Dbg_Reg_En_12 => Dbg_Reg_En_12, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_12 => Dbg_Capture_12, -- [out std_logic]
Dbg_Shift_12 => Dbg_Shift_12, -- [out std_logic]
Dbg_Update_12 => Dbg_Update_12, -- [out std_logic]
Dbg_Rst_12 => Dbg_Rst_12, -- [out std_logic]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_12 => Dbg_TrClk_12, -- [out std_logic]
Dbg_TrData_12 => Dbg_TrData_12, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_12 => Dbg_TrReady_12, -- [out std_logic]
Dbg_TrValid_12 => Dbg_TrValid_12, -- [in std_logic]
Dbg_Clk_13 => Dbg_Clk_13, -- [out std_logic]
Dbg_TDI_13 => Dbg_TDI_13, -- [out std_logic]
Dbg_TDO_13 => Dbg_TDO_13, -- [in std_logic]
Dbg_Reg_En_13 => Dbg_Reg_En_13, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_13 => Dbg_Capture_13, -- [out std_logic]
Dbg_Shift_13 => Dbg_Shift_13, -- [out std_logic]
Dbg_Update_13 => Dbg_Update_13, -- [out std_logic]
Dbg_Rst_13 => Dbg_Rst_13, -- [out std_logic]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_13 => Dbg_TrClk_13, -- [out std_logic]
Dbg_TrData_13 => Dbg_TrData_13, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_13 => Dbg_TrReady_13, -- [out std_logic]
Dbg_TrValid_13 => Dbg_TrValid_13, -- [in std_logic]
Dbg_Clk_14 => Dbg_Clk_14, -- [out std_logic]
Dbg_TDI_14 => Dbg_TDI_14, -- [out std_logic]
Dbg_TDO_14 => Dbg_TDO_14, -- [in std_logic]
Dbg_Reg_En_14 => Dbg_Reg_En_14, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_14 => Dbg_Capture_14, -- [out std_logic]
Dbg_Shift_14 => Dbg_Shift_14, -- [out std_logic]
Dbg_Update_14 => Dbg_Update_14, -- [out std_logic]
Dbg_Rst_14 => Dbg_Rst_14, -- [out std_logic]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_14 => Dbg_TrClk_14, -- [out std_logic]
Dbg_TrData_14 => Dbg_TrData_14, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_14 => Dbg_TrReady_14, -- [out std_logic]
Dbg_TrValid_14 => Dbg_TrValid_14, -- [in std_logic]
Dbg_Clk_15 => Dbg_Clk_15, -- [out std_logic]
Dbg_TDI_15 => Dbg_TDI_15, -- [out std_logic]
Dbg_TDO_15 => Dbg_TDO_15, -- [in std_logic]
Dbg_Reg_En_15 => Dbg_Reg_En_15, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_15 => Dbg_Capture_15, -- [out std_logic]
Dbg_Shift_15 => Dbg_Shift_15, -- [out std_logic]
Dbg_Update_15 => Dbg_Update_15, -- [out std_logic]
Dbg_Rst_15 => Dbg_Rst_15, -- [out std_logic]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_15 => Dbg_TrClk_15, -- [out std_logic]
Dbg_TrData_15 => Dbg_TrData_15, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_15 => Dbg_TrReady_15, -- [out std_logic]
Dbg_TrValid_15 => Dbg_TrValid_15, -- [in std_logic]
Dbg_Clk_16 => Dbg_Clk_16, -- [out std_logic]
Dbg_TDI_16 => Dbg_TDI_16, -- [out std_logic]
Dbg_TDO_16 => Dbg_TDO_16, -- [in std_logic]
Dbg_Reg_En_16 => Dbg_Reg_En_16, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_16 => Dbg_Capture_16, -- [out std_logic]
Dbg_Shift_16 => Dbg_Shift_16, -- [out std_logic]
Dbg_Update_16 => Dbg_Update_16, -- [out std_logic]
Dbg_Rst_16 => Dbg_Rst_16, -- [out std_logic]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_16 => Dbg_TrClk_16, -- [out std_logic]
Dbg_TrData_16 => Dbg_TrData_16, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_16 => Dbg_TrReady_16, -- [out std_logic]
Dbg_TrValid_16 => Dbg_TrValid_16, -- [in std_logic]
Dbg_Clk_17 => Dbg_Clk_17, -- [out std_logic]
Dbg_TDI_17 => Dbg_TDI_17, -- [out std_logic]
Dbg_TDO_17 => Dbg_TDO_17, -- [in std_logic]
Dbg_Reg_En_17 => Dbg_Reg_En_17, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_17 => Dbg_Capture_17, -- [out std_logic]
Dbg_Shift_17 => Dbg_Shift_17, -- [out std_logic]
Dbg_Update_17 => Dbg_Update_17, -- [out std_logic]
Dbg_Rst_17 => Dbg_Rst_17, -- [out std_logic]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_17 => Dbg_TrClk_17, -- [out std_logic]
Dbg_TrData_17 => Dbg_TrData_17, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_17 => Dbg_TrReady_17, -- [out std_logic]
Dbg_TrValid_17 => Dbg_TrValid_17, -- [in std_logic]
Dbg_Clk_18 => Dbg_Clk_18, -- [out std_logic]
Dbg_TDI_18 => Dbg_TDI_18, -- [out std_logic]
Dbg_TDO_18 => Dbg_TDO_18, -- [in std_logic]
Dbg_Reg_En_18 => Dbg_Reg_En_18, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_18 => Dbg_Capture_18, -- [out std_logic]
Dbg_Shift_18 => Dbg_Shift_18, -- [out std_logic]
Dbg_Update_18 => Dbg_Update_18, -- [out std_logic]
Dbg_Rst_18 => Dbg_Rst_18, -- [out std_logic]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_18 => Dbg_TrClk_18, -- [out std_logic]
Dbg_TrData_18 => Dbg_TrData_18, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_18 => Dbg_TrReady_18, -- [out std_logic]
Dbg_TrValid_18 => Dbg_TrValid_18, -- [in std_logic]
Dbg_Clk_19 => Dbg_Clk_19, -- [out std_logic]
Dbg_TDI_19 => Dbg_TDI_19, -- [out std_logic]
Dbg_TDO_19 => Dbg_TDO_19, -- [in std_logic]
Dbg_Reg_En_19 => Dbg_Reg_En_19, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_19 => Dbg_Capture_19, -- [out std_logic]
Dbg_Shift_19 => Dbg_Shift_19, -- [out std_logic]
Dbg_Update_19 => Dbg_Update_19, -- [out std_logic]
Dbg_Rst_19 => Dbg_Rst_19, -- [out std_logic]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_19 => Dbg_TrClk_19, -- [out std_logic]
Dbg_TrData_19 => Dbg_TrData_19, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_19 => Dbg_TrReady_19, -- [out std_logic]
Dbg_TrValid_19 => Dbg_TrValid_19, -- [in std_logic]
Dbg_Clk_20 => Dbg_Clk_20, -- [out std_logic]
Dbg_TDI_20 => Dbg_TDI_20, -- [out std_logic]
Dbg_TDO_20 => Dbg_TDO_20, -- [in std_logic]
Dbg_Reg_En_20 => Dbg_Reg_En_20, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_20 => Dbg_Capture_20, -- [out std_logic]
Dbg_Shift_20 => Dbg_Shift_20, -- [out std_logic]
Dbg_Update_20 => Dbg_Update_20, -- [out std_logic]
Dbg_Rst_20 => Dbg_Rst_20, -- [out std_logic]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_20 => Dbg_TrClk_20, -- [out std_logic]
Dbg_TrData_20 => Dbg_TrData_20, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_20 => Dbg_TrReady_20, -- [out std_logic]
Dbg_TrValid_20 => Dbg_TrValid_20, -- [in std_logic]
Dbg_Clk_21 => Dbg_Clk_21, -- [out std_logic]
Dbg_TDI_21 => Dbg_TDI_21, -- [out std_logic]
Dbg_TDO_21 => Dbg_TDO_21, -- [in std_logic]
Dbg_Reg_En_21 => Dbg_Reg_En_21, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_21 => Dbg_Capture_21, -- [out std_logic]
Dbg_Shift_21 => Dbg_Shift_21, -- [out std_logic]
Dbg_Update_21 => Dbg_Update_21, -- [out std_logic]
Dbg_Rst_21 => Dbg_Rst_21, -- [out std_logic]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_21 => Dbg_TrClk_21, -- [out std_logic]
Dbg_TrData_21 => Dbg_TrData_21, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_21 => Dbg_TrReady_21, -- [out std_logic]
Dbg_TrValid_21 => Dbg_TrValid_21, -- [in std_logic]
Dbg_Clk_22 => Dbg_Clk_22, -- [out std_logic]
Dbg_TDI_22 => Dbg_TDI_22, -- [out std_logic]
Dbg_TDO_22 => Dbg_TDO_22, -- [in std_logic]
Dbg_Reg_En_22 => Dbg_Reg_En_22, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_22 => Dbg_Capture_22, -- [out std_logic]
Dbg_Shift_22 => Dbg_Shift_22, -- [out std_logic]
Dbg_Update_22 => Dbg_Update_22, -- [out std_logic]
Dbg_Rst_22 => Dbg_Rst_22, -- [out std_logic]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_22 => Dbg_TrClk_22, -- [out std_logic]
Dbg_TrData_22 => Dbg_TrData_22, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_22 => Dbg_TrReady_22, -- [out std_logic]
Dbg_TrValid_22 => Dbg_TrValid_22, -- [in std_logic]
Dbg_Clk_23 => Dbg_Clk_23, -- [out std_logic]
Dbg_TDI_23 => Dbg_TDI_23, -- [out std_logic]
Dbg_TDO_23 => Dbg_TDO_23, -- [in std_logic]
Dbg_Reg_En_23 => Dbg_Reg_En_23, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_23 => Dbg_Capture_23, -- [out std_logic]
Dbg_Shift_23 => Dbg_Shift_23, -- [out std_logic]
Dbg_Update_23 => Dbg_Update_23, -- [out std_logic]
Dbg_Rst_23 => Dbg_Rst_23, -- [out std_logic]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_23 => Dbg_TrClk_23, -- [out std_logic]
Dbg_TrData_23 => Dbg_TrData_23, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_23 => Dbg_TrReady_23, -- [out std_logic]
Dbg_TrValid_23 => Dbg_TrValid_23, -- [in std_logic]
Dbg_Clk_24 => Dbg_Clk_24, -- [out std_logic]
Dbg_TDI_24 => Dbg_TDI_24, -- [out std_logic]
Dbg_TDO_24 => Dbg_TDO_24, -- [in std_logic]
Dbg_Reg_En_24 => Dbg_Reg_En_24, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_24 => Dbg_Capture_24, -- [out std_logic]
Dbg_Shift_24 => Dbg_Shift_24, -- [out std_logic]
Dbg_Update_24 => Dbg_Update_24, -- [out std_logic]
Dbg_Rst_24 => Dbg_Rst_24, -- [out std_logic]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_24 => Dbg_TrClk_24, -- [out std_logic]
Dbg_TrData_24 => Dbg_TrData_24, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_24 => Dbg_TrReady_24, -- [out std_logic]
Dbg_TrValid_24 => Dbg_TrValid_24, -- [in std_logic]
Dbg_Clk_25 => Dbg_Clk_25, -- [out std_logic]
Dbg_TDI_25 => Dbg_TDI_25, -- [out std_logic]
Dbg_TDO_25 => Dbg_TDO_25, -- [in std_logic]
Dbg_Reg_En_25 => Dbg_Reg_En_25, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_25 => Dbg_Capture_25, -- [out std_logic]
Dbg_Shift_25 => Dbg_Shift_25, -- [out std_logic]
Dbg_Update_25 => Dbg_Update_25, -- [out std_logic]
Dbg_Rst_25 => Dbg_Rst_25, -- [out std_logic]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_25 => Dbg_TrClk_25, -- [out std_logic]
Dbg_TrData_25 => Dbg_TrData_25, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_25 => Dbg_TrReady_25, -- [out std_logic]
Dbg_TrValid_25 => Dbg_TrValid_25, -- [in std_logic]
Dbg_Clk_26 => Dbg_Clk_26, -- [out std_logic]
Dbg_TDI_26 => Dbg_TDI_26, -- [out std_logic]
Dbg_TDO_26 => Dbg_TDO_26, -- [in std_logic]
Dbg_Reg_En_26 => Dbg_Reg_En_26, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_26 => Dbg_Capture_26, -- [out std_logic]
Dbg_Shift_26 => Dbg_Shift_26, -- [out std_logic]
Dbg_Update_26 => Dbg_Update_26, -- [out std_logic]
Dbg_Rst_26 => Dbg_Rst_26, -- [out std_logic]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_26 => Dbg_TrClk_26, -- [out std_logic]
Dbg_TrData_26 => Dbg_TrData_26, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_26 => Dbg_TrReady_26, -- [out std_logic]
Dbg_TrValid_26 => Dbg_TrValid_26, -- [in std_logic]
Dbg_Clk_27 => Dbg_Clk_27, -- [out std_logic]
Dbg_TDI_27 => Dbg_TDI_27, -- [out std_logic]
Dbg_TDO_27 => Dbg_TDO_27, -- [in std_logic]
Dbg_Reg_En_27 => Dbg_Reg_En_27, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_27 => Dbg_Capture_27, -- [out std_logic]
Dbg_Shift_27 => Dbg_Shift_27, -- [out std_logic]
Dbg_Update_27 => Dbg_Update_27, -- [out std_logic]
Dbg_Rst_27 => Dbg_Rst_27, -- [out std_logic]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_27 => Dbg_TrClk_27, -- [out std_logic]
Dbg_TrData_27 => Dbg_TrData_27, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_27 => Dbg_TrReady_27, -- [out std_logic]
Dbg_TrValid_27 => Dbg_TrValid_27, -- [in std_logic]
Dbg_Clk_28 => Dbg_Clk_28, -- [out std_logic]
Dbg_TDI_28 => Dbg_TDI_28, -- [out std_logic]
Dbg_TDO_28 => Dbg_TDO_28, -- [in std_logic]
Dbg_Reg_En_28 => Dbg_Reg_En_28, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_28 => Dbg_Capture_28, -- [out std_logic]
Dbg_Shift_28 => Dbg_Shift_28, -- [out std_logic]
Dbg_Update_28 => Dbg_Update_28, -- [out std_logic]
Dbg_Rst_28 => Dbg_Rst_28, -- [out std_logic]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_28 => Dbg_TrClk_28, -- [out std_logic]
Dbg_TrData_28 => Dbg_TrData_28, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_28 => Dbg_TrReady_28, -- [out std_logic]
Dbg_TrValid_28 => Dbg_TrValid_28, -- [in std_logic]
Dbg_Clk_29 => Dbg_Clk_29, -- [out std_logic]
Dbg_TDI_29 => Dbg_TDI_29, -- [out std_logic]
Dbg_TDO_29 => Dbg_TDO_29, -- [in std_logic]
Dbg_Reg_En_29 => Dbg_Reg_En_29, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_29 => Dbg_Capture_29, -- [out std_logic]
Dbg_Shift_29 => Dbg_Shift_29, -- [out std_logic]
Dbg_Update_29 => Dbg_Update_29, -- [out std_logic]
Dbg_Rst_29 => Dbg_Rst_29, -- [out std_logic]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_29 => Dbg_TrClk_29, -- [out std_logic]
Dbg_TrData_29 => Dbg_TrData_29, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_29 => Dbg_TrReady_29, -- [out std_logic]
Dbg_TrValid_29 => Dbg_TrValid_29, -- [in std_logic]
Dbg_Clk_30 => Dbg_Clk_30, -- [out std_logic]
Dbg_TDI_30 => Dbg_TDI_30, -- [out std_logic]
Dbg_TDO_30 => Dbg_TDO_30, -- [in std_logic]
Dbg_Reg_En_30 => Dbg_Reg_En_30, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_30 => Dbg_Capture_30, -- [out std_logic]
Dbg_Shift_30 => Dbg_Shift_30, -- [out std_logic]
Dbg_Update_30 => Dbg_Update_30, -- [out std_logic]
Dbg_Rst_30 => Dbg_Rst_30, -- [out std_logic]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_30 => Dbg_TrClk_30, -- [out std_logic]
Dbg_TrData_30 => Dbg_TrData_30, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_30 => Dbg_TrReady_30, -- [out std_logic]
Dbg_TrValid_30 => Dbg_TrValid_30, -- [in std_logic]
Dbg_Clk_31 => Dbg_Clk_31, -- [out std_logic]
Dbg_TDI_31 => Dbg_TDI_31, -- [out std_logic]
Dbg_TDO_31 => Dbg_TDO_31, -- [in std_logic]
Dbg_Reg_En_31 => Dbg_Reg_En_31, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_31 => Dbg_Capture_31, -- [out std_logic]
Dbg_Shift_31 => Dbg_Shift_31, -- [out std_logic]
Dbg_Update_31 => Dbg_Update_31, -- [out std_logic]
Dbg_Rst_31 => Dbg_Rst_31, -- [out std_logic]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_31 => Dbg_TrClk_31, -- [out std_logic]
Dbg_TrData_31 => Dbg_TrData_31, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_31 => Dbg_TrReady_31, -- [out std_logic]
Dbg_TrValid_31 => Dbg_TrValid_31, -- [in std_logic]
Ext_Trig_In => ext_trig_in, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => ext_trig_ack_in, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => ext_trig_out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => ext_trig_ack_out, -- [in std_logic_vector(0 to 3)]
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
ext_trig_in <= Trig_In_0 & Trig_In_1 & Trig_In_2 & Trig_In_3;
ext_trig_ack_out <= Trig_Ack_Out_0 & Trig_Ack_Out_1 & Trig_Ack_Out_2 & Trig_Ack_Out_3;
Trig_Ack_In_0 <= ext_trig_ack_in(0);
Trig_Ack_In_1 <= ext_trig_ack_in(1);
Trig_Ack_In_2 <= ext_trig_ack_in(2);
Trig_Ack_In_3 <= ext_trig_ack_in(3);
Trig_Out_0 <= ext_trig_out(0);
Trig_Out_1 <= ext_trig_out(1);
Trig_Out_2 <= ext_trig_out(2);
Trig_Out_3 <= ext_trig_out(3);
-- Bus Master port
Use_Bus_MASTER : if (C_DBG_MEM_ACCESS = 1) generate
type LMB_vec_type is array (natural range <>) of std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_addr : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_write : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_addr_strobe : std_logic;
signal lmb_read_strobe : std_logic;
signal lmb_write_strobe : std_logic;
signal lmb_ready : std_logic;
signal lmb_wait : std_logic;
signal lmb_ue : std_logic;
signal lmb_byte_enable : std_logic_vector(0 to C_DATA_SIZE / 8 - 1);
signal lmb_addr_strobe_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec : LMB_vec_type(0 to 31);
signal lmb_ready_vec : std_logic_vector(0 to 31);
signal lmb_wait_vec : std_logic_vector(0 to 31);
signal lmb_ue_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec_q : LMB_vec_type(0 to C_EN_WIDTH - 1);
signal lmb_ready_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_wait_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_ue_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => true,
C_HAS_DIRECT_PORT => C_TRACE_AXI_MASTER
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => lmb_data_addr,
LMB_Data_Read => lmb_data_read,
LMB_Data_Write => lmb_data_write,
LMB_Addr_Strobe => lmb_addr_strobe,
LMB_Read_Strobe => lmb_read_strobe,
LMB_Write_Strobe => lmb_write_strobe,
LMB_Ready => lmb_ready,
LMB_Wait => lmb_wait,
LMB_UE => lmb_ue,
LMB_Byte_Enable => lmb_byte_enable,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
Generate_LMB_Outputs : process (mb_debug_enabled, lmb_addr_strobe)
begin -- process Generate_LMB_Outputs
lmb_addr_strobe_vec <= (others => '0');
for I in 0 to C_EN_WIDTH - 1 loop
lmb_addr_strobe_vec(I) <= lmb_addr_strobe and mb_debug_enabled(I);
end loop;
end process Generate_LMB_Outputs;
LMB_Addr_Strobe_0 <= lmb_addr_strobe_vec(0);
LMB_Addr_Strobe_1 <= lmb_addr_strobe_vec(1);
LMB_Addr_Strobe_2 <= lmb_addr_strobe_vec(2);
LMB_Addr_Strobe_3 <= lmb_addr_strobe_vec(3);
LMB_Addr_Strobe_4 <= lmb_addr_strobe_vec(4);
LMB_Addr_Strobe_5 <= lmb_addr_strobe_vec(5);
LMB_Addr_Strobe_6 <= lmb_addr_strobe_vec(6);
LMB_Addr_Strobe_7 <= lmb_addr_strobe_vec(7);
LMB_Addr_Strobe_8 <= lmb_addr_strobe_vec(8);
LMB_Addr_Strobe_9 <= lmb_addr_strobe_vec(9);
LMB_Addr_Strobe_10 <= lmb_addr_strobe_vec(10);
LMB_Addr_Strobe_11 <= lmb_addr_strobe_vec(11);
LMB_Addr_Strobe_12 <= lmb_addr_strobe_vec(12);
LMB_Addr_Strobe_13 <= lmb_addr_strobe_vec(13);
LMB_Addr_Strobe_14 <= lmb_addr_strobe_vec(14);
LMB_Addr_Strobe_15 <= lmb_addr_strobe_vec(15);
LMB_Addr_Strobe_16 <= lmb_addr_strobe_vec(16);
LMB_Addr_Strobe_17 <= lmb_addr_strobe_vec(17);
LMB_Addr_Strobe_18 <= lmb_addr_strobe_vec(18);
LMB_Addr_Strobe_19 <= lmb_addr_strobe_vec(19);
LMB_Addr_Strobe_20 <= lmb_addr_strobe_vec(20);
LMB_Addr_Strobe_21 <= lmb_addr_strobe_vec(21);
LMB_Addr_Strobe_22 <= lmb_addr_strobe_vec(22);
LMB_Addr_Strobe_23 <= lmb_addr_strobe_vec(23);
LMB_Addr_Strobe_24 <= lmb_addr_strobe_vec(24);
LMB_Addr_Strobe_25 <= lmb_addr_strobe_vec(25);
LMB_Addr_Strobe_26 <= lmb_addr_strobe_vec(26);
LMB_Addr_Strobe_27 <= lmb_addr_strobe_vec(27);
LMB_Addr_Strobe_28 <= lmb_addr_strobe_vec(28);
LMB_Addr_Strobe_29 <= lmb_addr_strobe_vec(29);
LMB_Addr_Strobe_30 <= lmb_addr_strobe_vec(30);
LMB_Addr_Strobe_31 <= lmb_addr_strobe_vec(31);
LMB_Data_Addr_0 <= lmb_data_addr;
LMB_Data_Addr_1 <= lmb_data_addr;
LMB_Data_Addr_2 <= lmb_data_addr;
LMB_Data_Addr_3 <= lmb_data_addr;
LMB_Data_Addr_4 <= lmb_data_addr;
LMB_Data_Addr_5 <= lmb_data_addr;
LMB_Data_Addr_6 <= lmb_data_addr;
LMB_Data_Addr_7 <= lmb_data_addr;
LMB_Data_Addr_8 <= lmb_data_addr;
LMB_Data_Addr_9 <= lmb_data_addr;
LMB_Data_Addr_10 <= lmb_data_addr;
LMB_Data_Addr_11 <= lmb_data_addr;
LMB_Data_Addr_12 <= lmb_data_addr;
LMB_Data_Addr_13 <= lmb_data_addr;
LMB_Data_Addr_14 <= lmb_data_addr;
LMB_Data_Addr_15 <= lmb_data_addr;
LMB_Data_Addr_16 <= lmb_data_addr;
LMB_Data_Addr_17 <= lmb_data_addr;
LMB_Data_Addr_18 <= lmb_data_addr;
LMB_Data_Addr_19 <= lmb_data_addr;
LMB_Data_Addr_20 <= lmb_data_addr;
LMB_Data_Addr_21 <= lmb_data_addr;
LMB_Data_Addr_22 <= lmb_data_addr;
LMB_Data_Addr_23 <= lmb_data_addr;
LMB_Data_Addr_24 <= lmb_data_addr;
LMB_Data_Addr_25 <= lmb_data_addr;
LMB_Data_Addr_26 <= lmb_data_addr;
LMB_Data_Addr_27 <= lmb_data_addr;
LMB_Data_Addr_28 <= lmb_data_addr;
LMB_Data_Addr_29 <= lmb_data_addr;
LMB_Data_Addr_30 <= lmb_data_addr;
LMB_Data_Addr_31 <= lmb_data_addr;
LMB_Data_write_0 <= lmb_data_write;
LMB_Data_write_1 <= lmb_data_write;
LMB_Data_write_2 <= lmb_data_write;
LMB_Data_write_3 <= lmb_data_write;
LMB_Data_write_4 <= lmb_data_write;
LMB_Data_write_5 <= lmb_data_write;
LMB_Data_write_6 <= lmb_data_write;
LMB_Data_write_7 <= lmb_data_write;
LMB_Data_write_8 <= lmb_data_write;
LMB_Data_write_9 <= lmb_data_write;
LMB_Data_write_10 <= lmb_data_write;
LMB_Data_write_11 <= lmb_data_write;
LMB_Data_write_12 <= lmb_data_write;
LMB_Data_write_13 <= lmb_data_write;
LMB_Data_write_14 <= lmb_data_write;
LMB_Data_write_15 <= lmb_data_write;
LMB_Data_write_16 <= lmb_data_write;
LMB_Data_write_17 <= lmb_data_write;
LMB_Data_write_18 <= lmb_data_write;
LMB_Data_write_19 <= lmb_data_write;
LMB_Data_write_20 <= lmb_data_write;
LMB_Data_write_21 <= lmb_data_write;
LMB_Data_write_22 <= lmb_data_write;
LMB_Data_write_23 <= lmb_data_write;
LMB_Data_write_24 <= lmb_data_write;
LMB_Data_write_25 <= lmb_data_write;
LMB_Data_write_26 <= lmb_data_write;
LMB_Data_write_27 <= lmb_data_write;
LMB_Data_write_28 <= lmb_data_write;
LMB_Data_write_29 <= lmb_data_write;
LMB_Data_write_30 <= lmb_data_write;
LMB_Data_write_31 <= lmb_data_write;
LMB_Read_strobe_0 <= lmb_read_strobe;
LMB_Read_strobe_1 <= lmb_read_strobe;
LMB_Read_strobe_2 <= lmb_read_strobe;
LMB_Read_strobe_3 <= lmb_read_strobe;
LMB_Read_strobe_4 <= lmb_read_strobe;
LMB_Read_strobe_5 <= lmb_read_strobe;
LMB_Read_strobe_6 <= lmb_read_strobe;
LMB_Read_strobe_7 <= lmb_read_strobe;
LMB_Read_strobe_8 <= lmb_read_strobe;
LMB_Read_strobe_9 <= lmb_read_strobe;
LMB_Read_strobe_10 <= lmb_read_strobe;
LMB_Read_strobe_11 <= lmb_read_strobe;
LMB_Read_strobe_12 <= lmb_read_strobe;
LMB_Read_strobe_13 <= lmb_read_strobe;
LMB_Read_strobe_14 <= lmb_read_strobe;
LMB_Read_strobe_15 <= lmb_read_strobe;
LMB_Read_strobe_16 <= lmb_read_strobe;
LMB_Read_strobe_17 <= lmb_read_strobe;
LMB_Read_strobe_18 <= lmb_read_strobe;
LMB_Read_strobe_19 <= lmb_read_strobe;
LMB_Read_strobe_20 <= lmb_read_strobe;
LMB_Read_strobe_21 <= lmb_read_strobe;
LMB_Read_strobe_22 <= lmb_read_strobe;
LMB_Read_strobe_23 <= lmb_read_strobe;
LMB_Read_strobe_24 <= lmb_read_strobe;
LMB_Read_strobe_25 <= lmb_read_strobe;
LMB_Read_strobe_26 <= lmb_read_strobe;
LMB_Read_strobe_27 <= lmb_read_strobe;
LMB_Read_strobe_28 <= lmb_read_strobe;
LMB_Read_strobe_29 <= lmb_read_strobe;
LMB_Read_strobe_30 <= lmb_read_strobe;
LMB_Read_strobe_31 <= lmb_read_strobe;
LMB_Write_strobe_0 <= lmb_write_strobe;
LMB_Write_strobe_1 <= lmb_write_strobe;
LMB_Write_strobe_2 <= lmb_write_strobe;
LMB_Write_strobe_3 <= lmb_write_strobe;
LMB_Write_strobe_4 <= lmb_write_strobe;
LMB_Write_strobe_5 <= lmb_write_strobe;
LMB_Write_strobe_6 <= lmb_write_strobe;
LMB_Write_strobe_7 <= lmb_write_strobe;
LMB_Write_strobe_8 <= lmb_write_strobe;
LMB_Write_strobe_9 <= lmb_write_strobe;
LMB_Write_strobe_10 <= lmb_write_strobe;
LMB_Write_strobe_11 <= lmb_write_strobe;
LMB_Write_strobe_12 <= lmb_write_strobe;
LMB_Write_strobe_13 <= lmb_write_strobe;
LMB_Write_strobe_14 <= lmb_write_strobe;
LMB_Write_strobe_15 <= lmb_write_strobe;
LMB_Write_strobe_16 <= lmb_write_strobe;
LMB_Write_strobe_17 <= lmb_write_strobe;
LMB_Write_strobe_18 <= lmb_write_strobe;
LMB_Write_strobe_19 <= lmb_write_strobe;
LMB_Write_strobe_20 <= lmb_write_strobe;
LMB_Write_strobe_21 <= lmb_write_strobe;
LMB_Write_strobe_22 <= lmb_write_strobe;
LMB_Write_strobe_23 <= lmb_write_strobe;
LMB_Write_strobe_24 <= lmb_write_strobe;
LMB_Write_strobe_25 <= lmb_write_strobe;
LMB_Write_strobe_26 <= lmb_write_strobe;
LMB_Write_strobe_27 <= lmb_write_strobe;
LMB_Write_strobe_28 <= lmb_write_strobe;
LMB_Write_strobe_29 <= lmb_write_strobe;
LMB_Write_strobe_30 <= lmb_write_strobe;
LMB_Write_strobe_31 <= lmb_write_strobe;
LMB_Byte_enable_0 <= lmb_byte_enable;
LMB_Byte_enable_1 <= lmb_byte_enable;
LMB_Byte_enable_2 <= lmb_byte_enable;
LMB_Byte_enable_3 <= lmb_byte_enable;
LMB_Byte_enable_4 <= lmb_byte_enable;
LMB_Byte_enable_5 <= lmb_byte_enable;
LMB_Byte_enable_6 <= lmb_byte_enable;
LMB_Byte_enable_7 <= lmb_byte_enable;
LMB_Byte_enable_8 <= lmb_byte_enable;
LMB_Byte_enable_9 <= lmb_byte_enable;
LMB_Byte_enable_10 <= lmb_byte_enable;
LMB_Byte_enable_11 <= lmb_byte_enable;
LMB_Byte_enable_12 <= lmb_byte_enable;
LMB_Byte_enable_13 <= lmb_byte_enable;
LMB_Byte_enable_14 <= lmb_byte_enable;
LMB_Byte_enable_15 <= lmb_byte_enable;
LMB_Byte_enable_16 <= lmb_byte_enable;
LMB_Byte_enable_17 <= lmb_byte_enable;
LMB_Byte_enable_18 <= lmb_byte_enable;
LMB_Byte_enable_19 <= lmb_byte_enable;
LMB_Byte_enable_20 <= lmb_byte_enable;
LMB_Byte_enable_21 <= lmb_byte_enable;
LMB_Byte_enable_22 <= lmb_byte_enable;
LMB_Byte_enable_23 <= lmb_byte_enable;
LMB_Byte_enable_24 <= lmb_byte_enable;
LMB_Byte_enable_25 <= lmb_byte_enable;
LMB_Byte_enable_26 <= lmb_byte_enable;
LMB_Byte_enable_27 <= lmb_byte_enable;
LMB_Byte_enable_28 <= lmb_byte_enable;
LMB_Byte_enable_29 <= lmb_byte_enable;
LMB_Byte_enable_30 <= lmb_byte_enable;
LMB_Byte_enable_31 <= lmb_byte_enable;
Generate_LMB_Inputs : process (mb_debug_enabled, lmb_data_read_vec_q, lmb_ready_vec_q, lmb_wait_vec_q, lmb_ue_vec_q)
variable data_mask : std_logic_vector(0 to C_DATA_SIZE - 1);
variable data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
variable ready : std_logic;
variable wait_i : std_logic;
variable ue : std_logic;
begin -- process Generate_LMB_Inputs
data_read := (others => '0');
ready := '0';
wait_i := '0';
ue := '0';
for I in 0 to C_EN_WIDTH - 1 loop
data_mask := (0 to C_DATA_SIZE - 1 => mb_debug_enabled(I));
data_read := data_read or (lmb_data_read_vec_q(I) and data_mask);
ready := ready or (lmb_ready_vec_q(I) and mb_debug_enabled(I));
wait_i := wait_i or (lmb_wait_vec_q(I) and mb_debug_enabled(I));
ue := ue or (lmb_ue_vec_q(I) and mb_debug_enabled(I));
end loop;
lmb_data_read <= data_read;
lmb_ready <= ready;
lmb_wait <= wait_i;
lmb_ue <= ue;
end process Generate_LMB_Inputs;
Clock_LMB_Inputs : process (M_AXI_ACLK)
begin
if M_AXI_ACLK'event and M_AXI_ACLK = '1' then -- rising clock edge
for I in 0 to C_EN_WIDTH - 1 loop
lmb_data_read_vec_q(I) <= lmb_data_read_vec(I);
lmb_ready_vec_q(I) <= lmb_ready_vec(I);
lmb_wait_vec_q(I) <= lmb_wait_vec(I);
lmb_ue_vec_q(I) <= lmb_ue_vec(I);
end loop;
end if;
end process Clock_LMB_Inputs;
lmb_data_read_vec(0) <= LMB_Data_Read_0;
lmb_data_read_vec(1) <= LMB_Data_Read_1;
lmb_data_read_vec(2) <= LMB_Data_Read_2;
lmb_data_read_vec(3) <= LMB_Data_Read_3;
lmb_data_read_vec(4) <= LMB_Data_Read_4;
lmb_data_read_vec(5) <= LMB_Data_Read_5;
lmb_data_read_vec(6) <= LMB_Data_Read_6;
lmb_data_read_vec(7) <= LMB_Data_Read_7;
lmb_data_read_vec(8) <= LMB_Data_Read_8;
lmb_data_read_vec(9) <= LMB_Data_Read_9;
lmb_data_read_vec(10) <= LMB_Data_Read_10;
lmb_data_read_vec(11) <= LMB_Data_Read_11;
lmb_data_read_vec(12) <= LMB_Data_Read_12;
lmb_data_read_vec(13) <= LMB_Data_Read_13;
lmb_data_read_vec(14) <= LMB_Data_Read_14;
lmb_data_read_vec(15) <= LMB_Data_Read_15;
lmb_data_read_vec(16) <= LMB_Data_Read_16;
lmb_data_read_vec(17) <= LMB_Data_Read_17;
lmb_data_read_vec(18) <= LMB_Data_Read_18;
lmb_data_read_vec(19) <= LMB_Data_Read_19;
lmb_data_read_vec(20) <= LMB_Data_Read_20;
lmb_data_read_vec(21) <= LMB_Data_Read_21;
lmb_data_read_vec(22) <= LMB_Data_Read_22;
lmb_data_read_vec(23) <= LMB_Data_Read_23;
lmb_data_read_vec(24) <= LMB_Data_Read_24;
lmb_data_read_vec(25) <= LMB_Data_Read_25;
lmb_data_read_vec(26) <= LMB_Data_Read_26;
lmb_data_read_vec(27) <= LMB_Data_Read_27;
lmb_data_read_vec(28) <= LMB_Data_Read_28;
lmb_data_read_vec(29) <= LMB_Data_Read_29;
lmb_data_read_vec(30) <= LMB_Data_Read_30;
lmb_data_read_vec(31) <= LMB_Data_Read_31;
lmb_ready_vec(0) <= LMB_Ready_0;
lmb_ready_vec(1) <= LMB_Ready_1;
lmb_ready_vec(2) <= LMB_Ready_2;
lmb_ready_vec(3) <= LMB_Ready_3;
lmb_ready_vec(4) <= LMB_Ready_4;
lmb_ready_vec(5) <= LMB_Ready_5;
lmb_ready_vec(6) <= LMB_Ready_6;
lmb_ready_vec(7) <= LMB_Ready_7;
lmb_ready_vec(8) <= LMB_Ready_8;
lmb_ready_vec(9) <= LMB_Ready_9;
lmb_ready_vec(10) <= LMB_Ready_10;
lmb_ready_vec(11) <= LMB_Ready_11;
lmb_ready_vec(12) <= LMB_Ready_12;
lmb_ready_vec(13) <= LMB_Ready_13;
lmb_ready_vec(14) <= LMB_Ready_14;
lmb_ready_vec(15) <= LMB_Ready_15;
lmb_ready_vec(16) <= LMB_Ready_16;
lmb_ready_vec(17) <= LMB_Ready_17;
lmb_ready_vec(18) <= LMB_Ready_18;
lmb_ready_vec(19) <= LMB_Ready_19;
lmb_ready_vec(20) <= LMB_Ready_20;
lmb_ready_vec(21) <= LMB_Ready_21;
lmb_ready_vec(22) <= LMB_Ready_22;
lmb_ready_vec(23) <= LMB_Ready_23;
lmb_ready_vec(24) <= LMB_Ready_24;
lmb_ready_vec(25) <= LMB_Ready_25;
lmb_ready_vec(26) <= LMB_Ready_26;
lmb_ready_vec(27) <= LMB_Ready_27;
lmb_ready_vec(28) <= LMB_Ready_28;
lmb_ready_vec(29) <= LMB_Ready_29;
lmb_ready_vec(30) <= LMB_Ready_30;
lmb_ready_vec(31) <= LMB_Ready_31;
lmb_wait_vec(0) <= LMB_Wait_0;
lmb_wait_vec(1) <= LMB_Wait_1;
lmb_wait_vec(2) <= LMB_Wait_2;
lmb_wait_vec(3) <= LMB_Wait_3;
lmb_wait_vec(4) <= LMB_Wait_4;
lmb_wait_vec(5) <= LMB_Wait_5;
lmb_wait_vec(6) <= LMB_Wait_6;
lmb_wait_vec(7) <= LMB_Wait_7;
lmb_wait_vec(8) <= LMB_Wait_8;
lmb_wait_vec(9) <= LMB_Wait_9;
lmb_wait_vec(10) <= LMB_Wait_10;
lmb_wait_vec(11) <= LMB_Wait_11;
lmb_wait_vec(12) <= LMB_Wait_12;
lmb_wait_vec(13) <= LMB_Wait_13;
lmb_wait_vec(14) <= LMB_Wait_14;
lmb_wait_vec(15) <= LMB_Wait_15;
lmb_wait_vec(16) <= LMB_Wait_16;
lmb_wait_vec(17) <= LMB_Wait_17;
lmb_wait_vec(18) <= LMB_Wait_18;
lmb_wait_vec(19) <= LMB_Wait_19;
lmb_wait_vec(20) <= LMB_Wait_20;
lmb_wait_vec(21) <= LMB_Wait_21;
lmb_wait_vec(22) <= LMB_Wait_22;
lmb_wait_vec(23) <= LMB_Wait_23;
lmb_wait_vec(24) <= LMB_Wait_24;
lmb_wait_vec(25) <= LMB_Wait_25;
lmb_wait_vec(26) <= LMB_Wait_26;
lmb_wait_vec(27) <= LMB_Wait_27;
lmb_wait_vec(28) <= LMB_Wait_28;
lmb_wait_vec(29) <= LMB_Wait_29;
lmb_wait_vec(30) <= LMB_Wait_30;
lmb_wait_vec(31) <= LMB_Wait_31;
lmb_ue_vec(0) <= LMB_UE_0;
lmb_ue_vec(1) <= LMB_UE_1;
lmb_ue_vec(2) <= LMB_UE_2;
lmb_ue_vec(3) <= LMB_UE_3;
lmb_ue_vec(4) <= LMB_UE_4;
lmb_ue_vec(5) <= LMB_UE_5;
lmb_ue_vec(6) <= LMB_UE_6;
lmb_ue_vec(7) <= LMB_UE_7;
lmb_ue_vec(8) <= LMB_UE_8;
lmb_ue_vec(9) <= LMB_UE_9;
lmb_ue_vec(10) <= LMB_UE_10;
lmb_ue_vec(11) <= LMB_UE_11;
lmb_ue_vec(12) <= LMB_UE_12;
lmb_ue_vec(13) <= LMB_UE_13;
lmb_ue_vec(14) <= LMB_UE_14;
lmb_ue_vec(15) <= LMB_UE_15;
lmb_ue_vec(16) <= LMB_UE_16;
lmb_ue_vec(17) <= LMB_UE_17;
lmb_ue_vec(18) <= LMB_UE_18;
lmb_ue_vec(19) <= LMB_UE_19;
lmb_ue_vec(20) <= LMB_UE_20;
lmb_ue_vec(21) <= LMB_UE_21;
lmb_ue_vec(22) <= LMB_UE_22;
lmb_ue_vec(23) <= LMB_UE_23;
lmb_ue_vec(24) <= LMB_UE_24;
lmb_ue_vec(25) <= LMB_UE_25;
lmb_ue_vec(26) <= LMB_UE_26;
lmb_ue_vec(27) <= LMB_UE_27;
lmb_ue_vec(28) <= LMB_UE_28;
lmb_ue_vec(29) <= LMB_UE_29;
lmb_ue_vec(30) <= LMB_UE_30;
lmb_ue_vec(31) <= LMB_UE_31;
end generate Use_Bus_MASTER;
Use_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and C_TRACE_AXI_MASTER) generate
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => false,
C_HAS_DIRECT_PORT => true
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => open,
LMB_Data_Read => (others => '0'),
LMB_Data_Write => open,
LMB_Addr_Strobe => open,
LMB_Read_Strobe => open,
LMB_Write_Strobe => open,
LMB_Ready => '0',
LMB_Wait => '0',
LMB_UE => '0',
LMB_Byte_Enable => open,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
end generate Use_Bus_MASTER_AXI;
No_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and not C_TRACE_AXI_MASTER) generate
begin
master_rd_idle <= '1';
master_rd_resp <= "00";
master_wr_idle <= '1';
master_wr_resp <= "00";
master_data_out <= (others => '0');
master_data_exists <= '0';
master_data_empty <= '1';
master_dwr_next <= '0';
master_dwr_done <= '0';
master_dwr_resp <= (others => '0');
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= (others => '0');
M_AXI_AWLEN <= (others => '0');
M_AXI_AWSIZE <= (others => '0');
M_AXI_AWBURST <= (others => '0');
M_AXI_AWLOCK <= '0';
M_AXI_AWCACHE <= (others => '0');
M_AXI_AWPROT <= (others => '0');
M_AXI_AWQOS <= (others => '0');
M_AXI_AWVALID <= '0';
M_AXI_WDATA <= (others => '0');
M_AXI_WSTRB <= (others => '0');
M_AXI_WLAST <= '0';
M_AXI_WVALID <= '0';
M_AXI_BREADY <= '0';
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= (others => '0');
M_AXI_ARBURST <= (others => '0');
M_AXI_ARLOCK <= '0';
M_AXI_ARCACHE <= (others => '0');
M_AXI_ARPROT <= (others => '0');
M_AXI_ARQOS <= (others => '0');
M_AXI_ARVALID <= '0';
M_AXI_RREADY <= '0';
end generate No_Bus_MASTER_AXI;
No_Bus_MASTER_LMB : if (C_DBG_MEM_ACCESS = 0) generate
begin
LMB_Data_Addr_0 <= (others => '0');
LMB_Data_Write_0 <= (others => '0');
LMB_Addr_Strobe_0 <= '0';
LMB_Read_Strobe_0 <= '0';
LMB_Write_Strobe_0 <= '0';
LMB_Byte_Enable_0 <= (others => '0');
LMB_Data_Addr_1 <= (others => '0');
LMB_Data_Write_1 <= (others => '0');
LMB_Addr_Strobe_1 <= '0';
LMB_Read_Strobe_1 <= '0';
LMB_Write_Strobe_1 <= '0';
LMB_Byte_Enable_1 <= (others => '0');
LMB_Data_Addr_2 <= (others => '0');
LMB_Data_Write_2 <= (others => '0');
LMB_Addr_Strobe_2 <= '0';
LMB_Read_Strobe_2 <= '0';
LMB_Write_Strobe_2 <= '0';
LMB_Byte_Enable_2 <= (others => '0');
LMB_Data_Addr_3 <= (others => '0');
LMB_Data_Write_3 <= (others => '0');
LMB_Addr_Strobe_3 <= '0';
LMB_Read_Strobe_3 <= '0';
LMB_Write_Strobe_3 <= '0';
LMB_Byte_Enable_3 <= (others => '0');
LMB_Data_Addr_4 <= (others => '0');
LMB_Data_Write_4 <= (others => '0');
LMB_Addr_Strobe_4 <= '0';
LMB_Read_Strobe_4 <= '0';
LMB_Write_Strobe_4 <= '0';
LMB_Byte_Enable_4 <= (others => '0');
LMB_Data_Addr_5 <= (others => '0');
LMB_Data_Write_5 <= (others => '0');
LMB_Addr_Strobe_5 <= '0';
LMB_Read_Strobe_5 <= '0';
LMB_Write_Strobe_5 <= '0';
LMB_Byte_Enable_5 <= (others => '0');
LMB_Data_Addr_6 <= (others => '0');
LMB_Data_Write_6 <= (others => '0');
LMB_Addr_Strobe_6 <= '0';
LMB_Read_Strobe_6 <= '0';
LMB_Write_Strobe_6 <= '0';
LMB_Byte_Enable_6 <= (others => '0');
LMB_Data_Addr_7 <= (others => '0');
LMB_Data_Write_7 <= (others => '0');
LMB_Addr_Strobe_7 <= '0';
LMB_Read_Strobe_7 <= '0';
LMB_Write_Strobe_7 <= '0';
LMB_Byte_Enable_7 <= (others => '0');
LMB_Data_Addr_8 <= (others => '0');
LMB_Data_Write_8 <= (others => '0');
LMB_Addr_Strobe_8 <= '0';
LMB_Read_Strobe_8 <= '0';
LMB_Write_Strobe_8 <= '0';
LMB_Byte_Enable_8 <= (others => '0');
LMB_Data_Addr_9 <= (others => '0');
LMB_Data_Write_9 <= (others => '0');
LMB_Addr_Strobe_9 <= '0';
LMB_Read_Strobe_9 <= '0';
LMB_Write_Strobe_9 <= '0';
LMB_Byte_Enable_9 <= (others => '0');
LMB_Data_Addr_10 <= (others => '0');
LMB_Data_Write_10 <= (others => '0');
LMB_Addr_Strobe_10 <= '0';
LMB_Read_Strobe_10 <= '0';
LMB_Write_Strobe_10 <= '0';
LMB_Byte_Enable_10 <= (others => '0');
LMB_Data_Addr_11 <= (others => '0');
LMB_Data_Write_11 <= (others => '0');
LMB_Addr_Strobe_11 <= '0';
LMB_Read_Strobe_11 <= '0';
LMB_Write_Strobe_11 <= '0';
LMB_Byte_Enable_11 <= (others => '0');
LMB_Data_Addr_12 <= (others => '0');
LMB_Data_Write_12 <= (others => '0');
LMB_Addr_Strobe_12 <= '0';
LMB_Read_Strobe_12 <= '0';
LMB_Write_Strobe_12 <= '0';
LMB_Byte_Enable_12 <= (others => '0');
LMB_Data_Addr_13 <= (others => '0');
LMB_Data_Write_13 <= (others => '0');
LMB_Addr_Strobe_13 <= '0';
LMB_Read_Strobe_13 <= '0';
LMB_Write_Strobe_13 <= '0';
LMB_Byte_Enable_13 <= (others => '0');
LMB_Data_Addr_14 <= (others => '0');
LMB_Data_Write_14 <= (others => '0');
LMB_Addr_Strobe_14 <= '0';
LMB_Read_Strobe_14 <= '0';
LMB_Write_Strobe_14 <= '0';
LMB_Byte_Enable_14 <= (others => '0');
LMB_Data_Addr_15 <= (others => '0');
LMB_Data_Write_15 <= (others => '0');
LMB_Addr_Strobe_15 <= '0';
LMB_Read_Strobe_15 <= '0';
LMB_Write_Strobe_15 <= '0';
LMB_Byte_Enable_15 <= (others => '0');
LMB_Data_Addr_16 <= (others => '0');
LMB_Data_Write_16 <= (others => '0');
LMB_Addr_Strobe_16 <= '0';
LMB_Read_Strobe_16 <= '0';
LMB_Write_Strobe_16 <= '0';
LMB_Byte_Enable_16 <= (others => '0');
LMB_Data_Addr_17 <= (others => '0');
LMB_Data_Write_17 <= (others => '0');
LMB_Addr_Strobe_17 <= '0';
LMB_Read_Strobe_17 <= '0';
LMB_Write_Strobe_17 <= '0';
LMB_Byte_Enable_17 <= (others => '0');
LMB_Data_Addr_18 <= (others => '0');
LMB_Data_Write_18 <= (others => '0');
LMB_Addr_Strobe_18 <= '0';
LMB_Read_Strobe_18 <= '0';
LMB_Write_Strobe_18 <= '0';
LMB_Byte_Enable_18 <= (others => '0');
LMB_Data_Addr_19 <= (others => '0');
LMB_Data_Write_19 <= (others => '0');
LMB_Addr_Strobe_19 <= '0';
LMB_Read_Strobe_19 <= '0';
LMB_Write_Strobe_19 <= '0';
LMB_Byte_Enable_19 <= (others => '0');
LMB_Data_Addr_20 <= (others => '0');
LMB_Data_Write_20 <= (others => '0');
LMB_Addr_Strobe_20 <= '0';
LMB_Read_Strobe_20 <= '0';
LMB_Write_Strobe_20 <= '0';
LMB_Byte_Enable_20 <= (others => '0');
LMB_Data_Addr_21 <= (others => '0');
LMB_Data_Write_21 <= (others => '0');
LMB_Addr_Strobe_21 <= '0';
LMB_Read_Strobe_21 <= '0';
LMB_Write_Strobe_21 <= '0';
LMB_Byte_Enable_21 <= (others => '0');
LMB_Data_Addr_22 <= (others => '0');
LMB_Data_Write_22 <= (others => '0');
LMB_Addr_Strobe_22 <= '0';
LMB_Read_Strobe_22 <= '0';
LMB_Write_Strobe_22 <= '0';
LMB_Byte_Enable_22 <= (others => '0');
LMB_Data_Addr_23 <= (others => '0');
LMB_Data_Write_23 <= (others => '0');
LMB_Addr_Strobe_23 <= '0';
LMB_Read_Strobe_23 <= '0';
LMB_Write_Strobe_23 <= '0';
LMB_Byte_Enable_23 <= (others => '0');
LMB_Data_Addr_24 <= (others => '0');
LMB_Data_Write_24 <= (others => '0');
LMB_Addr_Strobe_24 <= '0';
LMB_Read_Strobe_24 <= '0';
LMB_Write_Strobe_24 <= '0';
LMB_Byte_Enable_24 <= (others => '0');
LMB_Data_Addr_25 <= (others => '0');
LMB_Data_Write_25 <= (others => '0');
LMB_Addr_Strobe_25 <= '0';
LMB_Read_Strobe_25 <= '0';
LMB_Write_Strobe_25 <= '0';
LMB_Byte_Enable_25 <= (others => '0');
LMB_Data_Addr_26 <= (others => '0');
LMB_Data_Write_26 <= (others => '0');
LMB_Addr_Strobe_26 <= '0';
LMB_Read_Strobe_26 <= '0';
LMB_Write_Strobe_26 <= '0';
LMB_Byte_Enable_26 <= (others => '0');
LMB_Data_Addr_27 <= (others => '0');
LMB_Data_Write_27 <= (others => '0');
LMB_Addr_Strobe_27 <= '0';
LMB_Read_Strobe_27 <= '0';
LMB_Write_Strobe_27 <= '0';
LMB_Byte_Enable_27 <= (others => '0');
LMB_Data_Addr_28 <= (others => '0');
LMB_Data_Write_28 <= (others => '0');
LMB_Addr_Strobe_28 <= '0';
LMB_Read_Strobe_28 <= '0';
LMB_Write_Strobe_28 <= '0';
LMB_Byte_Enable_28 <= (others => '0');
LMB_Data_Addr_29 <= (others => '0');
LMB_Data_Write_29 <= (others => '0');
LMB_Addr_Strobe_29 <= '0';
LMB_Read_Strobe_29 <= '0';
LMB_Write_Strobe_29 <= '0';
LMB_Byte_Enable_29 <= (others => '0');
LMB_Data_Addr_30 <= (others => '0');
LMB_Data_Write_30 <= (others => '0');
LMB_Addr_Strobe_30 <= '0';
LMB_Read_Strobe_30 <= '0';
LMB_Write_Strobe_30 <= '0';
LMB_Byte_Enable_30 <= (others => '0');
LMB_Data_Addr_31 <= (others => '0');
LMB_Data_Write_31 <= (others => '0');
LMB_Addr_Strobe_31 <= '0';
LMB_Read_Strobe_31 <= '0';
LMB_Write_Strobe_31 <= '0';
LMB_Byte_Enable_31 <= (others => '0');
end generate No_Bus_MASTER_LMB;
Use_AXI_IPIF : if (C_USE_UART = 1) or (C_DBG_REG_ACCESS = 1) generate
begin
-- ip2bus_data assignment - as core may use less than 32 bits
ip2bus_data(C_S_AXI_DATA_WIDTH-1 downto C_REG_DATA_WIDTH) <= (others => '0');
---------------------------------------------------------------------------
-- AXI lite IPIF
---------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map (
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end generate Use_AXI_IPIF;
No_AXI_IPIF : if (C_USE_UART = 0) and (C_DBG_REG_ACCESS = 0) generate
begin
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
S_AXI_BRESP <= (others => '0');
S_AXI_BVALID <= '0';
S_AXI_ARREADY <= '0';
S_AXI_RDATA <= (others => '0');
S_AXI_RRESP <= (others => '0');
S_AXI_RVALID <= '0';
bus2ip_clk <= '0';
bus2ip_resetn <= '0';
bus2ip_data <= (others => '0');
bus2ip_rdce <= (others => '0');
bus2ip_wrce <= (others => '0');
bus2ip_cs <= (others => '0');
end generate No_AXI_IPIF;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2006-10-27 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
-- stefana 2014-04-30 Added external trace support
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library mdm_v3_2;
use mdm_v3_2.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
entity MDM is
generic (
C_FAMILY : string := "virtex7";
C_JTAG_CHAIN : integer := 2;
C_USE_BSCAN : integer := 0;
C_USE_CONFIG_RESET : integer := 0;
C_INTERCONNECT : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_FFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"0000_0000";
C_MB_DBG_PORTS : integer := 1;
C_DBG_REG_ACCESS : integer := 0;
C_DBG_MEM_ACCESS : integer := 0;
C_USE_UART : integer := 1;
C_USE_CROSS_TRIGGER : integer := 0;
C_TRACE_OUTPUT : integer := 0;
C_TRACE_DATA_WIDTH : integer range 2 to 32 := 32;
C_TRACE_CLK_FREQ_HZ : integer := 200000000;
C_TRACE_CLK_OUT_PHASE : integer range 0 to 360 := 90;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_THREAD_ID_WIDTH : integer := 1;
C_DATA_SIZE : integer range 32 to 32 := 32;
C_M_AXIS_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXIS_ID_WIDTH : integer range 1 to 7 := 7
);
port (
-- Global signals
Config_Reset : in std_logic := '0';
Scan_Reset_Sel : in std_logic := '0';
Scan_Reset : in std_logic := '0';
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- External cross trigger signals
Trig_In_0 : in std_logic;
Trig_Ack_In_0 : out std_logic;
Trig_Out_0 : out std_logic;
Trig_Ack_Out_0 : in std_logic;
Trig_In_1 : in std_logic;
Trig_Ack_In_1 : out std_logic;
Trig_Out_1 : out std_logic;
Trig_Ack_Out_1 : in std_logic;
Trig_In_2 : in std_logic;
Trig_Ack_In_2 : out std_logic;
Trig_Out_2 : out std_logic;
Trig_Ack_Out_2 : in std_logic;
Trig_In_3 : in std_logic;
Trig_Ack_In_3 : out std_logic;
Trig_Out_3 : out std_logic;
Trig_Ack_Out_3 : in std_logic;
-- AXI slave signals
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Bus master signals
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
LMB_Data_Addr_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_0 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_0 : out std_logic;
LMB_Read_Strobe_0 : out std_logic;
LMB_Write_Strobe_0 : out std_logic;
LMB_Ready_0 : in std_logic;
LMB_Wait_0 : in std_logic;
LMB_CE_0 : in std_logic;
LMB_UE_0 : in std_logic;
LMB_Byte_Enable_0 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_1 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_1 : out std_logic;
LMB_Read_Strobe_1 : out std_logic;
LMB_Write_Strobe_1 : out std_logic;
LMB_Ready_1 : in std_logic;
LMB_Wait_1 : in std_logic;
LMB_CE_1 : in std_logic;
LMB_UE_1 : in std_logic;
LMB_Byte_Enable_1 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_2 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_2 : out std_logic;
LMB_Read_Strobe_2 : out std_logic;
LMB_Write_Strobe_2 : out std_logic;
LMB_Ready_2 : in std_logic;
LMB_Wait_2 : in std_logic;
LMB_CE_2 : in std_logic;
LMB_UE_2 : in std_logic;
LMB_Byte_Enable_2 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_3 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_3 : out std_logic;
LMB_Read_Strobe_3 : out std_logic;
LMB_Write_Strobe_3 : out std_logic;
LMB_Ready_3 : in std_logic;
LMB_Wait_3 : in std_logic;
LMB_CE_3 : in std_logic;
LMB_UE_3 : in std_logic;
LMB_Byte_Enable_3 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_4 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_4 : out std_logic;
LMB_Read_Strobe_4 : out std_logic;
LMB_Write_Strobe_4 : out std_logic;
LMB_Ready_4 : in std_logic;
LMB_Wait_4 : in std_logic;
LMB_CE_4 : in std_logic;
LMB_UE_4 : in std_logic;
LMB_Byte_Enable_4 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_5 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_5 : out std_logic;
LMB_Read_Strobe_5 : out std_logic;
LMB_Write_Strobe_5 : out std_logic;
LMB_Ready_5 : in std_logic;
LMB_Wait_5 : in std_logic;
LMB_CE_5 : in std_logic;
LMB_UE_5 : in std_logic;
LMB_Byte_Enable_5 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_6 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_6 : out std_logic;
LMB_Read_Strobe_6 : out std_logic;
LMB_Write_Strobe_6 : out std_logic;
LMB_Ready_6 : in std_logic;
LMB_Wait_6 : in std_logic;
LMB_CE_6 : in std_logic;
LMB_UE_6 : in std_logic;
LMB_Byte_Enable_6 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_7 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_7 : out std_logic;
LMB_Read_Strobe_7 : out std_logic;
LMB_Write_Strobe_7 : out std_logic;
LMB_Ready_7 : in std_logic;
LMB_Wait_7 : in std_logic;
LMB_CE_7 : in std_logic;
LMB_UE_7 : in std_logic;
LMB_Byte_Enable_7 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_8 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_8 : out std_logic;
LMB_Read_Strobe_8 : out std_logic;
LMB_Write_Strobe_8 : out std_logic;
LMB_Ready_8 : in std_logic;
LMB_Wait_8 : in std_logic;
LMB_CE_8 : in std_logic;
LMB_UE_8 : in std_logic;
LMB_Byte_Enable_8 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_9 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_9 : out std_logic;
LMB_Read_Strobe_9 : out std_logic;
LMB_Write_Strobe_9 : out std_logic;
LMB_Ready_9 : in std_logic;
LMB_Wait_9 : in std_logic;
LMB_CE_9 : in std_logic;
LMB_UE_9 : in std_logic;
LMB_Byte_Enable_9 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_10 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_10 : out std_logic;
LMB_Read_Strobe_10 : out std_logic;
LMB_Write_Strobe_10 : out std_logic;
LMB_Ready_10 : in std_logic;
LMB_Wait_10 : in std_logic;
LMB_CE_10 : in std_logic;
LMB_UE_10 : in std_logic;
LMB_Byte_Enable_10 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_11 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_11 : out std_logic;
LMB_Read_Strobe_11 : out std_logic;
LMB_Write_Strobe_11 : out std_logic;
LMB_Ready_11 : in std_logic;
LMB_Wait_11 : in std_logic;
LMB_CE_11 : in std_logic;
LMB_UE_11 : in std_logic;
LMB_Byte_Enable_11 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_12 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_12 : out std_logic;
LMB_Read_Strobe_12 : out std_logic;
LMB_Write_Strobe_12 : out std_logic;
LMB_Ready_12 : in std_logic;
LMB_Wait_12 : in std_logic;
LMB_CE_12 : in std_logic;
LMB_UE_12 : in std_logic;
LMB_Byte_Enable_12 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_13 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_13 : out std_logic;
LMB_Read_Strobe_13 : out std_logic;
LMB_Write_Strobe_13 : out std_logic;
LMB_Ready_13 : in std_logic;
LMB_Wait_13 : in std_logic;
LMB_CE_13 : in std_logic;
LMB_UE_13 : in std_logic;
LMB_Byte_Enable_13 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_14 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_14 : out std_logic;
LMB_Read_Strobe_14 : out std_logic;
LMB_Write_Strobe_14 : out std_logic;
LMB_Ready_14 : in std_logic;
LMB_Wait_14 : in std_logic;
LMB_CE_14 : in std_logic;
LMB_UE_14 : in std_logic;
LMB_Byte_Enable_14 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_15 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_15 : out std_logic;
LMB_Read_Strobe_15 : out std_logic;
LMB_Write_Strobe_15 : out std_logic;
LMB_Ready_15 : in std_logic;
LMB_Wait_15 : in std_logic;
LMB_CE_15 : in std_logic;
LMB_UE_15 : in std_logic;
LMB_Byte_Enable_15 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_16 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_16 : out std_logic;
LMB_Read_Strobe_16 : out std_logic;
LMB_Write_Strobe_16 : out std_logic;
LMB_Ready_16 : in std_logic;
LMB_Wait_16 : in std_logic;
LMB_CE_16 : in std_logic;
LMB_UE_16 : in std_logic;
LMB_Byte_Enable_16 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_17 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_17 : out std_logic;
LMB_Read_Strobe_17 : out std_logic;
LMB_Write_Strobe_17 : out std_logic;
LMB_Ready_17 : in std_logic;
LMB_Wait_17 : in std_logic;
LMB_CE_17 : in std_logic;
LMB_UE_17 : in std_logic;
LMB_Byte_Enable_17 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_18 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_18 : out std_logic;
LMB_Read_Strobe_18 : out std_logic;
LMB_Write_Strobe_18 : out std_logic;
LMB_Ready_18 : in std_logic;
LMB_Wait_18 : in std_logic;
LMB_CE_18 : in std_logic;
LMB_UE_18 : in std_logic;
LMB_Byte_Enable_18 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_19 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_19 : out std_logic;
LMB_Read_Strobe_19 : out std_logic;
LMB_Write_Strobe_19 : out std_logic;
LMB_Ready_19 : in std_logic;
LMB_Wait_19 : in std_logic;
LMB_CE_19 : in std_logic;
LMB_UE_19 : in std_logic;
LMB_Byte_Enable_19 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_20 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_20 : out std_logic;
LMB_Read_Strobe_20 : out std_logic;
LMB_Write_Strobe_20 : out std_logic;
LMB_Ready_20 : in std_logic;
LMB_Wait_20 : in std_logic;
LMB_CE_20 : in std_logic;
LMB_UE_20 : in std_logic;
LMB_Byte_Enable_20 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_21 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_21 : out std_logic;
LMB_Read_Strobe_21 : out std_logic;
LMB_Write_Strobe_21 : out std_logic;
LMB_Ready_21 : in std_logic;
LMB_Wait_21 : in std_logic;
LMB_CE_21 : in std_logic;
LMB_UE_21 : in std_logic;
LMB_Byte_Enable_21 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_22 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_22 : out std_logic;
LMB_Read_Strobe_22 : out std_logic;
LMB_Write_Strobe_22 : out std_logic;
LMB_Ready_22 : in std_logic;
LMB_Wait_22 : in std_logic;
LMB_CE_22 : in std_logic;
LMB_UE_22 : in std_logic;
LMB_Byte_Enable_22 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_23 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_23 : out std_logic;
LMB_Read_Strobe_23 : out std_logic;
LMB_Write_Strobe_23 : out std_logic;
LMB_Ready_23 : in std_logic;
LMB_Wait_23 : in std_logic;
LMB_CE_23 : in std_logic;
LMB_UE_23 : in std_logic;
LMB_Byte_Enable_23 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_24 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_24 : out std_logic;
LMB_Read_Strobe_24 : out std_logic;
LMB_Write_Strobe_24 : out std_logic;
LMB_Ready_24 : in std_logic;
LMB_Wait_24 : in std_logic;
LMB_CE_24 : in std_logic;
LMB_UE_24 : in std_logic;
LMB_Byte_Enable_24 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_25 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_25 : out std_logic;
LMB_Read_Strobe_25 : out std_logic;
LMB_Write_Strobe_25 : out std_logic;
LMB_Ready_25 : in std_logic;
LMB_Wait_25 : in std_logic;
LMB_CE_25 : in std_logic;
LMB_UE_25 : in std_logic;
LMB_Byte_Enable_25 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_26 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_26 : out std_logic;
LMB_Read_Strobe_26 : out std_logic;
LMB_Write_Strobe_26 : out std_logic;
LMB_Ready_26 : in std_logic;
LMB_Wait_26 : in std_logic;
LMB_CE_26 : in std_logic;
LMB_UE_26 : in std_logic;
LMB_Byte_Enable_26 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_27 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_27 : out std_logic;
LMB_Read_Strobe_27 : out std_logic;
LMB_Write_Strobe_27 : out std_logic;
LMB_Ready_27 : in std_logic;
LMB_Wait_27 : in std_logic;
LMB_CE_27 : in std_logic;
LMB_UE_27 : in std_logic;
LMB_Byte_Enable_27 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_28 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_28 : out std_logic;
LMB_Read_Strobe_28 : out std_logic;
LMB_Write_Strobe_28 : out std_logic;
LMB_Ready_28 : in std_logic;
LMB_Wait_28 : in std_logic;
LMB_CE_28 : in std_logic;
LMB_UE_28 : in std_logic;
LMB_Byte_Enable_28 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_29 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_29 : out std_logic;
LMB_Read_Strobe_29 : out std_logic;
LMB_Write_Strobe_29 : out std_logic;
LMB_Ready_29 : in std_logic;
LMB_Wait_29 : in std_logic;
LMB_CE_29 : in std_logic;
LMB_UE_29 : in std_logic;
LMB_Byte_Enable_29 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_30 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_30 : out std_logic;
LMB_Read_Strobe_30 : out std_logic;
LMB_Write_Strobe_30 : out std_logic;
LMB_Ready_30 : in std_logic;
LMB_Wait_30 : in std_logic;
LMB_CE_30 : in std_logic;
LMB_UE_30 : in std_logic;
LMB_Byte_Enable_30 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_31 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_31 : out std_logic;
LMB_Read_Strobe_31 : out std_logic;
LMB_Write_Strobe_31 : out std_logic;
LMB_Ready_31 : in std_logic;
LMB_Wait_31 : in std_logic;
LMB_CE_31 : in std_logic;
LMB_UE_31 : in std_logic;
LMB_Byte_Enable_31 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External BSCAN inputs
-- These signals are used when C_USE_BSCAN = 2 (EXTERNAL)
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
-- External JTAG ports
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM;
architecture IMP of MDM is
function int2std (val : integer) return std_logic is
begin -- function int2std
if (val = 0) then
return '0';
else
return '1';
end if;
end function int2std;
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0) := X"00000000";
constant C_REG_NUM_CE : integer := 4 + 4 * C_DBG_REG_ACCESS;
constant C_REG_DATA_WIDTH : integer := 8 + 24 * C_DBG_REG_ACCESS;
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) :=
(31 downto 5 => '0', 4 => int2std(C_DBG_REG_ACCESS), 3 downto 0 => '1');
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := (
-- Registers Base Address (not used)
ZEROES & C_BASEADDR,
ZEROES & (C_BASEADDR or C_S_AXI_MIN_SIZE)
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (
0 => C_REG_NUM_CE
);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
constant C_TRACE_AXI_MASTER : boolean := C_TRACE_OUTPUT = 3;
--------------------------------------------------------------------------
-- Component declarations
--------------------------------------------------------------------------
component MDM_Core
generic (
C_JTAG_CHAIN : integer;
C_USE_BSCAN : integer;
C_USE_CONFIG_RESET : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8;
C_TRACE_OUTPUT : integer;
C_TRACE_DATA_WIDTH : integer;
C_TRACE_CLK_FREQ_HZ : integer;
C_TRACE_CLK_OUT_PHASE : integer;
C_M_AXIS_DATA_WIDTH : integer;
C_M_AXIS_ID_WIDTH : integer);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
-- AXI IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_data : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_dwr_start : out std_logic;
Master_dwr_next : in std_logic;
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External Trigger Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component MDM_Core;
component bus_master is
generic (
C_M_AXI_DATA_WIDTH : natural;
C_M_AXI_THREAD_ID_WIDTH : natural;
C_M_AXI_ADDR_WIDTH : natural;
C_DATA_SIZE : natural;
C_HAS_FIFO_PORTS : boolean;
C_HAS_DIRECT_PORT : boolean
);
port (
Rd_Start : in std_logic;
Rd_Addr : in std_logic_vector(31 downto 0);
Rd_Len : in std_logic_vector(4 downto 0);
Rd_Size : in std_logic_vector(1 downto 0);
Rd_Exclusive : in std_logic;
Rd_Idle : out std_logic;
Rd_Response : out std_logic_vector(1 downto 0);
Wr_Start : in std_logic;
Wr_Addr : in std_logic_vector(31 downto 0);
Wr_Len : in std_logic_vector(4 downto 0);
Wr_Size : in std_logic_vector(1 downto 0);
Wr_Exclusive : in std_logic;
Wr_Idle : out std_logic;
Wr_Response : out std_logic_vector(1 downto 0);
Data_Rd : in std_logic;
Data_Out : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Exists : out std_logic;
Data_Wr : in std_logic;
Data_In : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Empty : out std_logic;
Direct_Wr_Addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Direct_Wr_Len : in std_logic_vector(4 downto 0);
Direct_Wr_Data : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Direct_Wr_Start : in std_logic;
Direct_Wr_Next : out std_logic;
Direct_Wr_Done : out std_logic;
Direct_Wr_Resp : out std_logic_vector(1 downto 0);
LMB_Data_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe : out std_logic;
LMB_Read_Strobe : out std_logic;
LMB_Write_Strobe : out std_logic;
LMB_Ready : in std_logic;
LMB_Wait : in std_logic;
LMB_UE : in std_logic;
LMB_Byte_Enable : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WLAST : out std_logic;
M_AXI_WDATA : out std_logic_vector(31 downto 0);
M_AXI_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end component bus_master;
--------------------------------------------------------------------------
-- Functions
--------------------------------------------------------------------------
-- Returns at least 1
function MakePos (a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
constant C_EN_WIDTH : integer := MakePos(C_MB_DBG_PORTS);
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal tdi : std_logic;
signal reset : std_logic;
signal update : std_logic;
signal capture : std_logic;
signal shift : std_logic;
signal sel : std_logic;
signal drck : std_logic;
signal tdo : std_logic;
signal drck_i : std_logic;
signal update_i : std_logic;
signal dbgreg_drck : std_logic;
signal dbgreg_update : std_logic;
signal dbgreg_select : std_logic;
signal jtag_busy : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
signal bus2ip_cs : std_logic_vector(((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal mb_debug_enabled : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal master_rd_start : std_logic;
signal master_rd_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_rd_len : std_logic_vector(4 downto 0);
signal master_rd_size : std_logic_vector(1 downto 0);
signal master_rd_excl : std_logic;
signal master_rd_idle : std_logic;
signal master_rd_resp : std_logic_vector(1 downto 0);
signal master_wr_start : std_logic;
signal master_wr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_wr_len : std_logic_vector(4 downto 0);
signal master_wr_size : std_logic_vector(1 downto 0);
signal master_wr_excl : std_logic;
signal master_wr_idle : std_logic;
signal master_wr_resp : std_logic_vector(1 downto 0);
signal master_data_rd : std_logic;
signal master_data_out : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_exists : std_logic;
signal master_data_wr : std_logic;
signal master_data_in : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_empty : std_logic;
signal master_dwr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_dwr_len : std_logic_vector(4 downto 0);
signal master_dwr_data : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_dwr_start : std_logic;
signal master_dwr_next : std_logic;
signal master_dwr_done : std_logic;
signal master_dwr_resp : std_logic_vector(1 downto 0);
signal ext_trig_in : std_logic_vector(0 to 3);
signal ext_trig_Ack_In : std_logic_vector(0 to 3);
signal ext_trig_out : std_logic_vector(0 to 3);
signal ext_trig_Ack_Out : std_logic_vector(0 to 3);
--------------------------------------------------------------------------
-- Attibute declarations
--------------------------------------------------------------------------
attribute period : string;
attribute period of update : signal is "200 ns";
attribute buffer_type : string;
attribute buffer_type of update_i : signal is "none";
attribute buffer_type of MDM_Core_I1 : label is "none";
begin -- architecture IMP
Use_E2 : if C_USE_BSCAN /= 2 generate
begin
BSCANE2_I : BSCANE2
generic map (
DISABLE_JTAG => "FALSE",
JTAG_CHAIN => C_JTAG_CHAIN)
port map (
CAPTURE => capture, -- [out std_logic]
DRCK => drck_i, -- [out std_logic]
RESET => reset, -- [out std_logic]
RUNTEST => open, -- [out std_logic]
SEL => sel, -- [out std_logic]
SHIFT => shift, -- [out std_logic]
TCK => open, -- [out std_logic]
TDI => tdi, -- [out std_logic]
TMS => open, -- [out std_logic]
UPDATE => update_i, -- [out std_logic]
TDO => tdo); -- [in std_logic]
end generate Use_E2;
Use_External : if C_USE_BSCAN = 2 generate
begin
capture <= bscan_ext_capture;
drck_i <= bscan_ext_drck;
reset <= bscan_ext_reset;
sel <= bscan_ext_sel;
shift <= bscan_ext_shift;
tdi <= bscan_ext_tdi;
update_i <= bscan_ext_update;
bscan_ext_tdo <= tdo;
end generate Use_External;
No_External : if C_USE_BSCAN /= 2 generate
begin
bscan_ext_tdo <= '0';
end generate No_External;
Use_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 1 generate
signal dbgreg_select_n : std_logic;
signal dbgreg_drck_i : std_logic;
signal dbgreg_update_i : std_logic;
signal update_set : std_logic;
signal update_reset : std_logic;
begin
dbgreg_select_n <= not dbgreg_select;
-- drck <= dbgreg_drck when dbgreg_select = '1' else drck_i;
BUFG_DRCK : BUFG
port map (
O => dbgreg_drck_i,
I => dbgreg_drck
);
BUFGCTRL_DRCK : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => drck,
CE0 => '1',
CE1 => '1',
I0 => drck_i,
I1 => dbgreg_drck_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
-- update <= dbgreg_update when dbgreg_select = '1' else update_i;
BUFG_UPDATE : BUFG
port map (
O => dbgreg_update_i,
I => dbgreg_update
);
BUFGCTRL_UPDATE : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => update,
CE0 => '1',
CE1 => '1',
I0 => update_i,
I1 => dbgreg_update_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
JTAG_Busy_Detect : process (drck_i, sel, update_set, Config_Reset)
begin
if sel = '0' or update_set = '1' or Config_Reset = '1' then
jtag_busy <= '0';
update_reset <= '1';
elsif drck_i'event and drck_i = '1' then
if sel = '1' and capture = '1' then
jtag_busy <= '1';
end if;
update_reset <= '0';
end if;
end process JTAG_Busy_Detect;
JTAG_Update_Detect : process (update_i, update_reset, Config_Reset)
begin
if update_reset = '1' or Config_Reset = '1' then
update_set <= '0';
elsif update_i'event and update_i = '1' then
update_set <= '1';
end if;
end process JTAG_Update_Detect;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 0 generate
begin
BUFG_DRCK : BUFG
port map (
O => drck,
I => drck_i
);
update <= update_i;
jtag_busy <= '0';
end generate No_Dbg_Reg_Access;
---------------------------------------------------------------------------
-- MDM core
---------------------------------------------------------------------------
MDM_Core_I1 : MDM_Core
generic map (
C_JTAG_CHAIN => C_JTAG_CHAIN, -- [integer]
C_USE_BSCAN => C_USE_BSCAN, -- [integer]
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET, -- [integer = 0]
C_BASEADDR => C_BASEADDR, -- [std_logic_vector(0 to 31)]
C_HIGHADDR => C_HIGHADDR, -- [std_logic_vector(0 to 31)]
C_MB_DBG_PORTS => C_MB_DBG_PORTS, -- [integer]
C_EN_WIDTH => C_EN_WIDTH, -- [integer]
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS, -- [integer]
C_REG_NUM_CE => C_REG_NUM_CE, -- [integer]
C_REG_DATA_WIDTH => C_REG_DATA_WIDTH, -- [integer]
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS, -- [integer]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ, -- [integer]
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH, -- [integer]
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH, -- [integer]
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER, -- [integer]
C_USE_UART => C_USE_UART, -- [integer]
C_UART_WIDTH => 8, -- [integer]
C_TRACE_OUTPUT => C_TRACE_OUTPUT, -- [integer]
C_TRACE_DATA_WIDTH => C_TRACE_DATA_WIDTH, -- [integer]
C_TRACE_CLK_FREQ_HZ => C_TRACE_CLK_FREQ_HZ, -- [integer]
C_TRACE_CLK_OUT_PHASE => C_TRACE_CLK_OUT_PHASE, -- [integer]
C_M_AXIS_DATA_WIDTH => C_M_AXIS_DATA_WIDTH, -- [integer]
C_M_AXIS_ID_WIDTH => C_M_AXIS_ID_WIDTH -- [integer]
)
port map (
-- Global signals
Config_Reset => Config_Reset, -- [in std_logic]
Scan_Reset_Sel => Scan_Reset_Sel, -- [in std_logic]
Scan_Reset => Scan_Reset, -- [in std_logic]
M_AXIS_ACLK => M_AXIS_ACLK, -- [in std_logic]
M_AXIS_ARESETN => M_AXIS_ARESETN, -- [in std_logic]
Interrupt => Interrupt, -- [out std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst, -- [out std_logic]
-- Debug Register Access signals
DbgReg_DRCK => dbgreg_drck, -- [out std_logic]
DbgReg_UPDATE => dbgreg_update, -- [out std_logic]
DbgReg_Select => dbgreg_select, -- [out std_logic]
JTAG_Busy => jtag_busy, -- [in std_logic]
-- AXI IPIC signals
bus2ip_clk => bus2ip_clk,
bus2ip_resetn => bus2ip_resetn,
bus2ip_data => bus2ip_data(C_REG_DATA_WIDTH-1 downto 0),
bus2ip_rdce => bus2ip_rdce(C_REG_NUM_CE-1 downto 0),
bus2ip_wrce => bus2ip_wrce(C_REG_NUM_CE-1 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
ip2bus_data => ip2bus_data(C_REG_DATA_WIDTH-1 downto 0),
-- Bus Master signals
MB_Debug_Enabled => mb_debug_enabled,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
Master_rd_start => master_rd_start,
Master_rd_addr => master_rd_addr,
Master_rd_len => master_rd_len,
Master_rd_size => master_rd_size,
Master_rd_excl => master_rd_excl,
Master_rd_idle => master_rd_idle,
Master_rd_resp => master_rd_resp,
Master_wr_start => master_wr_start,
Master_wr_addr => master_wr_addr,
Master_wr_len => master_wr_len,
Master_wr_size => master_wr_size,
Master_wr_excl => master_wr_excl,
Master_wr_idle => master_wr_idle,
Master_wr_resp => master_wr_resp,
Master_data_rd => master_data_rd,
Master_data_out => master_data_out,
Master_data_exists => master_data_exists,
Master_data_wr => master_data_wr,
Master_data_in => master_data_in,
Master_data_empty => master_data_empty,
Master_dwr_addr => master_dwr_addr,
Master_dwr_len => master_dwr_len,
Master_dwr_data => master_dwr_data,
Master_dwr_start => master_dwr_start,
Master_dwr_next => master_dwr_next,
Master_dwr_done => master_dwr_done,
Master_dwr_resp => master_dwr_resp,
-- JTAG signals
JTAG_TDI => tdi, -- [in std_logic]
JTAG_RESET => reset, -- [in std_logic]
UPDATE => update, -- [in std_logic]
JTAG_SHIFT => shift, -- [in std_logic]
JTAG_CAPTURE => capture, -- [in std_logic]
SEL => sel, -- [in std_logic]
DRCK => drck, -- [in std_logic]
JTAG_TDO => tdo, -- [out std_logic]
-- External Trace AXI Stream output
M_AXIS_TDATA => M_AXIS_TDATA, -- [out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0)]
M_AXIS_TID => M_AXIS_TID, -- [out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0)]
M_AXIS_TREADY => M_AXIS_TREADY, -- [in std_logic]
M_AXIS_TVALID => M_AXIS_TVALID, -- [out std_logic]
-- External Trace output
TRACE_CLK_OUT => TRACE_CLK_OUT, -- [out std_logic]
TRACE_CLK => TRACE_CLK, -- [in std_logic]
TRACE_CTL => TRACE_CTL, -- [out std_logic]
TRACE_DATA => TRACE_DATA, -- [out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0)]
-- MicroBlaze Debug Signals
Dbg_Clk_0 => Dbg_Clk_0, -- [out std_logic]
Dbg_TDI_0 => Dbg_TDI_0, -- [out std_logic]
Dbg_TDO_0 => Dbg_TDO_0, -- [in std_logic]
Dbg_Reg_En_0 => Dbg_Reg_En_0, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_0 => Dbg_Capture_0, -- [out std_logic]
Dbg_Shift_0 => Dbg_Shift_0, -- [out std_logic]
Dbg_Update_0 => Dbg_Update_0, -- [out std_logic]
Dbg_Rst_0 => Dbg_Rst_0, -- [out std_logic]
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_0 => Dbg_TrClk_0, -- [out std_logic]
Dbg_TrData_0 => Dbg_TrData_0, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_0 => Dbg_TrReady_0, -- [out std_logic]
Dbg_TrValid_0 => Dbg_TrValid_0, -- [in std_logic]
Dbg_Clk_1 => Dbg_Clk_1, -- [out std_logic]
Dbg_TDI_1 => Dbg_TDI_1, -- [out std_logic]
Dbg_TDO_1 => Dbg_TDO_1, -- [in std_logic]
Dbg_Reg_En_1 => Dbg_Reg_En_1, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_1 => Dbg_Capture_1, -- [out std_logic]
Dbg_Shift_1 => Dbg_Shift_1, -- [out std_logic]
Dbg_Update_1 => Dbg_Update_1, -- [out std_logic]
Dbg_Rst_1 => Dbg_Rst_1, -- [out std_logic]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_1 => Dbg_TrClk_1, -- [out std_logic]
Dbg_TrData_1 => Dbg_TrData_1, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_1 => Dbg_TrReady_1, -- [out std_logic]
Dbg_TrValid_1 => Dbg_TrValid_1, -- [in std_logic]
Dbg_Clk_2 => Dbg_Clk_2, -- [out std_logic]
Dbg_TDI_2 => Dbg_TDI_2, -- [out std_logic]
Dbg_TDO_2 => Dbg_TDO_2, -- [in std_logic]
Dbg_Reg_En_2 => Dbg_Reg_En_2, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_2 => Dbg_Capture_2, -- [out std_logic]
Dbg_Shift_2 => Dbg_Shift_2, -- [out std_logic]
Dbg_Update_2 => Dbg_Update_2, -- [out std_logic]
Dbg_Rst_2 => Dbg_Rst_2, -- [out std_logic]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_2 => Dbg_TrClk_2, -- [out std_logic]
Dbg_TrData_2 => Dbg_TrData_2, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_2 => Dbg_TrReady_2, -- [out std_logic]
Dbg_TrValid_2 => Dbg_TrValid_2, -- [in std_logic]
Dbg_Clk_3 => Dbg_Clk_3, -- [out std_logic]
Dbg_TDI_3 => Dbg_TDI_3, -- [out std_logic]
Dbg_TDO_3 => Dbg_TDO_3, -- [in std_logic]
Dbg_Reg_En_3 => Dbg_Reg_En_3, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_3 => Dbg_Capture_3, -- [out std_logic]
Dbg_Shift_3 => Dbg_Shift_3, -- [out std_logic]
Dbg_Update_3 => Dbg_Update_3, -- [out std_logic]
Dbg_Rst_3 => Dbg_Rst_3, -- [out std_logic]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_3 => Dbg_TrClk_3, -- [out std_logic]
Dbg_TrData_3 => Dbg_TrData_3, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_3 => Dbg_TrReady_3, -- [out std_logic]
Dbg_TrValid_3 => Dbg_TrValid_3, -- [in std_logic]
Dbg_Clk_4 => Dbg_Clk_4, -- [out std_logic]
Dbg_TDI_4 => Dbg_TDI_4, -- [out std_logic]
Dbg_TDO_4 => Dbg_TDO_4, -- [in std_logic]
Dbg_Reg_En_4 => Dbg_Reg_En_4, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_4 => Dbg_Capture_4, -- [out std_logic]
Dbg_Shift_4 => Dbg_Shift_4, -- [out std_logic]
Dbg_Update_4 => Dbg_Update_4, -- [out std_logic]
Dbg_Rst_4 => Dbg_Rst_4, -- [out std_logic]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_4 => Dbg_TrClk_4, -- [out std_logic]
Dbg_TrData_4 => Dbg_TrData_4, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_4 => Dbg_TrReady_4, -- [out std_logic]
Dbg_TrValid_4 => Dbg_TrValid_4, -- [in std_logic]
Dbg_Clk_5 => Dbg_Clk_5, -- [out std_logic]
Dbg_TDI_5 => Dbg_TDI_5, -- [out std_logic]
Dbg_TDO_5 => Dbg_TDO_5, -- [in std_logic]
Dbg_Reg_En_5 => Dbg_Reg_En_5, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_5 => Dbg_Capture_5, -- [out std_logic]
Dbg_Shift_5 => Dbg_Shift_5, -- [out std_logic]
Dbg_Update_5 => Dbg_Update_5, -- [out std_logic]
Dbg_Rst_5 => Dbg_Rst_5, -- [out std_logic]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_5 => Dbg_TrClk_5, -- [out std_logic]
Dbg_TrData_5 => Dbg_TrData_5, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_5 => Dbg_TrReady_5, -- [out std_logic]
Dbg_TrValid_5 => Dbg_TrValid_5, -- [in std_logic]
Dbg_Clk_6 => Dbg_Clk_6, -- [out std_logic]
Dbg_TDI_6 => Dbg_TDI_6, -- [out std_logic]
Dbg_TDO_6 => Dbg_TDO_6, -- [in std_logic]
Dbg_Reg_En_6 => Dbg_Reg_En_6, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_6 => Dbg_Capture_6, -- [out std_logic]
Dbg_Shift_6 => Dbg_Shift_6, -- [out std_logic]
Dbg_Update_6 => Dbg_Update_6, -- [out std_logic]
Dbg_Rst_6 => Dbg_Rst_6, -- [out std_logic]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_6 => Dbg_TrClk_6, -- [out std_logic]
Dbg_TrData_6 => Dbg_TrData_6, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_6 => Dbg_TrReady_6, -- [out std_logic]
Dbg_TrValid_6 => Dbg_TrValid_6, -- [in std_logic]
Dbg_Clk_7 => Dbg_Clk_7, -- [out std_logic]
Dbg_TDI_7 => Dbg_TDI_7, -- [out std_logic]
Dbg_TDO_7 => Dbg_TDO_7, -- [in std_logic]
Dbg_Reg_En_7 => Dbg_Reg_En_7, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_7 => Dbg_Capture_7, -- [out std_logic]
Dbg_Shift_7 => Dbg_Shift_7, -- [out std_logic]
Dbg_Update_7 => Dbg_Update_7, -- [out std_logic]
Dbg_Rst_7 => Dbg_Rst_7, -- [out std_logic]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_7 => Dbg_TrClk_7, -- [out std_logic]
Dbg_TrData_7 => Dbg_TrData_7, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_7 => Dbg_TrReady_7, -- [out std_logic]
Dbg_TrValid_7 => Dbg_TrValid_7, -- [in std_logic]
Dbg_Clk_8 => Dbg_Clk_8, -- [out std_logic]
Dbg_TDI_8 => Dbg_TDI_8, -- [out std_logic]
Dbg_TDO_8 => Dbg_TDO_8, -- [in std_logic]
Dbg_Reg_En_8 => Dbg_Reg_En_8, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_8 => Dbg_Capture_8, -- [out std_logic]
Dbg_Shift_8 => Dbg_Shift_8, -- [out std_logic]
Dbg_Update_8 => Dbg_Update_8, -- [out std_logic]
Dbg_Rst_8 => Dbg_Rst_8, -- [out std_logic]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_8 => Dbg_TrClk_8, -- [out std_logic]
Dbg_TrData_8 => Dbg_TrData_8, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_8 => Dbg_TrReady_8, -- [out std_logic]
Dbg_TrValid_8 => Dbg_TrValid_8, -- [in std_logic]
Dbg_Clk_9 => Dbg_Clk_9, -- [out std_logic]
Dbg_TDI_9 => Dbg_TDI_9, -- [out std_logic]
Dbg_TDO_9 => Dbg_TDO_9, -- [in std_logic]
Dbg_Reg_En_9 => Dbg_Reg_En_9, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_9 => Dbg_Capture_9, -- [out std_logic]
Dbg_Shift_9 => Dbg_Shift_9, -- [out std_logic]
Dbg_Update_9 => Dbg_Update_9, -- [out std_logic]
Dbg_Rst_9 => Dbg_Rst_9, -- [out std_logic]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_9 => Dbg_TrClk_9, -- [out std_logic]
Dbg_TrData_9 => Dbg_TrData_9, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_9 => Dbg_TrReady_9, -- [out std_logic]
Dbg_TrValid_9 => Dbg_TrValid_9, -- [in std_logic]
Dbg_Clk_10 => Dbg_Clk_10, -- [out std_logic]
Dbg_TDI_10 => Dbg_TDI_10, -- [out std_logic]
Dbg_TDO_10 => Dbg_TDO_10, -- [in std_logic]
Dbg_Reg_En_10 => Dbg_Reg_En_10, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_10 => Dbg_Capture_10, -- [out std_logic]
Dbg_Shift_10 => Dbg_Shift_10, -- [out std_logic]
Dbg_Update_10 => Dbg_Update_10, -- [out std_logic]
Dbg_Rst_10 => Dbg_Rst_10, -- [out std_logic]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_10 => Dbg_TrClk_10, -- [out std_logic]
Dbg_TrData_10 => Dbg_TrData_10, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_10 => Dbg_TrReady_10, -- [out std_logic]
Dbg_TrValid_10 => Dbg_TrValid_10, -- [in std_logic]
Dbg_Clk_11 => Dbg_Clk_11, -- [out std_logic]
Dbg_TDI_11 => Dbg_TDI_11, -- [out std_logic]
Dbg_TDO_11 => Dbg_TDO_11, -- [in std_logic]
Dbg_Reg_En_11 => Dbg_Reg_En_11, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_11 => Dbg_Capture_11, -- [out std_logic]
Dbg_Shift_11 => Dbg_Shift_11, -- [out std_logic]
Dbg_Update_11 => Dbg_Update_11, -- [out std_logic]
Dbg_Rst_11 => Dbg_Rst_11, -- [out std_logic]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_11 => Dbg_TrClk_11, -- [out std_logic]
Dbg_TrData_11 => Dbg_TrData_11, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_11 => Dbg_TrReady_11, -- [out std_logic]
Dbg_TrValid_11 => Dbg_TrValid_11, -- [in std_logic]
Dbg_Clk_12 => Dbg_Clk_12, -- [out std_logic]
Dbg_TDI_12 => Dbg_TDI_12, -- [out std_logic]
Dbg_TDO_12 => Dbg_TDO_12, -- [in std_logic]
Dbg_Reg_En_12 => Dbg_Reg_En_12, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_12 => Dbg_Capture_12, -- [out std_logic]
Dbg_Shift_12 => Dbg_Shift_12, -- [out std_logic]
Dbg_Update_12 => Dbg_Update_12, -- [out std_logic]
Dbg_Rst_12 => Dbg_Rst_12, -- [out std_logic]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_12 => Dbg_TrClk_12, -- [out std_logic]
Dbg_TrData_12 => Dbg_TrData_12, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_12 => Dbg_TrReady_12, -- [out std_logic]
Dbg_TrValid_12 => Dbg_TrValid_12, -- [in std_logic]
Dbg_Clk_13 => Dbg_Clk_13, -- [out std_logic]
Dbg_TDI_13 => Dbg_TDI_13, -- [out std_logic]
Dbg_TDO_13 => Dbg_TDO_13, -- [in std_logic]
Dbg_Reg_En_13 => Dbg_Reg_En_13, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_13 => Dbg_Capture_13, -- [out std_logic]
Dbg_Shift_13 => Dbg_Shift_13, -- [out std_logic]
Dbg_Update_13 => Dbg_Update_13, -- [out std_logic]
Dbg_Rst_13 => Dbg_Rst_13, -- [out std_logic]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_13 => Dbg_TrClk_13, -- [out std_logic]
Dbg_TrData_13 => Dbg_TrData_13, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_13 => Dbg_TrReady_13, -- [out std_logic]
Dbg_TrValid_13 => Dbg_TrValid_13, -- [in std_logic]
Dbg_Clk_14 => Dbg_Clk_14, -- [out std_logic]
Dbg_TDI_14 => Dbg_TDI_14, -- [out std_logic]
Dbg_TDO_14 => Dbg_TDO_14, -- [in std_logic]
Dbg_Reg_En_14 => Dbg_Reg_En_14, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_14 => Dbg_Capture_14, -- [out std_logic]
Dbg_Shift_14 => Dbg_Shift_14, -- [out std_logic]
Dbg_Update_14 => Dbg_Update_14, -- [out std_logic]
Dbg_Rst_14 => Dbg_Rst_14, -- [out std_logic]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_14 => Dbg_TrClk_14, -- [out std_logic]
Dbg_TrData_14 => Dbg_TrData_14, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_14 => Dbg_TrReady_14, -- [out std_logic]
Dbg_TrValid_14 => Dbg_TrValid_14, -- [in std_logic]
Dbg_Clk_15 => Dbg_Clk_15, -- [out std_logic]
Dbg_TDI_15 => Dbg_TDI_15, -- [out std_logic]
Dbg_TDO_15 => Dbg_TDO_15, -- [in std_logic]
Dbg_Reg_En_15 => Dbg_Reg_En_15, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_15 => Dbg_Capture_15, -- [out std_logic]
Dbg_Shift_15 => Dbg_Shift_15, -- [out std_logic]
Dbg_Update_15 => Dbg_Update_15, -- [out std_logic]
Dbg_Rst_15 => Dbg_Rst_15, -- [out std_logic]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_15 => Dbg_TrClk_15, -- [out std_logic]
Dbg_TrData_15 => Dbg_TrData_15, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_15 => Dbg_TrReady_15, -- [out std_logic]
Dbg_TrValid_15 => Dbg_TrValid_15, -- [in std_logic]
Dbg_Clk_16 => Dbg_Clk_16, -- [out std_logic]
Dbg_TDI_16 => Dbg_TDI_16, -- [out std_logic]
Dbg_TDO_16 => Dbg_TDO_16, -- [in std_logic]
Dbg_Reg_En_16 => Dbg_Reg_En_16, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_16 => Dbg_Capture_16, -- [out std_logic]
Dbg_Shift_16 => Dbg_Shift_16, -- [out std_logic]
Dbg_Update_16 => Dbg_Update_16, -- [out std_logic]
Dbg_Rst_16 => Dbg_Rst_16, -- [out std_logic]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_16 => Dbg_TrClk_16, -- [out std_logic]
Dbg_TrData_16 => Dbg_TrData_16, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_16 => Dbg_TrReady_16, -- [out std_logic]
Dbg_TrValid_16 => Dbg_TrValid_16, -- [in std_logic]
Dbg_Clk_17 => Dbg_Clk_17, -- [out std_logic]
Dbg_TDI_17 => Dbg_TDI_17, -- [out std_logic]
Dbg_TDO_17 => Dbg_TDO_17, -- [in std_logic]
Dbg_Reg_En_17 => Dbg_Reg_En_17, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_17 => Dbg_Capture_17, -- [out std_logic]
Dbg_Shift_17 => Dbg_Shift_17, -- [out std_logic]
Dbg_Update_17 => Dbg_Update_17, -- [out std_logic]
Dbg_Rst_17 => Dbg_Rst_17, -- [out std_logic]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_17 => Dbg_TrClk_17, -- [out std_logic]
Dbg_TrData_17 => Dbg_TrData_17, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_17 => Dbg_TrReady_17, -- [out std_logic]
Dbg_TrValid_17 => Dbg_TrValid_17, -- [in std_logic]
Dbg_Clk_18 => Dbg_Clk_18, -- [out std_logic]
Dbg_TDI_18 => Dbg_TDI_18, -- [out std_logic]
Dbg_TDO_18 => Dbg_TDO_18, -- [in std_logic]
Dbg_Reg_En_18 => Dbg_Reg_En_18, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_18 => Dbg_Capture_18, -- [out std_logic]
Dbg_Shift_18 => Dbg_Shift_18, -- [out std_logic]
Dbg_Update_18 => Dbg_Update_18, -- [out std_logic]
Dbg_Rst_18 => Dbg_Rst_18, -- [out std_logic]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_18 => Dbg_TrClk_18, -- [out std_logic]
Dbg_TrData_18 => Dbg_TrData_18, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_18 => Dbg_TrReady_18, -- [out std_logic]
Dbg_TrValid_18 => Dbg_TrValid_18, -- [in std_logic]
Dbg_Clk_19 => Dbg_Clk_19, -- [out std_logic]
Dbg_TDI_19 => Dbg_TDI_19, -- [out std_logic]
Dbg_TDO_19 => Dbg_TDO_19, -- [in std_logic]
Dbg_Reg_En_19 => Dbg_Reg_En_19, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_19 => Dbg_Capture_19, -- [out std_logic]
Dbg_Shift_19 => Dbg_Shift_19, -- [out std_logic]
Dbg_Update_19 => Dbg_Update_19, -- [out std_logic]
Dbg_Rst_19 => Dbg_Rst_19, -- [out std_logic]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_19 => Dbg_TrClk_19, -- [out std_logic]
Dbg_TrData_19 => Dbg_TrData_19, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_19 => Dbg_TrReady_19, -- [out std_logic]
Dbg_TrValid_19 => Dbg_TrValid_19, -- [in std_logic]
Dbg_Clk_20 => Dbg_Clk_20, -- [out std_logic]
Dbg_TDI_20 => Dbg_TDI_20, -- [out std_logic]
Dbg_TDO_20 => Dbg_TDO_20, -- [in std_logic]
Dbg_Reg_En_20 => Dbg_Reg_En_20, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_20 => Dbg_Capture_20, -- [out std_logic]
Dbg_Shift_20 => Dbg_Shift_20, -- [out std_logic]
Dbg_Update_20 => Dbg_Update_20, -- [out std_logic]
Dbg_Rst_20 => Dbg_Rst_20, -- [out std_logic]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_20 => Dbg_TrClk_20, -- [out std_logic]
Dbg_TrData_20 => Dbg_TrData_20, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_20 => Dbg_TrReady_20, -- [out std_logic]
Dbg_TrValid_20 => Dbg_TrValid_20, -- [in std_logic]
Dbg_Clk_21 => Dbg_Clk_21, -- [out std_logic]
Dbg_TDI_21 => Dbg_TDI_21, -- [out std_logic]
Dbg_TDO_21 => Dbg_TDO_21, -- [in std_logic]
Dbg_Reg_En_21 => Dbg_Reg_En_21, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_21 => Dbg_Capture_21, -- [out std_logic]
Dbg_Shift_21 => Dbg_Shift_21, -- [out std_logic]
Dbg_Update_21 => Dbg_Update_21, -- [out std_logic]
Dbg_Rst_21 => Dbg_Rst_21, -- [out std_logic]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_21 => Dbg_TrClk_21, -- [out std_logic]
Dbg_TrData_21 => Dbg_TrData_21, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_21 => Dbg_TrReady_21, -- [out std_logic]
Dbg_TrValid_21 => Dbg_TrValid_21, -- [in std_logic]
Dbg_Clk_22 => Dbg_Clk_22, -- [out std_logic]
Dbg_TDI_22 => Dbg_TDI_22, -- [out std_logic]
Dbg_TDO_22 => Dbg_TDO_22, -- [in std_logic]
Dbg_Reg_En_22 => Dbg_Reg_En_22, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_22 => Dbg_Capture_22, -- [out std_logic]
Dbg_Shift_22 => Dbg_Shift_22, -- [out std_logic]
Dbg_Update_22 => Dbg_Update_22, -- [out std_logic]
Dbg_Rst_22 => Dbg_Rst_22, -- [out std_logic]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_22 => Dbg_TrClk_22, -- [out std_logic]
Dbg_TrData_22 => Dbg_TrData_22, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_22 => Dbg_TrReady_22, -- [out std_logic]
Dbg_TrValid_22 => Dbg_TrValid_22, -- [in std_logic]
Dbg_Clk_23 => Dbg_Clk_23, -- [out std_logic]
Dbg_TDI_23 => Dbg_TDI_23, -- [out std_logic]
Dbg_TDO_23 => Dbg_TDO_23, -- [in std_logic]
Dbg_Reg_En_23 => Dbg_Reg_En_23, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_23 => Dbg_Capture_23, -- [out std_logic]
Dbg_Shift_23 => Dbg_Shift_23, -- [out std_logic]
Dbg_Update_23 => Dbg_Update_23, -- [out std_logic]
Dbg_Rst_23 => Dbg_Rst_23, -- [out std_logic]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_23 => Dbg_TrClk_23, -- [out std_logic]
Dbg_TrData_23 => Dbg_TrData_23, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_23 => Dbg_TrReady_23, -- [out std_logic]
Dbg_TrValid_23 => Dbg_TrValid_23, -- [in std_logic]
Dbg_Clk_24 => Dbg_Clk_24, -- [out std_logic]
Dbg_TDI_24 => Dbg_TDI_24, -- [out std_logic]
Dbg_TDO_24 => Dbg_TDO_24, -- [in std_logic]
Dbg_Reg_En_24 => Dbg_Reg_En_24, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_24 => Dbg_Capture_24, -- [out std_logic]
Dbg_Shift_24 => Dbg_Shift_24, -- [out std_logic]
Dbg_Update_24 => Dbg_Update_24, -- [out std_logic]
Dbg_Rst_24 => Dbg_Rst_24, -- [out std_logic]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_24 => Dbg_TrClk_24, -- [out std_logic]
Dbg_TrData_24 => Dbg_TrData_24, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_24 => Dbg_TrReady_24, -- [out std_logic]
Dbg_TrValid_24 => Dbg_TrValid_24, -- [in std_logic]
Dbg_Clk_25 => Dbg_Clk_25, -- [out std_logic]
Dbg_TDI_25 => Dbg_TDI_25, -- [out std_logic]
Dbg_TDO_25 => Dbg_TDO_25, -- [in std_logic]
Dbg_Reg_En_25 => Dbg_Reg_En_25, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_25 => Dbg_Capture_25, -- [out std_logic]
Dbg_Shift_25 => Dbg_Shift_25, -- [out std_logic]
Dbg_Update_25 => Dbg_Update_25, -- [out std_logic]
Dbg_Rst_25 => Dbg_Rst_25, -- [out std_logic]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_25 => Dbg_TrClk_25, -- [out std_logic]
Dbg_TrData_25 => Dbg_TrData_25, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_25 => Dbg_TrReady_25, -- [out std_logic]
Dbg_TrValid_25 => Dbg_TrValid_25, -- [in std_logic]
Dbg_Clk_26 => Dbg_Clk_26, -- [out std_logic]
Dbg_TDI_26 => Dbg_TDI_26, -- [out std_logic]
Dbg_TDO_26 => Dbg_TDO_26, -- [in std_logic]
Dbg_Reg_En_26 => Dbg_Reg_En_26, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_26 => Dbg_Capture_26, -- [out std_logic]
Dbg_Shift_26 => Dbg_Shift_26, -- [out std_logic]
Dbg_Update_26 => Dbg_Update_26, -- [out std_logic]
Dbg_Rst_26 => Dbg_Rst_26, -- [out std_logic]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_26 => Dbg_TrClk_26, -- [out std_logic]
Dbg_TrData_26 => Dbg_TrData_26, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_26 => Dbg_TrReady_26, -- [out std_logic]
Dbg_TrValid_26 => Dbg_TrValid_26, -- [in std_logic]
Dbg_Clk_27 => Dbg_Clk_27, -- [out std_logic]
Dbg_TDI_27 => Dbg_TDI_27, -- [out std_logic]
Dbg_TDO_27 => Dbg_TDO_27, -- [in std_logic]
Dbg_Reg_En_27 => Dbg_Reg_En_27, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_27 => Dbg_Capture_27, -- [out std_logic]
Dbg_Shift_27 => Dbg_Shift_27, -- [out std_logic]
Dbg_Update_27 => Dbg_Update_27, -- [out std_logic]
Dbg_Rst_27 => Dbg_Rst_27, -- [out std_logic]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_27 => Dbg_TrClk_27, -- [out std_logic]
Dbg_TrData_27 => Dbg_TrData_27, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_27 => Dbg_TrReady_27, -- [out std_logic]
Dbg_TrValid_27 => Dbg_TrValid_27, -- [in std_logic]
Dbg_Clk_28 => Dbg_Clk_28, -- [out std_logic]
Dbg_TDI_28 => Dbg_TDI_28, -- [out std_logic]
Dbg_TDO_28 => Dbg_TDO_28, -- [in std_logic]
Dbg_Reg_En_28 => Dbg_Reg_En_28, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_28 => Dbg_Capture_28, -- [out std_logic]
Dbg_Shift_28 => Dbg_Shift_28, -- [out std_logic]
Dbg_Update_28 => Dbg_Update_28, -- [out std_logic]
Dbg_Rst_28 => Dbg_Rst_28, -- [out std_logic]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_28 => Dbg_TrClk_28, -- [out std_logic]
Dbg_TrData_28 => Dbg_TrData_28, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_28 => Dbg_TrReady_28, -- [out std_logic]
Dbg_TrValid_28 => Dbg_TrValid_28, -- [in std_logic]
Dbg_Clk_29 => Dbg_Clk_29, -- [out std_logic]
Dbg_TDI_29 => Dbg_TDI_29, -- [out std_logic]
Dbg_TDO_29 => Dbg_TDO_29, -- [in std_logic]
Dbg_Reg_En_29 => Dbg_Reg_En_29, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_29 => Dbg_Capture_29, -- [out std_logic]
Dbg_Shift_29 => Dbg_Shift_29, -- [out std_logic]
Dbg_Update_29 => Dbg_Update_29, -- [out std_logic]
Dbg_Rst_29 => Dbg_Rst_29, -- [out std_logic]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_29 => Dbg_TrClk_29, -- [out std_logic]
Dbg_TrData_29 => Dbg_TrData_29, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_29 => Dbg_TrReady_29, -- [out std_logic]
Dbg_TrValid_29 => Dbg_TrValid_29, -- [in std_logic]
Dbg_Clk_30 => Dbg_Clk_30, -- [out std_logic]
Dbg_TDI_30 => Dbg_TDI_30, -- [out std_logic]
Dbg_TDO_30 => Dbg_TDO_30, -- [in std_logic]
Dbg_Reg_En_30 => Dbg_Reg_En_30, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_30 => Dbg_Capture_30, -- [out std_logic]
Dbg_Shift_30 => Dbg_Shift_30, -- [out std_logic]
Dbg_Update_30 => Dbg_Update_30, -- [out std_logic]
Dbg_Rst_30 => Dbg_Rst_30, -- [out std_logic]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_30 => Dbg_TrClk_30, -- [out std_logic]
Dbg_TrData_30 => Dbg_TrData_30, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_30 => Dbg_TrReady_30, -- [out std_logic]
Dbg_TrValid_30 => Dbg_TrValid_30, -- [in std_logic]
Dbg_Clk_31 => Dbg_Clk_31, -- [out std_logic]
Dbg_TDI_31 => Dbg_TDI_31, -- [out std_logic]
Dbg_TDO_31 => Dbg_TDO_31, -- [in std_logic]
Dbg_Reg_En_31 => Dbg_Reg_En_31, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_31 => Dbg_Capture_31, -- [out std_logic]
Dbg_Shift_31 => Dbg_Shift_31, -- [out std_logic]
Dbg_Update_31 => Dbg_Update_31, -- [out std_logic]
Dbg_Rst_31 => Dbg_Rst_31, -- [out std_logic]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_31 => Dbg_TrClk_31, -- [out std_logic]
Dbg_TrData_31 => Dbg_TrData_31, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_31 => Dbg_TrReady_31, -- [out std_logic]
Dbg_TrValid_31 => Dbg_TrValid_31, -- [in std_logic]
Ext_Trig_In => ext_trig_in, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => ext_trig_ack_in, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => ext_trig_out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => ext_trig_ack_out, -- [in std_logic_vector(0 to 3)]
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
ext_trig_in <= Trig_In_0 & Trig_In_1 & Trig_In_2 & Trig_In_3;
ext_trig_ack_out <= Trig_Ack_Out_0 & Trig_Ack_Out_1 & Trig_Ack_Out_2 & Trig_Ack_Out_3;
Trig_Ack_In_0 <= ext_trig_ack_in(0);
Trig_Ack_In_1 <= ext_trig_ack_in(1);
Trig_Ack_In_2 <= ext_trig_ack_in(2);
Trig_Ack_In_3 <= ext_trig_ack_in(3);
Trig_Out_0 <= ext_trig_out(0);
Trig_Out_1 <= ext_trig_out(1);
Trig_Out_2 <= ext_trig_out(2);
Trig_Out_3 <= ext_trig_out(3);
-- Bus Master port
Use_Bus_MASTER : if (C_DBG_MEM_ACCESS = 1) generate
type LMB_vec_type is array (natural range <>) of std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_addr : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_write : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_addr_strobe : std_logic;
signal lmb_read_strobe : std_logic;
signal lmb_write_strobe : std_logic;
signal lmb_ready : std_logic;
signal lmb_wait : std_logic;
signal lmb_ue : std_logic;
signal lmb_byte_enable : std_logic_vector(0 to C_DATA_SIZE / 8 - 1);
signal lmb_addr_strobe_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec : LMB_vec_type(0 to 31);
signal lmb_ready_vec : std_logic_vector(0 to 31);
signal lmb_wait_vec : std_logic_vector(0 to 31);
signal lmb_ue_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec_q : LMB_vec_type(0 to C_EN_WIDTH - 1);
signal lmb_ready_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_wait_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_ue_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => true,
C_HAS_DIRECT_PORT => C_TRACE_AXI_MASTER
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => lmb_data_addr,
LMB_Data_Read => lmb_data_read,
LMB_Data_Write => lmb_data_write,
LMB_Addr_Strobe => lmb_addr_strobe,
LMB_Read_Strobe => lmb_read_strobe,
LMB_Write_Strobe => lmb_write_strobe,
LMB_Ready => lmb_ready,
LMB_Wait => lmb_wait,
LMB_UE => lmb_ue,
LMB_Byte_Enable => lmb_byte_enable,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
Generate_LMB_Outputs : process (mb_debug_enabled, lmb_addr_strobe)
begin -- process Generate_LMB_Outputs
lmb_addr_strobe_vec <= (others => '0');
for I in 0 to C_EN_WIDTH - 1 loop
lmb_addr_strobe_vec(I) <= lmb_addr_strobe and mb_debug_enabled(I);
end loop;
end process Generate_LMB_Outputs;
LMB_Addr_Strobe_0 <= lmb_addr_strobe_vec(0);
LMB_Addr_Strobe_1 <= lmb_addr_strobe_vec(1);
LMB_Addr_Strobe_2 <= lmb_addr_strobe_vec(2);
LMB_Addr_Strobe_3 <= lmb_addr_strobe_vec(3);
LMB_Addr_Strobe_4 <= lmb_addr_strobe_vec(4);
LMB_Addr_Strobe_5 <= lmb_addr_strobe_vec(5);
LMB_Addr_Strobe_6 <= lmb_addr_strobe_vec(6);
LMB_Addr_Strobe_7 <= lmb_addr_strobe_vec(7);
LMB_Addr_Strobe_8 <= lmb_addr_strobe_vec(8);
LMB_Addr_Strobe_9 <= lmb_addr_strobe_vec(9);
LMB_Addr_Strobe_10 <= lmb_addr_strobe_vec(10);
LMB_Addr_Strobe_11 <= lmb_addr_strobe_vec(11);
LMB_Addr_Strobe_12 <= lmb_addr_strobe_vec(12);
LMB_Addr_Strobe_13 <= lmb_addr_strobe_vec(13);
LMB_Addr_Strobe_14 <= lmb_addr_strobe_vec(14);
LMB_Addr_Strobe_15 <= lmb_addr_strobe_vec(15);
LMB_Addr_Strobe_16 <= lmb_addr_strobe_vec(16);
LMB_Addr_Strobe_17 <= lmb_addr_strobe_vec(17);
LMB_Addr_Strobe_18 <= lmb_addr_strobe_vec(18);
LMB_Addr_Strobe_19 <= lmb_addr_strobe_vec(19);
LMB_Addr_Strobe_20 <= lmb_addr_strobe_vec(20);
LMB_Addr_Strobe_21 <= lmb_addr_strobe_vec(21);
LMB_Addr_Strobe_22 <= lmb_addr_strobe_vec(22);
LMB_Addr_Strobe_23 <= lmb_addr_strobe_vec(23);
LMB_Addr_Strobe_24 <= lmb_addr_strobe_vec(24);
LMB_Addr_Strobe_25 <= lmb_addr_strobe_vec(25);
LMB_Addr_Strobe_26 <= lmb_addr_strobe_vec(26);
LMB_Addr_Strobe_27 <= lmb_addr_strobe_vec(27);
LMB_Addr_Strobe_28 <= lmb_addr_strobe_vec(28);
LMB_Addr_Strobe_29 <= lmb_addr_strobe_vec(29);
LMB_Addr_Strobe_30 <= lmb_addr_strobe_vec(30);
LMB_Addr_Strobe_31 <= lmb_addr_strobe_vec(31);
LMB_Data_Addr_0 <= lmb_data_addr;
LMB_Data_Addr_1 <= lmb_data_addr;
LMB_Data_Addr_2 <= lmb_data_addr;
LMB_Data_Addr_3 <= lmb_data_addr;
LMB_Data_Addr_4 <= lmb_data_addr;
LMB_Data_Addr_5 <= lmb_data_addr;
LMB_Data_Addr_6 <= lmb_data_addr;
LMB_Data_Addr_7 <= lmb_data_addr;
LMB_Data_Addr_8 <= lmb_data_addr;
LMB_Data_Addr_9 <= lmb_data_addr;
LMB_Data_Addr_10 <= lmb_data_addr;
LMB_Data_Addr_11 <= lmb_data_addr;
LMB_Data_Addr_12 <= lmb_data_addr;
LMB_Data_Addr_13 <= lmb_data_addr;
LMB_Data_Addr_14 <= lmb_data_addr;
LMB_Data_Addr_15 <= lmb_data_addr;
LMB_Data_Addr_16 <= lmb_data_addr;
LMB_Data_Addr_17 <= lmb_data_addr;
LMB_Data_Addr_18 <= lmb_data_addr;
LMB_Data_Addr_19 <= lmb_data_addr;
LMB_Data_Addr_20 <= lmb_data_addr;
LMB_Data_Addr_21 <= lmb_data_addr;
LMB_Data_Addr_22 <= lmb_data_addr;
LMB_Data_Addr_23 <= lmb_data_addr;
LMB_Data_Addr_24 <= lmb_data_addr;
LMB_Data_Addr_25 <= lmb_data_addr;
LMB_Data_Addr_26 <= lmb_data_addr;
LMB_Data_Addr_27 <= lmb_data_addr;
LMB_Data_Addr_28 <= lmb_data_addr;
LMB_Data_Addr_29 <= lmb_data_addr;
LMB_Data_Addr_30 <= lmb_data_addr;
LMB_Data_Addr_31 <= lmb_data_addr;
LMB_Data_write_0 <= lmb_data_write;
LMB_Data_write_1 <= lmb_data_write;
LMB_Data_write_2 <= lmb_data_write;
LMB_Data_write_3 <= lmb_data_write;
LMB_Data_write_4 <= lmb_data_write;
LMB_Data_write_5 <= lmb_data_write;
LMB_Data_write_6 <= lmb_data_write;
LMB_Data_write_7 <= lmb_data_write;
LMB_Data_write_8 <= lmb_data_write;
LMB_Data_write_9 <= lmb_data_write;
LMB_Data_write_10 <= lmb_data_write;
LMB_Data_write_11 <= lmb_data_write;
LMB_Data_write_12 <= lmb_data_write;
LMB_Data_write_13 <= lmb_data_write;
LMB_Data_write_14 <= lmb_data_write;
LMB_Data_write_15 <= lmb_data_write;
LMB_Data_write_16 <= lmb_data_write;
LMB_Data_write_17 <= lmb_data_write;
LMB_Data_write_18 <= lmb_data_write;
LMB_Data_write_19 <= lmb_data_write;
LMB_Data_write_20 <= lmb_data_write;
LMB_Data_write_21 <= lmb_data_write;
LMB_Data_write_22 <= lmb_data_write;
LMB_Data_write_23 <= lmb_data_write;
LMB_Data_write_24 <= lmb_data_write;
LMB_Data_write_25 <= lmb_data_write;
LMB_Data_write_26 <= lmb_data_write;
LMB_Data_write_27 <= lmb_data_write;
LMB_Data_write_28 <= lmb_data_write;
LMB_Data_write_29 <= lmb_data_write;
LMB_Data_write_30 <= lmb_data_write;
LMB_Data_write_31 <= lmb_data_write;
LMB_Read_strobe_0 <= lmb_read_strobe;
LMB_Read_strobe_1 <= lmb_read_strobe;
LMB_Read_strobe_2 <= lmb_read_strobe;
LMB_Read_strobe_3 <= lmb_read_strobe;
LMB_Read_strobe_4 <= lmb_read_strobe;
LMB_Read_strobe_5 <= lmb_read_strobe;
LMB_Read_strobe_6 <= lmb_read_strobe;
LMB_Read_strobe_7 <= lmb_read_strobe;
LMB_Read_strobe_8 <= lmb_read_strobe;
LMB_Read_strobe_9 <= lmb_read_strobe;
LMB_Read_strobe_10 <= lmb_read_strobe;
LMB_Read_strobe_11 <= lmb_read_strobe;
LMB_Read_strobe_12 <= lmb_read_strobe;
LMB_Read_strobe_13 <= lmb_read_strobe;
LMB_Read_strobe_14 <= lmb_read_strobe;
LMB_Read_strobe_15 <= lmb_read_strobe;
LMB_Read_strobe_16 <= lmb_read_strobe;
LMB_Read_strobe_17 <= lmb_read_strobe;
LMB_Read_strobe_18 <= lmb_read_strobe;
LMB_Read_strobe_19 <= lmb_read_strobe;
LMB_Read_strobe_20 <= lmb_read_strobe;
LMB_Read_strobe_21 <= lmb_read_strobe;
LMB_Read_strobe_22 <= lmb_read_strobe;
LMB_Read_strobe_23 <= lmb_read_strobe;
LMB_Read_strobe_24 <= lmb_read_strobe;
LMB_Read_strobe_25 <= lmb_read_strobe;
LMB_Read_strobe_26 <= lmb_read_strobe;
LMB_Read_strobe_27 <= lmb_read_strobe;
LMB_Read_strobe_28 <= lmb_read_strobe;
LMB_Read_strobe_29 <= lmb_read_strobe;
LMB_Read_strobe_30 <= lmb_read_strobe;
LMB_Read_strobe_31 <= lmb_read_strobe;
LMB_Write_strobe_0 <= lmb_write_strobe;
LMB_Write_strobe_1 <= lmb_write_strobe;
LMB_Write_strobe_2 <= lmb_write_strobe;
LMB_Write_strobe_3 <= lmb_write_strobe;
LMB_Write_strobe_4 <= lmb_write_strobe;
LMB_Write_strobe_5 <= lmb_write_strobe;
LMB_Write_strobe_6 <= lmb_write_strobe;
LMB_Write_strobe_7 <= lmb_write_strobe;
LMB_Write_strobe_8 <= lmb_write_strobe;
LMB_Write_strobe_9 <= lmb_write_strobe;
LMB_Write_strobe_10 <= lmb_write_strobe;
LMB_Write_strobe_11 <= lmb_write_strobe;
LMB_Write_strobe_12 <= lmb_write_strobe;
LMB_Write_strobe_13 <= lmb_write_strobe;
LMB_Write_strobe_14 <= lmb_write_strobe;
LMB_Write_strobe_15 <= lmb_write_strobe;
LMB_Write_strobe_16 <= lmb_write_strobe;
LMB_Write_strobe_17 <= lmb_write_strobe;
LMB_Write_strobe_18 <= lmb_write_strobe;
LMB_Write_strobe_19 <= lmb_write_strobe;
LMB_Write_strobe_20 <= lmb_write_strobe;
LMB_Write_strobe_21 <= lmb_write_strobe;
LMB_Write_strobe_22 <= lmb_write_strobe;
LMB_Write_strobe_23 <= lmb_write_strobe;
LMB_Write_strobe_24 <= lmb_write_strobe;
LMB_Write_strobe_25 <= lmb_write_strobe;
LMB_Write_strobe_26 <= lmb_write_strobe;
LMB_Write_strobe_27 <= lmb_write_strobe;
LMB_Write_strobe_28 <= lmb_write_strobe;
LMB_Write_strobe_29 <= lmb_write_strobe;
LMB_Write_strobe_30 <= lmb_write_strobe;
LMB_Write_strobe_31 <= lmb_write_strobe;
LMB_Byte_enable_0 <= lmb_byte_enable;
LMB_Byte_enable_1 <= lmb_byte_enable;
LMB_Byte_enable_2 <= lmb_byte_enable;
LMB_Byte_enable_3 <= lmb_byte_enable;
LMB_Byte_enable_4 <= lmb_byte_enable;
LMB_Byte_enable_5 <= lmb_byte_enable;
LMB_Byte_enable_6 <= lmb_byte_enable;
LMB_Byte_enable_7 <= lmb_byte_enable;
LMB_Byte_enable_8 <= lmb_byte_enable;
LMB_Byte_enable_9 <= lmb_byte_enable;
LMB_Byte_enable_10 <= lmb_byte_enable;
LMB_Byte_enable_11 <= lmb_byte_enable;
LMB_Byte_enable_12 <= lmb_byte_enable;
LMB_Byte_enable_13 <= lmb_byte_enable;
LMB_Byte_enable_14 <= lmb_byte_enable;
LMB_Byte_enable_15 <= lmb_byte_enable;
LMB_Byte_enable_16 <= lmb_byte_enable;
LMB_Byte_enable_17 <= lmb_byte_enable;
LMB_Byte_enable_18 <= lmb_byte_enable;
LMB_Byte_enable_19 <= lmb_byte_enable;
LMB_Byte_enable_20 <= lmb_byte_enable;
LMB_Byte_enable_21 <= lmb_byte_enable;
LMB_Byte_enable_22 <= lmb_byte_enable;
LMB_Byte_enable_23 <= lmb_byte_enable;
LMB_Byte_enable_24 <= lmb_byte_enable;
LMB_Byte_enable_25 <= lmb_byte_enable;
LMB_Byte_enable_26 <= lmb_byte_enable;
LMB_Byte_enable_27 <= lmb_byte_enable;
LMB_Byte_enable_28 <= lmb_byte_enable;
LMB_Byte_enable_29 <= lmb_byte_enable;
LMB_Byte_enable_30 <= lmb_byte_enable;
LMB_Byte_enable_31 <= lmb_byte_enable;
Generate_LMB_Inputs : process (mb_debug_enabled, lmb_data_read_vec_q, lmb_ready_vec_q, lmb_wait_vec_q, lmb_ue_vec_q)
variable data_mask : std_logic_vector(0 to C_DATA_SIZE - 1);
variable data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
variable ready : std_logic;
variable wait_i : std_logic;
variable ue : std_logic;
begin -- process Generate_LMB_Inputs
data_read := (others => '0');
ready := '0';
wait_i := '0';
ue := '0';
for I in 0 to C_EN_WIDTH - 1 loop
data_mask := (0 to C_DATA_SIZE - 1 => mb_debug_enabled(I));
data_read := data_read or (lmb_data_read_vec_q(I) and data_mask);
ready := ready or (lmb_ready_vec_q(I) and mb_debug_enabled(I));
wait_i := wait_i or (lmb_wait_vec_q(I) and mb_debug_enabled(I));
ue := ue or (lmb_ue_vec_q(I) and mb_debug_enabled(I));
end loop;
lmb_data_read <= data_read;
lmb_ready <= ready;
lmb_wait <= wait_i;
lmb_ue <= ue;
end process Generate_LMB_Inputs;
Clock_LMB_Inputs : process (M_AXI_ACLK)
begin
if M_AXI_ACLK'event and M_AXI_ACLK = '1' then -- rising clock edge
for I in 0 to C_EN_WIDTH - 1 loop
lmb_data_read_vec_q(I) <= lmb_data_read_vec(I);
lmb_ready_vec_q(I) <= lmb_ready_vec(I);
lmb_wait_vec_q(I) <= lmb_wait_vec(I);
lmb_ue_vec_q(I) <= lmb_ue_vec(I);
end loop;
end if;
end process Clock_LMB_Inputs;
lmb_data_read_vec(0) <= LMB_Data_Read_0;
lmb_data_read_vec(1) <= LMB_Data_Read_1;
lmb_data_read_vec(2) <= LMB_Data_Read_2;
lmb_data_read_vec(3) <= LMB_Data_Read_3;
lmb_data_read_vec(4) <= LMB_Data_Read_4;
lmb_data_read_vec(5) <= LMB_Data_Read_5;
lmb_data_read_vec(6) <= LMB_Data_Read_6;
lmb_data_read_vec(7) <= LMB_Data_Read_7;
lmb_data_read_vec(8) <= LMB_Data_Read_8;
lmb_data_read_vec(9) <= LMB_Data_Read_9;
lmb_data_read_vec(10) <= LMB_Data_Read_10;
lmb_data_read_vec(11) <= LMB_Data_Read_11;
lmb_data_read_vec(12) <= LMB_Data_Read_12;
lmb_data_read_vec(13) <= LMB_Data_Read_13;
lmb_data_read_vec(14) <= LMB_Data_Read_14;
lmb_data_read_vec(15) <= LMB_Data_Read_15;
lmb_data_read_vec(16) <= LMB_Data_Read_16;
lmb_data_read_vec(17) <= LMB_Data_Read_17;
lmb_data_read_vec(18) <= LMB_Data_Read_18;
lmb_data_read_vec(19) <= LMB_Data_Read_19;
lmb_data_read_vec(20) <= LMB_Data_Read_20;
lmb_data_read_vec(21) <= LMB_Data_Read_21;
lmb_data_read_vec(22) <= LMB_Data_Read_22;
lmb_data_read_vec(23) <= LMB_Data_Read_23;
lmb_data_read_vec(24) <= LMB_Data_Read_24;
lmb_data_read_vec(25) <= LMB_Data_Read_25;
lmb_data_read_vec(26) <= LMB_Data_Read_26;
lmb_data_read_vec(27) <= LMB_Data_Read_27;
lmb_data_read_vec(28) <= LMB_Data_Read_28;
lmb_data_read_vec(29) <= LMB_Data_Read_29;
lmb_data_read_vec(30) <= LMB_Data_Read_30;
lmb_data_read_vec(31) <= LMB_Data_Read_31;
lmb_ready_vec(0) <= LMB_Ready_0;
lmb_ready_vec(1) <= LMB_Ready_1;
lmb_ready_vec(2) <= LMB_Ready_2;
lmb_ready_vec(3) <= LMB_Ready_3;
lmb_ready_vec(4) <= LMB_Ready_4;
lmb_ready_vec(5) <= LMB_Ready_5;
lmb_ready_vec(6) <= LMB_Ready_6;
lmb_ready_vec(7) <= LMB_Ready_7;
lmb_ready_vec(8) <= LMB_Ready_8;
lmb_ready_vec(9) <= LMB_Ready_9;
lmb_ready_vec(10) <= LMB_Ready_10;
lmb_ready_vec(11) <= LMB_Ready_11;
lmb_ready_vec(12) <= LMB_Ready_12;
lmb_ready_vec(13) <= LMB_Ready_13;
lmb_ready_vec(14) <= LMB_Ready_14;
lmb_ready_vec(15) <= LMB_Ready_15;
lmb_ready_vec(16) <= LMB_Ready_16;
lmb_ready_vec(17) <= LMB_Ready_17;
lmb_ready_vec(18) <= LMB_Ready_18;
lmb_ready_vec(19) <= LMB_Ready_19;
lmb_ready_vec(20) <= LMB_Ready_20;
lmb_ready_vec(21) <= LMB_Ready_21;
lmb_ready_vec(22) <= LMB_Ready_22;
lmb_ready_vec(23) <= LMB_Ready_23;
lmb_ready_vec(24) <= LMB_Ready_24;
lmb_ready_vec(25) <= LMB_Ready_25;
lmb_ready_vec(26) <= LMB_Ready_26;
lmb_ready_vec(27) <= LMB_Ready_27;
lmb_ready_vec(28) <= LMB_Ready_28;
lmb_ready_vec(29) <= LMB_Ready_29;
lmb_ready_vec(30) <= LMB_Ready_30;
lmb_ready_vec(31) <= LMB_Ready_31;
lmb_wait_vec(0) <= LMB_Wait_0;
lmb_wait_vec(1) <= LMB_Wait_1;
lmb_wait_vec(2) <= LMB_Wait_2;
lmb_wait_vec(3) <= LMB_Wait_3;
lmb_wait_vec(4) <= LMB_Wait_4;
lmb_wait_vec(5) <= LMB_Wait_5;
lmb_wait_vec(6) <= LMB_Wait_6;
lmb_wait_vec(7) <= LMB_Wait_7;
lmb_wait_vec(8) <= LMB_Wait_8;
lmb_wait_vec(9) <= LMB_Wait_9;
lmb_wait_vec(10) <= LMB_Wait_10;
lmb_wait_vec(11) <= LMB_Wait_11;
lmb_wait_vec(12) <= LMB_Wait_12;
lmb_wait_vec(13) <= LMB_Wait_13;
lmb_wait_vec(14) <= LMB_Wait_14;
lmb_wait_vec(15) <= LMB_Wait_15;
lmb_wait_vec(16) <= LMB_Wait_16;
lmb_wait_vec(17) <= LMB_Wait_17;
lmb_wait_vec(18) <= LMB_Wait_18;
lmb_wait_vec(19) <= LMB_Wait_19;
lmb_wait_vec(20) <= LMB_Wait_20;
lmb_wait_vec(21) <= LMB_Wait_21;
lmb_wait_vec(22) <= LMB_Wait_22;
lmb_wait_vec(23) <= LMB_Wait_23;
lmb_wait_vec(24) <= LMB_Wait_24;
lmb_wait_vec(25) <= LMB_Wait_25;
lmb_wait_vec(26) <= LMB_Wait_26;
lmb_wait_vec(27) <= LMB_Wait_27;
lmb_wait_vec(28) <= LMB_Wait_28;
lmb_wait_vec(29) <= LMB_Wait_29;
lmb_wait_vec(30) <= LMB_Wait_30;
lmb_wait_vec(31) <= LMB_Wait_31;
lmb_ue_vec(0) <= LMB_UE_0;
lmb_ue_vec(1) <= LMB_UE_1;
lmb_ue_vec(2) <= LMB_UE_2;
lmb_ue_vec(3) <= LMB_UE_3;
lmb_ue_vec(4) <= LMB_UE_4;
lmb_ue_vec(5) <= LMB_UE_5;
lmb_ue_vec(6) <= LMB_UE_6;
lmb_ue_vec(7) <= LMB_UE_7;
lmb_ue_vec(8) <= LMB_UE_8;
lmb_ue_vec(9) <= LMB_UE_9;
lmb_ue_vec(10) <= LMB_UE_10;
lmb_ue_vec(11) <= LMB_UE_11;
lmb_ue_vec(12) <= LMB_UE_12;
lmb_ue_vec(13) <= LMB_UE_13;
lmb_ue_vec(14) <= LMB_UE_14;
lmb_ue_vec(15) <= LMB_UE_15;
lmb_ue_vec(16) <= LMB_UE_16;
lmb_ue_vec(17) <= LMB_UE_17;
lmb_ue_vec(18) <= LMB_UE_18;
lmb_ue_vec(19) <= LMB_UE_19;
lmb_ue_vec(20) <= LMB_UE_20;
lmb_ue_vec(21) <= LMB_UE_21;
lmb_ue_vec(22) <= LMB_UE_22;
lmb_ue_vec(23) <= LMB_UE_23;
lmb_ue_vec(24) <= LMB_UE_24;
lmb_ue_vec(25) <= LMB_UE_25;
lmb_ue_vec(26) <= LMB_UE_26;
lmb_ue_vec(27) <= LMB_UE_27;
lmb_ue_vec(28) <= LMB_UE_28;
lmb_ue_vec(29) <= LMB_UE_29;
lmb_ue_vec(30) <= LMB_UE_30;
lmb_ue_vec(31) <= LMB_UE_31;
end generate Use_Bus_MASTER;
Use_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and C_TRACE_AXI_MASTER) generate
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => false,
C_HAS_DIRECT_PORT => true
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => open,
LMB_Data_Read => (others => '0'),
LMB_Data_Write => open,
LMB_Addr_Strobe => open,
LMB_Read_Strobe => open,
LMB_Write_Strobe => open,
LMB_Ready => '0',
LMB_Wait => '0',
LMB_UE => '0',
LMB_Byte_Enable => open,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
end generate Use_Bus_MASTER_AXI;
No_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and not C_TRACE_AXI_MASTER) generate
begin
master_rd_idle <= '1';
master_rd_resp <= "00";
master_wr_idle <= '1';
master_wr_resp <= "00";
master_data_out <= (others => '0');
master_data_exists <= '0';
master_data_empty <= '1';
master_dwr_next <= '0';
master_dwr_done <= '0';
master_dwr_resp <= (others => '0');
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= (others => '0');
M_AXI_AWLEN <= (others => '0');
M_AXI_AWSIZE <= (others => '0');
M_AXI_AWBURST <= (others => '0');
M_AXI_AWLOCK <= '0';
M_AXI_AWCACHE <= (others => '0');
M_AXI_AWPROT <= (others => '0');
M_AXI_AWQOS <= (others => '0');
M_AXI_AWVALID <= '0';
M_AXI_WDATA <= (others => '0');
M_AXI_WSTRB <= (others => '0');
M_AXI_WLAST <= '0';
M_AXI_WVALID <= '0';
M_AXI_BREADY <= '0';
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= (others => '0');
M_AXI_ARBURST <= (others => '0');
M_AXI_ARLOCK <= '0';
M_AXI_ARCACHE <= (others => '0');
M_AXI_ARPROT <= (others => '0');
M_AXI_ARQOS <= (others => '0');
M_AXI_ARVALID <= '0';
M_AXI_RREADY <= '0';
end generate No_Bus_MASTER_AXI;
No_Bus_MASTER_LMB : if (C_DBG_MEM_ACCESS = 0) generate
begin
LMB_Data_Addr_0 <= (others => '0');
LMB_Data_Write_0 <= (others => '0');
LMB_Addr_Strobe_0 <= '0';
LMB_Read_Strobe_0 <= '0';
LMB_Write_Strobe_0 <= '0';
LMB_Byte_Enable_0 <= (others => '0');
LMB_Data_Addr_1 <= (others => '0');
LMB_Data_Write_1 <= (others => '0');
LMB_Addr_Strobe_1 <= '0';
LMB_Read_Strobe_1 <= '0';
LMB_Write_Strobe_1 <= '0';
LMB_Byte_Enable_1 <= (others => '0');
LMB_Data_Addr_2 <= (others => '0');
LMB_Data_Write_2 <= (others => '0');
LMB_Addr_Strobe_2 <= '0';
LMB_Read_Strobe_2 <= '0';
LMB_Write_Strobe_2 <= '0';
LMB_Byte_Enable_2 <= (others => '0');
LMB_Data_Addr_3 <= (others => '0');
LMB_Data_Write_3 <= (others => '0');
LMB_Addr_Strobe_3 <= '0';
LMB_Read_Strobe_3 <= '0';
LMB_Write_Strobe_3 <= '0';
LMB_Byte_Enable_3 <= (others => '0');
LMB_Data_Addr_4 <= (others => '0');
LMB_Data_Write_4 <= (others => '0');
LMB_Addr_Strobe_4 <= '0';
LMB_Read_Strobe_4 <= '0';
LMB_Write_Strobe_4 <= '0';
LMB_Byte_Enable_4 <= (others => '0');
LMB_Data_Addr_5 <= (others => '0');
LMB_Data_Write_5 <= (others => '0');
LMB_Addr_Strobe_5 <= '0';
LMB_Read_Strobe_5 <= '0';
LMB_Write_Strobe_5 <= '0';
LMB_Byte_Enable_5 <= (others => '0');
LMB_Data_Addr_6 <= (others => '0');
LMB_Data_Write_6 <= (others => '0');
LMB_Addr_Strobe_6 <= '0';
LMB_Read_Strobe_6 <= '0';
LMB_Write_Strobe_6 <= '0';
LMB_Byte_Enable_6 <= (others => '0');
LMB_Data_Addr_7 <= (others => '0');
LMB_Data_Write_7 <= (others => '0');
LMB_Addr_Strobe_7 <= '0';
LMB_Read_Strobe_7 <= '0';
LMB_Write_Strobe_7 <= '0';
LMB_Byte_Enable_7 <= (others => '0');
LMB_Data_Addr_8 <= (others => '0');
LMB_Data_Write_8 <= (others => '0');
LMB_Addr_Strobe_8 <= '0';
LMB_Read_Strobe_8 <= '0';
LMB_Write_Strobe_8 <= '0';
LMB_Byte_Enable_8 <= (others => '0');
LMB_Data_Addr_9 <= (others => '0');
LMB_Data_Write_9 <= (others => '0');
LMB_Addr_Strobe_9 <= '0';
LMB_Read_Strobe_9 <= '0';
LMB_Write_Strobe_9 <= '0';
LMB_Byte_Enable_9 <= (others => '0');
LMB_Data_Addr_10 <= (others => '0');
LMB_Data_Write_10 <= (others => '0');
LMB_Addr_Strobe_10 <= '0';
LMB_Read_Strobe_10 <= '0';
LMB_Write_Strobe_10 <= '0';
LMB_Byte_Enable_10 <= (others => '0');
LMB_Data_Addr_11 <= (others => '0');
LMB_Data_Write_11 <= (others => '0');
LMB_Addr_Strobe_11 <= '0';
LMB_Read_Strobe_11 <= '0';
LMB_Write_Strobe_11 <= '0';
LMB_Byte_Enable_11 <= (others => '0');
LMB_Data_Addr_12 <= (others => '0');
LMB_Data_Write_12 <= (others => '0');
LMB_Addr_Strobe_12 <= '0';
LMB_Read_Strobe_12 <= '0';
LMB_Write_Strobe_12 <= '0';
LMB_Byte_Enable_12 <= (others => '0');
LMB_Data_Addr_13 <= (others => '0');
LMB_Data_Write_13 <= (others => '0');
LMB_Addr_Strobe_13 <= '0';
LMB_Read_Strobe_13 <= '0';
LMB_Write_Strobe_13 <= '0';
LMB_Byte_Enable_13 <= (others => '0');
LMB_Data_Addr_14 <= (others => '0');
LMB_Data_Write_14 <= (others => '0');
LMB_Addr_Strobe_14 <= '0';
LMB_Read_Strobe_14 <= '0';
LMB_Write_Strobe_14 <= '0';
LMB_Byte_Enable_14 <= (others => '0');
LMB_Data_Addr_15 <= (others => '0');
LMB_Data_Write_15 <= (others => '0');
LMB_Addr_Strobe_15 <= '0';
LMB_Read_Strobe_15 <= '0';
LMB_Write_Strobe_15 <= '0';
LMB_Byte_Enable_15 <= (others => '0');
LMB_Data_Addr_16 <= (others => '0');
LMB_Data_Write_16 <= (others => '0');
LMB_Addr_Strobe_16 <= '0';
LMB_Read_Strobe_16 <= '0';
LMB_Write_Strobe_16 <= '0';
LMB_Byte_Enable_16 <= (others => '0');
LMB_Data_Addr_17 <= (others => '0');
LMB_Data_Write_17 <= (others => '0');
LMB_Addr_Strobe_17 <= '0';
LMB_Read_Strobe_17 <= '0';
LMB_Write_Strobe_17 <= '0';
LMB_Byte_Enable_17 <= (others => '0');
LMB_Data_Addr_18 <= (others => '0');
LMB_Data_Write_18 <= (others => '0');
LMB_Addr_Strobe_18 <= '0';
LMB_Read_Strobe_18 <= '0';
LMB_Write_Strobe_18 <= '0';
LMB_Byte_Enable_18 <= (others => '0');
LMB_Data_Addr_19 <= (others => '0');
LMB_Data_Write_19 <= (others => '0');
LMB_Addr_Strobe_19 <= '0';
LMB_Read_Strobe_19 <= '0';
LMB_Write_Strobe_19 <= '0';
LMB_Byte_Enable_19 <= (others => '0');
LMB_Data_Addr_20 <= (others => '0');
LMB_Data_Write_20 <= (others => '0');
LMB_Addr_Strobe_20 <= '0';
LMB_Read_Strobe_20 <= '0';
LMB_Write_Strobe_20 <= '0';
LMB_Byte_Enable_20 <= (others => '0');
LMB_Data_Addr_21 <= (others => '0');
LMB_Data_Write_21 <= (others => '0');
LMB_Addr_Strobe_21 <= '0';
LMB_Read_Strobe_21 <= '0';
LMB_Write_Strobe_21 <= '0';
LMB_Byte_Enable_21 <= (others => '0');
LMB_Data_Addr_22 <= (others => '0');
LMB_Data_Write_22 <= (others => '0');
LMB_Addr_Strobe_22 <= '0';
LMB_Read_Strobe_22 <= '0';
LMB_Write_Strobe_22 <= '0';
LMB_Byte_Enable_22 <= (others => '0');
LMB_Data_Addr_23 <= (others => '0');
LMB_Data_Write_23 <= (others => '0');
LMB_Addr_Strobe_23 <= '0';
LMB_Read_Strobe_23 <= '0';
LMB_Write_Strobe_23 <= '0';
LMB_Byte_Enable_23 <= (others => '0');
LMB_Data_Addr_24 <= (others => '0');
LMB_Data_Write_24 <= (others => '0');
LMB_Addr_Strobe_24 <= '0';
LMB_Read_Strobe_24 <= '0';
LMB_Write_Strobe_24 <= '0';
LMB_Byte_Enable_24 <= (others => '0');
LMB_Data_Addr_25 <= (others => '0');
LMB_Data_Write_25 <= (others => '0');
LMB_Addr_Strobe_25 <= '0';
LMB_Read_Strobe_25 <= '0';
LMB_Write_Strobe_25 <= '0';
LMB_Byte_Enable_25 <= (others => '0');
LMB_Data_Addr_26 <= (others => '0');
LMB_Data_Write_26 <= (others => '0');
LMB_Addr_Strobe_26 <= '0';
LMB_Read_Strobe_26 <= '0';
LMB_Write_Strobe_26 <= '0';
LMB_Byte_Enable_26 <= (others => '0');
LMB_Data_Addr_27 <= (others => '0');
LMB_Data_Write_27 <= (others => '0');
LMB_Addr_Strobe_27 <= '0';
LMB_Read_Strobe_27 <= '0';
LMB_Write_Strobe_27 <= '0';
LMB_Byte_Enable_27 <= (others => '0');
LMB_Data_Addr_28 <= (others => '0');
LMB_Data_Write_28 <= (others => '0');
LMB_Addr_Strobe_28 <= '0';
LMB_Read_Strobe_28 <= '0';
LMB_Write_Strobe_28 <= '0';
LMB_Byte_Enable_28 <= (others => '0');
LMB_Data_Addr_29 <= (others => '0');
LMB_Data_Write_29 <= (others => '0');
LMB_Addr_Strobe_29 <= '0';
LMB_Read_Strobe_29 <= '0';
LMB_Write_Strobe_29 <= '0';
LMB_Byte_Enable_29 <= (others => '0');
LMB_Data_Addr_30 <= (others => '0');
LMB_Data_Write_30 <= (others => '0');
LMB_Addr_Strobe_30 <= '0';
LMB_Read_Strobe_30 <= '0';
LMB_Write_Strobe_30 <= '0';
LMB_Byte_Enable_30 <= (others => '0');
LMB_Data_Addr_31 <= (others => '0');
LMB_Data_Write_31 <= (others => '0');
LMB_Addr_Strobe_31 <= '0';
LMB_Read_Strobe_31 <= '0';
LMB_Write_Strobe_31 <= '0';
LMB_Byte_Enable_31 <= (others => '0');
end generate No_Bus_MASTER_LMB;
Use_AXI_IPIF : if (C_USE_UART = 1) or (C_DBG_REG_ACCESS = 1) generate
begin
-- ip2bus_data assignment - as core may use less than 32 bits
ip2bus_data(C_S_AXI_DATA_WIDTH-1 downto C_REG_DATA_WIDTH) <= (others => '0');
---------------------------------------------------------------------------
-- AXI lite IPIF
---------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map (
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end generate Use_AXI_IPIF;
No_AXI_IPIF : if (C_USE_UART = 0) and (C_DBG_REG_ACCESS = 0) generate
begin
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
S_AXI_BRESP <= (others => '0');
S_AXI_BVALID <= '0';
S_AXI_ARREADY <= '0';
S_AXI_RDATA <= (others => '0');
S_AXI_RRESP <= (others => '0');
S_AXI_RVALID <= '0';
bus2ip_clk <= '0';
bus2ip_resetn <= '0';
bus2ip_data <= (others => '0');
bus2ip_rdce <= (others => '0');
bus2ip_wrce <= (others => '0');
bus2ip_cs <= (others => '0');
end generate No_AXI_IPIF;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2006-10-27 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
-- stefana 2014-04-30 Added external trace support
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library mdm_v3_2;
use mdm_v3_2.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
entity MDM is
generic (
C_FAMILY : string := "virtex7";
C_JTAG_CHAIN : integer := 2;
C_USE_BSCAN : integer := 0;
C_USE_CONFIG_RESET : integer := 0;
C_INTERCONNECT : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_FFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"0000_0000";
C_MB_DBG_PORTS : integer := 1;
C_DBG_REG_ACCESS : integer := 0;
C_DBG_MEM_ACCESS : integer := 0;
C_USE_UART : integer := 1;
C_USE_CROSS_TRIGGER : integer := 0;
C_TRACE_OUTPUT : integer := 0;
C_TRACE_DATA_WIDTH : integer range 2 to 32 := 32;
C_TRACE_CLK_FREQ_HZ : integer := 200000000;
C_TRACE_CLK_OUT_PHASE : integer range 0 to 360 := 90;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_THREAD_ID_WIDTH : integer := 1;
C_DATA_SIZE : integer range 32 to 32 := 32;
C_M_AXIS_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXIS_ID_WIDTH : integer range 1 to 7 := 7
);
port (
-- Global signals
Config_Reset : in std_logic := '0';
Scan_Reset_Sel : in std_logic := '0';
Scan_Reset : in std_logic := '0';
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- External cross trigger signals
Trig_In_0 : in std_logic;
Trig_Ack_In_0 : out std_logic;
Trig_Out_0 : out std_logic;
Trig_Ack_Out_0 : in std_logic;
Trig_In_1 : in std_logic;
Trig_Ack_In_1 : out std_logic;
Trig_Out_1 : out std_logic;
Trig_Ack_Out_1 : in std_logic;
Trig_In_2 : in std_logic;
Trig_Ack_In_2 : out std_logic;
Trig_Out_2 : out std_logic;
Trig_Ack_Out_2 : in std_logic;
Trig_In_3 : in std_logic;
Trig_Ack_In_3 : out std_logic;
Trig_Out_3 : out std_logic;
Trig_Ack_Out_3 : in std_logic;
-- AXI slave signals
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Bus master signals
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
LMB_Data_Addr_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_0 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_0 : out std_logic;
LMB_Read_Strobe_0 : out std_logic;
LMB_Write_Strobe_0 : out std_logic;
LMB_Ready_0 : in std_logic;
LMB_Wait_0 : in std_logic;
LMB_CE_0 : in std_logic;
LMB_UE_0 : in std_logic;
LMB_Byte_Enable_0 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_1 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_1 : out std_logic;
LMB_Read_Strobe_1 : out std_logic;
LMB_Write_Strobe_1 : out std_logic;
LMB_Ready_1 : in std_logic;
LMB_Wait_1 : in std_logic;
LMB_CE_1 : in std_logic;
LMB_UE_1 : in std_logic;
LMB_Byte_Enable_1 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_2 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_2 : out std_logic;
LMB_Read_Strobe_2 : out std_logic;
LMB_Write_Strobe_2 : out std_logic;
LMB_Ready_2 : in std_logic;
LMB_Wait_2 : in std_logic;
LMB_CE_2 : in std_logic;
LMB_UE_2 : in std_logic;
LMB_Byte_Enable_2 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_3 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_3 : out std_logic;
LMB_Read_Strobe_3 : out std_logic;
LMB_Write_Strobe_3 : out std_logic;
LMB_Ready_3 : in std_logic;
LMB_Wait_3 : in std_logic;
LMB_CE_3 : in std_logic;
LMB_UE_3 : in std_logic;
LMB_Byte_Enable_3 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_4 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_4 : out std_logic;
LMB_Read_Strobe_4 : out std_logic;
LMB_Write_Strobe_4 : out std_logic;
LMB_Ready_4 : in std_logic;
LMB_Wait_4 : in std_logic;
LMB_CE_4 : in std_logic;
LMB_UE_4 : in std_logic;
LMB_Byte_Enable_4 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_5 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_5 : out std_logic;
LMB_Read_Strobe_5 : out std_logic;
LMB_Write_Strobe_5 : out std_logic;
LMB_Ready_5 : in std_logic;
LMB_Wait_5 : in std_logic;
LMB_CE_5 : in std_logic;
LMB_UE_5 : in std_logic;
LMB_Byte_Enable_5 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_6 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_6 : out std_logic;
LMB_Read_Strobe_6 : out std_logic;
LMB_Write_Strobe_6 : out std_logic;
LMB_Ready_6 : in std_logic;
LMB_Wait_6 : in std_logic;
LMB_CE_6 : in std_logic;
LMB_UE_6 : in std_logic;
LMB_Byte_Enable_6 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_7 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_7 : out std_logic;
LMB_Read_Strobe_7 : out std_logic;
LMB_Write_Strobe_7 : out std_logic;
LMB_Ready_7 : in std_logic;
LMB_Wait_7 : in std_logic;
LMB_CE_7 : in std_logic;
LMB_UE_7 : in std_logic;
LMB_Byte_Enable_7 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_8 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_8 : out std_logic;
LMB_Read_Strobe_8 : out std_logic;
LMB_Write_Strobe_8 : out std_logic;
LMB_Ready_8 : in std_logic;
LMB_Wait_8 : in std_logic;
LMB_CE_8 : in std_logic;
LMB_UE_8 : in std_logic;
LMB_Byte_Enable_8 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_9 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_9 : out std_logic;
LMB_Read_Strobe_9 : out std_logic;
LMB_Write_Strobe_9 : out std_logic;
LMB_Ready_9 : in std_logic;
LMB_Wait_9 : in std_logic;
LMB_CE_9 : in std_logic;
LMB_UE_9 : in std_logic;
LMB_Byte_Enable_9 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_10 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_10 : out std_logic;
LMB_Read_Strobe_10 : out std_logic;
LMB_Write_Strobe_10 : out std_logic;
LMB_Ready_10 : in std_logic;
LMB_Wait_10 : in std_logic;
LMB_CE_10 : in std_logic;
LMB_UE_10 : in std_logic;
LMB_Byte_Enable_10 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_11 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_11 : out std_logic;
LMB_Read_Strobe_11 : out std_logic;
LMB_Write_Strobe_11 : out std_logic;
LMB_Ready_11 : in std_logic;
LMB_Wait_11 : in std_logic;
LMB_CE_11 : in std_logic;
LMB_UE_11 : in std_logic;
LMB_Byte_Enable_11 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_12 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_12 : out std_logic;
LMB_Read_Strobe_12 : out std_logic;
LMB_Write_Strobe_12 : out std_logic;
LMB_Ready_12 : in std_logic;
LMB_Wait_12 : in std_logic;
LMB_CE_12 : in std_logic;
LMB_UE_12 : in std_logic;
LMB_Byte_Enable_12 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_13 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_13 : out std_logic;
LMB_Read_Strobe_13 : out std_logic;
LMB_Write_Strobe_13 : out std_logic;
LMB_Ready_13 : in std_logic;
LMB_Wait_13 : in std_logic;
LMB_CE_13 : in std_logic;
LMB_UE_13 : in std_logic;
LMB_Byte_Enable_13 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_14 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_14 : out std_logic;
LMB_Read_Strobe_14 : out std_logic;
LMB_Write_Strobe_14 : out std_logic;
LMB_Ready_14 : in std_logic;
LMB_Wait_14 : in std_logic;
LMB_CE_14 : in std_logic;
LMB_UE_14 : in std_logic;
LMB_Byte_Enable_14 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_15 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_15 : out std_logic;
LMB_Read_Strobe_15 : out std_logic;
LMB_Write_Strobe_15 : out std_logic;
LMB_Ready_15 : in std_logic;
LMB_Wait_15 : in std_logic;
LMB_CE_15 : in std_logic;
LMB_UE_15 : in std_logic;
LMB_Byte_Enable_15 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_16 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_16 : out std_logic;
LMB_Read_Strobe_16 : out std_logic;
LMB_Write_Strobe_16 : out std_logic;
LMB_Ready_16 : in std_logic;
LMB_Wait_16 : in std_logic;
LMB_CE_16 : in std_logic;
LMB_UE_16 : in std_logic;
LMB_Byte_Enable_16 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_17 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_17 : out std_logic;
LMB_Read_Strobe_17 : out std_logic;
LMB_Write_Strobe_17 : out std_logic;
LMB_Ready_17 : in std_logic;
LMB_Wait_17 : in std_logic;
LMB_CE_17 : in std_logic;
LMB_UE_17 : in std_logic;
LMB_Byte_Enable_17 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_18 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_18 : out std_logic;
LMB_Read_Strobe_18 : out std_logic;
LMB_Write_Strobe_18 : out std_logic;
LMB_Ready_18 : in std_logic;
LMB_Wait_18 : in std_logic;
LMB_CE_18 : in std_logic;
LMB_UE_18 : in std_logic;
LMB_Byte_Enable_18 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_19 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_19 : out std_logic;
LMB_Read_Strobe_19 : out std_logic;
LMB_Write_Strobe_19 : out std_logic;
LMB_Ready_19 : in std_logic;
LMB_Wait_19 : in std_logic;
LMB_CE_19 : in std_logic;
LMB_UE_19 : in std_logic;
LMB_Byte_Enable_19 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_20 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_20 : out std_logic;
LMB_Read_Strobe_20 : out std_logic;
LMB_Write_Strobe_20 : out std_logic;
LMB_Ready_20 : in std_logic;
LMB_Wait_20 : in std_logic;
LMB_CE_20 : in std_logic;
LMB_UE_20 : in std_logic;
LMB_Byte_Enable_20 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_21 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_21 : out std_logic;
LMB_Read_Strobe_21 : out std_logic;
LMB_Write_Strobe_21 : out std_logic;
LMB_Ready_21 : in std_logic;
LMB_Wait_21 : in std_logic;
LMB_CE_21 : in std_logic;
LMB_UE_21 : in std_logic;
LMB_Byte_Enable_21 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_22 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_22 : out std_logic;
LMB_Read_Strobe_22 : out std_logic;
LMB_Write_Strobe_22 : out std_logic;
LMB_Ready_22 : in std_logic;
LMB_Wait_22 : in std_logic;
LMB_CE_22 : in std_logic;
LMB_UE_22 : in std_logic;
LMB_Byte_Enable_22 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_23 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_23 : out std_logic;
LMB_Read_Strobe_23 : out std_logic;
LMB_Write_Strobe_23 : out std_logic;
LMB_Ready_23 : in std_logic;
LMB_Wait_23 : in std_logic;
LMB_CE_23 : in std_logic;
LMB_UE_23 : in std_logic;
LMB_Byte_Enable_23 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_24 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_24 : out std_logic;
LMB_Read_Strobe_24 : out std_logic;
LMB_Write_Strobe_24 : out std_logic;
LMB_Ready_24 : in std_logic;
LMB_Wait_24 : in std_logic;
LMB_CE_24 : in std_logic;
LMB_UE_24 : in std_logic;
LMB_Byte_Enable_24 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_25 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_25 : out std_logic;
LMB_Read_Strobe_25 : out std_logic;
LMB_Write_Strobe_25 : out std_logic;
LMB_Ready_25 : in std_logic;
LMB_Wait_25 : in std_logic;
LMB_CE_25 : in std_logic;
LMB_UE_25 : in std_logic;
LMB_Byte_Enable_25 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_26 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_26 : out std_logic;
LMB_Read_Strobe_26 : out std_logic;
LMB_Write_Strobe_26 : out std_logic;
LMB_Ready_26 : in std_logic;
LMB_Wait_26 : in std_logic;
LMB_CE_26 : in std_logic;
LMB_UE_26 : in std_logic;
LMB_Byte_Enable_26 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_27 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_27 : out std_logic;
LMB_Read_Strobe_27 : out std_logic;
LMB_Write_Strobe_27 : out std_logic;
LMB_Ready_27 : in std_logic;
LMB_Wait_27 : in std_logic;
LMB_CE_27 : in std_logic;
LMB_UE_27 : in std_logic;
LMB_Byte_Enable_27 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_28 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_28 : out std_logic;
LMB_Read_Strobe_28 : out std_logic;
LMB_Write_Strobe_28 : out std_logic;
LMB_Ready_28 : in std_logic;
LMB_Wait_28 : in std_logic;
LMB_CE_28 : in std_logic;
LMB_UE_28 : in std_logic;
LMB_Byte_Enable_28 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_29 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_29 : out std_logic;
LMB_Read_Strobe_29 : out std_logic;
LMB_Write_Strobe_29 : out std_logic;
LMB_Ready_29 : in std_logic;
LMB_Wait_29 : in std_logic;
LMB_CE_29 : in std_logic;
LMB_UE_29 : in std_logic;
LMB_Byte_Enable_29 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_30 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_30 : out std_logic;
LMB_Read_Strobe_30 : out std_logic;
LMB_Write_Strobe_30 : out std_logic;
LMB_Ready_30 : in std_logic;
LMB_Wait_30 : in std_logic;
LMB_CE_30 : in std_logic;
LMB_UE_30 : in std_logic;
LMB_Byte_Enable_30 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_31 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_31 : out std_logic;
LMB_Read_Strobe_31 : out std_logic;
LMB_Write_Strobe_31 : out std_logic;
LMB_Ready_31 : in std_logic;
LMB_Wait_31 : in std_logic;
LMB_CE_31 : in std_logic;
LMB_UE_31 : in std_logic;
LMB_Byte_Enable_31 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External BSCAN inputs
-- These signals are used when C_USE_BSCAN = 2 (EXTERNAL)
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
-- External JTAG ports
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM;
architecture IMP of MDM is
function int2std (val : integer) return std_logic is
begin -- function int2std
if (val = 0) then
return '0';
else
return '1';
end if;
end function int2std;
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0) := X"00000000";
constant C_REG_NUM_CE : integer := 4 + 4 * C_DBG_REG_ACCESS;
constant C_REG_DATA_WIDTH : integer := 8 + 24 * C_DBG_REG_ACCESS;
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) :=
(31 downto 5 => '0', 4 => int2std(C_DBG_REG_ACCESS), 3 downto 0 => '1');
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := (
-- Registers Base Address (not used)
ZEROES & C_BASEADDR,
ZEROES & (C_BASEADDR or C_S_AXI_MIN_SIZE)
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (
0 => C_REG_NUM_CE
);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
constant C_TRACE_AXI_MASTER : boolean := C_TRACE_OUTPUT = 3;
--------------------------------------------------------------------------
-- Component declarations
--------------------------------------------------------------------------
component MDM_Core
generic (
C_JTAG_CHAIN : integer;
C_USE_BSCAN : integer;
C_USE_CONFIG_RESET : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8;
C_TRACE_OUTPUT : integer;
C_TRACE_DATA_WIDTH : integer;
C_TRACE_CLK_FREQ_HZ : integer;
C_TRACE_CLK_OUT_PHASE : integer;
C_M_AXIS_DATA_WIDTH : integer;
C_M_AXIS_ID_WIDTH : integer);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
-- AXI IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_data : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_dwr_start : out std_logic;
Master_dwr_next : in std_logic;
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External Trigger Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component MDM_Core;
component bus_master is
generic (
C_M_AXI_DATA_WIDTH : natural;
C_M_AXI_THREAD_ID_WIDTH : natural;
C_M_AXI_ADDR_WIDTH : natural;
C_DATA_SIZE : natural;
C_HAS_FIFO_PORTS : boolean;
C_HAS_DIRECT_PORT : boolean
);
port (
Rd_Start : in std_logic;
Rd_Addr : in std_logic_vector(31 downto 0);
Rd_Len : in std_logic_vector(4 downto 0);
Rd_Size : in std_logic_vector(1 downto 0);
Rd_Exclusive : in std_logic;
Rd_Idle : out std_logic;
Rd_Response : out std_logic_vector(1 downto 0);
Wr_Start : in std_logic;
Wr_Addr : in std_logic_vector(31 downto 0);
Wr_Len : in std_logic_vector(4 downto 0);
Wr_Size : in std_logic_vector(1 downto 0);
Wr_Exclusive : in std_logic;
Wr_Idle : out std_logic;
Wr_Response : out std_logic_vector(1 downto 0);
Data_Rd : in std_logic;
Data_Out : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Exists : out std_logic;
Data_Wr : in std_logic;
Data_In : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Empty : out std_logic;
Direct_Wr_Addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Direct_Wr_Len : in std_logic_vector(4 downto 0);
Direct_Wr_Data : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Direct_Wr_Start : in std_logic;
Direct_Wr_Next : out std_logic;
Direct_Wr_Done : out std_logic;
Direct_Wr_Resp : out std_logic_vector(1 downto 0);
LMB_Data_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe : out std_logic;
LMB_Read_Strobe : out std_logic;
LMB_Write_Strobe : out std_logic;
LMB_Ready : in std_logic;
LMB_Wait : in std_logic;
LMB_UE : in std_logic;
LMB_Byte_Enable : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WLAST : out std_logic;
M_AXI_WDATA : out std_logic_vector(31 downto 0);
M_AXI_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end component bus_master;
--------------------------------------------------------------------------
-- Functions
--------------------------------------------------------------------------
-- Returns at least 1
function MakePos (a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
constant C_EN_WIDTH : integer := MakePos(C_MB_DBG_PORTS);
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal tdi : std_logic;
signal reset : std_logic;
signal update : std_logic;
signal capture : std_logic;
signal shift : std_logic;
signal sel : std_logic;
signal drck : std_logic;
signal tdo : std_logic;
signal drck_i : std_logic;
signal update_i : std_logic;
signal dbgreg_drck : std_logic;
signal dbgreg_update : std_logic;
signal dbgreg_select : std_logic;
signal jtag_busy : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
signal bus2ip_cs : std_logic_vector(((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal mb_debug_enabled : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal master_rd_start : std_logic;
signal master_rd_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_rd_len : std_logic_vector(4 downto 0);
signal master_rd_size : std_logic_vector(1 downto 0);
signal master_rd_excl : std_logic;
signal master_rd_idle : std_logic;
signal master_rd_resp : std_logic_vector(1 downto 0);
signal master_wr_start : std_logic;
signal master_wr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_wr_len : std_logic_vector(4 downto 0);
signal master_wr_size : std_logic_vector(1 downto 0);
signal master_wr_excl : std_logic;
signal master_wr_idle : std_logic;
signal master_wr_resp : std_logic_vector(1 downto 0);
signal master_data_rd : std_logic;
signal master_data_out : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_exists : std_logic;
signal master_data_wr : std_logic;
signal master_data_in : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_empty : std_logic;
signal master_dwr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_dwr_len : std_logic_vector(4 downto 0);
signal master_dwr_data : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_dwr_start : std_logic;
signal master_dwr_next : std_logic;
signal master_dwr_done : std_logic;
signal master_dwr_resp : std_logic_vector(1 downto 0);
signal ext_trig_in : std_logic_vector(0 to 3);
signal ext_trig_Ack_In : std_logic_vector(0 to 3);
signal ext_trig_out : std_logic_vector(0 to 3);
signal ext_trig_Ack_Out : std_logic_vector(0 to 3);
--------------------------------------------------------------------------
-- Attibute declarations
--------------------------------------------------------------------------
attribute period : string;
attribute period of update : signal is "200 ns";
attribute buffer_type : string;
attribute buffer_type of update_i : signal is "none";
attribute buffer_type of MDM_Core_I1 : label is "none";
begin -- architecture IMP
Use_E2 : if C_USE_BSCAN /= 2 generate
begin
BSCANE2_I : BSCANE2
generic map (
DISABLE_JTAG => "FALSE",
JTAG_CHAIN => C_JTAG_CHAIN)
port map (
CAPTURE => capture, -- [out std_logic]
DRCK => drck_i, -- [out std_logic]
RESET => reset, -- [out std_logic]
RUNTEST => open, -- [out std_logic]
SEL => sel, -- [out std_logic]
SHIFT => shift, -- [out std_logic]
TCK => open, -- [out std_logic]
TDI => tdi, -- [out std_logic]
TMS => open, -- [out std_logic]
UPDATE => update_i, -- [out std_logic]
TDO => tdo); -- [in std_logic]
end generate Use_E2;
Use_External : if C_USE_BSCAN = 2 generate
begin
capture <= bscan_ext_capture;
drck_i <= bscan_ext_drck;
reset <= bscan_ext_reset;
sel <= bscan_ext_sel;
shift <= bscan_ext_shift;
tdi <= bscan_ext_tdi;
update_i <= bscan_ext_update;
bscan_ext_tdo <= tdo;
end generate Use_External;
No_External : if C_USE_BSCAN /= 2 generate
begin
bscan_ext_tdo <= '0';
end generate No_External;
Use_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 1 generate
signal dbgreg_select_n : std_logic;
signal dbgreg_drck_i : std_logic;
signal dbgreg_update_i : std_logic;
signal update_set : std_logic;
signal update_reset : std_logic;
begin
dbgreg_select_n <= not dbgreg_select;
-- drck <= dbgreg_drck when dbgreg_select = '1' else drck_i;
BUFG_DRCK : BUFG
port map (
O => dbgreg_drck_i,
I => dbgreg_drck
);
BUFGCTRL_DRCK : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => drck,
CE0 => '1',
CE1 => '1',
I0 => drck_i,
I1 => dbgreg_drck_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
-- update <= dbgreg_update when dbgreg_select = '1' else update_i;
BUFG_UPDATE : BUFG
port map (
O => dbgreg_update_i,
I => dbgreg_update
);
BUFGCTRL_UPDATE : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => update,
CE0 => '1',
CE1 => '1',
I0 => update_i,
I1 => dbgreg_update_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
JTAG_Busy_Detect : process (drck_i, sel, update_set, Config_Reset)
begin
if sel = '0' or update_set = '1' or Config_Reset = '1' then
jtag_busy <= '0';
update_reset <= '1';
elsif drck_i'event and drck_i = '1' then
if sel = '1' and capture = '1' then
jtag_busy <= '1';
end if;
update_reset <= '0';
end if;
end process JTAG_Busy_Detect;
JTAG_Update_Detect : process (update_i, update_reset, Config_Reset)
begin
if update_reset = '1' or Config_Reset = '1' then
update_set <= '0';
elsif update_i'event and update_i = '1' then
update_set <= '1';
end if;
end process JTAG_Update_Detect;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 0 generate
begin
BUFG_DRCK : BUFG
port map (
O => drck,
I => drck_i
);
update <= update_i;
jtag_busy <= '0';
end generate No_Dbg_Reg_Access;
---------------------------------------------------------------------------
-- MDM core
---------------------------------------------------------------------------
MDM_Core_I1 : MDM_Core
generic map (
C_JTAG_CHAIN => C_JTAG_CHAIN, -- [integer]
C_USE_BSCAN => C_USE_BSCAN, -- [integer]
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET, -- [integer = 0]
C_BASEADDR => C_BASEADDR, -- [std_logic_vector(0 to 31)]
C_HIGHADDR => C_HIGHADDR, -- [std_logic_vector(0 to 31)]
C_MB_DBG_PORTS => C_MB_DBG_PORTS, -- [integer]
C_EN_WIDTH => C_EN_WIDTH, -- [integer]
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS, -- [integer]
C_REG_NUM_CE => C_REG_NUM_CE, -- [integer]
C_REG_DATA_WIDTH => C_REG_DATA_WIDTH, -- [integer]
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS, -- [integer]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ, -- [integer]
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH, -- [integer]
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH, -- [integer]
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER, -- [integer]
C_USE_UART => C_USE_UART, -- [integer]
C_UART_WIDTH => 8, -- [integer]
C_TRACE_OUTPUT => C_TRACE_OUTPUT, -- [integer]
C_TRACE_DATA_WIDTH => C_TRACE_DATA_WIDTH, -- [integer]
C_TRACE_CLK_FREQ_HZ => C_TRACE_CLK_FREQ_HZ, -- [integer]
C_TRACE_CLK_OUT_PHASE => C_TRACE_CLK_OUT_PHASE, -- [integer]
C_M_AXIS_DATA_WIDTH => C_M_AXIS_DATA_WIDTH, -- [integer]
C_M_AXIS_ID_WIDTH => C_M_AXIS_ID_WIDTH -- [integer]
)
port map (
-- Global signals
Config_Reset => Config_Reset, -- [in std_logic]
Scan_Reset_Sel => Scan_Reset_Sel, -- [in std_logic]
Scan_Reset => Scan_Reset, -- [in std_logic]
M_AXIS_ACLK => M_AXIS_ACLK, -- [in std_logic]
M_AXIS_ARESETN => M_AXIS_ARESETN, -- [in std_logic]
Interrupt => Interrupt, -- [out std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst, -- [out std_logic]
-- Debug Register Access signals
DbgReg_DRCK => dbgreg_drck, -- [out std_logic]
DbgReg_UPDATE => dbgreg_update, -- [out std_logic]
DbgReg_Select => dbgreg_select, -- [out std_logic]
JTAG_Busy => jtag_busy, -- [in std_logic]
-- AXI IPIC signals
bus2ip_clk => bus2ip_clk,
bus2ip_resetn => bus2ip_resetn,
bus2ip_data => bus2ip_data(C_REG_DATA_WIDTH-1 downto 0),
bus2ip_rdce => bus2ip_rdce(C_REG_NUM_CE-1 downto 0),
bus2ip_wrce => bus2ip_wrce(C_REG_NUM_CE-1 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
ip2bus_data => ip2bus_data(C_REG_DATA_WIDTH-1 downto 0),
-- Bus Master signals
MB_Debug_Enabled => mb_debug_enabled,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
Master_rd_start => master_rd_start,
Master_rd_addr => master_rd_addr,
Master_rd_len => master_rd_len,
Master_rd_size => master_rd_size,
Master_rd_excl => master_rd_excl,
Master_rd_idle => master_rd_idle,
Master_rd_resp => master_rd_resp,
Master_wr_start => master_wr_start,
Master_wr_addr => master_wr_addr,
Master_wr_len => master_wr_len,
Master_wr_size => master_wr_size,
Master_wr_excl => master_wr_excl,
Master_wr_idle => master_wr_idle,
Master_wr_resp => master_wr_resp,
Master_data_rd => master_data_rd,
Master_data_out => master_data_out,
Master_data_exists => master_data_exists,
Master_data_wr => master_data_wr,
Master_data_in => master_data_in,
Master_data_empty => master_data_empty,
Master_dwr_addr => master_dwr_addr,
Master_dwr_len => master_dwr_len,
Master_dwr_data => master_dwr_data,
Master_dwr_start => master_dwr_start,
Master_dwr_next => master_dwr_next,
Master_dwr_done => master_dwr_done,
Master_dwr_resp => master_dwr_resp,
-- JTAG signals
JTAG_TDI => tdi, -- [in std_logic]
JTAG_RESET => reset, -- [in std_logic]
UPDATE => update, -- [in std_logic]
JTAG_SHIFT => shift, -- [in std_logic]
JTAG_CAPTURE => capture, -- [in std_logic]
SEL => sel, -- [in std_logic]
DRCK => drck, -- [in std_logic]
JTAG_TDO => tdo, -- [out std_logic]
-- External Trace AXI Stream output
M_AXIS_TDATA => M_AXIS_TDATA, -- [out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0)]
M_AXIS_TID => M_AXIS_TID, -- [out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0)]
M_AXIS_TREADY => M_AXIS_TREADY, -- [in std_logic]
M_AXIS_TVALID => M_AXIS_TVALID, -- [out std_logic]
-- External Trace output
TRACE_CLK_OUT => TRACE_CLK_OUT, -- [out std_logic]
TRACE_CLK => TRACE_CLK, -- [in std_logic]
TRACE_CTL => TRACE_CTL, -- [out std_logic]
TRACE_DATA => TRACE_DATA, -- [out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0)]
-- MicroBlaze Debug Signals
Dbg_Clk_0 => Dbg_Clk_0, -- [out std_logic]
Dbg_TDI_0 => Dbg_TDI_0, -- [out std_logic]
Dbg_TDO_0 => Dbg_TDO_0, -- [in std_logic]
Dbg_Reg_En_0 => Dbg_Reg_En_0, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_0 => Dbg_Capture_0, -- [out std_logic]
Dbg_Shift_0 => Dbg_Shift_0, -- [out std_logic]
Dbg_Update_0 => Dbg_Update_0, -- [out std_logic]
Dbg_Rst_0 => Dbg_Rst_0, -- [out std_logic]
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_0 => Dbg_TrClk_0, -- [out std_logic]
Dbg_TrData_0 => Dbg_TrData_0, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_0 => Dbg_TrReady_0, -- [out std_logic]
Dbg_TrValid_0 => Dbg_TrValid_0, -- [in std_logic]
Dbg_Clk_1 => Dbg_Clk_1, -- [out std_logic]
Dbg_TDI_1 => Dbg_TDI_1, -- [out std_logic]
Dbg_TDO_1 => Dbg_TDO_1, -- [in std_logic]
Dbg_Reg_En_1 => Dbg_Reg_En_1, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_1 => Dbg_Capture_1, -- [out std_logic]
Dbg_Shift_1 => Dbg_Shift_1, -- [out std_logic]
Dbg_Update_1 => Dbg_Update_1, -- [out std_logic]
Dbg_Rst_1 => Dbg_Rst_1, -- [out std_logic]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_1 => Dbg_TrClk_1, -- [out std_logic]
Dbg_TrData_1 => Dbg_TrData_1, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_1 => Dbg_TrReady_1, -- [out std_logic]
Dbg_TrValid_1 => Dbg_TrValid_1, -- [in std_logic]
Dbg_Clk_2 => Dbg_Clk_2, -- [out std_logic]
Dbg_TDI_2 => Dbg_TDI_2, -- [out std_logic]
Dbg_TDO_2 => Dbg_TDO_2, -- [in std_logic]
Dbg_Reg_En_2 => Dbg_Reg_En_2, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_2 => Dbg_Capture_2, -- [out std_logic]
Dbg_Shift_2 => Dbg_Shift_2, -- [out std_logic]
Dbg_Update_2 => Dbg_Update_2, -- [out std_logic]
Dbg_Rst_2 => Dbg_Rst_2, -- [out std_logic]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_2 => Dbg_TrClk_2, -- [out std_logic]
Dbg_TrData_2 => Dbg_TrData_2, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_2 => Dbg_TrReady_2, -- [out std_logic]
Dbg_TrValid_2 => Dbg_TrValid_2, -- [in std_logic]
Dbg_Clk_3 => Dbg_Clk_3, -- [out std_logic]
Dbg_TDI_3 => Dbg_TDI_3, -- [out std_logic]
Dbg_TDO_3 => Dbg_TDO_3, -- [in std_logic]
Dbg_Reg_En_3 => Dbg_Reg_En_3, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_3 => Dbg_Capture_3, -- [out std_logic]
Dbg_Shift_3 => Dbg_Shift_3, -- [out std_logic]
Dbg_Update_3 => Dbg_Update_3, -- [out std_logic]
Dbg_Rst_3 => Dbg_Rst_3, -- [out std_logic]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_3 => Dbg_TrClk_3, -- [out std_logic]
Dbg_TrData_3 => Dbg_TrData_3, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_3 => Dbg_TrReady_3, -- [out std_logic]
Dbg_TrValid_3 => Dbg_TrValid_3, -- [in std_logic]
Dbg_Clk_4 => Dbg_Clk_4, -- [out std_logic]
Dbg_TDI_4 => Dbg_TDI_4, -- [out std_logic]
Dbg_TDO_4 => Dbg_TDO_4, -- [in std_logic]
Dbg_Reg_En_4 => Dbg_Reg_En_4, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_4 => Dbg_Capture_4, -- [out std_logic]
Dbg_Shift_4 => Dbg_Shift_4, -- [out std_logic]
Dbg_Update_4 => Dbg_Update_4, -- [out std_logic]
Dbg_Rst_4 => Dbg_Rst_4, -- [out std_logic]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_4 => Dbg_TrClk_4, -- [out std_logic]
Dbg_TrData_4 => Dbg_TrData_4, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_4 => Dbg_TrReady_4, -- [out std_logic]
Dbg_TrValid_4 => Dbg_TrValid_4, -- [in std_logic]
Dbg_Clk_5 => Dbg_Clk_5, -- [out std_logic]
Dbg_TDI_5 => Dbg_TDI_5, -- [out std_logic]
Dbg_TDO_5 => Dbg_TDO_5, -- [in std_logic]
Dbg_Reg_En_5 => Dbg_Reg_En_5, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_5 => Dbg_Capture_5, -- [out std_logic]
Dbg_Shift_5 => Dbg_Shift_5, -- [out std_logic]
Dbg_Update_5 => Dbg_Update_5, -- [out std_logic]
Dbg_Rst_5 => Dbg_Rst_5, -- [out std_logic]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_5 => Dbg_TrClk_5, -- [out std_logic]
Dbg_TrData_5 => Dbg_TrData_5, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_5 => Dbg_TrReady_5, -- [out std_logic]
Dbg_TrValid_5 => Dbg_TrValid_5, -- [in std_logic]
Dbg_Clk_6 => Dbg_Clk_6, -- [out std_logic]
Dbg_TDI_6 => Dbg_TDI_6, -- [out std_logic]
Dbg_TDO_6 => Dbg_TDO_6, -- [in std_logic]
Dbg_Reg_En_6 => Dbg_Reg_En_6, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_6 => Dbg_Capture_6, -- [out std_logic]
Dbg_Shift_6 => Dbg_Shift_6, -- [out std_logic]
Dbg_Update_6 => Dbg_Update_6, -- [out std_logic]
Dbg_Rst_6 => Dbg_Rst_6, -- [out std_logic]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_6 => Dbg_TrClk_6, -- [out std_logic]
Dbg_TrData_6 => Dbg_TrData_6, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_6 => Dbg_TrReady_6, -- [out std_logic]
Dbg_TrValid_6 => Dbg_TrValid_6, -- [in std_logic]
Dbg_Clk_7 => Dbg_Clk_7, -- [out std_logic]
Dbg_TDI_7 => Dbg_TDI_7, -- [out std_logic]
Dbg_TDO_7 => Dbg_TDO_7, -- [in std_logic]
Dbg_Reg_En_7 => Dbg_Reg_En_7, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_7 => Dbg_Capture_7, -- [out std_logic]
Dbg_Shift_7 => Dbg_Shift_7, -- [out std_logic]
Dbg_Update_7 => Dbg_Update_7, -- [out std_logic]
Dbg_Rst_7 => Dbg_Rst_7, -- [out std_logic]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_7 => Dbg_TrClk_7, -- [out std_logic]
Dbg_TrData_7 => Dbg_TrData_7, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_7 => Dbg_TrReady_7, -- [out std_logic]
Dbg_TrValid_7 => Dbg_TrValid_7, -- [in std_logic]
Dbg_Clk_8 => Dbg_Clk_8, -- [out std_logic]
Dbg_TDI_8 => Dbg_TDI_8, -- [out std_logic]
Dbg_TDO_8 => Dbg_TDO_8, -- [in std_logic]
Dbg_Reg_En_8 => Dbg_Reg_En_8, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_8 => Dbg_Capture_8, -- [out std_logic]
Dbg_Shift_8 => Dbg_Shift_8, -- [out std_logic]
Dbg_Update_8 => Dbg_Update_8, -- [out std_logic]
Dbg_Rst_8 => Dbg_Rst_8, -- [out std_logic]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_8 => Dbg_TrClk_8, -- [out std_logic]
Dbg_TrData_8 => Dbg_TrData_8, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_8 => Dbg_TrReady_8, -- [out std_logic]
Dbg_TrValid_8 => Dbg_TrValid_8, -- [in std_logic]
Dbg_Clk_9 => Dbg_Clk_9, -- [out std_logic]
Dbg_TDI_9 => Dbg_TDI_9, -- [out std_logic]
Dbg_TDO_9 => Dbg_TDO_9, -- [in std_logic]
Dbg_Reg_En_9 => Dbg_Reg_En_9, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_9 => Dbg_Capture_9, -- [out std_logic]
Dbg_Shift_9 => Dbg_Shift_9, -- [out std_logic]
Dbg_Update_9 => Dbg_Update_9, -- [out std_logic]
Dbg_Rst_9 => Dbg_Rst_9, -- [out std_logic]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_9 => Dbg_TrClk_9, -- [out std_logic]
Dbg_TrData_9 => Dbg_TrData_9, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_9 => Dbg_TrReady_9, -- [out std_logic]
Dbg_TrValid_9 => Dbg_TrValid_9, -- [in std_logic]
Dbg_Clk_10 => Dbg_Clk_10, -- [out std_logic]
Dbg_TDI_10 => Dbg_TDI_10, -- [out std_logic]
Dbg_TDO_10 => Dbg_TDO_10, -- [in std_logic]
Dbg_Reg_En_10 => Dbg_Reg_En_10, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_10 => Dbg_Capture_10, -- [out std_logic]
Dbg_Shift_10 => Dbg_Shift_10, -- [out std_logic]
Dbg_Update_10 => Dbg_Update_10, -- [out std_logic]
Dbg_Rst_10 => Dbg_Rst_10, -- [out std_logic]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_10 => Dbg_TrClk_10, -- [out std_logic]
Dbg_TrData_10 => Dbg_TrData_10, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_10 => Dbg_TrReady_10, -- [out std_logic]
Dbg_TrValid_10 => Dbg_TrValid_10, -- [in std_logic]
Dbg_Clk_11 => Dbg_Clk_11, -- [out std_logic]
Dbg_TDI_11 => Dbg_TDI_11, -- [out std_logic]
Dbg_TDO_11 => Dbg_TDO_11, -- [in std_logic]
Dbg_Reg_En_11 => Dbg_Reg_En_11, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_11 => Dbg_Capture_11, -- [out std_logic]
Dbg_Shift_11 => Dbg_Shift_11, -- [out std_logic]
Dbg_Update_11 => Dbg_Update_11, -- [out std_logic]
Dbg_Rst_11 => Dbg_Rst_11, -- [out std_logic]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_11 => Dbg_TrClk_11, -- [out std_logic]
Dbg_TrData_11 => Dbg_TrData_11, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_11 => Dbg_TrReady_11, -- [out std_logic]
Dbg_TrValid_11 => Dbg_TrValid_11, -- [in std_logic]
Dbg_Clk_12 => Dbg_Clk_12, -- [out std_logic]
Dbg_TDI_12 => Dbg_TDI_12, -- [out std_logic]
Dbg_TDO_12 => Dbg_TDO_12, -- [in std_logic]
Dbg_Reg_En_12 => Dbg_Reg_En_12, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_12 => Dbg_Capture_12, -- [out std_logic]
Dbg_Shift_12 => Dbg_Shift_12, -- [out std_logic]
Dbg_Update_12 => Dbg_Update_12, -- [out std_logic]
Dbg_Rst_12 => Dbg_Rst_12, -- [out std_logic]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_12 => Dbg_TrClk_12, -- [out std_logic]
Dbg_TrData_12 => Dbg_TrData_12, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_12 => Dbg_TrReady_12, -- [out std_logic]
Dbg_TrValid_12 => Dbg_TrValid_12, -- [in std_logic]
Dbg_Clk_13 => Dbg_Clk_13, -- [out std_logic]
Dbg_TDI_13 => Dbg_TDI_13, -- [out std_logic]
Dbg_TDO_13 => Dbg_TDO_13, -- [in std_logic]
Dbg_Reg_En_13 => Dbg_Reg_En_13, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_13 => Dbg_Capture_13, -- [out std_logic]
Dbg_Shift_13 => Dbg_Shift_13, -- [out std_logic]
Dbg_Update_13 => Dbg_Update_13, -- [out std_logic]
Dbg_Rst_13 => Dbg_Rst_13, -- [out std_logic]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_13 => Dbg_TrClk_13, -- [out std_logic]
Dbg_TrData_13 => Dbg_TrData_13, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_13 => Dbg_TrReady_13, -- [out std_logic]
Dbg_TrValid_13 => Dbg_TrValid_13, -- [in std_logic]
Dbg_Clk_14 => Dbg_Clk_14, -- [out std_logic]
Dbg_TDI_14 => Dbg_TDI_14, -- [out std_logic]
Dbg_TDO_14 => Dbg_TDO_14, -- [in std_logic]
Dbg_Reg_En_14 => Dbg_Reg_En_14, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_14 => Dbg_Capture_14, -- [out std_logic]
Dbg_Shift_14 => Dbg_Shift_14, -- [out std_logic]
Dbg_Update_14 => Dbg_Update_14, -- [out std_logic]
Dbg_Rst_14 => Dbg_Rst_14, -- [out std_logic]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_14 => Dbg_TrClk_14, -- [out std_logic]
Dbg_TrData_14 => Dbg_TrData_14, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_14 => Dbg_TrReady_14, -- [out std_logic]
Dbg_TrValid_14 => Dbg_TrValid_14, -- [in std_logic]
Dbg_Clk_15 => Dbg_Clk_15, -- [out std_logic]
Dbg_TDI_15 => Dbg_TDI_15, -- [out std_logic]
Dbg_TDO_15 => Dbg_TDO_15, -- [in std_logic]
Dbg_Reg_En_15 => Dbg_Reg_En_15, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_15 => Dbg_Capture_15, -- [out std_logic]
Dbg_Shift_15 => Dbg_Shift_15, -- [out std_logic]
Dbg_Update_15 => Dbg_Update_15, -- [out std_logic]
Dbg_Rst_15 => Dbg_Rst_15, -- [out std_logic]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_15 => Dbg_TrClk_15, -- [out std_logic]
Dbg_TrData_15 => Dbg_TrData_15, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_15 => Dbg_TrReady_15, -- [out std_logic]
Dbg_TrValid_15 => Dbg_TrValid_15, -- [in std_logic]
Dbg_Clk_16 => Dbg_Clk_16, -- [out std_logic]
Dbg_TDI_16 => Dbg_TDI_16, -- [out std_logic]
Dbg_TDO_16 => Dbg_TDO_16, -- [in std_logic]
Dbg_Reg_En_16 => Dbg_Reg_En_16, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_16 => Dbg_Capture_16, -- [out std_logic]
Dbg_Shift_16 => Dbg_Shift_16, -- [out std_logic]
Dbg_Update_16 => Dbg_Update_16, -- [out std_logic]
Dbg_Rst_16 => Dbg_Rst_16, -- [out std_logic]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_16 => Dbg_TrClk_16, -- [out std_logic]
Dbg_TrData_16 => Dbg_TrData_16, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_16 => Dbg_TrReady_16, -- [out std_logic]
Dbg_TrValid_16 => Dbg_TrValid_16, -- [in std_logic]
Dbg_Clk_17 => Dbg_Clk_17, -- [out std_logic]
Dbg_TDI_17 => Dbg_TDI_17, -- [out std_logic]
Dbg_TDO_17 => Dbg_TDO_17, -- [in std_logic]
Dbg_Reg_En_17 => Dbg_Reg_En_17, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_17 => Dbg_Capture_17, -- [out std_logic]
Dbg_Shift_17 => Dbg_Shift_17, -- [out std_logic]
Dbg_Update_17 => Dbg_Update_17, -- [out std_logic]
Dbg_Rst_17 => Dbg_Rst_17, -- [out std_logic]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_17 => Dbg_TrClk_17, -- [out std_logic]
Dbg_TrData_17 => Dbg_TrData_17, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_17 => Dbg_TrReady_17, -- [out std_logic]
Dbg_TrValid_17 => Dbg_TrValid_17, -- [in std_logic]
Dbg_Clk_18 => Dbg_Clk_18, -- [out std_logic]
Dbg_TDI_18 => Dbg_TDI_18, -- [out std_logic]
Dbg_TDO_18 => Dbg_TDO_18, -- [in std_logic]
Dbg_Reg_En_18 => Dbg_Reg_En_18, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_18 => Dbg_Capture_18, -- [out std_logic]
Dbg_Shift_18 => Dbg_Shift_18, -- [out std_logic]
Dbg_Update_18 => Dbg_Update_18, -- [out std_logic]
Dbg_Rst_18 => Dbg_Rst_18, -- [out std_logic]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_18 => Dbg_TrClk_18, -- [out std_logic]
Dbg_TrData_18 => Dbg_TrData_18, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_18 => Dbg_TrReady_18, -- [out std_logic]
Dbg_TrValid_18 => Dbg_TrValid_18, -- [in std_logic]
Dbg_Clk_19 => Dbg_Clk_19, -- [out std_logic]
Dbg_TDI_19 => Dbg_TDI_19, -- [out std_logic]
Dbg_TDO_19 => Dbg_TDO_19, -- [in std_logic]
Dbg_Reg_En_19 => Dbg_Reg_En_19, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_19 => Dbg_Capture_19, -- [out std_logic]
Dbg_Shift_19 => Dbg_Shift_19, -- [out std_logic]
Dbg_Update_19 => Dbg_Update_19, -- [out std_logic]
Dbg_Rst_19 => Dbg_Rst_19, -- [out std_logic]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_19 => Dbg_TrClk_19, -- [out std_logic]
Dbg_TrData_19 => Dbg_TrData_19, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_19 => Dbg_TrReady_19, -- [out std_logic]
Dbg_TrValid_19 => Dbg_TrValid_19, -- [in std_logic]
Dbg_Clk_20 => Dbg_Clk_20, -- [out std_logic]
Dbg_TDI_20 => Dbg_TDI_20, -- [out std_logic]
Dbg_TDO_20 => Dbg_TDO_20, -- [in std_logic]
Dbg_Reg_En_20 => Dbg_Reg_En_20, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_20 => Dbg_Capture_20, -- [out std_logic]
Dbg_Shift_20 => Dbg_Shift_20, -- [out std_logic]
Dbg_Update_20 => Dbg_Update_20, -- [out std_logic]
Dbg_Rst_20 => Dbg_Rst_20, -- [out std_logic]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_20 => Dbg_TrClk_20, -- [out std_logic]
Dbg_TrData_20 => Dbg_TrData_20, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_20 => Dbg_TrReady_20, -- [out std_logic]
Dbg_TrValid_20 => Dbg_TrValid_20, -- [in std_logic]
Dbg_Clk_21 => Dbg_Clk_21, -- [out std_logic]
Dbg_TDI_21 => Dbg_TDI_21, -- [out std_logic]
Dbg_TDO_21 => Dbg_TDO_21, -- [in std_logic]
Dbg_Reg_En_21 => Dbg_Reg_En_21, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_21 => Dbg_Capture_21, -- [out std_logic]
Dbg_Shift_21 => Dbg_Shift_21, -- [out std_logic]
Dbg_Update_21 => Dbg_Update_21, -- [out std_logic]
Dbg_Rst_21 => Dbg_Rst_21, -- [out std_logic]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_21 => Dbg_TrClk_21, -- [out std_logic]
Dbg_TrData_21 => Dbg_TrData_21, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_21 => Dbg_TrReady_21, -- [out std_logic]
Dbg_TrValid_21 => Dbg_TrValid_21, -- [in std_logic]
Dbg_Clk_22 => Dbg_Clk_22, -- [out std_logic]
Dbg_TDI_22 => Dbg_TDI_22, -- [out std_logic]
Dbg_TDO_22 => Dbg_TDO_22, -- [in std_logic]
Dbg_Reg_En_22 => Dbg_Reg_En_22, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_22 => Dbg_Capture_22, -- [out std_logic]
Dbg_Shift_22 => Dbg_Shift_22, -- [out std_logic]
Dbg_Update_22 => Dbg_Update_22, -- [out std_logic]
Dbg_Rst_22 => Dbg_Rst_22, -- [out std_logic]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_22 => Dbg_TrClk_22, -- [out std_logic]
Dbg_TrData_22 => Dbg_TrData_22, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_22 => Dbg_TrReady_22, -- [out std_logic]
Dbg_TrValid_22 => Dbg_TrValid_22, -- [in std_logic]
Dbg_Clk_23 => Dbg_Clk_23, -- [out std_logic]
Dbg_TDI_23 => Dbg_TDI_23, -- [out std_logic]
Dbg_TDO_23 => Dbg_TDO_23, -- [in std_logic]
Dbg_Reg_En_23 => Dbg_Reg_En_23, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_23 => Dbg_Capture_23, -- [out std_logic]
Dbg_Shift_23 => Dbg_Shift_23, -- [out std_logic]
Dbg_Update_23 => Dbg_Update_23, -- [out std_logic]
Dbg_Rst_23 => Dbg_Rst_23, -- [out std_logic]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_23 => Dbg_TrClk_23, -- [out std_logic]
Dbg_TrData_23 => Dbg_TrData_23, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_23 => Dbg_TrReady_23, -- [out std_logic]
Dbg_TrValid_23 => Dbg_TrValid_23, -- [in std_logic]
Dbg_Clk_24 => Dbg_Clk_24, -- [out std_logic]
Dbg_TDI_24 => Dbg_TDI_24, -- [out std_logic]
Dbg_TDO_24 => Dbg_TDO_24, -- [in std_logic]
Dbg_Reg_En_24 => Dbg_Reg_En_24, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_24 => Dbg_Capture_24, -- [out std_logic]
Dbg_Shift_24 => Dbg_Shift_24, -- [out std_logic]
Dbg_Update_24 => Dbg_Update_24, -- [out std_logic]
Dbg_Rst_24 => Dbg_Rst_24, -- [out std_logic]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_24 => Dbg_TrClk_24, -- [out std_logic]
Dbg_TrData_24 => Dbg_TrData_24, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_24 => Dbg_TrReady_24, -- [out std_logic]
Dbg_TrValid_24 => Dbg_TrValid_24, -- [in std_logic]
Dbg_Clk_25 => Dbg_Clk_25, -- [out std_logic]
Dbg_TDI_25 => Dbg_TDI_25, -- [out std_logic]
Dbg_TDO_25 => Dbg_TDO_25, -- [in std_logic]
Dbg_Reg_En_25 => Dbg_Reg_En_25, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_25 => Dbg_Capture_25, -- [out std_logic]
Dbg_Shift_25 => Dbg_Shift_25, -- [out std_logic]
Dbg_Update_25 => Dbg_Update_25, -- [out std_logic]
Dbg_Rst_25 => Dbg_Rst_25, -- [out std_logic]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_25 => Dbg_TrClk_25, -- [out std_logic]
Dbg_TrData_25 => Dbg_TrData_25, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_25 => Dbg_TrReady_25, -- [out std_logic]
Dbg_TrValid_25 => Dbg_TrValid_25, -- [in std_logic]
Dbg_Clk_26 => Dbg_Clk_26, -- [out std_logic]
Dbg_TDI_26 => Dbg_TDI_26, -- [out std_logic]
Dbg_TDO_26 => Dbg_TDO_26, -- [in std_logic]
Dbg_Reg_En_26 => Dbg_Reg_En_26, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_26 => Dbg_Capture_26, -- [out std_logic]
Dbg_Shift_26 => Dbg_Shift_26, -- [out std_logic]
Dbg_Update_26 => Dbg_Update_26, -- [out std_logic]
Dbg_Rst_26 => Dbg_Rst_26, -- [out std_logic]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_26 => Dbg_TrClk_26, -- [out std_logic]
Dbg_TrData_26 => Dbg_TrData_26, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_26 => Dbg_TrReady_26, -- [out std_logic]
Dbg_TrValid_26 => Dbg_TrValid_26, -- [in std_logic]
Dbg_Clk_27 => Dbg_Clk_27, -- [out std_logic]
Dbg_TDI_27 => Dbg_TDI_27, -- [out std_logic]
Dbg_TDO_27 => Dbg_TDO_27, -- [in std_logic]
Dbg_Reg_En_27 => Dbg_Reg_En_27, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_27 => Dbg_Capture_27, -- [out std_logic]
Dbg_Shift_27 => Dbg_Shift_27, -- [out std_logic]
Dbg_Update_27 => Dbg_Update_27, -- [out std_logic]
Dbg_Rst_27 => Dbg_Rst_27, -- [out std_logic]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_27 => Dbg_TrClk_27, -- [out std_logic]
Dbg_TrData_27 => Dbg_TrData_27, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_27 => Dbg_TrReady_27, -- [out std_logic]
Dbg_TrValid_27 => Dbg_TrValid_27, -- [in std_logic]
Dbg_Clk_28 => Dbg_Clk_28, -- [out std_logic]
Dbg_TDI_28 => Dbg_TDI_28, -- [out std_logic]
Dbg_TDO_28 => Dbg_TDO_28, -- [in std_logic]
Dbg_Reg_En_28 => Dbg_Reg_En_28, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_28 => Dbg_Capture_28, -- [out std_logic]
Dbg_Shift_28 => Dbg_Shift_28, -- [out std_logic]
Dbg_Update_28 => Dbg_Update_28, -- [out std_logic]
Dbg_Rst_28 => Dbg_Rst_28, -- [out std_logic]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_28 => Dbg_TrClk_28, -- [out std_logic]
Dbg_TrData_28 => Dbg_TrData_28, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_28 => Dbg_TrReady_28, -- [out std_logic]
Dbg_TrValid_28 => Dbg_TrValid_28, -- [in std_logic]
Dbg_Clk_29 => Dbg_Clk_29, -- [out std_logic]
Dbg_TDI_29 => Dbg_TDI_29, -- [out std_logic]
Dbg_TDO_29 => Dbg_TDO_29, -- [in std_logic]
Dbg_Reg_En_29 => Dbg_Reg_En_29, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_29 => Dbg_Capture_29, -- [out std_logic]
Dbg_Shift_29 => Dbg_Shift_29, -- [out std_logic]
Dbg_Update_29 => Dbg_Update_29, -- [out std_logic]
Dbg_Rst_29 => Dbg_Rst_29, -- [out std_logic]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_29 => Dbg_TrClk_29, -- [out std_logic]
Dbg_TrData_29 => Dbg_TrData_29, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_29 => Dbg_TrReady_29, -- [out std_logic]
Dbg_TrValid_29 => Dbg_TrValid_29, -- [in std_logic]
Dbg_Clk_30 => Dbg_Clk_30, -- [out std_logic]
Dbg_TDI_30 => Dbg_TDI_30, -- [out std_logic]
Dbg_TDO_30 => Dbg_TDO_30, -- [in std_logic]
Dbg_Reg_En_30 => Dbg_Reg_En_30, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_30 => Dbg_Capture_30, -- [out std_logic]
Dbg_Shift_30 => Dbg_Shift_30, -- [out std_logic]
Dbg_Update_30 => Dbg_Update_30, -- [out std_logic]
Dbg_Rst_30 => Dbg_Rst_30, -- [out std_logic]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_30 => Dbg_TrClk_30, -- [out std_logic]
Dbg_TrData_30 => Dbg_TrData_30, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_30 => Dbg_TrReady_30, -- [out std_logic]
Dbg_TrValid_30 => Dbg_TrValid_30, -- [in std_logic]
Dbg_Clk_31 => Dbg_Clk_31, -- [out std_logic]
Dbg_TDI_31 => Dbg_TDI_31, -- [out std_logic]
Dbg_TDO_31 => Dbg_TDO_31, -- [in std_logic]
Dbg_Reg_En_31 => Dbg_Reg_En_31, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_31 => Dbg_Capture_31, -- [out std_logic]
Dbg_Shift_31 => Dbg_Shift_31, -- [out std_logic]
Dbg_Update_31 => Dbg_Update_31, -- [out std_logic]
Dbg_Rst_31 => Dbg_Rst_31, -- [out std_logic]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_31 => Dbg_TrClk_31, -- [out std_logic]
Dbg_TrData_31 => Dbg_TrData_31, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_31 => Dbg_TrReady_31, -- [out std_logic]
Dbg_TrValid_31 => Dbg_TrValid_31, -- [in std_logic]
Ext_Trig_In => ext_trig_in, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => ext_trig_ack_in, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => ext_trig_out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => ext_trig_ack_out, -- [in std_logic_vector(0 to 3)]
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
ext_trig_in <= Trig_In_0 & Trig_In_1 & Trig_In_2 & Trig_In_3;
ext_trig_ack_out <= Trig_Ack_Out_0 & Trig_Ack_Out_1 & Trig_Ack_Out_2 & Trig_Ack_Out_3;
Trig_Ack_In_0 <= ext_trig_ack_in(0);
Trig_Ack_In_1 <= ext_trig_ack_in(1);
Trig_Ack_In_2 <= ext_trig_ack_in(2);
Trig_Ack_In_3 <= ext_trig_ack_in(3);
Trig_Out_0 <= ext_trig_out(0);
Trig_Out_1 <= ext_trig_out(1);
Trig_Out_2 <= ext_trig_out(2);
Trig_Out_3 <= ext_trig_out(3);
-- Bus Master port
Use_Bus_MASTER : if (C_DBG_MEM_ACCESS = 1) generate
type LMB_vec_type is array (natural range <>) of std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_addr : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_write : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_addr_strobe : std_logic;
signal lmb_read_strobe : std_logic;
signal lmb_write_strobe : std_logic;
signal lmb_ready : std_logic;
signal lmb_wait : std_logic;
signal lmb_ue : std_logic;
signal lmb_byte_enable : std_logic_vector(0 to C_DATA_SIZE / 8 - 1);
signal lmb_addr_strobe_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec : LMB_vec_type(0 to 31);
signal lmb_ready_vec : std_logic_vector(0 to 31);
signal lmb_wait_vec : std_logic_vector(0 to 31);
signal lmb_ue_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec_q : LMB_vec_type(0 to C_EN_WIDTH - 1);
signal lmb_ready_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_wait_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_ue_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => true,
C_HAS_DIRECT_PORT => C_TRACE_AXI_MASTER
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => lmb_data_addr,
LMB_Data_Read => lmb_data_read,
LMB_Data_Write => lmb_data_write,
LMB_Addr_Strobe => lmb_addr_strobe,
LMB_Read_Strobe => lmb_read_strobe,
LMB_Write_Strobe => lmb_write_strobe,
LMB_Ready => lmb_ready,
LMB_Wait => lmb_wait,
LMB_UE => lmb_ue,
LMB_Byte_Enable => lmb_byte_enable,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
Generate_LMB_Outputs : process (mb_debug_enabled, lmb_addr_strobe)
begin -- process Generate_LMB_Outputs
lmb_addr_strobe_vec <= (others => '0');
for I in 0 to C_EN_WIDTH - 1 loop
lmb_addr_strobe_vec(I) <= lmb_addr_strobe and mb_debug_enabled(I);
end loop;
end process Generate_LMB_Outputs;
LMB_Addr_Strobe_0 <= lmb_addr_strobe_vec(0);
LMB_Addr_Strobe_1 <= lmb_addr_strobe_vec(1);
LMB_Addr_Strobe_2 <= lmb_addr_strobe_vec(2);
LMB_Addr_Strobe_3 <= lmb_addr_strobe_vec(3);
LMB_Addr_Strobe_4 <= lmb_addr_strobe_vec(4);
LMB_Addr_Strobe_5 <= lmb_addr_strobe_vec(5);
LMB_Addr_Strobe_6 <= lmb_addr_strobe_vec(6);
LMB_Addr_Strobe_7 <= lmb_addr_strobe_vec(7);
LMB_Addr_Strobe_8 <= lmb_addr_strobe_vec(8);
LMB_Addr_Strobe_9 <= lmb_addr_strobe_vec(9);
LMB_Addr_Strobe_10 <= lmb_addr_strobe_vec(10);
LMB_Addr_Strobe_11 <= lmb_addr_strobe_vec(11);
LMB_Addr_Strobe_12 <= lmb_addr_strobe_vec(12);
LMB_Addr_Strobe_13 <= lmb_addr_strobe_vec(13);
LMB_Addr_Strobe_14 <= lmb_addr_strobe_vec(14);
LMB_Addr_Strobe_15 <= lmb_addr_strobe_vec(15);
LMB_Addr_Strobe_16 <= lmb_addr_strobe_vec(16);
LMB_Addr_Strobe_17 <= lmb_addr_strobe_vec(17);
LMB_Addr_Strobe_18 <= lmb_addr_strobe_vec(18);
LMB_Addr_Strobe_19 <= lmb_addr_strobe_vec(19);
LMB_Addr_Strobe_20 <= lmb_addr_strobe_vec(20);
LMB_Addr_Strobe_21 <= lmb_addr_strobe_vec(21);
LMB_Addr_Strobe_22 <= lmb_addr_strobe_vec(22);
LMB_Addr_Strobe_23 <= lmb_addr_strobe_vec(23);
LMB_Addr_Strobe_24 <= lmb_addr_strobe_vec(24);
LMB_Addr_Strobe_25 <= lmb_addr_strobe_vec(25);
LMB_Addr_Strobe_26 <= lmb_addr_strobe_vec(26);
LMB_Addr_Strobe_27 <= lmb_addr_strobe_vec(27);
LMB_Addr_Strobe_28 <= lmb_addr_strobe_vec(28);
LMB_Addr_Strobe_29 <= lmb_addr_strobe_vec(29);
LMB_Addr_Strobe_30 <= lmb_addr_strobe_vec(30);
LMB_Addr_Strobe_31 <= lmb_addr_strobe_vec(31);
LMB_Data_Addr_0 <= lmb_data_addr;
LMB_Data_Addr_1 <= lmb_data_addr;
LMB_Data_Addr_2 <= lmb_data_addr;
LMB_Data_Addr_3 <= lmb_data_addr;
LMB_Data_Addr_4 <= lmb_data_addr;
LMB_Data_Addr_5 <= lmb_data_addr;
LMB_Data_Addr_6 <= lmb_data_addr;
LMB_Data_Addr_7 <= lmb_data_addr;
LMB_Data_Addr_8 <= lmb_data_addr;
LMB_Data_Addr_9 <= lmb_data_addr;
LMB_Data_Addr_10 <= lmb_data_addr;
LMB_Data_Addr_11 <= lmb_data_addr;
LMB_Data_Addr_12 <= lmb_data_addr;
LMB_Data_Addr_13 <= lmb_data_addr;
LMB_Data_Addr_14 <= lmb_data_addr;
LMB_Data_Addr_15 <= lmb_data_addr;
LMB_Data_Addr_16 <= lmb_data_addr;
LMB_Data_Addr_17 <= lmb_data_addr;
LMB_Data_Addr_18 <= lmb_data_addr;
LMB_Data_Addr_19 <= lmb_data_addr;
LMB_Data_Addr_20 <= lmb_data_addr;
LMB_Data_Addr_21 <= lmb_data_addr;
LMB_Data_Addr_22 <= lmb_data_addr;
LMB_Data_Addr_23 <= lmb_data_addr;
LMB_Data_Addr_24 <= lmb_data_addr;
LMB_Data_Addr_25 <= lmb_data_addr;
LMB_Data_Addr_26 <= lmb_data_addr;
LMB_Data_Addr_27 <= lmb_data_addr;
LMB_Data_Addr_28 <= lmb_data_addr;
LMB_Data_Addr_29 <= lmb_data_addr;
LMB_Data_Addr_30 <= lmb_data_addr;
LMB_Data_Addr_31 <= lmb_data_addr;
LMB_Data_write_0 <= lmb_data_write;
LMB_Data_write_1 <= lmb_data_write;
LMB_Data_write_2 <= lmb_data_write;
LMB_Data_write_3 <= lmb_data_write;
LMB_Data_write_4 <= lmb_data_write;
LMB_Data_write_5 <= lmb_data_write;
LMB_Data_write_6 <= lmb_data_write;
LMB_Data_write_7 <= lmb_data_write;
LMB_Data_write_8 <= lmb_data_write;
LMB_Data_write_9 <= lmb_data_write;
LMB_Data_write_10 <= lmb_data_write;
LMB_Data_write_11 <= lmb_data_write;
LMB_Data_write_12 <= lmb_data_write;
LMB_Data_write_13 <= lmb_data_write;
LMB_Data_write_14 <= lmb_data_write;
LMB_Data_write_15 <= lmb_data_write;
LMB_Data_write_16 <= lmb_data_write;
LMB_Data_write_17 <= lmb_data_write;
LMB_Data_write_18 <= lmb_data_write;
LMB_Data_write_19 <= lmb_data_write;
LMB_Data_write_20 <= lmb_data_write;
LMB_Data_write_21 <= lmb_data_write;
LMB_Data_write_22 <= lmb_data_write;
LMB_Data_write_23 <= lmb_data_write;
LMB_Data_write_24 <= lmb_data_write;
LMB_Data_write_25 <= lmb_data_write;
LMB_Data_write_26 <= lmb_data_write;
LMB_Data_write_27 <= lmb_data_write;
LMB_Data_write_28 <= lmb_data_write;
LMB_Data_write_29 <= lmb_data_write;
LMB_Data_write_30 <= lmb_data_write;
LMB_Data_write_31 <= lmb_data_write;
LMB_Read_strobe_0 <= lmb_read_strobe;
LMB_Read_strobe_1 <= lmb_read_strobe;
LMB_Read_strobe_2 <= lmb_read_strobe;
LMB_Read_strobe_3 <= lmb_read_strobe;
LMB_Read_strobe_4 <= lmb_read_strobe;
LMB_Read_strobe_5 <= lmb_read_strobe;
LMB_Read_strobe_6 <= lmb_read_strobe;
LMB_Read_strobe_7 <= lmb_read_strobe;
LMB_Read_strobe_8 <= lmb_read_strobe;
LMB_Read_strobe_9 <= lmb_read_strobe;
LMB_Read_strobe_10 <= lmb_read_strobe;
LMB_Read_strobe_11 <= lmb_read_strobe;
LMB_Read_strobe_12 <= lmb_read_strobe;
LMB_Read_strobe_13 <= lmb_read_strobe;
LMB_Read_strobe_14 <= lmb_read_strobe;
LMB_Read_strobe_15 <= lmb_read_strobe;
LMB_Read_strobe_16 <= lmb_read_strobe;
LMB_Read_strobe_17 <= lmb_read_strobe;
LMB_Read_strobe_18 <= lmb_read_strobe;
LMB_Read_strobe_19 <= lmb_read_strobe;
LMB_Read_strobe_20 <= lmb_read_strobe;
LMB_Read_strobe_21 <= lmb_read_strobe;
LMB_Read_strobe_22 <= lmb_read_strobe;
LMB_Read_strobe_23 <= lmb_read_strobe;
LMB_Read_strobe_24 <= lmb_read_strobe;
LMB_Read_strobe_25 <= lmb_read_strobe;
LMB_Read_strobe_26 <= lmb_read_strobe;
LMB_Read_strobe_27 <= lmb_read_strobe;
LMB_Read_strobe_28 <= lmb_read_strobe;
LMB_Read_strobe_29 <= lmb_read_strobe;
LMB_Read_strobe_30 <= lmb_read_strobe;
LMB_Read_strobe_31 <= lmb_read_strobe;
LMB_Write_strobe_0 <= lmb_write_strobe;
LMB_Write_strobe_1 <= lmb_write_strobe;
LMB_Write_strobe_2 <= lmb_write_strobe;
LMB_Write_strobe_3 <= lmb_write_strobe;
LMB_Write_strobe_4 <= lmb_write_strobe;
LMB_Write_strobe_5 <= lmb_write_strobe;
LMB_Write_strobe_6 <= lmb_write_strobe;
LMB_Write_strobe_7 <= lmb_write_strobe;
LMB_Write_strobe_8 <= lmb_write_strobe;
LMB_Write_strobe_9 <= lmb_write_strobe;
LMB_Write_strobe_10 <= lmb_write_strobe;
LMB_Write_strobe_11 <= lmb_write_strobe;
LMB_Write_strobe_12 <= lmb_write_strobe;
LMB_Write_strobe_13 <= lmb_write_strobe;
LMB_Write_strobe_14 <= lmb_write_strobe;
LMB_Write_strobe_15 <= lmb_write_strobe;
LMB_Write_strobe_16 <= lmb_write_strobe;
LMB_Write_strobe_17 <= lmb_write_strobe;
LMB_Write_strobe_18 <= lmb_write_strobe;
LMB_Write_strobe_19 <= lmb_write_strobe;
LMB_Write_strobe_20 <= lmb_write_strobe;
LMB_Write_strobe_21 <= lmb_write_strobe;
LMB_Write_strobe_22 <= lmb_write_strobe;
LMB_Write_strobe_23 <= lmb_write_strobe;
LMB_Write_strobe_24 <= lmb_write_strobe;
LMB_Write_strobe_25 <= lmb_write_strobe;
LMB_Write_strobe_26 <= lmb_write_strobe;
LMB_Write_strobe_27 <= lmb_write_strobe;
LMB_Write_strobe_28 <= lmb_write_strobe;
LMB_Write_strobe_29 <= lmb_write_strobe;
LMB_Write_strobe_30 <= lmb_write_strobe;
LMB_Write_strobe_31 <= lmb_write_strobe;
LMB_Byte_enable_0 <= lmb_byte_enable;
LMB_Byte_enable_1 <= lmb_byte_enable;
LMB_Byte_enable_2 <= lmb_byte_enable;
LMB_Byte_enable_3 <= lmb_byte_enable;
LMB_Byte_enable_4 <= lmb_byte_enable;
LMB_Byte_enable_5 <= lmb_byte_enable;
LMB_Byte_enable_6 <= lmb_byte_enable;
LMB_Byte_enable_7 <= lmb_byte_enable;
LMB_Byte_enable_8 <= lmb_byte_enable;
LMB_Byte_enable_9 <= lmb_byte_enable;
LMB_Byte_enable_10 <= lmb_byte_enable;
LMB_Byte_enable_11 <= lmb_byte_enable;
LMB_Byte_enable_12 <= lmb_byte_enable;
LMB_Byte_enable_13 <= lmb_byte_enable;
LMB_Byte_enable_14 <= lmb_byte_enable;
LMB_Byte_enable_15 <= lmb_byte_enable;
LMB_Byte_enable_16 <= lmb_byte_enable;
LMB_Byte_enable_17 <= lmb_byte_enable;
LMB_Byte_enable_18 <= lmb_byte_enable;
LMB_Byte_enable_19 <= lmb_byte_enable;
LMB_Byte_enable_20 <= lmb_byte_enable;
LMB_Byte_enable_21 <= lmb_byte_enable;
LMB_Byte_enable_22 <= lmb_byte_enable;
LMB_Byte_enable_23 <= lmb_byte_enable;
LMB_Byte_enable_24 <= lmb_byte_enable;
LMB_Byte_enable_25 <= lmb_byte_enable;
LMB_Byte_enable_26 <= lmb_byte_enable;
LMB_Byte_enable_27 <= lmb_byte_enable;
LMB_Byte_enable_28 <= lmb_byte_enable;
LMB_Byte_enable_29 <= lmb_byte_enable;
LMB_Byte_enable_30 <= lmb_byte_enable;
LMB_Byte_enable_31 <= lmb_byte_enable;
Generate_LMB_Inputs : process (mb_debug_enabled, lmb_data_read_vec_q, lmb_ready_vec_q, lmb_wait_vec_q, lmb_ue_vec_q)
variable data_mask : std_logic_vector(0 to C_DATA_SIZE - 1);
variable data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
variable ready : std_logic;
variable wait_i : std_logic;
variable ue : std_logic;
begin -- process Generate_LMB_Inputs
data_read := (others => '0');
ready := '0';
wait_i := '0';
ue := '0';
for I in 0 to C_EN_WIDTH - 1 loop
data_mask := (0 to C_DATA_SIZE - 1 => mb_debug_enabled(I));
data_read := data_read or (lmb_data_read_vec_q(I) and data_mask);
ready := ready or (lmb_ready_vec_q(I) and mb_debug_enabled(I));
wait_i := wait_i or (lmb_wait_vec_q(I) and mb_debug_enabled(I));
ue := ue or (lmb_ue_vec_q(I) and mb_debug_enabled(I));
end loop;
lmb_data_read <= data_read;
lmb_ready <= ready;
lmb_wait <= wait_i;
lmb_ue <= ue;
end process Generate_LMB_Inputs;
Clock_LMB_Inputs : process (M_AXI_ACLK)
begin
if M_AXI_ACLK'event and M_AXI_ACLK = '1' then -- rising clock edge
for I in 0 to C_EN_WIDTH - 1 loop
lmb_data_read_vec_q(I) <= lmb_data_read_vec(I);
lmb_ready_vec_q(I) <= lmb_ready_vec(I);
lmb_wait_vec_q(I) <= lmb_wait_vec(I);
lmb_ue_vec_q(I) <= lmb_ue_vec(I);
end loop;
end if;
end process Clock_LMB_Inputs;
lmb_data_read_vec(0) <= LMB_Data_Read_0;
lmb_data_read_vec(1) <= LMB_Data_Read_1;
lmb_data_read_vec(2) <= LMB_Data_Read_2;
lmb_data_read_vec(3) <= LMB_Data_Read_3;
lmb_data_read_vec(4) <= LMB_Data_Read_4;
lmb_data_read_vec(5) <= LMB_Data_Read_5;
lmb_data_read_vec(6) <= LMB_Data_Read_6;
lmb_data_read_vec(7) <= LMB_Data_Read_7;
lmb_data_read_vec(8) <= LMB_Data_Read_8;
lmb_data_read_vec(9) <= LMB_Data_Read_9;
lmb_data_read_vec(10) <= LMB_Data_Read_10;
lmb_data_read_vec(11) <= LMB_Data_Read_11;
lmb_data_read_vec(12) <= LMB_Data_Read_12;
lmb_data_read_vec(13) <= LMB_Data_Read_13;
lmb_data_read_vec(14) <= LMB_Data_Read_14;
lmb_data_read_vec(15) <= LMB_Data_Read_15;
lmb_data_read_vec(16) <= LMB_Data_Read_16;
lmb_data_read_vec(17) <= LMB_Data_Read_17;
lmb_data_read_vec(18) <= LMB_Data_Read_18;
lmb_data_read_vec(19) <= LMB_Data_Read_19;
lmb_data_read_vec(20) <= LMB_Data_Read_20;
lmb_data_read_vec(21) <= LMB_Data_Read_21;
lmb_data_read_vec(22) <= LMB_Data_Read_22;
lmb_data_read_vec(23) <= LMB_Data_Read_23;
lmb_data_read_vec(24) <= LMB_Data_Read_24;
lmb_data_read_vec(25) <= LMB_Data_Read_25;
lmb_data_read_vec(26) <= LMB_Data_Read_26;
lmb_data_read_vec(27) <= LMB_Data_Read_27;
lmb_data_read_vec(28) <= LMB_Data_Read_28;
lmb_data_read_vec(29) <= LMB_Data_Read_29;
lmb_data_read_vec(30) <= LMB_Data_Read_30;
lmb_data_read_vec(31) <= LMB_Data_Read_31;
lmb_ready_vec(0) <= LMB_Ready_0;
lmb_ready_vec(1) <= LMB_Ready_1;
lmb_ready_vec(2) <= LMB_Ready_2;
lmb_ready_vec(3) <= LMB_Ready_3;
lmb_ready_vec(4) <= LMB_Ready_4;
lmb_ready_vec(5) <= LMB_Ready_5;
lmb_ready_vec(6) <= LMB_Ready_6;
lmb_ready_vec(7) <= LMB_Ready_7;
lmb_ready_vec(8) <= LMB_Ready_8;
lmb_ready_vec(9) <= LMB_Ready_9;
lmb_ready_vec(10) <= LMB_Ready_10;
lmb_ready_vec(11) <= LMB_Ready_11;
lmb_ready_vec(12) <= LMB_Ready_12;
lmb_ready_vec(13) <= LMB_Ready_13;
lmb_ready_vec(14) <= LMB_Ready_14;
lmb_ready_vec(15) <= LMB_Ready_15;
lmb_ready_vec(16) <= LMB_Ready_16;
lmb_ready_vec(17) <= LMB_Ready_17;
lmb_ready_vec(18) <= LMB_Ready_18;
lmb_ready_vec(19) <= LMB_Ready_19;
lmb_ready_vec(20) <= LMB_Ready_20;
lmb_ready_vec(21) <= LMB_Ready_21;
lmb_ready_vec(22) <= LMB_Ready_22;
lmb_ready_vec(23) <= LMB_Ready_23;
lmb_ready_vec(24) <= LMB_Ready_24;
lmb_ready_vec(25) <= LMB_Ready_25;
lmb_ready_vec(26) <= LMB_Ready_26;
lmb_ready_vec(27) <= LMB_Ready_27;
lmb_ready_vec(28) <= LMB_Ready_28;
lmb_ready_vec(29) <= LMB_Ready_29;
lmb_ready_vec(30) <= LMB_Ready_30;
lmb_ready_vec(31) <= LMB_Ready_31;
lmb_wait_vec(0) <= LMB_Wait_0;
lmb_wait_vec(1) <= LMB_Wait_1;
lmb_wait_vec(2) <= LMB_Wait_2;
lmb_wait_vec(3) <= LMB_Wait_3;
lmb_wait_vec(4) <= LMB_Wait_4;
lmb_wait_vec(5) <= LMB_Wait_5;
lmb_wait_vec(6) <= LMB_Wait_6;
lmb_wait_vec(7) <= LMB_Wait_7;
lmb_wait_vec(8) <= LMB_Wait_8;
lmb_wait_vec(9) <= LMB_Wait_9;
lmb_wait_vec(10) <= LMB_Wait_10;
lmb_wait_vec(11) <= LMB_Wait_11;
lmb_wait_vec(12) <= LMB_Wait_12;
lmb_wait_vec(13) <= LMB_Wait_13;
lmb_wait_vec(14) <= LMB_Wait_14;
lmb_wait_vec(15) <= LMB_Wait_15;
lmb_wait_vec(16) <= LMB_Wait_16;
lmb_wait_vec(17) <= LMB_Wait_17;
lmb_wait_vec(18) <= LMB_Wait_18;
lmb_wait_vec(19) <= LMB_Wait_19;
lmb_wait_vec(20) <= LMB_Wait_20;
lmb_wait_vec(21) <= LMB_Wait_21;
lmb_wait_vec(22) <= LMB_Wait_22;
lmb_wait_vec(23) <= LMB_Wait_23;
lmb_wait_vec(24) <= LMB_Wait_24;
lmb_wait_vec(25) <= LMB_Wait_25;
lmb_wait_vec(26) <= LMB_Wait_26;
lmb_wait_vec(27) <= LMB_Wait_27;
lmb_wait_vec(28) <= LMB_Wait_28;
lmb_wait_vec(29) <= LMB_Wait_29;
lmb_wait_vec(30) <= LMB_Wait_30;
lmb_wait_vec(31) <= LMB_Wait_31;
lmb_ue_vec(0) <= LMB_UE_0;
lmb_ue_vec(1) <= LMB_UE_1;
lmb_ue_vec(2) <= LMB_UE_2;
lmb_ue_vec(3) <= LMB_UE_3;
lmb_ue_vec(4) <= LMB_UE_4;
lmb_ue_vec(5) <= LMB_UE_5;
lmb_ue_vec(6) <= LMB_UE_6;
lmb_ue_vec(7) <= LMB_UE_7;
lmb_ue_vec(8) <= LMB_UE_8;
lmb_ue_vec(9) <= LMB_UE_9;
lmb_ue_vec(10) <= LMB_UE_10;
lmb_ue_vec(11) <= LMB_UE_11;
lmb_ue_vec(12) <= LMB_UE_12;
lmb_ue_vec(13) <= LMB_UE_13;
lmb_ue_vec(14) <= LMB_UE_14;
lmb_ue_vec(15) <= LMB_UE_15;
lmb_ue_vec(16) <= LMB_UE_16;
lmb_ue_vec(17) <= LMB_UE_17;
lmb_ue_vec(18) <= LMB_UE_18;
lmb_ue_vec(19) <= LMB_UE_19;
lmb_ue_vec(20) <= LMB_UE_20;
lmb_ue_vec(21) <= LMB_UE_21;
lmb_ue_vec(22) <= LMB_UE_22;
lmb_ue_vec(23) <= LMB_UE_23;
lmb_ue_vec(24) <= LMB_UE_24;
lmb_ue_vec(25) <= LMB_UE_25;
lmb_ue_vec(26) <= LMB_UE_26;
lmb_ue_vec(27) <= LMB_UE_27;
lmb_ue_vec(28) <= LMB_UE_28;
lmb_ue_vec(29) <= LMB_UE_29;
lmb_ue_vec(30) <= LMB_UE_30;
lmb_ue_vec(31) <= LMB_UE_31;
end generate Use_Bus_MASTER;
Use_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and C_TRACE_AXI_MASTER) generate
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => false,
C_HAS_DIRECT_PORT => true
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => open,
LMB_Data_Read => (others => '0'),
LMB_Data_Write => open,
LMB_Addr_Strobe => open,
LMB_Read_Strobe => open,
LMB_Write_Strobe => open,
LMB_Ready => '0',
LMB_Wait => '0',
LMB_UE => '0',
LMB_Byte_Enable => open,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
end generate Use_Bus_MASTER_AXI;
No_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and not C_TRACE_AXI_MASTER) generate
begin
master_rd_idle <= '1';
master_rd_resp <= "00";
master_wr_idle <= '1';
master_wr_resp <= "00";
master_data_out <= (others => '0');
master_data_exists <= '0';
master_data_empty <= '1';
master_dwr_next <= '0';
master_dwr_done <= '0';
master_dwr_resp <= (others => '0');
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= (others => '0');
M_AXI_AWLEN <= (others => '0');
M_AXI_AWSIZE <= (others => '0');
M_AXI_AWBURST <= (others => '0');
M_AXI_AWLOCK <= '0';
M_AXI_AWCACHE <= (others => '0');
M_AXI_AWPROT <= (others => '0');
M_AXI_AWQOS <= (others => '0');
M_AXI_AWVALID <= '0';
M_AXI_WDATA <= (others => '0');
M_AXI_WSTRB <= (others => '0');
M_AXI_WLAST <= '0';
M_AXI_WVALID <= '0';
M_AXI_BREADY <= '0';
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= (others => '0');
M_AXI_ARBURST <= (others => '0');
M_AXI_ARLOCK <= '0';
M_AXI_ARCACHE <= (others => '0');
M_AXI_ARPROT <= (others => '0');
M_AXI_ARQOS <= (others => '0');
M_AXI_ARVALID <= '0';
M_AXI_RREADY <= '0';
end generate No_Bus_MASTER_AXI;
No_Bus_MASTER_LMB : if (C_DBG_MEM_ACCESS = 0) generate
begin
LMB_Data_Addr_0 <= (others => '0');
LMB_Data_Write_0 <= (others => '0');
LMB_Addr_Strobe_0 <= '0';
LMB_Read_Strobe_0 <= '0';
LMB_Write_Strobe_0 <= '0';
LMB_Byte_Enable_0 <= (others => '0');
LMB_Data_Addr_1 <= (others => '0');
LMB_Data_Write_1 <= (others => '0');
LMB_Addr_Strobe_1 <= '0';
LMB_Read_Strobe_1 <= '0';
LMB_Write_Strobe_1 <= '0';
LMB_Byte_Enable_1 <= (others => '0');
LMB_Data_Addr_2 <= (others => '0');
LMB_Data_Write_2 <= (others => '0');
LMB_Addr_Strobe_2 <= '0';
LMB_Read_Strobe_2 <= '0';
LMB_Write_Strobe_2 <= '0';
LMB_Byte_Enable_2 <= (others => '0');
LMB_Data_Addr_3 <= (others => '0');
LMB_Data_Write_3 <= (others => '0');
LMB_Addr_Strobe_3 <= '0';
LMB_Read_Strobe_3 <= '0';
LMB_Write_Strobe_3 <= '0';
LMB_Byte_Enable_3 <= (others => '0');
LMB_Data_Addr_4 <= (others => '0');
LMB_Data_Write_4 <= (others => '0');
LMB_Addr_Strobe_4 <= '0';
LMB_Read_Strobe_4 <= '0';
LMB_Write_Strobe_4 <= '0';
LMB_Byte_Enable_4 <= (others => '0');
LMB_Data_Addr_5 <= (others => '0');
LMB_Data_Write_5 <= (others => '0');
LMB_Addr_Strobe_5 <= '0';
LMB_Read_Strobe_5 <= '0';
LMB_Write_Strobe_5 <= '0';
LMB_Byte_Enable_5 <= (others => '0');
LMB_Data_Addr_6 <= (others => '0');
LMB_Data_Write_6 <= (others => '0');
LMB_Addr_Strobe_6 <= '0';
LMB_Read_Strobe_6 <= '0';
LMB_Write_Strobe_6 <= '0';
LMB_Byte_Enable_6 <= (others => '0');
LMB_Data_Addr_7 <= (others => '0');
LMB_Data_Write_7 <= (others => '0');
LMB_Addr_Strobe_7 <= '0';
LMB_Read_Strobe_7 <= '0';
LMB_Write_Strobe_7 <= '0';
LMB_Byte_Enable_7 <= (others => '0');
LMB_Data_Addr_8 <= (others => '0');
LMB_Data_Write_8 <= (others => '0');
LMB_Addr_Strobe_8 <= '0';
LMB_Read_Strobe_8 <= '0';
LMB_Write_Strobe_8 <= '0';
LMB_Byte_Enable_8 <= (others => '0');
LMB_Data_Addr_9 <= (others => '0');
LMB_Data_Write_9 <= (others => '0');
LMB_Addr_Strobe_9 <= '0';
LMB_Read_Strobe_9 <= '0';
LMB_Write_Strobe_9 <= '0';
LMB_Byte_Enable_9 <= (others => '0');
LMB_Data_Addr_10 <= (others => '0');
LMB_Data_Write_10 <= (others => '0');
LMB_Addr_Strobe_10 <= '0';
LMB_Read_Strobe_10 <= '0';
LMB_Write_Strobe_10 <= '0';
LMB_Byte_Enable_10 <= (others => '0');
LMB_Data_Addr_11 <= (others => '0');
LMB_Data_Write_11 <= (others => '0');
LMB_Addr_Strobe_11 <= '0';
LMB_Read_Strobe_11 <= '0';
LMB_Write_Strobe_11 <= '0';
LMB_Byte_Enable_11 <= (others => '0');
LMB_Data_Addr_12 <= (others => '0');
LMB_Data_Write_12 <= (others => '0');
LMB_Addr_Strobe_12 <= '0';
LMB_Read_Strobe_12 <= '0';
LMB_Write_Strobe_12 <= '0';
LMB_Byte_Enable_12 <= (others => '0');
LMB_Data_Addr_13 <= (others => '0');
LMB_Data_Write_13 <= (others => '0');
LMB_Addr_Strobe_13 <= '0';
LMB_Read_Strobe_13 <= '0';
LMB_Write_Strobe_13 <= '0';
LMB_Byte_Enable_13 <= (others => '0');
LMB_Data_Addr_14 <= (others => '0');
LMB_Data_Write_14 <= (others => '0');
LMB_Addr_Strobe_14 <= '0';
LMB_Read_Strobe_14 <= '0';
LMB_Write_Strobe_14 <= '0';
LMB_Byte_Enable_14 <= (others => '0');
LMB_Data_Addr_15 <= (others => '0');
LMB_Data_Write_15 <= (others => '0');
LMB_Addr_Strobe_15 <= '0';
LMB_Read_Strobe_15 <= '0';
LMB_Write_Strobe_15 <= '0';
LMB_Byte_Enable_15 <= (others => '0');
LMB_Data_Addr_16 <= (others => '0');
LMB_Data_Write_16 <= (others => '0');
LMB_Addr_Strobe_16 <= '0';
LMB_Read_Strobe_16 <= '0';
LMB_Write_Strobe_16 <= '0';
LMB_Byte_Enable_16 <= (others => '0');
LMB_Data_Addr_17 <= (others => '0');
LMB_Data_Write_17 <= (others => '0');
LMB_Addr_Strobe_17 <= '0';
LMB_Read_Strobe_17 <= '0';
LMB_Write_Strobe_17 <= '0';
LMB_Byte_Enable_17 <= (others => '0');
LMB_Data_Addr_18 <= (others => '0');
LMB_Data_Write_18 <= (others => '0');
LMB_Addr_Strobe_18 <= '0';
LMB_Read_Strobe_18 <= '0';
LMB_Write_Strobe_18 <= '0';
LMB_Byte_Enable_18 <= (others => '0');
LMB_Data_Addr_19 <= (others => '0');
LMB_Data_Write_19 <= (others => '0');
LMB_Addr_Strobe_19 <= '0';
LMB_Read_Strobe_19 <= '0';
LMB_Write_Strobe_19 <= '0';
LMB_Byte_Enable_19 <= (others => '0');
LMB_Data_Addr_20 <= (others => '0');
LMB_Data_Write_20 <= (others => '0');
LMB_Addr_Strobe_20 <= '0';
LMB_Read_Strobe_20 <= '0';
LMB_Write_Strobe_20 <= '0';
LMB_Byte_Enable_20 <= (others => '0');
LMB_Data_Addr_21 <= (others => '0');
LMB_Data_Write_21 <= (others => '0');
LMB_Addr_Strobe_21 <= '0';
LMB_Read_Strobe_21 <= '0';
LMB_Write_Strobe_21 <= '0';
LMB_Byte_Enable_21 <= (others => '0');
LMB_Data_Addr_22 <= (others => '0');
LMB_Data_Write_22 <= (others => '0');
LMB_Addr_Strobe_22 <= '0';
LMB_Read_Strobe_22 <= '0';
LMB_Write_Strobe_22 <= '0';
LMB_Byte_Enable_22 <= (others => '0');
LMB_Data_Addr_23 <= (others => '0');
LMB_Data_Write_23 <= (others => '0');
LMB_Addr_Strobe_23 <= '0';
LMB_Read_Strobe_23 <= '0';
LMB_Write_Strobe_23 <= '0';
LMB_Byte_Enable_23 <= (others => '0');
LMB_Data_Addr_24 <= (others => '0');
LMB_Data_Write_24 <= (others => '0');
LMB_Addr_Strobe_24 <= '0';
LMB_Read_Strobe_24 <= '0';
LMB_Write_Strobe_24 <= '0';
LMB_Byte_Enable_24 <= (others => '0');
LMB_Data_Addr_25 <= (others => '0');
LMB_Data_Write_25 <= (others => '0');
LMB_Addr_Strobe_25 <= '0';
LMB_Read_Strobe_25 <= '0';
LMB_Write_Strobe_25 <= '0';
LMB_Byte_Enable_25 <= (others => '0');
LMB_Data_Addr_26 <= (others => '0');
LMB_Data_Write_26 <= (others => '0');
LMB_Addr_Strobe_26 <= '0';
LMB_Read_Strobe_26 <= '0';
LMB_Write_Strobe_26 <= '0';
LMB_Byte_Enable_26 <= (others => '0');
LMB_Data_Addr_27 <= (others => '0');
LMB_Data_Write_27 <= (others => '0');
LMB_Addr_Strobe_27 <= '0';
LMB_Read_Strobe_27 <= '0';
LMB_Write_Strobe_27 <= '0';
LMB_Byte_Enable_27 <= (others => '0');
LMB_Data_Addr_28 <= (others => '0');
LMB_Data_Write_28 <= (others => '0');
LMB_Addr_Strobe_28 <= '0';
LMB_Read_Strobe_28 <= '0';
LMB_Write_Strobe_28 <= '0';
LMB_Byte_Enable_28 <= (others => '0');
LMB_Data_Addr_29 <= (others => '0');
LMB_Data_Write_29 <= (others => '0');
LMB_Addr_Strobe_29 <= '0';
LMB_Read_Strobe_29 <= '0';
LMB_Write_Strobe_29 <= '0';
LMB_Byte_Enable_29 <= (others => '0');
LMB_Data_Addr_30 <= (others => '0');
LMB_Data_Write_30 <= (others => '0');
LMB_Addr_Strobe_30 <= '0';
LMB_Read_Strobe_30 <= '0';
LMB_Write_Strobe_30 <= '0';
LMB_Byte_Enable_30 <= (others => '0');
LMB_Data_Addr_31 <= (others => '0');
LMB_Data_Write_31 <= (others => '0');
LMB_Addr_Strobe_31 <= '0';
LMB_Read_Strobe_31 <= '0';
LMB_Write_Strobe_31 <= '0';
LMB_Byte_Enable_31 <= (others => '0');
end generate No_Bus_MASTER_LMB;
Use_AXI_IPIF : if (C_USE_UART = 1) or (C_DBG_REG_ACCESS = 1) generate
begin
-- ip2bus_data assignment - as core may use less than 32 bits
ip2bus_data(C_S_AXI_DATA_WIDTH-1 downto C_REG_DATA_WIDTH) <= (others => '0');
---------------------------------------------------------------------------
-- AXI lite IPIF
---------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map (
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end generate Use_AXI_IPIF;
No_AXI_IPIF : if (C_USE_UART = 0) and (C_DBG_REG_ACCESS = 0) generate
begin
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
S_AXI_BRESP <= (others => '0');
S_AXI_BVALID <= '0';
S_AXI_ARREADY <= '0';
S_AXI_RDATA <= (others => '0');
S_AXI_RRESP <= (others => '0');
S_AXI_RVALID <= '0';
bus2ip_clk <= '0';
bus2ip_resetn <= '0';
bus2ip_data <= (others => '0');
bus2ip_rdce <= (others => '0');
bus2ip_wrce <= (others => '0');
bus2ip_cs <= (others => '0');
end generate No_AXI_IPIF;
end architecture IMP;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i8259 is
port (
CLK : in std_logic;
RESET : in std_logic;
A0 : in std_logic;
WR : in std_logic;
INTA : in std_logic;
INTR : out std_logic;
IRQ : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0) );
end i8259;
architecture rtl of i8259 is
signal IRR : std_logic_vector(7 downto 0);
signal IRQ_LAST : std_logic_vector(7 downto 0);
signal IMR : std_logic_vector(7 downto 0);
signal ISR : std_logic_vector(7 downto 0);
signal ICW1 : std_logic_vector(7 downto 0);
signal ICW2 : std_logic_vector(7 downto 0);
signal STATE : unsigned(1 downto 0);
signal IRQ_WORK : std_logic_vector(2 downto 0);
signal INIT : std_logic;
signal EXINTA : std_logic;
signal EXWR : std_logic;
alias INTERVAL : std_logic is ICW1(2);
alias ADDRH : std_logic_vector(7 downto 0) is ICW2;
alias ADDRL : std_logic_vector(2 downto 0) is ICW1(7 downto 5);
begin
INTR <= '1' when ISR /= "00000000" or IRR /= "00000000" else '0';
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
IMR <= "11111111";
ISR <= "00000000";
IRR <= "00000000";
IRQ_WORK <= "000";
IRQ_LAST <= "00000000";
DO <= "00000000";
INIT <= '0';
STATE <= "00";
EXINTA <= '0';
EXWR <= '0';
else
EXINTA <= INTA;
EXWR <= WR;
-- write to PIC registers
if WR = '1' and EXWR = '0' then
if INIT = '1' then -- Write to ICW2
ICW2 <= DI;
INIT <= '0';
else
if A0 = '1' then -- Write to OCW1
IMR <= DI;
elsif DI(4) = '1' then -- Write to ICW1 (Reset and Init PIC)
IMR <= "11111111";
ISR <= "00000000";
IRR <= "00000000";
ICW1 <= DI;
INIT <= '1';
end if;
end if;
end if;
-- Write new interrupts to IRR ---------------------
IRQ_LAST <= IRQ;
for POS in 0 to 7 loop
-- if IRQ_LAST(POS) = '0' and IRQ(POS) = '1' and IMR(POS) = '0' then ################# ISR CHECK TOO?????????????
if IRQ_LAST(POS) = '0' and IRQ(POS) = '1' and IMR(POS) = '0' and ISR(POS) = '0' then
IRR(POS) <= '1';
end if;
end loop;
-- Check for interrupts in IRR, clear IRR and set ISR/IRQ_WORK (current interrupt number)
if ISR = "00000000" then
if IRR(0) = '1' then IRQ_WORK <= "000"; IRR(0) <= '0'; ISR(0) <= '1';
elsif IRR(1) = '1' then IRQ_WORK <= "001"; IRR(1) <= '0'; ISR(1) <= '1';
elsif IRR(2) = '1' then IRQ_WORK <= "010"; IRR(2) <= '0'; ISR(2) <= '1';
elsif IRR(3) = '1' then IRQ_WORK <= "011"; IRR(3) <= '0'; ISR(3) <= '1';
elsif IRR(4) = '1' then IRQ_WORK <= "100"; IRR(4) <= '0'; ISR(4) <= '1';
elsif IRR(5) = '1' then IRQ_WORK <= "101"; IRR(5) <= '0'; ISR(5) <= '1';
elsif IRR(6) = '1' then IRQ_WORK <= "110"; IRR(6) <= '0'; ISR(6) <= '1';
elsif IRR(7) = '1' then IRQ_WORK <= "111"; IRR(7) <= '0'; ISR(7) <= '1';
end if;
end if;
-- State machine for interrupt acknowledge
if INTA = '1' and EXINTA = '0' then
case STATE is
when "00" =>
DO <= "11001101";
STATE <= "01";
when "01" =>
if INTERVAL = '0' then -- 8
DO <= ADDRL(2 downto 1) & IRQ_WORK & "000";
else -- 4
DO <= ADDRL(2 downto 0) & IRQ_WORK & "00";
end if;
STATE <= "10";
when "10" =>
DO <= ADDRH;
ISR <= "00000000";
STATE <= "00";
when others =>
null;
end case;
end if;
end if;
end if;
end process;
end rtl;
|
library verilog;
use verilog.vl_types.all;
entity memory_pipe_arbiter is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iDATA_REQ : in vl_logic;
oDATA_LOCK : out vl_logic;
iDATA_ORDER : in vl_logic_vector(1 downto 0);
iDATA_MASK : in vl_logic_vector(3 downto 0);
iDATA_RW : in vl_logic;
iDATA_TID : in vl_logic_vector(13 downto 0);
iDATA_MMUMOD : in vl_logic_vector(1 downto 0);
iDATA_PDT : in vl_logic_vector(31 downto 0);
iDATA_ADDR : in vl_logic_vector(31 downto 0);
iDATA_DATA : in vl_logic_vector(31 downto 0);
oDATA_REQ : out vl_logic;
iDATA_BUSY : in vl_logic;
oDATA_PAGEFAULT : out vl_logic;
oDATA_DATA : out vl_logic_vector(63 downto 0);
oDATA_MMU_FLAGS : out vl_logic_vector(27 downto 0);
iINST_REQ : in vl_logic;
oINST_LOCK : out vl_logic;
iINST_MMUMOD : in vl_logic_vector(1 downto 0);
iINST_PDT : in vl_logic_vector(31 downto 0);
iINST_ADDR : in vl_logic_vector(31 downto 0);
oINST_REQ : out vl_logic;
iINST_BUSY : in vl_logic;
oINST_PAGEFAULT : out vl_logic;
oINST_QUEUE_FLUSH: out vl_logic;
oINST_DATA : out vl_logic_vector(63 downto 0);
oINST_MMU_FLAGS : out vl_logic_vector(27 downto 0);
oMEMORY_REQ : out vl_logic;
iMEMORY_LOCK : in vl_logic;
oMEMORY_DATA_STORE_ACK: out vl_logic;
oMEMORY_MMU_MODE: out vl_logic_vector(1 downto 0);
oMEMORY_PDT : out vl_logic_vector(31 downto 0);
oMEMORY_ORDER : out vl_logic_vector(1 downto 0);
oMEMORY_MASK : out vl_logic_vector(3 downto 0);
oMEMORY_RW : out vl_logic;
oMEMORY_ADDR : out vl_logic_vector(31 downto 0);
oMEMORY_DATA : out vl_logic_vector(31 downto 0);
iMEMORY_VALID : in vl_logic;
oMEMORY_BUSY : out vl_logic;
iMEMORY_STORE_ACK: in vl_logic;
iMEMORY_PAGEFAULT: in vl_logic;
iMEMORY_QUEUE_FLUSH: in vl_logic;
iMEMORY_DATA : in vl_logic_vector(63 downto 0);
iMEMORY_MMU_FLAGS: in vl_logic_vector(27 downto 0)
);
end memory_pipe_arbiter;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:45:27 11/28/2012
-- Design Name:
-- Module Name: mips - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.tipos.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mips is
port (clk, reset : in std_logic;
inst: out std_logic_vector(31 downto 0)
);
end mips;
architecture Behavioral of mips is
signal Estado, sig_estado: Estados;
--Señales memorias
--banco de registros
signal RW: std_logic_vector(4 downto 0);
signal busW, busB, busA: std_logic_vector(31 downto 0);
--memoria de instrucciones
--signal ADDR: std_logic_vector(4 downto 0);
signal DR: std_logic_vector(31 downto 0);
--memoria de datos
signal DRDat : std_logic_vector(31 downto 0);
signal RDat, WDat: std_logic;
--Señales Controles
--control ALU
signal ALUCtrl: std_logic_vector(1 downto 0);
--control saltos
signal EscrPC: std_logic;
signal salida: std_logic;
--control general
signal PcWriteCond0, PcWriteCond1, PcWriteCond2: std_logic;
signal Reg_Write: std_logic;
signal ALUOp0, ALUOp1, ALUOp2: std_logic;
signal ALUOp: std_logic_vector(2 downto 0);
signal RegDst, MemtoReg: std_logic;
signal ALUA,ALUB0,ALUB1, PcSrc0, PcSrc1:std_logic;
signal sig_estadoControl: Estados;
--Señales ALU
signal entradaA, entradaB: std_logic_vector(31 downto 0);
signal cero: std_logic;
signal mayorque: std_logic;
signal resultado: std_logic_vector(31 downto 0);
--Señales Extensor
signal extendido: std_logic_vector(31 downto 0);
--señales PC
signal loadPC: std_logic;
signal tempPC, PC: std_logic_vector(31 downto 0);
--registros temporales --
signal registroA, registroB, salidaALU, Instruction: std_logic_vector(31 downto 0);
signal entradaControl: std_logic_vector(5 downto 0);
signal tempA, tempB, tempSalidaALU, tempInstruction: std_logic_vector(31 downto 0);
signal loadA,loadB,loadSalidaALU, loadInstruction, loadEntradaControl: std_logic;
signal entradaExtensor: std_logic_vector(15 downto 0);
component MemoriaDeInstrucciones is
port( Clock: in std_logic;
ADDR: in std_logic_vector(4 downto 0);
DR : out std_logic_vector(31 downto 0)
);
end component;
component MemoriaDeDatos is
port( Clock: in std_logic;
ADDR, write_addr: in std_logic_vector(4 downto 0);
DR : out std_logic_vector(31 downto 0);
DW: in std_logic_vector(31 downto 0);
R, W: in std_logic
);
end component;
component BancoDeRegistros is
port(
Clock: in std_logic;
Reg_Write: in std_logic;
RA: in std_logic_vector(4 downto 0);
RB: in std_logic_vector(4 downto 0);
RW: in std_logic_vector(4 downto 0);
busW: in std_logic_vector(31 downto 0);
busA: out std_logic_vector(31 downto 0);
busB: out std_logic_vector(31 downto 0)
);
end component;
component ExtensorSigno is
port(
A: in std_logic_vector (15 downto 0);
S: out std_logic_vector (31 downto 0)
);
end component;
component alu8bit is
port(
a, b : in std_logic_vector(31 downto 0);
op : in std_logic_vector(1 downto 0);
zero, bigthan : out std_logic;
result : out std_logic_vector(31 downto 0)
);
end component;
component control is
port(instruction: in std_logic_vector(5 downto 0);
Estado: in ESTADOS;
sig_estado: out ESTADOS;
RegDst, RegWrite, MemWrite, MemRead, MemtoReg, PcWriteCond0, PcWriteCond1, PcWriteCond2,
ALUOp0, ALUOp1, ALUOp2, ALUA, ALUB0, ALUB1, PcSrc0, PcSrc1, PcWrite:out std_logic
);
end component;
component AluControl is
port (funct: in std_logic_vector(5 downto 0);
AluOp:in std_logic_vector(2 downto 0);
--AluOp(1) es 1
AluCtr: out std_logic_vector(1 downto 0)
);
end component;
component ControlBranch is
port (cero , mayorque, saltar,EscrPC,EscrPC_Cond1,EscrPC_Cond2: in std_logic;--1 es menos significativo
salida: out std_logic
);
end component;
begin
ALUOp<=ALUOp2&ALUOp1&ALUOp0;
MemIns: MemoriaDeInstrucciones
port map(clk, PC(4 downto 0), DR);--siempre se lee nunca se escribe
MemDatos: MemoriaDeDatos
port map(clk, salidaALU(4 downto 0), salidaALU(4 downto 0), DRDat, registroB, RDat, WDat);
Banco_Registros: BancoDeRegistros
port map(clk, Reg_Write, DR(25 downto 21), DR(20 downto 16), RW, busW, busA, busB);
ControlSaltos: ControlBranch
port map(cero , mayorque, PcWriteCond2,EscrPC, PcWriteCond0,PcWriteCond1, salida);
ControlAlu: AluControl
port map(Instruction(5 downto 0), ALUOp, ALUCtrl);
ControlG: control
port map(entradaControl, Estado, sig_estadoControl,
RegDst, Reg_Write, WDat, RDat, MemtoReg, PcWriteCond0,PcWriteCond1,PcWriteCond2, ALUOp0, ALUOp1,
ALUOp2, ALUA, ALUB0, ALUB1, PcSrc0, PcSrc1, EscrPc);
ALU: alu8bit
port map(entradaA,entradaB, ALUCtrl, cero, mayorque, resultado);
Extensor: ExtensorSigno
port map(entradaExtensor,extendido);
RW<=Instruction(20 downto 16) when RegDst='0' else
Instruction(15 downto 11);
busW<= salidaALU when MemtoReg='0' else
DRDat;
entradaA<=PC when ALUA='0' else
registroA;
entradaB<= registroB when (ALUB1='0' and ALUB0='0') else
X"00000001" when (ALUB1='0' and ALUB0='1') else
extendido;
tempPC<= resultado when (PcSrc1='0' and PcSrc0='0') else
salidaALU when (PcSrc1='0' and PcSrc0='1') else
PC(31 downto 26)&Instruction(25 downto 0);
loadPC<=salida;
tempSalidaALU<=resultado;
tempInstruction<=DR;
tempA<=busA;
tempB<=busB;
sig_estado <= sig_estadoControl;
inst<=Instruction;
Síncrono: process(clk, reset)
begin
if reset='1' then
Estado<=F;
PC<=X"00000000";
elsif clk'event and clk ='1' then
Estado<=sig_estado;
if loadPC='1' then
PC<=tempPC;
end if;
if loadA='1' then
registroA<=tempA;
end if;
if loadB='1' then
registroB<=tempB;
end if;
if loadSalidaALU='1' then
salidaALU<=tempSalidaALU;
end if;
if loadInstruction='1' then
Instruction<=tempInstruction;
end if;
if loadEntradaControl='0' then
entradaControl <= DR(31 downto 26);
elsif loadEntradaControl='1' then
entradaControl <= Instruction(31 downto 26);
end if;
end if;
end process Síncrono;
Combinacional:process(clk,Estado--,registroA,registroB,salidaALU, PC
)
begin
case Estado is
when F =>
loadInstruction<='1';
loadA<='0';
loadB<='0';
loadSalidaALU<='0';
loadEntradaControl <= '0';
entradaExtensor <= DR(15 downto 0);--indefinido
when ID => --en ID la instrucción siempre es la correcta
loadInstruction<='1';
loadA<='1';
loadB<='1';
loadSalidaALU<='1';
loadEntradaControl<='0';
entradaExtensor <= DR(15 downto 0);
when EX =>
loadInstruction<='0';
loadA<='0';
loadB<='0';
loadSalidaALU<='1';
loadEntradaControl<='1';
entradaExtensor <= Instruction(15 downto 0);
when MEM =>
loadInstruction<='0';
loadA<='0';
loadB<='0';
loadSalidaALU<='0';
loadEntradaControl<='1';
entradaExtensor <= Instruction(15 downto 0);
when WB =>
loadInstruction<='0';
loadA<='0';
loadB<='0';
loadSalidaALU<='0';
loadEntradaControl<='1';
entradaExtensor <= Instruction(15 downto 0);
end case;
end process Combinacional;
end Behavioral; |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_ok_7_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_7_e-rtl-a.vhd,v 1.1 2006/11/22 10:40:09 wig Exp $
-- $Date: 2006/11/22 10:40:09 $
-- $Log: inst_shadow_ok_7_e-rtl-a.vhd,v $
-- Revision 1.1 2006/11/22 10:40:09 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_shadow_ok_7_e
--
architecture rtl of inst_shadow_ok_7_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- NEED RESULT: ARCH00590: Variable declarations - composite globally static access subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00590
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.3 (11)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00590)
-- ENT00590_Test_Bench(ARCH00590_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00590 of GENERIC_STANDARD_TYPES is
begin
process
variable correct : boolean := true ;
type a_bit_vector is access bit_vector ;
variable av_bit_vector_1, av_bit_vector_2 : a_bit_vector
:= new st_bit_vector ;
type a_string is access string ;
variable av_string_1, av_string_2 : a_string
:= new st_string ;
type a_t_rec1 is access t_rec1 ;
variable av_t_rec1_1, av_t_rec1_2 : a_t_rec1
:= new st_rec1 ;
type a_st_rec1 is access st_rec1 ;
variable av_st_rec1_1, av_st_rec1_2 : a_st_rec1
:= new st_rec1 ;
type a_t_rec2 is access t_rec2 ;
variable av_t_rec2_1, av_t_rec2_2 : a_t_rec2
:= new st_rec2 ;
type a_st_rec2 is access st_rec2 ;
variable av_st_rec2_1, av_st_rec2_2 : a_st_rec2
:= new st_rec2 ;
type a_t_rec3 is access t_rec3 ;
variable av_t_rec3_1, av_t_rec3_2 : a_t_rec3
:= new st_rec3 ;
type a_st_rec3 is access st_rec3 ;
variable av_st_rec3_1, av_st_rec3_2 : a_st_rec3
:= new st_rec3 ;
type a_t_arr1 is access t_arr1 ;
variable av_t_arr1_1, av_t_arr1_2 : a_t_arr1
:= new st_arr1 ;
type a_st_arr1 is access st_arr1 ;
variable av_st_arr1_1, av_st_arr1_2 : a_st_arr1
:= new st_arr1 ;
type a_t_arr2 is access t_arr2 ;
variable av_t_arr2_1, av_t_arr2_2 : a_t_arr2
:= new st_arr2 ;
type a_st_arr2 is access st_arr2 ;
variable av_st_arr2_1, av_st_arr2_2 : a_st_arr2
:= new st_arr2 ;
type a_t_arr3 is access t_arr3 ;
variable av_t_arr3_1, av_t_arr3_2 : a_t_arr3
:= new st_arr3 ;
type a_st_arr3 is access st_arr3 ;
variable av_st_arr3_1, av_st_arr3_2 : a_st_arr3
:= new st_arr3 ;
begin
av_bit_vector_1 := new st_bit_vector'(c_st_bit_vector_1) ;
av_string_1 := new st_string'(c_st_string_1) ;
av_t_rec1_1 := new st_rec1'(c_st_rec1_1) ;
av_st_rec1_1 := new st_rec1'(c_st_rec1_1) ;
av_t_rec2_1 := new st_rec2'(c_st_rec2_1) ;
av_st_rec2_1 := new st_rec2'(c_st_rec2_1) ;
av_t_rec3_1 := new st_rec3'(c_st_rec3_1) ;
av_st_rec3_1 := new st_rec3'(c_st_rec3_1) ;
av_t_arr1_1 := new st_arr1'(c_st_arr1_1) ;
av_st_arr1_1 := new st_arr1'(c_st_arr1_1) ;
av_t_arr2_1 := new st_arr2'(c_st_arr2_1) ;
av_st_arr2_1 := new st_arr2'(c_st_arr2_1) ;
av_t_arr3_1 := new st_arr3'(c_st_arr3_1) ;
av_st_arr3_1 := new st_arr3'(c_st_arr3_1) ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_1 ;
correct := correct and av_string_1.all
= c_st_string_1 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_1 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_1 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_1 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_1 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_1 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_1 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_1 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_1 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_1 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_1 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_1 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_1 ;
av_bit_vector_1.all := c_st_bit_vector_2 ;
av_string_1.all := c_st_string_2 ;
av_t_rec1_1.all := c_st_rec1_2 ;
av_st_rec1_1.all := c_st_rec1_2 ;
av_t_rec2_1.all := c_st_rec2_2 ;
av_st_rec2_1.all := c_st_rec2_2 ;
av_t_rec3_1.all := c_st_rec3_2 ;
av_st_rec3_1.all := c_st_rec3_2 ;
av_t_arr1_1.all := c_st_arr1_2 ;
av_st_arr1_1.all := c_st_arr1_2 ;
av_t_arr2_1.all := c_st_arr2_2 ;
av_st_arr2_1.all := c_st_arr2_2 ;
av_t_arr3_1.all := c_st_arr3_2 ;
av_st_arr3_1.all := c_st_arr3_2 ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_2 ;
correct := correct and av_string_1.all
= c_st_string_2 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_2 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_2 ;
test_report ( "ARCH00590" ,
"Variable declarations - composite globally static access subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00590 ;
--
entity ENT00590_Test_Bench is
end ENT00590_Test_Bench ;
--
architecture ARCH00590_Test_Bench of ENT00590_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00590 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00590_Test_Bench ;
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: EUDET TLU interface
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity eudet_tlu is
port (
-- Sys connect
clk_i : IN std_logic;
rst_n_i : IN std_logic;
-- Eudet signals
eudet_trig_i : IN std_logic;
eudet_rst_i : IN std_logic;
eudet_busy_o : OUT std_logic;
eudet_clk_o : OUT std_logic;
-- From logic
busy_i : IN std_logic;
simple_mode_i : IN std_logic;
-- To logic
trig_o : OUT std_logic;
rst_o : OUT std_logic;
trig_tag_o : OUT std_logic_vector(15 downto 0)
);
end eudet_tlu;
architecture rtl of eudet_tlu is
-- Components
component synchronizer
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end component;
-- constants
signal C_DEADTIME : integer := 300; -- clk_i cycles
signal C_CLKDIVIDER : integer := 4; -- 40 MHz -> 10Mhz
-- State machine
type state_type is (IDLE, TRIGGER, RECEIVE, DEAD);
signal state : state_type;
-- Sync inputs
signal sync_eudet_trig_i : std_logic;
signal sync_eudet_rst_i : std_logic;
signal trig_tag_t : std_logic_vector(15 downto 0); -- only 15:1 good
signal eudet_busy_t : std_logic;
signal eudet_clk_t : std_logic;
signal eudet_bust_t : std_logic;
signal clk_counter : unsigned (3 downto 0);
signal bit_counter : unsigned (4 downto 0);
signal dead_counter : unsigned (9 downto 0);
begin
-- Sync async inputs
trig_sync: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => eudet_trig_i, sync_out => sync_eudet_trig_i);
rst_sync: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => eudet_rst_i, sync_out => sync_eudet_rst_i);
eudet_busy_o <= eudet_busy_t;
eudet_clk_o <= eudet_clk_t;
rst_o <= '0';
state_machine: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
state <= IDLE;
eudet_busy_t <= '0';
eudet_clk_t <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
dead_counter <= (others => '0');
trig_tag_t <= (others => '0');
trig_tag_o <= (others => '0');
trig_o <= '0';
elsif rising_edge(clk_i) then
case state is
when IDLE =>
eudet_busy_t <= '0';
eudet_clk_t <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
trig_o <= '0';
if (sync_eudet_trig_i = '1') then
state <= TRIGGER;
end if;
when TRIGGER =>
-- Raise busy and wit until trigger is negated
eudet_busy_t <= '1';
eudet_clk_t <= '0';
trig_o <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
trig_tag_t <= (others => '0');
dead_counter <= (others => '0');
if (sync_eudet_trig_i = '0' and simple_mode_i = '0') then
state <= RECEIVE;
elsif (sync_eudet_trig_i = '0' and simple_mode_i = '1') then
state <= DEAD;
end if;
when RECEIVE =>
eudet_busy_t <= '1';
trig_o <= '0';
clk_counter <= clk_counter + 1;
dead_counter <= (others => '0');
if (clk_counter = (C_CLKDIVIDER-1)) then
clk_counter <= (others => '0');
eudet_clk_t <= not eudet_clk_t;
if (eudet_clk_t = '1') then --sampling on negative edge
bit_counter <= bit_counter + 1;
trig_tag_t <= eudet_trig_i & trig_tag_t(15 downto 1); -- do not need synced vers here
end if;
end if;
if (bit_counter = "10000") then
state <= DEAD;
trig_tag_o <= '0' & trig_tag_t(14 downto 0);
end if;
when DEAD =>
eudet_busy_t <= '1';
eudet_clk_t <= '0';
trig_o <= '0';
if (dead_counter = 0) then
trig_o <= '1'; -- Trigger now (16 clock cycles after the inital trigger?)
end if;
dead_counter <= dead_counter + 1;
if (dead_counter = C_DEADTIME) then
state <= IDLE;
end if;
when others =>
eudet_busy_t <= '0';
eudet_clk_t <= '0';
trig_o <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
state <= IDLE;
end case;
end if;
end process state_machine;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Utilidad_RS232 IS
END TB_Utilidad_RS232;
ARCHITECTURE behavior OF TB_Utilidad_RS232 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Utilidad_RS232
PORT(
clk : IN std_logic;
Recibo : IN std_logic;
Devuelvo : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal Recibo : std_logic := '0';
--Outputs
signal Devuelvo : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Utilidad_RS232 PORT MAP (
clk => clk,
Recibo => Recibo,
Devuelvo => Devuelvo
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-------------------------------------------------------------
-- Recibo un 11111111 con paridad 0
-------------------------------------------------------------
-- IDLE --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Recibo <= '0';
wait for 0.10416 ms;
-- 8 BITS DE INFORMACION --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Recibo <= '0';
wait for 0.10416 ms;
-- BIT DE PARADA --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-------------------------------------------------------------
-- Recibo un 01111110 con paridad 1 MALO!!!!!!
-------------------------------------------------------------
-- IDLE --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Recibo <= '0';
wait for 0.10416 ms;
-- 8 BITS DE INFORMACION --
Recibo <= '0';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE PARADA --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-------------------------------------------------------------
-- Recibo un 10110110 con paridad 1
-------------------------------------------------------------
-- IDLE --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Recibo <= '0';
wait for 0.10416 ms;
-- 8 BITS DE INFORMACION --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE PARADA --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
wait;
end process;
END;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: eth_ahb_mst
-- File: eth_ahb_mst.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Ethernet MAC AHB master interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of eth_ahb_mst is
type reg_type is record
bg : std_ulogic; --bus granted
bo : std_ulogic; --bus owner, 0=rx, 1=tx
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
error : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, tmsti, rmsti, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable nbo : std_ulogic;
variable tretry : std_ulogic;
variable rretry : std_ulogic;
variable rready : std_ulogic;
variable tready : std_ulogic;
variable rerror : std_ulogic;
variable terror : std_ulogic;
variable tgrant : std_ulogic;
variable rgrant : std_ulogic;
begin
v := r; htrans := HTRANS_IDLE; rready := '0'; tready := '0'; tretry := '0';
rretry := '0'; rerror := '0'; terror := '0'; tgrant := '0'; rgrant := '0';
if r.bo = '0' then hwdata := rmsti.data;
else hwdata := tmsti.data; end if;
hbusreq := tmsti.req or rmsti.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
if r.retry = '0' then
nbo := tmsti.req and not (rmsti.req and not r.bo);
else
nbo := r.bo;
end if;
if nbo = '0' then
haddr := rmsti.addr; hwrite := rmsti.write;
if (rmsti.req and r.ba and not r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (rmsti.req and r.bg and ahbmi.hready and not r.retry) = '1'
then rgrant := '1'; end if;
else
haddr := tmsti.addr; hwrite := tmsti.write;
if (tmsti.req and r.ba and r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (tmsti.req and r.bg and ahbmi.hready and not r.retry) = '1'
then tgrant := '1'; end if;
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111" then
v.bb := '1';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.bo = '0' then
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => rready := '1';
when HRESP_SPLIT | HRESP_RETRY => rretry := '1';
when HRESP_ERROR => rerror := '1';
when others => null;
end case;
end if;
end if;
else
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => tready := '1';
when HRESP_SPLIT | HRESP_RETRY => tretry := '1';
when HRESP_ERROR => terror := '1';
when others => null;
end case;
end if;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if (r.ba = '1') and
(ahbmi.hresp = HRESP_ERROR)
then v.error := not ahbmi.hready; else v.error := '0'; end if;
if (r.retry or r.error) = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bo := nbo; v.bg := ahbmi.hgrant;
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bo := '0'; v.bb := '0';
end if;
rin <= v;
tmsto.data <= ahbmi.hrdata;
rmsto.data <= ahbmi.hrdata;
tmsto.error <= terror;
tmsto.retry <= tretry;
tmsto.ready <= tready;
rmsto.error <= rerror;
rmsto.retry <= rretry;
rmsto.ready <= rready;
tmsto.grant <= tgrant;
rmsto.grant <= rgrant;
ahbmo.htrans <= htrans;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= hwdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hsize <= HSIZE_WORD;
ahbmo.hburst <= HBURST_INCR;
ahbmo.hprot <= "0011";
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.std_logic_arith.all;
use WORK.CONSCTANS.ALL;
entity COUNTER is
port (
CLK : in std_logic;
RESET : in std_logic;
UP : in std_logic;
CNT_OUT : out std_logic_vector (OUTPUT_WIDTH - 1 downto 0);
TOP : out std_logic;
BOTTOM : out std_logic
);
end COUNTER;
architecture COUNTER_BODY of COUNTER is
signal COUNTER_VALUE : std_logic_vector (COUNTER_WIDTH - 1 downto 0);
begin
COUNT : process (CLK)
begin
if CLK = '1' and CLK'event then
if RESET = '1' then
COUNTER_VALUE <= conv_std_logic_vector (0, COUNTER_WIDTH);
elsif UP = '1' then
COUNTER_VALUE <= COUNTER_VALUE + 1;
else
COUNTER_VALUE <= COUNTER_VALUE - 1;
end if;
end if;
end process;
ASSIGN : process (COUNTER_VALUE)
begin
CNT_OUT <= COUNTER_VALUE (COUNTER_WIDTH - 1 downto COUNTER_WIDTH - OUTPUT_WIDTH);
end process;
-- kombinacni logika, ktera nastavuje TOP
TOP_PROC : process(COUNTER_VALUE)
variable auxTOP : std_logic;
begin
auxTOP := '1';
for I in 0 to COUNTER_WIDTH-1 loop
auxTOP := auxTOP and COUNTER_VALUE(I);
end loop;
TOP <= auxTOP after 10 ns;
end process TOP_PROC;
-- kombinacni logika, ktera nastavuje BOTTOM
BOTTOM_PROC : process(COUNTER_VALUE)
variable auxBOTTOM : std_logic;
begin
auxBOTTOM := '0';
for I in 0 to COUNTER_WIDTH-1 loop
auxBOTTOM := auxBOTTOM or COUNTER_VALUE(I);
end loop;
BOTTOM <= not auxBOTTOM after 10 ns;
end process BOTTOM_PROC;
end COUNTER_BODY;
|
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package multlib is
component mul_17_17
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(16 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(33 downto 0)
);
end component;
component mul_33_9
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(8 downto 0);
p : out std_logic_vector(41 downto 0)
);
end component;
component mul_33_17
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(49 downto 0)
);
end component;
component mul_33_33
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(32 downto 0);
p : out std_logic_vector(65 downto 0)
);
end component;
component add32
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
ci : in std_ulogic;
s : out std_logic_vector(31 downto 0);
co : out std_ulogic
);
end component;
end multlib;
|
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package multlib is
component mul_17_17
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(16 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(33 downto 0)
);
end component;
component mul_33_9
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(8 downto 0);
p : out std_logic_vector(41 downto 0)
);
end component;
component mul_33_17
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(49 downto 0)
);
end component;
component mul_33_33
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(32 downto 0);
p : out std_logic_vector(65 downto 0)
);
end component;
component add32
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
ci : in std_ulogic;
s : out std_logic_vector(31 downto 0);
co : out std_ulogic
);
end component;
end multlib;
|
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package multlib is
component mul_17_17
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(16 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(33 downto 0)
);
end component;
component mul_33_9
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(8 downto 0);
p : out std_logic_vector(41 downto 0)
);
end component;
component mul_33_17
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(49 downto 0)
);
end component;
component mul_33_33
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(32 downto 0);
p : out std_logic_vector(65 downto 0)
);
end component;
component add32
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
ci : in std_ulogic;
s : out std_logic_vector(31 downto 0);
co : out std_ulogic
);
end component;
end multlib;
|
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package multlib is
component mul_17_17
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(16 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(33 downto 0)
);
end component;
component mul_33_9
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(8 downto 0);
p : out std_logic_vector(41 downto 0)
);
end component;
component mul_33_17
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(49 downto 0)
);
end component;
component mul_33_33
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(32 downto 0);
p : out std_logic_vector(65 downto 0)
);
end component;
component add32
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
ci : in std_ulogic;
s : out std_logic_vector(31 downto 0);
co : out std_ulogic
);
end component;
end multlib;
|
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package multlib is
component mul_17_17
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(16 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(33 downto 0)
);
end component;
component mul_33_9
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(8 downto 0);
p : out std_logic_vector(41 downto 0)
);
end component;
component mul_33_17
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(49 downto 0)
);
end component;
component mul_33_33
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(32 downto 0);
p : out std_logic_vector(65 downto 0)
);
end component;
component add32
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
ci : in std_ulogic;
s : out std_logic_vector(31 downto 0);
co : out std_ulogic
);
end component;
end multlib;
|
-----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package multlib is
component mul_17_17
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(16 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(33 downto 0)
);
end component;
component mul_33_9
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(8 downto 0);
p : out std_logic_vector(41 downto 0)
);
end component;
component mul_33_17
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(49 downto 0)
);
end component;
component mul_33_33
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(32 downto 0);
p : out std_logic_vector(65 downto 0)
);
end component;
component add32
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
ci : in std_ulogic;
s : out std_logic_vector(31 downto 0);
co : out std_ulogic
);
end component;
end multlib;
|
-- NEED RESULT: ARCH00568: Attribute declarations - composite static subtypes with static initial values passed
-- NEED RESULT: ARCH00568: Attribute declarations - scalar static subtypes with generic initial values failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00568
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.4 (1)
-- 4.4 (4)
-- 4.4 (6)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00568(ARCH00568)
-- ENT00568_Test_Bench(ARCH00568_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
--
entity ENT00568 is
generic (
i_bit_vector_1, i_bit_vector_2 : bit_vector
:= c_st_bit_vector_1 ;
i_string_1, i_string_2 : string
:= c_st_string_1 ;
i_t_rec1_1, i_t_rec1_2 : t_rec1
:= c_st_rec1_1 ;
i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
i_t_rec2_1, i_t_rec2_2 : t_rec2
:= c_st_rec2_1 ;
i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
i_t_rec3_1, i_t_rec3_2 : t_rec3
:= c_st_rec3_1 ;
i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
i_t_arr1_1, i_t_arr1_2 : t_arr1
:= c_st_arr1_1 ;
i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
i_t_arr2_1, i_t_arr2_2 : t_arr2
:= c_st_arr2_1 ;
i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
i_t_arr3_1, i_t_arr3_2 : t_arr3
:= c_st_arr3_1 ;
i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1
) ;
attribute at_bit_vector_1 : bit_vector ;
attribute at_string_1 : string ;
attribute at_t_rec1_1 : t_rec1 ;
attribute at_st_rec1_1 : st_rec1 ;
attribute at_t_rec2_1 : t_rec2 ;
attribute at_st_rec2_1 : st_rec2 ;
attribute at_t_rec3_1 : t_rec3 ;
attribute at_st_rec3_1 : st_rec3 ;
attribute at_t_arr1_1 : t_arr1 ;
attribute at_st_arr1_1 : st_arr1 ;
attribute at_t_arr2_1 : t_arr2 ;
attribute at_st_arr2_1 : st_arr2 ;
attribute at_t_arr3_1 : t_arr3 ;
attribute at_st_arr3_1 : st_arr3 ;
end ENT00568 ;
architecture ARCH00568 of ENT00568 is
begin
process
variable correct : boolean := true ;
procedure p1 ;
attribute at_bit_vector_1 of p1 : procedure is
c_st_bit_vector_1 ;
attribute at_string_1 of p1 : procedure is
c_st_string_1 ;
attribute at_t_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_st_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_t_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_st_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_t_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_st_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_t_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_st_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_t_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_st_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_t_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
attribute at_st_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
procedure p1 is
begin
correct := correct and p1'at_bit_vector_1
= c_st_bit_vector_1 ;
correct := correct and p1'at_string_1
= c_st_string_1 ;
correct := correct and p1'at_t_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_st_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_t_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_st_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_t_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_st_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_t_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_st_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_t_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_st_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_t_arr3_1
= c_st_arr3_1 ;
correct := correct and p1'at_st_arr3_1
= c_st_arr3_1 ;
test_report ( "ARCH00568" ,
"Attribute declarations - composite static subtypes"
& " with static initial values" ,
correct) ;
end p1 ;
begin
p1 ;
wait ;
end process ;
process
variable correct : boolean := true ;
procedure p1 ;
attribute at_bit_vector_1 of p1 : procedure is
i_bit_vector_1 ;
attribute at_string_1 of p1 : procedure is
i_string_1 ;
attribute at_t_rec1_1 of p1 : procedure is
i_t_rec1_1 ;
attribute at_st_rec1_1 of p1 : procedure is
i_st_rec1_1 ;
attribute at_t_rec2_1 of p1 : procedure is
i_t_rec2_1 ;
attribute at_st_rec2_1 of p1 : procedure is
i_st_rec2_1 ;
attribute at_t_rec3_1 of p1 : procedure is
i_t_rec3_1 ;
attribute at_st_rec3_1 of p1 : procedure is
i_st_rec3_1 ;
attribute at_t_arr1_1 of p1 : procedure is
i_t_arr1_1 ;
attribute at_st_arr1_1 of p1 : procedure is
i_st_arr1_1 ;
attribute at_t_arr2_1 of p1 : procedure is
i_t_arr2_1 ;
attribute at_st_arr2_1 of p1 : procedure is
i_st_arr2_1 ;
attribute at_t_arr3_1 of p1 : procedure is
i_t_arr3_1 ;
attribute at_st_arr3_1 of p1 : procedure is
i_st_arr3_1 ;
procedure p1 is
begin
correct := correct and p1'at_bit_vector_1
= c_st_bit_vector_1 ;
correct := correct and p1'at_string_1
= c_st_string_1 ;
correct := correct and p1'at_t_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_st_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_t_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_st_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_t_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_st_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_t_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_st_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_t_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_st_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_t_arr3_1
= c_st_arr3_1 ;
correct := correct and p1'at_st_arr3_1
= c_st_arr3_1 ;
test_report ( "ARCH00568" ,
"Attribute declarations - scalar static subtypes"
& " with generic initial values" ,
correct) ;
end p1 ;
begin
p1 ;
wait ;
end process ;
end ARCH00568 ;
--
entity ENT00568_Test_Bench is
end ENT00568_Test_Bench ;
--
architecture ARCH00568_Test_Bench of ENT00568_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00568 ( ARCH00568 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00568_Test_Bench ;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_rst_module.vhd
-- Description: This entity is the top level reset module entity for the
-- AXI VDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
entity axi_dma_rst_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000
-- Scatter Gather clock frequency in hertz
);
port (
-----------------------------------------------------------------------
-- Clock Sources
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ;
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_s2mm_aclk : in std_logic ; --
--
----------------------------------------------------------------------- --
-- Hard Reset --
----------------------------------------------------------------------- --
axi_resetn : in std_logic ; --
----------------------------------------------------------------------- --
-- Soft Reset --
----------------------------------------------------------------------- --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- MM2S Soft Reset Support --
----------------------------------------------------------------------- --
mm2s_all_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_halt : out std_logic := '0' ; --
mm2s_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- S2MM Soft Reset Support --
----------------------------------------------------------------------- --
s2mm_all_idle : in std_logic ; --
s2mm_stop : in std_logic ; --
s2mm_halt : out std_logic := '0' ; --
s2mm_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- MM2S Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_mm2s_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_mm2s_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
mm2s_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
mm2s_cntrl_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
mm2s_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
mm2s_prmry_resetn : out std_logic := '1' ; --
--
--
----------------------------------------------------------------------- --
-- S2MM Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_s2mm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_s2mm_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
s2mm_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
s2mm_sts_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
s2mm_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
s2mm_prmry_resetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Scatter Gather Distributed Reset Out
----------------------------------------------------------------------- --
-- AXI Scatter Gather Reset Out
m_axi_sg_aresetn : out std_logic := '1' ; --
-- AXI Scatter Gather Datamover Reset Out
dm_m_axi_sg_aresetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Hard Reset Out --
----------------------------------------------------------------------- --
m_axi_sg_hrdresetn : out std_logic := '1' ; --
s_axi_lite_resetn : out std_logic := '1' --
);
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of s_axi_lite_resetn : signal is "TRUE";
Attribute KEEP of m_axi_sg_hrdresetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of s_axi_lite_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of m_axi_sg_hrdresetn : signal is "no";
end axi_dma_rst_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_rst_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
ATTRIBUTE async_reg : STRING;
signal hrd_resetn_i_cdc_tig : std_logic := '1';
signal hrd_resetn_i_d1_cdc_tig : std_logic := '1';
--ATTRIBUTE async_reg OF hrd_resetn_i_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF hrd_resetn_i_d1_cdc_tig : SIGNAL IS "true";
-- Soft reset support
signal mm2s_soft_reset_clr : std_logic := '0';
signal s2mm_soft_reset_clr : std_logic := '0';
signal soft_reset_clr_i : std_logic := '0';
signal mm2s_soft_reset_done : std_logic := '0';
signal s2mm_soft_reset_done : std_logic := '0';
signal mm2s_scndry_resetn_i : std_logic := '0';
signal s2mm_scndry_resetn_i : std_logic := '0';
signal dm_mm2s_scndry_resetn_i : std_logic := '0';
signal dm_s2mm_scndry_resetn_i : std_logic := '0';
signal sg_hard_reset : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Register hard reset in
REG_HRD_RST : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => sg_hard_reset,
scndry_vect_out => open
);
m_axi_sg_hrdresetn <= sg_hard_reset;
--REG_HRD_RST : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- hrd_resetn_i_cdc_tig <= axi_resetn;
-- m_axi_sg_hrdresetn <= hrd_resetn_i_cdc_tig;
-- end if;
-- end process REG_HRD_RST;
-- Regsiter hard reset out for axi lite interface
REG_HRD_RST_OUT : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s_axi_lite_resetn,
scndry_vect_out => open
);
--REG_HRD_RST_OUT : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- hrd_resetn_i_d1_cdc_tig <= hrd_resetn_i_cdc_tig;
-- s_axi_lite_resetn <= hrd_resetn_i_d1_cdc_tig;
-- end if;
-- end process REG_HRD_RST_OUT;
dm_mm2s_scndry_resetn <= dm_mm2s_scndry_resetn_i;
dm_s2mm_scndry_resetn <= dm_s2mm_scndry_resetn_i;
-- mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface (default)
MAP_SG_FOR_BOTH : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 1 generate
begin
-- both must be low before sg reset is asserted.
m_axi_sg_aresetn <= mm2s_scndry_resetn_i or s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i or dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_BOTH;
-- Only s2mm channel included therefore map secondary resets to
-- from s2mm reset module to scatter gather interface
MAP_SG_FOR_S2MM : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 1 generate
begin
m_axi_sg_aresetn <= s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_S2MM;
-- Only mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface
MAP_SG_FOR_MM2S : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= mm2s_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i;
end generate MAP_SG_FOR_MM2S;
-- Invalid configuration for axi dma - simply here for completeness
MAP_NO_SG : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= '1';
dm_m_axi_sg_aresetn <= '1';
end generate MAP_NO_SG;
s2mm_scndry_resetn <= s2mm_scndry_resetn_i;
mm2s_scndry_resetn <= mm2s_scndry_resetn_i;
-- Generate MM2S reset signals
GEN_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
RESET_I : entity axi_dma_v7_1_10.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_mm2s_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => mm2s_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => mm2s_all_idle ,
stop => mm2s_stop ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
-- Secondary Reset
scndry_resetn => mm2s_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => mm2s_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_mm2s_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_mm2s_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => mm2s_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => mm2s_cntrl_reset_out_n
);
-- Sample an hold mm2s soft reset done to use in
-- combined reset done to DMACR
MM2S_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
mm2s_soft_reset_done <= '0';
elsif(mm2s_soft_reset_clr = '1')then
mm2s_soft_reset_done <= '1';
end if;
end if;
end process MM2S_SOFT_RST_DONE;
end generate GEN_RESET_FOR_MM2S;
-- No MM2S therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_prmry_reset_out_n <= '1';
mm2s_cntrl_reset_out_n <= '1';
dm_mm2s_scndry_resetn_i <= '1';
dm_mm2s_prmry_resetn <= '1';
mm2s_prmry_resetn <= '1';
mm2s_scndry_resetn_i <= '1';
mm2s_halt <= '0';
mm2s_soft_reset_clr <= '0';
mm2s_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_MM2S;
-- Generate S2MM reset signals
GEN_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
RESET_I : entity axi_dma_v7_1_10.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_s2mm_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => s2mm_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => s2mm_all_idle ,
stop => s2mm_stop ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
-- Secondary Reset
scndry_resetn => s2mm_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => s2mm_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_s2mm_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_s2mm_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => s2mm_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => s2mm_sts_reset_out_n
);
-- Sample an hold s2mm soft reset done to use in
-- combined reset done to DMACR
S2MM_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
s2mm_soft_reset_done <= '0';
elsif(s2mm_soft_reset_clr = '1')then
s2mm_soft_reset_done <= '1';
end if;
end if;
end process S2MM_SOFT_RST_DONE;
end generate GEN_RESET_FOR_S2MM;
-- No SsMM therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_prmry_reset_out_n <= '1';
dm_s2mm_scndry_resetn_i <= '1';
dm_s2mm_prmry_resetn <= '1';
s2mm_prmry_resetn <= '1';
s2mm_scndry_resetn_i <= '1';
s2mm_halt <= '0';
s2mm_soft_reset_clr <= '0';
s2mm_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_S2MM;
-- When both mm2s and s2mm are done then drive soft reset clear and
-- also clear s_h registers above
soft_reset_clr_i <= s2mm_soft_reset_done and mm2s_soft_reset_done;
soft_reset_clr <= soft_reset_clr_i;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
library work;
use work.pkg_6502_opcodes.all;
use work.pkg_6502_decode.all;
use work.File_IO_pkg.all;
entity tb_data_oper is
end tb_data_oper;
architecture tb of tb_data_oper is
signal inst : std_logic_vector(7 downto 0);
signal n_in : std_logic := 'Z';
signal v_in : std_logic;
signal z_in : std_logic;
signal c_in : std_logic := 'U';
signal d_in : std_logic := 'U';
signal i_in : std_logic;
signal data_in : std_logic_vector(7 downto 0) := X"55";
signal a_reg : std_logic_vector(7 downto 0) := X"33";
signal x_reg : std_logic_vector(7 downto 0) := X"AB";
signal y_reg : std_logic_vector(7 downto 0) := X"CD";
signal s_reg : std_logic_vector(7 downto 0) := X"EF";
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal opcode : string(1 to 13);
begin
mut: entity work.data_oper
generic map (
support_bcd => true )
port map (
inst => inst,
n_in => n_in,
v_in => v_in,
z_in => z_in,
c_in => c_in,
d_in => d_in,
i_in => i_in,
data_in => data_in,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
process
procedure write_str(variable L : inout line; s : string) is
begin
write(L, s);
end procedure;
variable L : line;
begin
for i in 0 to 255 loop
c_in <= 'U';
d_in <= 'U';
inst <= conv_std_logic_vector(i, 8);
opcode <= opcode_array(i);
wait for 1 us;
write(L, VecToHex(inst, 2));
write(L, ' ');
write(L, opcode_array(i));
write(L, ':');
if(n_out /= 'Z') then write(L, 'N'); else write(L, '-'); end if;
if(v_out /= 'U') then write(L, 'V'); else write(L, '-'); end if;
if(z_out /= 'U') then write(L, 'Z'); else write(L, '-'); end if;
if(c_out /= 'U') then write(L, 'C'); else write(L, '-'); end if;
if(d_out /= 'U') then write(L, 'D'); else write(L, '-'); end if;
if(i_out /= 'U') then write(L, 'I'); else write(L, '-'); end if;
c_in <= '0';
d_in <= '0';
wait for 1 us;
write(L, ' ');
if store_a_from_alu(inst) then
write_str(L, "Store ALU in A ");
end if;
if load_x(inst) then
write_str(L, "Store ALU in X ");
end if;
if load_y(inst) then
write_str(L, "Store ALU in Y ");
end if;
if(set_a='1') then
write_str(L, "A:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_x='1') then
write_str(L, "X:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_y='1') then
write_str(L, "Y:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_s='1') then
write_str(L, "SP:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
write_str(L, " ALU: " & VecToHex(alu_out, 2));
write_str(L, "; MEM: " & VecToHex(alu_out, 2));
writeline(output, L);
end loop;
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
library work;
use work.pkg_6502_opcodes.all;
use work.pkg_6502_decode.all;
use work.File_IO_pkg.all;
entity tb_data_oper is
end tb_data_oper;
architecture tb of tb_data_oper is
signal inst : std_logic_vector(7 downto 0);
signal n_in : std_logic := 'Z';
signal v_in : std_logic;
signal z_in : std_logic;
signal c_in : std_logic := 'U';
signal d_in : std_logic := 'U';
signal i_in : std_logic;
signal data_in : std_logic_vector(7 downto 0) := X"55";
signal a_reg : std_logic_vector(7 downto 0) := X"33";
signal x_reg : std_logic_vector(7 downto 0) := X"AB";
signal y_reg : std_logic_vector(7 downto 0) := X"CD";
signal s_reg : std_logic_vector(7 downto 0) := X"EF";
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal opcode : string(1 to 13);
begin
mut: entity work.data_oper
generic map (
support_bcd => true )
port map (
inst => inst,
n_in => n_in,
v_in => v_in,
z_in => z_in,
c_in => c_in,
d_in => d_in,
i_in => i_in,
data_in => data_in,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
process
procedure write_str(variable L : inout line; s : string) is
begin
write(L, s);
end procedure;
variable L : line;
begin
for i in 0 to 255 loop
c_in <= 'U';
d_in <= 'U';
inst <= conv_std_logic_vector(i, 8);
opcode <= opcode_array(i);
wait for 1 us;
write(L, VecToHex(inst, 2));
write(L, ' ');
write(L, opcode_array(i));
write(L, ':');
if(n_out /= 'Z') then write(L, 'N'); else write(L, '-'); end if;
if(v_out /= 'U') then write(L, 'V'); else write(L, '-'); end if;
if(z_out /= 'U') then write(L, 'Z'); else write(L, '-'); end if;
if(c_out /= 'U') then write(L, 'C'); else write(L, '-'); end if;
if(d_out /= 'U') then write(L, 'D'); else write(L, '-'); end if;
if(i_out /= 'U') then write(L, 'I'); else write(L, '-'); end if;
c_in <= '0';
d_in <= '0';
wait for 1 us;
write(L, ' ');
if store_a_from_alu(inst) then
write_str(L, "Store ALU in A ");
end if;
if load_x(inst) then
write_str(L, "Store ALU in X ");
end if;
if load_y(inst) then
write_str(L, "Store ALU in Y ");
end if;
if(set_a='1') then
write_str(L, "A:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_x='1') then
write_str(L, "X:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_y='1') then
write_str(L, "Y:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_s='1') then
write_str(L, "SP:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
write_str(L, " ALU: " & VecToHex(alu_out, 2));
write_str(L, "; MEM: " & VecToHex(alu_out, 2));
writeline(output, L);
end loop;
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
library work;
use work.pkg_6502_opcodes.all;
use work.pkg_6502_decode.all;
use work.File_IO_pkg.all;
entity tb_data_oper is
end tb_data_oper;
architecture tb of tb_data_oper is
signal inst : std_logic_vector(7 downto 0);
signal n_in : std_logic := 'Z';
signal v_in : std_logic;
signal z_in : std_logic;
signal c_in : std_logic := 'U';
signal d_in : std_logic := 'U';
signal i_in : std_logic;
signal data_in : std_logic_vector(7 downto 0) := X"55";
signal a_reg : std_logic_vector(7 downto 0) := X"33";
signal x_reg : std_logic_vector(7 downto 0) := X"AB";
signal y_reg : std_logic_vector(7 downto 0) := X"CD";
signal s_reg : std_logic_vector(7 downto 0) := X"EF";
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal opcode : string(1 to 13);
begin
mut: entity work.data_oper
generic map (
support_bcd => true )
port map (
inst => inst,
n_in => n_in,
v_in => v_in,
z_in => z_in,
c_in => c_in,
d_in => d_in,
i_in => i_in,
data_in => data_in,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
process
procedure write_str(variable L : inout line; s : string) is
begin
write(L, s);
end procedure;
variable L : line;
begin
for i in 0 to 255 loop
c_in <= 'U';
d_in <= 'U';
inst <= conv_std_logic_vector(i, 8);
opcode <= opcode_array(i);
wait for 1 us;
write(L, VecToHex(inst, 2));
write(L, ' ');
write(L, opcode_array(i));
write(L, ':');
if(n_out /= 'Z') then write(L, 'N'); else write(L, '-'); end if;
if(v_out /= 'U') then write(L, 'V'); else write(L, '-'); end if;
if(z_out /= 'U') then write(L, 'Z'); else write(L, '-'); end if;
if(c_out /= 'U') then write(L, 'C'); else write(L, '-'); end if;
if(d_out /= 'U') then write(L, 'D'); else write(L, '-'); end if;
if(i_out /= 'U') then write(L, 'I'); else write(L, '-'); end if;
c_in <= '0';
d_in <= '0';
wait for 1 us;
write(L, ' ');
if store_a_from_alu(inst) then
write_str(L, "Store ALU in A ");
end if;
if load_x(inst) then
write_str(L, "Store ALU in X ");
end if;
if load_y(inst) then
write_str(L, "Store ALU in Y ");
end if;
if(set_a='1') then
write_str(L, "A:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_x='1') then
write_str(L, "X:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_y='1') then
write_str(L, "Y:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_s='1') then
write_str(L, "SP:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
write_str(L, " ALU: " & VecToHex(alu_out, 2));
write_str(L, "; MEM: " & VecToHex(alu_out, 2));
writeline(output, L);
end loop;
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
library work;
use work.pkg_6502_opcodes.all;
use work.pkg_6502_decode.all;
use work.File_IO_pkg.all;
entity tb_data_oper is
end tb_data_oper;
architecture tb of tb_data_oper is
signal inst : std_logic_vector(7 downto 0);
signal n_in : std_logic := 'Z';
signal v_in : std_logic;
signal z_in : std_logic;
signal c_in : std_logic := 'U';
signal d_in : std_logic := 'U';
signal i_in : std_logic;
signal data_in : std_logic_vector(7 downto 0) := X"55";
signal a_reg : std_logic_vector(7 downto 0) := X"33";
signal x_reg : std_logic_vector(7 downto 0) := X"AB";
signal y_reg : std_logic_vector(7 downto 0) := X"CD";
signal s_reg : std_logic_vector(7 downto 0) := X"EF";
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal opcode : string(1 to 13);
begin
mut: entity work.data_oper
generic map (
support_bcd => true )
port map (
inst => inst,
n_in => n_in,
v_in => v_in,
z_in => z_in,
c_in => c_in,
d_in => d_in,
i_in => i_in,
data_in => data_in,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
process
procedure write_str(variable L : inout line; s : string) is
begin
write(L, s);
end procedure;
variable L : line;
begin
for i in 0 to 255 loop
c_in <= 'U';
d_in <= 'U';
inst <= conv_std_logic_vector(i, 8);
opcode <= opcode_array(i);
wait for 1 us;
write(L, VecToHex(inst, 2));
write(L, ' ');
write(L, opcode_array(i));
write(L, ':');
if(n_out /= 'Z') then write(L, 'N'); else write(L, '-'); end if;
if(v_out /= 'U') then write(L, 'V'); else write(L, '-'); end if;
if(z_out /= 'U') then write(L, 'Z'); else write(L, '-'); end if;
if(c_out /= 'U') then write(L, 'C'); else write(L, '-'); end if;
if(d_out /= 'U') then write(L, 'D'); else write(L, '-'); end if;
if(i_out /= 'U') then write(L, 'I'); else write(L, '-'); end if;
c_in <= '0';
d_in <= '0';
wait for 1 us;
write(L, ' ');
if store_a_from_alu(inst) then
write_str(L, "Store ALU in A ");
end if;
if load_x(inst) then
write_str(L, "Store ALU in X ");
end if;
if load_y(inst) then
write_str(L, "Store ALU in Y ");
end if;
if(set_a='1') then
write_str(L, "A:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_x='1') then
write_str(L, "X:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_y='1') then
write_str(L, "Y:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_s='1') then
write_str(L, "SP:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
write_str(L, " ALU: " & VecToHex(alu_out, 2));
write_str(L, "; MEM: " & VecToHex(alu_out, 2));
writeline(output, L);
end loop;
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
library work;
use work.pkg_6502_opcodes.all;
use work.pkg_6502_decode.all;
use work.File_IO_pkg.all;
entity tb_data_oper is
end tb_data_oper;
architecture tb of tb_data_oper is
signal inst : std_logic_vector(7 downto 0);
signal n_in : std_logic := 'Z';
signal v_in : std_logic;
signal z_in : std_logic;
signal c_in : std_logic := 'U';
signal d_in : std_logic := 'U';
signal i_in : std_logic;
signal data_in : std_logic_vector(7 downto 0) := X"55";
signal a_reg : std_logic_vector(7 downto 0) := X"33";
signal x_reg : std_logic_vector(7 downto 0) := X"AB";
signal y_reg : std_logic_vector(7 downto 0) := X"CD";
signal s_reg : std_logic_vector(7 downto 0) := X"EF";
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal opcode : string(1 to 13);
begin
mut: entity work.data_oper
generic map (
support_bcd => true )
port map (
inst => inst,
n_in => n_in,
v_in => v_in,
z_in => z_in,
c_in => c_in,
d_in => d_in,
i_in => i_in,
data_in => data_in,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
process
procedure write_str(variable L : inout line; s : string) is
begin
write(L, s);
end procedure;
variable L : line;
begin
for i in 0 to 255 loop
c_in <= 'U';
d_in <= 'U';
inst <= conv_std_logic_vector(i, 8);
opcode <= opcode_array(i);
wait for 1 us;
write(L, VecToHex(inst, 2));
write(L, ' ');
write(L, opcode_array(i));
write(L, ':');
if(n_out /= 'Z') then write(L, 'N'); else write(L, '-'); end if;
if(v_out /= 'U') then write(L, 'V'); else write(L, '-'); end if;
if(z_out /= 'U') then write(L, 'Z'); else write(L, '-'); end if;
if(c_out /= 'U') then write(L, 'C'); else write(L, '-'); end if;
if(d_out /= 'U') then write(L, 'D'); else write(L, '-'); end if;
if(i_out /= 'U') then write(L, 'I'); else write(L, '-'); end if;
c_in <= '0';
d_in <= '0';
wait for 1 us;
write(L, ' ');
if store_a_from_alu(inst) then
write_str(L, "Store ALU in A ");
end if;
if load_x(inst) then
write_str(L, "Store ALU in X ");
end if;
if load_y(inst) then
write_str(L, "Store ALU in Y ");
end if;
if(set_a='1') then
write_str(L, "A:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_x='1') then
write_str(L, "X:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_y='1') then
write_str(L, "Y:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_s='1') then
write_str(L, "SP:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
write_str(L, " ALU: " & VecToHex(alu_out, 2));
write_str(L, "; MEM: " & VecToHex(alu_out, 2));
writeline(output, L);
end loop;
wait;
end process;
end tb;
|
entity ent is
end ent;
architecture behav of ent is
signal s : bit;
begin
s <= not s;
end behav;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:15:05 01/29/2014
-- Design Name:
-- Module Name: FloatingPointMul23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FloatingPointMul23 is
PORT (
a_in : in STD_LOGIC_VECTOR(22 downto 0);
b_in : in STD_LOGIC_VECTOR(22 downto 0);
res_out : out STD_LOGIC_VECTOR(22 downto 0);
sign : out STD_LOGIC;
zero : out STD_LOGIC;
overflow : out STD_LOGIC;
underflow : out STD_LOGIC
);
end FloatingPointMul23;
architecture Behavioral of FloatingPointMul23 is
COMPONENT Multiply16Booth4 is
PORT (
a: IN STD_LOGIC_VECTOR(15 downto 0);
b: IN STD_LOGIC_VECTOR(15 downto 0);
o: OUT STD_LOGIC_VECTOR(15 downto 0));
end COMPONENT;
COMPONENT CSA8 is
generic (width : integer := 32);
Port ( a : in STD_LOGIC_VECTOR (width-1 downto 0);
b : in STD_LOGIC_VECTOR (width-1 downto 0);
o : out STD_LOGIC_VECTOR (width-1 downto 0);
cout : out STD_LOGIC);
end COMPONENT;
SIGNAL tmp_mA : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL tmp_mB : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL mul_t : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL add_t : STD_LOGIC_VECTOR(9 downto 0);
SIGNAL add_t2 : STD_LOGIC_VECTOR(9 downto 0);
SIGNAL bias_normalized : unsigned(9 downto 0);
SIGNAL a_zero : STD_LOGIC;
SIGNAL b_zero : STD_LOGIC;
SIGNAL output : STD_LOGIC_VECTOR(22 downto 0);
CONSTANT C_M127 : unsigned(9 downto 0) := to_unsigned(127, 10);
CONSTANT C_M126 : unsigned(9 downto 0) := to_unsigned(126, 10);
begin
tmp_mA <= "01" & a_in(13 downto 0);
tmp_mB <= "01" & b_in(13 downto 0);
multiplier_i : Multiply16Booth4 PORT MAP (
a =>tmp_mA,
b => tmp_mB,
o => mul_t
);
exponent_i : CSA8 GENERIC MAP (
width => 8
)
PORT MAP (
a => a_in(21 downto 14),
b => b_in(21 downto 14),
o => add_t(7 downto 0),
cout => add_t(8)
);
add_t(9) <= '0';
bias_normalized(9 downto 0) <= C_M126 when mul_t(15) = '1' else
C_M127;
add_t2 <= std_logic_vector(unsigned(add_t) - bias_normalized);
a_zero <= '1' when a_in(21 downto 0) = "0000000000000000000000" else
'0';
b_zero <= '1' when b_in(21 downto 0) = "0000000000000000000000" else
'0';
output(13 downto 0) <= "00000000000000" when a_zero = '1' or b_zero = '1' else
mul_t(14 downto 1) when mul_t(15) = '1' else
mul_t(13 downto 0);
output(21 downto 14) <= "00000000" when a_zero = '1' or b_zero = '1' else
add_t2(7 downto 0);
output(22) <= '0' when a_zero = '1' or b_zero = '1' else
a_in(22) xor b_in(22);
sign <= a_in(22) xor b_in(22);
zero <= '1' when output(21 downto 0) = "0000000000000000000000" else
'0';
overflow <= '1' when add_t2(9 downto 8) = "01" else
'0';
underflow <= '1' when add_t2(9 downto 8) = "11" else
'0';
res_out <= output;
end Behavioral; |
-------------------------------------------------------------------------------
--
-- File: ConfigADC.vhd
-- Author: Tudor Gherman, Robert Bocos
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module writes an intial configuration into the ADC registers and then
-- manages the optional SPI Indirect Access Port.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.PkgZmodDigitizer.all;
entity ConfigADC is
Generic (
-- Parameter identifying the Zmod:
-- 6 -> Zmod Digitizer 1430 - 125 (AD9648)
kZmodID : integer range 6 to 6 := 6;
-- ADC Clock divider ratio (Register 0x0B of AD96xx and AD92xx).
kADC_ClkDiv : integer range 1 to 8 := 1;
--The number of data bits for the data phase of the SPI transaction:
--only 8 data bits currently supported.
kDataWidth : integer range 8 to 8 := 8;
--The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 16 to 16 := 16;
kSimulation : boolean := false
);
Port (
-- 100MHZ clock input.
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain).
asRst_n : in STD_LOGIC;
-- ADC initialization complete signaling
sInitDoneADC : out STD_LOGIC := '0';
-- ADC initialization error signaling
sConfigError : out STD_LOGIC;
-- ADC initialization enable signal
--Configuration of the ADC over SPI should be done after sConfigADCEnable is asserted which only happens after the CDCE clock generator is configured
--and the PLL inside the CDCE is locked, otherwise the ADC should be kept in reset
sConfigADCEnable : in STD_LOGIC;
--AD9648 SPI interface signals
sADC_Sclk : out STD_LOGIC;
sADC_SDIO : inout STD_LOGIC;
sADC_CS : out STD_LOGIC := '1';
-- SPI Indirect access port; it provides the means to indirectly access
-- the ADC registers. It is designed to interface with 2 AXI StreamFIFOs,
-- one that stores commands to be transmitted and one to store the received data.
sCmdTxAxisTvalid: IN STD_LOGIC;
sCmdTxAxisTready: OUT STD_LOGIC;
sCmdTxAxisTdata: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
sCmdRxAxisTvalid: OUT STD_LOGIC;
sCmdRxAxisTready: IN STD_LOGIC;
sCmdRxAxisTdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end ConfigADC;
architecture Behavioral of ConfigADC is
signal sCurrentState : FsmStatesADC_t := StStart;
signal sNextState : FsmStatesADC_t;
-- signals used for debug purposes
-- signal fsmcfg_state, fsmcfg_state_r : std_logic_vector(5 downto 0);
--External Command FIFO Interface
signal sLdCmdTxData: std_logic;
signal sCmdTxDataReg: std_logic_vector(23 downto 0);
signal sCmdTxAxisTreadyLoc: std_logic;
signal sCmdRxAxisTvalidLoc: std_logic;
signal sCmdRxAxisTdataLoc : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal sCmdCnt : unsigned(4 downto 0);
signal sCmdCntInt : integer range 0 to 31;
signal sIncCmdCnt, sRstCmdCnt : std_logic;
--Initialization complete and configuration error flags
signal sInitDoneADC_Fsm : std_logic := '0';
signal sConfigErrorFsm : std_logic;
--Timers
signal sCfgTimer : unsigned (kCountResetResume'range);
signal sCfgTimerRst_n : std_logic;
--SPI Interface
signal sADC_SPI_RdData : std_logic_vector(kDataWidth-1 downto 0);
signal sADC_SPI_Done : std_logic;
signal sADC_SPI_WrData, sADC_SPI_WrDataR : std_logic_vector(kDataWidth-1 downto 0);
signal sADC_SPI_Addr, sADC_SPI_AddrR : std_logic_vector(kCommandWidth - 4 downto 0);
signal sADC_SPI_Width, sADC_SPI_WidthR : std_logic_vector(1 downto 0);
signal sADC_SPI_RdWr, sADC_SPI_RdWrR : std_logic;
signal sADC_SPI_Busy : std_logic;
signal sADC_ApStart, sADC_ApStartR : std_logic;
signal sCountResetResumeVal : unsigned(kCountResetResume'range);
constant kCmdTotal : integer := SelCmdWrListLength(kZmodID);
constant kADC_SPI_CmdDef : ADC_SPI_Commands_t := SelCmdList(kZmodID);
constant kADC_SPI_RdbckDef : ADC_SPI_Readback_t := SelRdbkList(kZmodID);
constant kADC_SPI_Cmd : ADC_SPI_Commands_t := OverwriteClkDiv(kADC_SPI_CmdDef, kADC_ClkDiv);
constant kADC_SPI_Rdbck : ADC_SPI_Readback_t := OverWriteID_ClkDiv(kZmodID, kADC_SPI_RdbckDef, kADC_ClkDiv);
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of sCurrentState, sNextState : signal is "TRUE";
begin
sCountResetResumeVal <= kCountResetResumeSim when kSimulation else
kCountResetResume;
-- Instantiate the SPI controller.
ADC_SPI_inst: entity work.ADI_SPI
Generic Map(
kSysClkDiv => kSPI_SysClkDiv,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map(
--
SysClk100 => SysClk100,
asRst_n => asRst_n,
sSPI_Clk => sADC_Sclk,
sSDIO => sADC_SDIO,
sCS => sADC_CS,
sApStart => sADC_ApStartR,
sRdData => sADC_SPI_RdData,
sWrData => sADC_SPI_WrDataR,
sAddr => sADC_SPI_AddrR,
sWidth => sADC_SPI_WidthR, --tested only for width = "00"
sRdWr => sADC_SPI_RdWrR,
sDone => sADC_SPI_Done,
sBusy => sADC_SPI_Busy
);
-- Register the SPI controller inputs.
ProcSPI_ControllerRegister: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sADC_SPI_RdWrR <= '0';
sADC_SPI_WrDataR <= (others => '0');
sADC_SPI_AddrR <= (others => '0');
sADC_SPI_WidthR <= (others => '0');
sADC_ApStartR <= '0';
elsif (rising_edge(SysClk100)) then
sADC_SPI_RdWrR <= sADC_SPI_RdWr;
sADC_SPI_WrDataR <= sADC_SPI_WrData;
sADC_SPI_AddrR <= sADC_SPI_Addr;
sADC_SPI_WidthR <= sADC_SPI_Width;
sADC_ApStartR <= sADC_ApStart;
end if;
end process;
sCmdCntInt <= to_integer(sCmdCnt);
-- Register the SPI Indirect Access Port receive interface outputs.
ProcRxExtFIFO_Reg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdRxAxisTvalid <= '0';
sCmdRxAxisTdata <= (others => '0');
elsif (rising_edge(SysClk100)) then
sCmdRxAxisTvalid <= sCmdRxAxisTvalidLoc;
sCmdRxAxisTdata <= x"000000" & sCmdRxAxisTdataLoc;
end if;
end process;
-- Register the SPI Indirect Access Port transmit interface outputs.
ProcCmdAxisTreadyReg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdTxAxisTready <= '0';
elsif (rising_edge(SysClk100)) then
sCmdTxAxisTready <= sCmdTxAxisTreadyLoc;
end if;
end process;
-- Register the next SPI Indirect Access Port command on the transmit
-- interface when the configuration state machine is capable of processing it.
ProcLdCmdTxData: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdTxDataReg <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sLdCmdTxData = '1') then
sCmdTxDataReg <= sCmdTxAxisTdata(23 downto 0);
end if;
end if;
end process;
-- Timer used to determine timeout conditions for SPI transfers.
-- When a command is sent to the ADC a certain amount of time is allowed for the state
-- machine to read back the expected value in order to make sure the register was correctly
-- configured. Some commands do not take effect immediately, so this mechanism is necessary
-- (SPI Port Config register (address 0x00) soft reset write for example).
ProcCfgTimer: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCfgTimer <= (others =>'0');
elsif (rising_edge(SysClk100)) then
if (sCfgTimerRst_n = '0') then
sCfgTimer <= (others =>'0');
else
sCfgTimer <= sCfgTimer + 1;
end if;
end if;
end process;
-- Counter used to track the number of successfully sent commands.
ProcCmdCounter: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdCnt <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sRstCmdCnt = '0') then
sCmdCnt <= (others => '0');
elsif (sIncCmdCnt = '1') then
sCmdCnt <= sCmdCnt + 1;
end if;
end if;
end process;
-- Register FSM output flags.
ProcInitDoneReg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sInitDoneADC <= '0';
sConfigError <= '0';
elsif (rising_edge(SysClk100)) then
sInitDoneADC <= sInitDoneADC_Fsm;
sConfigError <= sConfigErrorFsm;
end if;
end process;
------------------------------------------------------------------------------------------
-- ADC Configuration state machine
------------------------------------------------------------------------------------------
-- State machine synchronous process.
ProcSyncFsm: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCurrentState <= StStart;
--fsmcfg_state_r <= (others => '0');
elsif (rising_edge(SysClk100)) then
sCurrentState <= sNextState;
--fsmcfg_state_r <= fsmcfg_state;
end if;
end process;
-- Next state and output decode.
ProcNextStateAndOutputDecode: process (sCurrentState, sADC_SPI_RdData, sADC_SPI_Done, sADC_SPI_Busy,
sCmdTxAxisTvalid, sCmdTxAxisTdata, sCmdTxDataReg, sCmdRxAxisTready, sCmdCntInt, sCfgTimer, sConfigADCEnable,
sCountResetResumeVal)
begin
sNextState <= sCurrentState;
--fsmcfg_state <= "000000";
sADC_ApStart <= '0';
sADC_SPI_WrData <= (others => '0');
sADC_SPI_Addr <= (others => '0');
sADC_SPI_Width <= (others => '0');
sADC_SPI_RdWr <= '0';
sRstCmdCnt <= '0';
sIncCmdCnt <= '0';
sLdCmdTxData <= '0';
sCfgTimerRst_n <= '0';
sInitDoneADC_Fsm <= '0';
sConfigErrorFsm <= '0';
sCmdTxAxisTreadyLoc <= '0';
sCmdRxAxisTvalidLoc <= '0';
sCmdRxAxisTdataLoc <= (others => '0');
case (sCurrentState) is
when StStart =>
--fsmcfg_state <= "000000";
if (sConfigADCEnable = '1') then
sNextState <= StWriteControlReg;
end if;
-- Perform a register write operation for the sCmdCntInt'th command in the queue.
-- For some sCmdCntInt only register reads are required.
when StWriteControlReg =>
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
--fsmcfg_state <= "000001";
if (kADC_SPI_Cmd(sCmdCntInt)(20 downto 8) = kChipID) then --Read ID skips register write
sNextState <= StReadControlReg;
elsif (sADC_SPI_Busy = '0') then
sADC_ApStart <= '1';
sADC_SPI_WrData <= kADC_SPI_Cmd(sCmdCntInt)(7 downto 0);
sADC_SPI_Addr <= kADC_SPI_Cmd(sCmdCntInt)(20 downto 8);
sADC_SPI_Width <= kADC_SPI_Cmd(sCmdCntInt)(22 downto 21);
sADC_SPI_RdWr <= '0';
sNextState <= StWaitDoneWriteReg;
end if;
-- Wait for register write command to be completed
when StWaitDoneWriteReg =>
--fsmcfg_state <= "000010";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Done = '1') then
-- AD92xx devices require a Transfer register write operation
-- for the previous register write to take effect.
if ((kZmodID = kZmodDigitizer1030_40) or (kZmodID = kZmodDigitizer1230_40) or (kZmodID = kZmodDigitizer1430_40)) then
sNextState <= StReadTrsfReg;
else
sNextState <= StReadControlReg;
end if;
end if;
-- Read Transfer register and check if it is cleared.
when StReadTrsfReg =>
--fsmcfg_state <= "101110";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Busy = '0') then
sADC_ApStart <= '1';
sADC_SPI_Addr <= kSetTrsfReg(20 downto 8);
sADC_SPI_Width <= kSetTrsfReg(22 downto 21);
sADC_SPI_RdWr <= '1';
sNextState <= StWaitDoneTrsfRegRd;
end if;
-- Wait for Transfer register read command to complete.
when StWaitDoneTrsfRegRd =>
--fsmcfg_state <= "101111";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Done = '1') then
-- Check if the expected value has been read; A timeout limit
-- is imposed.
if (sADC_SPI_RdData = x"00") then
sNextState <= StSetTrsfReg;
elsif (sCfgTimer >= kCfgTimeout) then
sNextState <= StError;
else
sNextState <= StReadTrsfReg;
end if;
end if;
-- Set the Transfer field of the Transfer register.
when StSetTrsfReg =>
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
--fsmcfg_state <= "101010";
if (sADC_SPI_Busy = '0') then
sADC_ApStart <= '1';
sADC_SPI_WrData <= kSetTrsfReg(7 downto 0);
sADC_SPI_Addr <= kSetTrsfReg(20 downto 8);
sADC_SPI_Width <= kSetTrsfReg(22 downto 21);
sADC_SPI_RdWr <= '0';
sNextState <= StWaitDoneTrsfReg;
end if;
-- Wait for SPI command to be completed.
when StWaitDoneTrsfReg =>
--fsmcfg_state <= "101011";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Done = '1') then
sNextState <= StReadControlReg;
end if;
-- Read back the register value configured in the StWriteControlReg state.
when StReadControlReg =>
--fsmcfg_state <= "000110";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Busy = '0') then
sADC_ApStart <= '1';
sADC_SPI_Addr <= kADC_SPI_Cmd(sCmdCntInt)(20 downto 8);
sADC_SPI_Width <= kADC_SPI_Cmd(sCmdCntInt)(22 downto 21);
sADC_SPI_RdWr <= '1';
sNextState <= StWaitDoneReadReg;
end if;
-- Wait for SPI command to be completed and compare the read data against
-- the expected value (the kADC_SPI_Rdbck readback sequence)
when StWaitDoneReadReg =>
--fsmcfg_state <= "000111";
sRstCmdCnt <= '1';
sCfgTimerRst_n <= '1';
if (sADC_SPI_Done = '1') then
-- Wait for bits that are set/reset by the ADC to change value
-- (Reg00 soft reset for example). Amount of time not specified by data sheet,
-- the timeout value chosen empirically.
if (sADC_SPI_RdData = kADC_SPI_Rdbck(sCmdCntInt)) then
sNextState <= StCheckCmdCnt;
elsif (sCfgTimer >= kCfgTimeout) then
sNextState <= StError;
else
sNextState <= StReadControlReg;
end if;
end if;
-- Check if the command sequence has completed.
when StCheckCmdCnt =>
--fsmcfg_state <= "000011";
sRstCmdCnt <= '1';
if (sCmdCntInt = kCmdTotal) then
sRstCmdCnt <= '0';
sNextState <= StResetTimer;
else
sIncCmdCnt <= '1';
sNextState <= StWriteControlReg;
end if;
-- Reset timeout timer.
when StResetTimer =>
--fsmcfg_state <= "001001";
sNextState <= StWaitRecover;
-- Wait to recover form power down mode.
when StWaitRecover =>
--fsmcfg_state <= "001010";
sCfgTimerRst_n <= '1';
if (sCfgTimer = sCountResetResumeVal) then
sNextState <= StInitDone;
end if;
-- Indicate that the initialization sequence has completed.
when StInitDone =>
--fsmcfg_state <= "001011";
sInitDoneADC_Fsm <= '1';
sNextState <= StIdle;
-- IDLE state; wait for changes on the SPI Indirect Access Port.
when StIdle =>
--fsmcfg_state <= "001100";
sInitDoneADC_Fsm <= '1';
if ((sCmdTxAxisTvalid = '1') and (sADC_SPI_Busy = '0')) then
sLdCmdTxData <= '1';
if (sCmdTxAxisTdata(23) = '0') then
sNextState <= StExtSPI_WrCmd;
else
sNextState <= StExtSPI_RdCmd;
end if;
end if;
-- Execute the register write command requested on the SPI Indirect Access Port.
when StExtSPI_WrCmd =>
--fsmcfg_state <= "001101";
sInitDoneADC_Fsm <= '1';
sADC_ApStart <= '1';
sADC_SPI_WrData <= sCmdTxDataReg(7 downto 0);
sADC_SPI_Addr <= sCmdTxDataReg(20 downto 8);
sADC_SPI_Width <= sCmdTxDataReg(22 downto 21);
sADC_SPI_RdWr <= '0';
sNextState <= StWaitDoneExtWrReg;
-- Wait for the register write command to complete
when StWaitDoneExtWrReg =>
--fsmcfg_state <= "001110";
sInitDoneADC_Fsm <= '1';
if (sADC_SPI_Done = '1') then
sCmdTxAxisTreadyLoc <= '1';
sNextState <= StIdle;
end if;
-- Execute the register read command requested on the SPI Indirect Access Port.
when StExtSPI_RdCmd =>
--fsmcfg_state <= "001111";
sInitDoneADC_Fsm <= '1';
sADC_ApStart <= '1';
sADC_SPI_Addr <= sCmdTxDataReg(20 downto 8);
sADC_SPI_Width <= sCmdTxDataReg(22 downto 21);
sADC_SPI_RdWr <= '1';
sNextState <= StWaitDoneExtRdReg;
-- Wait for the register read command to complete.
when StWaitDoneExtRdReg =>
--fsmcfg_state <= "010000";
sInitDoneADC_Fsm <= '1';
if (sADC_SPI_Done = '1') then
sCmdTxAxisTreadyLoc <= '1';
sNextState <= StRegExtRxData;
end if;
-- State used to register the incoming SPI data.
when StRegExtRxData =>
--fsmcfg_state <= "010001";
sInitDoneADC_Fsm <= '1';
sCmdRxAxisTvalidLoc <= '1';
sCmdRxAxisTdataLoc <= sADC_SPI_RdData;
if (sCmdRxAxisTready = '1') then
sNextState <= StIdle;
end if;
-- When an error condition is detected the state machine stalls in this state.
-- An external reset condition is necessary to exit this state.
when StError =>
--fsmcfg_state <= "111111";
sConfigErrorFsm <= '1';
report "ADC Configuration readback error." & LF & HT & HT
severity ERROR;
when others =>
sNextState <= StStart;
end case;
end process;
end Behavioral;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity mctrl is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end;
architecture rtl of mctrl is
constant REVISION : integer := 1;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
sdhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
end record;
signal r, ri : reg_type;
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
signal lsdo : sdram_out_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rrsbdrive, rsbdrive, risbdrive : std_logic_vector(63 downto 0);
signal arst : std_ulogic;
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
attribute syn_preserve of rrsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
arst <= ahbsi.testrst when (scantest = 1) and (ahbsi.testen = '1') else rst;
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive,
rsbdrive, rrsbdrive)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
variable haddrsel : std_logic_vector(31 downto 13);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
haddrsel := (others => '0');
haddrsel(sdrasel downto 13) := haddr(sdrasel downto 13);
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddrsel(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddrsel(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1'))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
if (((sdmo.aload and r.hsel) = '1') and SDRAMEN) then
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbreadword(ahbsi.hwdata, r.address(4 downto 2));
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if r.address(1) = '1' then
writedata(31 downto 16) := writedata(15 downto 0);
end if;
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then
v.writedata(31 downto 16) := writedata(31 downto 16);
elsif r.busw = "01" then
if (r.address(1) = '0') or (r.brmw = '1') then
v.writedata(31 downto 16) := writedata(31 downto 16);
else
v.writedata(31 downto 16) := writedata(15 downto 0);
end if;
else
case r.address(1 downto 0) is
when "00" =>
v.writedata(31 downto 16) := writedata(31 downto 16);
when "01" =>
v.writedata(31 downto 24) := writedata(23 downto 16);
when "10" =>
v.writedata(31 downto 16) := writedata(15 downto 0);
when "11" =>
v.writedata(31 downto 24) := writedata(7 downto 0);
when others =>
null;
end case;
end if;
v.writedata(15 downto 0) := writedata(15 downto 0);
if r.busw(1) = '0' then
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.echeck := '1';
if r.area(io) = '0' then
v.address := ahbsi.haddr;
end if;
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE) or (r.area(io) = '1'))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
v.wrn := (others => '1'); v.writen := '1';
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 16) := sdmo.prdata(31 downto 16);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when "11" =>
if SDRAMEN then
regsd(31 downto 0) := sdmo.prdata(31 downto 0);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
v.sdhsel := sdhsel;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) or ((r.ramsn & r.romsn & r.iosn) /= "111111111") then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
if r.sdhsel = '1' then
v.hresp := sdmo.hresp;
end if;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if oepol = 0 then
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
else
if WENDFB then bdrive := r.nbdrive or not memi.wrn;
else bdrive := r.nbdrive; end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
-- scan support
if (syncrst = 1) and (rst = '0') then
memo.ramsn <= (others => '1');
memo.ramoen <= (others => '1');
memo.romsn <= (others => '1');
memo.iosn <= '1';
memo.oen <= '1';
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
if oepol = 0 then
memo.bdrive <= (others => '1');
memo.vbdrive <= (others => '1');
memo.svbdrive <= (others => '1');
else
memo.bdrive <= (others => '0');
memo.vbdrive <= (others => '0');
memo.svbdrive <= (others => '0');
end if;
end if;
else
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.iosn <= r.iosn(0);
memo.oen <= r.oen;
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
memo.bdrive <= bdrive;
memo.vbdrive <= rbdrive;
memo.svbdrive <= rrsbdrive;
end if;
end if;
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.address;
memo.read <= r.read;
memo.wrn <= r.wrn;
memo.writen <= r.writen;
memo.data <= r.writedata;
memo.mben <= r.mben;
memo.svcdrive <= (others => '0');
memo.vcdrive <= (others => '0');
memo.scb <= (others => '0');
memo.cb <= (others => '0');
memo.romn <= r.romsn(0);
memo.ramn <= r.ramsn(0);
memo.sdram_en <= r.mcfg2.sdren; -- Unused
memo.rs_edac_en <= '0';
memo.ce <= '0';
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
sdi.edac <= '0';
sdi.brmw <= '0';
sdi.error <= '0';
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
end process;
stdregs : process(clk, arst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (arst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits, pageburst, mobile)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => lsdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
rgen : if invclk = 0 generate
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end generate;
ngen : if invclk = 1 generate
nregs : process(clk, arst) begin
if falling_edge(clk) then
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
if (syncrst = 0) and (arst = '0') then
if oepol = 0 then rrsbdrive <= (others => '1');
else rrsbdrive <= (others => '0'); end if;
end if;
end if;
end process;
end generate;
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.prdata <= (others => '0');
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
memo.sddata <= (others => '0');
memo.sa <= (others => '0');
end generate;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity mctrl is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end;
architecture rtl of mctrl is
constant REVISION : integer := 1;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
sdhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
end record;
signal r, ri : reg_type;
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
signal lsdo : sdram_out_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rrsbdrive, rsbdrive, risbdrive : std_logic_vector(63 downto 0);
signal arst : std_ulogic;
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
attribute syn_preserve of rrsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
arst <= ahbsi.testrst when (scantest = 1) and (ahbsi.testen = '1') else rst;
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive,
rsbdrive, rrsbdrive)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
variable haddrsel : std_logic_vector(31 downto 13);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
haddrsel := (others => '0');
haddrsel(sdrasel downto 13) := haddr(sdrasel downto 13);
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddrsel(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddrsel(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1'))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
if (((sdmo.aload and r.hsel) = '1') and SDRAMEN) then
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbreadword(ahbsi.hwdata, r.address(4 downto 2));
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if r.address(1) = '1' then
writedata(31 downto 16) := writedata(15 downto 0);
end if;
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then
v.writedata(31 downto 16) := writedata(31 downto 16);
elsif r.busw = "01" then
if (r.address(1) = '0') or (r.brmw = '1') then
v.writedata(31 downto 16) := writedata(31 downto 16);
else
v.writedata(31 downto 16) := writedata(15 downto 0);
end if;
else
case r.address(1 downto 0) is
when "00" =>
v.writedata(31 downto 16) := writedata(31 downto 16);
when "01" =>
v.writedata(31 downto 24) := writedata(23 downto 16);
when "10" =>
v.writedata(31 downto 16) := writedata(15 downto 0);
when "11" =>
v.writedata(31 downto 24) := writedata(7 downto 0);
when others =>
null;
end case;
end if;
v.writedata(15 downto 0) := writedata(15 downto 0);
if r.busw(1) = '0' then
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.echeck := '1';
if r.area(io) = '0' then
v.address := ahbsi.haddr;
end if;
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE) or (r.area(io) = '1'))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
v.wrn := (others => '1'); v.writen := '1';
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 16) := sdmo.prdata(31 downto 16);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when "11" =>
if SDRAMEN then
regsd(31 downto 0) := sdmo.prdata(31 downto 0);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
v.sdhsel := sdhsel;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) or ((r.ramsn & r.romsn & r.iosn) /= "111111111") then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
if r.sdhsel = '1' then
v.hresp := sdmo.hresp;
end if;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if oepol = 0 then
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
else
if WENDFB then bdrive := r.nbdrive or not memi.wrn;
else bdrive := r.nbdrive; end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
-- scan support
if (syncrst = 1) and (rst = '0') then
memo.ramsn <= (others => '1');
memo.ramoen <= (others => '1');
memo.romsn <= (others => '1');
memo.iosn <= '1';
memo.oen <= '1';
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
if oepol = 0 then
memo.bdrive <= (others => '1');
memo.vbdrive <= (others => '1');
memo.svbdrive <= (others => '1');
else
memo.bdrive <= (others => '0');
memo.vbdrive <= (others => '0');
memo.svbdrive <= (others => '0');
end if;
end if;
else
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.iosn <= r.iosn(0);
memo.oen <= r.oen;
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
memo.bdrive <= bdrive;
memo.vbdrive <= rbdrive;
memo.svbdrive <= rrsbdrive;
end if;
end if;
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.address;
memo.read <= r.read;
memo.wrn <= r.wrn;
memo.writen <= r.writen;
memo.data <= r.writedata;
memo.mben <= r.mben;
memo.svcdrive <= (others => '0');
memo.vcdrive <= (others => '0');
memo.scb <= (others => '0');
memo.cb <= (others => '0');
memo.romn <= r.romsn(0);
memo.ramn <= r.ramsn(0);
memo.sdram_en <= r.mcfg2.sdren; -- Unused
memo.rs_edac_en <= '0';
memo.ce <= '0';
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
sdi.edac <= '0';
sdi.brmw <= '0';
sdi.error <= '0';
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
end process;
stdregs : process(clk, arst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (arst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits, pageburst, mobile)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => lsdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
rgen : if invclk = 0 generate
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end generate;
ngen : if invclk = 1 generate
nregs : process(clk, arst) begin
if falling_edge(clk) then
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
if (syncrst = 0) and (arst = '0') then
if oepol = 0 then rrsbdrive <= (others => '1');
else rrsbdrive <= (others => '0'); end if;
end if;
end if;
end process;
end generate;
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.prdata <= (others => '0');
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
memo.sddata <= (others => '0');
memo.sa <= (others => '0');
end generate;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity mctrl is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end;
architecture rtl of mctrl is
constant REVISION : integer := 1;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
sdhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
end record;
signal r, ri : reg_type;
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
signal lsdo : sdram_out_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rrsbdrive, rsbdrive, risbdrive : std_logic_vector(63 downto 0);
signal arst : std_ulogic;
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
attribute syn_preserve of rrsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
arst <= ahbsi.testrst when (scantest = 1) and (ahbsi.testen = '1') else rst;
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive,
rsbdrive, rrsbdrive)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
variable haddrsel : std_logic_vector(31 downto 13);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
haddrsel := (others => '0');
haddrsel(sdrasel downto 13) := haddr(sdrasel downto 13);
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddrsel(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddrsel(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1'))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
if (((sdmo.aload and r.hsel) = '1') and SDRAMEN) then
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbreadword(ahbsi.hwdata, r.address(4 downto 2));
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if r.address(1) = '1' then
writedata(31 downto 16) := writedata(15 downto 0);
end if;
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then
v.writedata(31 downto 16) := writedata(31 downto 16);
elsif r.busw = "01" then
if (r.address(1) = '0') or (r.brmw = '1') then
v.writedata(31 downto 16) := writedata(31 downto 16);
else
v.writedata(31 downto 16) := writedata(15 downto 0);
end if;
else
case r.address(1 downto 0) is
when "00" =>
v.writedata(31 downto 16) := writedata(31 downto 16);
when "01" =>
v.writedata(31 downto 24) := writedata(23 downto 16);
when "10" =>
v.writedata(31 downto 16) := writedata(15 downto 0);
when "11" =>
v.writedata(31 downto 24) := writedata(7 downto 0);
when others =>
null;
end case;
end if;
v.writedata(15 downto 0) := writedata(15 downto 0);
if r.busw(1) = '0' then
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.echeck := '1';
if r.area(io) = '0' then
v.address := ahbsi.haddr;
end if;
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE) or (r.area(io) = '1'))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
v.wrn := (others => '1'); v.writen := '1';
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 16) := sdmo.prdata(31 downto 16);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when "11" =>
if SDRAMEN then
regsd(31 downto 0) := sdmo.prdata(31 downto 0);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
v.sdhsel := sdhsel;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) or ((r.ramsn & r.romsn & r.iosn) /= "111111111") then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
if r.sdhsel = '1' then
v.hresp := sdmo.hresp;
end if;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if oepol = 0 then
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
else
if WENDFB then bdrive := r.nbdrive or not memi.wrn;
else bdrive := r.nbdrive; end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
-- scan support
if (syncrst = 1) and (rst = '0') then
memo.ramsn <= (others => '1');
memo.ramoen <= (others => '1');
memo.romsn <= (others => '1');
memo.iosn <= '1';
memo.oen <= '1';
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
if oepol = 0 then
memo.bdrive <= (others => '1');
memo.vbdrive <= (others => '1');
memo.svbdrive <= (others => '1');
else
memo.bdrive <= (others => '0');
memo.vbdrive <= (others => '0');
memo.svbdrive <= (others => '0');
end if;
end if;
else
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.iosn <= r.iosn(0);
memo.oen <= r.oen;
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
memo.bdrive <= bdrive;
memo.vbdrive <= rbdrive;
memo.svbdrive <= rrsbdrive;
end if;
end if;
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.address;
memo.read <= r.read;
memo.wrn <= r.wrn;
memo.writen <= r.writen;
memo.data <= r.writedata;
memo.mben <= r.mben;
memo.svcdrive <= (others => '0');
memo.vcdrive <= (others => '0');
memo.scb <= (others => '0');
memo.cb <= (others => '0');
memo.romn <= r.romsn(0);
memo.ramn <= r.ramsn(0);
memo.sdram_en <= r.mcfg2.sdren; -- Unused
memo.rs_edac_en <= '0';
memo.ce <= '0';
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
sdi.edac <= '0';
sdi.brmw <= '0';
sdi.error <= '0';
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
end process;
stdregs : process(clk, arst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (arst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits, pageburst, mobile)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => lsdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
rgen : if invclk = 0 generate
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end generate;
ngen : if invclk = 1 generate
nregs : process(clk, arst) begin
if falling_edge(clk) then
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
if (syncrst = 0) and (arst = '0') then
if oepol = 0 then rrsbdrive <= (others => '1');
else rrsbdrive <= (others => '0'); end if;
end if;
end if;
end process;
end generate;
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.prdata <= (others => '0');
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
memo.sddata <= (others => '0');
memo.sa <= (others => '0');
end generate;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity mctrl is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end;
architecture rtl of mctrl is
constant REVISION : integer := 1;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
sdhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
end record;
signal r, ri : reg_type;
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
signal lsdo : sdram_out_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rrsbdrive, rsbdrive, risbdrive : std_logic_vector(63 downto 0);
signal arst : std_ulogic;
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
attribute syn_preserve of rrsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
arst <= ahbsi.testrst when (scantest = 1) and (ahbsi.testen = '1') else rst;
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive,
rsbdrive, rrsbdrive)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
variable haddrsel : std_logic_vector(31 downto 13);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
haddrsel := (others => '0');
haddrsel(sdrasel downto 13) := haddr(sdrasel downto 13);
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddrsel(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddrsel(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1'))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
if (((sdmo.aload and r.hsel) = '1') and SDRAMEN) then
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbreadword(ahbsi.hwdata, r.address(4 downto 2));
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if r.address(1) = '1' then
writedata(31 downto 16) := writedata(15 downto 0);
end if;
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then
v.writedata(31 downto 16) := writedata(31 downto 16);
elsif r.busw = "01" then
if (r.address(1) = '0') or (r.brmw = '1') then
v.writedata(31 downto 16) := writedata(31 downto 16);
else
v.writedata(31 downto 16) := writedata(15 downto 0);
end if;
else
case r.address(1 downto 0) is
when "00" =>
v.writedata(31 downto 16) := writedata(31 downto 16);
when "01" =>
v.writedata(31 downto 24) := writedata(23 downto 16);
when "10" =>
v.writedata(31 downto 16) := writedata(15 downto 0);
when "11" =>
v.writedata(31 downto 24) := writedata(7 downto 0);
when others =>
null;
end case;
end if;
v.writedata(15 downto 0) := writedata(15 downto 0);
if r.busw(1) = '0' then
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.echeck := '1';
if r.area(io) = '0' then
v.address := ahbsi.haddr;
end if;
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE) or (r.area(io) = '1'))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
v.wrn := (others => '1'); v.writen := '1';
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 16) := sdmo.prdata(31 downto 16);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when "11" =>
if SDRAMEN then
regsd(31 downto 0) := sdmo.prdata(31 downto 0);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
v.sdhsel := sdhsel;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) or ((r.ramsn & r.romsn & r.iosn) /= "111111111") then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
if r.sdhsel = '1' then
v.hresp := sdmo.hresp;
end if;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if oepol = 0 then
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
else
if WENDFB then bdrive := r.nbdrive or not memi.wrn;
else bdrive := r.nbdrive; end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
-- scan support
if (syncrst = 1) and (rst = '0') then
memo.ramsn <= (others => '1');
memo.ramoen <= (others => '1');
memo.romsn <= (others => '1');
memo.iosn <= '1';
memo.oen <= '1';
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
if oepol = 0 then
memo.bdrive <= (others => '1');
memo.vbdrive <= (others => '1');
memo.svbdrive <= (others => '1');
else
memo.bdrive <= (others => '0');
memo.vbdrive <= (others => '0');
memo.svbdrive <= (others => '0');
end if;
end if;
else
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.iosn <= r.iosn(0);
memo.oen <= r.oen;
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
memo.bdrive <= bdrive;
memo.vbdrive <= rbdrive;
memo.svbdrive <= rrsbdrive;
end if;
end if;
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.address;
memo.read <= r.read;
memo.wrn <= r.wrn;
memo.writen <= r.writen;
memo.data <= r.writedata;
memo.mben <= r.mben;
memo.svcdrive <= (others => '0');
memo.vcdrive <= (others => '0');
memo.scb <= (others => '0');
memo.cb <= (others => '0');
memo.romn <= r.romsn(0);
memo.ramn <= r.ramsn(0);
memo.sdram_en <= r.mcfg2.sdren; -- Unused
memo.rs_edac_en <= '0';
memo.ce <= '0';
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
sdi.edac <= '0';
sdi.brmw <= '0';
sdi.error <= '0';
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
end process;
stdregs : process(clk, arst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (arst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits, pageburst, mobile)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => lsdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
rgen : if invclk = 0 generate
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end generate;
ngen : if invclk = 1 generate
nregs : process(clk, arst) begin
if falling_edge(clk) then
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
if (syncrst = 0) and (arst = '0') then
if oepol = 0 then rrsbdrive <= (others => '1');
else rrsbdrive <= (others => '0'); end if;
end if;
end if;
end process;
end generate;
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.prdata <= (others => '0');
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
memo.sddata <= (others => '0');
memo.sa <= (others => '0');
end generate;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc901.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00901ent IS
type AR is array (1 to 10) of AR; -- Failure_here
-- entity is not visible until end of declaration
END c10s03b00x00p05n01i00901ent;
ARCHITECTURE c10s03b00x00p05n01i00901arch OF c10s03b00x00p05n01i00901ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00901 - Declaration is not visible until the end of the declaration.
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00901arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc901.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00901ent IS
type AR is array (1 to 10) of AR; -- Failure_here
-- entity is not visible until end of declaration
END c10s03b00x00p05n01i00901ent;
ARCHITECTURE c10s03b00x00p05n01i00901arch OF c10s03b00x00p05n01i00901ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00901 - Declaration is not visible until the end of the declaration.
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00901arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc901.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00901ent IS
type AR is array (1 to 10) of AR; -- Failure_here
-- entity is not visible until end of declaration
END c10s03b00x00p05n01i00901ent;
ARCHITECTURE c10s03b00x00p05n01i00901arch OF c10s03b00x00p05n01i00901ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00901 - Declaration is not visible until the end of the declaration.
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00901arch;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 =>w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Fetch command write interface from fetch sm --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
ftch_done : out std_logic ; --
ftch_error : out std_logic ; --
ftch_interr : out std_logic ; --
ftch_slverr : out std_logic ; --
ftch_decerr : out std_logic ; --
ftch_error_early : out std_logic --
);
end axi_sg_ftch_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_slverr_i : std_logic := '0';
signal ftch_decerr_i : std_logic := '0';
signal ftch_interr_i : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal sg_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sg_rvalid : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_slverr <= ftch_slverr_i;
ftch_decerr <= ftch_decerr_i;
ftch_interr <= ftch_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
s_axis_ftch_cmd_tvalid <= '1';
-- s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
elsif(s_axis_ftch_cmd_tready = '1')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_ftch_sts_tready <= '0';
else
m_axis_ftch_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_ftch_sts_tvalid = '1')then
ftch_done <= m_axis_ftch_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
ftch_slverr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
ftch_decerr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_DECERR_BIT);
ftch_interr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Early SlvErr and DecErr detections
-- Early detection primarily required for non-queue mode because fetched desc
-- is immediatle fed to DMA controller. Status from SG Datamover arrives
-- too late to stop the insuing transfer on fetch error
-------------------------------------------------------------------------------
REG_MM_RD_SIGNALS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_rresp <= (others => '0');
sg_rvalid <= '0';
else
sg_rresp <= m_axi_sg_rresp;
sg_rvalid <= m_axi_sg_rvalid;
end if;
end if;
end process REG_MM_RD_SIGNALS;
REG_ERLY_FTCH_ERROR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_early <= '0';
elsif(sg_rvalid = '1' and (sg_rresp = SLVERR_RESP
or sg_rresp = DECERR_RESP))then
ftch_error_early <= '1';
end if;
end if;
end process REG_ERLY_FTCH_ERROR;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error <= ftch_slverr_i or ftch_decerr_i or ftch_interr_i;
-- Log errors into a global error output
FETCH_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error <= '0';
elsif(mm2s_error = '1')then
ftch_error <= '1';
end if;
end if;
end process FETCH_ERROR_PROCESS;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Fetch command write interface from fetch sm --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
ftch_done : out std_logic ; --
ftch_error : out std_logic ; --
ftch_interr : out std_logic ; --
ftch_slverr : out std_logic ; --
ftch_decerr : out std_logic ; --
ftch_error_early : out std_logic --
);
end axi_sg_ftch_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_slverr_i : std_logic := '0';
signal ftch_decerr_i : std_logic := '0';
signal ftch_interr_i : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal sg_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sg_rvalid : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_slverr <= ftch_slverr_i;
ftch_decerr <= ftch_decerr_i;
ftch_interr <= ftch_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
s_axis_ftch_cmd_tvalid <= '1';
-- s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
elsif(s_axis_ftch_cmd_tready = '1')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_ftch_sts_tready <= '0';
else
m_axis_ftch_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_ftch_sts_tvalid = '1')then
ftch_done <= m_axis_ftch_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
ftch_slverr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
ftch_decerr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_DECERR_BIT);
ftch_interr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Early SlvErr and DecErr detections
-- Early detection primarily required for non-queue mode because fetched desc
-- is immediatle fed to DMA controller. Status from SG Datamover arrives
-- too late to stop the insuing transfer on fetch error
-------------------------------------------------------------------------------
REG_MM_RD_SIGNALS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_rresp <= (others => '0');
sg_rvalid <= '0';
else
sg_rresp <= m_axi_sg_rresp;
sg_rvalid <= m_axi_sg_rvalid;
end if;
end if;
end process REG_MM_RD_SIGNALS;
REG_ERLY_FTCH_ERROR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_early <= '0';
elsif(sg_rvalid = '1' and (sg_rresp = SLVERR_RESP
or sg_rresp = DECERR_RESP))then
ftch_error_early <= '1';
end if;
end if;
end process REG_ERLY_FTCH_ERROR;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error <= ftch_slverr_i or ftch_decerr_i or ftch_interr_i;
-- Log errors into a global error output
FETCH_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error <= '0';
elsif(mm2s_error = '1')then
ftch_error <= '1';
end if;
end if;
end process FETCH_ERROR_PROCESS;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Fetch command write interface from fetch sm --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
ftch_done : out std_logic ; --
ftch_error : out std_logic ; --
ftch_interr : out std_logic ; --
ftch_slverr : out std_logic ; --
ftch_decerr : out std_logic ; --
ftch_error_early : out std_logic --
);
end axi_sg_ftch_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_slverr_i : std_logic := '0';
signal ftch_decerr_i : std_logic := '0';
signal ftch_interr_i : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal sg_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sg_rvalid : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_slverr <= ftch_slverr_i;
ftch_decerr <= ftch_decerr_i;
ftch_interr <= ftch_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
s_axis_ftch_cmd_tvalid <= '1';
-- s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
elsif(s_axis_ftch_cmd_tready = '1')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_ftch_sts_tready <= '0';
else
m_axis_ftch_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_ftch_sts_tvalid = '1')then
ftch_done <= m_axis_ftch_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
ftch_slverr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
ftch_decerr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_DECERR_BIT);
ftch_interr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Early SlvErr and DecErr detections
-- Early detection primarily required for non-queue mode because fetched desc
-- is immediatle fed to DMA controller. Status from SG Datamover arrives
-- too late to stop the insuing transfer on fetch error
-------------------------------------------------------------------------------
REG_MM_RD_SIGNALS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_rresp <= (others => '0');
sg_rvalid <= '0';
else
sg_rresp <= m_axi_sg_rresp;
sg_rvalid <= m_axi_sg_rvalid;
end if;
end if;
end process REG_MM_RD_SIGNALS;
REG_ERLY_FTCH_ERROR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_early <= '0';
elsif(sg_rvalid = '1' and (sg_rresp = SLVERR_RESP
or sg_rresp = DECERR_RESP))then
ftch_error_early <= '1';
end if;
end if;
end process REG_ERLY_FTCH_ERROR;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error <= ftch_slverr_i or ftch_decerr_i or ftch_interr_i;
-- Log errors into a global error output
FETCH_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error <= '0';
elsif(mm2s_error = '1')then
ftch_error <= '1';
end if;
end if;
end process FETCH_ERROR_PROCESS;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Fetch command write interface from fetch sm --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
ftch_done : out std_logic ; --
ftch_error : out std_logic ; --
ftch_interr : out std_logic ; --
ftch_slverr : out std_logic ; --
ftch_decerr : out std_logic ; --
ftch_error_early : out std_logic --
);
end axi_sg_ftch_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_slverr_i : std_logic := '0';
signal ftch_decerr_i : std_logic := '0';
signal ftch_interr_i : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal sg_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sg_rvalid : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_slverr <= ftch_slverr_i;
ftch_decerr <= ftch_decerr_i;
ftch_interr <= ftch_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
s_axis_ftch_cmd_tvalid <= '1';
-- s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
elsif(s_axis_ftch_cmd_tready = '1')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_ftch_sts_tready <= '0';
else
m_axis_ftch_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_ftch_sts_tvalid = '1')then
ftch_done <= m_axis_ftch_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
ftch_slverr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
ftch_decerr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_DECERR_BIT);
ftch_interr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Early SlvErr and DecErr detections
-- Early detection primarily required for non-queue mode because fetched desc
-- is immediatle fed to DMA controller. Status from SG Datamover arrives
-- too late to stop the insuing transfer on fetch error
-------------------------------------------------------------------------------
REG_MM_RD_SIGNALS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_rresp <= (others => '0');
sg_rvalid <= '0';
else
sg_rresp <= m_axi_sg_rresp;
sg_rvalid <= m_axi_sg_rvalid;
end if;
end if;
end process REG_MM_RD_SIGNALS;
REG_ERLY_FTCH_ERROR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_early <= '0';
elsif(sg_rvalid = '1' and (sg_rresp = SLVERR_RESP
or sg_rresp = DECERR_RESP))then
ftch_error_early <= '1';
end if;
end if;
end process REG_ERLY_FTCH_ERROR;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error <= ftch_slverr_i or ftch_decerr_i or ftch_interr_i;
-- Log errors into a global error output
FETCH_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error <= '0';
elsif(mm2s_error = '1')then
ftch_error <= '1';
end if;
end if;
end process FETCH_ERROR_PROCESS;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Fetch command write interface from fetch sm --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
ftch_done : out std_logic ; --
ftch_error : out std_logic ; --
ftch_interr : out std_logic ; --
ftch_slverr : out std_logic ; --
ftch_decerr : out std_logic ; --
ftch_error_early : out std_logic --
);
end axi_sg_ftch_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_slverr_i : std_logic := '0';
signal ftch_decerr_i : std_logic := '0';
signal ftch_interr_i : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal sg_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sg_rvalid : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_slverr <= ftch_slverr_i;
ftch_decerr <= ftch_decerr_i;
ftch_interr <= ftch_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
s_axis_ftch_cmd_tvalid <= '1';
-- s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
elsif(s_axis_ftch_cmd_tready = '1')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_ftch_sts_tready <= '0';
else
m_axis_ftch_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_ftch_sts_tvalid = '1')then
ftch_done <= m_axis_ftch_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
ftch_slverr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
ftch_decerr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_DECERR_BIT);
ftch_interr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Early SlvErr and DecErr detections
-- Early detection primarily required for non-queue mode because fetched desc
-- is immediatle fed to DMA controller. Status from SG Datamover arrives
-- too late to stop the insuing transfer on fetch error
-------------------------------------------------------------------------------
REG_MM_RD_SIGNALS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_rresp <= (others => '0');
sg_rvalid <= '0';
else
sg_rresp <= m_axi_sg_rresp;
sg_rvalid <= m_axi_sg_rvalid;
end if;
end if;
end process REG_MM_RD_SIGNALS;
REG_ERLY_FTCH_ERROR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_early <= '0';
elsif(sg_rvalid = '1' and (sg_rresp = SLVERR_RESP
or sg_rresp = DECERR_RESP))then
ftch_error_early <= '1';
end if;
end if;
end process REG_ERLY_FTCH_ERROR;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error <= ftch_slverr_i or ftch_decerr_i or ftch_interr_i;
-- Log errors into a global error output
FETCH_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error <= '0';
elsif(mm2s_error = '1')then
ftch_error <= '1';
end if;
end if;
end process FETCH_ERROR_PROCESS;
end implementation;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.all;
use work.spi_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
use work.transaction_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
--===============================================================================================
-- Types and constants for the SPI VVC
--===============================================================================================
constant C_VVC_NAME : string := "SPI_VVC";
signal SPI_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is SPI_VVCT;
alias t_bfm_config is t_spi_bfm_config;
constant C_SPI_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => warning
);
type t_vvc_config is record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_spi_bfm_config; -- Configuration for the BFM. See BFM quick reference
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
parent_msg_id_panel : t_msg_id_panel; --UVVM: temporary fix for HVVC, remove in v3.0
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_SPI_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_SPI_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_SPI_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT,
parent_msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information for the wave view during simulation
type t_transaction_info is record
operation : t_operation;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
tx_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
rx_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
num_words : natural;
word_length : natural;
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
tx_data => (others => (others => '0')),
rx_data => (others => (others => '0')),
data_exp => (others => (others => '0')),
num_words => 0,
word_length => 0,
operation => NO_OPERATION,
msg => (others => ' ')
);
shared variable shared_spi_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_SPI_VVC_CONFIG_DEFAULT);
shared variable shared_spi_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_spi_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_TRANSACTION_INFO_DEFAULT);
-- Scoreboard
package spi_sb_pkg is new bitvis_vip_scoreboard.generic_sb_pkg
generic map (t_element => std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0),
element_match => std_match,
to_string_element => to_string);
use spi_sb_pkg.all;
shared variable SPI_VVC_SB : spi_sb_pkg.t_generic_sb;
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
----------------------------------------------------------
-- SPI_MASTER
----------------------------------------------------------
-- Single-word
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_routing : in t_data_routing;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Multi-word
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant data_routing : in t_data_routing;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Single-word
procedure spi_master_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Multi-word
procedure spi_master_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Single-word
procedure spi_master_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Multi-word
procedure spi_master_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure spi_master_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_routing : in t_data_routing;
constant msg : in string;
constant num_words : in positive := 1;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure spi_master_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant num_words : in positive := 1;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Single-word
procedure spi_master_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Multi-word
procedure spi_master_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
----------------------------------------------------------
-- SPI_SLAVE
----------------------------------------------------------
-- Single-word
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_routing : in t_data_routing;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Multi-word
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant data_routing : in t_data_routing;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Single-word
procedure spi_slave_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Multi-word
procedure spi_slave_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Single-word
procedure spi_slave_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Multi-word
procedure spi_slave_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure spi_slave_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_routing : in t_data_routing;
constant msg : in string;
constant num_words : in positive := 1;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure spi_slave_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant num_words : in positive := 1;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Single-word
procedure spi_slave_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- Multi-word
procedure spi_slave_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
--==============================================================================
-- Transaction info methods
--==============================================================================
procedure set_global_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT);
procedure reset_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record);
--==============================================================================
-- VVC Activity
--==============================================================================
procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic;
variable vvc_status : inout t_vvc_status;
constant activity : in t_activity;
constant entry_num_in_vvc_activity_register : in integer;
constant last_cmd_idx_executed : in natural;
constant command_queue_is_empty : in boolean;
constant scope : in string := C_VVC_NAME);
--==============================================================================
-- VVC Scoreboard helper method
--==============================================================================
function pad_spi_sb(
constant data : in std_logic_vector
) return std_logic_vector;
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--==============================================================================
-- Methods dedicated to this VVC
-- Notes:
-- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command
--==============================================================================
----------------------------------------------------------
-- SPI_MASTER
----------------------------------------------------------
-- Single-word
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_routing : in t_data_routing;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data'length;
variable v_num_words : natural := 1;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize
v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_RECEIVE);
shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.data_routing := data_routing;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.action_between_words := RELEASE_LINE_BETWEEN_WORDS;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
begin
spi_master_transmit_and_receive(VVCT, vvc_instance_idx, data, NA, msg, action_when_transfer_is_done, scope, parent_msg_id_panel);
end procedure;
-- Multi-word
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant data_routing : in t_data_routing;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data(0)'length;
variable v_num_words : natural := data'length;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize
v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_RECEIVE);
shared_vvc_cmd.data := v_normalized_data;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.data_routing := data_routing;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.action_between_words := action_between_words;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure spi_master_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
begin
spi_master_transmit_and_receive(VVCT, vvc_instance_idx, data, NA, msg, action_when_transfer_is_done, action_between_words, scope, parent_msg_id_panel);
end procedure;
-- Single-word
procedure spi_master_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data'length;
variable v_num_words : natural := 1;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize to t_slv_array
v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
v_normalized_data_exp(0) := normalize_and_check(data_exp, shared_vvc_cmd.data_exp(0), ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_CHECK);
shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0);
shared_vvc_cmd.data_exp(0)(v_word_length-1 downto 0) := v_normalized_data_exp(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- Multi-word
procedure spi_master_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data(0)'length;
variable v_num_words : natural := data'length;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize
v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
v_normalized_data_exp := normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_CHECK);
shared_vvc_cmd.data := v_normalized_data;
shared_vvc_cmd.data_exp := v_normalized_data_exp;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.action_between_words := action_between_words;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- Single-word
procedure spi_master_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data'length;
variable v_num_words : natural := 1;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize to t_slv_array
v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_ONLY);
shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- Multi-word
procedure spi_master_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data(0)'length;
variable v_num_words : natural := data'length;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize
v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_ONLY);
shared_vvc_cmd.data := v_normalized_data;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.action_between_words := action_between_words;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- Single-word
procedure spi_master_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_routing : in t_data_routing;
constant msg : in string;
constant num_words : in positive := 1;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_RECEIVE_ONLY);
shared_vvc_cmd.data_routing := data_routing;
shared_vvc_cmd.num_words := num_words;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.action_between_words := action_between_words;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure spi_master_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant num_words : in positive := 1;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
begin
spi_master_receive_only(VVCT, vvc_instance_idx, NA, msg, num_words, action_when_transfer_is_done, action_between_words, scope, parent_msg_id_panel);
end procedure;
-- Single-word
procedure spi_master_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data_exp'length;
variable v_num_words : natural := 1;
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize to t_slv_array
v_normalized_data_exp(0) := normalize_and_check(data_exp, shared_vvc_cmd.data_exp(0), ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_CHECK_ONLY);
shared_vvc_cmd.data_exp(0)(v_word_length-1 downto 0) := v_normalized_data_exp(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- Multi-word
procedure spi_master_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data_exp(0)'length;
variable v_num_words : natural := data_exp'length;
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize
v_normalized_data_exp := normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_CHECK_ONLY);
shared_vvc_cmd.data_exp := v_normalized_data_exp;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.action_between_words := action_between_words;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
----------------------------------------------------------
-- SPI_SLAVE
----------------------------------------------------------
-- Single-word
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_routing : in t_data_routing;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data'length;
variable v_num_words : natural := 1;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize to t_slv_array
v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_RECEIVE);
shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.data_routing := data_routing;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
begin
spi_slave_transmit_and_receive(VVCT, vvc_instance_idx, data, NA, msg, when_to_start_transfer, scope, parent_msg_id_panel);
end procedure;
-- Multi-word
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant data_routing : in t_data_routing;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data(0)'length;
variable v_num_words : natural := data'length;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize
v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_RECEIVE);
shared_vvc_cmd.data := v_normalized_data;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.data_routing := data_routing;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure spi_slave_transmit_and_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
begin
spi_slave_transmit_and_receive(VVCT, vvc_instance_idx, data, NA, msg, when_to_start_transfer, scope, parent_msg_id_panel);
end procedure;
-- Single-word
procedure spi_slave_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data'length;
variable v_num_words : natural := 1;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize to t_slv_array
v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
v_normalized_data_exp(0) := normalize_and_check(data_exp, shared_vvc_cmd.data_exp(0), ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_CHECK);
shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0);
shared_vvc_cmd.data_exp(0)(v_word_length-1 downto 0) := v_normalized_data_exp(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- Multi-word
procedure spi_slave_transmit_and_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data(0)'length;
variable v_num_words : natural := data'length;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize
v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
v_normalized_data_exp := normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_CHECK);
shared_vvc_cmd.data := v_normalized_data;
shared_vvc_cmd.data_exp := v_normalized_data_exp;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- Single-word
procedure spi_slave_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data'length;
variable v_num_words : natural := 1;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize to t_slv_array
v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_ONLY);
shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- Multi-word
procedure spi_slave_transmit_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_slv_array;
constant msg : in string;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data(0)'length;
variable v_num_words : natural := data'length;
variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize
v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_ONLY);
shared_vvc_cmd.data := v_normalized_data;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- Single-word
procedure spi_slave_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_routing : in t_data_routing;
constant msg : in string;
constant num_words : in positive := 1;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_RECEIVE_ONLY);
shared_vvc_cmd.data_routing := data_routing;
shared_vvc_cmd.num_words := num_words;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure spi_slave_receive_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant num_words : in positive := 1;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
begin
spi_slave_receive_only(VVCT, vvc_instance_idx, NA, msg, num_words, when_to_start_transfer, scope, parent_msg_id_panel);
end procedure;
-- Single-word
procedure spi_slave_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data_exp'length;
variable v_num_words : natural := 1;
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize to t_slv_array
v_normalized_data_exp(0) := normalize_and_check(data_exp, shared_vvc_cmd.data_exp(0), ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_CHECK_ONLY);
--shared_vvc_cmd.data_exp := v_normalized_data_exp;
shared_vvc_cmd.data_exp(0)(v_word_length-1 downto 0) := v_normalized_data_exp(0)(v_word_length-1 downto 0);
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- Multi-word
procedure spi_slave_check_only(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_exp : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Helper variable
variable v_word_length : natural := data_exp(0)'length;
variable v_num_words : natural := data_exp'length;
variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0'));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- normalize
v_normalized_data_exp := normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_CHECK_ONLY);
shared_vvc_cmd.data_exp := v_normalized_data_exp;
shared_vvc_cmd.num_words := v_num_words;
shared_vvc_cmd.word_length := v_word_length;
shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
--==============================================================================
-- Transaction info methods
--==============================================================================
procedure set_global_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT) is
begin
case vvc_cmd.operation is
when MASTER_TRANSMIT_AND_RECEIVE | MASTER_TRANSMIT_AND_CHECK | MASTER_TRANSMIT_ONLY |
MASTER_RECEIVE_ONLY | MASTER_CHECK_ONLY | SLAVE_TRANSMIT_AND_RECEIVE |
SLAVE_TRANSMIT_AND_CHECK | SLAVE_TRANSMIT_ONLY | SLAVE_RECEIVE_ONLY | SLAVE_CHECK_ONLY =>
vvc_transaction_info_group.bt.operation := vvc_cmd.operation;
vvc_transaction_info_group.bt.data := vvc_cmd.data;
vvc_transaction_info_group.bt.data_exp := vvc_cmd.data_exp;
vvc_transaction_info_group.bt.num_words := vvc_cmd.num_words;
vvc_transaction_info_group.bt.word_length := vvc_cmd.word_length;
vvc_transaction_info_group.bt.when_to_start_transfer := vvc_cmd.when_to_start_transfer;
vvc_transaction_info_group.bt.action_when_transfer_is_done := vvc_cmd.action_when_transfer_is_done;
vvc_transaction_info_group.bt.action_between_words := vvc_cmd.action_between_words;
vvc_transaction_info_group.bt.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg;
vvc_transaction_info_group.bt.vvc_meta.cmd_idx := vvc_cmd.cmd_idx;
vvc_transaction_info_group.bt.transaction_status := IN_PROGRESS;
gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER);
when others =>
alert(TB_ERROR, "VVC operation not recognized");
end case;
wait for 0 ns;
end procedure set_global_vvc_transaction_info;
procedure reset_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record) is
begin
case vvc_cmd.operation is
when MASTER_TRANSMIT_AND_RECEIVE | MASTER_TRANSMIT_AND_CHECK | MASTER_TRANSMIT_ONLY |
MASTER_RECEIVE_ONLY | MASTER_CHECK_ONLY | SLAVE_TRANSMIT_AND_RECEIVE |
SLAVE_TRANSMIT_AND_CHECK | SLAVE_TRANSMIT_ONLY | SLAVE_RECEIVE_ONLY | SLAVE_CHECK_ONLY =>
vvc_transaction_info_group.bt := C_BASE_TRANSACTION_SET_DEFAULT;
when others =>
null;
end case;
wait for 0 ns;
end procedure reset_vvc_transaction_info;
--==============================================================================
-- VVC Activity
--==============================================================================
procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic;
variable vvc_status : inout t_vvc_status;
constant activity : in t_activity;
constant entry_num_in_vvc_activity_register : in integer;
constant last_cmd_idx_executed : in natural;
constant command_queue_is_empty : in boolean;
constant scope : in string := C_VVC_NAME) is
variable v_activity : t_activity := activity;
begin
-- Update vvc_status after a command has finished (during same delta cycle the activity register is updated)
if activity = INACTIVE then
vvc_status.previous_cmd_idx := last_cmd_idx_executed;
vvc_status.current_cmd_idx := 0;
end if;
if v_activity = INACTIVE and not(command_queue_is_empty) then
v_activity := ACTIVE;
end if;
shared_vvc_activity_register.priv_report_vvc_activity(vvc_idx => entry_num_in_vvc_activity_register,
activity => v_activity,
last_cmd_idx_executed => last_cmd_idx_executed);
if global_trigger_vvc_activity_register /= 'L' then
wait until global_trigger_vvc_activity_register = 'L';
end if;
gen_pulse(global_trigger_vvc_activity_register, 0 ns, "pulsing global trigger for vvc activity register", scope, ID_NEVER);
end procedure;
--==============================================================================
-- VVC Scoreboard helper method
--==============================================================================
function pad_spi_sb(
constant data : in std_logic_vector
) return std_logic_vector is
begin
return pad_sb_slv(data, C_VVC_CMD_DATA_MAX_LENGTH);
end function pad_spi_sb;
end package body vvc_methods_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D3_C1 is
port(
rst : in STD_LOGIC;
sel : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D3_C1;
architecture D3_C1 of D3_C1 is
begin
process(rst,clk,sel)
variable dem:integer range 0 to 9;
begin
if (rst='1') then dem:=0;
elsif (rising_edge(clk)) then
if (sel='1') then
if (dem=9) then dem:=0;
else dem:=dem+1;
end if;
elsif (sel='0') then
if(dem=0) then dem:=9;
else dem:=dem-1;
end if;
end if;
end if;
case dem is
when 0 => seg<= x"C0";
when 1 => seg<= x"F9";
when 2 => seg<= x"A4";
when 3 => seg<= x"B0";
when 4 => seg<= x"99";
when 5 => seg<= x"92";
when 6 => seg<= x"82";
when 7 => seg<= x"F8";
when 8 => seg<= x"80";
when others => seg<= x"90";
end case;
end process;
end D3_C1;
-- rst=500Khz; sel=1Mhz; clk=20Mhz; |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias2,
S => net5
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net6,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net6
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package avalon_mm_bfm_pkg is
----------------------------------------------------
-- Types for Avalon BFM
----------------------------------------------------
constant C_SCOPE : string := "AVALON MM BFM";
-- Avalon Interface signals
type t_avalon_mm_if is record
-- Avalon MM BFM to DUT signals
reset : std_logic;
address : std_logic_vector;
begintransfer : std_logic; -- optional, Altera recommends not to use
byte_enable : std_logic_vector;
chipselect : std_logic;
write : std_logic;
writedata : std_logic_vector;
read : std_logic;
lock : std_logic;
-- Avalon MM DUT to BFM signals
readdata : std_logic_vector;
response : std_logic_vector(1 downto 0); -- Set use_response_signal to false if not in use
waitrequest : std_logic;
readdatavalid : std_logic; -- might be used, might not.. If not used, fixed latency is a given
-- (same for read and write), unless waitrequest is used.
irq : std_logic;
end record;
-- Configuration record to be assigned in the test harness.
type t_avalon_mm_bfm_config is
record
max_wait_cycles : integer; -- Sets the maximum number of wait cycles before an alert occurs when waiting for readdatavalid or stalling because of waitrequest
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
clock_period : time; -- Period of the clock signal.
clock_period_margin : time; -- Input clock period accuracy margin to specified clock_period
clock_margin_severity : t_alert_level; -- The above margin will have this severity
setup_time : time; -- Setup time for generated signals, set to clock_period/4
hold_time : time; -- Hold time for generated signals, set to clock_period/4
num_wait_states_read : natural; -- use_waitrequest = false -> this controls the (fixed) latency for read
num_wait_states_write : natural; -- use_waitrequest = false -> this controls the (fixed) latency for write
use_waitrequest : boolean; -- slave uses waitrequest
use_readdatavalid : boolean; -- slave uses readdatavalid (variable latency)
use_response_signal : boolean; -- Whether or not to check the response signal on read
use_begintransfer : boolean; -- Whether or not to assert begintransfer on start of transfer (Altera recommends not to use)
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the Avalon BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the Avalon BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the Avalon BFM
end record;
constant C_AVALON_MM_BFM_CONFIG_DEFAULT : t_avalon_mm_bfm_config := (
max_wait_cycles => 10,
max_wait_cycles_severity => TB_FAILURE,
clock_period => 10 ns,
clock_period_margin => 0 ns,
clock_margin_severity => TB_ERROR,
setup_time => 2.5 ns,
hold_time => 2.5 ns,
num_wait_states_read => 0,
num_wait_states_write => 0,
use_waitrequest => true,
use_readdatavalid => false,
use_response_signal => true,
use_begintransfer => false,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
type t_avalon_mm_response_status is (OKAY, RESERVED, SLAVEERROR, DECODEERROR);
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
function init_avalon_mm_if_signals(
addr_width : natural;
data_width : natural;
lock_value : std_logic := '0'
) return t_avalon_mm_if;
-- This procedure could be called from an a simple testbench or
-- from an executor where there are concurrent BFMs - where
-- all BFMs could have different configs and msg_id_panels.
-- From a simplified testbench it is not necessary to use arguments
-- where defaults are given, e.g.:
-- avalon_mm_write(addr, data, msg, clk, avalon_mm_if);
-- avalon_mm_write overload without byte_enable
procedure avalon_mm_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
-- avalon_mm_write with byte_enable
procedure avalon_mm_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant byte_enable : in std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
procedure avalon_mm_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT;
constant proc_name : in string := "avalon_mm_read" -- overwrite if called from other procedure like avalon_mm_check
);
procedure avalon_mm_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
procedure avalon_mm_reset (
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant num_rst_cycles : in integer;
constant msg : in string;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
procedure avalon_mm_read_request (
constant addr_value : in unsigned;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like avalon_mm_check
);
procedure avalon_mm_read_response (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : in t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT;
constant proc_name : in string := "avalon_mm_read_response" -- overwrite if called from other procedure like avalon_mm_check
);
procedure avalon_mm_check_response (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : in t_avalon_mm_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
procedure avalon_mm_lock (
signal avalon_mm_if : inout t_avalon_mm_if;
constant msg : in string;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
procedure avalon_mm_unlock (
signal avalon_mm_if : inout t_avalon_mm_if;
constant msg : in string;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
);
end package avalon_mm_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body avalon_mm_bfm_pkg is
function init_avalon_mm_if_signals(
addr_width : natural;
data_width : natural;
lock_value : std_logic := '0'
) return t_avalon_mm_if is
variable result : t_avalon_mm_if(address(addr_width - 1 downto 0),
byte_enable((data_width/8) - 1 downto 0),
writedata(data_width - 1 downto 0),
readdata(data_width-1 downto 0));
begin
-- BFM to DUT signals
result.reset := '0';
result.address := (result.address'range => '0');
result.begintransfer := '0';
result.byte_enable := (result.byte_enable'range => '1');
result.chipselect := '0';
result.write := '0';
result.writedata := (result.writedata'range => '0');
result.read := '0';
result.lock := lock_value;
-- DUT to BFM signals
result.readdata := (result.readdata'range => 'Z');
result.response := (result.response'range => 'Z');
result.waitrequest := 'Z';
result.readdatavalid := 'Z';
result.irq := 'Z';
return result;
end function;
function to_avalon_mm_response_status(
constant response : in std_logic_vector(1 downto 0);
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) return t_avalon_mm_response_status is
begin
case response is
when "00" =>
return OKAY;
when "10" =>
return RESERVED;
when "11" =>
return SLAVEERROR;
when others =>
return DECODEERROR;
end case;
end function;
-- avalon_mm_write overload without byte_enable
procedure avalon_mm_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "avalon_mm_write";
constant proc_call : string := "avalon_mm_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(avalon_mm_if.address'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), avalon_mm_if.address, ALLOW_NARROWER, "address", "avalon_mm_if.address", msg);
variable v_normalized_data : std_logic_vector(avalon_mm_if.writedata'length-1 downto 0) :=
normalize_and_check(data_value, avalon_mm_if.writedata, ALLOW_NARROWER, "data", "avalon_mm_if.writedata", msg);
variable v_byte_enable : std_logic_vector((avalon_mm_if.writedata'length/8) - 1 downto 0) := (others => '1');
variable timeout : boolean := false;
begin
avalon_mm_write(addr_value, data_value, msg, clk, avalon_mm_if, v_byte_enable, scope, msg_id_panel, config);
end procedure;
procedure avalon_mm_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant byte_enable : in std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "avalon_mm_write";
constant proc_call : string := "avalon_mm_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(avalon_mm_if.address'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), avalon_mm_if.address, ALLOW_NARROWER, "address", "avalon_mm_if.address", msg);
variable v_normalized_data : std_logic_vector(avalon_mm_if.writedata'length-1 downto 0) :=
normalize_and_check(data_value, avalon_mm_if.writedata, ALLOW_NARROWER, "data", "avalon_mm_if.writedata", msg);
variable v_last_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable timeout : boolean := false;
begin
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_name);
-- check if enough room for setup_time if clk is in low period
if (clk = '0') and (config.setup_time > (config.clock_period/2 - clk'last_event)) then
await_value(clk, '1', 0 ns, config.clock_period/2, TB_FAILURE, proc_name & ": timeout waiting for clk low period for setup_time.");
end if;
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
avalon_mm_if.writedata <= v_normalized_data;
avalon_mm_if.byte_enable <= byte_enable;
avalon_mm_if.write <= '1';
avalon_mm_if.chipselect <= '1';
avalon_mm_if.address <= v_normalized_addr;
if config.use_begintransfer then
avalon_mm_if.begintransfer <= '1';
end if;
wait until rising_edge(clk); -- wait for DUT update of signal
v_last_rising_edge := now; -- time stamp for clk period checking
-- Release the begintransfer signal after one clock cycle, if waitrequest is in use
if config.use_begintransfer then
avalon_mm_if.begintransfer <= '0' after config.clock_period/4;
end if;
-- use wait request?
if config.use_waitrequest then
for cycle in 1 to config.max_wait_cycles loop
if avalon_mm_if.waitrequest = '1' then
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
v_last_rising_edge := now; -- time stamp for clk period checking
else
exit;
end if;
if cycle = config.max_wait_cycles then
timeout := true;
end if;
end loop;
-- did we timeout?
if timeout then
alert(config.max_wait_cycles_severity, proc_call & "=> Failed. Timeout waiting for waitrequest " & add_msg_delimiter(msg), scope);
end if;
else -- not waitrequest. num_wait_states_write will be used as number of wait cycles in fixed wait-states
for cycle in 1 to config.num_wait_states_write loop
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
v_last_rising_edge := now; -- time stamp for clk period checking
end loop;
end if;
-- Wait hold_time specified in config record
wait_until_given_time_after_rising_edge(clk, config.hold_time);
avalon_mm_if <= init_avalon_mm_if_signals(avalon_mm_if.address'length, avalon_mm_if.writedata'length, avalon_mm_if.lock);
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure avalon_mm_write;
function is_readdatavalid_active(
signal avalon_mm_if : in t_avalon_mm_if;
constant config : in t_avalon_mm_bfm_config
) return boolean is
begin
if (config.use_readdatavalid and avalon_mm_if.readdatavalid = '1') then
return true;
end if;
return false;
end function is_readdatavalid_active;
function is_waitrequest_active(
signal avalon_mm_if : in t_avalon_mm_if;
constant config : in t_avalon_mm_bfm_config
) return boolean is
begin
if (config.use_waitrequest and avalon_mm_if.waitrequest = '1') then
return true;
end if;
return false;
end function is_waitrequest_active;
procedure avalon_mm_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT;
constant proc_name : in string := "avalon_mm_read" -- overwrite if called from other procedure like avalon_mm_check
) is
begin
avalon_mm_read_request(addr_value, msg, clk, avalon_mm_if, scope, msg_id_panel, config, proc_name);
avalon_mm_read_response(addr_value, data_value, msg, clk, avalon_mm_if, scope, msg_id_panel, config, proc_name);
end procedure avalon_mm_read;
procedure avalon_mm_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "avalon_mm_check";
constant proc_call : string := "avalon_mm_check(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_data : std_logic_vector(avalon_mm_if.readdata'length-1 downto 0) :=
normalize_and_check(data_exp, avalon_mm_if.readdata, ALLOW_NARROWER, "data", "avalon_mm_if.readdata", msg);
-- Helper variables
variable v_data_value : std_logic_vector(avalon_mm_if.readdata'length-1 downto 0) := (others => '0');
variable v_check_ok : boolean;
begin
avalon_mm_read_request(addr_value, msg, clk, avalon_mm_if, scope, msg_id_panel, config, proc_call);
avalon_mm_check_response(addr_value, data_exp, msg, clk, avalon_mm_if, alert_level, scope, msg_id_panel, config);
end procedure avalon_mm_check;
procedure avalon_mm_reset (
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant num_rst_cycles : in integer;
constant msg : in string;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "avalon_mm_reset(num_rst_cycles=" & to_string(num_rst_cycles) & ")";
begin
log(config.id_for_bfm, proc_call & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
avalon_mm_if <= init_avalon_mm_if_signals(avalon_mm_if.address'length, avalon_mm_if.writedata'length);
avalon_mm_if.reset <= '1';
for i in 1 to num_rst_cycles loop
wait until rising_edge(clk);
end loop;
avalon_mm_if.reset <= '0';
wait until rising_edge(clk);
end procedure avalon_mm_reset;
-- NOTE: This procedure returns as soon as the read command has been accepted. To retreive the response, use
-- avalon_mm_read_response or avalon_mm_check_response.
procedure avalon_mm_read_request (
constant addr_value : in unsigned;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : inout t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like avalon_mm_check
) is
-- local_proc_* used if called from sequencer or VVC
constant local_proc_name : string := "avalon_mm_read_request";
constant local_proc_call : string := local_proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")";
variable timeout : boolean := false;
variable v_proc_call : line; -- Current proc_call, external or local
variable v_normalized_addr : std_logic_vector(avalon_mm_if.address'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), avalon_mm_if.address, ALLOW_NARROWER, "addr", "avalon_mm_if.address", msg);
variable v_last_rising_edge : time := -1 ns; -- time stamp for clk period checking
begin
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_name);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_name);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, local_proc_name);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, local_proc_name);
if ext_proc_call = "" then
-- called from sequencer/VVC, show 'avalon_mm_read_request...' in log
write(v_proc_call, local_proc_call);
else
-- called from other BFM procedure like axistream_expect, log 'avalon_mm_check() while executing avalon_mm_read_request...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- check if enough room for setup_time in low period
if (clk = '0') and (config.setup_time > (config.clock_period/2 - clk'last_event)) then
await_value(clk, '1', 0 ns, config.clock_period/2, TB_FAILURE, local_proc_name & ": timeout waiting for clk low period for setup_time.");
end if;
-- Setup time
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
-- start the read
avalon_mm_if.address <= v_normalized_addr;
avalon_mm_if.read <= '1';
avalon_mm_if.byte_enable(avalon_mm_if.byte_enable'length - 1 downto 0) <= (others => '1'); -- always all bytes for reads
avalon_mm_if.chipselect <= '1';
wait until rising_edge(clk); -- wait for DUT update of signal
v_last_rising_edge := now; -- time stamp for clock_period checking
-- Handle read with waitrequests
if config.use_waitrequest then
for cycle in 1 to config.max_wait_cycles loop
if is_waitrequest_active(avalon_mm_if, config) then
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
v_last_rising_edge := now; -- time stamp for clk period checking
else
exit;
end if;
if cycle = config.max_wait_cycles then
timeout := true;
end if;
end loop;
-- did we timeout?
if timeout then
alert(config.max_wait_cycles_severity, v_proc_call.all & "=> Failed. Timeout waiting for waitrequest" & add_msg_delimiter(msg), scope);
end if;
else -- not waitrequest - issue read, wait num_wait_states_read before finishing the read
for cycle in 1 to config.num_wait_states_read loop
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
v_last_rising_edge := now; -- time stamp for clk period checking
end loop;
end if;
if ext_proc_call = "" then -- proc_name = "avalon_mm_read_request"
log(ID_BFM, v_proc_call.all & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
avalon_mm_if <= init_avalon_mm_if_signals(avalon_mm_if.address'length, avalon_mm_if.writedata'length, avalon_mm_if.lock) after config.clock_period/4;
end procedure avalon_mm_read_request;
procedure avalon_mm_read_response (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : in t_avalon_mm_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT;
constant proc_name : in string := "avalon_mm_read_response" -- overwrite if called from other procedure like avalon_mm_check
) is
constant proc_call : string := "avalon_mm_read_response(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_data : std_logic_vector(avalon_mm_if.readdata'length-1 downto 0) :=
normalize_and_check(data_value, avalon_mm_if.readdata, ALLOW_NARROWER, "data", "avalon_mm_if.readdata", msg);
-- Helper variables
variable v_last_rising_edge : time := -1 ns; -- time stamp for clock_period checking
variable timeout : boolean := false;
begin
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_name);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_name);
-- Handle read with readdatavalid.
if config.use_readdatavalid then
for cycle in 1 to config.max_wait_cycles loop
-- Check for readdatavalid
if is_readdatavalid_active(avalon_mm_if, config) then
log(config.id_for_bfm, "readdatavalid was active after " & to_string(cycle) & " clock cycles", scope, msg_id_panel);
exit;
else
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_rising_edge := now; -- take a new time stamp for clk period checking
end if;
if cycle = config.max_wait_cycles then
timeout := true;
end if;
end loop;
-- did we timeout?
if timeout then
alert(config.max_wait_cycles_severity, proc_call & "=> Failed. Timeout waiting for readdatavalid" & add_msg_delimiter(msg), scope);
end if;
end if;
if config.use_response_signal = true and to_avalon_mm_response_status(avalon_mm_if.response) /= OKAY then
error("Avalon MM read response was not OKAY, got " & to_string(avalon_mm_if.response), scope);
end if;
v_normalized_data := avalon_mm_if.readdata;
data_value := v_normalized_data(data_value'length-1 downto 0);
-- Wait hold_time specified in config record
wait_until_given_time_after_rising_edge(clk, config.hold_time);
if proc_name = "avalon_mm_read_response" then
log(config.id_for_bfm, proc_call & "=> " & to_string(data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure avalon_mm_read_response;
procedure avalon_mm_check_response (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal avalon_mm_if : in t_avalon_mm_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "avalon_mm_check_response";
constant proc_call : string := proc_name&"(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- normalize_and_check to the DUT addr/data widths
variable v_normalized_data : std_logic_vector(avalon_mm_if.readdata'length-1 downto 0) :=
normalize_and_check(data_exp, avalon_mm_if.readdata, ALLOW_NARROWER, "data", "avalon_mm_if.readdata", msg);
-- Helper variables
variable v_data_value : std_logic_vector(avalon_mm_if.readdata'length-1 downto 0) := (others => '0');
variable v_check_ok : boolean;
begin
avalon_mm_read_response(addr_value, v_data_value, msg, clk, avalon_mm_if, scope, msg_id_panel, config, proc_name);
v_check_ok := true;
for i in 0 to (v_normalized_data'length)-1 loop
if v_normalized_data(i) = '-' or v_normalized_data(i) = v_data_value(i) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
if not v_check_ok then
alert(alert_level, proc_call & "=> Failed. slv Was " & to_string(v_data_value, HEX, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, proc_call & "=> OK, received data = " & to_string(v_normalized_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure avalon_mm_check_response;
procedure avalon_mm_lock (
signal avalon_mm_if : inout t_avalon_mm_if;
constant msg : in string;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "avalon_mm_lock()";
begin
log(config.id_for_bfm, proc_call & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
avalon_mm_if.lock <= '1';
end procedure avalon_mm_lock;
procedure avalon_mm_unlock (
signal avalon_mm_if : inout t_avalon_mm_if;
constant msg : in string;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "avalon_mm_unlock()";
begin
log(config.id_for_bfm, proc_call & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
avalon_mm_if.lock <= '0';
end procedure avalon_mm_unlock;
end package body avalon_mm_bfm_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity thermometersLogic is
generic(
termNumber : natural := 128
);
port(
rsTxBusy : in std_logic;
rst : in std_logic;
clk50Mhz : in std_logic;
clk3kHz : in std_logic;
rsDataOut : out std_logic_vector(7 downto 0);
rsTxStart : out std_logic;
led : out std_logic_vector(7 downto 0)
);
end thermometersLogic;
architecture Behavioral of thermometersLogic is
component DummyRO
port(
clk : IN std_logic;
osc_out : OUT std_logic
);
end component;
COMPONENT toplevel
PORT(
clk : IN std_logic;
Vccint : OUT std_logic_vector(15 downto 0);
temint : OUT std_logic_vector(15 downto 0);
busy : OUT std_logic;
alarm : OUT std_logic
);
END COMPONENT;
constant THERM_NUMBER_SYSMON_Temp : integer := 2;
constant THERM_NUMBER_SYSMON_Vcc : integer := 3;
signal chosenTermometr : integer range 0 to termNumber;
signal termometrCounter : integer range 0 to 2**16-1;
type state_type is (Start, Numer, Czekaj1, Wartosc1, Czekaj2, Wartosc0);
signal state, next_state : state_type;
signal rsTxStart_i : std_logic;
signal rsDataOut_i : std_logic_vector(7 downto 0);
signal termometrRegister : std_logic_vector(15 downto 0);
signal termometr : std_logic_vector(termNumber downto 0);
signal termometrEnable : std_logic_vector(termNumber downto 0);
signal selectedTermometr : std_logic;
signal nextTerm : std_logic;
signal clk3kHzD : std_logic;
signal clk3kHzD2 : std_logic;
signal sysmon_vcc : std_logic_vector(15 downto 0);
signal sysmon_tem : std_logic_vector(15 downto 0);
attribute keep : string;
attribute keep of termometr : signal is "true";
attribute keep of termometrEnable : signal is "true";
attribute keep of nextTerm : signal is "true";
attribute keep of termometrRegister : signal is "true";
attribute keep of selectedTermometr : signal is "true";
attribute keep_hierarchy : string;
attribute keep_hierarchy of DummyRO: component is "true";
attribute s: string;
attribute s of termometr: signal is "yes";
attribute s of termometrEnable: signal is "yes";
begin
Inst_toplevel: toplevel PORT MAP(
clk => clk50Mhz,
Vccint => sysmon_vcc,
temint => sysmon_tem,
busy => open,
alarm => open
);
led <= X"55";
Termometers:
for I in 1 to termNumber generate
Inst_DummyRO: DummyRO PORT MAP(
osc_out => termometr(I),
clk => clk50Mhz
);
end generate;
Termometr_Counter:
process (selectedTermometr, nextTerm, clk50Mhz)
begin
if nextTerm = '1' and clk50Mhz = '0' then
termometrCounter <= 0;
elsif selectedTermometr'event and selectedTermometr = '1' then
termometrCounter <= termometrCounter + 1;
end if;
end process;
process (chosenTermometr, termometr)
begin
selectedTermometr <= termometr(chosenTermometr);
end process;
process (nextTerm, rst)
begin
if rst='1' then
termometrRegister <= (others => '0');
elsif nextTerm'event and nextTerm = '1' then
termometrRegister <= std_logic_vector(to_unsigned(termometrCounter,16));
end if;
end process;
Chosen_Termometr:
process (clk3kHz, rst, chosenTermometr)
begin
if rst='1' or chosenTermometr = termNumber then
chosenTermometr <= 0;
termometrEnable <= (others => '0');
elsif clk3kHz='1' and clk3kHz'event then
chosenTermometr <= chosenTermometr + 1;
for I in 1 to termNumber loop
if I = chosenTermometr+1 then
termometrEnable(I) <= '1';
else
termometrEnable(I) <= '0';
end if;
end loop;
end if;
end process;
Next_Term1:
process (clk50Mhz)
begin
if clk50Mhz'event and clk50Mhz='1' then
clk3kHzD <= clk3kHz;
end if;
end process;
Next_Term2:
process (clk50Mhz)
begin
if clk50Mhz'event and clk50Mhz='1' then
clk3kHzD2 <= clk3kHzD;
end if;
end process;
nextTerm <= (not clk3kHzD2) and clk3kHzD;
Synchro:
process (clk50Mhz, rst)
begin
if (rst = '1') then
state <= Start;
rsDataOut <= X"00";
rsTxStart <= '0';
else
if (clk50Mhz'event and clk50Mhz = '1') then
state <= next_state;
rsDataOut <= rsDataOut_i;
rsTxStart <= rsTxStart_i;
end if;
end if;
end process;
Output:
process (state, rsTxBusy, termometrRegister, chosenTermometr)
begin
if (state = Numer and rsTxBusy = '0') then
rsDataOut_i <= std_logic_vector(to_unsigned(chosenTermometr - 1,8));
rsTxStart_i <= '1';
elsif (state = Wartosc1 and rsTxBusy = '0') then
if (chosenTermometr = THERM_NUMBER_SYSMON_Temp) then
rsDataOut_i <= sysmon_tem(15 downto 8);
elsif (chosenTermometr = THERM_NUMBER_SYSMON_Vcc) then
rsDataOut_i <= sysmon_vcc(15 downto 8);
else
rsDataOut_i <= termometrRegister(15 downto 8);
end if;
rsTxStart_i <= '1';
elsif (state = Wartosc0 and rsTxBusy = '0') then
if (chosenTermometr = THERM_NUMBER_SYSMON_Temp) then
rsDataOut_i <= sysmon_tem(7 downto 0);
elsif (chosenTermometr = THERM_NUMBER_SYSMON_Vcc) then
rsDataOut_i <= sysmon_vcc(7 downto 0);
else
rsDataOut_i <= termometrRegister(7 downto 0);
end if;
rsTxStart_i <= '1';
else
rsDataOut_i <= X"00";
rsTxStart_i <= '0';
end if;
end process;
Next_stage:
process (state, rsTxBusy, nextTerm)
begin
next_state <= state;
case (state) is
when Start =>
if nextTerm = '1' then
next_state <= Numer;
end if;
when Numer =>
if rsTxBusy = '1' then
next_state <= Czekaj1;
end if;
when Czekaj1 =>
if rsTxBusy = '0' then
next_state <= Wartosc1;
end if;
when Wartosc1 =>
if rsTxBusy = '1' then
next_state <= Czekaj2;
end if;
when Czekaj2 =>
if rsTxBusy = '0' then
next_state <= Wartosc0;
end if;
when Wartosc0 =>
if rsTxBusy = '1' then
next_state <= Start;
end if;
when others =>
next_state <= Start;
end case;
end process;
end Behavioral;
|
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
signal x, y, result : std_logic := '1';
begin -- only
result <= x;
result <= y;
process
begin -- process
assert x = '1' report "TEST FAILED" severity failure;
assert y = '1' report "TEST FAILED" severity failure;
assert result = '1' report "TEST FAILED" severity failure;
report "TEST PASSED";
-- x <= 'U';
-- y <= 'U';
wait;
end process;
end only;
|
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
signal x, y, result : std_logic := '1';
begin -- only
result <= x;
result <= y;
process
begin -- process
assert x = '1' report "TEST FAILED" severity failure;
assert y = '1' report "TEST FAILED" severity failure;
assert result = '1' report "TEST FAILED" severity failure;
report "TEST PASSED";
-- x <= 'U';
-- y <= 'U';
wait;
end process;
end only;
|
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
signal x, y, result : std_logic := '1';
begin -- only
result <= x;
result <= y;
process
begin -- process
assert x = '1' report "TEST FAILED" severity failure;
assert y = '1' report "TEST FAILED" severity failure;
assert result = '1' report "TEST FAILED" severity failure;
report "TEST PASSED";
-- x <= 'U';
-- y <= 'U';
wait;
end process;
end only;
|
-- ********************************************************************/
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: PRINTF SUPPORT for cores using std_logic_arith or std_logic_unsigned
--
-- Revision Information:
-- Date Description
-- 01Sep07 Initial Release
-- 14Sep07 Updated for 1.2 functionality
-- 25Sep07 Updated for 1.3 functionality
-- 09Nov07 Updated for 1.4 functionality
-- 08May08 2.0 for Soft IP Usage
-- 22Oct08 3.0 Moved into SVN Properly (TEXTIO Project)
--
--
-- SVN Revision Information:
-- SVN $Revision: 3758 $
-- SVN $Date: 2008-10-22 01:56:45 -0700 (Wed, 22 Oct 2008) $
--
--
-- Resolved SARs
-- SAR Date Who Description
--
--
-- Notes:
--
-- *********************************************************************/
library IEEE;
use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package misc is
-- synthesis translate_off
type INTEGER_ARRAY is array ( INTEGER range <>) of INTEGER;
subtype NIBBLE is std_logic_vector ( 3 downto 0);
subtype BYTE is std_logic_vector ( 7 downto 0);
subtype WORD is std_logic_vector (15 downto 0);
subtype DWORD is std_logic_vector (31 downto 0);
subtype QWORD is std_logic_vector (63 downto 0);
type BYTE_ARRAY is array ( INTEGER range <>) of BYTE;
type WORD_ARRAY is array ( INTEGER range <>) of WORD;
type DWORD_ARRAY is array ( INTEGER range <>) of DWORD;
type TIME_ARRAY is array ( INTEGER range <>) of TIME;
type BOOLEAN_VECTOR is array ( INTEGER range <>) of BOOLEAN;
constant ZERO : DWORD := (others => '0');
constant ZERO16 : WORD := (others => '0');
constant ALLONES : std_logic_vector (31 downto 0) := (others => '0');
constant UNKNOWN : std_logic_vector (31 downto 0) := (others => 'U');
procedure waitclocks(signal clock : std_logic; N : INTEGER);
function to_std_logic( x: UNSIGNED ) return std_logic_vector;
function to_unsigned( x: std_logic_vector ) return UNSIGNED;
function to_std_logic( tmp : INTEGER ) return std_logic;
function to_std_logic_invert( tmp : INTEGER ) return std_logic;
function to_std_logic( tmp : BOOLEAN ) return std_logic;
function to_std_logic_invert( tmp : BOOLEAN ) return std_logic;
function to_boolean( tmp : integer ) return BOOLEAN;
function to_boolean( tmp : std_logic ) return BOOLEAN;
function to_boolean_invert( tmp : std_logic ) return BOOLEAN;
function to_integer( tmp : boolean ) return INTEGER;
function to_byte ( x : INTEGER ) return BYTE;
function to_word ( x : INTEGER ) return WORD;
function to_dword ( x : INTEGER ) return DWORD;
function to_byte ( str : STRING ) return BYTE;
function to_word ( str : STRING ) return WORD;
function to_dword ( str : STRING ) return DWORD;
function to_integer ( din : std_logic_vector ) return integer;
function init_data( seed : INTEGER; size : INTEGER) return DWORD_ARRAY;
function init_data( seed : STRING; size : INTEGER) return DWORD_ARRAY;
function maxval (a,b : integer) return integer;
function minval (a,b : integer) return integer;
function absval (a : integer) return integer;
function muxop ( s: boolean; a,b : integer) return integer;
function is_hex( str : STRING ) return BOOLEAN;
function to_uppercase( c : character) return character;
function onoff( x : boolean) return string;
function notonoff( x : boolean) return string;
function decode_params( str : string ) return INTEGER_ARRAY;
procedure getstring( para : out string; str : string; pos : inout integer);
function debug_level ( x ,y : integer) return boolean;
function to_01( tmp : std_logic ) return std_logic;
function to_01( tmp : std_logic_vector ) return std_logic_vector;
-- synthesis translate_on
end misc;
-- synthesis translate_off
package body misc is
---------------------------------------------------------------------
-- Handle UNSIGNED to std_logic_vector conversions
--
function to_std_logic( x: UNSIGNED ) return std_logic_vector is
variable y: std_logic_vector(x'range);
begin
for i in x'range loop
y(i) := x(i);
end loop;
return(y);
end to_std_logic;
function to_unsigned( x: std_logic_vector ) return UNSIGNED is
variable y: UNSIGNED(x'range);
begin
for i in x'range loop
y(i) := x(i);
end loop;
return(y);
end to_unsigned;
---------------------------------------------------------------------
-- Miscellanous Conversions
--
function to_integer( tmp : boolean ) return INTEGER is
begin
if tmp then return (1);
else return (0);
end if;
end to_integer;
function to_std_logic_invert( tmp : INTEGER ) return std_logic is
begin
if tmp=1 then return ('0');
else return ('1');
end if;
end to_std_logic_invert;
function to_std_logic( tmp : INTEGER ) return std_logic is
begin
if tmp=1 then return ('1');
else return ('0');
end if;
end to_std_logic;
function to_std_logic_invert( tmp : BOOLEAN ) return std_logic is
begin
if tmp then return ('0');
else return ('1');
end if;
end to_std_logic_invert;
function to_std_logic( tmp : BOOLEAN ) return std_logic is
begin
if tmp then return ('1');
else return ('0');
end if;
end to_std_logic;
function to_boolean_invert( tmp : std_logic ) return BOOLEAN is
begin
if to_X01(tmp)='0' then return (TRUE);
else return (FALSE);
end if;
end to_boolean_invert;
function to_boolean( tmp : std_logic ) return BOOLEAN is
begin
if to_X01(tmp)='1' then return (TRUE);
else return (FALSE);
end if;
end to_boolean;
function to_boolean( tmp : integer ) return BOOLEAN is
begin
if tmp/=0 then return (TRUE);
else return (FALSE);
end if;
end to_boolean;
function to_integer ( din : std_logic_vector ) return integer is
variable xv : std_logic_vector(31 downto 0);
variable x : integer;
begin
x := 0;
if din'length/=32 then
x := conv_integer( din);
elsif din(31) = '0' then
x := conv_integer( din (30 downto 0));
else
for i in 0 to 30 loop
xv(i) := not din(i);
end loop;
x := conv_integer( xv (30 downto 0));
x := x + 1;
x := -1 * x;
end if;
return(x);
end to_integer;
procedure waitclocks(signal clock : std_logic;
N : INTEGER) is
begin
if N>0 then
for i in 1 to N loop
wait until clock'event and clock='0';
end loop;
end if;
end waitclocks;
function to_byte ( x : INTEGER ) return BYTE is
variable x1 : BYTE;
begin
x1 := conv_std_logic_vector( x,8);
return(x1);
end to_byte;
function to_word ( x : INTEGER ) return WORD is
variable x1 : WORD;
begin
x1 := conv_std_logic_vector( x,16);
return(x1);
end to_word;
function to_dword ( x : INTEGER ) return DWORD is
variable x1 : DWORD;
begin
x1 := conv_std_logic_vector( x,32);
return(x1);
return(x1);
end to_dword;
function to_byte( str : STRING ) return BYTE is
variable str1 : string ( 1 to 2);
variable x : INTEGER;
variable dw : byte;
begin
str1 := str;
for i in 1 to 2 loop
case str1(i) is
when '0' to '9' => x:= CHARACTER'POS(str1(i)) - CHARACTER'POS('0');
when 'A' to 'F' => x:= 10 + CHARACTER'POS(str1(i)) - CHARACTER'POS('A');
when 'a' to 'z' => x:= 10 + CHARACTER'POS(str1(i)) - CHARACTER'POS('a');
when others => assert FALSE
report "Illegal Character in the Hex String"
severity failure;
end case;
dw(11- (i*4) downto 8 - (i*4) ) := conv_std_logic_vector(x,4);
end loop;
return(dw);
end to_byte;
function to_word( str : STRING ) return WORD is
variable str1 : string (1 to 4);
variable dw : word;
begin
str1 := str;
dw(15 downto 8) := to_byte( str1(1 to 2));
dw( 7 downto 0) := to_byte( str1(3 to 4));
return(dw);
end to_word;
function to_dword( str : STRING ) return DWORD is
variable str1 : string (1 to 8);
variable dw : dword;
begin
str1 := str;
dw(31 downto 16) := to_word( str1(1 to 4));
dw(15 downto 0) := to_word( str1(5 to 8));
return(dw);
end to_dword;
function init_data( seed : INTEGER; size : INTEGER) return DWORD_ARRAY is
variable xdata : DWORD_ARRAY (0 to 4095);
begin
-- In case there are any 16#FFFFFFFF# type constants Causes VSS to complain
assert seed>=0
report "INIT_DATA with integer Seed cannot be negative"
severity failure;
for i in 0 to size-1 loop
xdata(i) := to_dword(seed+i);
end loop;
return(xdata(0 to size-1));
end init_data;
function init_data( seed : STRING; size : INTEGER) return DWORD_ARRAY is
variable xdata : DWORD_ARRAY (0 to 4095);
variable seedxx : DWORD;
begin
seedxx := to_dword(seed);
for i in 0 to size-1 loop
xdata(i) := seedxx +i ;
end loop;
return(xdata(0 to size-1));
end init_data;
function maxval( a,b : integer) return integer is
begin
if (a>b) then return(a);
else return(b);
end if;
end maxval;
function minval( a,b : integer) return integer is
begin
if (a<b) then return(a);
else return(b);
end if;
end minval;
function absval( a : integer) return integer is
begin
if (a>0) then return(a);
else return(-a);
end if;
end absval;
function muxop ( s: boolean; a,b : integer) return integer is
begin
if s then return(a);
else return(b);
end if;
end muxop;
function is_hex( str : STRING ) return BOOLEAN is
variable ok : boolean;
variable str1 : string ( 1 to 2);
begin
ok := TRUE;
str1 := str;
for i in 1 to 2 loop
case str1(i) is
when '0' to '9' =>
when 'A' to 'F' =>
when 'a' to 'z' =>
when others => OK := FALSE;
end case;
end loop;
return(ok);
end is_hex;
function to_uppercase( c : character) return character is
variable ok : boolean;
variable cuc : character;
begin
case c is
when 'a' to 'z' => cuc := character'val(character'pos(c)-32);
when others => cuc := c;
end case;
return(cuc);
end to_uppercase;
function onoff( x : boolean) return string is
begin
if X then return("On");
else return("Off");
end if;
end onoff;
function notonoff( x : boolean) return string is
begin
if not X then return("On");
else return("Off");
end if;
end notonoff;
--------------------------------------------------------------------
-- returns no of params, para1, para2 etc
function decode_params( str : string) return INTEGER_ARRAY is
variable pos : INTEGER;
variable PARAMS : INTEGER_ARRAY(0 to 9);
variable i,x : INTEGER;
variable ERR : BOOLEAN;
variable BASE : INTEGER;
variable c : Character;
begin
pos := 2;
i := 0;
ERR := FALSE;
PARAMS := ( others => 0 );
while str(pos)/=NUL and not ERR loop
while str(pos)=' ' loop
pos := pos+1;
end loop;
x := 0;
BASE := 10;
c := str(pos);
while c/=' ' and c/=NUL and c/=',' and not ERR loop
case str(pos) is
when '0' to '9' => x :=x * BASE + character'pos(c) - character'pos('0');
when 'A' to 'F' => BASE := 16;
x :=x * BASE + 10 + character'pos(c) - character'pos('A');
when 'a' to 'f' => BASE := 16;
x :=x * BASE + 10 + character'pos(c) - character'pos('a');
when '#' => BASE := 16;
when others => ERR := TRUE;
--printf("Illegal character POS %d:",fmt(pos)&fmt(str));
end case;
pos := pos +1;
c := str(pos);
end loop;
i := i + 1;
PARAMS(i) := x;
end loop;
if ERR then
PARAMS(0) := 0;
else
PARAMS(0) := i;
end if;
-- for i in 0 to PARAMS(0) loop
-- printf("Got %d",fmt(params(i)));
-- end loop;
return(PARAMS);
end decode_params;
procedure getstring( para : out string; str : string; pos : inout integer) is
variable i,x : INTEGER;
variable ERR : BOOLEAN;
variable BASE : INTEGER;
variable c : Character;
begin
i := 1;
ERR := FALSE;
for i in para'range loop
para(i) := NUL;
end loop;
while str(pos)=' ' loop
pos := pos+1;
end loop;
while str(pos) /= ' ' and str(pos)/=',' and str(pos)/=NUL and str(pos)/=';' loop
para(i) := str(pos);
i := i + 1;
pos := pos + 1;
end loop;
end getstring;
function to_01( tmp : std_logic ) return std_logic is
begin
if tmp='1' then return ('1');
else return ('0');
end if;
end to_01;
function to_01( tmp : std_logic_vector ) return std_logic_vector is
variable ret : std_logic_vector(tmp'range);
begin
ret := ( others => '0');
for i in tmp'range loop
if tmp(i)='1' then
ret(i) := '1';
end if;
end loop;
return(ret);
end to_01;
function debug_level ( x ,y : integer) return boolean is
begin
if x>=y then return(TRUE);
else return(FALSE);
end if;
end debug_level;
end misc;
-- synthesis translate_on
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
RhrbwOyJB1EkxOJx3ABqRk3Va+7K3EJHZVPGIcCoGsSMnOOGWH7q6VzPOfjcK/djKPO6aFBoil75
jQwswaRRUQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
LCTlbuF/Pe5PDxJKJwDmFdDkdDk19GHdt378mO/YQltflOygDhr11gCVrBzfYS02NHqaPd5/bySu
7JQ7BQOeRxRaz6kOAXIywiBhmVX21ozJpSD9YWX++cpoX2Hzx21vie7VHdBuVCd3dcSrAK02PIh3
KQYQ85S2o8AzlKpsFk8=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
o83p4yh0oTgLDG7Xfc1wgs4jILGH1Afuo6ZEi3g5oOtKQrlkia8l0l+AzK0CZN6geQVbN9v3By8i
WzYycokm0wzcIz9ice0LtKeT+ax0xhsgQnz9Qm7joJjyaXidfkKiDSXWs9qUO/5yg0ocMCtuV6Vy
X+oPc9kihxC2JoIOAIk=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qFbja/sHwn/4C9HJKO6mwiiXixbKvz/pY0uQwgBSvdDvsJnVpURPIZcd/6cPrjI7jCb2L2ZYUxjo
OD7e66fAIQ4Fg//zuIIx29BHdcBxENfBwvxV9WMdbgO5JbeM8TDH7sUVg1FYVW1Cj6XD20DFLK2d
vwOuv58tfuLH1qA2IJy1LreXjKAfnSYwXNNgkWsLHf0HNlF1BLaq0ZYOS35wQ0+LX50oyZIXCr+N
JkR13JyuCDomGP7fERuhdzE04K1CdRn3rjEcsxYOwLOnB0SPSbBj4lBx4ONU0cfvWBzoVcsVMIbP
m/ybAvJlXM/GrDa69R8Y8Ovx05heeJoR5H+zQw==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
fvKvImhKuX4Y0Y6AUieBoEW5oZj1O6zYwY/+HHrKkKgaM1CnSrcODNJTpm8quvRi1mZX7OA786d3
2FySSCAI7NmYiW1tWydoja+l00gQTFMgW/UrwN5E4V0JowxqUF1iu1epVZ+6x/e25PvEtYJ6tlHd
B50G3sCwsdy49pORs80wHiIjPV81HJpnQ5cU2wNr9Sym935FvXHSrzPAmhKxjh0sRZWkS8X8pJFE
3vES6QHURg+O3x6fyl1zEzCdtoS5kk4U4rMYiK4DGLZiLIBWYSb7RUzVsPxP0Ad6390hx+wSZ+hX
AIvESkLWW8PZxdjlqiH5uMh6bSBOcXXXu8FeRw==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rx21WDVFigb5iRNmq/GF+n+tT8sAt0anxbVCjDKiva2zVerqHXLBxWwmIo8ZDwgQwl6kPSNATurf
wsLl3xuYZbupRQiXSV62L2j7uhoTg5gdexW3J3ZgJbqydyznH8end92RJqs7XFidLZ11oY+sBEX2
WZZFU8tlC1UZmwKKu4UKUHOIm6wu0Nuh+yeD4yP6OiKmRBn9y40bNX6p56LkCggypHithHpqzIuX
hkij3oeZERvwFCR1LaKtiFF2zdqXORGlBWM0qYixWDF+Q8LzHHgalXIl9W7A8JdruB/VjFtsacGQ
bADNP9K30JY7Cl4D9OCU6Jq1EhIksCcjUkhB3g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 119040)
`protect data_block
aI7bWNlUNY7c3ZGc2pBm9hopUS7X9dogWjraYv5tIlivzz9gczwsyTYslt2YnJ+/LMUD0nXdKdYR
pIOJo/aWGlROGQNyxtDvDPMgCW7a4DPe4d2FZKyxCYU+CQOcwKyYKPMu//M4Nk07v5nerSVaQ7Le
OdKRx8fLib7Mqz+v6M2QfuG4WiAH5mEZMrMYGvNc6cM6lzrDDv3Vo7a4QH+HgtmYndaMRsWTsgUV
LCdDYAfRyVZLLHoT5OUk/Z+g6Wev9BpvlH1harOy8yu2V1ObxlXarhHEAUtInUsg+xmZa3/gDaEd
h0y4u1D1dYYk5K3bwsKZ7TqH9qG0MuGogByVHGubD9Wbf6bbWI+tfdCRfFRkuAlRANSEycVNfo3P
dvDLoCKNv+fqlqATA/DirJlE4aeX1FGHg/Sy0vJnD4eqTf8y4RO34KE6Pvb7M0PRmAy5XsRDV4Zz
ZUHzpVCDy0rQl5XPvf30t9DFPzgQ6FM+B8uy3eZDgxX+LPa3HTzWL9755yXRXxMtu8bA+7kuAIQe
w2vRvE9w3z8vs0PKdYqKQprhC+fJMG09cL4BrJdykfHiJNBtr/bBq+WSSVPZfZb3NZri+LVtlQ5W
jHJMYlSNitgjITDwAPMvlQQPz629GFt5O2ia7KgOuPF+6iQuXxZY1RCnj3kp6HEugTHcoaH4w7Vj
JXDcb1BaaqKm+Yai4kOYJmC+zhD59QujL5xgv9Rck1BDQgnz/s0hnxDtXCAVBiVUOinMSofPVpG3
Oh2elmXIbFm6Q73lpwzNFJEtQl5cQRg1up1wHrTJ5aZHJSP05vyv3UJQxKd6uQd/o3uRyBgiHWt0
65f89jvOJbql9IsL/CjV+STNpy9RICtYTtbzPVXcxodX8MKdhg2RA8UC+WYoOGc2lMAi1lH75FC4
LP1jaW8BNDH7US+A58TU+vyCzp9xaemgiaHwAYTUj7Rvh/K0cljdPIW+FZmDXdq/YiiR7yHG4S9b
UwpePm30esrpmCzC4N+NWeuhdgHFuYCfP/IfyDP2jtD4vyiEB2evaMbpsSMPK2jbwI/thbF5ZesW
FOFifXwxCksovXO8BfY8ss7Wtmwg/ZGOr78cnYtbJvTKoGIFklrHDTzADmyqQVnBclXwVcWdG/oL
BWoUPqGuQ6ICIW638WeVvTLsShCmHFhE19G8gETeeBqmaiN9OwIuBx5Wbh4W1V0HF3iGSe3rGRxm
h01hav/EkgtONJYaIq73OYEH/5d+BvW94TomD7n4YQvzARdLreD+xrHNKOlnPBP7mWiNiRpR+MUG
0utyazgOV/G8ymwzMEVXEavYeXP0sVR9PAvJOvm/56pM+q3i4iYZ0qJbHgA0hoKf8L83AghefJwu
4bYMPpHTLsAAnMLQsKtuwcLTmYKsiCZBl0lAPGoh2R76nFVB53R9rx1L4sKlAbUV2pxWQRGDpPNy
IquA42Tm5Hc6cLxV22yKiugnVBmKxq3bphkP2K5Bf7iHhSM+MjJJ5PMtMS6C6bQqdoMeV6Gt1c5x
gl7fcm97rx1LiFjx1m8K48Mznqs9zgH0t4NUU2QjTy0gNYiTx70fny4lBuAHVAknqUvzZqUKfXrz
D18b/rSoCRLFHNo6zLqi9d+6PsJSvctXBcm990cHlx9gNKrz8hKpbLQLAeLxtIq9lfFvSesEVTPI
HAj6jqi818uv+cD3r0HmWj4Mj6WzLQqgFkEUtfB0vUl7HKzYdKaTcDq5aSmsRj8DFP5Ry8K/c0VF
4LTTdrG8vPku40J4p6oH6LDVs8n6J0+FPbs+B8cPSJJoF+ebe9Fg1xWIwNzRVYS3Ren8vMxtjka1
nX6eZOa99Ll/+gYuxI7vXo8L1LhsBhBUyOjBvGjZOZcV1VqwqYvuLlUxEwsYWGxl0rj1cbHiaJz2
lLq5LNQKn0FESAOs620rUNwEtn08Z3Cg7VtBd+SdFQomlmpzyDGFU54j39yIKP7EFPhB5FfSzIUU
lsaAF7qCCucRTipNYbD5g+vmeTiD2X5HDgmgoc3aBw5RG4T0/CiZzPBNIcz7NFNyTedmE+1HJI3q
x2gIoEqfmbTKzw9h7pokjXsPZB5CplrStcimcWaiASptWEISNoonrCKFffatvIbK/QVumWT2yOrp
J0AcwsaExOxt9CgrNtco2RZrszF1Vq3bTB/KLwQATNoNYR4N+S8WAYfUyM/CK6dObGw6Nzj0Y0ML
6eAztsoaDfnsVo3N+gVIOFNA4Itc0tQA/dWMeNt9phrAX6LJqWZi48I0rjpIw1dYq/LGsr0M0D0c
ZIPqb5fWAf1fnVCIgr5MP7QIncykiPJ7Zs/J2Lo+gLrGCs2FvhACYdl7ub1a/Pe74Pn3HdytiBsm
pMPA5WhXo9j4nTnt1/CsELRA6JoduqGWStAQdcyr8GUWo0Bg5NrGU8X+9R3AXd7L5F0RDpqOxblq
GldFv6ZaB2uBsfPqNYtiwonIPClfUYbvDFUSzj3e3LK6by4aKV910o+qsaBtfkOyz4/i8s9ETCJG
RhYTq3EeGvg6Ql/5zjFyslGTZm0C2vFxM6V20BttR1vV6Yw1JA1pLBr8vod6tDA5/2qgRWN03r/a
W/tswr7+KaqiOW19hmvweCAGiHkH+eesnYCTZuzfwI9HMAwhfIdikIuvxv6k58vS42oFcO8td5eB
EMFTLMcmiJoXMbm0nS0zbrZA7GogD5oSRH02bW8KXeT+T/GOrPP+MgGxpSr2fWe+3tUXIXpy2qG1
5zkweA/aY2Dz+dPz7rFEUnR/oIQZV9ngVa58o0xQ6EcbmhfiqCPaa19WaMFnon/dwIs1E7VtpVO3
bHgLCwXMoizr3J/ZZZSy9cdUr3hdjNFqnOO1zgIrBbcU8b+rTr2Fbwkr3yF0+iruXhYMTmv6je1H
OHoFYAfzrcvr2K0ha8TOXU35kQ4iHSzKXOScp7FSWizIjdrwoNDg5STCdV8YRLVF+QClpOeNuIOg
yx66l7Ok5OATJdfxQymZNxhDrLM0PnouDA6jJd9yrDcrNEja404uFQEB37OFNhNSJ+5/OVnXB7VQ
+v3kBBU/iWLwSYs4+JSQur2H/cHVixyHYBKWXgiH12k4wNOPhGRx8sIxk+xZfuHhwg6r1LBq+2L1
5Nh6mEx58l4tJdy65zh/GexHxdBFB5eZh5mBHss0MrHZqu0EL1JgiqbSzcs3QX1xZXerdyNUnbHx
diLMmSGhKR+ZLiPnx2cItejFRM17SYDc5t/i5iCM46Ei0I8U+v/Cpe3Yw+OTdNhvjt9QQKuhLubN
8+pxnX7eRCFN5Zdp1p5S1YDucsGnYI0hudU67Ot9mDH9N8Lh1Pqlj4OnUoY9ak2ZMC6zESPdL8Ey
UyFwljmHNbCd2iH5tutiOLc5qkJtgjbboZj0bWEo/8yWvQys7mmp5Ts9gDFcRPkpMkizITlxkbBC
I7VGbgagUttzL6TJgA5+T3YcbEKDbYjLMFkQL3LWljL2pvGZzF+HecWv0dLltcGqjlQPmUPwJwoP
bq7lF17szD+91/FS4YDEAZhRJqORL3uz+o+d/pFFetxQiAImbX7IZ4eHMCYV3j8XIHjyJJcKqTRB
0v7pAPV1bX9yb0dOZ2oDwf8GPRGRvo1RRkCzhwa5G6Kfn+ScZywr4IGXHkQ0Pl2yRTYEdC9yz4qU
3JK6lKgqmqOcaLfp2YSg190BzeQeJsEGRf2A9cHdZkTakngKj1xHQO9+E3uMkJjJv3jXho/aZN4w
EFaT0XYgkCEfU7oCkUn0Obv5oQ0oCuxQ1PkVL7aqeiUL8QhoD0RkGOCt7faSpw/tUuAwvBA1icKR
Ia9muGExd88VN3TjbcvaTruYnCZ7XE3HBNcJw3UB5En6gDFDGBJ7ktJpAHTBQ9/uFawBi79Q38VK
LQYoLCn4WODfNyy9Ang5RxojMcZcBXSziKyZL6HlQ+9C9kitYesx9juQHr4G57CoAFBteKlMFrxr
Ki19ujOxu2lwnESO6Aev4kvlg/8tB85vt4cmG9l1SPPNlvi2J2eGZVBFRyTZGETF+YrdMAmV9s5k
95hjAWGG65R1rA9XQEImyazL5An9vwweUzsbj1WSqfH9KSHE7cx+y/ONtcJ+VeC7MD8qQCaEUJ3F
rnjSXu4D48d8a52/deybiqEp8eQaZ3wd2TeTs96gE78mlWFy9bx0x0jUhfUrzOlsW45frs3YARbj
p3tKehq3Y2bg2nF8YDaRYpiRTFYmVWSrI79zvQ2BI5j/RONzH8EwiDVNmjrNeC66AXCx7MKcp7ET
tsV27AL0GYF7w6bTTv4yLi3flNr+6MkIJUCVBbvhUMQvGYG70rZ4uK7uxtBpYCQO8KrJjju/569U
Cl239/ROV0qTn5ieoy9xqus+YKR7QzooxY4jlxgU/Pf4pJeLsrfKtqepWJ6KgNk50/9NtNmBjK78
FVBZbN7INXVlcgCWmiTh7fPp56wo24PEd3XbrEbtfPprjr3HsC/dYuhfaTrpFSy3PrtzeiCkanBX
JO9TCiEWsSvnu0oxEUhW1g26Uphm2zTw8s1+3rI7oRd06bkcivoIqJhXtv2F/fnGGxfT/1jCJlm0
BkscXgBjN47TLc2Qk6fVYhUMr4I5F99Poy0eG4IfUqi1lXuSg2bQNI5HZLQAhdl4jIWh6z/REovV
1/z0OCSbudd3tqClDYwpsefk6SYLSoWDH1Yb2NPlAyi8jkdsXoG65kn7vunvc5xzeEU/FXc1q8Wm
vEUS/F6faHae3qnD4Hb+jo8hzZX6BIhTyVfootR6yJccvZRdR3tUzNMUYTAe25WrB1lCIGh//7gR
n23/fOPm7fNLayIqxpwOLwJeghnqZSljtSsi3EE7aY+we2wS6pRn0g1g7ZzhRJD2r6KzBKLUIihR
B04YZgM8wcX2ddArD5ZrwNvRbwxuYj7vu1cWVmp6+sBD3bktfkCqhIx3b0ZF8a6I7h9x5V+cGjKK
VzkICzY8350nkEutXEIp/jwByf9Y9hXJWbaGOxba8lF14FvXU8ZqV9H4ZWXR2HwpBafxkQegr5cd
U4XIiIpwwvMwFDhqgRe0S0AEvDMfhQQ9EHyUDH1qffSqaUR0nc6F+Po2QJaK1QHzsPxmx5oHUzFt
a8YN9YdPwh6pg5NqNCoxdogyx2uhZx1j0uiKuAcmkGWn1WvucC96WzfMxLSbNhJnopWQg3eSoVJr
bDJilycM0+Wom/CwM1GC5IQwEim+6Q+NTtsw7m1tHCvmBCWsF0Q8oSxw1tjMsapk2RY9l8j2kP7w
6uPP7IQnHq+ha+/7N2eMjYhzouEtL29A9/4np1XhWDgYZ5pBJq8DDRSGOdNJqcy2HbQE/fKTDfds
FAc4yACFHGG22yxD5OoD/ibLGR+zad4WSIKT4sb4b6si7wXptvekygVLb8i0/honnC40zopWpEQb
/xVhFEh34169FdeG9mW2s88L3lQQGS/NkuRraV4ZZkdZTZ//nN0XanGxoePB8TXNjK1Z6HSlcX2a
f8yrVJs47WXgj/pWPrDawMdEHeUGBecMfUmgWJIDQ3eGcihaz3XvbDz3GT/I3WFcElGFWf2bmbV7
esBQVWUzLrQk92AqueeRH0fPz8yK9l6Q1oISDVMnP57DxhaXlBUINa1tzzzY5CcG9DHKYBUcT96T
idRrxNJ3lAlpz7g5/KIP6yHgvhJYxpdrPWQNxVEOqjxJM0jrLEYcnPBteFE5j5Js3DO1vp9JGm7M
GrH32j5berycy4I7THaGj702gmwsv+gomgl28sZYBbD+MnwUnJZmWjcdltvosp077NXZH+62AHe/
RGDqXM0woIcAHEQf10BZEr03vecsHCFKE1PbSyWKVTw55qF7zfViwvHbvsQ+cnzbGqGaiU4yuZGO
tqVtc7d74CcKkcuWWqyJ12AtceV94Qzox0vj6kdDx8FNTyG4x8hFluzRdPPOJ5JTWsI0U2SdOWwg
hzUTytZ8MBMlogWSArWswaPX5TwVEgcLVtTv3STzy3b9UQaT3W3gZg00LUPXQJ1dyMyHf9T4BB1E
YzsLJkfWykMFXRUy9Kzt3fBD5qhFdL0d+ow4Qj4SaU2p9+BNGwIWNnjmvbzimamM+FPk7CYsmg8i
PXcPDIicie7+xEkq5LaY1EdKcayDBjkFHxKcQyQ+1Ul+I04IdMRXvH/s8bqaMxtOxxxfrIl5aaDl
6x6U7kaLTkJEwzi/X19JfIlhfZJLQa+fy24n70Eb8fSBIbmSBedmRtj192zN+Pc5UCaL/Eh1MkAP
k17rsPlMxQXGFk72T0Y+4mMK9c0c786/bVPbHAsc+jlu58vSatBET3NLH/jPNRys55a6f/vihN0F
tI/3DYEjdKl3Pvx6JUcLAcHWVkSf+MV68XgmCnv2G+tPEf6jJvORsExBvM84QhEoRgqKCFsV2TfM
wuSVa0OlFShzTy2iZNd46IEu8thpoQ83I1x4TceCr481lKbmiO16bgXt9u9hApDkix35vY08jz+Z
tLZ9zwr4hpjvGHh8/WDtkQBlJw5Bu/uks7BbDqIZAmLq9UcMtT5BsfkleyJTYGKRmuSLLRn5qpOG
3B4R8YT2AsNtakYRh97PQcIwQAkWCa7PvfKHGyAlp9G4IlKH66aYAHWVDlxMtqVcDBXetY7BWclc
8tlFzOVOKwPJ3Vy97TS3AdR4nH7Ga0PcocRdGMk7YE1z5M+bEfWPG5Yt4Ou8oaEUkuPC8bPDRdzZ
VMIJDc2KG856QKUJnFAEgJTLV3zHwukr4Xf1ip2PrHIA3jtyBXXzKOvd58kD0xdvKJlmQmZ7LSdC
CNzImHzgpH+n6OniwVQvDY71qwJST85PsYRzHzUkpUNyF8UNrNbzdrXfrmCDCkPtJOYOQjc2hHc9
RC6OJd3Q4eXz9vfuIC0Tuq8sBlQ0VC+QTfKZ3Qd41sWceMemw7GlUjiZ6O8+YMOwL48/zi8ScvTw
KRVzz3qWtVoK/By4o4K/QWD1BHZzSpNrvHUXuc/7TvYj9oeluYYnn4H9tZ38PYPjE6bEg5z082MJ
usy0WdhZPuhNxI7U4wbUkOf+gxajXOQ2DNpyzDh8XGSXIb8FRNClrYWQJMSQ9pirNiA7vAlxFvqm
BAkEYzh+JlhZeL0YJzfomofEX1DOatO8s7ysexTTovEnVzm26AjipWiPHT4vP2mRmYHcfDZmAYwR
wV1xPvsh2BPcbVa0sM2SErEXgOQ2ESk8vRxw4I3+q7n2rQ1NrkHBeJrveRcnFfLUpPbrUi44Jb+A
LH2XeJoTeZHHFkTpL3ejttjiKuCE/sJTQ6jq9FKZJcmMJVqftLkHCaC4hNi4ciB4vk6xuYzzU9Nz
8YlkHDfz13/5zZnmr3p7sjD1ZqiXnyH5H0nkPkbtYGbHwKDYUa6dKN/8vr3UgLZda/JPnKDacNxg
OuEmdRcZzyJWix0ct1OhgMMDIBBX/FEEYzw504SgSzbrZynHMmm9O90jPNH6yriqJLwHxZCsJXeq
wSU0+q4R27w+C6hvYzMgZ40/l73kMujW26bqvuuSdO3p8lspsG4oZOTK58PiGW49V2uhWRdZrpDc
d/PnPzVLlDghuUc7QRz+0gOxpNkdtJVx3Xznr4Gu011/hqiJrtnIfGh7qaAJbzR1Jjc0mgy3KhnE
7FRXIVD9vBDM5sm6tmLUicj/nfCIXRGb8b3BTy1j7Q0P4TmAEQvLLCQDeCN8Sscr1JMsAuCHE343
ECJkCufLaeiS6Jbl3Fvb5fr5+pzvIXEcvxxV3jqx+Xsr1RuYg4Hi5ucChWCijJQB6SbXjRtBdX4T
sqbnsQ7gX3TbNSYqJ4mLyMDIuOyALj+K1fUmGygqNbLgZOXunUCmoObi7j9z6/BIKJYGBAmMiN86
4mF/acgqnaLS19mg0jz0dX42CqGbjcjW6fIMTt7YTpPJLC1cXLOlDgeOcFku1xX/OQovP3DBrJXL
ZIC/2H4YPA2zFExyZNYZw68oqYXjTU6T+quxWjxNfZIhqpv5ksj80mOj6Y/npijNX4ioAFQQThb0
hNkER46/JitttNytSCS3htueteG9WLcMTuF73CM9pRPeOpImc5gBpNJzy2JJLNBBO8lPjh79zF2m
X/tBAFx8rAOzE25NBEW+8w5txt5/eHPgCk1diRQEkIF9ehIPp1if6JnTv6xJ0lSl4k4LpZ08KBbF
ts4FaCGOR/w96auZ2OmPTTJAl6lIGxKDVWiq4s5SXkiXhJx24xj/uZxm2XD6zFCI/K0VLFrZnQLI
9r3qEOQ6ppmQ4HUn+CCIMGOxBmInw2ggdrhsJpU1pHe97sNqDY283o1NcVGLLgkPsqAtOA91tRDT
0Kcb10TSCyGwxC0mj6b1UV1G0FA7X9vvvMh5/DbEjKySYeJ0mmWV19iz65ae4hymVvMQ6pwirLS8
BuVwbWnePtnYkPgbVSf2/7i5XGqqGuHIG5xtSq1lklHvr6UCMwTFHpGy9O4KdPXu0nfF95rLg18f
5+N/V20jLN2wFpp8ghVnLEshKl8ZXROqfKUrVyAg8cE69bKo5WS+DEF1geTKD9EOYhQ1ak7YQ7Ur
/p4/DJV+UTqZkCIdbN36u37AkHjVHhavXZ18Ow23pfmN5AAt1oMqkf6JPhl2YYBGW+BamrpTwIgK
m+8Ggg7p3RuefqqzoCeLftKykmtiIRo2OFvwBGyWsA9NAWfJ71vkaJmap4ztcL8+9ZcTk3gR/SyW
T+8ArRz5dBAt4cmaAkYlOEGHwk7opoaMFcd+1/Z5lWzMXtijCIH3LcH5LWv3XHGoRCA0BV4pdgBY
rQru7DXl0jF1+qb78c/thAIjH6vxOAZdEGXqd+yd39ZREBYxPfOUxL+5vo5eOJ4EoZ/q5+OBxYpq
ImtQkuphewVyWA+HIwGIYyM2tTZ9GUNtdwp5bXJBf8Wnvqeyjo0RVxnc9VOBU1mD+q6gTjEMy8q1
HpvJGXhhJutjSqdBA/gc9jgkov46n2OPp6zH7tW58yPEZRxJ+6hK9GRXlWWt1GilIjBs2yAgLtr+
r1Nk1QJzQQgTtskI6227lNWvfODYHK475Bu2OOizg9ebPVhRWZ8IQpjEGJRR62BigqfOkZYG1Sey
3Ud0IPanDWDPvVISnQFOOnyxM6hU8JkWjAbkcfI70fK0E22tpZCFQY+ZY+e4WYaOTmh8DpLRYt2r
tnjl3ohePF5KhpOEjA/CVuAxpAzWb+L+qr4XJdoaKEmzxgcMJAzLEW/E7MWkS+fUlSjEh1BS5OkR
Mn9/BP5LEbhrdqOU+E13NApyFySq5a6aiR8UotejM4ZrnM3olh9F+YVjKNIDOv2PQUCgWlM2GW5c
yKPvbcgrFokxCtR7BFqysbJQ8BUCflmBC0dbfNkX/+YSn3Db+NkGch1pfxYrKs+lrCBdUV6GCFwQ
eyYooW9rYF2N83AKa8wWMrLTzovRIK3vswuPwpJoLsaDe0zEaN4rekfQJdjzma50GLgaS0sBkxpQ
Pf7Fh0uDc7PCIDbw0fktpOzd1daBkeBW1eq5gcU5veGgwQcRM+qf1g7crpLQ6E75Gk/pWGGZOn5v
JKY6ft32IWOcp150g2YnlLHEX30JhniVl+yF+/LKqNc2M7QM8NSuxoQ/ika3/IV7ScbJD4yPFNNp
g8cEBx/Kgwg3Kcg6UObQJ80hxKr5xoGhf/OKguVXxoMrwZBYr7kCQf7fnOw8v500bl+R5/5vxnSZ
WvGVC62kvORHraYeuK0lOXKHum4T+gY+ksO6+dauKl5YTNIO0DRwybHi0bey5Ti8KZia3uEvcuCv
JP6hRmVXbNYpkw8GNybKz398d4Llh7wb+whmWafnfN2C8uGmGQFF6HtuB97Ec4MTzHx4QslQIB6I
H6i1vybIdSHRv1U+Cmq+8J71jsisoa+1GnrT8Yb+lMpeAmv3KqZuRay5PfiSbqMRxzGp6aejjlPc
VHSLLD+VpkHZLuZozXhWFdiAeTzL+XQgjegTvspZlYvoE2kdpROwZRFr3FVms/2IlQ6zY3r6x2Xp
lCBd/e7jRCQq6sO21oGq0s+tZv/wzrFnpVMBhyvsSYZYgyUvXHoq6En7nXTbYlbHZbPZ2GoZ5KBg
13kg76ZkJQxd3qAZ288rdvufzqnvMNUAoIBhJkTT+tDC6fOnWqlV+8/cvHdkptiFYPfUWljkX1Yw
xYe7Gq7cET/eNFKC5LXOa9xQ6DML/oU//q+AYHAJ1244c6cHZ+kjQcJkfMrf8A+7KllC4tcjcMyX
5sLCQo6mDIQM4LduAoLfVt/GxHbQKqm7iHCjcd8T7bPXmDc4E3VHZKKk8DjyPKHEEuxYStY84ph2
MAx4Y6LOM6osOKnfiuvh8mI55vHVKbEFQudXSEnTGpYJULr21WbB152XyDGua8SuKFRalcPdmAfm
vCcrWUuiYjA7JbkChp97JjsVzJo1Tq1N7Rj+thiL4tZN0bnbtv5XSIAxukca4GDPYK7emYgl2KvQ
MSlBOOnzK8qtwLnQb6hKbWjYVkyXY0dlHmGcEfzLhzYWcXg5PgUqmM8EIpSf02ZusYIOe+IsOgXR
1PDrPDqFzAr65J/Mo3ISLGO73KRSG46HgAIIUNLSwqRWJVjGtZuTvZzVg/E2WTBO3tSRKHu0E6oo
NyO344V5/ejUNyl7vrSYzWUSkAybPgq2i0NC93VMuHOsxA3XyJTo/GmPD1RLp31SFIRNi3w+KQ6g
a93acJYyBJ1N95Kzvaj5iVwaqOkikvXC3uUKfE1cQjpbDnRapxwG4zGif5IRqiT1csymObzFoP14
qaEdfY3BwU8d7kHvruwYJ9xgoeFjmPLZChZX3IoInleWb8lj3O1zMNsfMOWtbwFuf+dm7lubXF1I
/POsqnPxlm5g+o3bQ51SOD8pueWg/70xlL4ZyxLUAJIBduScAPb1afDTxwKlcHLYC+49+3jb0BcX
GKgoEOLagXe6FCOqfO0qddWr7E07rReYN8+6sJOtohqZvmh9l4jSvcIghrD8yB429/jbpC68b/0W
sBYNiNhrGBF4NyBMgF3qS+gp0tmTfsqOgmxWKxgHEgGmn4IA0ybepnhvlRTPhIa1UnIzdzjoNbNU
5pl3vKc8+P/Pe9qcNzfzQ+A9/LCUV8S+u9ewSTX6HiO7mV1UpvdwIV48Hst+a3+K19yxnJN2//6j
MpZ6atbrnToS7BLsEHmq4GRFwzmCCX4jM+OcTMwyqK9onsfKSIAKqfpGz26YuUNd2ArpTkTrsleU
4Y6JbH7csJDzPvgqx5QDMkdwPoqHNOQnPshcXV6R8jxVv4nx7liDXKRXhwO2yoMhD41gY1bbIc0o
g8m3JAHjlZRGuYeWklmHAQ40Rx+RZlndUW94AhrDearvcF1VYVldQlGOeZ5LIMi0g/e8kU3rTj6d
neGMKXZztNbPvcvRNF3QdADZOcCI0PqJuGRdlJkeF4XG8ZjhoNLnAkGg2TBvvzVAFXCH0wyZOy5s
uEBNKQ4bUyQlDVae44xMas6iEVl9C8hNHg9xM+gXFXWCUI5nRVwcaXLgPoH5IkAB5u/y/Xx0c90o
tYfFiH2bnF9WgMrBnBzcTYzgT6yFSy/DlO8RHGbyFtOeD5KMhWvxqcPvWguH/BPTJcn2Aro4+p75
NFn45dD5gsCv+dkcM54G6DRQO0pkqdQwWGiW/Z6Rr20Hv7vJm/WQLBeJIkpMvVhMFk3s2Z7ItdXw
wPRe4GWYjb9T/5+NBfPAZH7PTepqTnpJUg6yNUNcIOAZ2DVPlcV+B3qUZrWHO2h8ZCgnMG/JAAJ0
EqOm5tmV0ludQzJQRPRJ6BoXTIE3PiMEmJagICyCKXrSSeAVfJDVWxq2V7eB3S1XPmn2CCWnV5tl
4Hw1sYEIduj7fsGkIabPXKunZLOsXjQvLayd2HxBu8Px9SyqTLb3HezSaaBdZei4FZISwIPoHsqz
6rpD3Dt1X4qFCIKDH9qKihsvLWmElviK5AobitJe8Zmu1yroq4WAcC9ncKBztzQAf5Nvcaqjdm7B
O8FScs9YHmB7qN+5hQCkdVzIKJ5z+GoAfEaqYZTEH9fd8DYeSBdV3wH4OfLs0LaoG8J0zRBsD+LC
Mdax+fj2KSaMIKEcPTsdqMpQ4ijZ2EUiVx+W2MLLEtiPuN3CPutYFKvSIvN5+gPgZXTVfK3PajH/
9kU7PjMDnODotj0jmKliecPRPwL7cLBBTiqK1KtnFJrl9ArXhp42+RirkyDqTpJxx2cpgCnSlRiY
iPN3Krm7LyP4zKOrhqO+oHDZ+lDlSc+qKOrYb+B76HoPF09g5vOpgMO0eGAyH+6jEBpQDw2y+0Xh
mbg5vewuqeARrSlhi4pkE6GBspomE+6mVUJl2TsE25SWQeT4w9BWB3m8thVnhPBKeyCCLs5djBpK
XqerV0EwpBcxgmSQxLNtuFYKRVvabszoXIJOWVn0YtYbsoEBZIYKbkzo4WbpOmGLxyEHmqTKt2A2
yrabyHC7J3dEzebue41WntW2B/54VFDdP531m9twllyQz52BkEVPzftq+6NpgZXAgr7tE3Iuhr+K
+F74LlVaSFZUvUdyKdzTJes5zoVcQF7Jv4/mcN7xwd7xnpgFigZq2SRBZqMIUvjgSb6mrudPMMGo
Pt8jIA+jYifF7Oreg2yeO440E50roN6w4VU6ys3amuXvqVxvu1pZc8DQKBATG2awItQO4g4znL4E
Bg3DkYY19KLbEon8GvP+vPeevf0c4CFESU8HDgNT81bv3TZbvbps6VoSm+w9bpYTsZ8N2FXszHN7
ryoYhIY9QdlPqjSK37LS/d4NBETPkmVByzBNhQGLe01x6RRhALyhi5dFD7Xn+1lLINaGxI1JDhXg
orJQy47Zm8RL3l3aVCk+696JP3y6F/WFYncmuKfQc3ptBibxjLV75tvELnEAujDv5lzRmSLiSkZA
+fjFnS0i6/J4CN496INwzIS0MSigqKf0Q1y+6N8q0b7xz8HpIRU3GqLivbzktdc6jY+6GX72HbQD
JRLM7eKA8AIoc5tI9lEIVslhjaZbQht8w0e4Fzor0bX6ZMTkUOP+KFmR/0DZYS7nvRqdnOfMkI1r
cFeDy7Kl9dcJKTh6MmpkumIebOCa6t4WTQ8RfngB6xsHKE0AxXcFQKjtUg32JnR4eIJiOeksKOwc
2Jrd1aXuEbVeSlpKGB2yAkjWJcrh46YHmbUDucz5TN6Y3r4A7cMv4xmpay7wawrC7RbxpT9VMF58
Wll1n7+U8sBNd6hUD31O8UN+Mg7pADq6lFgJ0qXeGedU/8dQ2Elxb/NkLjBMABT27LnBwyKiegrf
upmp2x5fXkOaYTiRF1/1619/xQN95aPeEGMgdRInFBEp2HoUjZ6IxnFGst7gOoNqquFV8yD4Mqr4
XeWcgcUpkTEb7DNN3XnA9I3HTs6t8SrR9TLjAHVK+ksgAyWNsmeF6urpRZEDcK82sHKrg3drm4ya
ownR5oUTGkuEDUM6UrcGcPxV7l3+bFAVMLhJaQK+yLC2OV7VANV+EhalYQW1cyBgly3GospDc0nn
IG2/nXr0rhCmd093zDZXK0I/jyoSiXeFGGDCCJU4CybHEcuHZIQEeaK0DiB97xogvTkvS7RtzHUt
fvYFGMh+LeztMXe2iUcUYgLXxRj15Kow8UQlaLNGkggwoS0JWNiDRp8TpZ7BqnWKOEGirpWXdp1n
6J5z9aawIEQYRE0OlLfapwNsnE7dP9s6O5qbHO3fvWqaoOxKeGEkFZ8+XnumhTlDzzKN3BqHZ1kH
lrI96GPZKyE7YUy2wahz+Oh/BnMpy4vQkNb0+fTo3Zni2IZgkfbGb6FgARIAhZEQ7orVhGLdqQ7j
dertFwq6UH8nNPs5jnB0Q3JXKztkqXhXQJFetHAeZHdhVdr2BEXBjH48BLhVPKcVjTzZ4dLcSlXF
Tyl/29EpZsXA7X2a77+HyMSkSdhCYZH42r72VEa6fLmEY4ifHbLjUg5750/3KANQMyXxYGwMPP5L
wfpZfYuEqhUnOOsbaqR9wDZyMmsVSWdYX0yD7SQwevFEkK23G7zn+e6MD4p49QjODnIrMvYgWwAf
a7hk3+D3qZYh/jLLrkHS2mrJGwUte2XbTroYwH7rO3vGpnkfMivr7szesbrGOEhq5sKXrORSPqfR
YLMWZhlyk7HUyF6HGCE7IKBdqmWvqQ/XdqLO3ZXqKNMp1dyAR+Wci1/P9X7PenpjdJOPQ5NYVQIE
QhC+PKjXypRFN8pD9JYaGkDyREEtaAQobqQgrci87ioC0v67ybJwjXe5gLt2pN5pUEldmKA4D5at
Elq1ILcCs3o0kApJIUU4tIeORxsvaBYmRErHpfeG4GWzzoWIurfLNB6Ssi32WRkf9ILP4QUTEeRR
6tBF9C7DkVs4RGZy5ngBaFgn5OIKxh6Bl0WVNemxnLHincvMy2ckXS095FQRwdriwo2vNWG4Jp0a
eAyz8cNR94f75qOihSl1EaFr8hIWZYTQf87B9DlPsKA7CGmNiH8mgApIKzAsVw8UwHm2I522d3Go
7jZsaGoUJneR0g1Vf87xBJ6l4svzadAWeoFM4sCZ9YQZSDX8zHGPHXnzbggQefzakfdnylkruTYQ
5ZJLfq/iRsB5gBg7CmHjya1CdNeYce1l5YFy9LolNB8LbZ91rLG649GPp9M9lHgn61IxTDq2iWFG
1oGrBu/URfAIqnvAfNDpNUWPn49sBl9OSsn+D5L9NdxDu4KIpnmwOob4t0OlKjnNuNCy1f5XklQ3
E3YY3/D1kV5y/XqTdpTmRoAuT2eSIu6KGa3+vT3ODwzQsR7YLKPJjFFeV4q+mPlsSFFgVyMDJwbF
FSIquAUECZge4nwHopb38sxawgTV5C5oa3c0+rjaYR+zwPthIvKapIot7nc1loMDcQh/E0NonoRg
bFRIH8uwB1TK39EqadsjV3RFU1Aa7U1OiRCot+EutRvZgsRT7SXFIKYNXtqjlHrvaA5NOa9LTvcs
JgUQiC8R8wtA/xXvm3jtyFuABIkUGHofHdg4qRA3JIWYXvjxEJDQvfsP8SaLg5Igof0RqJdKJBOj
VSNIT6aOubtY52vUltsIw7UYmQGzifM07XUXiEBbM8WopwCfrGfdnw8LgH5tTUBB6CBqOwh/ipT4
l7G9SFGMf5F7kehnqU6etNH1vcaQSxR1SeYCNhfNdf03dPXGGJ5GyYUYe/v3GbYWYCzFK1CvGKMG
G7nMX5GKli0RY11r0LfqQQII/YbPuCNH6Y+qRc2Q94kxz+PYMcPEq6KTABNZVu04lZUS15Ntd8UG
7bqTq76H7SRq/UlN4w4Y+XwaWoQUNKzb9mvUk7b4V3bR1VropOLxCOyELHSVLnCawSgANVNadVeZ
KKPEVC+MkKCEsA3Sk+7yypDK3/br+1Xz4xkcs+5fmFkm+8OQ78JHVOAzpgmzkNkqAqi9AAWP/96b
aP/SwJAt+hmO+y7lBaT1cXw/2bAxbHWrTVrbAVzPcvCMRPQ/KtEbIeWpMl102LDoCKcIOS3PEHBd
k5EHeqQbKHA/k0FBeiEUR/FKS181T/goJ3Wlwxqgfsink88bvwjx3zdRVhxO5KUIDiGG1JDZ6AKo
sFdEIHkeBlLKfWeiS4z1ycs2tXFx+WiDQ0w7axwHLlucFHbhQo/NUCjYRbOog0dxkwZOesqgszeD
MXOpbxYgaCGc61CFK+YlAYY87I/btkyOjtMUuAp19jBuB4nakyjyCU+LjvlbFKQD4LXU1XHKzyxv
riZWsblSnqvPw2Tb/COuUGIbhBYHXzbrCmyj58+t6AovyojTjqS0YhpT885XMJWVEV5Z1FkicoFU
I789bBSVhTNDTdTn3Asd6g5nzYGHVCz4J3L/bk6itb2Ce5vaYV7+Ni1Inr+j2Zmj5a7I2r/PXY4+
hVgDt4q91TEYQog9bIkKePf4Fu0zLuW7kt9pGN+fOY8ZSftCOH/+udV/BuzbOWCnIfHuFtOgFmgZ
iUqCm5sC0EKj+LOy9tA0kmrJRcK3boaSlSUwY/WPfPrXj0ErEI48OpVX+S7Cj+wllU3sdG5jBFJO
9G2gBJEeEo/ao2ZLjUV9KK0ymQiiG4bgIIVf+3b4jfSaCpfhWv3SddzWrFBYlyIZJ7rjQaihk+or
nQptKvKoZBfEk65ckHXx7JO6GQDy1817vcvbhvWucpcV14sNSZohFrMMCvAUfKi6n+7beqbkB1MG
unY4uT7u8AVasJzaRfEyfLc/WAHeHkh+gjIiIXua9dybRsJY7m42QFs4/gE2QeP/EnW2KLo2vQIo
O3J99nLfM3p8DxNBjul7ncWX4XuJT54WUjEySCFP3nnTf2vc5Fq41bor+8zfg9x9KaBglJLSP1iH
MIBM8LIMwf99nhFQuZdIlU6OFTYc0KRK5khYqHTr5G5sZNloqIFOxawp8cjvoy+0dYEcZr5a2QJn
05x4A5NI7jpoypIMJe2mfszfzoVjgMPyX3uuIgTsWxMLmAt9ASokqzdF1B0INHKsEzFldbxzFgms
jntihvMtL5VKUG/mUU6rE+whKwd0gs+4gsEL4fWrROwvICaN6x6xDezhX6/AANdUAa3xOyA9Izta
hYd1M0RKxV8/TngUvGEeW7jjoZ5g7ZEyySu5aCD5M/YKEk+qPR3Eb9yOthHzPXUkFW9xDncCa9q1
6h5VAOsKBCzxBsGZQSAn5VKH6MEvAE8ju3bq/2lv58QjuFqIFNW1oLrSuIX6FQ4tqaib4CCNAp+n
kcBIjzS0xdsGsitFEQqyNKYBr1iAIm1B4Rmugi2Uhn5gjhldr7yWPrauC/2lFe6JM6b8ac7/F2Md
vw9JmAj3BVFHnhBjifSWGN71HeLadKf5FZKkkh7ET0dYysdfduBL8q/Sg/uZSURb9RMyu89ftAR1
j7QxUDioaEX9yR4ubKze5C5I0kAQT0MgSsgrMjEJcLRtfJ3Hb8szEC6CrPB8B4qOAyKeM0eMwAs4
KHw3cdRCegpqeA0RJBjSUsHKn4sV1uk/7kBQ6zNcSOux/V3XZ0cy8kJ/q1pK87lmoG3P56zcIOnf
7sgb9gb/1TATBPShYxvZlIG3la9tiP6BFWcsQeHVjwDpJIQR7hEtaetTjMlODFg2HlvWJK2p32Ur
7iutF5fBQdpEhpnsHPsdt84KxeYRQoUZsBBkWjeYvZ5Ntoaqy8Wst/LnMC1duIoxScvGMEZndzaa
FS5xZ1IM6LbMEPkSeJbgzcryU1eDS9HoBGfPWjc0anQV0kKCMilIL0/G8PyP8kBdlRddILbEoTpm
dQVK9uPiNnSjeo6whW2KAAw1BivTOgX3RKjyYl0WC/h54IF2Gj9QsuocujJYZk3+pHYGpzWqtAqS
vfndfpXGWmnHM5k8jQF2/GZNUbHG74hNBqjJIhU75k0shLDDvCO/bkcNS21ij82H8MdOe+PrBy+k
fuLEQWGsktvCVowzhYVoajy9q4NmIyVIa4t9KFJrdI4VxybauiKMSN0Ct3JHqF3MMBwxJp+IQR4B
I0IO1xNrjasU2ohIK0aysomYpJ9oZmMfyPuBPvONbRhE0TloANwD/IC46oy+JLf+xaZYM3PPf/gd
uGYSJ3BPx4yo66hT5Um6yIsUcmIP1lr5ZHwaGSe6/sjg+6gwa37nIsX/HlRYDKTc36gFSsdUO0/X
WSya2j+jSGE8gdE9LqlfLJo+X12h5JMsjAXyfIrN9JUMSajp+0/DW31KNqVnDGe7D4Xv/u9JgNlR
A6cDu9I3gQQYQ3xWXEjyfHnRxRE3poxtoN7sMG9q7WyK6BddPYLqXjakbhPEuZ/1ejXrInCSCXNd
vwkEv1L+jSjVNwP+0wpicQOg+FVO7XBnXOipPt6O9IrcOzTM9Crav3CKjOrIx2o28W9L/trc1PKz
izKD9Hha1MHSOUyPl+4sh+AepL4ki750yMMIMh2ciERKetouc6cfDDoQl9hPSJlgxYCbPULDAy/W
7dlCPOzr0um66myTOmRHuP6R6d6mCC1Kii6GLgAtzoG+VSPw5J2bNLZV7F0sb9qDCGWtQbHdMfeq
Kjw1DJ8heO4Suhfwb1A0jn2C2qQzpa6auIl1rBWF5I/xofqlqnkYgZGOWQne/E1qrUjai4+axhmQ
L/szcP3kbf9KMZXaPeNjvqZa4LSP0KK7mcz2Qg/FVUsgXayvEjLle/qHoNq4JlYn3a5trQKSRYgj
pQmmWpsUE+RA5jT32nFzwlITm3sgbodGL2VR0+n21VE6YQv6BXyUh9pZZA4mrULwNaTHyvOobzzI
c9IAM3tmTaZsqWSnOxzvGZmR1/nNN+Hht7jHAFqZqLdatYbu0AtARjQ+zit5ZEzUraZBiVhyl2Ol
v1lAWFcLU8rmJ5/yDAgjGx2p93IQSG5p1+n3xNsE2ZpZKFioCltnD8uCmKnFnv/tz4nfADwILSgd
NvUXmDDnt36Kkds7VQpER/qXHlqrKTRspZJNhMsA5DUJwxEjgGydYRmtSTPPSKdFMCGfLCq+p/yG
MVJyTFlDcoPtE2AjY7B8mL6uO26hhLn3avifpKp8nwGuWn7Eqh3uCASDXTPKOtv/xY1ip0yyp49i
b87A5p76+AnqJTXFNFPxkulbr8gnkVt4SvaxaQZBfdhnN0hUrmCkJchL2P/939h4kGj6pgo1wfuC
ZWICTpnWeSh0fAUt65cx9OE08Vf6O5uryplYsq9X91NF93THaxqhuL64zKXnfAK53IQ8D3ONINor
Y71WSGBF3gipsSsrt9vdUEDJpeDTKcuJz4TE+KH2DVDpRS6cbQ1/u0nqd0Cv7mrUqFvS4p9F7400
izIr5Bllv1fSTpi+ObPTfzWZcx0FHirN5uBMqoRSc0JpUolCQHAEXyxAbwwGqwjct9kRwpt5ogrG
WZG/VrX/S03Een9TuW0lMKnfthMFZrZOA5YTEzJhYBwTirDlFCsDGdEBKa6xWwMpX34X68CWxC2E
fJEJ7icG7h22Xz6tCBJaPp7E+CQqaC5lvmUwuEk9XtJ2MzcBCbS9AIfw/MxRLtZWy0zpzGaRciV0
Vd1lMILV7ZF17r1NIL7fmTnepuTfUJAf/nOLdFeoe4BA4LcjSC/ec/u2IEzmEXIZTnRR/d4iB9Io
oh+r50O9Zy3qnuQGQeCMDdQTd8gf7wDhJ+rbon///DhBNHHD/fdGvDE0GxZzPBhZbCv8bNPULoG1
+cBDQfd1KdNbmBH3+X7vESzdC4Ype8eBUsAZ+mzyQ4dvj0uGt45OjLVAhQuEtDa0oM7x1XHWaSkj
4G+B27vHvOPRFg5WORbvDKiRahnyywAFtW1UzZ7c4fuv12yRQsc/eSkDorinZ2MIqksCZh8aNjx5
5/xygRgV0liaB31Y8+75tMy2frcwfasstYnvdaJn3Rz1DTiD9Xj+S0bwQraDginay+Ct1n189zC1
pDs2WIaJZgVR/+z2upxcALwT87Ck1Pj3Jc7N0HdxKBd941m59+QCKjpbBoe2N5cEDSnBrW8LE8sd
c3V7DTCDIdanKDjfV7PPYHHu5qbOwkua8udYjqupyx433coOZD1xfPaL+biG9UgjW4Fhblb1/mUk
lNERwPnWKL+1+s8DbVc6puWISYzANnPRwscrhxSzw9E5cb8ZjpqcW8SzP3FDkewGn8yxUrMSrC3p
m9b9KzYa7x+StIEqn/jCWQmqLClDo6sqAHfk7iRiNo9GDvFDr+z5kMQ2a16+V+sMMXhKNsy/JUpe
UkuFi7KXKYifTOf0jGdyyn/Kv3UbBLImqziv3drDXSe2Feh+uMpt/9XZ5VJOgn1/RrHb+mg8WUS1
XO0atp8ze/BF70CAwTyGcN/Pto8xsJFTHy2ZKmmz2hzPd24KT+Ok/yX2Y04vJSL6BMmTwrRkefr/
RkEqirtlz5A5Fmmvcn6T9JvDA+H44VdARyDeGADtK5aMWUb245fCCgK2GePb9L6zzsdgQKiYTr15
SzR/cbW6Iaj3AXPks5iKhRQdbTv40zYksQNdbTJwv7JOt0+e8yytFuCeH0zeQgGIhcf0Nyr8EO5S
3iR32LCqv6lW3BWfuzMQsVN7Sphc7q4EslLS08qkpQGolrVRRtqqZKyfYoH1zMv83zWRmok2urIY
LhiSzfgMm5xtzMLL95N4uCJFdYKoeykEHXWeZgkUKD959KnewdR0FLoOwSCSMO8fnZp57GbxUvdd
jRPbK4fdPTj1ozgztIva5sQdO2arWAb/cwsQrI0TlZUMp8xG6A81X+8nSlmUWxJLjaQa0+WP73si
wqvNYINzMxclFVPTKA2MWQySwxn/CKNSZ16kI2PlWP6keuol42U9uA/1eFvnfFFGdlUi7z1NwF3l
ZbJbLrU5SA7G25WyyD407gvRXRo9A/g39A3XzPMTk067tCczTpA/rBQsU+S3SJIHx+wQGd/2xGEk
+H2Rr1KIxeJZqQWllT1elJsRgIs3DH8RyqcEuHvvYgOAwtVyHiZ9yOTOHyNN8P2Tx0+HxZVq5Oix
PYH6WvhAUyvxbJZ4jI6nhjuHhLUR8+E5zh//WmS07zPYzZYFAmHAGiv7a93Kxp2ffNNgnOodSdMF
1HWaASSqvHd1E9S/ljVwdL8q82FdXLVbQRVd0ZiTJPoXi+TXoSeFn1dDkRKQz0JDDsjFoBKbyeFm
kNeNN4gdxep/XkPmFR54JZYLUNLv4eqso35ernhnvlhBJm4F2aRuTbtRyqCHCDjiVfkODYIYoXbG
+eHbr4wFnxgjTpY64qNOj+0zk54QNrcnzQ4b8sW3UUY6RIEGqU7EnX+e6ovbWqQSicEItELN8L6V
mfyepdmTcBHao04GXQSrW0LldttNHJ811ExvdU/oOeq26RY7+YzcwzMSLergr3/zjg8OWeAW3szm
f6aYoYPMkj8JBQzrQ2Lp2Sw/ADcOvJ655OsNBgaf35AB5cyHr7+5OerpYxP2MiJP+2jFJ7EyT7F6
xdhIqv4sr/3heKxTcZMDNUI+uj6Z/VhcABOsXAwwtEBKHmqcqRnhA7DmDM7m4Vrm8kAvm1w0XWfw
IPMlisi8fp15h0PlkQCBLWTOPIg/QEHf2NqYdVNWwMuWiw07K75nzjDSWUWxnQ84KMLbE/pn6HqG
h5PgzEHdWu1OF8wC1g1r6wsVThtNExUnANqBcRQLNscxVzgFG7Y6OuZ1kgmz8hCn2+IALaY/3e+Y
HhCncvnjbC5RJekdjkesbaGSzXEhILIcK6cuX27WMkTkJ7RGgpHCfxFMi10XrnHA3L5rbZtcV0qV
WmL8yCqSLW6iABAhD0eLF22fHYCJdzWdR31XJ7UOH3OodhvPK57cZtudhCkkF3XdGFvpK1DaYqF7
rLJNB80TOo4Pn5e4w/d9kmlpnZ9WwdYlD4+GuR/JJQvXAxkuWqR6CTz4wHaFdpL7HS1OVXWaua5c
HOF/cq6QElyhs9Xktj9MvED0hq54W4GwzdtXM+PTJKZFrNMDHAuUbbtuXYNzaDxvcNwNSMGIMZUP
fIaNXM+nt6Ib5AUZH5tnZISnKnwtj5JZHCSzE9W9diC+iu3lpWYGLJwcKCtGPmitm6S1Q/jquOC8
4uDvFn1+btsiVgdQWFcF4bPDyWUmvsB3F0QoPyPxuG0ow3IBrVZdN3DYYUw3fcTxvtRSTR/Df4+B
CtAr/5+o5CCO1kR9/pyPQJQyQl6/M/k+fnb8WZPkyEpORLeT0nkG10omQNHGzFMy5n+OqbCtVEWo
145LoE+kypxQf6BF51GaXdoqBF2FUdNVJ0KjXscOj6KQz7WZFv5PCzL4DXt7/lgQaNosEUX7gTuu
JLPR5YS53Nql9CUulmrjjR9tS7XQyta71Vy0Nohzl7HrPKD0G7IcVdgTLL+DR5lfwPj7KzmO4Tx+
YSGTXtYUyYLyVW/ymDwcgzzmYWI/iYEVqzpl5L+C9PTj6lhirSBqDa5vJey718JgF6XPX39M1tsj
5B2XrvOXf8IGcwbn8kPg2UxeQsuWYV9MOIMuW4+/91q2V4/Riggh0sHVyD1xFLnAHQ11euBmfBBC
HTDXnBo9oMqsQL2Z8twvjgRd0zbnGnS0G19Wy/sXTAxFhBZk9gQa0TIqb9Xvj/LBeKTDOsSo2Ris
Pb4AeZ3Yr8eTiiUgJaMdI17PA2AMvUelOdJ1ynzwcHriVcBIQR7699mF0qOSpdT6m7/S+aooAB1m
oI5dWtDZqGTlGQSjUOy28XOGulEOEf7G+Tg1/eGs12+rjtrU0aEU16BSFCyQSI4JUzDv3RInj7BK
FAkQyv0TCPkxZjJtyI3gZ552OSWZQpO1oBhQ8WTboJrTrCgLjbOZZHfI99Tt6u1+nVwz5RLXOFrk
SLVrsAAJTBITQRCqVqD0C+dCu6OruTzDKAPv+Ga5vGLv+snffZFN4vRbFC0fzwxNE5yGdHLYfbqt
GGEUh9NT8J1pn+uZNy8YEl2ZHOseTDhrLVdECsy1hOJPzQusW7Om4W2ZcmYNT7LcABVMfQKHH0Q0
too7xAhcVpQKtVhRWcXcNg+vB29XWtT4oe14UvWOjC0WO/3x8csRDHejDml7+fKgKtzjeEGcgTLP
zOlyEjscJjNzgYwvrW3ftBSth/Pr0mSSLwyDjIxGM5ANnDkbA7fS+qSmjl3Ab55jntpNPEDh1l4R
OLaWDNw17np1aMMZCNINBeGfs8VNbbz6GiGd/HW+TrXA+vSDxs1PQPmYWJjogpCK5J2PzbPWdlhF
WkpoES0n8A0HA+7AvAQ1EK0ipHldPkwRXEcErnPqYMkXEYJyCX6HHuBy04aEeswRh19c217fDEYb
ZmU5H/2tUdT5GuB4NAgwAj9PxwJe2Z0/7EQd5yaYd/t5rMR8WsKuANYHSmm2NAHtDSt1eEe+iLhV
JhR1n63T9kkHE5t1lsRwxT7KqCnQu8jGjozkKTW1LdyB2Rqh7CI2rj/6HM5t9jHDylVF/QTItW0X
OTwDzPYcdDsl8Y4MqufpP24q0qDL+g+F2WRahvF8yY+D8XNE+9POWlRGe3dMnCrBGg+hoQa9t6Hu
Lob68cyx97uund3uekYkDVrEpGue8Nu0aEGoRzk4q6zwRLxTCNCM9ih3VZn2ANspXGOEC81BWrql
B0aAzourpZiNgj6dLeqQ5q9+Njq8/Oyhbu9IgfraknwUnsWAuW4hRKKQf+N0jTKN/nlTw5vNCXMD
ba/dowkPHpi58ZZ+5DLAla3j2sPmg2cRH89esy5Y9o3EwJNm6MjeUiDln5Gmn5eFDguVwr97UYO3
RBYvltMTwvowMsd8+DiE41qPiqiXYiK1eZEHD9kpIyOl98yRu+34CvOgmz8TRZdBsuKmDnSvNo2r
VKscKnDRBuZ4ep04oyySVXoMl0nXvcEqXNRrRBhV4G2uSQ9o5fiaBthDXfPnUNW25sjQkmJa5mzK
oV+XrzO4aMIevx5i9HsPxOS2Zab85DxdAQBo1uE9ZG7P9O1JImCQYAtkWznqcGtAPQEbS3cfraAb
vGH30oSei7s35mvXZDtm23HJUMOGKgwCWu9Dcw5M8u5rzvCNM/iPXReDXUWIZIo0jc1+bFFMfhgR
W5rNSmsc1UUBnMATI1+qY5QBAArmR0QMF6zcgCul1UHZiGHBU4uZCFpkPFVkU7zwqBx63D0QaPBv
XWuvTZye27F/z+VikxuSAbk6Cveisxo9K1odfyH8NhYY0kQtzo2lGJyDNcQD7gvXfTAqyKudgoAY
94cwpZW0a87MubPpyLoYIRe7MhOvP8dBe9pqgBRTIrU2ryNP5PuHtKBJ7zTdFEYG4PPdsTHmC9ol
mwN6PJqDqWvr4zHJ7PuAM6YxacDp1Lkm+wXY3XKKR70AADhlIpMj2W4tivlxUUXR6YidBtU4O6tf
29mlb70Uro0aybxbR/088pxf43oI8vEnUQfT7LlgIEOPbbkIeNO2PdkIaUAqbS4Mjvd7+Zvd2l26
PJMhETATKZZH6k9+e+ZUlekpCqnm7HY0h6q5BY0umKdt/5aZjsKb+iisBZJZgJ7/8OKJQ88GOAMc
uQvom5OKZbnVXNPpG5HkyQ2KfGt6iTi2SMNAxv4aefkcSj3Nd8cWLDzUz27caEyCktzbCxW+sjNN
EJRvS2YlY0ec5uWZhkkx7JgUmmol9yDjwL8766l+OY4/s9xxIoQZYGMm6PI255W7Wk2XOpitMceM
A48VwPoYh5fyuj7GzFPF4X2aEgvzfkMGNltuilsAza8Hk4Z6FESLtSItnwSxPVxYzlzSwL0R2LPy
8zQYcHXkuTpzPMyNg0lNZbcHledqPhfMqVWfY3poC15dYWWbGC7bIkYkf5oxBaHC20lTWtsLTZgB
pJdGtBKPLAfZhLBWFSstqp7zhp+NmyXTtxOnrLqvOqAlWCYi4dcRvjkEkzt0/TSwcjCflxSA3IWL
lpf+enKMfrY4aKPSz1O07+Ey/qr7k9d0UNrqbWVb+BV3iiU+XO+3fkeF7Yfn+6wsdlAQx8pnk9U1
e4EJu9DndKl1157PCVB+FT1UuxhSu0fCZKC48bmjVLSBihf0joDpFVg+Gg64Exn9OW0t50OaXAyr
p8ym7kD3/n5Uupt6WxwmkeTuwFnWQCgYthchEgXxZPdSXOvm5TFUnYjf13SeRUjTvhKErY8/a2VR
YEQxHOEDElu4r8vGkZEt2KPU+wpS1dcKaCFWitHEnLNALbndyNS51IeYsad2cp6bVM6P4oPPS2Ix
ulAG64TtQdmyBogMnl6qXErGyM78EPv0oF7OyaL47Z8pMpdaglNWde0jKH2TozOtCAfSRT2dSs7x
vbRpzhFbvJESNm2kokmd85c2ONCe9zYKh327RNg99/e2YUHyQecaAsWvGCJm0rwpO8bXq8xq5rsU
vEH009N6d4gLA3ZXXxepBINOkwKpQKf3zKia7w/88QAlwP5dHtYmW4YuScmSjYjr8NNwM1vNgWeY
GXvXH32pleM3zDcYw2nRqb2TfUJ6mV0Fv9G1UZ32EMMEzpahL7cfIICgY5SebnCmOk/WTzU1l/cg
FngdXa1M1QgQS3S4aLwwYMi57LoiWdMxIT1gijhV0vDMuQNu/ZamqJTgDEUy7CTGDV2R5fWDLzd3
sqYjCsvV3MN4NVlnJVvUJE3CBLfRonUtqTN0xna+JR+5a3UMMeUyBeuRkZcziKmFB7dZDdBVP66L
+WtjsfJTatUd0HmVOLR7d998dhXrPWVsjtunKEha+kta59x0gEI6fGUZQ6rQ4VzW+S7ne8DkpVeH
X56/ryR71TGDD5Lzour/9g4NTwMO6SzO0IUJNjd7GNF3NfMYbMwbHnF16iCY0JA+G8AKMbBYincT
sYyMNIWhw2lZA4dFFMCFjcLKTpKTvz8PX8WzHgl+2xUGPvX/MTGnX0WX/z3AYH8JDSASTu84kZXy
PE75FvftklbFK4kQBfYIPm3wRbz+ofaGA+Aebvah0FfhPj8XV0UlggO9qkBYlFthmDCPC/FDVHr4
Vkdya0uy4i1BxOerRHIlSh5rq6w5ML973JVMQ1Tk2W/7O+4opiu7QYS00pb+3ivl1ugnvCFn5IFy
Ge5McqmgtMybMlV0xw0wOnN/cPRXpwHEpFNT08wGl8JJYmBL4gjAq8JWCqnNOmnvBLBOl0t9YLCc
06QkXSdoG8M/9CsOchOr7nSI8E/Y3pDUabm6rg88edLID3dYcwDxoLoCYMBhaFmLCzbvwVctmE2z
Ysv2PaSYNLhxeOJvxlQDXOVV6jB/plXjcrwSuXv0KdcRJ33G83pPCTeCyBRje/wgjHDtdygIWwpf
pIjN4m6po8tzvtZQgJ2mvT8+A03RzT5Tq2IFtOApgS0lpP6OuIv0rNIjvk0zC/tk8hd/O6hf4qFR
lbzBaPKRcP+3ZuAegUkk0yGgKfpG5u73TR+1Lv7f1MZh4REWbYDzrzvzWg79NG8FI7UDP+w0jxpT
VqNslMaCyh1otXqlqfzK3nLdmKqgJYRWydayRGg9cG58+mpUS654YyFpzSq7k+IrtEn9uEcmOzl4
/4sgy0Rhe+4053svrdQ4FPksqW5dGeA9CgsZSD5Z/PdZnO9bABTxxTsfCWK1nqfnHwJz+v3djJEI
Ums9sBYPkCha4L2E/T+6p41mZMKFZ+CxyIeULsv5NNX522+UHjRUmLS5lhHMjFAs0U0N4mu6Fmh1
epQE/ePTj8FQ/8l2u4zs8KUcUZDkvxRjCZurS1nJc0mgg//bWPk6wyRGD5jpFzrG9cGHzcQmXP+k
CsYQpyhei1tu+6IeRHuR+P9H8aqZKmn+MvFN9Nmd7Y3lnGdMDbo8tw7koe3/tjnOo0DBrIY1LY8i
2RcQbifb5/BrNBZ2QV05UMNLV7ZpFoTEcNYhRtZbX3U1A5iFmSTTBqxFgI5zyO5cCvUeIQoGOPMr
3eYQIFRCAQhHWVIU8YD5k/8m5XNNkQvorHAcuTCQMBKEYNQagtjvMP3mpp3a3RyDh05lws2XycAj
6nKMuVeWEWAEJTXB1oAo9AgdbseoTjevLceRLgQ30BfrwT+BpfymA7FGJAI5KGV+FRz7/v1UdeLB
BM0GQV+NTgZ4bBJHnRSGCrfKdkt6Ht3fL9KY9+/bxiXOW6NT/+wXj8scmuCZjMeQqATDOulVkdBB
13CoAYfSFHGU9F7xbM9o3vQKVDRb9/2zYxAhjQlc8NRy/+ceJb8JKv+sAQPMeD8m2SXKzTBRuAzK
WbNZjt3XyWFYjeldEiyda5g459jeZWImooz1oBWUN+GL88cIXX2f1hOH43uNFyXdDs7l+SYw1BgR
zoeLvvJJMeial6TKSlmBThlClbEgXeJeavkpVqlnx7rPDYpIxEDhLbr0kB9gAF/nycZjgs/z7zOr
ia0VTLiuMsaYNONSKHl7fGCRl24dSRfSeFjF1dJBXdC8N+Uusy7Oiai8wb2vP9F1HeIwAm0zYArO
jupbeOirac0xWvn0AP1I/K1dWKaKNX8u5YeqftKw+reOUfKGf0mKRhkaZktdHtlJQMjg9vCxwdl2
zJNfDVFujPaxqO3fw59op23S9KxEu8iJQHH1rFpocTYqUdVhT4KLaBsPCfGs2rEt01MWfFlZyPVN
Jwx24zuKHt2KHRX6vIUxUdzEumUuThkxUBv6CxD67X2pDy6S6yUs2+JpTQbDDMWdpzjwminDnLpz
0a6IUh5ose8kAdGh9+KmwpQWSZ1l31FtY9ipPsbPCsGY0/r0T8IjryRA9Mrnu2reeWlUN9BcX6Sn
00n/hanpTkQ+FOT/NCVrFZOMKqKbZ9do66lLPqrqY2XNJNseyC9nJostH0mS5vUozZXNpNSTV3KN
noYWx2VWew0X6DnMY8W0NG+38IRV6PYtFcJGvbdTLGv4inQJsDdLglh/yGgXtQdWzdDzC/5SZMwP
r1nqAkS/Pu6ZrX6dq1amdgBDl9G59xHc+OKWLzHDCF6yNKSxTc0ScU9tL0hH081hftyXznj86XSf
IhQ8wEl2n3Mg+zlneERtGJ7jGYWp+TeITmSdccjKbiS0fMKTEco8BJvd+TP0xhseG1giBsqpTyjx
g4u9k3cZPrKEUr4gCfa9cleQByJ1no5jwwHiaYG8OL7/pAiX39IVt47JvgZx6iZJxbfZpxQ+sZuW
WW9gatN9i46djhlRutej2Tkus685Ozht3mFlCLP/gajlaParrN6RRlADPoOzwChtptFm1gou9vX1
WDPXJWX5SfqlScpIm5VlPbdFcZupmNAB/mofHlD5lu7C5iJb3drHB1+gKO0kuuYmSQtEVvc5SVBj
FeqoxY8PceCd0vqswSrEQAAQr7QAMGM/j5CGNnPsZMkOGoYI4MooKj83Gel/FdFo3+Uxr+m8htGf
2YFrkEjmySusJN2sUFwoOwN4q1kP7bX+4idzng5DA2ujMJ6lE9pqIa8PuEsVv/N8HqjyJQN0GzIc
GOmBO6gfgudsqqkIifvw3HD2LIGRfZTOSl3MBxIxkrUzZCKwcYvkO8dBvmByHPGcawN3U5qQBQLi
1E3zbrEaAatA1mnhXmkKtSnj/HddrcWiBlR6Od63S0ZF+NdQIjcVVKd4l8+I9yJl27ro7mRARvtB
+XtMru+yfg6eX6hlO+Dn/WzwmO4z8IO2+c+jZqzfn1yFj5r2++X4rya5tAznkVR5ulUHPOeb1/d+
bcqKeCaolCmR6RsbOKJhTx/qI7VztW3iZEUV2+8mT8BhrZaRWS2y5mNINGB+y7pAOxKhdNacW3ef
pH3wWXZ0oXDR5GDU6eZe/MEUz5FE8AMbGvocrX4n3LJ9TJLzYmhhGIgN8A3teD7K7Npc2F5lhs2n
n2xq96k3Gd1JhF/Y4xlfgsQGMDe/FrZhgsVsFt+Axwq6BVOW47uwShfUQNmIGVTEyrfTCtDqgiv9
jV5skvxKchePOUMkr4VNAwVDaoiZtn6Eim2XdtzU/oR3pqTicBm0wCYZ+rCPGvzpPSWLr+kwJwdO
UM6WCZSioGSUEW27IIo6tKq+GpJCxxUFNYxwaAuupcWbK/4PsymUV0Q9jT0okittrbbTy16tPaSN
1s055WX4BEE0Hh4OcKYmmxQCouF3UbljPynvult+UQF7EkKiGQqM7qD19wkeu1m1WC/P66NP1Q1C
n9nA2NpCAi9cTzVVQtKEPPOfj+XqnjWa8Cg3ZLecLJe4piy/Z0OPzUieuKGwKKBDBW8L0YQXBXEk
b9xUxNCK6QX3xab+IzYXFEfhW1JpP2I0A4gcBJDBKeXli8/IHQ7s/9C5NilBT+2K4cOF+7S6anPX
viyrnBaCEXwrmwvcFfh+oiKN2GwpCi2vBCXNPZGLKm1DBOo6YM4DBJtUdMdNiwn4hdLz4UT0FzFz
4CcRE5ux2QPZfsXFF7TTng/+J0dehG0CdcqkWbSCEdeRnf1xGtwOJ46a0Sriw5Rm+8b3FQX9YoTd
+dkqHbIEGxhFN2LzsRzuJ9Hf4Xk/TniBDK6xdthY7wIOkHxR/v4Wi4Dcekon86Mxox4nRsjEx3mn
4EOilAMS8nKkA8pdK+j5gWdQnHhKZ8hRn3mN/YDrlgzUe849vcz5jcW8mHWoBQJ6nZUFdI87aG4U
kfsmHzm7Sz+1oV8yUhRqtM1Jq1MM7iyyixWNNpcoyvpsJCzwUlmS5Ht2kAbyZHmhq1r2BaQ2J0Oh
X6lu7R7j0y1U9QSOMuMRczf5XQQGAU8v+5dufyaa3ACnAHh2JBxaq1c6nRNI56hxP3AeZFCZEIME
o1JFwS11F9y2srpY/UDDyHFIw7dCXYO78uq5QJX9rR0LuZ2PR3U9+9z5uz6noMxpoQWHBP0MZFvC
jldqnRUgu0aNk/VzepnMtQxFL3+sq4gbBnSX3/AF9pNLKD+beBg6pmYPbPzaaySQ3BBndvYnSDiC
kz7/WZWYL6KMfHnneJaxG6uyQyS84l8eDmFdJAf0YC9CETm8iLHzVqmHgFx1dNWcFd8viwz8iTwW
zwWhlg5FAXGTbJ9MSytQzWlN9SNLDtWEQHK6YXv1kF/x6BVdR1nFoHOm+wcrM1uufZAFT9lZSNFs
NSSe9JfTm8RnM9M4UAkp0kbD88sfcJDVIA5EkcSDsECWMMjkKiX/u6SXCSzmB9m/vr1DjepBM5AG
a1pfV11aSTTSQ/g1WjfzYTgdscj/1DvQZaCZYoirrAbLRAZW3jtsdsJhlDoCoq3VknFjC71JAkoW
ipjUvZJ+VhaaDq79Uyu1nVqImbQl/EoIL92zBSEO8Yn3x33ejYksOz9KskUDON5of8SKECKK4eR1
jK7Ea+6WqwWfZ1m7HJCeJ/tfs/rnRZuG01MLOOznJH7BbdgP9DG5q1u8c4+AItrLkvgMIAdmD+6h
VCUDxM24njYv2TZkb1RYpApu+x+YRZPmk7e/iYXbTlR5+IS8+Oan3Ehlk21R9/c2UN3bLqegsfDV
p/1ySsSDAqKf1V+BasEnfb6j7o7E06FZKASOAczq14Zlh+ibA0h5rHFZyeJhOIPc11t3RiYJDUXs
cgOTjUJ61+yBAgATzungHdgZgqLHHocbE8dJN3lGx4GYOGcjf7d6Vri7dnSv6sXZAVpO0xelOYOu
rJ2xjJqCGOANvTGWen46K5D8MYnxxIADWJS2i+6giOf+DBZwmZbhZ3k9alCOo4LIHybwnGMQiaPf
u1yautR/OnEVHgI95ySEH7SvLJuENQbhgAQ61ZFPAz1d2nzKmnxEexK+5Jj/Tq0OPD8dIjzXSgrt
JxocNuOpVjK6KPwfF8FC8cPbjkgfSq9fQpdUkzeVLPWY4wW2AngJAQxMswDqgAo7lIDVnwco6vUU
PwrtFR6d+vzKERbmde0vQU8DqGPAf2h/hdqmmD9OGvxaHJ8b7k4AiaOONI5bIMZW3uX87EokpbGE
O1SonR5JjweeXKRWlV2i3NhvtmQToVEexR1XBI4zmVCWhb6JkusKch4gmQ/5Qa6rosef9UoIO3o/
pjUNbidB9zDUJ73jfYDUWATj4ULLGDKG4ViG16OegHFMrZCtsc4yE3pDBiI7w0XyXfH1tyPK8/GC
OKa80Hj5qaTSHB1m1nbPkjf9EZrHXTXRFPciamkZxRsrFyERUjPoFgDa1UKuvP8RQaS5gzGWemHq
aktJaWeXo1NAK+ujiOCpqp6rJP9HSrQltxeSRH9tHPMmV5JZhydTuTiUBykCPnv4vsdZPg1SD40O
eyU+S5zEUmD4bHm95WKK9Xcst+i1fZM/SSHrxXIqUKxyq5hqrd4Axk+SV1DBfcRFimdQgX8VTITY
1kYqhzr1pAnNbZvz/MXi7cCPPZCCaKiFDN5FTFBqk7hY5jtz6CRut63dIOKs6Y88hASd+6/yrZni
q8hfNAO+dOvbgobw0t7s3DiTY7qZVZPG6TNww8Kdn1p/mPTF5OmSiGv3ao6SI5AXB8UvhaTmFVtO
GupobYs0gtbkOPVZs+6a5+UdcRbG7r9JHaXjdpE1M91TpNqO7IqZuiNEaUikOMx2Gs0j4WJEmFw3
mlSeGChJlMDhNR5avP5/hOa/ytUx39oNW8C61vbvrZ1MXkVB5HE42y/1+zjHOduGm2RsyDI/p/EU
8Zqr4F7WD3284d8NnAhMDT9yL7NGLc5DwOAcLp5KdzZW9JSjekCzEwXdqqHG6V1EU05Cq/I0JjBe
/APC6bX8Y5CLjpHk5x+i5ihFhVKQ0u8RWhUWdWtjPYX5wTa8ekqdrE8x/SOfgvrXYPbdhIvJmL7b
6QP41Wva7pYSgBxTt3VTE4fzfzPae1qxcGmEGE5qdM5qoaf+Dq9v7UO7pVUYBvm9MLV2ZRaPQ03d
Zs+L4yXwMSLPki8ie3pkCWLYvRVbnPSfMyuBvGpUf1AympDy1F11+XlupMxjgNx9xWL1xZRi3Mm4
1KfSL/opNw6DhDq/5ZknjrlsY3k+D8MzYnVQSt9gnFGhnkLnrecfqL91li/p0P0Q9AS1pGS8CLXy
uOo7wbAndhVtJ1BbfsTnsSoLGKxvAjvaydn7HS9Fg9LYduF7EUNkLUSNxbhuPr5Ex2Ni5y3HwVX6
Sr1hGV3JM9+SqlyqRNKXQaqVGezivfqmhjOcJ0j1qcTWe5rO9flefnmlZFnuPIWxEzpnvoYmxm4e
TQSCGsVjrMC16frfNUKB+m9Nn5BVPhLPVJAwU7nC1mHS+MB7vzuIxUZQNy/0+83DL0ryjtGMNC9j
Q3j+qfxJNTxLmNPFGHRZ4s47bZ08WwFXPMca+ON5BQ33ZqPG0hsKYQ0RSVlqeTyDQG1EgHmhoM1V
pKsgUw6BSV76JpWnGu4EHyofnHpYa1/JzVdBQXhy+yrnUAcj3+UxWQLuu0+1UD0gpF1shya0VJ3H
zQv3UFzekGyK1XHGjTthS1HB7oPTzKAz6L7bWtOBHEn2JTX2eVkXYCwn7/bsH6xMjO7fFP/kQ83s
8dNL1Y6fGshtdvSyDsXg2xJyvHbnuN++Jqapeoni/qAIB8hLtx5j1B/aiHBrISjW0FnRTTgYGDnu
OI1qsuQY0TEv65v9czPh4jQIhSaYP9XyFF+BZ5OTzLCeu12OgodLpQZBW3aeNRvFmZcya4CGtARV
Tl4oMwhm4P/Zgot/mBy5yoEwIsaJny/uI9aSUg3cOMs4mXBtmE7MmkOCJ08479Yr+BsFUaWEq0j+
9kN8bBGvAZnM32WYaSkc7LijZiTX4hLy2G4If3y+UdpbkSty7I0gdTzIAtOYfxPH4a1TnsDcwx9U
QKei85QGKSDiDNgO471Sistp35CVi+zeDgQyiDq+7vssB1a7TMKKV+XvuPJgTg2jB92HaVdv4DtH
i6yiMDsRi9SytO/kvQIISZ862mPEa1FSxCMcGnCooV7EWEqCYDlFFo0WwWEgkoaJ4NqPV8VBRE7S
qG9eAKHYqCJufSlrst7d1e3MSl6ZDInmDwZvOQWpaMCxDO5ZVcRu49E/b3xUvOaMHjONOMC5TVyl
Se/4COJ04akKJ92J9zss49Ib/6R57iTiy7d1mXsu6+z3F0tAys6tOKrBvkVPIaJtFvL9sojXTKBK
15lnwaYe4nhunHZ13k5blfAYLqhT8UdOEZMQ7yBII8mH6Hcw+aXtuXnqC5CftXDevlS6V6qTolZc
9k8JnU1S4n00XZkwCKnDT/JC/2PWMnA8v15botMohluW9rcY33elKhuoNJ/BWpb89tusIMNSPMRY
iTXKXD+PQ6FIYQYEacoPtxSaumZTUzozjOiFcnpFro67U7LLNGjtgHZbAlf2P7oimC2QvhVxMQnX
c6/SvlBmjx/Bd6hLHE0oP5h3anHP99NRR76WnAc6LwGRZ7Zeq1liLbpl8yQ0sE8NX5NZQiHhpHj3
8v2RB6dqoONgbRxu0EoUQjmeVMq8upe6fwbl62ZwdpZVywshl9jw4T3RZwN1gjZS5aupiSK4KUrN
9ok6gp9l3N31DjUSk2LPGNL6KxojASCPm+zBndCvJobyzVjctQykFr00tBh/f4LaSGQvt5KKmRQv
8+hSFlJtgRNCU69fxcau4Pf083jI8Mfs+fZLJxoiUm2/EDy+1XAJT+lg4fopLQyzE5WHt5zPTxhN
mZK3CPnVmflekOgZpsdjhsqwmmtKettjdcTmDc8t1cgnZzq6K02kJ1XbQfM0lvUWH8GCaxUZebCD
NDNUOUp3nLf9DjXj1vjCq8sgtzXAR2kRnHbIrthj7rF4AkCYAgiiHhiUSwItYOoN8Yb3zdn818ER
ozqTa0VHzxe8YGQbjCl7lL3RXw8G4xNau2h7+lUEfpOGvSWx09x7/cjHOnJxdFMlowS9IOV6WksS
29OxkG8zLqP5HH3xGzoh6PGHd0CmuLkOmGcdvndoOBfG68RuMMQ1NNroxT4hT3GmywhlFfKqnA/1
4GDXa2cLIx8ZY0rpj5Gbo3IyIv4K4zvD7vBPB/u+kmn7NEYuXyOE4pL3CeDbriA/P5boHIyLkxvt
9fO01XKxcq9CSfLivc9il0gp8dn9HIrnHh3OaXViQgx403qr/+Kcfkd/BeqQUCvF9GzSyucYCGG3
wo1z5deFrSsoxM5YARts90LV2DjuSb6YDOo8Cjx0jsjIuQKTx9SykfTy1fnqXmp49a8IwYZwhC5N
aMUXl8SqVIQSXh4IihRSSgqb4aQSjT4Rq57EWTacdVp2LAN3AjWErbnbuOOWkcC7XoeWrd4EmDdP
RkbMGctOZIXJ6o9Tp/qJt7VTvfz90sM+0k6aOwJ0GoQq6HmVWVKO5vHJoYnlsw26Wh35BQxvxGFL
T+AP2nUjfiBqLSnxXeOM+Nu1OnlEF8BuAXB8l7E8j3Rbrhn+2fcXqBrRos9lPNGFtYd1Gp+NyL5z
5l/jqSQa1PwwwE62kJwfHn8ogfyxMN+j3iQe8C00+FmhvOc6tffruXd5rrtxMkpGI7m4Q890FyDE
fmxC+jJwQvae6J+ADMAxQFgS7xqnX7go3WNnH19pOTndHj7xpK7IqTwVURHeTvBWWytjjMOJrmg+
ZSyMBjtQS5N6cJyMYu/rTBAr2qwChVXQcUcln+I+meMAu0ZFMwD88l1y8wOnkzJ4gqYRypXLB97j
ZI4hCGif40dXssrlAPHWmRajInXsfx5QnoVlunl7r92mnEIWj0yDLmvC9Y89VAKB3lUff67Z/E6h
4IITiVPCiAc/E4l1bCzcq6ShmADJctvWL22wcc54kYF8+b6ZUtVAzHeAkoS7Xv/YlH+dOc/zpYXj
eNG8+qG7NGEe96vUQMWXNvGicqoVdw4ZbGIrLUVRgq9M9HPMluJ4FRL+B0wIdp3a84dQTtiZDS/7
k2y6T03JMXRxuez9hBMnqiochbqdmTC4nWIHKZEV+Js6+caFBM6xm8lhX5jCXHmTtBf4t4OCTW94
XRfTvOywwJ2/4+UJVJhFJ3IJW2kcNuIgyBz+esT40aeUQU8uriDTouCnG1p3kpTrakByugL/c3+n
NA61I8LtLtiyNxR2Q5nfjhqe9yUt8ewAftmy7VXNZKIs6paB8EtxrYxCEzbh856C/R6P0h057CY+
R8O9rmO5HzB35TZhZe9QoOR9hB06RPWziqQJX3yP3x5UZgNBIDvfFa6z5vuri/4xukeyj1vGmTu+
/kOlPNCy1vf1vfdmZKkYA1znDAYF+eiWD13bkKdoj+awudirGgRlk1jiPWfE3aKhSwTh4RWltbCY
3mWWoPIb+tJEaSmlcEtX57lwJ35CPfgMmgs8B22OuPbZHpEcWm8lUz36dExNVOiI7BmDuKHk8rWJ
bt9An8HF2uv5yq5sBrEd3xdc95KoJPJ5iA7JSdDykVZmL5T+RQzNrS8DDCAV7HfKzcSzoHwLdY1p
hGnlMkyBXRNjiWUNMP3jr2GDGzUhJMocoTO6mZ+9D29AAReqA04U02DfEzK7Kow0EysbKG5Fk5yN
Vo3EtOjCkddeC0BwHB4jLIQ5fALmQduRVCqWTWQbHdbIzd5DgetzPRHcxc12ghoa589Nsq4I/BYl
c2WkhgEIV3KIIT/KQcF7rUCc0PbbkRYOqUuVtdftTrIN0NhyKFo+8knfoN3tMSpjmK5GjXqKZe1M
aABYZ/lDU0OazSlHilU5inCfusIf4tqopqlF5SSa3gtisxQq1VjBCuWmNQy9RclvvFwNshYS/4Dh
Ms8YQquDID/JKKYiYgT8fB1qaKHy4lW5qa9iQEW5HxtZF3Ta00sJUjU7eJ+cNUJzL8WGiy31+QCv
ZGpwbj+5XSYHMglemtXbGfaKcFnD2pAetFudB52P8FHlLOwbSdtehSl8ln/NPzDj8keC+CBaEnmA
apv68dTBdyrgpGqImyGx86kqCm9591xzp57selVO3O/SxUZoNyOlwHr1l0ezmWlR5uHV966y9UPv
fBk5CPbFNOJowezXtnRxIMglhcZsTBSj1fRuNCzOUtgxIwSZNZkuUoh07QhrV8KMgKJ7ZmSqh6Hr
7leWjTZBZIxtVm66Ivm/aL9Gu/sl73JkJ5VDQ0cd6iUwQnLpgOWRJ5VY9UnhiE4XbRZuv+TAqWr2
DScG/dkVHNwXKeT+iTM250FKyxDs/QUKKtSQ3XrZOb9NMHYj32CDLz+cRNTYSxXBwDiKY27qpx3z
OiPrUTk4tv2Efy2ImnBiPWNK4Z6eWD615bSXLh8xniHxV/z3wRdYUJtbsnPW233NBFDNca6OuHGQ
qosK8nlGN9zacw5NPuUoFG+XgdOkTpyVCLnVTAM6Xh4PD4UHDWuY2crGCDujlCQM4Cqtsz7slPx4
riVV6qqNeQ0PfIeAQB0rfm0ykVLLslBWvmDIMGRah1NWx13od/FyDXnog3gSEngu1IyEimHJNIyp
bK0b/2YFjynPBDSgRE8kHbULJ4f+RPsdgwesRFNvGHU5c0LMM4Wky23JkjVFgimrX5OFo3fPYyci
MRJcvA6TmdRSKBpj+cwIRigB/qSwqTG9dqHzYLIS86FyRWzGCXTQBfw7QuLcdZp7UFYegB9fp8Ov
0h7zfZ99fpps36ug00/aKErRVhEFG2Yovbyopzw7IoFXlPoEDGgMF9fAFYdTV5kcEyzpz49BkhoV
9uVR1577uGD8rp590GxwZXwJcLneIEGYU/KQfMW6pazGfMQPW+fwZPN8N7VsyP0AdnS29b/4eYiP
3rbV7+evv0QkSQ+6B3Q2YXULigCTU4oUmyQP/KNsb7b0HsfDptXvl3UxpeNvYJeUV/Yw8z6TLUyr
kIjVJO3UsN9AvRydWeLLRwSGD4uCPcTsFQ4OOM2OFs7VOfdHkzZsAna0d+zJmv/mAhiH/k78/h3Y
g2N4nRdqsGBaPmT6Jj5XuJ7/JUEfneX+EtcWRceNfDVJVNnnkjROGtXwhQcWO/mxpT2YoJSrHcmb
81VxMeqC3wcHqBmQusbQ83hDDSf71sbqHM3rMR1LWKaSYjJq5uENZnY3k3ZT0lRj5vmL7ELo+RuD
0R5kbf1qwHMVBuFPBZB2YUFsVCLxhoiAvCnSfVmxjiQuR2wL+s4rQre99WL2WiRFMaIOEAKhxyTn
2p6ndASHN5a6CfrE0QPg3pm626TRDW0truhNFkZr0/wK7RWr9yDwEh2q4QlgvfpOMLbxGQpSjbAb
m1RVwqqTYxjqlYBa7vorPFOCGSfNnLRnkkUbmD4ER7AWRq7Vns9h6Waa3VHS2cEdoHcqMrnIdOKN
/6an8fyNeYfxbxaGRpocJT0L+vbI0V/fccN2KNBevOlMyGmiVRzz5k2RZWfEZM6pLudLF01lt8hq
FUJocj16NGU22Apnv4k4wfBh0LY/+uM3ECBbsB9Vql4HZAh6o0I2x0AyKifD1ynqT0s2UCxdunDz
TcDfSuQwpGiKaQafSbvqe99Z4+IKLrJi0IlyB+HWywjYXh6/dnTWcb6+jX780hnTOwBBzjQQxqoU
MxAv112u8tuiFnwe4xcMXEnxOaM8vCAiwW4/mD2gPCufTxrskxkQ6xNukoeJIlY8oL7J/Eihc3J0
iZtkG1VtueXZVK06zsSzHb8dl5iwoTmcdEg3pbZt6g4Y4A4LaCqeWudQ4futJa/qiF/pGxw/VKg9
6FeAqqlcRnN3aUcbHp9+paf9xHAuVSZu9YOaMxzn8+eigA6p0hOVY+CLnAcFaFC7TeNnGt99JiRM
gJ1iTfS0oE3le172U37KYATQhcDl7dDHo1m9jFcNIau7gLXLfDk1JTRga8Okol20/86rRRfdVbY+
zLjarmoSBBg56Feb//yvEwmGa1iZkFj7AoQUB6LCVqz2H7zZN5Q7gF8HoKU2kIUgJl6Q+o/oD8d/
ixIXG5fMnu9HkbnUiVTgxz0LXXvmdJZ8kwiEEGlmI28H6yiKnIN/AE5zlqofy5Zq/aXvafTFX5Vz
Fl2++78n+hBkxM7A5CI0nda9wBt/G6dCQpCng+S7nrYZtpdi0wh18p09LWfSqx1PM5cufbi3W0Ty
YIdntFSWMXX+2SGQ502QEPAJVsa4hJesGgPsMTpu8jAPyRNoQRG9KyXz30B1m4EAWtBlO+VGuOST
gdHOdZRWr0WqhB3Gx+fqCUcIkD+NuF5fJxzzLQk2/D/kYEK4eugP0/qyj/wYKBLSkZR/K/CmKRKX
Cjwp0f06fOOCTRpIhXPDmh2WZ8A1gjnGkDJYasXYaJ4+d0rYXbaWBgrySz27V+EEsNOXrrO0FRhW
gzKRI8ZKLRuwwZt16Aeg2W/FrYfaN1llU48lG8GZqOBcYF0uR45DRZaHl+LVkTptb0+hW/Vr/o1B
jdY7sWFRC14qPKUZlCf2UodxIaN2u/Ox7WdpUjsWnQweSRH9bL6N4xbnJBXx+IOa2CFW8EvnmSY6
w+xJWB8l/zV00pB2DaoYLKMELwbpXE3OCCz3wlGm7R24EY3yKziqQ2dwdDuI8SR+rF/rzBZdvvAz
hw4F7ubWqigo/Fm8o6X9UZY3cs44Rk2pg8ofCAGeAbqTCpBIG28ECLFid0/LWNMuONqo0f8ETS2h
UC2CGmW2K/MrC+nFLJ8BhtV9ALP3jKyGLSoRIS1SXb+HJhSMNEC4xZIbV7oQUvSZb4C9hiC3p334
Kuw0PB230EfHoYQZEmnMDL2gscMp6APitI15QZ+pdS+xPjw5InFN9OWG4PmfWsOo9RGJIc23cGju
coMdMKpOAcLKx8qPhomx6rdiNU0D3xv+6kjkV2VwYxlKNI8PHkhboYiQTv+LV6FyvVXUirXP3Sax
Pq7mRLlKMgM9PHddW++ZCyjt78BnfMe7GlbEb/WYTs2AMcmcm/Cdf278B/R63MDUv8vFRPb53vUe
CzmgGmFxotG1WVLDJEkMSte+UKkP6UIXIPxD6U+8MRPpRgSHILtKsai2jVZtPXF66TtNsU+TbB2O
MF6h/r1JtKGwAoe/CPb7Z0ccr6Vzm/ocrUc9Rd/AyTCINQzA1WJSCLgUuQKDKq6Zqv+ctogjGjcQ
h7uuJFbTiNyeF8E/kISITmontc/nh0RRgIEni3n9SKusV9iHTaXVIQeQJmhYjlCwcI8u7x6GSJBL
WErhS2hVwDVooVGqmLlFkyvnBZEfFx9iQujbUxLfUmumc1sB0EXCzVqAk02iLzapQY8Kv9TElRid
YR4Pxq4uyn38UQCaNV0mCXp3mrjxIpCW6NIgsaqnvyEikk7lWy8B9nWgnTfj1jFkVDEuUmDjZIzM
kDhFzd0ImEqQz6N8ksHO+gK0kp6+Po0X7N0bLDMjH33MNkPuPfLUPpam9KT6zhPxNkCUfmJN+ju6
iUG6dOJL2v38xksLK/6Sx0WtgnE/xxsSliSumVnJLGL/+wvwvbve9ozSyM2+Y90UoSpUoanvDK09
VKlis9ivB85QkNsiGPPjWM27nLCWdi9gRNb9Gxn5pOOGf4Y9h2OTrIXn064ehkWMsvjFPZFFnVXb
T/JQDSbMB+3s1mULoWPZxH1U3buvDd3zSIJknY+suQs7DOjz2x1WpsGiu1U3NE89QBXewgG54eyx
pg07IXANC5HhfI+EHd3Czw/JRW9BJUCFHvRZ7wfe5+IwCDgx3W8aZjge3gRdlyWY4VxdAAbEiSRf
ERb00/QZUXhcKwV+ol2sNDtX6eLD5pqZpr+goWRXiH3XKdon/3EHa0AkUemd48FjhiTzQ2X2kWA+
T+Fli/tuuDLaqkanXil6gedStUo6NhZ3XMdR2aKyBScUQZq1H0/JqpTQWe8hXNVxmLjLsLxZJez8
dRHd3Xi7oXk+b3oM7kuTgl06IYjZ8oyXbDkzLECMCL+0vaDD7aWgjzPnCnKydSFQzHMnUoNGUxG0
zEjyL9XaXkSk7ArDF/F2lycUzKivWCuFiiVqZqJDRRYJiUL6EM2Mfplzst/SaImxjbh6z8EuaL41
bPChAJDZNat9xUISBzvkefGambOOpYu+nSWPPv88SudLa23vGGiGmZumjK17pzkPKesiQDxZr8s8
jsImpLRlEbnOs2nnwC7EgmO9uXi4JE+Vb3B810pMNIawcd+Y0hB8Pq7IilOe3wC3avCuEIpK2WQo
S0szYa7CyW7GcuuvrH2uM1yT5B1nm8iqLxxmYsaD95Ikd5A2nUox8m7NRptnYXCdLxtRybdmholu
Cpzb9i3Qm95Tkrb8OqZBiw146FnpcOMFO34dcVV/ctlVdno/kZTTFbQvGRvDUJiHj+q943k8zFro
5V+abMFtjG5erEnAuM3ELHo3kfiW2kZXeKMLPaRyHaUTvKxWs5FFue+j0sRVjV9R0p36p6DIPv+1
DZXUy5DVWNtbT9/YM85U2a8VwBjS1LvULWodWffJgWDake3p6x/CQ3Mk7O+CK4UxgDPLuqhos8hz
C/YEtieYjMuTTHPoGevCNG/HVo0JgM6EBRvhitttk4Mk6OiaV4NdVJiwxNCY7ro/6PEuoJy2YpKc
uTm41wz9bGqGlu0+MgKX0DAeL2fz5Q+/aBqTY1vl2dlXtjSb64AzdlBlX0bDLO604GJblYTgZUja
OYeSmXhKCK2XyJ93ba0SEvSZnU4wCGK2UTNzNuB3S6UPnJZU1vZjb/C0EamYLqI7NuAnJHYjgExJ
51lwyyghmE55baDS9W9hHYAJhLDCCrVDBBLZT4GfVhJbBo0zmRCAv4rpPz/+V8JtsKnPHe6LbeMG
OoOUNnwT08u0DEDPYjlGSz4itoB9Js+czCAUiDLeBerwTmK97czEj8vqp7EueD4KLlsMS584jZF8
4BeU7YbwbrPe2jf+4E7+V9RkoZxMKEBlQ+8kaCP/E57GqylmYVZH5I8soiY3SP96yZctZ/W0r34o
lWw41qbKaggjElcaFIaRPGdVnQBXD77vuFrHtlc4/hAC5dsgJTR3VgSJkfZ583DwUvxCfaCS82pR
OJvUqk0xMTFqLnp/s4I0xvTb87W5BsVq3ybegUZrENx9law+drHdBwUpcrBRRjDtD4jwYDcckjfa
2K5xMf1b/44D9RTr2FPrlk8FJ//ScLtLoKzHZ2QfoCxBR6s81Wb8spZX3HwtmCc1mjIlB0W/sQN/
pSEqQaxBYElDoaSqTjY/lS+VvpP2pUScKIJV/tlZvVl5/P9DFau6DmrT4Q331lQtaTgOEV45p7eC
99+WGfkPGCs+FUR/LNrhsDOHZupf/5EJXJhFy/tkY+OEhFtPB/HZ//nqxvhxjSzYSG0F0GQvHpP0
rPjh04T+jbfKUoKToYg9AtS51Hp1RcOLeH17RN6Rc8++6S2cKZaMkpA4QcQmvm9FmyeCfQCjlpFN
SDaBkuP0CT/mZEx4k9MWUdj3I3XP7uC6HH0iepomRUicOhgXl2EQfGxD9x0uNgcXnqEABDwMLpnf
Dlo3dm6C/ShBdUP+QIQZwSaE8vr7FZa+FI04FKkyWo7JdlrKY+cA/LuTJsXfeKiE+fRbrHVZtYUB
ktuxv0JWquLn9uA98whMJ/1XupSVGRkey9Hv9umj6N6bJ/9KV/w3pz2f6w0AMxZBpq/8DAEEcVVr
Xe4cpwSyUVLSRJMKkEfms1tzyMKz1ir05VWNcx5gqpZTR5J5mqPmnB9k8eE9VwikZ47ffRzyvSUz
eMQLeAhSEqn0WiB+/dL8VazEK73658E0b52wHv1DvHwT9a+u5B+H0rlfCNGNFTbOQTIcQraZjnu+
koZy5xoUeCAxIeuq5Nhe/AJsV/tMJUB2AIY/3LkOvycXiNC38DH9s0uwyHfdPcP/yp2uBAtrJ/b0
FTCtzLOeeQPrKwZaPysAPPIxz0MmPmZ0liVmP0h0RWPnkQzR1jGD0fHUVfI9lTtV/H3amRSVvTTv
DssRBC/EXMPW4nZLwZpjOLLX5/NR0yP71GuEN6tPbw2wAUAJgLTgOKApbMmoryLQB+uv3Xgi+J4H
NUYM0FDOJAaaOb5n/kSy1VrqRX18WGhhMJn6MM4+bweeLrLwvShu0NtGMCPv0y1DflQWtXy5ZJ08
bUHpeqlCp2ISEjo/SZeX56MsbZS/w+TCWAPBuXKNS8uYSMQNbzIgl3yEug8+eYbO9RMU2pwGlH9T
9vTtBaoUbCJcbdhDXhfx8Q7gZ1U5yZk1QAJafNofE7QElebdaHak8Io/CQtda+cDUMMC1mpHJ2+z
qmg0KZw+j2FlRzDLZOlNYWyok/wag6H3iBO8s3MjzEpW4/O3b07SNFN3sgqSkvaaJcdJfv8hpOna
KbDcDnfeUiu5Ck+AhA1oKF7GeD3jfraCCzfsujZtldq4/pjY41Bdzq/4I9dPNLeaILvSVyH5pQrl
j08SFrrbJL63A5pflsBYU//dwTe9Qx4UWvrLpM2bUq5yVEU+fx7KRU4pTbqnu5gtJtBiqS5Ij0rw
2j7B46WeXs+KnyCL9Tg4AvLf+pXBYsWDWYeq5Sdkl7nZkHo8nqmtno5apylk362Gv3AOzbyVgs9P
Bpxpfi3EgyGihFTkzIF9lcNVBL4lU3DF8/ohXgYj/WjvtqIJItHXEF53//Sg0QQ09rdOojokQRSx
zp1AVmCr0h/zkgZIsFeGgRQ7Kj4gtOTEEapLxnYiNBlqOQL5HPLec+qfIfUbN7PiFsF4++3Rit/c
minwlktpsV3n5zA8QGNwrTnAU/O3NrhZAKMY8SiXnwpIE4/G6VGwWGBlmZCIbFCKukWj4RQG49UE
Yl8y6twFn+wLm3pt4NvyOE6+e8iMo7Q4YdmbJeb8C3HLxB9PJffm4rkbD2D8B411g2i3JpLZfn4i
CuiyfPa5FldPs6jF8SDrBswZpodKsFUgHTwG4VtRbuQYGeJ2KhAL4ePKCwcPQ0Bchtg2OAaPAIHW
0X73WBQ7iDuVInzRmxX9LN3koS+G8pXHkt8n2K1o6fv/p3mexDg/L/oZL/1OKf7kX2pzchgCnsPj
2S4W3vBcJRrfGT3UUyzU/xPYTfAruDqXrj00DWiJLL34Z3paRp+xPYkpI3sj5S8XV+CxXudr39Np
/PulNW91MznqlrSSto18ldSZnZ/GuhY17y1iq/lop+UrJe9VBSiAMcfIcw+j8Or7njc5nhscUMUJ
K2e6lBfCF2+3nv+5a4rMdZ2VVsKbvei1ozIcXHoWce0fYcACcz4/KXJNpdcSZl0/UKYMWtaGZMLq
qmSd7UaoA3cn5VC6+VIBdgmZQ20gj3xxTCjfy0gbKmjYeoNKZC5Jd+6pw1HUExcsKLkhj8Zj4VLz
jWkJMz9jU6fdXHqRCM5T6tD4ptXnEnVK1UbMD8wk6WcTPli8CtJDuts1A9rNrgJ41U+8ZBTBZ/U1
kl8aJ2pKDBUZCxgvL9EFuDagREyUcGQ7QXx+JESYI2gqXHPmaNEiOuF6r6SGrLTdvNK3N+YM4Jm3
FQ4BKz4gi9DlrwxegtfrEjHwZJ4FIIuGk4QScuxQoU6mjX4k6OiPi/CZ4hWg68cnzt+LePEZpydA
nQ3qZwwf5AkSbXE+NDPS9icEZ6UZjp4fGuHQBgiSLzi6lrA+RMVR7Yf3OmywMn9Uwhq0gLssY5TX
XYimP0bMl+mnaVBElnlgCJe5sGj6P+2g4nZylfZ4HBzWcWNHw7yTb/Tkq8TYunkbyYiwOmWySa43
Fp4r3fht+pEvNqiHtWF3AAwtG0QP6v/yVywy+hKSaYMoDdmHSLKMQqVgi4vCs9lDENzX/Y2txpHT
sWMiYh6YGcxoZ+5eGt5SWF6JnJ0zmyiPt9qIX7DzOTPjSDh+d5LERbdl8HNvmSw/7BtSyoFzyuXP
jZD3ZLKLs4irdqiOLINiWf6YGz1EQhXwdUVP7abOVjVO94fuKvY0PBzap4U64oTgN8tfc2WVRCjs
xgTGKSWveAwu9t21Bb0ypudHyelHvb0q/dfByUGzNa4dy+1eQ/WRzrlKQcIYNUCaJcvLJMGl2ogp
S3UGHeXaMckjup3bntVZ/6jF7awijFpMiYssBvurhxuoz+/h3E5XK5+1O762pTVk4b+YqygDQjxv
oZicZQYrfB/1xAVHJCFqicraQHzmLtWPKt0hxQyxUljSjL6sJxo9e21gY+qBGvsDmBA/Jodcb2eg
cdlHqhHfgXK74FTgE7UXg4F5Qab0r1gfy5SNsXMSzih5ci1HFS9zinnPlVWu2HVmcFVqQ1iAQTOr
in6fNCzARUd/Uvj1r67gXOi8lY3ygqUsSKD9hFqCvaLTALp0sko46FpTRHhxP8vzMRlzrBbNgjC6
nPv66NeZ+fiwTeSgpthrmY4AzcfUcE06zAjaAksOxf5vCNkyxWqbFqZ1NHUtrFrHMlfKYMR6MYI6
gGloIr2jad1to1FhEWkKPFByK4wSE0w2vhKZhhgYAYYdSiYXFYvnDAs8KdYuBROn3IbzTOjb4DzJ
mI2sQj4khXSz4YQj0KvwP6+BDR/kwm7fG2qSvoxZU4xNsuKzyu3TmABa+dUfqnVsF1cFRu5QOiAC
/0PTq/g3pPEKbU7P7bWWl6C+X0CDVPH7kWMItaYso4qjkhPzpjqSHKX46qYNTbNDbwV3PTzWjUN5
TmDLYh8j5ZRCwTnG2KsS6UArEhVFJjfgkextIDOw3wMV5YvW/kGAyNfmdRONVse25XxN++Lv2Cma
qt0OPjy7oYGJe425YpFcdzF7ixl8AZtwY8pSspkV6me2P1v4IAMOOjsIUwRzGDTbTHO1bryDVpsQ
kCda+VN7H13avNrS+wCMPWXs8F/ZBS6DEazVLUVu9Y4QIg68FviVWBHB8ymn7h6AOk9IuOs4C1Dw
bZfE0f7mufUT4LU2ynnawt2GgrCdJ+kjKBDwxUTgZ3S2CeiZZ2af8/ePclR3q86jQBwf65cgI6Om
InsWE1FiEQOu0Uf/1PbRKKn7fuqIuix7+WteCMe3WJSmQu37iZLhTls4J+vqTgA/sw27ic/cce7j
Ek5mNGs6kjRUpDjWf2OnJQog+EKwk9KhZh/gtrsgo4yx2IF6/HOL+HMEuumWd9jusa3ZSl++f1Pv
G1SHuIlv09USCWfNDR1RaQdOQ+sZRy3rmnalhOWwIBxbS+QJSWVBMYE9wtGqjYRv0YLPEFZLc4bx
lSag63wyXJjqHVWndYLPArVYcODF9BUPMkxJbyrcP3SukgewunVjFQkXClXC5ItAeIvkaAkeBxUG
xPxRUlPFOCpNdpsrE9DtAL2Asm6ASv8ePPz624VQeEAqfW/aeXDcRti5dJo+IAhfflVZYCi+9f2b
K21XFa5N79h2F65dpzcK072Tc/eX7lUJlUKE97mndt10Rj7nwspRpRTN5yKZPsPG0w3JtVeaWgAw
7ORuD72YszaDD2iyNGA5/Q3wyX6BEHwHr5WLLMP0dBZo1OTiaLbzcb31XZ8i8BD1vnsBrzhEk5/e
nmX/7NKYSLW6psv7Etwqe9AX4sF9fd9BY6mHa238NQ78I1edAwP7fZb5RC3+3K/mRqlyWNOuQEtX
QfSp3IpN9pM3Duy/6rZ60SAuTorvAigQluLZOZ32SluPVc8lUSRbQjiiPqxQn6xdZwQfbbpI/Ayy
0SedA8m6Mn1uacuDMbKbfV6GBfhWw1OEHKRuyQhgmVUrmwWGmqDE2kj7/EqS3DGL9f7sjXFiricY
a2F2wDP4NpezH/+4R4ODAfct0xTD/DE+ZtJLyX9gpf/sa0fsla95QTRt9X95/Kq4nUP96HLAdYiX
lGEMqcPqDzBeF9PFEJjDeP7288xC4uKs3XTSnhrCwP6GTU55SNbwjbSLFUniC3FR+m75eXy+QZnf
SVAHt0TFNCJmr6h59UIUdE3YdnGcUcJQvhYbbWZGxyWSUn7uJEKQZQmri37Obx+4PMPvwDztVVR4
1PwPwR/anviEKhh2EV8FRmV0eFh/w+P49E1EzpKj6AkHf/AGTiuneYmzGQmU1jYxy1JANi/gF1jz
CI/A+EwZknnIlaMWr9K2xOXJKH9hit5S7EIygLGtgA1vw+Tb8JdbQVwXT8CLYqHEP2XotqDg1+Wk
7Mmjgsrhgu5x6UIK0n1v5Ik20qYvwOmX3NTcwE5zxXo1pWs9fiOtg8+tS8YU9Masp0fqzjhbqksv
rW+Sdeed2U9aeGbsTDDVNJ+78mFbYAxmaZwPnG17XyL/LKdbPeWyWrKIlK5FBfrRxduoc40QTJiZ
S4m7OvsP/Y0ag7VX4mIU5ft3qVX7c7vVG0gj2IQrtiV3jC0WWFTDSQPFse7N1D5pXgkeSvCVXdHF
9UqYnFI+2600IXLrsqPb/Zz7nqUckqhZvBMmlMfJX79UziFDo+k6kGOKfRaEOgE952iZq3StzxwW
g39VWyOE0peo/FMYq7cn+EXFdAgiiwA8fq+VMeUHNorO4TuNEeJHzlfm9VqipU5mmPizIjS/8kZp
WH4otR4Vq/yWlycZo0NTeK+jXUULh3YORp1sO5MpXdihfc913IcBFYC8h13F8rgB405kb+msdTn1
yM6xeMDWDE2sWbsVMgEXZRQN97aM1cdz6esbquq8+bMIghWlH+LiKID1QgtwfSPKNADHXrIe39JC
wB4lh6jvzj6hVZBCLW8iMYK7xF8bq6QEIkR6d3KRh4RPmATf3wJrxAvwsrft+iegaWtOzKgaBaHs
yVl+hj1crUpt21knN41TQy4Jl9GsX1Mv3uaXwR5/CxF0s/pvxASMnorPU7TfxFzxiVvjfzuKnzpZ
Z3seR/Lf76u5d9Vg1aQHe7i8zPMD44OPYFonleitxkJmt0nY3aO1F6y6JnawQGODi2pw06hSOZUr
Hv9Se8KyFz06M4ZgiahRM4UAVOK+gvWg21MB3xmk2bh85IiXuYFSMUL+q1bWjI5/3UeLisIEOjN8
rohZ7AuXmfQDo/u46m8ZmmUEIjwVw9U9LVAPBqtZlxGbzDvpGcZ4R0Ri5gbwYvFqoG7Z0C980mNC
7VfrwZ9349Xuxz92uTIitbVVN5FE88W+eyOyQvLPrlPJ9zzz2K70unVCNeEH1ghai/TH0513mfme
nFqkx6zPc0Sts8pSkE4u2c1J9hf3t7Cm3fgmDEPoy5Z3iqv0OVrghX1x5l865Ry5tgbT0eEsNUmK
UykJxkvQRtyvOFtmhpCpBpbXrrc5XJtXFJoG5AFhtBP7hV43s7n57uZPIvFeEHvskumUUjcvnyFn
b79QJsTZerNZvgQ95vjkt9hyiHwGPb91WIjeilYejq5+mX9AIvS54vjMHqkesysJC6s/hB8bHfD2
bbctq5Q3mZETsBgvq28nN6MHAUs8Yq452OYXUxpbZov5nYHG85rreBfrUHfJeUAiKqQuSbJ4kSLD
79+llqtNxDBrsd3s4Qpj6/lQjXUfLdv6tgPCZ0ffKKyQgm6X64C2Y5Xb7/Qz0+uCfPavBYQVH+Du
NbEh6bsRi9BpBaziiHOuMLD7uzL1CGGGwB1bIcH+73HvJUx3cpIB9pOIRMBcB/8ETQJv5ABL5PPA
TSk9IGIZPjziUm5JbN1JlRwpkLMtsWF+yP86UuM/iD9X+C9yMpAFohhbvvvSh205PagNcp+QQmyi
Vzw3Ete972DqNh3Ss1doLxSCgaSnpo5FRz7ZhcMfMSnaUYD/7HPPqCB/tkSn7AcX69yTjj9YNwpe
Swg4nfb84DcY3svF2VBPTjR8dSyzXDc/oE6cuoGFuUQlxlz7Oq5JFQFIdOK2dL0bv7hTJR8NZgne
7PYDpF2OQYWhq4elBc1UUlDhCQzm7LpGXMOuRn8y+sRePTMoC3TwN2EA2eDb3x4oAkLfZyWVTxM2
IhQclKNpcUwcxqseAT5xMKpdm6EIfDcMSAKE0hqW+zlbmYTkNC9pauGtE7tjDHIKn8hKe+cX/5TW
VJLQS3ZsqGdc9t/TeDJtG0vplJ8UKbHm8AhRPKZq8fH55k5xo+2QSH15WX8qD8aDiKq8c+lMASjE
mbRkqJn9B0vPfoG6t2BBbjNy8GbanAlf+2nQ4+XV9qo5twJkoGryKL4zYVpGs6DBG72t07cIVTog
EIQPPMqj6I6VUcUo212KBwb+dKLHnRCyRvgQiDW05B29zfw8pOmolpEZWC+3BRdwo62HBYGCWIKi
Tn2c4O4veLscz3U960O4LHD/bC/7xNyklXJCzh1PxApiNrnCI6BZmF7OXFewaXS7d/WkIzgofg8n
yQxDRKVHIjYyI2GGAHduEEC1l+1DROAmM+VCbA8X2r+E0ixYnyZpEsv9hUqjjNaplpYrjTxvTwCN
K26ytWR8h1sxsota1SuMeGuWojWKc9k+rxaqtA2FoAqeJyoiAGIqV/QEEPT2wCAq0pUxUSibQHai
LritFyOH7L6WEwvmELiODhhyfxL0SteNf8X0DwkLyVQObptQxRCuDuGYjZJrnThZApH85Clucjk6
GoJXjpFpxGI1UgFzPZ4xCt57UHvsKZHYiKIZ9ARKuUODaguSkGGKduOp9AaZreIDE8sBecb+hY4R
ZSxs/rgxiUqbKF/2fRCaerLg99rI8MgWSj+R53144iD/RENGmaVcfEMByHYvqkKgu0Zdz3q1/CRK
NZGQIkqXo4wDGhqSdGafXfkJFCwiy8u8baKr86lt6Wegpr4HHgvl73+lq9palLL6O6WqkNC6yI7M
C/c2eGcpQ3JV8aQK6WoNNiII5setelIXgAFfDFyKaRAQWswmG0p68MWT/HdCuJfxNfhVzUWB6DTR
0Rn17a9gXOCfRDY9XYf1AM8FYR6rsPVzDIsaPVL/RHNZTM3y4ITBUACgJ48p4Iznky2a7rleKfhR
hOHQzuSAoYQcNIWwtOzRbv0YRKDbh0/qlkoeyFbcWdI8Iz/VxuwKUg/SDnu5sZCWHfI3/9mZzgKO
AWLSWWjhgMtjNu6eXlJDC4gaVOQrkFX31xLzpUVAdplAPPwkNa+yqY9pCXcVdwkt3f4tBrdQO+TP
9ktYGL8ryCFgj8HMzrcKBfvSvnhdU+zwRfEnobFI7Sg8D5oPSBQoX8Py8l4OyCVCqF0YyWV0Eb4A
M2i8jVlebFv8sopoIvc54y7FTAYpsQsxByNKA0IoYgweR177IN89EiTZDzYln18ezzk/Lki0Egd2
v2Nm9vVXP7rFljhUrL/L++YgrNXQ41THddxBw0P5Eeu+yGksZBCAXnPePyUkXXNGmKXMCcTOi5rJ
NFhvOzCyjh6sNYQj6+vMZiHWLBPzdG7DRrOlXrOBDgi53B+Wq4JcemDzZxZ4y2Yp/vP6YmVg7BZ9
TT7+7WLEcsF4AsieiVyT21fpv5hKovW+z6QdgGZOdEiLjCaB7ZGmgri+OyZmz7Fv1RqVOehFVSbB
3oe4IunQ4wzNGHxNjFffaYKLPeWSuNpBeuGHj60mBGYQ7YSRPiziAUD/C3l8H9hV3EtGVJWVTbId
xWrmsao3axdhTcIlnjk+LQ7224VfchnHDBmm+8zlsilmBeCQMQvRcuXyA9VW8tuVcHcm5ABVlFDE
kmQwMtFS9Gg90U0GvnG8GQGUXYNJuy2ag2LooxmNXX7jvqtxdnhMs+Cwcx7KFItvo+jDbPLd1HIJ
MG84eORuoJYWezK1R8S7+xcLHi3SwygrIfpx4N8uZ9BDtWPF8c9cRE6jLO4li1uk3nsrt8dhnC4S
jX9/7QYSvv/Hm1JbI+p114rii+NnH0Zgjnn7lVjukF85h+WibKFny5nCBfZtGVonYTqD+bZkmAVE
Ec1rbRB07WoDCSHUNpeDa6KVbWtqmKg9hEpc2ucbptLc7JjsKa3aH3HSle4ynMZk4xHjBN7aF08y
DZ3ux1QX454dV5iu3c0JIN8YEhRzZ3Rgmh54Aa/cXyc+w9Zv4O7+XbLEfFKumNjXx+UMpzrzMZHB
T6y3LpSy9ZDJye1akQ7gR7a9wNlmmkql5R9hpoEo3sVTLryfp84FdXX/nc7+dXRs6/4JH2HElz+B
CE2Tm7/7crv7xehEVOQrVls1iH7jnIh65XTVeoC1cu2ZFTMlqUDebqU7aYx7l+DYZrvJlvzZucsh
uLHjmk5FTogFjvZlh/wymugpZ/WifgaiTAe092Bbf3c/s+Kqf3J4zQKi3gf78EWqoq3D1jNjdbwy
evrjor9CJe6pucNsspfCxZYMifItqsx4XikS2LTim1v2oDl1v+7V41aZdWYRqcGlR4NAwNVL3VSA
mnGjjulVwgc79yZxzZNdsdeM4eNtLlOHdlu1UbiWXqd6h6LUMx8syA2136keLM4tDbW+l3kex8M5
2A3/wxQFtmw8aGo9OCcUGYo6tRLkSaj4vQqUH9ZwcrznjRQ+12qcDYLO37sFUXKWnlxpwLATbPiU
cRU3eSunGBg+bhqvfYF3Z+R2srBjnTJfitlJGuki5ITL6JhHKF1b5Hsc0EbWRuX4I0Xb/GpcocGq
i/99AG4tep5ToM3yMagQlX+uvXsbR2z9YLNe/wPqzfyK7XfhrfzWMhIq1WShqudFHGjxSKw2YRTj
Ly16ImDXJNIJuGc2KNrVx95/OYZzekYzorwiPY0VoVomp8dHrssHhSabfFQo7pJQlWSAdXhLiXZr
9GOzkZq3P5UrVEIkYRek23NkqT2S4zDF6iRYepVhxF3ERn0H7ESv80pUHBfNSj5U7XhS2nItTCNb
9nmkpgz6kFMGGff+INVBjLhv0H+PthgLc4tgKVbUAXHiVIiZfj9gBJHMWDWSMTUwc23Qpe2UZ/dK
Y/Bd2k6cR1I5Rz0qC45BRZ+yAfyaqqXDMWghPc/0zIe1EWyDiWA4A6aSKpo/oRjVslVhBn1HMelx
4C5N3gXLhchAHTX6QY80M0BfIaXrKUvtVsGv0YEVK2+T2fQSjeNteamSKqRg/TFY0nN/Swb+eL7h
mw2xwoPlh4GvjXu06ORa38xSmJ3xo13pdIRR1t2/viLONL6kyzlbZ2a7/wm5ueXTMSLjC6dqqapG
ZHLYs849JNdqB8kTSX0y45JLKrUW6vCIooHdknRxo4BodoGvOO6e/Knn+4Nd9zHoXQw/ayZwYFg0
aOxocH41H9fN12CgRpZh/UxmZmp6GFGxyxu3r0AY3OOkfMZBRt8pi+K6dLePvCsZdy+lxEJYl5Sq
RJfnhf9OY9rk4wf8NHVl7Jv2h3itqIZoE+r5KPJsxR4Dj8Jl5KlM/eY7fXOqHz/6dTBilbr0KFFh
gzaHcNnugE0GmZne7G0OhkL6EfyIPfmlK6vHkdsx9CRxB1w6vgVgPoJ1THnB+/0XnY3Fo43mZfyH
KPQQeH9yJ7T7SXhfCTYzLb1QJiVJflnOZZiUihnglzB4dNsNEFb+MVTRJLs0T515uSpL7R9MuIBK
+YN2EIkQ/D/7wEHrAN0N39YqtgA3rUdhsnzB10Afnb12yruL/zyzEQ4AuQ/Cvnw5LJhqvvmh6dF4
wYSAUNbLKU00kknglrKYathQmQ3vJ+u2GDWwlHdlr3d0FtwPSDuPNycKNbOfpZOdDNPazyabdZ17
nCbU5RAwemcxyWIgfkg6IL2DAgJ3FZq/oXU3V+w5EB7aWXPOKbxXm+E5OmJPR55TyYWZbxM6B1qk
iUnYyHqLCLCmXM/QjmKWN4XrvaM8v3c6hmIB5QlAab4h+pKA085gLB91d081NTknaC4b52kc1lZK
Fwzy+2nOLMTYo1mRx7b5VYhxsCfXSx4htrCxtYPKiSgiwR6kQj3oTgpT86vL+OtA+YZ2bDmpdqE3
zYaKBFJsU8ejc/3oFij6+FtXN/4y+Md+WgEI4txfcVReeneRdLK+lLDHoIH+xCZtxyv47T+ubNbq
5tAkeGV0DCxq1AjL+9Ge0XCF+ReSJecPSwwDr6KVLyKOYftUlKO5HuQd3oa0qhCF9TeY6D9sVp91
g2sGhebJq71Eft7xXZ4SlOFly4R0ZhQnUqYidGkM9hoUU+45foVV2EBt6zn/fI8Krm3eZKEkYu/p
sfKdu6dOp3jdS7FeVGC7EHfITiyNMzGiG1C68iu59/A8SclwvzC0smJo6E6u6+SMAecWBqQ7ve8h
OFDFYtQ/svCm1FniqFtTerF5grzJy7phIqdlh+Cc+N+pbghvk/anUmcwKfW+rvVJJcA/IO3zEJU1
panYoNC8ADTfmZScOECXC7ojdCygIvg9cSPjPYSQlt5Q9QgFijUf+9PZWdgYFE3w5kZyqinFEpgX
dYXuaTzETo9CEywMGvKj6/R9fhI1kaG3bk0+uWnXiOo/Dr6pNyAhR0g3wejk3KzyVUFto4i8VjKt
YiiQx5aNFnRFgfFWBRdRQInZoxQ4gB65W0npCVa6YyB7VMfpyoy2JKQ8WsfMm61YpPxUqwMdqQfk
ynyMpgTGqhZSIScGYMhSd74WPKeKXvdykYbwidu17hdl+pr1ak2dgDs5EZgtUFAQurcPcCJr7XME
C/Kj30SY5ZXIRNcRaMkDvQYVgfgo9vKTxzoWgd2J4/WWqfZ7rMG84IbexMW8i6La5qWGNId3sjLT
bl+nRhz0w4aZiqz5V5+W3rAb2w6jUgS4cn1to0klEeZYYklfITuMlGODBZLrcmLBlRfZ2ujuCAaO
qPqUS05WN5KPB+4aB2vu5zCXf1jho3qFNzv07JfNelSzcuuUw5XrL2pruzW8/jQjqx2YQR8m52hp
YWyEUksx6nkQxKk6cl4txwhLYt7XBvzH9DuRhMdmBdmoWHp/Y7o29BkPKirrXCBRwzWUlA8oSl36
tYoa0roMytV7jzc4bG5D7DXM93SF61sYwsz+rBenuXFWtXihvzzEvo+ax+DTP3pjmeAY8rBG1IdZ
SsBnpUy0ZEeeK4RMfrehl/RDBgPug9ELO2tZaNgB4VsIRmPHwsZqTB8n1mw6/CvVzWUH4r9tiDY1
LXYFtcMUzlHsr8ctWSTALQhJHPKprcQLTSPdJ0ngFcWUrohZ9bDKVAl+8odwk2I/k+TWRZbgaCYU
1SprgLyenQ78Q1jtGXV48vv1yOv8RWn8utm0wYNbJxHK40gNTxWmjSwvmKjWorn9LgEehZbm2EZd
PXZpzliXUyKKqlZ39APl70Afxx01v7hQVIkiErjFYMTBugf3Lfh7bgreZEr1r8l4QB0OYUdSNxNt
JkFEhy83f2zFhIEexRiDzOatyzilC0p/Amq6EUK02lO9UA4mjoyfiPWc9G4hOiziaozmcVt9TmDf
z72AXjQCho4cAYX+MFkhDoEnkUbQ0AHx3g9UKH0FG5tidm1qdyFmseu73I1C4KRsLuXXHT6lkQ+M
KrwT+xObkJ/JljMlTBpXxeHY9fU0i5FFYHVa/BSjI+dzS6dVrkJhcA5tERnfYUJMa+1panf63qJj
eWfd8ugjBOen0q24R4QE4+NSA3OO+kT7KV4oa/rP30SwpHAt+e4+AOxsA6VOPwCq/8lk5uEYkZ3v
viOEJgByGACiMtmpDTX1tF+Ed2sC3L6MJshuz/+hilGbP6nZgERl0abGRs8VGg3h9p07r7sPGhIP
EyN10uqoGnHyDk8X+dZVN86ZdA07t68j3Dv6bmrd1iEZdwRNMbxlLytbRVBb9LJmPytckhiIXYKV
9QpFFZK2n0eHryNbaDyapMsMLzqkBOP9xi7ED6MtY3BMb85ylh1NT3D1vIMqjmIOXpO0BqATKEQx
0UHx1NoZ99f9MD0BAUNSr/IvGCpU+66y60QJM7JtXGzVQkLDuGbcyD1sTqJn8HzrIwmUvFJ41z+i
aqsICIbPwNEt7TGifRmuvxvysycSaU3e+pgwils4vWGBI84loBDBUbOLv/sUPvFiGxAKw5H/JJCc
afHeEeE7zV+LeV9juOvNVfli6CqZGcg+MSKjsLBCM3xBZdJ4pdKwC7D0RX437hJ5QXzTVNPtb/Tr
2K7PQjhGxGFdO4PrcUdXD2XH7d43PuMsxScobjD7QvWwBnEZ4njSx0O5kOxDpgqbL3AqSkUDbOvX
UgZ7wKVUqUdkoa5dmx9PYeaRMYgzz3Mrsx5a9KRBecN2Y75WkzpyHpk+8hiAemeFqWw8+T3LYcM1
1OHI4Am2Gj7j6iC//rywXVqvabhY/2rJ6OX8zR9A5zSzocjF6mH1uz5O0vuAhkEpzs4hSqkUHaAj
o1rSCx8NpGXLno1ko1jH8Z/Z4tySvlP66YsgI+Y9AiC/rg6m/jL+Xb7j7GdiE14tv3omHkPgrr7d
iAehAWhXN9TQOIyZLuFlENaawMHwoCVghfz9mytxqB1txhUH26IJbn3YvjbuatuNa+djlps9KMb8
37UbNB6rOdako5u/31kjO77bts8OFrEbas/rEW3ISWqx5Uv9QupGuK0MN7uWSO+Z1axFGRi/Rttr
/3ZY9U4rAJl5vC+F0ryAK2txb7ZsFeOc6HITSTNq1QzQrlleqXBMfRDthP2yifN724ZIYVpaA3bJ
wG+QZoUF0r0bNirQfAXKYkaCJcdd8UBMOthcNJ0vYQgCy0XUKg9RE9xBCw3JFK372PfT2wGkycvW
vFdn4486+o3t8wueZVuPiChMgrzgoZOFfWc+AdKTkML0HxJmiLfbGSOz1ehF7VaqawDfJWHp21MT
aSFna1B1Nq8hvj7pFUB/+tgxYrR+GeSFYo+QJUqE+CdL7Y9MhAGZgVxoAru3+7ma0UrGiP4XPrEV
FyxQ4rhGYJW08JOEte0wHwuRnNeE6ePb580i/XU1BbSPiI5TMdP3IME2UZzjqbKbyihhjeLqPFhY
IE1tR1vY2fnJltt9vgttNKpzZGKTgpu1YiMUv2ZsOhQAvpvKSzwXsta4FdqXAozmnwaDJl1TDZe1
XdBgw8ufZcwxlmqogbfi4kSL6v62zQz9YYi0wu3PZ/xdkjA5zxFL6bRD90AoJJkncdh6CUz/kdwz
LHV1ZbfYwLJrvrjvI+uAX5F9Z+NJiAUnztiIhqvLDBdJorL+KEngSxIR216VoBqWMyyzHZYB+oPG
cU6aNSzWGJOtTucbWAfOsPSkxaKCLJm6kbrhp7eCAE3AWe3AWTZNArJv+a9FeJRv+mYhgPaTLAz1
AA44atStiXdugB2M+Oq7wrYLnmkAcdaqR5/LsG/X8CYhIJLtN4pDAWnuwOURZZlEpIcRe76RstFl
hPHl2EeCwaAR5z4dNj1FFTqimS474PU51eSJJGW4tTMzncfi6KNCzJ4zjrPv2h9bWy7BeyuGuPYM
FpsN/OfJPrRt/nYmhNBeCJVFRuHwyBmotPUQMqGoY6+HS7Mm9NrEKKDM8vj8/fisZy2N2wtzNYtP
lR66meJEUPQypXw6WcGtBpJGJX6972hz1qAPOfskzaag6RWYPnZsQaXM0uXhI9aB4xsvO3C7k4Po
DqxRRn9cyO2yv6RkXl1B4W4ksm5vFBA0e8FbKSXoFIGv2es0O1R8eISc6j9y0xeKbgYjfwvZ+q2W
fTWSvHqqZ5Gi/vaFVhuW2jZoidPKZoFo0fXFH0oR1WurjSB/ohwuZRPqVrr6fua3ETs+4XesL+9v
nNnQ/xxJhhqTmhE89ORl/KoJHN40pzSWCBygxtT0U8SgmifqvwGLPil5Ie3CQektsZHbRP0qBr0l
w2SoLzBMRvjAR7D2ApIMKYIQqFMqokXTn7Hz3pkdec8muANipg9AawDtshyqDSv7gwMltvTQ3ckB
l5vk6xwKmGe/GJxwgxbV8iNTx2CyKtN1Sf34Bsejfm7Pvlka8RwCNzApbmRetVvQ5UwwOHBiQwpC
gA9aESSCzQndIMTJDnf6ZLSKk6K1QW0gbjroJ/Fns30okZLlgFJa21hvm/AEb1QENpHeckwA/vl+
niAXj+z/WL6XoqcfuYp1sqxmfY2woaBXIAra2CH8Il3mm7/c263C3JFrDbFMpuoqjfVOEJx5q7wO
SMRQ1dXkbGWtu3IsLI7Uuy2imLF0B2RYJpRVnPOcPEj2KusBqEnHDxScMqPjhwK1GH/pkN5uLmye
ytjTwgzlQdHiEOdLJNpAuQ+f++aj9MMAnOQo8Be47wuqSofpPN0D2JVIZ5kcnUy/wzlIwCPIpdLE
rh7OBRyoemqa1fewyb2E2h7T2UhghY7koEGkwSCgd6/3YHaznI3jw0blDkKALIxpwQY3cG6/5aqi
95A+2lJop+0fJK3MZuwxosBrFtcAK3zkooqpPS95sAox3VrPmf1axreeSbupYra+SgrSBtu2Ym5c
5gtMCBFs0oIVEU5R4ddKsaNIXFVEH0GHx/edYxzsNK6lCX0FL2UbdiRiUI0vz2fVi49x7VtNJOhz
gPrLZKHskkDD1U+IeSLV8HKF78sWegkSpxrnShQ7nZzvuU0jt30inbPuDOJFMGpEUm0hXMnWZErx
qR/PD0vzBbdXFRusJfw1r8IiwbjZHmBqSxSxY8klgMW5hPgED1ONBq6xRQN811CjiG3wy0vxZEPF
hSa/uslSFLkWd7f0Qe/qdy9MVmbhvCO3+Aw/F1UfYs2fWfa9cOk25IQ5kmAwMJmPQRrknhLiNFHm
Pf6ePKJDyx+V5hnCDr74i4kxBkyeU5QaH+LO8Rz28NcWKqhXE7y17LGAZ3aK84tZ4tLWmMwunRng
OJxBeDnHr2P42MGwwkg7DZWGqwbfra/sO8HhWLtBjwYppR/gn/uSfLL3WTB6wvKBfxqCMsMZT4fS
YFqr1An7hCufq5yQrbkiruWUsGmlPZ1MhNR2WG0xh7JyLPC+Q2jAoPB5w4HSXLGRG7ABMQ5oTsmr
Z1awra1wBarIZ1GLFquDE6qa9DYyIRaOQwhveE9TBNMW+DmfOtdnaIZfPMLSzhONYx0cQ5ZjsGWA
ip7v1fMYl+qI23JTB6pyBrDcHopIx9wQJtYtbXd8yY+vq//Js8OaqejB6pp9O8wqGkaGS8CCRaKB
wFGK5E8bumDaoFgG+snxJwuB96/vdkM52AdIqpyl+x7ueckSabtzqrK8V3H0sTheD5FW4HCUjZzV
93tVEN1xjM49/nGxS7EHHUxCZiD2ymtkt/30kSgcZn00DoO24gk4eRSzoZlb/IE2h/7O17gHkel6
3Rn6vhXEaR0SD1Vhn312NmzJYTbJPWW6i81vbzmqq/EbSXLSpZ1V9+NHMk+Qa3NL6TndlNsDsMFI
u6clbsgORp7dJFlCr4zB93zpSto/kFQBxvUsiqZPVXmeYvFXK/7r2hvw3i5igQvQ6LG6uo63IJvL
x88ux0qYRpsFt6BzVDqXq/eUipWoegPuMxrh157IgcX4TtVjXPvWhPBcr+Q50hXHi9V/CUXh86FN
twgszcr7eepc1R368HbCGOEv5zCrih/XxZiT1zM9YszungO+1RFWtXKj/MjxkzYJUXAwWgM9sSYc
nxYqJA5E4iXgnP6YjJibHe5pWXzkrQGAoBJi+Yq4cxzw52c5Qx31Lb6WbEUmbaNtW2uvmnrmFEnx
LNDoAVAywnH4Z00JEGFsOk0eUYgxdkC5f0HCWJ2RNBWQuPqf7DgVNZuBer62PI1CwggAl4YYAahq
jHfGnxuCaF0Lj86Z7xVEIGgqX9v/8TLA0SoLe6/32pDpI09HwKribLzhYjIAC9X1Z9JHCDLeAdgb
BwPNnXWwH14pBR7nzwRb/xSS5b4FSIYC7lVv8Fr1OhVCTjKGA0zWVZ+C439SHAsV5nhMJLdtNrrU
jHqM3OACSJnBJEB/NGVDVS9/psgRUQHJlsUsJjcl1jnAksIXCSa1pnhSlBmyYUgZChehXdvhLwh+
TAYWsFyg3ys1c2DL8XkR9AFPDuIUvxj8EufTFqHTf3fzEedmtcBaNySjyzvqCL4eqHhI1fSaDm2L
sXyHWcFR+tJ3JykpiusFLFfnc2v5vLI6WktNNk+6WH7+hUODSc5ZYmglGjW1lkXiEbYYBTgXchDg
hhNPqJ5PVydzKTg4Aa2zJ2YWVgH9jylYnq1JyfUAqEEMn5mJteed5U7jJw9Z5cWzfrT9I9xBewPq
Hbd1cnj2od0+I+mvKTJbB+E2mZpcF2phoh0s3jX7IDp5bqJR2z8uMaIzqKgw8cuBZ0UE0hQN/Q4x
k5OZ3E8vmdNkNfsC/EX+d3p7k3emmgC2i0IawO2qXxaQTujQLqfNT+d89tLmlBrNMYDJsrsj45NT
4fo6fykr/bhLeSY2sbp8YLHU9/Sr+6idWGXHX0ZFu0atPzAyWKZIgDHrwhVlGqFv4qyNSzNqnqXp
4SEULbfDnqa+s9deB4dExcl1rdFSGtWbNWhyYQLu+62465iYUWRmVZKGl+U/i+bZyEtq1hnBduJ4
gL6T+WiRwr1xQOaBdPLfAnZcWmzctpvoIDZO0yg4SdiHbzU93Bj2chWNsvr1PeGdDmqnxcqFaQX3
R3STv94ZCuEmmYN253OdliTJFTDrjp1cLLP9V5E0K76sS+1BQBlYqWb1eTEO+KZ8ty2J63OVOKWI
OVidNHSL87+LWCg8r1ModydCAcMucpr8PerXoM97FXBTl2JTnR7fS8MXY8oFlpZwdHph0lCA0XON
8OWOTRTVeg9f2X95EGREYBDr7KVJLC5//tTmmB8b8O7LbM+XnBkq8qPduDljyBqwutbxncq49Jb5
1PcF4EjH5RRa98D7aFAnKTO6NNv28qFgUBz78JnznK9XgwNk/XTagPA65AB/lGFoIbdbs4HaSwdB
HpJtvc7HY816mxVG76/9hWqAWjvSfpg60rAV1rtzwC+wpV1cUzrHa3ivoU67M2BthpqAzxcdgQMw
baHTVsc9841XRYlj039A1yqjj2b3tC7TGwF/UzRAx7SQ33WeGv4M8pwGE0A9T9PV4Tw7tCI9meod
CYlZ12kcoza+tWF3TJ95GXV6OLVpunnBD2+paALg3HkZERPoaMKmoXZiv4a5JEWftHBjCOyZv0DQ
1ZiLYrxwLSmvv5X3mAOh4AwXZ/fJBuOwO79R0z+caZjrrsDKzdK5E1VKXJyRG5rnXbDYKKAjH8uS
2auf21GmUFCjPM/3BDAqUTJEzG+CmSA5LB+QXNcOHkkwRI+JDkUfnh3mL/91x+bJjKPNA+MnRvv6
pnVH7nLbrxdfCnymfXGtLptZbEtwVWWmxmFalFlWoUBbthup6AgoQy/F8jffGJRT7IPW877KpaMf
KXpF8KGrv9nzope2CXwqeE0iTJmXFPReJTafEoD4Nx1WBB28VGQ4aSgdDzEAnKTL1Ac50dPggEZm
WdK4KB7WXwIEklZVSvnkbjIFwBGyj4AYQpYZw/XfzVSB0hBgmTYuq4PU4wjOibMi6EO/NMmVgxIS
kAAAT0YTvs7JYMdyaqIDerxE9BsnLA0nyPd5S5rIofF6QIr6IDhevQx/TZ6oNUuAO6KQRCa87FCc
EXYH/3UJIKnnQiDllEmDZiwLz9ICEtdQBElojUixpFkgh1UdP2geCD9hiNRblJEf8LqnXXvEQw1h
TWuD9iBT6KNXzXhAZNU1yvLsWcstzj2luU9Am1ulF7jTBNoRhzxc8OmyLs1aqxIR4Ivu5cAaEpXr
m4fAbEL20oSFD8jhO7lnFXAzWS1qx6P26bc1EuuV6RyRIZX16txsidHZx+eBqe6bESMuuapEQTY8
cCAl53pyQLubpHHf2EgHcuDb80aGZX+NgzB0n8RolKujTSE/yFLKfyJwSVCcg71WA6/h07m0vXIM
CjzZtSh0SeWykKjzR4kHrdfRyYD4NaZBR7IXJ+g3AqVogCtAPqYyKVjorMW2tehgdfxSjR3Lm2F5
7Lirt2EYiii2P0dbl7weT4GUV0IU3Rks9SHkRLW+RG67maDwrBizEndzbFt883hUWggUs9nUL7XN
is2QtG+xZC0SUh7RePPAGzXvJFoNp6PuBImLbk9HGlBspp9HF30EcccI8G0mbsLMuTzH3IAkX6Ze
JEXuCnr0ZpwwwVl0POVCct7Bq0PrZBrWIzFaHcOsG7N/AfjwDyN8rnFqfUXZs/9prQlUHXVNjs5A
itDz78G7/ouVPJ+AckO81SnC9gUqf2dGGBDf3liPI8paszv6q8LvftpoUYwysrjsy3KB5Lr7BMim
pdQ/27L3ExiLzesBD0sJwvhc3PsFcMZey/ZrQmAwu7oJE9dGgt3YGylvv5GNikQw2yET1+CUXGT2
EksmnMiqK86BoGgybFgnodusKR9Y2shhPo4sG6mdsuyid8KF1WTSttvrpG7MrB0ZLXeldfVJINt+
W2ipeXKmyp8P4RQrYFf7zMPny9FCym1bokuAqzErTeRQ4QtkfJ6QKmbke/RnBXrbk1w0p203ySS5
o8gKsE1sbAPICWzmTh7VAUhNS9MtFlHIrCNAtQ6GW+aCZSJ7rxH2VXl1Lm2Vf0m43E9unciiSZdX
KdMTGm7b+Lw3AMzVlLZBWbOFglacWrAtPzAfd4rHOpExMHScrKM1l8LlpvtbyopvtqcHdL/AuQGz
mZAv+9I7TvpSc8YNEi+FVI4taJWI3vZPA6nY6r7orrvKVMxQooWarxLgGDslQ1KSBess0/pGP/sM
M9S0LWiP8mHARvcYNNGW3umYg8WXuCwnIXmE6dGiJAiWaK8eyJxkkbXZ/36QLxW1uo42MhuL/FRQ
t8jFsT1Jx+cT6DpLjykXarQD5ZSYIDfuixCWWsu8GYE8OYiWI6zy8N8lfTA+cngBRv4bM5m0MnDa
mq3dWxhx1hHY3GTUvXidurUn0+RxQVA/b17nlUCoTYCJiLamVFzFG3ClZfOP/mYcUpkWpYlLybgy
v8IZXK3fFKFrYbF4ZtFkudv16Ex1FqJpllAHxcatVXJZQc8qNWhglwlYTdxtjf6BqK/a0Q4DiZ3t
xrK2pyrGzIvqz9yUJIFoVd++iqYRX1px42mYGLGIuKELJRY2gM8QEbPDOAA68vpWt94N2hVxcS3c
EXGzLAqHecUUDBJqKIOrsub5r/44TVo927zB/vLeAGy+YINxAtoW3U3CQnE8KR6duJpekPIKo0Lg
UBUFr3be9Sx93Od29oFizhcpLedIvOIBMSENSHu5zEThFyHps14QbauztRG//TghrYYEEccPt+s5
TVT19DFMIO3PUaSjxd1VblxpCd3ydt3LiWlJxTsI6pkv9StMnHnHPTy11RmCeHySZVI+5Zgx6lyx
S/57nL0dl+wkVjVJGo6v8FE9uWMsd4tdS3CQ6BQiLXbRb7uXMSMt5wxHSL0QDW36cpC9GvjOQygS
cMTaYYarTcGhdjxaUtwAvBWZYKpmN4oX6W/71nGpTbO+x8J6Ne4sPl3hSguIRHhY7Nw14a9fp2+l
reRA+a55pSky+f3aJX9bIIz4CcRRaYbdlHo2CWwshH1H5SwrIA4Yqu1VfZfRmt2zo3wnAodFgFoh
E4kqqmrOk0QsP6w2rG6SHdflfDdN+jQ6PgXiX+3Uw6/5Pt61X92PDPW06iUe7OSIUtceQrnqcfNU
O/jvv/RBWEcj6Sx34acylcIxE2W5caa5VAShR7h15RBV25QnhG8Vwss9DYz4oVfHazeIHhgQRQFV
ANLvtQk0tNy5EkDMI57GzE+PjCJprtPkQuCGYv8voEwvigbkOhhriOWrH3lfnXw8EB6YCloFOQsZ
/fl0mw+MR8S6O8+SkiA+Ap6eqzTmo36Wg0lbTyRvLSHM+X1UURmcbIiCJYMgXbhcdqlQsEAFTVWH
1sGVqHO79Lhx5Bj6MEY65a9UQBJJltttpojY3tH22JX3HBrcCCcSDJ3R2yOSgxNUdk4Ke8oAd7vl
wceMJiR3mqYcS1NE9NTJ/N7aFgPzGtoJcn2/y8t4hfVPRXMfW5wXOsZnia6gYFSu7n0eM1WTLyoz
7ibOBVQVoFp2FLsE9mjukRQzgaBfvy5frtIg0oD//wXS6gontpdROpYuX7X0cO7F7bp070/zhG9C
qxGnWvTQwO/5ix1GqHT/UcpdVnuqpwV6tKqvQYLW/bnmybRCo7wp2uImG4fcZNafzoeYwpSpQAQC
bSizI6SsGpda7QpnmmehqB9xO0XIYl9nVDTVyWYlfeWyYRWWUwS+idvNqb60Kj8TXV2BTIJm7GSi
8fdGh7e0gzzvxqdb/5khSgExzCGpyjgdvFdygU/CdJOeEjLk3pVij0FrofTimUb9HLkKqWc75pbE
DEPym03RgzS7WUdO+4CulmSlaxtwDssV9KIpRVYvI5j0GleESIo9E3GpegIyx7QTiBKbdeWJfHSe
u5evUcOmWEPN85lU4ZIqgEwO9065IYTAR0M6nSSXdWdRtb7GIW9/QsG1/hLIQu7qyhL5j9Z6EHas
F2EqOx220l/rHKulL+dH0CvzYM73SdkXe5dBNbyvvlma4xWvRM99vYXDbZ28yFXkGsiK9ez/uSg4
240TdrcvZTbNATw32RupdBH9jd5If+Y9hGbboVDu/4cRs0qm/iF9WV8xot/Apq3u09c2p5cR1JFf
WE27h5u7AjrKAdQt/OaL+mzvKS6wF02HD0BB820RcJQFmopedqZB13u0jEj8dFf6o7WGP3t/GhTn
p9b+UFYLbi48tjuFh62gVKYl5KbpQo5EDf7yceWyfsOKQcKMuAZcFGwFd4a0j0RfBkSetqEdjL4Z
KAG2PPHFFcDjQqo6mZikLJsSxbuOHD8HUsAVHB7O2d3C8O7NcKqp9F6Nk4jM+Slq08/Ng/kxJ93v
lWG708pEDjmb7+1NkztVY4/B6B1qToP/P82p84XNjG+0Nn+LwLC/i36TVlF9YEeOwyHg1xk/e11L
oGoQJI4LCvXjXftOT0ONaEjVrzJmdESSCSjLpaqQDk0JTCmr/+KiBduVnhbzR9onZugKW9UBmIH1
AdM9ieQLGGq3n9Ewy3ZmuFB2YF/jT0TFXhc/DKefjnxwkNjSg1gKXXrYMEx5Fd/BxwWhpdkjiMqc
BW8dbgKz35M9trf5eS5cXf5bqT9jGmarYjcSFgarr/Pk79l2KDAtLDMj1J6kQFtf8p5iQDE/+jAm
iPcoAE/bwZVdJk1k/3XOJyS6jB560WIQFGtuOPFcFqJQcvOtYBByBSFnNlsXPqdHkyfOwIehvetz
COkliEMhQkKJ0AdbOVMA4QLz0V1dqhhTE7rVWm9tm4qxUJO5b03qBb330djowoUNG5pkjsgCr0CA
Eczd0ZdZQQEtlwGFczWii22M0xnzAplcyrMwwiI9YirrZ3fGW8VhoLOqJjvgznX4LjfGecHUDyGP
CEuscdc2dCK/ucG0B/BAydrhMmRnHAZnFkLJds1VAlblwfDu4GIyldSgSrq/lCkfJKZay8vNeBB+
yRCxGoyF+yokiSAPGF3BV6uDi6syUneuvWEU6sUu+XX32QteDa8l1QmJBjJ5AsBs8/zyToKwiu1U
qaLKfgoAiqklPXNRJAZfV1cKon68HLFTcUgFf7Ih/SX2LQRjlmeQhQb5RQa7u/tetrpQ097g+5LQ
IP9QnrSX/heVIink5fZFXY1DyOk6c2SttANHyaQd1uwYmrfHF5ZOWd7OzzEk5+8OLjB3oFLfTOP2
rY0sjQZlcp/CyosyDgtNg9C+hawZXWC41jwFAlXPi2Y93Gi0iwx0rRW5N6ljLBz4lhy4hBCBHbqV
uuPwWpaNEpOBW8roeHjkQGUbnJ09CJrckZcmxXFcP0eWPDE8RaHVKuSbez364wT7319soZ4gHJ20
lwgxY+vR+fm2yOs5A8Q7l1OTbHi/EX8CVXMsbglZEb/bWOJuSnIMO4bUfztCPKEsChOgE+jepw+r
aqvjdkIp/TbasybA9F924xprLEE9R+wtpN8DgnIpc5IKgKciSONNsqkfgE+fTFhvPFj3f0R56+VN
R6TqdxN5KAVZNxEOkg1CCdmja7u1VpzyQ3vZthVRjv9QbDdw5FDY/Yu3/gY2+owXZiaXwdvZ4LdN
brWOG9/X8rN1jIxth3wHISGL2pzfbcLr9OxPquMnt71U9Er/qljNSmpLJQydebSiCuJrYJMXei3u
P0O1/f/mXbj5WEPXGWwgJAqRfayEduZqyuMaD/nez3hW3Ax5zKxJ+NLqMqkTx5tg76HybqYE4Wpy
sP9ZJTBjeWXRMXQjmEBCmwcYiWcL9+yPjX4GVJNDblcGbgqnEj+yXtvAT276VHRC7TytcbfD3Z+j
2YC1SkTRS9lT3p4heMiuLHcT8N6uJOw5RNwpNZgJU5vayUJhWM4xadmSCxvla1QPd7Jzcn3PF+a4
5Nb4YTSbIG1JjSNpCOE8K4/U7IYkmFMwp7Nl2/42ZgMUT/mLRFkCtkSqWjg+3AmIRwwWO4j06x70
+2Q79csXDIkk6axpNm7WlEIxEdVhJFyD20XjvFqgaJDbTtUDRVC0GCpMAd2mtqIZ/JeB8L/SFTSr
KU6zYdHxKR/cYWKFS85P6WKvTfvO8ExbNqL6PE82KBUT1h3TMRQo4ZJvUiVa9OibfMwK2bm7XNKY
R3tSvdlKtbx2ekDspd+PgbQbwOX5ACeoiWv8NNvc70AGlYjw0ApP1rvd/BnzRuOVYZPjxpp0+j18
oMOlUw0X8VVXpbvKZQwEpcmTVQhDxwUZnumxkj5lGZhdKKJN4wtIysFE5KN2EqqnB4tMh8Xaqo3t
QzuEPxxHld4EG3/SXALtsJYtAijmF2hR75K1qgSvj/8MdQa2qcwEQG+EG64wjUyzRocKCLALfdbS
RUli2RFTrnqAOMuTXN9CHTB/sk2x8NXQJ9m3Y5TJWoCmGulJHdzIWU8txfR64CBEw3tvQn6YfiA1
JdoygfAd1gfwTV5pGHC0TO2O3bCu+TR8YE7UpLrnCWWXv+oLDUDDaFnjiFf3NC6K9008kM4lPJ2D
smyMhIyWsvj3Gecl95l/vzI7ddIE7yCtKSzNO0FMCm+t7zzkIBVMxZLp7WY0KY3AxeMXbP3j60AC
9BN+BjLC6M0KL9LPUgcu6v1KrOzdd0Uu8kzukik464x5RcePTLE6FDJhMplMVwAM2ITBtEYG4Ia9
iGGdjl8GYK1bSiWZbpYCA9YpJ1AFsgDw5d/ZUrJLnseJ3glTRfhlxdXF/PVUDvYSf5TAgqAh8l3r
0Ggm6kxIzFJL+GdVoUdKu2Zp2BIGdfbd2oYaem1z0Z9KRPjTznHorm/HBVwYnIRPVg2KBuUu3Ih+
vofqMeMQJ5unhX8YZcFsSkQPX0aWA6EnRDTGZHMyE6F4jToPM9jhbCNVyqVesA3l8XN7PSecrDaI
pfUjrShVlGKYISdvbo541MILJcJahrt0M/NUdfKYe5r6fGg292MTCC4kfejSM0XBDp9UkbCfkV6y
wPI8SiXeD98pugVY4GcF+FFzx3/5Ri1+B+laxBwdbrqfuCjU3bmnU3upsP9K+AKz8Woldv7p1CJ/
obXiP+KoydseUhU27d40OT2/hqS0xkRYuZ3lvUuP09TQYcthmvPhRBL0491CJ2FYfx/ogdkjZW48
DiwQS2FBijBYIRakE+z6samMhRLDenxMuTUTsbBbVxP8de5Gn9CTSR9FeL6erwOpTsM6EdzB5FLz
9RCPiPG3iaYEKwxp8PYCA0oHesjiRI+ilkpe4tESU4e3qZmyoewXEllnr1uNHZB7TLyCGfrBznbj
+fKC47uqqTZlQ34KMeqCn38YFjVHi9IM2qCD0XFOhyBgLaSGHZcecFvaKjB9qJ7ORXa6kfW1LWKT
jSx3i4qKsKnUd7PjaEdE4FklbDsFEbVpehR+M3e9nR4BBtSZ6NOHb+EmnUinxDF0V97CT1NjBhom
eWvdGlaThrAgJyWNLQEyktmcz+6dvtOLMhAX04pWjE4k1F1XhHzm1yXJ7Wmm2xbn2OwfpcE4RL5k
NTUFDBX78/uB9wjGFs+n2RRvY63DPj9tOywlXkgQso3KOPyLqszLs15JWE2nyccwDmnuA2yKvCVY
60qtXPiY83r9NlA8/0i9AHwbiGxRaMf+HcHXpSDLUC4CdeHjXorLvxPzKI2+B53CqdAKakmuXWYd
76NiJnxygCFKnRAjYLjII7F4QldQRsaFHjmg6PB3lpvP9px8u+5bPjNjLMCow0dBlzLgWtSd+aDE
qMAotNO1/OlBegH+6aAkjzKH8FCFhazlONoLrIiVsoR/9zRWT18VolSr1485+3s2EQirfKwRsLab
7pJ8asXKQy4xEVhlNJr/ybKVYVt6gKh86XxCrG9ap2rTXyZIh0HtKduF15xVc1DWNprctKNstJJB
R4UB0/Y/hzU7y+eCAhWhJ4SlaxeOl67MkDAwc/GVZ1kFCXSCRUdJRQJGbcq3yNwd+RuFglrcS194
kbfFMj8Z1eqQon3293ge18r4nEVHpnVOJ0l7LzNm5zQiERFsvmA5LSq5OjkgBkww3LvNtnVdiAjv
+mKRUhLt07gXYh6ursVfXDMM0bS3EmjWPwu8waL5TsiSP3SAsVAI/qhGQ4IDnHP0obA9iotWEiTG
4BOHji1Pj4BSKkjfC9jCcEjfF8ZSocf37fw7VMKhJtKstDsQTa1k6bbJGSP3g18rzm2TXlHWaVVB
hUDGjUJ94xXaZ5WHQsGntPRHZcAKZVoeHmJd7H6UdU0zJDGW7oxbVVqEHdAY6AwCdm1S+MVcXveH
dvnet0eMMX3r7a98nsq1g1VDvGRVXwy8eWDUA5AdKSoi1BsKS4bAqejIDvG8Q7g9hEQgLSqnlC45
gVB9bmweS7yRG8uuVCiw/+2GSAoNgxjRzXKVIV2WllTFrh9x7PzumbjkeDMo80qK9lJSeHDMJJad
JFNvn6WwhwKoLcEjvyY7idGm4MpjNQ0aineVIv5rzTiSCysMeox4ExJ8sk6+uAiSTaFjEH6LzL3P
YmS20B/zCE7U5KFA+QJtTztQPO2t5yWnHe76UDM5Sk/ydlZbma6LjPC5BVpuleZxb7RCbfgJWxcQ
0FHiwH24EOjPku4d7VSDhyBO+892ycbrbLWr28JPV+oI+Z2ETlZxSOWaVkgke1n7j/n8ZKdN2IuA
x6PqlAnbgeHU/2lXuWvcVPg/8rCTSB9W0tkr3H7k9B5JdV56JSN+xE4Ovabg+yHOyRV6FT3DwY9S
iGY4abVTA+J23xMtIpfJVwbjh4HdWvXMrdYU/09mn5StswUTRlOsuU4sbMLwzK3V1xmnXJnytodk
cF0adUhTJfJtZIYdMJwMhPHDd2PKV+cdtqSpqjtYX0HQxtDqGD1HLyOcHaH0Zvm3PhKd+rpizpYx
+sJHOuZVLSb7X4ZEdIMU9Bszhnac/MAWVb3wOtWuzbnMVMG85q4u4wVsq/6v++hNwvE/1lDibC9N
InCVfRCXZ5RsellRaIbtQ7coQwb5Nz0Jkq6PSX4Jfn1/Rerbi66J+7xhHXAVOwc7Lhmq+APWrxGA
y32KJNgJ3UXId6UC7zghmWLh2MWYXGlNiGTOR+10uLL3Dk2m9d0alOPX44iy7Aykz+P6jh8Ht8v6
SOiQ5kcLEhvQVOCu7S/iS0buBKNrDuN6A4WnMs54kBj30nT3os9HKVaMDLv+sF/CvhO47KTcacgZ
xDjNO89wuAHDhcLZFfuSySjysG4GexNIFPZnfsbBIu02oKGATilciC8VskdY+90EgKgQNKlGwWZC
whym7tPdqGEWWTEBrl4WVejYtQS6CVmStEM1LWQQ3OPbWkl4FZnD81lMJjIHKvMiv6Cm3xRg4ij9
XSb61SW8A6BMzEljcqRakpOaZlfVJNhbAHIFszo7Jhk1u2AU5jJTjsuJGYm8uSyqTGSaB+0Hfczw
ruouKkN+DN0uurAOYyk2lzB+HU8KSxtLTjcwese2r7UMf9OWzQwfRPFFhkOxoTvzRfnm+NWtLgwx
8qIbDiXaoVbCLgkn4+u/Yt4P2LpUPd6cK+0CE9fO5Xjfu8pK6A8doKcidoVQW5FC7gwMhKFrjxfy
esI0gcTZzNSLwU7dixD+moDirUlS9/Jv5KGTbwJt1kiPqMyaYfHMz6ZeNLXsYRvCLYGBp8s1NHKb
gygFhIgzMNvEioCSjnebUEqXO44vsJVEQiE24WIAFlTuDQfHpIpGGC25CKIDtCVPYRpL3KTkfZ/L
GT0qf6LTTBmnPEP9lOOW6YuBPff9GNVsxoHdnin2ro4YHmLmEvrbROhe1YZ0tBin2barAtw4GaoX
wY1lODcDU6Nnal9FEKbkVpoRB7pekxN4Y4AnBX8s7MMBQJSx5RKQ6SREra3VbBBWdog0nI3oIPCI
ZcfTVGlioivvwqfKVQLTNKFFveMlCvRvvUP+85ZFL8ZCGbKTNtqrgaF/BBVWTelqO+FjxYLEqIV1
AWRcU/y2EqbKyFwLn9k7pxjJSU4exTgSj/vt2b02c53gJ6Wg08XvriZhT2+0LIoWUh8cuE04ug/7
Wv6Lj89/mniMXogaWr5fsvLb36j6bmTw1p5v+C8jIqyjTLA1wgG1b3z+Iz/f8Pvk4L3w237Dgnde
FjpkX3JS/XH/oynJzL6UTcj9KYMU6Wh7Jk+xR9/7EJY889+86ZMZJHK3Ks9EnpeWYEWPmAY09tai
8fWdkV7NmGIwokZ9ixnpldLFVSxY1yDXJsHEMqhK8dHdB/ORelKqKk3HBicEjE6YMkbCL47LSDBL
iU6rUGVIfU33/B31VbdKtdJDHsPTrE37x+jGbw6obMcqLtI1ZcOf//IcwDkgie+JouM+EnkZDOlw
b1K2GoH34JLj5w2wvUlfsqRGzg8CwqVpyaOXYqx0BB8tNQ9+x30VQugc3J7mpzdhxugbMhqALwid
YXRAWvwaGsLlYh6c9qX/owDiyH4p4AWZzmHJ4CIh1HilFruwTZhN+ubPCT7frVpMMK7Cr6qA+xl1
Zq/5a2D8deIQJmchpRC5O1kQMZc3vAVkqpqZbh24JtrxCRufOJ/7yAYbAuBxTM4ZRpdAIIn13aBH
4rsQrcMLYRLp2et8+JeJ6DUZLohxHXToH/YVRyt566SNE4XHqQzfhFh7fax1CSkyRr3+jzb2O6ke
U6zrvoa5facURKDmMCFLb91XPYWxt6L+JRv2K0CjwPUkSQ3b7jpSt8LzbNwHvoeY3TyFI+l4Xe09
uT6QI/6OyRYCbBX+B/zy83ojxbdG/7zjchOs7kQiE/yb6Q0qb8goWpjlDMUbAwm964RBwgzDLRFJ
8rF64xqKmvpJO4J37ZKfT45NUUztLigbc/x+/EINj0e5RDhkoXRkeugqYtsonMW0HcNoRYcM3pyu
/1JPW4uB3FNULnW8I7tDvNT0xVXT+wGu6t0RbRF1PDS0SOP3cO7205+Gh1vDsrrtWnZRl8zGHaTt
u+tfiqLtDdQku/gs/POs/QYInFpBgtbjzxqHeHew5Eaf3NrYRSGE2sFD0qT0pHwHDq4o4OUpJZTQ
LIBdnv92Co/iNBrSdliIL9dcQh0RY1QOTTiGuY50wo3XXhELhmzvjjSD5mkbfAyfr06OWyjtx11I
24/qUOW8y8u6VSJcVH1Tf8fJTwRsostLrjBsjASD1PKo9pu4XQiold0vHbQ5kxNmyj0dGQg/loG+
X1qnZs8+BfH/t4J/foY7ahnbKuk+RH9vufZusbh9uGecXQ1yAhE5gdB5Q7TY23tc+WDiGLeaAv84
I5DGTQQ1aDooxt1iiqiAZN/Qt/ltHad1a5u4Gx8oF25xa/V7/Ywtc/Mi/tKG9I+ZkIdu+zjkdFwV
QpVY/t4jrzbcdKDY8qWoBIACdUMi2uecUKdjfGTZi5asVjZKdP3pmWGabCaMDeXwlGHxV+eoCycO
u+FAKTB/ON995ap1QWeI/5uWyyyUO5HNtyp/1ZJFjZAOPM3E1CcUOAVain+5iPU0+UAty0yCs0dX
8vq/SxDlxndeAchvF5sJE6z2/MTg7jQ2VRWcY6GJSvYj8hOX+WA2+AIYq0o0/MjjhZQpj44L0RtL
Jdhxyx7YNngYfH3GtKkNQUqK1jJyy0qjoPU57FACimReRZZdqZ9dqVx2L6RgaS+xeK2eyP8BSGsN
MJ+fWekTBxXzbSNRL37rFhmaWKi/HVYKBrNBAKI/9rhVO7wBHFqFuKUpQxEdwnrnZK6+B4zubOTv
ZAoHKc1sRsAef3C3W8M4f0XZefhdt7hpcsW61TNRx/hMDy8AvZ6BLjX49ZVBQsHF++FG/sS3g4av
YQv3govY+Yc/NkjgRwThwtayyBge9jhnwHQnEINONcMIwUEPJl+cSdQtlT+tEUKouC7/6M79+10q
J2sL8qYly9O3eds+eviOmVygD07xZOLi8rWNcQpeG1aipe9GKGAkaUpyO3bOCS1BXzdmwv2vZ50E
rhH9wt4Uo8a4UmTxwLKFtTAYX4cANBdJGYmmI5Mtc1jFDKsgi7kY9sbzx9Dz0SEVpEGyYXjykPEQ
l4V78DOkRVaF/ZSQQuY4PXIUq3YhKq3YWBKYm56EYG5Cf5I0HloMHazB62FNKZZb6QhuC5n/z2G2
nLSOg63XdsFWzM7qaDGJ6XqEXgSfibKuMX72Vjt8VA2FQSRd49LsUNFt+rHVENAHkwSOjC6pmpQO
Aqt6BTJ07UfOTcWnAwDVq3rYJtVmNQMjmpjgHIcltMJ9Ff3ihFQPoGq10jW8iCJzIXXTLx8EQHL8
Dn8PaBZ9oquR/Z1a39jmtzkqPvTxS3XD3/nhvxw9Hxw+4WLwB8U+HQYJN6vdXwzJiKdp94BXktBI
f2xyXu8pT2Oy3x8OqG4EmCxtpgAt63p3S7XPpBpS9RCoAK0GJYibAOALNDWTNxTmDH/wiiHKSOcR
HBfbEIk5xAiUW89U+uIHWHJdeQVC09bkRzPs+6GesadsO2WcQCmnD1TfyGcdawPeAFb+/HUVAejZ
maL9qCdsARDn86oNEX078nLerC5HZEFoACMatIGUvsuWX4Aym+4Tf/l3THFop1yu+Pb+d0qDMxej
8/wkwyNM665v1cgFNeA2qgP/zxnsXKOIO/dzadyWq7mNID0nxAZIhGmQnBzYX25QguTBFEsGtY87
W5LBNq8ZiDzk3DhMUtsGtgv7lkSv6jz7JG/aG/Aulrv1OaG1G1o8SrlC0dU4sJnkwh/2a8Hu96LJ
93MdYGz0DaY0io4i8bjGF/W5ZQ/YGRZJTcv5zk+yw8465b/wy09H6BDD1jN8G88YHYY2zvJpnVZV
vZY/m3y3tgTGTrY5rD/TGp2dy92QOYHmFrPFJ/3Y5NbDoPthXtAtChFMW0uZ7fMvKWd4YFd1udvE
NUiy1Ss2yugY1IRI2fpD47blbS9CLb13ukBEmXlIjkpkZYnL9JMGaORK7xOv5BPVmHhX5SvvM66y
2gsLck1XAn/baniaddKRtmfwCY487owXwO7dmjpHc7FOvH8dXZDKcQYocQMDvTDj20Y9JVzOCfOJ
mnu2gYYZi98MAOvR07WQ3B8Q6DXegrPrG7P60h2RUao7bRdoJlXebbrPqFdxZyLycOaiI7yj7w9o
FF5RNALjl93Y5IdpkUXhEwTTHnwH4F2bLBFqntV5XKK1tIH1dhUzSgHn1Au59kb99TbOG9vU4bIz
r9rBOkwce3BaGtsRjLqNv07o6WqHVUSybszrnGIIkO1mD39geWpWtFq50YOrawI5Y5fIXxUKpUlj
z5Ciq0ckUiGLUZb2oHm7pSA6X3mvg2q9+3zszVzWwmYf71sU1ZJDIkJs9TJS/P++KEhO4qvck8kv
qzBXNg9YtpM8GHzNI1w20H1vHs3zVbWIAHwX9DhGAMzhhoxF97NfTrBUIloJz/ceH4mGfQO9xaAO
nWpefET8zj2NNyTvzXyMdumVY4Jva/vSUYxbyiZCb+R/RElclq+ssDHt+QRYMUNro0zb1xvZUQDx
6RxmUmwPnM3CU9mAT8CtNiZDHC6FEmfsNZZXym3EkUdZKk3aXEMoYy8wL3w9YlwkH7DurxKRMNaY
eXU/e7dyTFR3zJTE+M7NxjStfZYQRW4cuu4EYeVomcCCtVW+ZHjbBX1TA60nNAcbPq68ffIcB64J
bnY8V0HOSIyXgNfbQ6TN05cFSGEp1rW1TwEL4QOsVwQuoMR3CZz/s2wnB6eMvCrNH/3Ot37ZZi/K
b5Rzv614M+4oBmlgydo1mf6xX+sT6JdQ5luLh9sO0Y5kbIJYANkNbHlJwmGWnilqiJNIY0WiW9xG
aPQSTP02OWWHtgA9d18ATK1/JRSTzvR+B9pZ4VI1CZws93Ob173xhw/qRNN/JzT9X3I+4uLlRKIY
UnPBD9chUiSYcpveN3ZNaxkNauuHYTuCiRoWddykieaCkSm8lyP2r/7dKxMxX6DcGFHbVHpxTwwv
jGkZQ9A9+mxhVA0ZMwB9wcL3u6S6R+B6RfAOCln6nyKUgIX6pTgyIE3dUuXYk2gzCx6WNcAVCi7e
24Wf1mFM2ORkei2KEZv5yrllO2tPSJD1Pbc2tdp2hySuMHA669pTiYuD7V6HCYaQrubgg3smRNxn
U60B9LZX8XCJHtum7QeGVw5ULZLnLBtJdxP++GI+IxWaLUQNd0QBwt85jtLyAv+4EfwTHyi15y7M
AgQsejF/ebD0jCvfCqvgI9kt2Fm2xrDRfD3Q4hB8AJptLnrLz0TbGC7cMMdSJZkMBWHAr0cDGXS9
/V0tbhOJL3+xAk5q2qx6dQDafl1hwhR98giirom5v6dxA/2ycQB++X+hu7OxxFxMnyXv8KZlCnuc
hStRzBCS/mE+uQj8G8Ns04247AFGBrizXPvGpqfzognslRaBi0rpTLOEYRdAuI9+TadYjPAJG+wE
Zp9cLMepjx93MUA/ovZ01WiPEjt+ELgIFmp+cXj07FDspGH5Bn0QsW6ZQe7OkMXUSWOPc+WWW8KF
v/HQs+p8y7ak9aszalCqJKjoKSpmTKBCPCz/Mi/I2ITpPdwDE2har+cWexlpi0fSwT5MpG9FOt0o
y2oUU6GjoCMD5Y9GwM5dn8wVSEs4NqIAmWwBvCEuxRJX9qwjGzud5BZSPRTsmWqw4xGkmJ4jjGbk
J82OHl2PYniUIIgT2G0vpvqHFPNIi0VYIgDWQ+Yiz3Ejoq8qh9liL2+INH41vqkHR7kyDViy7njg
6Q7P92TJ00yQgivTAbXQ3n2CsRtt1A149DKBuRn8TyvOPMY3a/PLZc2VqBqL3/f3sowNCECkppAy
fEHEBa110mexo0VJDZOp5/CjRkjUNrLqxSqwBPJaeS3z5UxD8xlCd+HBkNbriuL7zvegfjJj9CvI
tdjjcqwcge3gZq0FasUYfUSV3ljwG91Jg90xUI0TbnnB92OyakE2CYQfx/FLrVW5XaDa2hDgy2tF
itaU5HdRhH3Erv4QUAqhsDKU4xHbP8PZHdmIQJKRKzdzU9ooR+ZBeSFoY2diaH+3kPOIT6mIQUIo
EhBtT77qfy+EsdXVG7qmkKrLx1AS0ALZS0Y25bj/VO9R0v4ReAUhPNkKNE6Py8HGqmj2gNxQpKNy
GtUoMn3DDSQ1hRyUFVvXThxbTotvROLImuTo6GQFGFT97v5QhllYop7UKVO3Uc7fZE81wD4B04Pj
IXU/gT6T+TrmsnbEZeixM5a1prBnqr9drf55Py8FjvgRnvD983yXOiLajeknsQG9leytLJ3qyrBH
g0S1D4exF+NroQVw6xDtu+stlcmR8sb9u2yH23gSNpmvExblt7Qg1BZI4Zfuuk+cNCDMWsm+fof8
fjmH6qgj7jx6pZjiJRXymL0FccvOpl4T0zJekkkBEdm2SCFCrOyThzkR6hNftuf/ZR54rIHrOdEv
ogyuoNIvkGSTYx0LSVu3OK5hRtg2zbYT+USLud2HZkXafg1LUe1ExCSFsYgPBbNRiAh6MkrXcq7o
5XYwa+8FERB83sGqe9aaFrNcDKOgMIxjjia0IYcD9kZfXBhqpOEmMJ98cjXu/crWthKNbZpAKE4n
fQLJGCCUJ3j2WYJSHeBy7C9ukOUpQgLeyLtKlsGnYVRom3AC2oAL1F2RI3XkXbQmokQSray0NFin
pzlbESjeoN1UU+MekUIAPRvuXXVuBPs6LLG+2Aej+HFk4O23zzHUJiOulBXl4sT1g+s3FFCwXew+
MB0XitxvVg58CkPDhSCZc7rJgaEMhrjFw0H7kTUMN3duyior00l/PMAOylEjq3PLY+aAXXYCZ2zc
fVSBtRveqRKESx8K5B9Z3n90QCK2JJjQ/Ak6vy9zYI4qePAapuVSpQL6gLHxe51Mmk2Z8ZnKFH1/
v/X4PmZrJiRTv3hOH6nULy6qqr8GCgHm9TSICjTehxNxlStUIcLz4pUcJ7HQavj0SSra7HYr/Wrp
vS8momG5IiMIQdpR9NjSfSMNxkCd6L4AOfrXi6sqGm39a/0sZ/nr19FDdBTRLhEhaxGscU/tyBZU
74YJYCFYoK0PWQ1imCy9YxOP9jYkBKTvMMzyqUdhGwnHDOfWByF7ZH1fFqDiTzfiHoW7twjvPyv+
Hmxow41SApv+29MmAZ//c7rqMzOZtWy3/Pt09UUQOQioO7TI8mc9va394q2/hct0LAA8jYgXgXPD
R/09ViJQORgk5/c9iosCM1JfNwUnSrNXX50ADWVwD6VNwE2X5TwrerjZ8duzxNHdpuJ9+GJRshyz
Y1ok4Vpw3p/H762d75ryDmWQziHnuPYSjzT1jLXJq5bln7R7i2THgqrBZZLsq8alPq1NPHHDZ6pv
HjLbRvwcSctdQBPw7iE2CWg03rzT5GE37ArIirdb/2fLGcstYlLeIQkK3e+S7mnADHWD304i5Klf
9Va+EXPnO584IFRmJWBEbOYmgVgUQ8TEO7edXtFLhze8hs4IrFRqj/eZeTyRjTP7vQ3fOYKroNih
MsHDd5UUVFnARszeodtPHY2kqaxJ59bwVO8h6x7JFCwDE2E5xf7jEr9ierMXybpnCpI4TcQXzL5m
IA3ba5+Fm5Xd5iLqhMiQdZWXcz5/tFXX3m45JG6J3H3fqO4hM3V6eV5xae6QbWtoSgN2MQ5gQ/3r
AOer0Y6dFumXiSR/A3gpJ1kN0xDIa8jVOtnObWzWAwr/x/IYPsz0sqscmykzyAwDoSV9KN7hXNuN
vLjR0KtP7zrZym/uqqJFeJ1rf5e437wc7Kml4JCl4Ld3ecNOr8rm2nrXQaRWax8x/Tr7WgJ0XOvZ
+weeYtx/Pwvzu652KqtFM0xm+8yTPelvGdw1vEQ48zWOWam+uq5nBCJjP0VURxSfGM/2V+HBmDVx
KC2lDtTHe440CAN/s1/MAMArRBcQvYYC1py4qTB/R1ETvq+aqQCVV6P9WvWjB+F7GJj1+/zvaszj
qjK54oohnKm95IFFYaaDfIwx4otQ7OyT31qYukL1B50HafwnJ1jnuCBpd25aMWBdYgLX9CKngXJA
dFm1hw14t/h/Ib5ZRprMtXTUhg86Jimh3axXqCW9gAUd8hwdmKc+yBW72f7TL6VJm5zA05wr5moe
Qt97DIQ3GjbeY/QmPhculY9mlaeaiG/jAiAd7v1Q7cFLXSsqNfVurx/ayv2yJigbYgfMra5Cy/Fm
mp++lMjFu7BqbMvgMegAh5+Va7X8qbsZuM7dwNscdD1V7qMHk50HegU3bX7ctGiWpbZktTJkadhi
5Ucd4Pk87kuGpU6yn12Wc9C+w4tGRt4sOjdFaDMSN59X0j9uz47uNkYwhZ9peT16XOoknxldNg9z
6wH4SlzlJAfyyQTOxXan7VSM4QzIbZvwVULGtNvZcFyqKEjzHs0FBz/iUJ/EyltToqN/iG0cl08e
ejLLas5f4bhtpxcDdgf/IHwnAExnOkpv6a1DCcB6NfkssQruGBUeRy34LlmDQo3gtiqm+wfj/+3m
33OVsYwR8lC9hIGZGjSSYm59PIBPzvxi1b8hCWenHZxKt+owzA4cVATz2I18gfnRHOcOI7cnazUP
zDoYLePB8HXyx513J7UmG+OQSubWSwN5YHv32JSJ/BAAq1ygt8EmOdFu0QfXvlsDGSmLRQC8Romq
DjEDbqAwebEdu09HMLNzeObxeWzC7CGepadlnk+6XRqXWmYUk9YXgACThiYxpmkhYQelN7OciFo5
NVReW640+8RSoJj8JucJ5Ae1HONRRGdUXDQmz3U4SJWo7MkaqbweX2iIoTk3UXkW6dubxvMKiIFf
w6mb4mnGKawbmvIXv60cJSZEAlVegf6hgkUnu3QE4X1gPouY8uuaJtpiKLcNGfFLIGipcXsTbIuJ
n4NoXVhsrQmN0j4j7Napo2Az7eJNV0O8Et0YQIkSbkRbEtY2Y0u2/ia6swyQlx8HawbhwWzY3Pew
I3+qOpuTlnveeDhiXtEIu8Cme6J5kngIVPfV9zXGiUQI64neVToOKp6UwYbIDoSn/9DRQNJSVfPX
Uk/J0ummrbtGcKg8Xcv+O4RAiMWC8WqMEg8g0oBsY9ZshgIAXERza20bU0xPKzlGJKr6iWxpFY0r
5yXjh003vlFyjpb1KILk7BVi3Umd4yh2yJ9Cq96JyNFafuwKZk4VgdpCZYhhOdZi21PYuyNl49gR
fDsTHqQmuHlbSKLQbxkXJBwa7DQfqaSp1cJCOjB76ioGnheA+ysCB9oZDtFkpl3NpP7reUusQ0jQ
lm/Mu0YtqdCrMeLz4dhwbMtd3UTrO3IQERNLxEJvUjwQoaZmg+FV9QRKmYUGTL0kgXuHcC7QEEUD
dHKeX8rTykYbkAEWwuvxeNB+aahxkCyOcVGf2bdKN4LDrG9jsfKD+tJ6sQMYTjhOfVT8KG6H1J5W
GVId8wEVtyEHBW0zxf6VNhmev30UYEaqxB7cZKGSDjLnCXdlcLFzNYCFhvBz1BPoyyB40vsCpm1A
p+HfNoh0AguX+iJAQbyLcTadBvMrQnSBRbs2KJ6QD70EIakRldsL22X/WQ36PAhIUuTAuZ3JbtoX
6Itrkr7bD0s1Th5evL3nH+QrCkfX1BlG069U37osX161AVdcqIhpfIVKw1ssyEFXtVz/17Jw+4QT
v4Wk+hJNVojpnmt0Z+ftlbL1smyiEa4EnLeMX+7ycDdO+Va0MwBleyRjwZWe6wAdObDyIc/I+Pnn
H7tCH2Psji7rumhvsAbeLxM2XGC51OZ1yVJlH15kNxyUWiGOyeV6zUcNO+CeyxGh5y/DEJCjLb7+
oeoop3EEAUKLeMqvOIfOWx86q13CdJDIqTfShVWSMIj/gugifVX4VcC9wDKbPrxA/8+uY4qbansn
IpaBmNIc7iEFG8hjQEOYIUJsQ8+B9VbMUW7NtUZOi26S6nLjDXRmyJ3PjJLFb6TSGlETJO+ZTBsy
6ZYQAuBmiW0gnTt7U1ltAeadbWam/M0Aa98TsoBaXz4HMsEJtk+hSGQgQqctMTy3Z4WI7kWzhkkp
RhuIG7VWvcsQzKMdIm5WwFoyBCjpAYS7oWF9EijB7eOrUQw8lwJHOXKT+2eGXQ0/i+ZNlpq0Eh4Z
04VIIokizp7/ToYvGCNQg7R8ZGDG4q+zhTKt4T8DFRKcUHc2fu1K5/oBtb3iMuZt4F87jNLX8d02
Ge/kdfR1bTLwy7SDVIBhpjydPcRt6b7ncW2gTMiQ08r2JpJSnscoXIL9La895v0dU2nBTlAifgpB
y5iaMSUONl4d9+cGFKHrp/+qJdr5A1o1XxyoRTqlhPqJ8n9P6ewlk0/kJGCHlaiYYZN6IsL9kPaU
l874LrbvUWqJ8Pen4wmB5y8yBN2yxvHiT6fVNEW3zuMXY7QEIrhV2bNNVJSicekRhhEVrpjGPq8Q
9vK53yHxuRwz5tBnSmhVOsk5OUi9ipy85UXGdGdEsG7CIYjTTZRjKl44Oky/d2hrvsxSTGM/RDfN
k6RjRS6oJy1bXCsfDc0yhuiGwZkP8pz2Yq8k0d13p084au3GPcF+txCsXFGYATma/Ci5nkkng0ZX
ACrKW1JhKXVAwwnw94RKzaaT3X/UiyLpQZ+i+srzisUpTLea91XQuUtCF9sDMBFA0RWNnzF/saCV
qqXkKVaWgH+m/gvODlykQsYG6+C19o+kCPjLnXhGtAt8DzvGAkRv8eW/UnIij/WBM+uuZRQIk9mU
huKqB0KRZcFQDPx1dNn6IfOovse/oJLMsxu/YtJXQM1culThs+AaY740xIzol8GcCEKkg/Z1cEPf
kdarDfAhQMk0UTA8yhsCerlIR0KabMP+RchaIyWYe3ybv7TyYkwCRTGZHEtK7RrZL8tLkndyfDa4
C/lQZhWbOd3q4iE8hZqWEEq8HZiWT9rC7z63mSRD8gPE9RQ3dd/BsZz9yNqwKwb4UVBgmc+4E1/C
F7OMPE2JX6XGEoRrxStFjfsi5laA+w9+++6AKq5+Wl+BgbPkAClF5powvQ3KaUNt7GzGv8Up/pT1
5rzy+C32Xs19xCs8JBmcBYorrvyww2+kN5YowvCyvgJpqrbnyOHlOCCX+DM7CsNWIENsEf9vF56J
Jwxu4O+Y1bcKoatW9SV6xPBgg07k5ruYus0dxBbDC47tVDAWu4qS4oCRvSiXxvEZmW7tM/wxi4iY
20PVHLjUVdtr78BkDpBeIr3sEKwb+qF5RiejFhUoAz8Cw57tXiSeebLcXapBHJZDdYUL1oTy1yVg
NQJLuBYYIqbhkRfB4BYqAo1aaL/xoOQteFyI4iCe8OI8ZN0wF2icWKwBIZ93zlk3VOdYaD5J4WJf
cJVMAiLIws1N+5cFzEXpyKoAKIawQ+suy9ylBPbwb1bIGsl1W0x/afsfSo0b0WX88NM//Iw6fRAG
MhYJxOmwi/7uSQWfaiRX90F0azSLErlYpxtik8olJlLPaTwFRnpR4Ify8k+PGwiz/q0HWq28Nj6d
hg6I36Kjtz7o9BESYip+3wpXtMknRoUWNdpF1SKKZG0RcySNFOLahc3Zhg/mBz/AJ6U32kfidl9y
BKE3Nl+HrPUCRx/oR/695oQF+jTPXo0LA3su/Urn7V1LHKWn6YEaenqH51ivMyIl+PISBbhNbbLk
yyr4FK7z7QeyJahMqz4I0yI6KCcBEE0U1uUcDlvJsWJL6v3V5Y4JIl0QvUPCp0+TDlOQrqZ5m6aW
YQAynlWlTYHrpGP8OsmvWlo0H4ADGY76JOA46h+triQGdQgoZcefScL9b+w4FcB6Q7h7yqEsDiYa
lrqHxdyOGRq5WZJNcCE7l8eeOLceEKwLwdDs9jWGIZZuDwW30It5FmSMTv0NpzpcY918c6uWdgoo
QzONzYrckacmpdFbMkZoABK849AAh4tJkXBFyrXjX0DzSmyelfc8mA409RFNXR9IeKeqSpzMzLAK
a1CQGAMav3b7EoSZqF5EHCi5OaQfkgg2kZ/ju/+DF3/GnbPLHnJ1sTqs3kBa9JEmt+HgoB5pgLV7
+rVECp1Jr087ccWkJ8wJiJYkD7oIkY3FkB4LQ79Hpp5qCzDCfHiqgdQoiSbZ6JzcfEpDuiahD1f3
OWfybGsZmveJTNq+maEwmLO/wspcPmLN9Vq2nRUCYuOpNWbn3coI48DnIQQyvtrd4FdDQGjzZieo
8MvAX1cGSTCvvmbrDUO2cTFq0UtH9dle1fVmRD4a8lCvASlBIbi27sGjb3W7Krq9eDsLHcJRT38C
0eksWcwD5Vn562bjdSs4gycIFk57vmqsto+tubq/+TKzADatxwhrM9VZ3mM9qvutd1kp76LfFw8O
/GYjStZrRRUzn1XJovx4fYdSWK8E+6TGEQrHQozq/+UiH2ZZEpcWJ91UB4ejO2sZmeav4sAWd+oK
zNLEDEzgpf8WdSdmx5zhPhdHmzzYAIBdDI0iItEVv6wsDCGg7jEFsKaSVjBkrGV9TiopwqfXZunN
oTWStcKof4dPTY5KUxhePsfxX6ixqu/kDzsu6kwEMAMyn8PpJ5uebblnwmGPDUl6/KkdZFdp9Ku1
xtGke92uWw6XpFO85iK7sseRmuMA5yowhjDNaVI1wi2RaT/Sq1HYRHRoCXiFP7C1yGrisqbZj3se
8Hxp/EtLF/QaycH4Jq3I4dAfQ1N3C/khbBJankl/0B8MdW3xr6Rpben4qVO1mo6USBPoicyF6AhK
yHYppNzzw0Mf76rIr0zXBGOeYPOMtr5OcG8mt/x4LyDcP7Y2Z4GUBAUmd1OzKJXwL010eobyO5O/
0nGfrYsG/a/OO/UkAAf1DG15nG4xQWCadUcYuz/Ev2b6cKZwHMrmmMGRH8OVKlN6vtqVN/S9tX7R
KQT1mw8ofh3rVBovTpa9e7F9Kf+Da/KCD5kfi74r+zNQKQWoOu76bxndb17LqahMxBaOHYNRSPi/
VitcGPSMW3le+J2IzSimTiQMQTiAnlowNvG97K1gVYXe/CZrDxYcwpsnK/LeWcSQLFkQ80Wz0caL
2EzLHWtRqF8rhXTEEVoQNvMo3UDsLDTVMDAUhaW7XeC5BRo2M/ybYQBEIe+PpLcL5ZMIsCUtGjIl
wMgbYYqPtiiadlmlVZ22OcR4fOotQFLM35K2BqAEdAcBNNLRWpa0XG6msSv1JEwPGMXKLgNclxt8
eN38NzoKlBwISK73h4czBMtA6FJOlfbdhM9WVNAC+MI/BCj6ozxtZdnPketKjoV3TaYUec+CUhfb
UmVZ3+2O86cMMSGpg0iDzvRLnNPDrqd+HyJSgMdiyDwHiQtu9ZYjmYWKBdZtX4Nd35gUgAaaMum6
DT9MeFc1mZN+Vxq9+LkUIRH0Nyv1mmTMpcwJ+oP9rpYiM8jgDlz3sKaIsWQoyjSeo/oEHqbpDE2P
x6ypPDT3zgDyU7ViPDE24niHkcWaN3Yg5cTDuOz3Dl/2Gm15PUFIkbLECbK3HPO4Wa824WN2ykRC
XFCX7GNnK0hD/J+Py+MRPmBCJ2mCv+7GlCKgrZwEyAJ6ALrZvGTbCkbOLk29NEZN6i+/fYot1shZ
AkCNUJSQQc9QIOmzsZZ5Pifsr9/G8YqUJgGVcEVxSk5ooMo0W0qadSyW8mpwoj9FmkPdWaKfQs7a
sj1FJg8NrsYj6l0Bq8xHs5L3I9vQFUZRQ9Bi4PQlNUPc7mGjbIQaP5G8mru3YgRvxXceSBMZsE8X
LG6ufMwCWBRcEmyWCbJet8MBz3Pz3PwAxOu1PyOK6jg1Qvq+qCsAf+SPIOSIWuToTteRfQulURil
Ov1X7UUSiQtVyJSYilPxoLxPnEeC+gJuvOibUc4bjyIGImYJJsOveCBzOGyIZm3tnLXNESO+jcoZ
409vjuQtoewWraSbaJG4KzDKQL3sf446G1xA6rbhAa7ghW7+nw7ixMN1BtKeUVvt1rgJgqIC1eYO
xUK77PRrPoiav4leSQNfaHANHpmtowBiFNk5v1P3O+iNiNhLE7yIrJcNQTHrtrSPc03M0oakzpPW
szShkJCHOP5aEP9p30JJWlFEJ8pkmPNPiiMU+pNWRQapGPpG5bjh1t4q0V2BoaZYtcAwP6ZO7GFb
IH/pwN3PT7HtEVj0LLD1FhTd0Qv8XQPOaiG8Mf9eoa+4OrCqKs99F1jAcKqpKU8t4+MbTH8KkNiY
9HFybJOmhdYYU18QJADUJwpPpZV/uPaTPguiXVgx8rVqLS61lDl9zwXsWS6ZBxOzB2BXyPSFAHtL
/+Zd8D2XfaaJf1rV9VH2toIO4jbSwu7S+K0yvU9B7cQ9I0FQWc9/2oeu5MPxvq8cwQgsIcV63FRR
oLPSb+zTynm72LXuqpBB5Uz1F/B9iYRlggjaMoOvnOQWScAGdnDlGkeYR1ymtLfqO34rCJ1/WJNR
VebFz0xFpo3fEv9ILEx0mLL/E9oneRtC502/5cOzmkrOt0+e+et8R/xv9zjou6F78g23TXOd+/+z
80bxPhRwS5VaLyyWhtSDBha5EkuiUAcACvQG2BcgFiFNJ+rvMt3714u1ltg63Lq2x3HJnmnB70V4
O2KTiUnz9pw9vM6MP3rvH9P0VJ2bgfdWvLQaY6tLjyddB07jl7O4Bo3gN7JAJN6VUKXrpvT9YSUS
Kq55xyxcR+NY2sGR9NXa+RWjwmsFH0J5iq7/fs24KwaPiHufXYBIKoOKfI++MA6oPuci5Q8FhNd+
g+fqu6na1J0R2LUIhI2zcjlg3wkOhqUtLwRIyWsF73E1AsQwbDGgBifs3lw0bAUSGQA7aiRy4Hyo
y1EsnP+eLiMQcrReYzjMcZktqZSyAH4zX/faOXLCV9g7rDHc786BDNBG3ETuUCn3q7dR2nrxPH7p
Kyjq6vJEF+nrOBMA5/T1gSdWwEu9XXPm9vZbShgCMRR4llmjzrKPDxrOANciJcKyWqe+81ci/rjb
mlKgLubY9WD7vmeP/wzdj0IqlvJUMkbhq1TyqeMN/B0lUJcY7vIMoPLffJq5ZalcDn6topHwvhfc
5JdbEaj3+AlurLsJlLnkEGYHJHTiD2OWOOOfjOVy7oOUmQtcAF+JEJHYVhzND0VdJqCVqL4Nr8kj
ceAx40L5l46nuv77rg1qFZ6YqMUvEfzFnAxxMhsQz4hykBkDX9KNoZqCWguVKPG5+6xwIdrXr2nj
l0EmRZqZrPjRrqzPJShSuR05Zo4pu+ETUY6rEPp5FDYTXJKP2di9AL5/HLj9qGjKdr8pw7XfcKkk
tQbzFkfcLAC4xpAHojP4Q5zgkIEGp5he2Zw1W3i6H3aMWjxYyi0GQffPFL9X9wLSdvbaZ9L5w9Lm
swehdarIsCw9k9ZMSgIDzwUMRN/0o5Yj0QuaQrkORZbmJA4YllhrYTjLCYn7EwGnvRkezHso1Qx+
VuoNThbwbxIsQKfkLl8UkYAYe70bkSCfrb8b2/YNJK00gsaco6wR1IQcuNK+whFXSaEkapH/o/OC
UDb2fh+n4T3hEMGzN0fCSIIOOWME9irEe5fSxzOMFI1n0tNTImSpppLeytOfV4ZxaOJaV/FiYYeu
0Mung/AYnm857azdYGBiWGRbK6hy38kGgfhRomCmJ7alxJRzx647l6jZhOBvj1R+ClwV/HVUkZB4
xP2+Gu2VLRb2Z+wG5Bbmm2XO+TllTHGZV0zoLgsVOq8b1Syiwk+B7BeO8xWbiXGizJ/1+CFdHBic
Jq4nEw8vOhvp4vmm0mLjZtknVuLz6PtYfKPzXQjFM2cmqKf1th2FKxfvc65rX6kQTfss7vFwxufw
qQG9gJsTqoPGRPuN+w0WZ9tpqvddXSacm51G4mhpcJuzO95Jp4eBOCDtl10/AGNDp2ULVD7CxL1K
lAQDhKHP+WjTYq9IOtQTcXSg4KanZCOL6UroYekdqqQV+GPw6+7MQDZLHHWv8vjhuk6r3f/4SMbD
80wHTkTLRrkLgFINT5ITDoxybErYrTSfmaZ6HITygfItHykPWB494QMKvLQ362ya2Yn8hW3vP/q6
5r5+4y40qEBefx6OkA9UyQOWDtnpkx8ScjBs0gEQgmEpDBcQkUtVQ3K1u/1Ok/yq02qGuVDbV+Cw
DNQnkXeLig3jpChbBMkkifcy0kRhvXy244DUKIfCAtPs39giA0UkwurgmNmehTwqbCGWjmgunTyi
b16/JJuPRRo/6NSYqEO+i9wwgVF04vi5rXAm0CaENGEJKi3T8Q52fhvhcn627r/VWD2vtElAKMfx
7/ZDuGWPnKzzJ/c2HwuPxUOQTubvnfz9Bd2zKQsE0uC280KnBQunlbcPtVJcCIz+J822iMIFM/80
Akb5wsVlXHCa0aJVryrt3Itc12jwd4G9l/CguHM2oTj3B6Mn3egZNXD20lmOmKXYx8Rb0ZKB4FWw
XCU0v43PgMWzIfP8mc8wg8dSHv/PbSdF4dRoZzg/92/roI3mE7/xAjBVTUEai6Gwya0dXimPUfCb
CbuTOzvased7UYnUUpVMNCnzn7SRotO7X2LiBZF9a1SS1D9BjIqnn9w5zfiBteezT78+BzQ65Mt4
OE05PSzKQq2ZBdEoEczH7JY3yf8HCdiHirKhgKBoTOV367D9qZ8UNebT9lC76Ywi/mecq50azktu
aX5c1Rf7Gvx5Hr1gpwvsxTkkOAIrdhv0SyAu+jYosv78yU6luUMO0jaFIrUtf4R0P1s/r56N9zsZ
SK6jro4itxYG+o7uMc6ixuyeX978TZrTYO2HRObN8wSnttkqmLVGbZ7th5d76NBWlXxXskOFdykR
cAVsdneVW88YArUGFuLB82MY8DrLdCN8ooBZQNbLWR0cZibJWX83sPC36pjtGicTBui97A16vNiZ
dszCq5orh58T/4Xf2Ms5oihYIahuH5IkgBJLaPdbCUaAih5vfGzdPv2g5R/KtMiW1s4h3ORh3CH5
GWpDznU5trS2+YzWvGiQRy1v6nQPUNtfxMfVn/UpdJxlDrB0zm8jZsun4KLCDMO5f9FCxOOednWB
DkcuqF3yNUpwStRFJaxCOC37DQwiQiTnVYlE5JLAf2bG9Bio/5qaM7XrbADU5UnjbvFTAplX0Ea1
Eas513MeoWxvZEv4CciTwV9zR3wkWTx4So2EsYURD7Nn04ebAgdV7Jx0XdpLkCRRhl/ZXYXafFqP
3cxHfthFiWR/Iwljv0J0odN8d9zaZ5jYEn03Dc+DpPdB+Lx6MarJNuU+1g0so+Ivc/CDJiTe6eBk
yvzC0J6GNYluKS+P2bDawADEmzdDhWy/4qRFAMfo8RXCS/+UsdUv8Nh/Xu99YPWav7x0j+VlCHk0
4oicqaLsk6QC5kU54v1t7PB1IGVtixGrOQejuF2T3uqez2b6qcthjlFYqyZD61V6OaU9LMhoINpD
9S+fzi3+FAjFlfnG4yv9h2hAqg9+TyxUrgf+9t46TsyhO0qgiulqkHfllSu1EU8Cxu97fCNFfLK+
5iGgv8OqRSfMjktdxBYhxSqhgvkLe83ug1QLJvixlUBnLABKUVD0GePYAC/T99VKweFccCUsu30W
i229wQIHIVF4IXlWKMd4qJHJuko2dWb/Zwr9pvhhQNnmXAldfohcf9qKYuhNPdqC1fFLCXfza9sp
Snh9rSW+xNOMWKcgG9M5BeFZ9XqomtQ+AbwyindpW9fy3MA8NnYPuWus7n5G9eXkb6yzvff9vRkZ
7jzK283OKW/C6IyIWiQObPYhS0DedTC5PbtU57wPBXK96DrHXGIEjF3MSyDawnId7BUeIpqJESR/
5xMA3oBv1qhl6DbWxS2b5BvLuhLAneGU2DhTuoUdJKqlIm2GOoqPFM2BdGQl7GKRgJHt4ULBs8P7
LfIMAgHiosVPD1KO9PRd5FUobbqW6qhsv+n3UBqwV0nD7Ybbln39FCU01DozGwvCWgvGrp6MK717
WK3gLsXcpMk7ybM/EdDT7AR3mAaBAwg1YSEDxDq9dTP/K/hPgzZLW866ZKdTIlLZa/1Al9bAzX7L
PbRx1HGn2oYIzIoeHQCzl676oUT0grs58J4Ve9Ry4pWlhlSTJRfNaqyscjeIv1+yp7ylRZi7xFbY
p/Ua2OVAdDcQhMp5tM8nVbGiNkCiRmwg+7ub0KH4IFUbW8p796/neuvIQNgzX477U9F1dzE1HQrr
DZxeqYR3ME0K7CKZ0FR4PAFvwqshW7lZD3IELl6JLOmFY1qnDwzLPI4ZEq9ULYrCZErhjgSQWDHL
qmo1dWdgDZG5Ib26oyw27Uw5KbHGJOst6B1nxMaFfMpRaESKgW1hpMXoM0mjGKEoMliDnxpAjDFh
SD/cCZ2nJlwDBSYf1cV/oqKZV4ek6L13e3kp+SIf/fe4uGTUDPgpyuOHTS3UBAInjKlsMGA2jFt3
k8eWk6NmX8zLTv0oa9l01AWoHlgI9uR7Wr9NDluH1aZ19pXFUnHxr1sOgiJrtebWKk3e+83PCP/J
m/OgSnG+ikr6gvnR3rSAefgLVLT7FFu8CLnigQS73F93z4hwUQxTmDXgjBD+rOsWrwVW//e6zXK9
djzhFHJ3MEJ3jlSg0BK8CBqDileSt/MdCpsdQqGDRpIMnxlzELzBmO8yo3r7A+oK/whVpi2RFXTm
xXdNFnSagogJzWqh6LwsORhsQjRx9Do5KhhXhDNcw6SUnNlt+G2ODHFXZoRpwzvPWXUp6TP84FUq
OQPiqt3W/mKcvvca6DKbjvUX7we0fRobiQO9cmARJAhl6FoKGHRPrslVxqLNygCc7Qbo//Q/RKBH
hO0deaql/7znELAIX1KKhpN7HzweQnz3Hlt2dhguM1ekK1+p6BBtfsCk6k9cJl539YNDZ4hLhRrH
+UezoB4fZY4aw5SmiGpR2wElkcM9z6PRLA7KArST51bmKHgLau4arGx/T1I7S7A9InzsnayECtyP
svnOImx5acD87iZnEXCIKDufOrQhBIL3jwPbLiAXnOmIHXNHybEvcXfbGI45EKSCMo0mvvdGLu6g
usr+Ca2TSgubruc6HeP3UFPf3IORq1ZJO6yQ40fh57hUTWPersPGkk6xIzjLUWqHPVgkB2ItTV9c
vgim0SF9tz3WHTx2CKJ/+pcjZfa5/tPllj75uEfMvhKJNk8x6WBtXWwDK1ZUlQ1S6A8Ju1skGUB9
2xfRAzBY1XNPzozULMKEV31wjfsJXMnPEZU3e9QApFhxMuW41U2f5kN4vu8KI5+KAY6lk9gSBRox
Xr6HNw1B4mgd+3BYdihkx4uSmxy2Fn9sNvJxxhk9WWSgFdK3BiJYrLsZyc/7g3Pj1PbO+b+zj/mz
TcLiWvqmxtibwY3Gbs0+iT9ah3ty+Z1qV45lZg4NeGO3WhuzxP6cgklqRsfoGOstLzBPmnRhRsUf
uBmMC1jFuIbeeBrSfeMCbxWvynRFPFxQzv/1UtsyE2E3CIY325F40PneCTWy07w4Kss/G8xmQrwc
CG/M/HQaHno1LY3MUl9zgvztK3/M30VDLn3cTWjYu7UXVuabY8SusL/G8PJQDA8I6AZO6RRkHMTn
JeQvseythbjE8JNx8gAHiQVHbRsuxnlH4J8F3w0SG++iyevM782iyh0zVpYj5zkUvlnE04DDSWak
bH3UcOM4Q7w7/zC8JG5OsnuwF1jgE60up1A8IapyJTDF1I2/nf+G8IRNvbNXSAM+Vg2JFwb9h9D0
g5vFd0EX+fm6jRXamYftcm/zQ7EygeFtZi129yfjJPZnROvgvmgY3QAnvbnhTK0WHDZMMnLaVGpm
2H06SSoDwIukE+VChAMAwkWWI/ssWEPUid1Qaoldpl+ihV6EKzxeV4HLSC2T8nCXXd6Dz8+YGC7b
ATzHB4ceI4mUcix5rQC+6AAZDumjVYiko3IncKcxoPeGKC7CfsiwcPlvrD/09/QBcKFsQa/MoSfn
1+n+qUgHL8eDmYnjtOhvy8VEH0VcbWoCJCxnW8afsZ4RtZwPu94aFXF9yw1/QNOSlj1c1rA2EuSw
WdChwTt7kZkKOKrun/WHEYt0a38IeUgIIXKAoqoOJWewGE9RPIkCCHyi1N31tVo53YKU1JeQTANW
qbrXWiabqwDiL8TTDQtUzXXShYZ1oSHlQxSgd1B2RKrRd9Yxpjm2rFxRBW0bgo4xg5H34ZrBPccD
NbO47K+eQ0cePpuvKIO3PLiYTiTMQRStYP63h3j5yDQhPvsWJ+o7ExO2+8qESdPKcdm8JSzgSNkm
sMT/Gygnn360P/FVrN2AfHE1r/xmY6IVldJbOSQnF9A67UONBGqrbIRJOfac/5FhYVwho11qMQhC
DTF4s5DYCi5PBAKGVK+p09JDaLQjwbUQJlAUtjE/0OYEPQLTdZyt0OdItm4ZkRGVkfXqpFWW0JEU
y0Gcr/o09CX3SRFIMY91r9n69XN0GLTG0vJHEzy3lPWx4IEPly83N+WboYdgtk8jN/nprbEsqutM
/fKIjUW2WUR6w0QLRjB6jr2hj7ZpsJITLYgV78VHl5yTMRTqh7LwguS+VFOS8boxMy6cu4uXE6FM
hjS8z7crXy03IFZKVNFJdd4pnyQtXI7XZ8JU2rZd3Zm2nY6+qJWlyI/Ephyb8zQPM1FfdCWU0Ucm
JHjl20b4wLh3XGJiEUzDKh+aS7y/2gA/pTeh4OB6DtgbT3w3A2M15ajLhRn9Q/dqDEx1WhTA3Nfi
4Y/m6hF5gArOHYQInFmXpY/dIH77uV8W8UvAWfj7lv1QhCMQCLmHgbZg4keGWUrnaVt44BPZv0vA
FhL/y0vUe4DWCt1gHZJbb7tkFUznMZ/BtoDG6+lKVW5BNIQ533ZlMUvVZ6khlu0QTN9nzSkrGqqE
I2+VPvTpZLHs8t5Qp1DkVchG4EJYnMG27t9j3Kva3OLLX2rSzy6siKUL3abTwIWTYBBkboInTjXY
oSh+v2A+sG4xOeBRxLsP9RlWBvzkvvakZwjzUB95oFzVGN28y7GylC25bFIqdZJhKtrqpOL1apiL
T267iuMHM1OfEaGALbk0+KFE2Ynq9LmLwFwdejTWHR4iRMWSwp/gfV0n+SAWFZMORisYELP28ziR
2Eim+DZf1NWPQKQMJ02/GyCZJI4huLzdNKEh9oC7YmDAcmhGmso64oLuxfdub6zKCOOeiQEEW5eS
TYkXGDrG9CESnaBEZZ9R7Cx+/EkOHUEBfpRpCx0gNSB4oj+Gw8kZ9EoJVf5qHfZNjvFP3q5msbcs
WTr/KyYZdK1nfGspngVqgkxHc9fIxRixk96ja6wCIfLccvDHR+apFt4a3+DHsn7DRseFydEA7cGQ
dvZ7AoCqF8zaTc7913fgjKkclYQTh3/X4EkFcOGoAyuVbksLy2cK8okHL/c7Q0B4y8sy+o8ypacQ
rtYBEXN66c2SuHvgrDuYXBlmTzcwU2vqGJfzjCb17eFtuOqstGhj5lwVsKU0ZpGBN3woBWtuMpy6
oabHdKuPcO3Zyk3LDPWDHyd38JFjXUWsEyAlt5Tj8yPBAhY2MEAdrf4c4VAxmd+sI261HSJuXqDu
USAWQe1D7tqZBk/LZedCP5HIreQ2BfBUKaXRkLfKP0+ud0t5w0f19aXj68LKKH4wbAN4H9XqnkcX
F+vfdpWexPNqTbcNXUtiphIoLcsiIDONedL3tTswzK+iM2ALh3aWsHnfui+vnLX+jqsasp9eT/+A
1XUYYejdMTpCOffDWTacMmMMXbYl95kyZ5hh0SNTg6p5MzzDXinVynLVEuqilX0mdy+O1BOoBB4G
cN4l7C5uFnbyOGh+eqPp+q66x/vup+5S7pjxjlT2vCDDt9r5pTPm26LbfdDat27JO5guE2hDQGSR
+qjx2H8Unzf/ghp4T7aGf5EcmqZgeKR+XhS9r7bUtOL/TScwEnBi3FxVo4iRSN5JkWa49wFzzC4x
XvNBbAd4g/XGuivdNzLf31vc0JU0cJok+t07yXjFi544CHuiO0Xvq48CGzu3VZhggcegiH7PRfSf
lWTZMkxXU9HTdwAa1RaYF7xC/IQNig+uxXdoZrfQhgaTg+OBk/617JaBCVTqYFkAM1PHCE2lKqjx
Zr+i6GV1K8BTN+q1HFHCo22W5z6mKCLilyqtQp9LO/SlSLcBQ23q/Zi0O0onzRFvNVjnTA98Z18J
NlSHbZkPTHbIDnsltYNZaRynLOiaEP7QzsXg4feyUVW/6pbIQsZWrblweF4NEkEXS8q6jGR2jAN7
oRrxA6XChit4NNKabJw/xVgG+ECgqs8iKcWyrAFVneha8eoIcnq+/8ZHejSvrnz1L/PouT9KQjHL
fZ/8AqMg86kxsAB2lVCYeRf72zzZk2SXtFD67iIFa2wLqUkgeGvu9a+o8LPDWq6vs7x+ALkOabS0
Hw4352M0n5CIZJXqlGPkdFu4lGeJatnO31ptmJMh2Zy0lVztT3q0iXFEViegzapEYqyLhFFulF8m
BU6dWuTKRBCumbq4hOPitfe5fv0YO2NmopCJHu50IS3wIS8nitha/RNkfU8Q5/NLuAGMkbPvPnIf
HSTIkSWoeG/GQHH/Ll0EfLHOLjCqd0pVygemK2JYqpqDFpoYAV9DJC0/nvzptrFm/blLW6JJWoQn
8yGcBQBxlxFNe5nKvqQpRLqvvdjBe87VYlitm1Su6vSIIPbeFI0tcSMyLIl26TS3cR9X2BaEgFfo
/48bfgPO80P5vsPnRtZuZoChmUz3kRAcUgB/C5c3dUHq0wRZh3UJLnXPsAiO5H9sAKp+XiXr7W/s
LUnPGK2ySWli0axA15skNb+Y/Z3x3ofWTLa/Nk5HYXJzXTO4xPx+3HolPxWgEjAqCLtpCYgtsZqm
NLU1eSnMELcGyA7wBde5JTPJrD97qC0x2XE14R05gnfNrgoDmGnucU5pH6PNWWBDMMHcJ65DtA4t
dF2Yf+l8/36LY1mO1eVeEDT84UqwvtlXC52sbJ+7+4N59/8DcfAUK5snY/cCa75wry9v3WOiar+U
OJGsn2YTxxh0zaIoV2Tz/KlUOoe95hXVyPqooU6v+EW3ou0wQhpepXyx40jTYbk06CwU7XuTrM6t
/GCuV2Wmw6c8oxf8fjkYy1UpOLki/EyyjDLteuD0hgfHw9zn1jav1sZxXUa1M4o5Z3S8mqg6am4T
Bb5saGNNecKLkyEiojVvVA9QnBR1uiEZCNRxQO1t1fmTRRik6gGz2OKccY17JYCdXH+C79IRYtPd
LCFLbz8f161z0vRXyQQQFkNJyCZJr2lYR6iw/XA+pD2kJ/4ReRpywz85V81UmwUZd/3bD0eFz9If
+ABVoVSKY0hRjUoFKXFqdM2ClCfO0Llv5hkOHb6GZOUSCosvNP+cVX0EYykrJaCHhDhUrY31SuJ1
YAmmRQyP1jB1kJvsCU1eTVYupjdk7y/CGURdcZytD7MuvsjIhuYfrt510LTyu7Y5lwr0jvXB2TVw
RczFcS5uM6MxDPaEnBhISCYVLWaZqtORnXpnnA7NlUiK4KkRRF1HItIVvEWHW7pLBGd4WSoBzeLh
e8pt4j57Fb4VlZ380Vwhx7tvGwKA1BPy6w6wfGj7/LMCIuU/HDF5UTdo+LT0c6e1S3d9tY1zliMF
svB2etXmNe0f+90qr5dGVgD0bE8pvQiPIufvB9r9hdklnVPd0NZm0KmkaDPM24c75HKg9b6r+Oh3
1Agia3Mem8IjHscGwTAg+NipcsbO5zYG0s7QoY0WCEhYxJEZDj9r5Ncw7PPXH9jC+zJAMB+K2tMw
cSKhxXeddCrZIBpe2XPkUJRAPqU9BXkiHJSRk2NyjM39N0eHlN7FuNGjpJQxDl1jC6o7hQbWfSc5
ALARhhPY6WxvwzaveAQium5MlJRMD22Ov6XMYY85eZHaesLpchX1kqgQb179sJMW49y4b/ZQAc+h
WVi9yKVyzQXMfdOctr8wi+Fp8P3rsdLRKdpmZuvtW7eSiYDG/mkOJ1nQlsjjpmLP194DS3S+uDJQ
b+3n1NVgvoWefjnJRfJlv8y/ekLlt47tphu70DwyJz9zPhip4KFDkvXHM+v4+o/SxZrW02hHe6Lg
XOcFyd2W2TCZ10Esvdpqi392qzKajuilQb6HJUI575bzjzpVMXXq+qtxYqVYH5yiD1BJb++NzQS6
Qu8jfodu2+JOImMvrEeKvXmRzsvu2DGul6rLGQfEoPrzc+gq/4JHaMTKQDShTsfE4LGm04zC0QvF
BbtjEGp6aCXGLJGtDnL5Jah5q1Y7ssMo4MMBmaAHaXB8G/tSiy+vI2dDck86oeSNHMIY0pQegJmo
YPnJKm+lzZLJGDFZ2LJqZ9cadmAJuXvh0b9k4GSyODBjGpJ982wgxUrW5y4104ot1PVto/yHEBBW
w8BvxD1sBoY6wW5GPPEVsu8vJu9LoYOVkxQ/kFt8T0aOFG8ack/ZOazr1vvHQNgAUgNK8EOlK1XF
CRO5AQoCTmibv9VcbJIY/q1xKIkovWIt1raYqkwzyv1NPuPluJNUIgE4wR4Xy986744OM5DnbcN7
G6je6jCsVoWfy839f5UWQ6XdwfqfZWQDODCwgq8kwoNrjYjGZB+HfBPSZ26Yn6YFP0skp1tfVw9i
ZLklnlCP8I3Q0b+BFXhEdLrbAzsPDtvKONa/XAS25fTAj5BOz3V81ESXeHuX3Q7mEjdtjmuDU84Q
9PV1Rdl01NZ08gzLSHAsmDLfT/mV5EXj01PcvRxDuw9SnqLNIJm55aVmTHRcg1QuW6/S7s3BJGlf
n8FKiZVb7oCVJ5uvulmH/XeBIwu4sRvKZESUhnSlP/WwqltZ/8eXHyQa5ksxjBCevlI3viEjbOuN
WaHLucwAd6FM/yrSAzS1QEZtQgUqCU+Abq/mfiRWnePDGUvphI7zMQBSYYGqNHQIIyFowJr492Jz
nytTilwAHESm6vLF41tDtvY2NQHCw/YxCS3LZ4RZIQxUIKN/BXkUB/jokOeRYlVUOI3ZITNbmFl3
P7UET6RZOa71pD1o4pnRgmnczCKI2kCWe1KfohAw01bG9pJ45yPSvgGMpdM8GaLLd5sH6sxVha+W
GTPrQ8a+XIwj49q1q8b0RSdubJIVc1o8mGjXA6En9vOT7EsB9hRHvKOVV6w6QEWT7f8Gv/ju6Klg
LJZ05P6faidApf/g9YbW78ID4+r28vNUgt5WESkt/hQBCEJMhgMiCvUuinjC7pj7A603RmJ84hu0
KHkQGeJqZcLNImzdQM57StKIqkRjK97Y2T2R3YTRnBKnZtqbTmcwKflp86hVwdRdbdVkhDb4DPOx
Yj+QxCAGzSK19y0xrxUiI8jC5GQsHZEeHXDVE7GQYvPbUaTtwRahdflwyqArOehMgTgH/xI654x/
VER9Q5tnrjwnW6exRDTYVOvOKrGYfnpIWABfiJHpn7+p5XIwDAloIv7F2j3OghrmXEQusyVe3cTz
V4zYituxGEoPAefGZrc/KxJNeS8BaHzUeF1rWLlgoM7kWpvq/KLgWZfYu20Bkn7cUoGfzISJvIBg
KglnJMGOz4BlxKIFZtrBuc9KnqtndTcdaKBS8L/txFUdC0P7BNSOpzvQoCw9yPawFuN/51rAnU9g
9F9NhM88FtmOM1KAQwkrjjz4f33NBqNZ/zwYzc88siaswvHetTkf1KfWtgd6PrzkVvVPfSYy1vk3
EkDRWDyi4YURSfgK9X67XmL4FK/qUi7/mbkuovde9+C3EHB9o06ViX+/Gs/m7T0iwgfy03GIkTYt
7xxZJLa0dPd4pD4+CLUfrfH1HH+7RCGZ4wnTQbI2RYY9cHVML3+nNysP6xbvvkHFdlmFc3aC+gtF
WHJxcvPL9TlbA+2khgXqH1bV2c2Zn7j4cjdBqu9E6CZ94Iw2DVnBVhoQEKVm8fCbUKq6NMI7if6a
KZvIh6hmPDx60CLV/fyrDbxvwOOhu69MqFcm3mPTshYsSC5guaao2355pBuJZt2J4VVu0xX056Ks
vdZnxnHWN4Mw3Unnc7QiiaL90uP0gURAYUKmGgSJaRHbhd3HVq363RAwhu8VfBhcOCWyAPj8v2F4
9jZWRriYn2rgVdiL8zDi1w5VcpRWqCBgdpOAu05UHKv349pk3jWgAp7oW3Iymb8DrrCbwmDCilvZ
eHtd4roZgyDQglvXlSfS2yeofgrrbYQlx0AwNbJHex0AIqC58/8FivkaccojFejPc3VCQqpu5yLr
eE8Z/zqklFZoQBVhjwjfjKplV8NdIwXzRanP3OMp3xTZWPgaGrtqsbDHXKVGXi+VDBXNQnnECUG+
jeSHtD1Idde6aT11IqAXQnhAN3ZVhemaYHamU6PSuMWXRAHRmLYImDHYaFchrdImFu5cPbEXiYYk
7hvR8hcztY+eraIROg6A4dTqZfD3360Q6pTmntTqLyz+duPCqcAvWm6QW1WmYn2TD0/p4QZPE6RG
pWqtiv3PkFQ8T8gED8dcrmxhBlRC1M7gMmLwclH27PuwUNdfpRpdCLSEtjL+K8VRsj4OKaa8p+3o
kE0fIL1LhLzedqQPWxaovyzaVm2kgxfS3sffaNO+v0H1Osh13bg/vsflaP/j76IwF3hTlzZIuBFB
pcUypgjcg4Ql7ysNboIiwoECbbStWkqmdaTQ5enEOVZig+DKYvZKRlD+32mDuY4bIV4/UpVXp86e
CZB/2GIeMlC0kALtFpH64MOuWF9fpgX9BPnPFpv3rRV1TZ608GNtG58nCEv+x6Xetlbzes5Z4FO/
AwQ32h/Q1MtH605vzEsQQpqhdTex8/rq2Rzp4GKcOhtSUuYbzQOge94WJqCK2QXx06mzv4Msl42y
V+ivj+c6jAyhw0vtbjHklr7ZXF2n/DCH3ee8y/yUrcP9twi04rWOHndi0wchMri0S65/jTflE2tb
/j6EewHvP5SOcfQWyZlVTGq8BsEWS+Fo20raggYsXviAmdS90Sx++UcbmiQHvYX8OamlRvrh32F0
muBzyT6o2leU7Q6YP5uqw05c998MxLs8IdHlPpLx0ua4hYoUEPPzautNtqReC/czmpc6lbVzRXhu
UQFdNcXd+/TykT/4EOlSMvUs9YSEiAlMCVY4ctRa7N5MqCq2l9vX+Ji34VQqYXRkbDZZojk1Dr70
MXtHSaNbwcNy22Gwy72tRevTu/A6OZQE9dFrjhZ/v1uNvePDMAvSkE+WyD6qxFFBh40ssLuAFIws
XwUjhB4oo3HRBilj5Wu1mAHtvDwtfUSAcZZ6L2u5D9F9FrSEYdM2hkNpR39roVY5XxENzdA6qLb+
QXj+nRF25uRY8KXcyWdOsmb74+NfyboD0yM53OzzKnw/MtZSRGjwiQ1SToGFJe5f1fR363HcdXc2
aOVInF0B9PO2Zr5aeoBSNO8FLXpjR5IYWicvfFIkLQc4cEouqj8u+PBXK9/b/mo0Ov6AsQHCu/oA
Ewnd8TtFnFVs65qaiTm63HTniQH/iWRcSBbLe9sMtBYATQ9GuKfsGQcVCe6REaytmdYCT1CvEJv/
FyAHHNp2pMX+/lZAI1GC8MTKiUWbVu5gX7bG+Y290p2/mdIYBdQJ06PkLMPmCLPXg406dY9NVNcr
EhrInQjJt/d1YjJ46fjcU9vM0xO46gJR4Z5CYiMvDehwtNel/P4FLw4J9gdwFESnYUu5p6Fm/b8T
VcJkm8dtD3l/fUMttirnd5Ta7X8BgzEG0L7EndjaMlyABS2G+vkW3OnUA68mMoKHzoG+iycr/zls
8YrxW6hwS1XKVh++HMB6RsYsWvTkj0XPR7YRuNJAvTfUTPS8woVNj9XpvL0NX/PilHiKBn/Bjpwh
jZnx0DG09t/dmisiXnYhdQERlOX0RGak62hlTa3Sarkerh2FJJEaNS2HiUxyuLtbylzjgns0tp2d
uGd48L0UK4h4bJqbaqfOganNJ6cRwel3MW3wXDS7At3B5ZntPZ0B3V1vK85/mAKBeUHBr7EusLHY
rFdGQXiVI7PxKYmE94Oje26nPzkH1XGtYu85J54vLGTyQDVIo8KkAL95LeBMZKNFzyef8qPJWvr+
A96a+/kae1/45DFKNTYXK21+FaoR/bqmZ0cOqXZFRHUMvQ81sm5pvptf1zhb9m7ajKm/LXOgYLR6
e0aafzzX1jIXrG98sCvhlRaNqeJqggmciC4xJB/mSJk5gdhQovzBwRLvmDyuYJQV7l0/ciseQ7gj
uQ0nlPFpOSBPHgg70CSTtA6JgZdSWyFJf+aavGyT2ZotImdSby1utvybw2T4AjKwiqw12VWXYMf6
8+Ya/pIF3vca87JOiNY/UQxmHW+A7wyN+GumdsNeQh9vY+Ga7WbCZSxcN96sXfk96zY1zssnfhhw
yehdGqvTMtoV6ql8prpqhXcVQx93Uwed/KRAkL4a34B/S+pxDg3i9JlON1UOKLYc5gEBF8nNm98T
twYOneM2OpR7yQnS+UOX2Vf//aCa830Z5d+iyXgctfWBK3rnYdaNhPeYgn77DprHWrZ70D13w+MB
AY4c6VekAb9DW+udx4u0CXxmK6d7aHWCmXYRmv6a+bZRZqv8pRDVqRmyqdKtc0WNhPWlWkeVEajq
c7vl1UuNkkoNm0prVIZxonnKYAzX555kFTxM8UgCKhFyi7j+9WuJNUtK2FfaGkhBaOxE4KtwkHXX
8pwKi3m6HvR9ULvfKYzaiBlOHMz6l0zj06W6GkRhQPSMy400XyHt6sp1VwnTa+WIzMrSUXQJ+AUf
NWJ8ufyUziHX+HK84lx7EVyeEEzq41pfSR1mG6P0k6MFmEE9wKzLhXoVylXi2djFVPjn4f6IwzaV
vdXIouyQSoKqvLfjtl3xF8hP1iItazJ6EhmrIzjk2Tyb47MSDHMI4qtQB1wrNtPPdFoKTyU1syH9
JOqUfms1WXG06e5sJU0t0iTxFOcigMrmlHC8Ea32/3ybrbb2OiDt8VC3sIXxTCxcPmRMzA3Hmrvj
+TQoydjzmLe7+GW7NKrAxhC5YRzTWoENsQlMktM8D1bTelM0PW8CcyoWZMUDTTzHil1VseNaj2/0
cpkGbrsBPalXzoiUGc1euZd3bgd/u+twSDJcpYYHIMFeN4vRzhx9OjSYuG30vS72CCtfq/qnhRyr
rNPI0EqNWrMTS82SfCqhbG7O4AU5M5PRHfKLwaKTC2ECPh1bUnz7MCp4LBw9ddAciLBFItAZVSYo
sTZ43rFXVr6go87Fdz7c9jv0QfiQdpd31t20UCfJdFlSokKR4kavta3t8lVUMfg82hJ7kKFF1Yew
bKgqkuGmppn3gHGneWBt0pAsc1zy10Zff40XENkovWQgJLSRcvmgLzizHjeYix0wbgFL02weenoa
4SPNMeX5M7JUx5sMWWe5v3YyAXZ6x+j1Dlwy2jCd5WU8fOwrlFhMObTfxY+tL/gyMQ/93k8SWjcS
I6jgvhfuMQ7mQ4k2jB/afoJLN/kCGv8/53GrK1BdiH/XSwaFhfbxlDPQm3JS3hr3Vnk2nzd9rtSu
bCryPh42YEG8wjcjmH92FwfoG7tY8pwmpK4wHf3I6VSlLPS6a+jPHei6dSBRju4j17rRWQtnnfHl
mahXd9zQ14Iohtaazl8fY+eRoZy7aUenVCkIEoRPIQe+doaYF0nNbqhfVOg/OZMU3RHKN69FBySQ
F1iY3oemrkcNz5Gad86LxLM2FFbcu0roOesc8J/RcHvD4oZJqVfUZZfdc5wPE7H8bO4RL+GbBVPj
OE+27MM4p7kJHUw2OH4MUFzyMCDwyskbXrrtM4bp8nIs6YTt6MTh/dR1sCox5UPxxlgwCmLgFwUL
lr6yYeGZ1rCm/UiBjcYtU32C+2OVH0pvKSoP/rlclesu90Y9dmegtXabBLL//I1zQ9NPEg7VPhyn
1a4OzEirSWipwxwbzdztwhcdmXBnX2Fwb7nJ1A03aNOmV0Muw9uZVSVFNsvFAGCtLBn4VPveUcSW
aRLv2xSoD+5waZTWUKgq1MDE+bIcGPmYFkGHPVNDO04U/FgSt0sXjabh3dyedco52HbUuX+emCYe
EzOfFxBZXAP7SOf41p1kcmcWV4J9LBQ+wc6diOJeaxTwc+TJTUpFjXQ63pFAc9JD9xzhjLllQt2Y
jtsk0PMGtKwkzw9a73xiFYqxJbf0EPaWm0vSopa+lFBRHI+Nd1LkzXU/slboeAnNE4vL1uj2S1en
tjMTTZMIY4Jij3Myprd86xLGyAscSLsF8AkXZxvIgxlXWQHumEN7uc7vcYuy3tPNY1KkPH2cl1aV
uZekgI2U0/20Ddy7IfNVeLjynqjTbriD5wNb+6hLz9ToxJLj20dUk0JXn86WNb+VEQvNV+cOGwne
pXPMX/I7eSG6Nl6JupeRSNgGguRENHT5HA6xj9BgS8Pbvj0uj1l/F+aDzSfu9rLT6ITZEuI1K/K0
8DJebr8EzhYYrNyrd3rnLm1cRvU2u6KTgE4hNWet1sbtEzDnJj5avVAb8l7rvrJVfE4mvgUXxT0g
Ao8XQroIxCVo87rUFGJbp3i7lu/G+4DBykRqrml92dAZlYLH5sGIL4ndrcc/k7Whjrg/NXwnQsiD
1K50j7dA/D1Ug90t+XV/SOgcUt1B7D10fGqQDHfJbgYtV2CJ308hB3dnBrsDJHR3hcM4Wnlx46lP
iJA81tMWee7LRaMaEtSk070b3Hej+mq4jktzKBCOt5U+F8R3Cvx+k/3eliAgdfjjz13JhK3KI4Lv
h+7oHCCNSJxLdTtrACrjVgjAJrTDbX+JDT36HlDGfO3G0I+lJhv5479jJTtK6RfVXIme9wpVtr+R
tLVTsw2TUcOqJPvaw0IEXPxPO6ikUDNgfCpKyOpC93AihfOyGLxIMOIpq/gx5vGxur1pvHoWAray
ApPrfZnCpqxVEJL+qAGuIIATNFXVaqPwml62NPO0TWNccq0lPD2W1dtlKfE8bVQEVex5hqQzhxtr
uyb9pfyEIA9vo0BqwMgFEGZq0phdoWpSG90ie3OkGQxHB2S9n1Eqjnj2V5r6NCUfPX3cH8t/h8zE
V3Ke+13kH1bgMc+aSGKBuRR25WIfnYKaWI1XkDV3UdSXVEmS81wY/SQEkBUCF+ibZR3o4lBNdnoi
YPy17VI7rSB4ZkPYhWsTIYljhG+kZMcvAHa4+6V5hACjCEQnDfaWU+hMDai/7zzKmadbVEzJO9rQ
cSzma7IR7fQCvBiFmSFGvnyHCBLJ5F1hSis66l2piNW435WqLHLbuNZPLJkKVuosYOtMrLJoepcv
+i6CqRDLMMAmR0jRoBlho1Tgi6YGRlf6LNgAiSNc9dFcnvK7zrLxsdp8Ogip0PJJfudX147uFrbt
Bn8eyrhyqW2coYer/AJjwun0AleAv9xOvSr+ZTY3Bo+c3HB03UglkGhnOwz4dGmQjJmsUMYlETQM
o6iEPmL63dJJZl+rKe+a9VH2PnHhDauV3nILSOVY7OEMrgwflglnVQzrIsCDVEdJr11JPiTwQtGv
G3GF60E9DhHICgllE47N4LYVOHl4o4RUsNmjIzs0SCqd9Yw+F0fuy0xzjH7e8g1m7FLLCniHVsaZ
E26KbPwz7q/C77P3zPJ+U+ptNbrCALY5Z5ya8nwGSvKlX/02gjw7TIEYdpoPZ4NyWSs2ygpY1+aI
l/F0mYLNn6Ay6xK5FNQPoinPPgkLvkDugaWmhy+MMiB7c0YYGTyE58EeV0ieRcFwHapV5J/ZO6ly
Z/XRyajzTzuenlNuqo+Tx1MZ6iUlrN7th5Yqlur0UXZhIllCYlr6wMvJtErXPNOms3hUmDozuuXk
a+F4+tq0k8jF18JNAXJX4dEeZD0ljNdhf5byKOx67Kc1K9Co+fNamjJMo5yKUsyr7TGjiOGOlM6X
LV+hE9QfyLER7gZC2pmS2yzXKwgCGmCYvzyokzR2n/QFKhIX1MQgTpGqvul4sNDrdTVTdv3f4rMG
mFM7iZkCgIQcTpQ2JfbswFOcaf+ZslunC/WoEB1R8JUFWTn5mHEMR2pNT8uscn8CDaqfyuL/T031
J7EG5448YuUmzwWDzzz0+SR6RwrDRuEzhOFctxVMGBDMODQRZVdP8lQ8/ftSMn9+s/AJ2ETwc8kO
dgVpNvEofGoXO2mptujvUsoxqOnMv5eMC8m8lLrZnkaREghrYdx7yjb10YiFLqZfl+FuHUV2s2AY
PnzCxLZUgJig0uqiRE2SJh/FgAeEzd1Du9Ic+/X5Rc17q8/PfpOwIBL3UW3fThm2mc7XZai0CaxB
a/Ln+bp3NHkDQSGMzKSyq/Fu6f7A28grsunf6+QIAa7Csx0InioqVLRXHzsWP4LoU7l8TAgwTc5k
CMk7zBADj8JNRFcQdJFI3+w0/OxHaNgwBXzknMApjTAvPkH398nm7E9LbUflrg+2P5swV/AEl2Ds
jrnP/9r3cUyqlydUpA4ZT7Ww9u3sXGlQZ0Fin4dECwU2VbVIVdRlz1ClRE1mLGNBxeAHFoMk8UAN
08HS8sLcf3/8SlxTVJrT3/Zwp0uLXYTkEdakYwE2yAr2kv2RYTh3pVadPiCssi516u1lldbiWPed
JP9QPBKVfw4JC2eCniCuI7jdo+x5qD19HMB4a/xJ7pqUiOtxz3N0TpMHKue24NP0du6/wZNKX0bl
TXnSpv2MOg6sKvCxZ8e3CgKU7Pw6Yymzj7IZThYjmWMgS+3zwrCcZDNtKTm9JCDJVDAgG8fPTz+4
bJQOrrxL+K9BSIIGgtZVrvmhr3FPabzPFDm4XjIm24c3Fi2jethM6OMJCCX0yo+SieuasKyJuail
wFtRB67oS1RAQTMDvvdert5v1be/u6kYqvBBi6kqvqkhT5xL8minxcDUjr9eB7Wg2ddcJKkaGwHb
R7ZEGSj+YheMYiEPANcVEzWXw4yMxRWEJQjenGIYVYiR4mXakcYn/DWsrlJ7EKF2TwSvmogiFBru
Jum3NqGQSmRh2UEXsolohSRjTEoeANP5/JsYFWBBph4WnJRlzZAiHOMquoClStpH0uDzvWdMJWJU
fKUa6sdqBFjwCUp4Hppha1wCpEFpIylN+Y0ywXFwRdCCuvLT68gF1+Sn6iOEhlI2/ryQ0HqFNixO
DfLp+bTO8JNSYCpOs/NjzXBMJcg8NB9iQtVmB5ENUxw51FR18FVafmzrywhTPn+bU5m7WOd+rF3M
W72pMCpRIBvxngbAXksJBc7YfRJC0oZVZGtPyjEuQbCsMJZbIdbNazhHx/RsiFqWQ7xv/WkUV6qb
TqUxqsOyM+y44iyEJusD0Ia011B6gKy9jDPQqyHSJDFFM5OzhZ5yMKyZrfCqEnT5H3HIyLlHl4JN
tKjbyaUEh6fpHZWjaExJQf2wG3dvXK47044i3uFsb/uv0Ah4WMlx8fin7/1mAAL1MKBfTMcF3ipL
8ObhmLJa6M/pVeXQ9S0ufn4EqeX4ET3Sfkzk7HCa4JeHG1Ma338swx05g3Pupwl8QSBG3nOIPQCO
taY2N3WoMqZ2LeO6sYwc560vAX6CpQT1ojo1e5EF3CaepZnsAi8OvoCHzTTa1OKrlg0vKdl2gn0N
6VRURvQT3oeZl7bbDFEnR+nHP0pGcJqQiLWtgdCOhgwMGyra9kzFOMoX4gMjJ/xknGN8RUQDdsgR
tlBJQX4cZ5cQ/eXOuDQmVKRg2iSy71mMuAiDANn7GnMBOrMS+XsadblpmMTZmgx6ALb1uYQmVuzA
2kQGYHKLcjaJ2qQjPx16b7QoJn3wdT+cCCBDMcEqjaeaNk0r/yFiPWkKW5VIZgxOKvKDwdW76+js
8YWlG8NzAR+2d8mqhjDLgn4XnJka8TZZ0wnT7MRfu9/eOCLi03jyoAvku7azEV6eTSTRC8ea9OcC
JEqxzsj7fA2+RIi7Y7cAy3t5B5DLa8XYoVVHpu0nN71V05Z1pKl2BtdzfqmywMkl8AlL9MWYzpnJ
4G6Z46efAQ42qoBW3HzJBJy16i6eDb/0ipIMgGFSlOsfKPgNeBG+e2oPcRSSfTmFaOgMP2lb41Hi
CjZXjC00+2e+xDTq8wtr3LtHo1DzIXG4s563FJBQ0eC+FsKpqW7vR2lLUU9semDzxiQ9+/h8XEZW
+1F4ozr+TANFHlFeB9XhO0aHGfSy6+92pot3L6rJrNpPWtX+JD46+OqRXDhXosWy9TKPzK6sISEV
DB7EF+/Zq3hlK4Fv1T1jQffRjwCjAKjnGL1Bg/1U5ru+wsUQoMh9MTJfEtJhC/f/A/FrAf2RrtHB
vKxgUUqJrRh67dWehHyybsJmCWITiYJd6dZ9KLsK8MezIgxOLjPNYvy6taGoOKCMEOyTn/9Az4Gw
FesvAD6ksFNXaL8TZtVVu9k+DW85lwhiKtWhZjhexX3Rl9pRuf0JhUNVpCY2+OpPWFHi8S7mipF5
iq0uUmgvYy6mynv/GORuLSJvv1W212AUzXwuPAqRrJe4I7MhC26ADz0gCsr0o/fFXhGwaa67Vrj3
S7gq16JEgJj+6N2Gr65KdnAE4haWEZgvAY897SYeog9IN6pZWUOK7r46OWsk9M1b++VORAkW3S3/
LtD5l3YTI5632ndpt1jxL+FAMNUNorJuIVF8Ldd7BcTCTFUIncVjCBJM5frDtyxJypCnna8kEZuo
cGkKHCPARE8ZB0Du7j+rcWRBE/Su6sFWrV7eoeMpj47LujdJ2Af7s44uILOhLfvE8SA+WA8sEwLk
6Fid90EnQhwnfp11bnu2dWJBKZn43A62s9Q5I56Ez6vpGA1ErjZc0tYCl8MnbKly+GcM0XGXAZYw
W4v67ekEBAW1os1LDpNb3xs0XmKQCYtF3DRu5LxnKAMqWR0oI5dSupBbbYhlI2Dow5XauFSUlLDB
6F6ZEG2mlpNlxiYdQQpNH8s0eEVu2GZCIONkthtw4vQh6t4neK3zTZK2EFiWvoYXymLSf1pqQ5oB
7QKQ6EPVzDtw+kYR/8pATeUOPdAupYYIIx2L4RrL0koQm1bWd2XLbJI54gPYa4S8EqFvIjzXBCqR
t4W+wYiNVlJ53flmgYEc8s76LvS5iN0LuvCDgmVfvCaO4ZdemaluBdYGbwmamWMeTLv+NXFSwMhT
QckrggqO5emT4fa6NzlRFE5Q4jAHm0LrLJdfmbX9kFRC9R32eXlELAnpu4myVHv/DhVCTLu6hSUA
M52eRLXfKD4m81i32g4yHSlW/7HSUAa4ys4fu1FCmGOfrP3Gaz05D1qJttqpToG+6q/7N6wCdBVW
4DVkbnvxeDAVOCXs3wNd19nyNdBqXRY8LcPMXs948tD8cxTapF5gdSleBQwdynACqgJVxJsO/EaG
DGRiaxRKc6HAVWruZ7Qwy+7GYwyJetVQ3Waq6G0pXouj0spDg5cWAA724wNlX9cbzJlsQt1HQeTP
vDUgTwzcaCcuOHoWxysmbsAZUraQK6zmSSrFItjYuyQcJe71fBlkPusB8apU1gZctpNmOp7CVG2j
p8sQmPOZKuX+pCd/pmqLCgDFpwoJRACzbVvdZ7CoeRU0sle6wognSI8peM3uICH9Lj3pQcfkVAI5
dhrNyfUz+Eay+pQiBfq0T0N1FRfhZU1BSDoz/97GaKx7JU7sxPpDPiYS49KleaOfy/j9HhN6YpsW
Kh/QPMRtL5DFtrmDMBiobpWh5OukCNOqM8blOkcm94gimjgzwQgakX8hWOAE9NsFLvxvbbDFvrOo
RMWuIfhoHB48KmHDgRutWU93b540vpwPGPgL3VAh6gfORTZAZhlRMMm9tsuVq7ugpOP6ZwMWIhHv
sVF+I7NowjUw81R6s/BS4WA69ILSEa4i6lwqIL+dzNGCLJtkCHK+6Xkn4aj1scYRNJPMJOymu1LV
nMQ3ssNy26yo6RQoxgcUdfgDM15Pr3HZusYuXpGenlrbDx0TAYpu1/zhnaC+frjPQDOXlxzI9nUR
s5/PIctRIfgl5MiZniMoSVGM28DKKyaX0WWJMb1sSmC6dyZjXCXFYzOp9gOjWb8Z/tnCplMsf85n
t/YeITStYNwqfyjYR64UANz9U6X+5gSMRomxRHD7sDz3ykaaAeip/kWoqGea+9fOXGzJAYlmXMo7
p1DSYXD5ziTGnx+GO9pRx1RSyI1T6+/Vi+bovBp6ldae1r4O9vEO3bDPVDmffL++er5iv0qco70F
h7qyPIHJtCxl7/ySLvB/BgMK8YO3cN2Raqygeg1Cjd8uSbkAYkCR4/SOM2Z1B4YHOYi5fxzPemP+
ssI1/VHS6raj33247fQHKIO8hr4QOjuVk6yiqR2mFu2U8smbR+M/fpW7OvM6ZLpkIQaCu6OkKF8x
f3ywmuHcJq7XBbwuG97jLqVfD/2bF0tBFMFow4tdnKMLu4pt0ekah/1vLq2tflmfHO3Vg6BFhTMk
aEz8UEtF7+1veH79QOpzeDh1tkmxEVLZW0GPpwMsd/BaEPIjfFl9+3ktAk7RD93ctP6nrKSeWVp9
R+9hWnsh9ymNlQR0s6i3NShb0IDampKCzrFccip1dnMIetYAzWnKwjfdx1Trnjoh+TSqp7oepTVq
qNkQhrgG5SHYBh9s+RnkIThyY7cS3pJiI4oVsJ0z8VA51sn4ij+BLzJN0kVuUly701r4B/8Imxm8
rEzH1KobhBUCRm4ifJs0i793Wjq/0ZwDjtRAAxp+Yvp6gPm+Z3DGfN3qZW3arG89ouBSNUT0WUjI
CHX/zPIwh+mV9UF07WUxd+lEWOkHoKD0RbHlCIEYmo2RNq+W7k1ysaAF+uJ3NKnbro5eavJQ7q80
rr1lwdNRMAc0BS8lAd2FrEevATaysGi9Dd+w91NSi9iAyWsRc3HUwH2baNm0IkXZs+3R0qSNxJ3+
rRZVozvaZoTo8FMikds3gJs2QiX+f5p2QUDpysiPhMDpEDhvW9gPsSpLzc9rV3i8nwf4IkP9tQbg
hNDY+tahIWgn2Us8A+X3fYHAsApg2wpuigyucQIDJ2g3jw5YiwDttYv7zsuAyru3RtAbl7wBGLMw
b8VZZH597WJ/dG9JVkm5CZjihhSTiGzUKAW2GRpjiWGBBow6rIKf498c/0oMQ3kobvzN//mdwSg/
rJP2sRJYO6+TDOZsB035pNcFglOEoPYHxmKhi92KY3XEK3i/Yg5uzkfW8MqRgWdH6+UEV+g299QO
dEwVwYoNK/5fqh8A10o7vTDaDqesL1hwc9FgQv/As0n7sD151N8XL4vkFbAySG5LKlgod8AKOJam
HdwKkvOJPau1Yx8SYVSZ2Em5Ef1rALEZtR4BqRaIxYlrPLTupqQvnSmsnH6W5v23dg+I95COtde8
AaDdo27zAFGwC7HCNrZxX8P1TpR7lctn+u2WdBdmdUXpZvzXNAJ9+VF+eNYApTADem3zqejecITp
EpDNcCSYcSw6Ujw0L7iEUR6uozcea8p/NsaaDOzyZIdXMQS23xNTc7YcU/j1BJCCQvdXGxl0GeBE
STJ6hp8QVtCNrnMB+x+qki+sVkzSbq66SuB5d7qOUIVzDsNMvxoIHxET8j6uBdg8FVrbqvIVXH2b
+Ydy4EeOiDhe5QK8EjFDHUJb656CJ1Txlsp0suFw4QDm0Rwiz0agPCjpAIAEJIhk8WL1tNHNcc2n
zP0ZCwivabuP4zs9n1jYgJvpAiO9ibEu10H34wVbI8hy2tFW1Zj0iafZGbVcXx/byB5jKJ6imPc9
6KB5b8kGJpkT/LwpJ4WMIKNaI/XOoENJZDRVP7RM1trEuZ8fH/7wsfja3dF8NU77Hi4QYQ5by5zs
gZWGhGR1fy66cD8zmPAV23jv1xeTqcZ052rayPyGqmAMBZ9f5v88uyXY8ebmxvEprBek6gj1cPKl
tZ7bAoBypfgUpalxGKxC3TdhmRNElkuitFSXt3xPLfvTZ6GKEpImiI8G0LYIwhyhh9eGn0wbOSpY
ntDoFVAyz9PKzZLXQlSxhOMrIdLlspCJTVTwG9iClEXsob2/Z7yd3Htv1ZlccBa/zI2PAbLqq+d0
FHfzcCaUsr8w2AT5es1OKCcSxziSFu9T1PmvJYD7kGzZXDKhvx0s+INvjtzM8NW/HGfl0lAvNq3M
HcaFblYIWRJqpc5bTX8ziVHmDazti3lCx0JcKEprlosHFgulmJyfUN3DJXfAcPfpVySmgdWY51TK
X4ZAlbL0TE8JbC4QxH4t4wr8G3H7eqj0wsdnYd+nSt3KgH6D61qQR/oA4BGA9dH/o15Yt74gMzuq
Fq4YumGuTTUb1KBfDUnEc5H6Ti7S3xqisuaJUe0DmEHSUbRfYD0jcyJUA22ybEmCYiLH+fsRTMsY
iPSJU6OFThU8mCdpOrxW9ZY71ZHR8Pu+pPb/vxiOnTVRaHnEUn12HZA0A1rK4BptQB3ZdSSRK7bG
hLD5eaUHwLHoaXcm20+nrxKQZ3zJlcZ7ZmF8FmAjG5ctZBiWWaxrUBpjaKSqrxGGhpdLlFaSfT8d
ODcbkvb136O+neuNDRKv13Ojqz4tgcOpNy2wlSBPRqWHCfZwB/QpDlefLANGnX24upLP3U9DLr+T
/cMvWVhXAvek/wOiGJGPLJ37D5lCqUo0KDbswugRJiw+l3a7fZ2eK45Spzh+C4H2Y86fx0909oAT
KmuCeptzl8wE+6iEgaUzn2c/juiiKzUlOaz8Eg9IrQKD6PMD6+Zkv+b7VxuOVkR/GiZRr52eRbFk
JQVEIC83QJ+uk32/B9DaYok84fJMs897xupxDr1aC6Z5B5IzTXMeDHm4wxDprC+NcSdXEi81IuG5
q0xgPrMFksgSG8uwH1Ggi5JAkkHWedR9nDH5p8KRJX30XcSS3dFl0ALthIYuyDb03RqaWN3OoeaJ
aD5YakbP1myqynuuEDYpVZzQbyPmvTKdf/PqMe2AeZ+DF+S7AoR3pTG688Y5HuuvO7vPTtELrcko
tQ0miS7Ss/87QCmDphU3VWuV/XanOXHnGEAvcn7H/PDin4sxVNvFnlo5Dx4iCG76Nz+RgLpdTYRc
BSPrKVdghwXAYhY19DWVzJ0/nbiiP2at24AqOSTK8ME89s9yODJSgT8f9KrSWYVQHyiumztzLa6R
ed/k4dkqnqp0u0FZ9qGoSQk45aiOS8EhTdXqCIOQDvu6yeBRDxhbcx18s9EmpYRQfXh/jvnLZHA3
xZHN/mdo3uMjnd90hSmc4ooHSu8GXn6JzOidWQECK1lkDtR2BKikArS/GaNwG4ZvMIPSMi83N5Af
AgFEEqFXRXzHtgFGJGBLjAi34ywWYt3A9sKriBHMe7G3ic88TtAnK84sw0uRLk7a8q23tCYZUujG
7t9xbuv7V2eWoMTwZZLWcGJJObxHFsFkGDa63pXhDtJTBCZe2gYgRPRdjrOIiNN+PM4dSqZnZnEo
2X+Q06RbFgdV+wYrGBtQTzLz91J0NZDj5XL0aEpR4n/NzsdSd9PqicumyHzWYSLQJuYsXSHFCf0V
A20NFs0OpWkHvkJmUQVDfhajRhlKTamaHOJVNjdGIjdVL8WjBNxQJCql/4clSab4xWGaxsqm2SnR
2JsWjayReUPJOsuqm7luHVTMzoKc9QuvoM34NVT5XzOXYPrHDUTfurnqnTI0G6ggFUOkQKe6LPkx
KQov996xz/vxMJO1jzHpjOVCUVh8mSndI27M20qLtukL3C98igXjOe3M4+vAKXIctu4M/fFZd1Oc
za09RK5B+d+zgTwQEIPLA0G5sOfJgXI0YAru5gzCv+bb8BEm+rW8LT/ybUa49SF1KGSbxDLJiae0
NXNDWx6v/Ot7WhscKLZxZFkh7uLqtU7reCGDSsEert8WFfjLY+9QVE4oROvuW6OucZJccqp9FG4v
Uk73jvi8DvXL3dRqs+WFebkNUZMn5iUUlAbiagNPFo/oaZz6SMBUkoxGDFvKA9D0plAfNdOGUa7X
iL78IXWfMrSLup2PfeTaNrgzKwGz5KUo2kUbglAnKfiTkKzKT4PhL2ycbtsqjUetgop5bPUN2Icl
+yqu8GOHLC4++2SvZh7XFC1FEzJRbK6TFgNpfzFmCK61tnbGtrWBlCidT4R4TU1M1DMfO9cfjr4K
eTQR/f9v1s4q7Ih6TeB5vonYu82ZTXWfTVoPFTI2wwwzFr5NHmU7DM+UAUR77NkSh17K82pGJYOE
WqhbAYWJFRaUX0Ew3wOHrU+oqQnJ3Zq1954VzCWBn3PsWcO6qgljdxE/d1hkEsMMyX79FKQpwptN
oy3bcuW5EaPIlh0TuZtIhx6JPlEOExyzNzbdod4g5JELfzgRAfgHXcevfaC1UpPZ25EdOi+qTdwS
4MTiyMdEu3WCui0pgcPnASmGEVMIaAYvuRERw0wD/ueZqdZU8JKykJeb5EVLODYaPb+iJXsujSRV
Pi4A4o0pL7a3BGvrpOCT/c+GdSJsO7Wd0yfQXbI6DWqBtDjl9F1DU4++F2pfX0MdKKQsbXRwAouv
vSbqJe+Jo4fS7BhLzUCI/NPhYkW6V597BH4inX5SGcCRS3hE7Lmh17ZP0Yk1/cZtBpQapUXPDxDn
JVQuslkHjkyDuDrrAogGWZy5BmB+sVK8ZeaXcdEztaKA3DYGXB55I1cKMgzvjqrTuw9k3V7dML0g
yPTQnS/6bY1EwcVuJqhMNi87rGnNsJhFTtxvea2H3435GpmYuuS6NLztcBSXLM5b38K+/dcGGfHF
OVghMNEOGXVCOP0z/tM9Oe4cMN6LwY9SkPbIOPeYqFYQSb1gFY5Nx8N8Le8r66DhimmQwj9BO/xL
bs2eur+M3vvrVyMOk/4JqaVdqY6QIFtoSwbRLPKf8WY+YOYvnpR1Fc+NG32iYHv0oKuNDHBwkJYT
uANxHyX+dyEOm3s5XEQgGCgcSrVRLi14l8rZ2uWT7bGupgxkzl72lXWW51/mKn3VL21H9+GazGj+
rmymhaRcDMbWSpZh4Ecx0RhLrMbo3fPTz+RJHkqMg7bL9a10KziNP3Fgtf6pvAOCsq2tpoCkX/Of
oWMbNq1oO48YvQLcbx+YOBAhOr1PVcmxS71S9L+yndUFoBBbdPO5kdz3DtXkkPxJ1GOfr2EKWT0e
/yOEGfV6/fLexbCY5LKCbVCgpFW9W8JEKf86IkJPKNedogiW0jM/l0Rq37ThvoSfRR6nCVw1G7kY
aGyuQSsApNbFpN3ybHOWRtpiGkFlYpzOFBnMaW12gSehOWG6IacbNjDWCBoyCBkiYbtWmubYNThW
+3CZaUnimTIZz/UgOLZ823JFwLCpxGS3IRf7+4unA58s5FppSMKdcmCslOrMG1XVlT0/377+ytkK
WtbXY9qkSILpb7i4EPVsQBc+5Ty+7E6InPQQe4c3tIT7ZOyI9l67PrZ0iDS+vypiqT8IiCPSAOJO
eVsVVlsFKHeXOIyuUc1SG9yD8kmT47e1Hc73LYaVaMLGZqsXelbjFfPKLefhxuuio48akHMjfMw5
ymKThEDjQ5iV611xWUYGKzgy+PC4ex3i60FUxd+n+JzNMD82mwEtpZr/u/GiF3rDcjjgL9hSt9Dp
qcSEJA2uhq7yMnaZ/z3zaKtxf0fOJ9YR//HVADc2v/rEgDdUXuBlsXdlVzfna2iR6jgj0OsmGbog
9GFcNJR4u3Xh881ikQTJ7USCwklpndeWiUo2AXUkHs0qu4F+r7pjzGzcHSwRJHqXLblK1TxNJdZ3
ie76AKFeERrCo7UOT/zDCwgKSSCKeCf+1prKKp3pesblfD6Ezqvf0jRSEEm8FtfgHhIBIu66zgxw
17/xtkj4xraa3OU1HRn4ON2k3OQKLHlAtgDDMdcpdQB9ErMxsGzKbsnPCUnOg0QhCpr1rXd/crve
/rfqaMjs3I1RFr8Peto2ornnW6xmV1LMhhIEDJA1wyMmUnkGjgEeH2Bbhw8Xi4BoFtsoz0j4zVm4
JbrLQGRKfsv2RP+n58qALz3PcAGe1IkLk1yO+7QevMfTQuMG0TXsND36dyviylRGEBpZiCz7qGxn
ZXwTkvGXBGIJMVTaQqSIUq7LBFhqNblHue3jhaMx5/hWKJzpjzKN3XZO/k4JXXMR5+yNnpFMzPdr
1aU7aUJx3VX52cu7j6IhaVPFo9bUkHV3wQuSIHuYFbXjBfnzoHDENIb3Jx31xL/wqqf1cFxLWsPv
q1SfAAx+cnVUAYyWCf9P1nj2zc+liTp0MJ46zAc7vkd4RDBDDvakYbwdSri+erR+/Kgukm2YTumC
IKtOTbrsE++TI+QpSlPlEZPdHT2hRwzXWNlPeX9M+2aqKjIE+LP57Ucblj2BlP4tCSHQkgnG7H3t
qqIx8atXonkriuodu+H3IVIDP/SMcvkrSu3BxfjTXyJkjWf2v4eL1AEzqurnikLkpHbO0nD0wh0J
dGZJXsrk68TXCIRVXcV1sta9SmjkgGOeZ/miqqfuv61FxO0FSSjCiUZAHjX01JvBtRP1gEwCvVaJ
Sq5mxlqafi1tb255/hzp+Ke+9LHx798tzcugxHvQFWSpKpUYMPl2z4Dnoa0BGWP0QDxZMtV3pjCa
BdJikRiUeuAKVrw114yxEzk30mAB3ekf6yqb0cB85kjYLzPiHR5BtmydINFES1Gp0eCKqX2b+GAa
9RSq5peutQRXfzV6VLKdt2HrsHs3l85Hiji6ZMbZtnsia4Tj5aetsFCw4pStzps3KEJqZ3djdoIf
UYIBU6EhsvyuK1npzwLWTvEEpMjrRvmlg3P+zdgAuze9tyxjPxcwxoFTW4ePlKyzniJpTiECtD8F
ehO+xyTfzlM/z7N0neYdt61ANqiYv/STusr9ffooLQi4Ye0A42kJyb7rokfzAYB11imET+Pi3wrP
YCHy2IMx+q9mrKnmWF/d19Vfm92sLrhbSGz21eIMtJBZoOgeijOmhOZK2aVScvy2tzadI9nlppid
goRd957C80eBgPd5jFNiURgyYG3QE27s3pv3XzFze5YJhbiKm1KmZvOnhg/wWrJjXs+GQ3Pc25x4
gjvc87zsPx2dNmYhvirsXSqpxNbCKWnGTdCmby2ucDDVXzXFdkv1QFXgzotgexSu6gmdxucA4GNB
BP8L2rNGTHQUMTm2duzxvROHZ2iUzk4vKMCyy1z/rSKRl1DHZ6VrJhqEVfqYWa6Xm4WhyFZ/08O/
BpuiCRVXagsdGnHcNLpTs7GbVjRx0LGyeKgcE6BmkIDta76mjTHrXx+CIHi5WbFQ632HYC0Z977s
tadFuIkAY+nJaIkTx67Zv+gULYmG5uqGQyPOZWnAEXH5+Vf270jht4s7hlm08Nl4s+J1C+vfLMLQ
3SzwD26VFeH4ExN5pi8HHPe8p112Uskz7BmYO8vZJYvS+egF0YSgPbvLrtWj/NQ9ppZkpGR+2p+L
c+dRmPLTj0HYfeHSFTiUndswZ/e3rQaTfW6P5ziGzfcg0Bn1MfIS0NFI8yzOF3Xd9mvG+QotT0Dn
8aTCQICNonI5r6i67WPrZAU+QQBh+4WOyGzswc1xpS4XmJkRg/mqiMBAADYwaBdPrdBoeomqcKAn
z/+xvhSM3e5VqMp4Wnev8OUsEPzJH1DPoNrOq+cWYgqIGSzIFIXTk1AQsVuIzimVa2qtGj7jVtTU
pZ7nUL3FcehQonUcpWNas/E8CDEMqmh16YCAcK78jV23Qh5Qgz7GKpnWCRhF/N+UIjonDRUBrR4Y
eBaSB9wVlKcCdKtYr9N5b6+5pLwRBUQHcDNKuGatpwPCAIqE+Q4GohqJpMybktD7p4gJVIWlAAcI
gIq3Y04zyUyLyCQSzqafDArXUt2HYzd8F+no7w2tmWrFOfmWTetVKCvtDe8fPvP+G7nP18HcNYcU
0iJ5IXz+frzfmnyIE12BCNIT8oc2vKL1v8qw6wZAvXQBL8Ona7dlML58xVnPWp7ksyvYyxGhP7Ko
zxJQQGZc5BU851j+uKepBxjEtB2NbVbDlNlLDdMinoRsOIicsqCTKgsQH0PesUSyWAHpqyq41XeA
JaBQSW+1lMFj9Qj9Zmxz6oR4A/ieaFhnl+gzCkfGaJ4VRi45NZ47NjXAjOVXI4qbIf8zClxWoyMT
VseuzR2h8thfHCsNbo0cJNLN7FEPWJHz8N/vMF1aBapFngBALg7tTLVYhXIkESnUoRW0zD+rMfwU
AMq2Pwh78VtlvDq4I8lnoNCY+spaOvfDYLCxasOghla8Mkq0yNDbKP/HsRnhzZeZzRhQqy1pkQU6
uL6iL9LiAr1eRMY8LtRdo+i7dDtrot8d8sXHlTn7tgSIFTcw4BA++AHuF5J/W5XX1nT6aL6VsaK3
1M1mLMPPr9ippOKmrSRByQ4/HpT6ZZgppVjtsTNiB4tpbsWTfIbJVygpiEDIEIblQhHsK1FenHbT
qBA4022d4mPNyVznyzZM1aYEVG+RgdMoWhVr8CULqlHMMsg8h/+v+sOgllY6ao3X1M1RpqJUdLmU
vwXXB8rpnbvnxOPrO9Fp0aYHDfCYFkmcgTi8auNLANrJuqzIjxnWNtp5V7Xver5RFRQUqavq+eGi
4Mk3zeeVO4kbzG2qBNHXXmP1Avr1OmDHd9EGsJhJGj7C53KBI3PoP28FdD8fA9ufhOAedXepfrkq
fvLC89vbQZXNbdaIlNcaZHmMIF2B7Vw12JsR5A4WeY9zs29zUGInzxFncbR8hsH5T1LqXN0AlvV1
s+lH/NdAQxv5wd68vdcK/1i0yRNGzXsvpJfS3x9ebHq+9AwojT13yunH+HTw+bB5fwzo7Tr89JoL
++Xb5Wqw6MqiMouwR+UJ+g2ry/ARqL2G+5HGlPAjkRqWIS4cOw0kZONBOKK5faTJYRA7KDZEWKWr
E4ByaKBPrDnzdRuf4WLyiaQgW/OiBQWYcvYP0FVBXAFgPt0ySiZDqpum6BmyQ4te6NNddHLStcKE
bkYJmALHkergtO+Blio0YmR23aBXNaX75APDQCktnb7dJwBSxNZ12QpwET2MAE9bjfqdhefBOlPu
kAbdyFbW6ilLbBIsecDhRcQbYEpOikCelluSmhzQIg89kYFhxw1q6y1AKndR7AhLDCSUUJlX4xj9
wQEkQRg8cgq++PQ+4RGBh2hrIJWrzu+wA8k3T3NILKLyVCUyb4y8O4lmxk/qAdPE9Waya+yzw8Hy
O2rJ3qHMiQc4exr55pm22MzzTImKx9HcPheH2r0Yk7i815ClM5dAIBh8EJFr6jMyy0AzjYBmfCnB
XVKDTrMTrdhIiHPv4Efz6t3gJePGbi9dn68DveFdrFkmT6bAT5c+2O+1qoa5ZPAYRBI8833M/auU
oCtw8tEYmCEVifks1z6eSdfYkb67apQcpPZzH5olmrXHGx06X2Ygguvq2Ug/5zmMlNec6ZPpplVx
GaD+XjBdB3o0NgtJPNYx7FA8IinaoFhrRgrBomQISvokITqZXXe50cynOYJyRlTR3ZW069QvirDp
TwQrYsJ1EQsm0mIvtWVkvb7zHmOYuuB8JgTOf6wFSB1+A+LgiN9bfYV+3kF+Hl3DJQcR8Sk6SIbZ
rUIdAoW8VOflOaOJ0k66KoXPN95jDXFmLNTY6A1u0LCbxloWHtPmtmxB0Ar/eAVwi7rfQ1U6+bww
rdW9BjtDnHL9EgaX2k2dWDQkulkGzBSePCAJecXhRjBviM6srkaWxaoaJu9mReSHT5pAkeABUMdX
gdYoT73Jvfvc6M5zk1fMrzi21+0b/NTdFnhMz2ACyOcsAzucyC/8fEPeC+vRQRsJV5UMPw0z0iyR
/z1t1fY1SH1TjOqeIu1/lRgGP/TM3tZLWTsalIW1GRLWYFjowvE5G/dzEquiH8xMK2ikewoZWO2s
aeQm00/C2Ys/dkj05jo+Cz7dAO/HHUrbNqxzHfP8AqSDYHZGqxdsnTfpELoY7QJD5TAKBFQHkvcm
b62Tyg/A2fvd72QX1c8VpsS1VM7eoKqg4UBkSwqwTr3lwqy6uSU7ihRpRli7nsTIJOWMO5Qw7sBn
9SgO5GD7utX1hxtCBu7+B8sQAOa9K+tfhnoT0ZRECA93rbkT1fTD4VOJ1qOrrylb0OhC9lEeEwCW
ov8wRmdsrAzJ3UG0c5lXbzo+FNmbshlKhy3hb+Vd1bkCeDnztQvVIoVyZkGo14omyj9Z+X/Dw0Ts
mO6WBbhk5NAm/SphPmki4tTvKsMBSzSYPr8ObLWKZj4ewcdGh3DYQW4Fx3Ihqc3lslg4vHuVYjHE
9toS9+GmH1zUn1TSkc/EUMZd93OXY6MxskT2oFzYs/2tB/QPfFSG7N27gQGvC201ki/9iANap9un
IZW11Gs0Q7JYI/PWt7heiUe3rHDzIYMZj81cvhrHZOAYi1bBcrDr2bzUDsU/RJQdctLPilHNWixi
bCCS53c8LmtDLVxKa3/sU2H453woM5Ck6yGLvDXfcGHUVjhTR0DapvOf5a9F4lpYWNXEBOOBuGA+
WUInB/DTDWA36s80ftnu4UEugva2IcNk0sq0wIpvcPFbNhA+U0jOPB8zflJvvvXnx45M7ijlXgG9
QTg80crbjJsVJnkreu4gbID2fvEJvly+pKnk6EPARINkVb6lBTMqpnl7+TQY/dSzEAE/q6XaOCvk
QATc3OLqNJUhDsi8WFftn8agioTTZiQNqg2UKMnKoJdbLUzhHT1K1P0HQp+uaMH3psF8ZOI29Ekw
V9bpQFGNKCeJv1JYJOhnnH2Ta9xcEhcwVEGx1Hp0iW8mZq5wP7GxeXmrOLXygmObPD1fFwkrEYuc
YoED5o/F3ckzaq8FRWWqxIW6u277vNPAK1rfuis0Xt+HwgZSSlnoqSA3cd/7wBGvuCgbhhgn4kNj
igNspxwTx6oJLkMt5sO6SjyBnWGbH+956dBcXraqSo6f7Gmve2Ox0ZZsJJiGU7ZTC4XZUxiJn4qv
yoiFO2b09YlP6iVIopBdUfcbwy3etz3C6D8/p2+sOoyOfCIRuxONJgk2kEDVwZOtQlVOl5d31rAG
nEardgxhkUmG8ukcNq2TUKyq4G3mepRTRaxvewwUybi0KO/QAvQ6IEKs/fEYTixRkjiPedYv0W7Q
0f3amjhhVyp+8ZFyjzWv7+RwpZhD7Y6ipkifsqdHoTUw51cnNoTQUqh/AqPU/VRvlbB8Liw6VsTs
9SCSI27dgEjNEkj2sM+GFaDIAESN+HvtefKdPV9zCzcbRrGL1XpvPJjlVy8fHf7+YGsecNtsurCP
J3amGoe2BonxHjaB4hIY00HVeYVjC0gcESTOfaMj4W6SGcw1jGOc4M89NyKi3GdW9bNaWFahbKaA
AxqaRJ2eg1s5PulaLVmHTxHWSXZ+k8S2fpO7DsqbToB1KBxHHSSRTrfYDIgZJeXZKQ8HsBMO8JVF
1CcANxsgFG41DfL3saTD0oUDn+OG4HIyq7ijv99IctiTkAHo8jfPwaQrPmcFp/BlFfIxUj0Ytcwc
UesIJPR/TYXm2aQY9hlQLzgERQNJniUQDSqxpk2y/wf3Rwvnne8j9LtVLhgNU3ZoK6EHcXaQ5Rf8
JSNdV+3LR+pte/Jy0gTdQSbE66LXEZFWqHfnwBCgCX5VrzAadtcpg4CGbH+j84K2eusDR+cLxeF7
vIFbEvPqqxyURoLwn1lL2u37cffJuQF3Ejjte7m2K/UhP0AjVkjro88OdUVFgQACxrOJJcT/P4rc
+0HIvHtBQiKo61sO68Mi0kaeJ3MdUA8JUV9A6byAe1gBcaYybGEZgQ5Pj37iazQ074wrWLk9xbDm
p38xAZtEqF0up2z5tRQjNo9PzKcS/mv2fWwYvASTet1CmZe9/buBOlGwjlJ6jnc0T6myHxHBbV2v
zspDLfP04u/6KXLFb7ZR4AERsYj5g0QUZ1ctObLD2t9/rQqlOk9jXxLYxL23SYRh+ils4+IDpIhR
d0WOboiEuDyB3Pza+y3YVCFG+cW3xjP9Gh2AnEtKurCaESmteIFb3ZVOAFcLl+t8w5Cmu8dyXbQz
rBxFkSRE62/4Y0+KRlSqOy5PYpFUdXG5GTUgP2uF8tqoCLdXFrbKTxVRf5UPCOLyA/IYzhaRdMLV
js/Q7unwuCu1ydoIa+n+gTvfj8VbPHV/qb7tkuDGquafBQoXS1JBMc5LsZg+iiEWp7Z0FEuIw6kv
14so29HkP4lQQqwbtNS8qygzgWGqNEyapCsCRpz/8KnYeDTDtaQ+56SM7QF/3YxZTn6mayTw7FoA
32oIpP0RvME7hfvXmqX+JzntVMsyiFdTczUQnJSKdCOw0CEvtg1KqkSRZB0gxowB0NEb9O+VcxAQ
RdjixFLuFHW3/g0U9WZDKxMCI55hegVkNL7Gj0PEPcH6H2L3GC5i5P3E8+bnUkSBmOfv0yQgmPwb
E18UNK5eDEPzyQOi5b7V73jRjkmIXiZbBz5b+jTG5v5lImW3tcA1rOrkcRwoSrUwedtXrljFvzus
fsY+52R2LMVyqH8+Hd5pxxodKI/PvetYYY/4VCVv6dZgT470CPI4ZzCJtgs2Sjsq8fe4tU3ajHWJ
vtyXYmDXzLvsHJvLICuQRWJksxNcnZ86aK5BMZEiPXAYwpLMPVkDhf0+tpSyYHU8fT7K4qHTkOzm
j1Sx+HlBKoCIcnyC0FQuLCNXmoGJBPzG1z1GPHPoKlVr4D6NbxAaKQaDS5e0tQN40KTi5Byt6H/v
FY01Qve3jDRWumgxIkMKOnab4QOXd6mnNFUkCZoqvn4SOjVV/o/kZf7+N0niu18J/dM1B4wD/FHf
edCK1194NtQeSnWZ59oekOVgJAVLpRu6P3Bo6Jchsz5PWkZlpf/j3wOKa3tQdy5nJaJFo/kmSQ5h
gLCnytYgz8apl5CiQ8N8tPYDDYqzYNx2tHA/xOQ7IFlVgMLifBBJrg248BMMPPO+UDvvpJib3LnO
9OwOgtnocpGYA6L42iAcBwpY9nJ/HWSte8tAI0PzOg68EHOg2LinvL9TPGY05bvAuHyqT+6YRXAg
yyVs4RUXyBY8wlYpiJ88oMqM04IdQavkzm7oiag4qWZZgperY/3zw7tBikllJt4bYkvYJ8I8seLC
hOkCfIrIcZcR7Ua2n6NZDSyPbZv+l7JUcRrl9SwSi8vQ7XBuJs17rMIhsdsPY8jqhBWlfL7gMYLg
r/JC1mX9gG122iUICyc0DWdtHqlW9R8s5f9nMF6av/VlRrNElfizAkexTfyGj8bRH3Sg41ZENs8L
FdZVH3dEUY7mLNVlncQDFu7dd2i/uw++y7qV/YBWASB6P+Smd6aiq1MrvvgFZRmGAXSVs4KPhyDo
w6/2JOmH2PHYhTzIiWAhrXBecm60nS516DHogWVGD33IRSVd0yoC0ar90nalNhWC6+wDq4Q0x83h
cKpD7RbfvtvEO4RNGywp1202y8KBbWTF0FEkiqNvcM7oQUTYXWJsjV9h48lCrJcJ7SFzutLoAHXR
MHKk1qjiHBZb3Q0hapvqXIXkCWkkdhpadzxriK8tRp5RFJf798agfEtKEjqtxZR8rPGPyRKmt2XO
jjyV2iQqqkdjBaybtQ91yX400H7LNcNmIOmyGYhJ7j3u7LjM+PH6as+nEIgoUzu1V7/ALXP+ZlIC
pJdn6R7SlOp9D0iYNcDWea/i4xjy+qggwy2KvIqB58CG679jAn0/Ow7Xy3AUHg+V2P0NCTtadYbh
9sT8aq+xlsSJ71vsx/x0M404Mj/FRAcjXPhf/JD7TOfQngK1bi8jCgfkrcwPuFgYpJWcFEIKXFmK
LuHwpCJoeWwQ4/7nvNBexPgASNfH8W9WbEzXzcEHDxkg+n3xP+nLcyv58J5PnXrBkdoQMuEmEu+9
k9J2gLeRt5Mw5vUwkaaCuZd8bFdrGbRd+Lrg9rlsH9JHSi89zKxUbQ5UMFBGgArYIPhhXzDrFFxr
uahzkJa91B5/6TNHTyUJz+6zIAwQvQLIrhiS6gXMz3v+NOIn+nnzhZcACPT7Dl4MdtyYxNIyg7wq
bfTP2Ed/h5+qgAT6Og5nd7aVM6ZjcLHN2S9G9fHUBuNPUKro9KE51BYOrovATBCvuWigeqtsD22Y
sWeNUzmZ9KnpHZTXC29x/9eY7JjKH6706gvoDU1eoNowZKqAqldYoPMGjRBkW5sV5/ym7rUI+9ME
iK14osXS3Vmgo7c7wkfA69cQ1rp3xjSvzStvLOTIB69VI68qbDWB+34kFEguEpkG1qQXKPyMGbYQ
vQJKVpuk2Ywxq0OqpQw9uD/N5k0Fmo3y2ohsD5oU/y/bBsCaZkiveFXDNMqajX+b831LV22Wgt8q
f9U68BSFU651Plq2aKmimD9Bbr3GEMSDrUkTQeFt5d3B1I5FegFs0tBM0Rk2bdOveh058GZ5pnep
m+jkj1l7RMt8yz2Qn2Y7gjbpEwS4uyY27AUaV+dA9iwxRscXboPTPNMjZuMLZwSe0njp2oysZ/+p
LziRh+83MyP2qdEoDTKApnQR/dLosTxcu20ddEk3KHAj9Z0I5qhlbOHN/CavrBUXF8PZ7HeyF6R+
/1Eq0D9QRVdr+SFqA9gbBnxLpxuJl8mXUERQtOwDEkSagQYJCg3nt9K7d4o+dymqcbn3mHvManPV
jOyVzyhWPecUA2Q/tEU4IA1oeEyr06JrR9HuSJ5LLQhWFRcZkhOFwN6JZ0M/r66caWVEZm3G5zyq
27AtAT/PHEOYVyD1wl/arnoUhHvCigKEIoEQ+89hVcx6bkTmjvpEqCzbydmWW/t8dvVCEVNPa9l3
+JtlEsGhomsjVn6CyNfRBSfDao+DUW/zfHthRZ+V9BNFTO0itwC6m8O+EymMTxo4Pi3lEs+9O7jw
7wJg6uq7hImhRmle/VwsIqW6N/N0DX2hUp8ijckYd7xmm7U/OVVBlP/LoQcWjPPmmCAZIiwfRYMG
8icpKDEios9A2NZ5topzi9isbVYD91ClePg+g8siv8K7sh3A3pcJ7djbKBJ2ibNfjG58wgWQI4CS
zcTLVRdhi2liykwHPwaAYnHfhUUBgCsUpre8csvk6KKuOKzyX//4Aqr0ituD8m7ChNHBpmfZcYGH
sdbfpigDKhWI8iONohdyDVVwN1xiABBmAk/XqZvkBhIvdECIpcPODu0EQ+0MU4gLw4sIY9MHrj/5
GaMf9xwNs/BT0CRgxYndlx3uwtOWWLhHPhaTBgxa+8ADzQ71r5PNzXPPKKGNl3g65+ZnsKkuvz39
ImjrHj0BDU9hZzuo5eY1DrDD9PWN3VUsm5SIo7YGpNWpojdWvAURW8tk8auOlRLVGyLRCLI24/7X
rIBKGlX6uJE86sm+aCGWXfJ1g3/ZCfgzrryWfuzm7MzpeyY0ocUSXYYJ8xO/DsHlqNr9L0YFuSx3
8gyzPI2A3fVNobdrMzpO6aZxSm+IpEN6cPgRNUmKuP/enObna0hsrQsxjRbPSd51Toc98+m4cs3D
wjafa23tvAY8HWEmbJYyNxgqsQRAEPC21tYZrPnsWS3ASLEHPVZizPapREUU+Vuamq2HkGhRNnwV
wu6CNOnE16aya/R9TFKA+/FhKc82OVZhBYalEoZuftt5bChHHCxNQJYV8J5lyZO//sKaoXoz5pHW
qnDkSFF/3e4YaM6JLtrKa2r3UFenwAKoPmmWQV+bqxpgO8Ss2THRGlWTQreoPjkWgwwlYWwhLchi
3WMOHREpJpJKXXcaG/yiTARBq01N4dp+JjZ6lGuoo9tbd6cudB13AzaGj9HTCW8eKuRdF3NzYPiV
A5qEBTu5J3cyoAXD9y7YxEt4ItqfANsRUF8KH7dQqmclqD4ZJaoORy/KCGb+UZHKWYg0eZZ+n6ZI
Nkh+FWNweXH6MAlYOcpu/xaS6b2W6sPA21Qq+QhE/9M0fw7DnNeS6Mj4H8S88EA3PcaNYenBuOnU
4mobMVcLyHkLvePtTJB5OzY4qvSd9FXDDWf76k1HZAvPeEK7TdApKwkrVBZJSYtYbvBRYk4BgAk1
JrJG2k1KtuwvoT5FnZjKTT6I0FWKGdmEg9TG7Lyr9l7C4lP2FM8MHTny0PnHoseHTixYneQ9Er1o
F3TqG29xkcB7aWWN4oxlFKk98IHzE2cesf6J8dJREwQlSoglIYBKWAXQd6s0IZImh5UXGn2m6e+I
lGI2uaSvb8fiYWZrp9xApcPf4xjarATDMmciPcXsnhIovk9oKP5bYM14DQe6eMRA1hmY1NCccrWg
slLKzoykQOMal/pM7YLVQDA0BOhUmQqMeMlmFK+6AYqwncWJG8H6W49ulhjVaJGfCuXWt4lUP4nJ
Qfs0sale6Bsen+EkcFuDhQniOW1jo6C8FjqcldZ+e8PzeQg8mH5fibb30Yw+RviRMmfHmgNspnV/
nmbPB1Z0DlRLo6pytyVMzppcQZtxXLw7urMklvAp6xTJDJyw3E0+r05BIKkSwkUpPw9RuFnLpW1C
YkrG1E+4orj7PKL95w7W0aQj7UKlJ5Aq6UPtYIQNNIZ+0VRCDb2on8hkS04S23hJQ5bRVufvtPJ0
l7A46sTcqKA5UqQn8XAgODX1wCKsGqd8rPzbtLsHOCMeXEzK03kXMgphfKHw2NVg0/UMR9XkdUKJ
AuVB52TAKjGE8aQPq4oUkzqXsI8kUz2prM14Xupq8P1X5WAopBqcRS7nZ2/VnccQzNxr4GRteGPz
LBDEWzAXZOBCHn8dtETHEkoggTt4Js3ZjNXMSBdIG139cIlRkhZSpiPd0rtLvJMTThfQnUMzkAAm
JVfbCA81xVDR/NO8CH3/Hxtdo+U7tmPBwD27vawmCsU21XSd+ZTDeKNdzWtRpL8o986F4yeZObkd
1T14kUaE9MQ72xhkg0tAOuxgzy24Bllke8GICm+OS/QjmDMpDW+Y8mlkvtT1cStZDtRmTAkNkeMT
CuX7GoYCCoJTvXGrI2/XJfz9JMoFr6aulpwAuckmFVoHEwH/kaknDAEi6QGZaVYfkvVGV4NXV8aC
rbaPzj05pCNjm/Tdc6Ag9fbJUY/tZ7K+7RUSUrvQezP6rQYkxxQz6wgpBVvSdl3yP8Mf4wj8A2af
ST+Nkv+3HFemdzXgewi/+c04FTLZ03sVmPNXf73QGr/qSf0pqsPpckMbAvB39kSfU8iYpp+QPNo6
mNfHA3FUN7+zEnH3S0AxFVaQIFrqewp1se01+KilrjJPQxkMiPLLibe27kbpQO6czw1nbqCq57sV
NEDpyLgW/OPzzoAcDWSZVotbCKaobmJx2VdBwXRh83JBdHtkYLlJTiDv2e437AsIRP7tgVLFf0oo
D4Kc6SX441Vm+W0127P40rggIl6ksGItJonMKCoxMv4Ky4DAy1Gm+c9HhVuCY9Z3sTDxf46Nuhs6
dDPJREijJZDKLN6H7nBg57fwh1lbiddGDO6VZpQeET2NrGbeRypPzc/irec/Hq+tY06RZkJNUfqS
kRojv586YfAlrSzRrIVO3W4uAQenYQ+ADJttViqw+B8bYbxYeWbqfmT6o9HYKW+uXYEO1u76xD18
c6yduJCAKL5fyeBN92GxIrbb1HmomB21LrVmCPB+qzEa6/TIUxUoVyleRJkMzPa31atFXxKKjrqb
70R4cFt0BrAAZ4J5OBs/TB2XwGo8mqMt9AAoijn1gAFs9Rr/QFIWb4bk6e8M6S+PhVcThulfVbg3
IYXrgyNYx4nWLRVbNGXcFQvFqC9osWDFr74QOo9uLxYRq3oFvl3e0MscsLVjyFGJqkNIpAOssK3l
mmR0ANjzYpPjV/0khqLuygxgAxPQGHeu9dHHGaq6sgW0GbCiDcHkB3ALLSonDejp/gu2wckAEqLe
Fgy40OwOwHHgfc2cnDMuWU2y7PsirkhxrDpwzSHQ9FVWo34tJJy9xycbfYTwBMPOF6HZM4BkJkLE
i4ct+LeZSqCuoBCyCq1wS8RJKsdlKoFYcGx5V3AgkTczc4gg6cgdOd3i51FC64AWdhD/5N4/MwzC
nsW37dY+5qiMBkCutNqoS1m3KwMeMuUN7oS7Oqw6k17f+oWrayCrOAqqcM/Czin0gBm1IlgNNytt
XdeVWonxMMvJzIc5Jcfe5lZOXclyqDoHgPDfWPuNqyfe/OtJrFcvQ7GA0GTVDJ5fbbpKyw7z9H+1
EGveBCbDDDwEDbQEO+kNNr9uP4bJpkVuEOYvpGfVSCykmoJZMdVtV9Lljrn4Szo80NtQNBE3+z++
yeJBUuhtrhsDft8QXl/JAYjUW7o/v5nWY83TNTKX61pO8TYCQvxtgQ5BsAKFlA0m9kDPdi50FUG6
vudSYb7NMfdrKgAy9JuqWit92lV3AFLxvjaUlFWdLr5kOqv4p6AyRHlFVfs+U24ca2AojVFPQNMd
M4qJPG0KWwUB48H8VjrVr/l/yEvkPASTU6lcwDr6faI+jHk0HVrBciSqcgonRXqvatyB9MmrtOjI
bNzqD62Oi9Dh2ZVEkWZqoI3LGBCLbzE0UNO8CwXX0LRyBmU6PtFiF3uCr4qs3A+qeIGhOriOM7RU
1HIUfzOGHu78o3nW03B5cZZVzSioKnbr5LlCepm7ChMwjbHiQdEFA5ZHBJfl6/nTVuy4KkKCk8Rd
/yo0AJcyuEf2BSQNriOGtNjjsYXPHU7D4enoWNpCPb1LHd3PfD4Lmz4X0OxarXYoK+WycDTe/0Ph
UUGKYVx03x4UsBKYT6W6jDuIi3gEgMPtJio7c+jvWJRk7DZ5Hhr83K166RVCaBhWYcnMfQVzJVPE
R99Nk4iizTPuky5ROof+MVk413ttfo/sC+cO5JuiZHk1I3hO9zSv0u2Nd4xF1wV+2FtVkqbs9iqF
mu4l0KPtqoAe73QzeFp4zRXLyLvaG63zhc+BKjNV+qbL5hfhdJ/a8bEwvV687bzmxxls4rYQR3a6
xVL2oPFQubA3peFkfNiV6SJf6RDQqD8D505seWEyf1nAqJqkkxlvNpV1z8JWWA6ij8clVmvwF56P
GZN4YGDVXGwYVtwaLtvK+EGsO11Oqdqu32dDojeaPy8FxOXBmRnIMj6Uzmv9EMZ77rzLjUOJYC1z
SYImAiYOaLesrTOrXcIZ4pn/GWx4mw2aVJQ9GF53jxiKXD4qI8DPYZZwb6kvZAW8U/OqPjcQtfuK
eUhyInh2aMwbfhbFnGMVBl5miwG7/YUhYg1q9ulLC7hyxHhIEJZaUOeb3VTazszF/MwqogcSVCIs
q9f0XwPtm0BpbD+ndmFQGVXM5iZGP424eUNy57uzfGlbktdCj3rcL5o5GuGZZ86egIcNjM35oJzz
oJL6wQTAgsDZmyssh7SwHjjueh/xpRfq2Q2ilA6D5gp/YJqUPgbb+0spCgJ2tUH25/ndsi3x0yeQ
IR042F2FILO9uC4U0Ju2oXFnuI9KBCeBNAQYTFk7FoUwM9eYeb3Rkt9r30+MMkx0F3d77Kb7IPYJ
ftCXTu74DScxMNQyI0WvWqJA6B6ZLZJ9TwqLTGlB+aIyoFNHDfC61LnkODhdLwatH1J5jbY7w81g
7PRoNXzsUl92hXQ4ehgTt6Sf2ua13A7Zjl1cCxMsj07M7DtuWI4bGDxhTyyrxlydUZYkJeelgKxz
AEZW2H+6dZZAENfIzGafyiYx1hr6vyZZ/tub1TCxcT8WgqZrnN2gh0f/0UEOLovjXMxHQiRwNFl/
1u3nJIWL+fbw1eBSdIHzdshaZPvEes4Dd56mRdIvAC1FYvAelbkdSV9tYRbYHCkEw4Ctqs5lMPJt
AcHbl1pZ2aa+FB45LiBw0qBAxOsnvXF3Ri3h8SGER8yIyqWbz2RJkPLvceYnAIQCo5Md9hQ8p4vV
qWBOCZr373jhUtG596J82IcnsfiGb87FariiKnGKJrb4Y5K+74XO4+l6zwPJh4jXV6scxm5DYVsf
JNYQZ1+vwjNGl0dAt30aed2WNtd7VT9oXALlV6FUbkp5X4tQG1lS4conDT4R6ER//3qbj+uPxsoh
PiScVQJY+siBXj5P9QXtGXguxUGKS58EsoT9NNBdPl3YweyrjhzBsPY0Di/DKFqLEqrNJ+a2Q3ix
xju7v68r4fBo0/3bj1ZkoVbMY8aUOklTpwfCWpfFmeUdWC5WPaLyf3DMXAY7i3Oy7pJLQIsbJo3z
Bm/ucLK8bcUBxrZ54virt/v9hEbhfjNb0ib/baJlN6lDoLbosyn4GCrs8wBBwuhzY7iy6QVeoy0j
NfNBsz0bFXrV1ZVMhKBVv9D9SrEypStE9qPoD2cbjRp2b7aLycCB2RQY5sjjvNsy0QDXR5eyBXlp
M2lWjAeBCJrcS/KC7hz6AjIOfrT4NfwndghXZj+c9BcRJM7wKYDpwKbNou44Yh1DwUtZQU5E7tWC
usIdtCdbMRirPYs3WCGzVsFGsG8ShhSjV/JGC401EA3c6EZa21Abj09Z1i5No5Re8NCy2R69hRb2
vu+XKLgFLus92QbdFhaUl/FYjZd/8BK6fVQ12Myz9Q1an4b1G2MJZiqSxTHtI+z3hnC9hp7C9SQi
Ix56/1YTphePuA6+vHs2KLXbac8CBnufd8nakwFCe3icQmsi7n1xDqjPu1PbcpmKIIg3F4UWuA9A
kiKKMXxQq8EYcv1ILGqTpRDMiFtAJkPgN8KWPt/s40GaVDvwHH1M2SkgGuclZDJJaMPwDeMNxGGI
ddb9FbmXosE0ml3/rfHf9PILgYrRxVW5hiz92CzsUUx+fFQ1YYof34a6wlpO7g8pqohILTWh+jxa
d4TKPZyy/LaRUEqwIqw/J+3URApJwtmb3RQIsKgMkeQwzQ4BwT92dFhGPKhcnnJyRR50Ge16wkdV
5qDc6fY0+1zsf7mHZ2ATgIujIgHi9uipmx+Aq5iXYMOljc2GtPxkTpcH58toibGpXYERXuNU+lp3
LJRhVB1bB9aKdKjGpeNllkLxIPc2IiGqf1G23uhfau+reWJ/84zYPFMZbeGQtrw3pQZ7oEnT+2kT
n6nYCTUWfr78SKpLOTcp2a8z6GcMlj1Ejb/jvGU9keT11SBSSKJxcy7tEO3azjmtENLhjo2Zop7l
bzIZ8We3yTqzxeNf0Wj+LnB5BcSEGbATOV55LgARZwIzKf+hMLO1ULG6Jv5LZI1r/IMbc5Q6f+m5
gA2JJoi1CJ7jdXRDSdnim23Kr8jqjU0NnyWE/4PION/VW+4xKDi4Dghm2fnZpGx0jtMkN+59uJuK
3Bnuh/y5d8V3MulB8JURhfgn3YYo5JjUlUuHXLOS9M/6KBs7IhGi7eQloudFLvmzVQjqKUK6Lh2M
5acA5/c4F3txCyPU/PECbuyU+tb9Gdu2Iztc8KgM/XWHbU0simk6fso4Ep8wZzeSAcRP5turNlmI
ngPpAPHPP+uYH0jyBLynVLw55Je2XUws5orP+wD18ilM2CUgSzn18IYQylz581sxZdcd6JY5275y
e/TnxMr+C7ZDsl2rfYExSISTCpepMhEbO5WHEeg7OqtLYtOsLNk2r04Jy/PuTUlzVKODZZT3JOvj
CWsQRU8U4RWQXaIn4T5aaVF2EzNDMda5/5W1ohgEzXX0QTLBk6kgd8spF8QZlwTOUT9LKFs7+J1Z
hCoQDqw2SweehUYlXAj3WMF4HNzsGD+XHBTM5LiDb32FUamBHU6KzC2DRnOg/KC9SNOfcRbRvgpv
BsTziqVg+rDYy13pNJJbsJWfpYC7HU1N5q1EeqySDcoKFah2IKhqiWwYPE7zBubeEK0ZDsMC/uT0
kmlUNw0st+03hmsbXX7m/CIHETGSe3Jw1S8c3kvgWC9w6JoGRe7QB8E+JCwICcvTpj+o4Cka4V54
elZFK/L+UnuF9TmiQAMhhqZbn6eCollF04wLzd2KSTxLWiTUK/6yu6c9R4uD7aXO1wdqqU5cOj3R
luaHDCjrdtdBF1BjJ76HFPbgNGl4QVnpjHyno1dXXlX4RVpOUZHre6uw2MEg1UIrBg4FJHcGiiAk
MJiqPnC494zgDxveLFM9QJdcadV/EXl8WUW8Y+Jq9HXw1Nz2E6vbssWHgQ73cEPLnh3tf619aPqC
3Ls6MogQiQtKjlfKTnqiv/UUwCaS7Gqdpp+U5NS3pN1uLaLCcLw7rJzD9wd0DS8nH/pL8CyNveek
OU+wv7DLJLHSGeAbPQJFFLoA0c6c8Cs53yl6B7stwOiSrK/q8jUzEF3zZ6IGNKjsIbnJdjMjZDKw
WQRCKLjB4QA84cWlFIxlBI92iOrvzU1zr26LmN7dpPgHbZAikmC0mWnGWAkbFNcek7WaJ/4IrGJI
zsvRjXCB96d9ZYN7StCKu0aEOcDJ5WiIlK+xFDfRqKu4zOTp7bXYsJFEhO1h8XcFy2J8EqB7YzjO
FDgbvz6n0MqmtRinlR88D+yqeHrsl2Skt0zXJPeUiubJUsFsVwEBFvfT60iClSuzo6FboMnfa/od
z1QUvRQttfvyBgswaOJVoQZRjHr0THva1+STE0mpKBZCRET/o7dlbT5jH3Aj7FRERrH2BkXot+wQ
GD9Mv4dqf7DTbVplFAHzBXOIIM/oPKC+N5hyTujVpdvxrbxr/qaJnlIQ35keZYfi8gasyF8WyfJb
oz4FbdfJ8ggwVIZ3w0kyt9TTTflnximZ19hk/+Q+1tXz1ISCuB324kXC/V9kH3ceXRzM88/s4M0g
zFaxL2zyHsSStt37uKvSHyFe27VtwPpnfmwozjY/6K31Ne414TEqnqxydEcmZkGJjfLqDN6KSvIt
b/HMZL3xQ3sa9jiglyAsmgjd2OFziosRSLrqNpS6dP4E4h7IU0Xb+OmlY6OwovLIcqZ4U71YmHZI
b5EMijih+LCic5ZETKmWVOL9nFKL7wO+Nxu2CkIInuLi6x6WnI5MlTlAgY0zpFEPHDUSjCsO1u/8
GMHJy+CvK/I21i1z6D66WU9o6XbM37WigAiVFb5ceuw3H/6eS1IFX64ZlA35CXADJP9syOo3idme
5ztWIxCqioCeiP/cbPYydclBO/930leYgOiUo4Y8as2A/NP9Px17oiShzyuY4zO83dveVSgQ5iRk
Oc5xxbgBdbA16prDTQQRwmlKYeBzYVA53antwwVAV5T93Vc+YrHNjjZQn4qMmouo8piGmCiYwCiv
Y3YwDrYNcn3GozWDbN9FmsFd+8jIBSRpP98ERuN0B5vxiEbl2mPB5z0IvDQab6v2l1Li1ODfIRcx
DRm8mC1h2oqwdYh2lmy21hx+sFJmsMlJJ5dg+SgCiWIiq6pr5bXqCBUnwUcFmB6MwY8u6R6z6tZd
7Xa6Enb2Je/ZD/7jpDe2Q2OSsJ19iwFCwMaJY02PfppLuWRKHANKJk5CDIKOKnmGepth3SIfhkOM
X4q/7tm27rTxuv9XVBMleS6+Snaki1022/QOwmeG9ZhVQaDh16QxXDvDtRPLtTpn7KdE+5wdUcb3
GaLRdK91ZCHSdi//ZFZUfOcCJCHd9a0mbmDIeqrkcLMajQk8007WpmVkrVljof5xHIGRc0DSmt56
oLRRAbTWHXq65LbgwnzAh4UshLtUDwY8uUe6xPyPb7SM4X3IqeeCajPi6xpUADG0pXUhx4vZDrwY
S3b28BRhaxTB5k+M+qJ8XDjWRT69kg+10pcGIG+ZlkQl7eQaZvc2a5OR6I4UISWKaoRh+K0mXm0X
wEPgBZFaotm+oa0kkDOaopkESx+mYP/vW+gyyVqJPhBmy5B9Oh3rqbVf7cD7JC1NqoGZYiQpD2KX
2QwTVnfHmtgX7laOnk9dsYGNUH/G0QRR6jxCkgmg488e2736gkWLR5/YPqMIQDhO6ofSNX/b7c34
Vsz0QNfXYj5hBCWIZzE44nT300wpzbiU8FGUC8k6DXF94grzjvAxlexogVakv22AwOg2yN+v6EgV
KBhYxSwcGZK5nWG4N8qbe/v2HBB0CV3ooIBT1k4RWIhI+6t3siacro0nTnm64KjG5bZnyZcvhFrQ
4ZNYnMwATQS6mbC0us4ZTuSKHjIkhqp1DVLZ/654ghkHX8sGByvNUHpKYVLMWuj5dOa0grr3iJeT
tzzFxz8zi5O6+3zTZdgxt4JZH9yGAhTRCZR3GNvwwrDRsZk621HjZ5Wt0RaoB9Lx5BeTfRH06mOZ
AuNWHLRwPS02XVMIu9Mjz7G4K38QUNoB4viA7OAS2y/guSeCNNqGR6BnVtDPzFqB6ByqNR3xSYaj
B93mSqqwbEsdEZigkCYB2exnqx9o5/+3fgrDa+ZUFbJ3xRHk/Ry0S9ptTStGCVRbidGOHMcIkufz
dR7CHK6Vwmxyu3KhfYqtdNQhYtbhc1LUYp+g3WVEu7fCTOzLRcHzOQUSkgulB0kTYbLB34e59o6e
9HHOjin7HkpJWp31aAhGfUNPCMi1E+PFpxy03X810YR89Ruo9ZNaAmx1p/e0HqVCocqr10pHX5LX
4cEwOc537P4QyWxbfi/FlApXF43kG/1typpYnqDGWXTokKNXkk5ESUaccJipGky+Ow6K5XOQ4dst
11KRQKHQs62NuEuUxZdSFLxqYqaGfTBiaW60LTXCOPrNAZoJQduMn07WzZwBeAyIJJpRL97EhnX3
IfzW8sf6eWj2FscwLGzBMo9LM5X4mRsUFpG8cZEGNwTvkzKgzQ7gMGLGgWacUj4LtloWNvhqvEEU
+fKA6qeAmBy26E8tlSffJ3zEju41GNBBjKBU8huEvWn5zYIpnYpcO7jfbfa8t1Jcfv1XbfTD1pWv
0zh2BjooZSyIHcoZDI4oMeTGR+8i2kFJKm/sDcVPIxPOKZKZ6QAPXmaaTiHhkBWaJUthTAYU5POK
Eyw2l+iHDzATOzQi3RYioeztLACmrKa7q0EE/ehTydjUAcipHNm/NOMWUB7/MqkwYVW48U4hCnjm
UFzhRjaDPoeVIFEUI7viGvlCBuuoES9LXb62/GoD5ahTvWua2UqkGDtohGVVV+MbDMNw1cJCtdo/
8L71CfHumRx0iE1FK8mI2hslkNZ3KpyP4p9XgowjE8Oy0DvrNQv1NW5OmvSA4PB1jCmshK6VMiaF
AV5pzc6ax+VAMs+la/8M3K2pijceMBC19+i8w/LRc7Tszz6TqtrQKg5Z/Nc7KJEm41z9GMgUjo96
30eXxdvm0DIm/IySJ3zBx2o+J8MdehMD8iJFWnEh+pmHjq9OtIveZfuNwLxLfSVakWtc1TF1LTsC
y41PST8/R9XR8IERbIxXfkpWgm7X5BRt5oHUq2zRlVuJqimohLNAhagD/hviJkGSGdNv49x4uO1p
Mr1NZ8fi9BfymgwXwURBm7vvPqctkx9jIkQsojUilFYNQKEPrlSASZiJM4XcE/PVQSrcBoR7EV98
ZM4+CFjuclF8Xaj8LLbZ1icbUCjDBhsoaHuLN8E6x7zfQhzLgMPgQT/osgkerPxtEKTtypjFsKtq
N8G3+uwBr1Ow12RJRw92L0RITRvk3iTIAtr7A35PDvznw2xlCWWRrB8q4/jbjuNrsouM83cgBGFX
vIKDWIScCR+jG1LASSc8kSfOjmGUYnU73t27X2OYIfsWSVIwVX9dXl+dwoXzwChT/DaRfzArdZZ0
lugSJd8YxYxb9WzkkS5LYihxTM7qP3LoDRwRD9E/wq8Ux9BuXccvb3DYUXn91hefCm+WnoYpD1Rd
3bJkHCvXGE1nSZg32O4BKFhQqx1sO8bVSe4ivaFw5tBXIHAh3GWcvDlb+XBWiGROIcnZC/rYCwQm
pXyiXV1DZDxbHTLb5JiYxduvv+YRrs45Kt6egMkZYKFEOBQpOGIP6bXgTZF8XlF3DmIDXZ7QyDFg
CLg/aAN3tCsJnFwDJu/Hql94houNLrZY+leQmWF2OjG0YbHqueHodUrEQr9BdBEJoaGt3Dck1Qnv
OMf22zPUTi3GBDDoTJEXDnrwVaPKnTKOEIFfRSkYih9bwRNgepnZX/gszoFM/+CWmPnquaGg39mQ
Ylr5creuhVjbONWJEFHjnSf8/iecu8ec2nGZ1Ij2H1/znOmfmkvoGn0vx3Sf1FCYDcC/BUalog+2
eXH5GSvfdD27J2GHZGxlVul+/fBHD2tfkEJsOliI/Lv33Ny7Zw0zWr2GctD6sTvJ8f09Tl5BAW51
1fcJhZFI9+8OAGx3UZb+ymH58/P3Z6h7CnmxhCCfHsWa4TPTGONuRr/TWqQnNF6UMS2GXLGBdWNA
KS+b36wEV0XxBSIyq6IfMyfTk87MNW3668ApIfXIg5XiBY8XIw14fkGYoiE6iu/6sG3ScsPDIdWj
/pV5630xhgdwHEN6ZMgwOnxBqd46dUDiP8Zc5sRvgCs5md12pxG2qeadwcqTiwNZyGMlB+PoMEGF
iZkkXd9SHXl7i51w+ZyMjETeXxapJkQDr/60z32tJ9JIAD6ZiRCsJVwVRaXcMn58/9jT1KXCjdus
qny8Xmu8wPoYFTVjqqmrheHwv0hQM/QE8Xe3LwKQvfbnGgepx13DP5aAXi/pswuOMHdcT78aN894
zSErRVBLk+V7tykvmnRGeaoPsudbkkzc1GpL+xUZZF/ysxbRP0/a58eDPITlNciuj9QWfxVCfdJ0
2OD/zgQxaOY6Gt7g2ZdYolDJklzgLnopWgIvejKyuJSaGSvRmEULd4aEhTb20BrXFJEdEsx2pQRr
nCW9CllMwuSYM9U6Z1xowyjgLX7m3eqDU7V1dFOP332lqzUVHR+5Rzd3JzcrSlusjj0ggfWOy3eI
VETiF7UMRouyQndDyJwQfpIfVqKVFhW7LKVObI9mO3igPk/J6oid6tdBQEebjqW+zOEKPaIC7DFO
zT7A/BdCJEArf0WeWOwgddyiNUCgKQVkoj2JCtQ9RxX8tJ2N3ATrAL4d+kOtOEdRI8AwchyWUxUn
zs2/c3FULbcmnbmxO5ny7ftdcybiVJPFXFVo/lTFKa4hUdzsNbTc6HzMws7gNyMcisR6zO+V9vFZ
SYO2J9YbP2qI96lcXWx/wVSyszcWYrXpnPqjrzmuB7jFMqPaGs+w2peGSCXXflYHssTM+iUmK8Ig
2UEYxRsDXRddOAxxS4AxLiESpZmbj7AzNfL6OXyxQf6j/dYHvEaa3n3QscpDrANkkQ66O3jfo9S1
UDqUEUDCql1V3fCY3Z0UdPwv4zdSqpZlOM0dtjdqkFvloTfQAtwLg92WHRoS0Fx2tIj9o8unYPfC
4y2Kn1KOWydjlcFuOXMzZguKjCkoQYUGsqxq9jSKafYMrq2hPx7UalXX8GVhhAWju/jDnP5zq8W0
4yn84xQYL8+mjK2LJLDw75/kW9hZTHTxPWrGoQeWg8WtzUvTaNT1fbw5csB96Ldmw4o85326rXum
jITAv+MuWJfCZu/C3cz0WINoAf77MiAX4/1zVr1KSLvbc2IlPvjzhwBW4TaTuBx6DvbqRyL6hfmo
iDHdtTLp07Mvuwx+Gfp8qHrPCxZiLVEmqNNbBf0SCpXt92ztpR4VxyMnpvfrS+m09zwFkwgZoRTk
Viqi3WrElC7r20nZUzr6lMqFslo0G4+d4axamZvdQDM1+R5+Ncn3n3yIwTHvsUB3iAHsAwQdd2Ll
ccwExU18iviSazqRjYKRLDSKkTEtkiDenPEBdgca4PUCBzoySy7rjCuKC3+VAaY4drOkdlssFynW
hwwE+nRbii3NooPCd3SbHXZYPrnia6HeIJpi2jE3sqJtEZjUyNaY1fJhrFxMLnv6dv/kLdsgFkHA
Hz2VZRCl6bby5cuBA6gAfxVecyAqP7AeYjrGyrM2GzGuuf41C0xTMpbiVnR1pAAQuLUAKDLdqOZT
pvBc3wUNEfa2KtPertlPf0hw4jFqiKRFXXBsROwHMAv0Gc+so8VaFFzpYy+A25i8aOPOsRlDUnL/
M3ftLl4GrL1wkFnmSAQTte3oQlXXyItREskaJBAvqPWDM++ozaiRTh0DKhYRKPIfeSsU+gJ8rUKc
pbqx0FjcqpG+YMfvpdXR9CXahFIcn372ovlplh1jVnFpnIinS1Ng63cYh9+EL9Vj5rwPk44qd/X2
j8ZDrzPU83Wec4V8b5grHjgOXDkVEqAKRk8mqUMYgW4LkGYM+ar5ieOonB6oWSKkET6DK+a+ZQ+Z
cUJH+WDiV4zwRHytBa9EmmpOwzqsoG/yR60YWdL92X4iLeL5tWDc5z6hNXIZgYq0l8tnbGaeKubl
bhSTRlcZhXU4jYWRw40dJe4sJclp0oNg04ywykqLuHxCf9urTd2bzQ1+4fYG0A2+roeuphp4BSqq
fyK+kcnZ7MhXvFsOxHqkSkjYv0SUNwqsDJKw9pOdG5gFLmqWoCVqEm8/hAFoypOWR2SPQoUnjpoJ
nf95S0Jpslg1Yv8GSJfZ1/H04904tbbhkZJ7qhegH7NL65+pQMTcrVNzKtSkTPmbMWv06A0t0Wph
pKC6ZzpE1/szR3Qjs013FhMq5aWEj1RCVDQjcry+zhTZ2hP90B89fSQmv6Wupu/Oyf5kenSd4e7Y
kuCQVTG7bByP/E2tP9OEvf4V0u5U4ENeah+aEKiCkUb/j+90TF2Qu529yWzFPglXKZrHtWpSEQCX
yeT/gprZvd2dq1I5W7sX7MfIJyTN8FGKs5CIi/z/OzhjLe/SHmmJu8HP32yBfMq7IsA4DVjALsE1
Iv5VY0YXb+Gn99zcBgyv2hy6jSNk5VyVoHn5As/vzX1HvfENG7Xu4KUcQltPF4BEzAEEX/HyZdKA
IMi639CRyXXISLnVVI6n5y2wxbVRFyP3neOWs7JRv8wPdrL1f7yi3xSSLOvROwG7n3V9wy2TKW1i
GoAXWWF0tMesItllPPh/Kik2skZalvC1/DodpPA8wOeJAvbUukOlFPNNZ0z6cGC1b8KpXKGWnvhp
GZflDCySaahTDhWowiwXPfn1aX5RNAbGPxe9eaitBTWi9rU4mcoddXSBfoKPBQ5+s3heRX5xMBut
0WNYK9lzTq2o0PSZN7xYc0eqT4TgqSG6u+GOb5R2mLz2A+/VfnbSVVaLH7SQBmVj/5/x3Pf9dBoz
MekY4nQ1QbnNmI6oxESsqDOuLRAvrU0MbUZPxxZxe0Aok8cFDqJ/Gv/R9jDGrHT9H2UGs6WaNXgj
WLneyKgOSiguYllqsduKf82/aekV8w1ejy/cYtSJzA9i9rM9bOTDGRcyiC4+zJYwHkxbCOaYqvzp
rFF23x8pQuscohUygB8jeSnc0KOgs0qUx9oX4B2cY5AlF+cCDnZkOc8yBfYNkbz493Z65VxpscH1
wyg4TzCjR41gavz+9AH6CyfielY/Tr34TXygQS8/JxnhvQ13q5SUKuyRXpBXoFeMCOUqTnW0B0SI
YwRwS54HACjx7fmIsLC6HzdPUhgIL88rt1hYHTjxaImaygBk/RlJselHwe7PCJslrAMP2tWFjgdi
Xq9EMfz0jTbjgEMxbsMb1pLd20AINhkm1tw5RXhaiRPVzSeBggLme2hF1prNqd23aPzroCM1Maqi
Upp+SaPIYPeYNGCUG1nEcZ6glWUJyPM29zmKzBn4WHL6czCT4HoNjJy6qyY5RlWkSGEnbgx0s7dB
+MddJ5FvdmEslk2lnJoPuVvYHFKZjjTzHls0LWQHq8kSraoK/VBcheMH9bupQ5mnhanO+2lCYpjI
G2xSJNEmVOvDiu2CteLh2bgScqPEuamu5C/uFlfyuNa8582l42RMndGwU+v1QOiTRCu7JPhHW5VU
9bj1ax7RCGYyare4YKYt+krQHm+J9NTmX8KAVCLwpM6Tg4zXQf2dsnhx4WKuU/Dpy1ZG5x9mnkNj
0qc+flzzZMXPz7bfzobJflAncjh05qV7fMSzm9FftgSPlhHxmKgkt9G4EkXTpgUf/CDZDwsI2yoT
M84xwzTVtZoOrFcNOvc/G5qIbf/Gy6dUiljPsLoJnsC0T6w4oOHA/4NtMPJOs0uqhq3xyx5ISrvi
MWuSvwYZzPnzi+9s268DXJdEvDqLzYaPF0A/XfUx73f6Bi45aS/pVqPqeS8plgPjKEnq5BSpa17C
+fnLE4lBubE8nFIOB/DBSKW/ic/zrruM575jBGY/sNqZThA5iQABznsRJl7zGcDWHtpyJaqg9pLZ
EiV6xt2qry7uJpaH6QBp1a7NXbWOquuFXJIPFVLnVWyaiQKhkQhK85vkdzZbbQJ85vV3ZFwSbQnb
HzLGZnv/RHjLQy3AjFWoKMeFr0KkQhPg5PUKuW6+qHba3xdotGZfC4KTjFy3lpO/H/D+uoBNt61G
RZ5TfGV+hGCzljk4++koFZ8+Z62oBKwOq684NbHxsHF34NATan8nm1q/K+WaQb1v1N3mfnPdHLq5
9JVrR2xqVudRLnpiCifE/4YSjg5XNsPdn7ucwooEIIh5ToDJJ8TXPZ7tix16hossBt/vIfTvG7iM
Y9ooC2aUxSBMYvdJMk4d/vJxlzhA6X5Z9y6SftlqJquu4eXmLRcoI2kiUa48r5fVjjztdkhIQUj1
NQ5y4TacaXbsQOWoVW0WO/jfDbU3Hag1UEgHZ8eF3x84BoDz3vfMAyVPNpc1pf8ODu7pYEOp+uJj
e5n2JZcw/J9VMijwM/J+GuLpIKhpzkg9PSyybONaanifvAuWE+1OKQWKehLutw+DxlYklLF34JHW
sJmCfvOBCHQCXPirj8knrRyqCluBYmd0HuWzYQlo+f4TCKKZWE+3rd9grdlWcafPNRTOjNUnitQ+
lM2muiSA9TvyT1U699UL0/9v3Ta122VGCNbsENDzkuQ6Ol7Yb0CKrjJC1f87bkoOhkef+oGMFKpw
/7AMH6x0kjZQ/mogRnNUaJgKY6GHR1AVC7T/ua2Z1z3lDQrBMyG+zl5Mew/Gd+evdsMTnphpnHE0
9Ma0BH7wEH7/Id0cuTwzGDymR8qUCQ+diU6xDw1TCrZ3Wfj2E+kzmN14UJdaQnDsv80ccAaXvgeA
n36uknYhNfWD6i4B+OKufjXM2pT866eA48TOtFrISEUx9DPjAv1bnDA5IXIhmI8EQ3Lzi7Xc/UmC
BkcgM+BnX/w0ToHBKp4ki+nrFcPXpljvVc/y2ExJb+i5gZvQDQD2ZrJ0gZtnGUyzWr3B0zVNa4zH
x2xveJ4x4aPS03wJS8l9FmcXdGHsCkL7lJu2Yh8uXGGlMk57Ble3q14J0U/0Z7fOg9wcE5CjJHCx
WIb4dauQO7K1erEzRc+MpBUfp2QPHbizWsPtmR7DjMZ3Lp8Lu1UsBe2h9kIyVJvbqLCVfPJQW9nG
+lwuLc7nuaM5F27wx7kU23XIk4l/YV3KNPhIt3Ww6Nc8UADaDKtavBgc6+InARrAa28hXkyFKxBV
wkr5S2Qp1TvbGkMQbfDBxFQ8ByuInVad4u7KGl/4lRMjL+tXrkJrJem4pss1wEsVF2KjSvPcSXGj
Mtkg1G6L3g3laPJFFvPAQREdYNWQwTzkFZ4QLm/cvVSRQTKOfBukrei5HxJt9Bh5ggt9Y4vhBuTp
zCnnrESghZO7Z9JwcHDWL0tXOiPi2v+ue1Ll16gOzmlkqaOoJcgExdXVIszRjvsGj2paZ+gmDucA
hoC6aeoMOD1btmEnUUNIgcx73SL8uRCvpWy19WQsggf8PB6prn5c0n8AzqOJMQ0fiB+hToAqeJKq
bMSPUX+OSfNF3mjQYAz6oTUucVfreIw83bvPb3E/UsRXqrHaocTLVTpFvCajNopwxLyrQTGYfSH1
UqiB5ZhllA4pRTCAbI8X09OuL9SlXS1s8M7xN/1ABSA64+i+ObWC4XK4fW6ID4NWR1r4VpaNZryd
Qw5JQMlRzGWH9/sM+o+tS0HrgYwdFGOV+ZECPxD4OFfEmZPeYWZMbQvEmKoCeM0eKT4Zd+C4b6iV
Z33ZyzljzHMosw8rzU8DPzj9GQXTdtyaGAruC3UdP3CbM7eD2FZl/wyBuiui6wGGVxX1HRCk3zV+
qMBRLlKsXnSpIWFatcWgV+WPFDTcpUA1+NXAKXGYsxKi+072M8NrntDs9UH6QcIoADHBTxkgLFgm
f9yRJD2rNepOtpGCp8I+0Z/LqbGJBeFfo0EBKF/pnc0yIkIw59X2HEzTRpgtyeNuJfd7oirbaFN+
VXXuiYef3aiQFz0lOzJ0khteiezsKR+KK2QzpG7pap440H3gz9RdrJt0YLfxiR8bZK/hXuzFzp8e
RnOSKlk23Xx5BwO5rYddfxpYqZK0dYrhZMpxMudKrLuSaUoJobPR36vCCoyNGvKSndDnIwPvRufw
ZXTj7jlm4JTw0WW/6d3HSvCaAKENljoLZ0lKtlCNfO40C/0OBdbiRu5X2lhBSoNcaoBXTQ+sAxDG
/z6M/jw8jhaNJfybcCAAgt6GAzTDOun1G1UzyizQqgV1iz0oQFL3u/p5ap9UCj4WuGgay+G9aZLs
/dY9J4cIS8wabcngVWfw+YlKln3cjTthkXVDkV1D4RdWuJGz8mWagiCxQlcR2mNipJal+XiYL5Sy
7OpcLUcIcvdjLsb8ZsiOs9/CXginvlmb4qTZgOMAs6CLm7tDk+BlUGyFN6m3k8QkhiB6HDX2ylv7
rcXDIm3GotthWcyruiNBQJO3a4er00CHN3ILPUKEpBlWjNtZjoxL19LWdwDOEBvgZQdEORvfbIC9
AQ/7rzh5HROmpbDXEFeEiN+ajCwPnIadS8KEOC4f3T4cs8ZvDjkYTs4NmqdB7ZBJAlm5ujC1st+M
OVAPqGNCmZqmxCU/o6DyCcTHEyW5aR2SW+xd6FiFnsmHamLestpQkInLg/9Hq3Qc1XTJWP7BqAM5
TDKIc1U2oom5hHTHfBC3YDWH3ngr5OG7QBFuXx63E546juohePtjF3G/Ja1aFf2OLAXB6j+3Be0V
4gIvA4TMkE3kLBe8SDQkEMpVEHaRKKYpBiAPNlboicIrlv7LEJW4nhLh0bMd2pKJMMbXSsQ3JTsl
CBxuhm0F42OtdegJFggU2VCR9RLlj69hVROlkiyZ9II5va2/+LJ97bjexuJz2bMpuBn8eSRYJ8Rn
hm00VxO7wFsZXwf7m2TyG90XoT7dS4wLfkoBfX2+xH9DuT4SKHLOizmjXryCM7XUgxE4PuXrDXek
2/XIK4Wap/9s92SPySN0LXHLigArauBbJmM8FOzQK11JNOmpY4wLaGdE42PDccdIGpdkMKRWdlQk
Exr4nomPRtlaqHVLox172x5cJGemjAHrXWSHlmHKuqBBKF1+ALmJHngsVHOEXJNaAOQCoz4lhBf1
Dv3zuyN11ku2ZciHrFUMwiUFSbO1KvgPuBk9NTdbQEVstFGcv1vLmHuZDerUk14IpxI5PWSR1qmi
rMMDsIKEX/PqMKic2mskj/dTybHhCApToBvdOS2eGieq4POyWN1laFBcNpbl1Ji5b0U8I0K6K6gm
b5xW5q+LL46pcRMc4L1nobqYkIMAyGxWAjhYmCxYW2ntMfPpTIMj0fk3VkcpXVOHv4UAjB1zs9g3
tiCts/KqXftcZJr2fsuO9JZhi1FECykHQwFyl0fp+HXe+Z2HTaNQJ6MLlHFfzdBuoVJcXZvP/aO7
4DmEzmizwnQCwJUgtHEnz8hJZqOuTKKLcZtAWBX1mR9Z8hdB4g/G2Asf8QrEVKSGRTBDf5Tp0KQF
8D3mr4ix1g5OosRLI8oxqs+8VIwP0tmvHNTS6w/qIckr2QftfnGlso1Dst29TQZkG/AGIsIL9mqd
EX0H4ZyNXndQbo/za7aWCNkWtr8uNQ6nFoQqdptzJDtAwA6fFkznyQmJuMml+5l6t64dBiNSX/Uo
7taUonh/UM/86W11o5k75T3uo5EpYcm7NP0wf+gWzMZcAaHum/uMa24Vl+3HrHQFIG1tX2TpnFar
ad/IgFdFfOY5NMWY1j+o36LH2CG9AYXOzYQ+cbWdF9kJHzt/W+/aFYAKTj68ZP2rA3GwkJjru6Hz
LMEQ1bEo5KvdgRiZFMSVzIgErJSO1QhzeBlL08jOw+5Qzers8+p4R1lBj00tViVPDmFo/01hEZeo
IvXRzNgOWMiVmiTTBQs9V+ynNOmmJnYZr9f3brkvWF+g81UIHy5vadj2vW2OdVMLO0Z2f5KkknX5
el9WtJQe4o4u44RQAvDUXaHWCRRpYxt/PE1IVnZKI62YmCliO+ByNfm6b4EW2ZieuqxOttkYQH11
P5Qf6Z86wb8FATKVS4BLegHLsXeONR+d1h7CZYI+/tVW23alQd4bm+aAZydPdcR8xNULYpu67VTt
mdsjPab0RtQNHQnuc1uoAaUuhQiYe27Cv4j8xHn3tqhDlE0W4m/7+WvfCJB1gIt2U9tVABj7jrnp
X67tgRYU4mt8vKPIwflnSNy0r2guU0I72ZRtlnKPeXgN5jGb1CJf0mMew62cCZpjJX3+Ir78z8Cb
0bDkW+v0RJnfskuwFsF2YRdEF3fMd8IyLP0ruYhSyriwnH1TYKLGbsr+nfOzwFPfxjJ6MVlf3rub
GlEaQljCV1v3kXXHEoJ8fQcD5Y/tEH/BjpAa5tEVg2cjX4Tc44FDOx0gIz4TdsjlCmK4UMAgPuSV
mDQWukY0CP1oKHPsYS9m/J73o32AllYsEW5/5afUgi1CUXObeAeETJe5pPTXU1fOSGZZ98V1fSbF
/ktpou6llFfsVIBjJKPO7s2gBDE+aZ1dEQ25IhK5Rv3cJSbbHCbjAchaQwZwuZ7OG+lWpYLnXZKo
R7+7SxqaRN3RF3m36mmhJLj7k1oNZjRsuM6P4ZHG8IETWK5wcYLp0JBxeS2ZlJ8z40K+1euqLugz
jvkQ1t3O6qU9phPnBvRF7HLM2x33SydJ9PkrzLK15Zgg2y2klfSDWCS7UfGLKvxqVLIo8RzJ8ghS
IJENDmon/0SZdWmZc8ixKBoJBRDKKuL0isvyddx619YbzQVq7K1A0g10RP+wFZomGUn1gN9BMmjz
XLPu6UeyV/wM5t3cByqWt5+iwyjQt0mAdSC6NMQQpLEc5agCFR8aBQdqTIkH5eum2zeA59+oXHb/
OGoEn6nX7nrvujcMLc8ey3+8gohdVuFr/TRWAt/xs7gXdIZop9B0nvHaeyUDka1i47R+TtN6fQOE
JiWqFC5rvBV7N537mfjHg5n/Lh4clqbRglS8hulFE6iUQBslI1jRXSjv8NJYYXuws6CAp85euxMG
umGEuHKhVSppbkfz8bOz5cH6I2SMbM+nwmex2+3cj2ObYJQrQpsGj4UA9d8WDAOQP1ABTrnVbOc5
qrJsCoyll/uz1ibrDiGZbxpMEvBovmClhiTuncj7RIQ7dE9cpSmy2iBU5E1WiGxFgogmP/PEH1f6
ZC5bbWj7pvxaU9f/36XaxPPYvC0L3QzpXeba7jMNZB+bqaCYrR66Dx6nNxisT2dlZS3SwosIooWJ
qiiQjjPabRahFDrmlR49im4MMKeH9F334mYHH6NL/flIjlNPJ4hgZf/Pkr5ltHMXVnp3sv/UTyX6
4Q+56h1mZA5Lfouy654CZXiE/wqMgqtACZ1X5Lk77Jfj5DntWrRRdTlFi70lHYlKlFnT4fKg0Lvx
lQnZzKpEwwQrATs8c4IztWB15LTAn/mQrNhZ0LLcUTNi5+SDuHYr//8yZlCn39OqkocLGcEdHt8+
E4H0DiN6V8bASNIny04kGnWBKlcAL38tuCZM4yvEthF21hjPeNNKEgMjVNCemrqx478EelMSea2a
fFjK1lwquFS0NQsgi8fQCMGe4eWlWJqhxPuU36wYx+x+f88sMsYZQiiBVGQoO8CBMpEmYqMnJDGj
EPGIRBJ8NIKiujNr5TgH+AMh4mY9KMZS7Ecq7Sh10MtTDicd9zz2WQdBmBIszvE9YjrNsXgv3+/j
VZ8K6DcXjItxcSZWC88vGbKp8Hefjmg6aLAN4B6SM20vP9rc+hlIS202CtthIKuDhMNxwEXipk8S
srv7smDTIuaJEc1Qfpyuo1zf9Z11BJm0zVkVy6p1kJwcY3sDW52p3PM26l+QO38JNyL+YWNKqlo1
QJF0/yMz0Yl096FmvG84EU4j9tqcsREw0HLrXQJSc9Sde90tpqckLmEManYL4n/oBvy/jU9sT3G8
plQITPuICMdrRGTF2CIKIiZ3c4g/ypnDoL1bsVfu53Qsry0WOfhA+MwiHcj9AQsFzSi9JEBKLmq2
VraZ526z6sexfw/vpI7t8p83dSyPX+FmyO3lTgIPZNowFX8SkPZxBQtLuyb0M/Vh9aZBhC6kdKax
cOW9E6GYw50YpOrhBPdNvKkXoKdxuOzmcXtJc8BKgP4PR5/md7fNUiQYfcbiRSbxXN8pw/IYPowf
T1l63JbYxQ0t4my11miIOpe2GgLWcEvgi521vsZnoZO4O5hxK0ZgvQm1TYeMEnQ7EbNfVN25RN0C
JFQjFbt/flCSJ4VUbbMdsimNARmsQ+Ue7x7BfZuS8zCMfadrshhViPqbT1K6NQPbUBRt8Z4iLDHg
IxHd0y0I3/vuKAdnTxHN1AxXUhgTuZzKKsbj9uxBgc2pG2F3UfXl+TgZN5ideya8otxx6ZAmDcIG
dKt175n4M8+PAfdM1PxHrFSykxttpy6IsR8GIVKpgUU+IQi7Pc40LRPuhg17VnNRD5Hh67CHh0j7
gat1JNsYVSjqzjn+oSlenklfEtgypjgBLEm4lfQBLxyE2RHDkBt0QAlcjaL6V6gbUfmRnfxGFyxY
AQPakmsscVPmaV1rr3+/oHH6fK55me8B/3Mi2z1KnDkUrrsyRBJ1ch4PNM1W46OkFyD0KBV6WAhA
jrWTvXXdeXQh3BZFFRVYFwHyCu3FD0g/SqQP2SC28GXVGCCGIncjrwdVpwspl8bqWk3EqoHc0of9
/3pZ268wlfRSCeT0UUPttrgjrAS6cb5Py08uBTQcuhz49LaDZeC78GxCuqmlVUHXUw6S54L8mwk2
75IHrDT2JfoEPjBVFC7xCGy9YZen0Tn858cXKStcZ7HpZ7Ntlg+QN7hfHKpuwq/LPE1M6Bv9x00E
A0j9qHgCZX02WaCBAsTazTKzawDysQZnRNm6KKz9cdDjfz3WhblK3cVrtWpmPjMv9T9aRBHtFVHC
KOhb+bqCMxTs/PHQbYwy83cMT1BZfZi0es2iqd84tExrGKWk8n55Tiyt+7tECNy4HqdikGi3Md9H
GjOSo5854KFdSHw1pWz4061Y022bljRuUMLQAGtwkwTy8e4VqFH4RpdJyAJObHhOsvNk/hdWd8dC
Qx29lyMm3RWTMo4zQHqsThrMkUDBd3NAZxvdblEnamtzdGA2vgesLuT5Gn/4iXvXetg53hrOBNEJ
g7q5dWDLqxqLtvEGkTmwQ+kp4OEqGscl9xLIkRYcMwLhlFlYUACZIccEW/c3rhINQA1EWuSy65ab
vG1HyfSZj7F7NrU7n4W+6DgBJuGx8ItqO27dtiKvu06OhPp50aYLTYx+cNG/iiph4Tw6epyXexfh
R6YjE+gu9EB+fwbLNEmCUDx7BtHuQmXb0YPbgyxMGlBNYKHrefNC9gy0ok0TcHvcRa8vLp8WFRrU
elJYMQF7Rp6gCGdentdrCo3erysCwVUiGcbC1sxP+p8Qx66lObiMrByKgLeEQCjc3N453gIZWpPm
PppucknSE7cJxZVSg6hcP99Q6iHKo/ais+Mi5YH7DYhxcF/nshCFZO9uWa/CdlOs4PEw/KDkQ8gK
yzoOxMey1BEjrDfNNNbvkrfioHMazqibmAvemZTFapGPZoyarxLrv19RTf4tQXepZew07Tv2WPtq
14xBkfQ3iC6yPPMQJ4zMtmuuPEz7CPMsm89bWPjYHUsMQL0XPm5NpxRYhPNr5PIlHN1tbWNNX4fK
WBo0HKNzBBtpCBHPflwABMZjlWYH8WQAycEG+3X8SuSOwYWwwZcx08W8Hrfxc3FgndixPujZhrMm
PDNX/WHJEt9jSGCO0PvqntiLdc8ISct4kUzpek0bWMIu4+LjoJHU0e8CDw0RX7bJ666hMUEUbvq1
u1TR/7gNmYIl+joK/d/rGdwJ1ifuJxzX6ZuzGOgIa+V4tAl0M1GWNv2qXNDPdIjKmG5pbDXdNXwm
dNEsTNSgPKhupTHtLonWguFHx19p59RWdixoroCdeMfZt4fBUR0RYOZ1dQVUqNcZi/HIq0/cGIMh
TNoL0xG93Es2bIPKttwznO0guk9/SJMM3qMaoS81rO882zs/8vCJrZrPq9hsMGcxWOAXzZd0b5Ae
TSMHdIqKPqtVAPlJRTS5MkeK//EQdP8vf7EOvBx2L3vakdKlNojR0vTpSgUDth5dGEWPWdiFOAk8
4lx/KPDzKF+Wus4V0KSXP4eV0mW1oUWc3eiGCCvnLXwO3I64g8I/lDgrjlTBxorm4q7xYRNequbc
sRa4hx0+1pl04/a7kmZ+zIMibcPUEd94IxXzkRvHAj1gmBpKBABJnRnE821Q02oxRJxYxMrKM3Bj
sHjhecpvoYE2DqxoAxaTL2EXnrhsbrWZEsFILAxj3TeytudKnILs3hdYMsNS8WM9/oEqJ8PVTSBn
ITq29GZGw2GAtAPMaYU7941hGwwKOc81NgmwTTCLxu5t5K+1JGzymuUCoJusf+dVqB0lx3VSZn03
/6bfd7luxct/15w73ZX9fJO6Pi87cdo3s1BDQw4gwkq1gDBSq9sczhg+XNACEKjknieYxTYZN0Yx
AhpOovTAAQEJdg0vfYRVdbUAzibxhlH+k3P6oTkWZRnCyaTq0FFFZ8pEgVE0Y/ev1oXxfATdY4WW
k6xxNtbMbcsHOl59Lj8bDV4DomCCVJZy9hcyJRlPwmDvTAtA5eOrgMrprsxw93dRCgNUe/YkPUsC
SC7K+i1QGSQMdLW+mrq4JANHzBIacwcpNdVpazSgTJ7j6M+BANwJwQOfC7+bU1+XECoz65uqID6D
pLLaOlprtvv9YtG/yTxV4RxtuoJqJWEOE3IhOeQHczQ5ndYhgltU0/dPdpNyYwg2K+2eM/g8BJxZ
0erdJ7TdUVykRhCt+wlUiu7p83m4lcVraGx1DX9A1RrU4jxELHcOCEc0wRxuN/lEB1VABfkVShgh
uzJRUTjuedMxemmUfKv2eOpYVg1/eEjD08AWqgmRlhUFlKGwpRoG7hfpgVHWLu7Afq8AL93nm7x+
j/Sc7YgwDCdfGz6AZVoUa3UdJyeWQvRtUvhJALhUW3GsMVjEpzsUeggwZEmMrYIGEAK/H/vYBFYR
oVL4M7kbsPBtBcCJ0l6zUa/+iojjsQsF1sJKzg148EpNjO+QYFzBp61lnYwpMpt/W7mj0lxar1XE
yzIV8cPnObgUTbfFWoyaLLeZtgQcjncHBd73clFvyvHyHcnMjiAxEABLKRinamjjc5DnKEngiAmt
ictd1WNhJkxwj+B9mFH0uMJhuuzUJX4EoFMngNjrwQufAfu5AxJ65mrKRZaHauVgD6ugCtC7MDG5
5tIoLokUlJdfJDaAY1AA7qRLgKcp0hfhBVJSsE8zA+GGVPyQk0BfaEdEy+PDazPHILXIanxuHMB3
i71Yo9pQm/Wv1mjF+Dmgx/iD+JNY7aLQXa9ASBC2XjF1zwf83ZCMzStI2sYAKhPQmtq+zpDNnC5U
TD+fezYNx8vMZZ4xZCTc05YEYLv2rzZmgKMU3y+9oPWd32KhnCX6gE0hpLle2Z6Ylpi4qHre0S+N
xdGTBbEshwZWTDzBVHhqqiKVX6TOYMaoFn8Xqk9OAekczV7jXvECQngwcJWxtwcrd89Tad1dYdQt
4/9ZngDkzpTMTgPN5Yxa/h0BM8mo+aIZw4IJNj7mvBX2+3NhyICqB9ML4XGwoIg8pbV1VqkKe02d
QwC7k9z0Bhh+y9KpVF1pHCqRcMDoSuFORXfwk5fK/b+XAhyS+VWsQXQByv2FN68SEiJfsc9TyEof
ETW7QsT48qnO5E6iYoh05A/jXLFojJx86X43MD3N4dFikhyFTg0Et63yKrDPb3X9AXoWWYE15jhX
5UHELi9q4yqSPry8aAeZsuxBwHaULDvVczckx4aYBXrN6Sgbu/MhzD+VHvLin2gbGfjSk2IhqT3Q
LkhKn18mceqahJdq7Yw9LrDVwUzGg50VvDMo/t7QIvta5mg+K25rcY/uuTN/866YKTEJu6bp82En
coodjf9GvdqihfotU6OqfSAELwKfml7bizPTWMgh/b2aI1NHDNROp+IS9Obx3Q/KfIMOqGUCPPrr
cvcid2+zIw1mVKkJ9ZN4O7luZDS5rQ61UXF1pQWaYfzN5cx4DQprqhGCU26+AAlOKGsKCUZPivWR
GG0kGCnVn6uRR1CQk1H1EsfYXj7AirsAnO/LmepC73mkalFxSgFzOsK5h6vj58q/qKN4DwvYlfgp
G4dktOlvb8nPbepZpKmaCLDFlAxFCf2dVPmneQlJLcR32H06H5fYznJrPuBmslciN3EnjcRzU5J3
Ewbk7ei1qZC/KbkPg0qbyATM4VvEtVDrwvCsBKQdPpWMPYa4xSAqoL7kXmw1pIyn3vBkbUIuK+z0
8wXYD56c+i71lEfUPYEPJBz3UKA+W+gRlMwKl7gVvB1QERJCbN9IvTTDMYladbfTxldomNtgR3Sh
gKVHuneoz+OY7y9TFVwYQZR/a9vzHMDkaa5r7PLUOGjEyaWXrzcs0TAVwyUxX5ck+1sDeaE2TQF0
MRm2l8h8KtYRST+4tuWbRNgF5ArJYez8T/rFvKVSQ8KtAn9vGVv5CXnnT8B6VUnlpL+WqxZXy4EQ
fSm+gK4SjFoDNBEYakor3hEep0f/voQFilUIHaAdsBrNPke4L5ekGu5Z9Ud6eo4Z1hK1fpJCjMOK
FgTObyLbGCIeaWvhI5dT/hyQGEO0/vuX8uXSgVozUs+IJGJ22F9EzaFtsL4h3sh5KHQxOqv3PkuT
ywzeJIZd90rfoO60LMKgiyrGUQ9jAuhpLjYOD0CYmcDu4PFFEAqcdBTvIhoXsRC2sMf//83UX1oB
xvWAA31aEYHVb3lYCgE85hIvt8X/hD1JDjR9le3+VcSE+1wOY/3OuGuWy5/ggXuG1yzlGnQD2hw1
O6U8toiK3Mzwl/72cfS1rjyV8JwJWO+mjulzj6GDLEWBGL+EoR0rnyrtEtVwH0gY+/ifZjG/xdbI
3WOKv91WR8nmdrSS9+1qDwe7jBVCvzzSN4zO+gK9GLjYO63LeeOrSuqfAIIyMUjxrrAwLGIYFxHF
2e3dQMWIW/kG71wO48lILnimyHhzpmZE+gCIWFdskGqpXhpWZFw+ogBqHk5oMqpiVqL7Iu5pyzbg
beXvQy2EWj9QeDvpKRbmrwOM5yTzoOLlugCUnIeuupia+KSQcDFv3t1XQaFqfIZVspJhnVvlhz+d
pqL+QgPlUYubKny7Pf0rz+C5CJUQsgXjlnbtV/veHknWhLaZreSZDZ5R1QRfnZ4OOdOfFr6Fbi9A
rQcCyHYHkYR91khntE71ULDY/hUlkRHlQ6bF2fGNXi9R3uMWGFwiqlDl3Iihipq5nhtD+/08JYwU
trha8EuL5Tf7TYouAEhXTUdkReD0WaBfk3aAHuSh/6qXfEILYyfBbTx4Bwe6E0RQjL2O+usUY7om
mx8z7lUrIOz+S7maXoRk10Fmt/MikxC+/aNlgha446If8vV/iKBptnuBjnm8be6E2Ate65ap+4gh
2fGtmM5IOK48rgQFP3WIQz40/dywDVyQmvAn7SzF/r8ZLzaqxOarGCL1B0nsIV2LnrESMI1k+y8o
bYO3d8Lsabm0nxn26ln85Ts93Yl+x0bfy+qxjoR51qxbIST0a9tzdKb/ZKbieLViZ6LisbGsM6CO
iwm+gGfggljT/NiZh6xgEj0r0c8lqE81efnWNzJw9lgDj8HLSt0XjCf7dVr3apYT6yuhho9XMR77
bX5ojp++OYrEolYDmZ8oliL0s83vvduoqzOZ2bNfUdg4aOJTvSqkHn4TCA5q8CZA5JepTUhi8gAe
Mh2h2s4iHPssPb6h6hC6e5CjdfVuTLlyGX7kOtko6OZzLT7eYUOLZSm4ft+5K7o50cbXjJD4Lgdg
l/Ben3+Ays3pLKI7UvgxB8/4VAuiwrxhnzE2zG2lgQYZMlYZbSQE/CN5f9NKMpvlzuMK+R0jAau6
JnzPKTlFjM7pNv7VdtAxMXFXa6TH10DSG49D+tR1AueUDVv9hx2xD8Gfji7gcxIX1GrqjMaUxXWf
Kcd/lwHJ2J8/UGXCykA1IC5g5/Pv6TG5IZdTEQXPtE587natpQ3ec0391y7Q2CA92gGMY/UyuSL8
hyJK6rLJCLfDDQVFsH50HZyOBFDjJcsemS9ga3c3I8gEbekuSsKMLcgJCRraSRJf6tU0KdFEb1+s
6t4TeASJUnvafSIYTzJ8wXn0lYKEgVusurwJ54QIWf83v2iZOb1RsbuuuAvQw6pQOtxMhntjSW5w
PS9KSwD3SGcp4jkKJ/SNrRsOXLRTVi76VhquTRATDBDYhSKQhlX5RWsG83MRM5jMp0hhQrVQZfuN
Ko+1AuDPyrvdX8AYNh7+h8Fwm+cp3EWQjEgl8QSyJJ8m+x1xrN2bIvvsGwvcyR9CrWdgXcgXOnoI
M/Pi0yIVCjU/cNcwAOBgU/7bLqAt6seOV2ZcFL2mvkiuiIxLx+eG7LcaGjz+Kbgvoma1MJQ88Z93
Ruq1PqgKpKIbWCz6S+jDXQgnYkf0VmwwvJpa9Fau94W6Sf5K9gzjl9g6wv6t7u6VFop2VjVqDZPF
P8/IdOYQCNINWGa802fwky1H5nO/DqyOIRntxMSCCPW9PShQwhBMN06qZVx4SiHZs8O4Q9CEkrZ6
KyrIMqjhCzoS3Mn3MOOx2gF4GB/g5z8c4IHwL+fRlTfjJjBRyawjLE7wRxXhCyzTAHii33L6Cx1C
jVXymvmbYQV1TOl6yLxFjdI++RLLS1Cd0exXGNpryfZ6k9CjzvgJXExojFENJbXMe9ohacQ/UChb
PlwNTa9MxDRASfv2NrAaXmhW1ipmn7e7lOYRH7O9c4M3zZDgxgYMyA9dw474eD0rsSAIXXnLT3g+
nuL5q+g9f9HWbhBDBKJVFjUJcxQ0e3+jm4KM2+QDJ2OB/6yx9dzUVMObNDY9Q1RjwPxir0uNvHa5
Rf88V9wyf451aZUxlpmmXm5Sk3SvVzzpTWTGVdtzi7wWBkAk+C+Zh4R1VqrhRlVgyzexP8gtvRlC
TTc5+hVVja+VFCqyBN5NXNuk+SGZL6Ra9vsLe9aVTpJGH1yOAEMnA3D3+G5NbpkQm8yjtcdWJw0Z
AyQTCZZcdgNCIBvz64VZQpF8Waz1Tpp45VJxadxF3oe9pbO0YfUcAi+gwX7n/G4xdXkTvAn+y48M
qJNpj688QLaHntVu7lTgo6SdfRMxiEZqdTvjS7NMgoS0XYXaR3H3Dtr3VuSJu0cGTvIzDElvJSgo
mF5BHeICeoTEcdGdRx4AtTJ5HyxBziG3RqcE4ojzaMZhyREqELT/Q+0ZtezEEqJLXLomMIuTiHWn
Zatzx87I13RXc+txcTFV5vWTsWSTLZPW5bFNklDAIrA8uM4/5rM+GfJyylBk2aDQdB2Q1hUjPTmx
mm0mv02HFDauPszqBnc3XKAOgGknOMh1tkt+H7Wp5X/wsVaZ8R3/2rCx+OpYfplYxzxsiptLILXT
qNw/mygHWzaE5sOFYsuNLpULIiEICRLeaCflkiMXZc6raaF6mptqnKUiapE5m4R4TktLavQjVAYn
VJv33eZWvrj7Nk24xH7cNqgmagvydJvf2MNmYhd++95CgPGbV/+cFu/rjJpiGMAFIZOh5dALj+F1
tPXiXViX68lnbyyU2nB9uzGM3CUvKKuF4VooEIk4u0f9NeUB9rCdJQTCr52e0b6VE1zgR+Hxm4vy
ObcPRpwLAhi/uJe2Blmj6mqoOkP3IBNEunpvgyjYWNEhX1aBz8mdlj0yvPKRauCmlWTY5YBybU/o
SbddzQDX1nLf0ZwF1Jiny9n6DMgde2WQxOXwUYp/ETsMvQ3M5DeykYvq+vJ/bG2ZyjpxgHuxW8Lr
kR2Tz2docyrOcvveqO44ekkbkkA0uGg4D8arjIL2B3xCQmrUVC+i991dC8gIemj594hlusRW/ZHz
tSaL22np3bWQ3gYWS8zcU63znq62hN6z8a5XoN+W3DUUk7bfRHvcKywvT015+SfGRxW1y5lu+kV7
wV3XNUbNVFUNVsfCVICranWv0gg61GL8tQ7Bso/+wl7VfZRs3V7lzhD//0hHem/0xyqnOFvdZ8P2
99L0iU3h7lKFhksfvEbyFD3P5ACGLV6K/Xv9W1tqPKoM4UIDNHxsh1Vsl+ltRgUhwH0l+GUGzZ7t
FUiKR7pMM+Viv3dNY/JETLr2AyQuKzrRWEpuJIMBpETm6yl6XllKpSt+akz2OIyuIFUmYzs1oZn7
MQJR+dRHHullFGJDkMSxuR3tkNkWVJdvm1jWckbv1Yqb6U5jmm+WyCCfTSnA+T/KsEQq86u3PxkO
0ZbOi/W3rtVhxlkx8eZ6/Im226//XtIpABDUuUm2yMZnGcs8VG8jCVQFCIXOfXkW+fhRnc5ATiJg
GIJBKRdS6eqY7za6saWpUrEG1ZwBwhd1Hu1qFsZ3Oq4xxEPAuVF8xxPUL6oHu2utEYsnD/kB+rva
db9Q7IEb+nmyYpHnoAnez2g+WFYLS7YIHeQNhjZtBn550hQ4jGbHhpioDz/lXTTf0OHg6POeMp6Y
bNqxOcNdq0JDNZi9KMULnEMq8vPRr3CiFpBIs1Dc0rxOCyFkYXWqFQF5GSlKE6Ea56sUiAbjBVg4
ggQ60QlkHxZShbLXVGynBYdK2nWxHyZSnDAhSAxd/Uok1xAhwrzkMVJur+OCfZ+lONdXn2xIuRIJ
30BOKdjljy3S+KmvHFJ5Kcce4q6pLA910rX4Ck/8V44kzqsW/DilN5SHri+XGFyXeIffp3ytwwPj
pFO7M3r+rJ/hl9jT0T3hsG49EmK7iHPGnHXOsifoDXgrUxLSk5WpB1Mwv+5iXIf7K5kmYqVaD8Cl
ys2fUvumaCrLAHkRmm91fvHqbSrquJ3pHKobJBO09BEg6GOC3cMIk00+W+LYSxpJXunG4LDwOSxc
yS0q1SxBS/iMoUW52gYJWeqOUSgSXCRjILDVF0gIeQpp4cJxim7a9QtY+sqUNrLVIPt8NZDcHosT
GAUcGTtGOpVa/LErNn2PgN7yUNvsGbH25FHzw03cYbjhas7Jll8oqn3ONT/65AiZGR0mXQrAP1/f
LMLl/y5LbhIgi5tsNi7GEJilaoYh7ngnbynnW+fSMLRL8xg/0eZaVX7cwnjfXjjt5Ckdh7ALBc2i
aPCQIqilUR5SwebxF943RfyZkhtAe2MX5ngz7/V/HDSDUs9PdpmFjxu3BccL+HcajVXR93nWmG3n
u9v4I+HndVkEYhJnDoJh0kif1uVTKUmBJXf7GiFxmZsp3NfrvvfnMr8G5atgj3lF1D9xhEcM2e4G
fNK/4BdA+o4wsBtm5HCyaz7OVPCirGkI5I51OAZ4TMef3AwWfhRzPQzPteOakzibL4ZaUrFEDXrU
fpkj/qmZiXc4w7fmNahhEfOR0UryFCSwSiLyiiKZnCSiU8XxDgLB5PosOrQtpOMgaaFHAlSty5oX
je9+zXpaAnSEVkT7xUUEEAW/ipiwd/Gt3ABx49TibFr6RiI0O0n7r7XNC8EyyXRqDFWE98zy4s5b
LrmCdyv7Q7KiEXo7a+Ko9tpNN2GJ1kW9LJ2xzo8refh4l4HKYUxCOJW2rXh13vaTrDLAhE+lYo5o
ijVAvfxpjVub6YEd4vkm2szpG7TOj9luDUbFVVOTJ7R4TFT/NQi+lvETriDyg7UoOA/XdWa7hsYI
rRp2iqjfSMMfDx+1RmBquRPIOL/mCUDKnUIACNJTHLafdOT8nk7DrEe3M248E5/B4hj41i6yr/cg
QOYFDIrq8ZpWQ2ky/ZJrv1B8dwEl3rHYVHaZ1OUT6jlxwkNsCcpDkNhY7tpRXTC6RxQNjGIfTZ/p
7uh584w5qVTa627XUsdSacNvWQwQcFR43VjK+Q6lDV5CN6vJaQaTkLj1LA9g9y+c089H/ddeAUQY
7/v7nyoIsI3is3GwaHxx9Aln65EXUZJu57kxI99U70L0Unbf3YA6+FZhfEuL5VXy+/iUTJMbzgKD
VlDI6YjK3S0RhNuLdzYFJoKBCqLkNKjI9rpSqDVw0ie/TMMmu3rmeTUogE7E4jiVdwKlCYc0GC9g
C+9G6S1WLVtgP8Bm04+/EhDX4JU9uFQ/O0c+llU6DE19/TMsAqMSKiGrKaN2yJdzQNMcp6yvT8jo
eU8XzcBlfm7VMF9Tn37UI6gdphToKhvyJcOxz7S+CDd+Q9aHwA7ZnpHSrJx/Nl1kngnPxjQ7ZzHo
TvdngQOXT/qFcnNZEQOBbsZuNxL3qQCKNqOrY1s3Cp0KJpJfSn7FbjVSSD/Z1odBptEHHsdHbyQs
uDY+WO8XdbzFymYYj8hLaUuJM8FyR6FndcASnJ6CE886GzeKBHyn/qbbinx2f2+AummyGQxyJf7S
eTM2Vrss/xoWc2b7e5VDALncaHQUC2Y1+46ZYEjbyL31UmXzQLv1F1WJ//ThNru9dDYWjvJqAVxV
9GhstaTc92bO8VYspS9GnqdyNCFk0vpWV5Kl3X5a+Tt/XmNpj2NIDJD55RuuzXLLk29r8siNO6ch
ioV8MfEXIXhVv63Qz6If2TRsJVvx4A4yJDzaAxOWxepOi53P7EjkFlPuzp/u1HJy/NZJ233ilTIt
H58nqNc3Tm3QaUicO6qsA5UdXYJ0ouDP6TU9Bzis9bTThaoImRgJsjjJyBxtsJIHYdnAguez1uIz
/No+Q8ah0AHtOcBO9EswmGa285UbpS8yA5j0Jj0qKunopOOU7L6bEvxHsofxRi3JpswT/gV0eXb5
Tdgm1+DQyHOgDoGdefPHd6lkVYWmAdP1gB4bV69m1J+JAEt+kejAclQwTbX0HlvxjO/9qGO13g4a
ffmxxL6Fx5qUyngPGDQ+DGrWcTwnBzTR1DtykSI2tSdWTmNMOj3gIinXIsl+7MJ/hQrLSKIf8Fss
+uycaO6KekwAR323pkIBUOikDkqaqM3DX0ErfoL3t8enuRpieZHoK9qZox+VXE5BhDd/VDY9+mga
5r0E+OQar1JX50v3IkAKigKcqvU5Zsd2cA+jbSbVVEuHkAs234ChX0UfRFgy0Y53Pgpdd/HfFZoN
LmuTTcZN7jZaet4HykQqJ0SukAoLs36RDVk+pyH0b9gjmv5p+bDNWZ+S7kTfmpyVQ+HtBMcEs580
apauM5/1IgCg79PbaT8LlJD2Pu/HLMO6Rjw/P2laj+edzigzkZ/hWwdh5ouX2ckDjt4TGwnvzFsG
dJu0DAM4lJzqzbz8VqhnhpWsS86JoyR1w/ZpfyqM63qRtRkc/S8LyhLBoIc0dwXb0h/43NbYyBvd
dN4fcmHbJLLu+Atz07ejaPxsDb242pjyGuWApNf1/IAok69nyzaBFsdUu87mRluehAVY9LvQBSdv
WcMk/H5VZPwXphhI4v6AJuLHDjWFVuPwOkZEfgxdXTzIryV1ufSsyHjkGjiMdpfTCfMmK4pV3z1n
avZaDUXlRvojkp86Set5n9eop2SipuB7NdkmliA5wnqbBAkPjWC3FbJzZQi3o4xdew8WUp+bEYRs
1TZZNFoXq/2RUd4IKD9jSU0xtGtPw4uWzp+bcUnLiGqESYjHmCB7cDDc3R1seprt+VVvnPI7ghkc
LdosRYbfWQFMkQA+tQhFke3s1VVh7ef5oGmGnTDmUxiHEs3s+hXvUa6y8cc+BdgRx898HoALemEB
RvmS5MOsLtAkNtJ2DUEzMdrGBlUNiFV9f+RENqQD24H2gJx/eEZFoLNFxejUecue3HGxtacWotCR
kXRGwJOjzL4fdrz8kgnsQ14OIC4nWawJuyTSeB9amEbQ84nDlHvHsRZSRsgjozmTgjiSklQDQ15N
0ovo9vmgF0FgjoWbVpXoFm73QLMobdFAD7mVFnkKjnwAsS4Vr9s1yHsdv5zcE92jZis6j9Je31g4
a0mbfCrw8ECFWtm6j/dXg/EY0Am7wq1K5MIWipYu4hUMh8fZORrKcLVf4Bpk1LQGpZd1mQ91kwNN
H1cyiNPdBvQK4GXAV4diTkxvH9euVIEnnWCKO1WsAagG6Yy44hXz6QALtytZwofsQTK5+sBSjvxM
kt/Zm1D16u6T7JDHY1OOmWh+Pw6jKrUowjn+rdzr/d4U82r99f3+515AQe4sGWrSL5OeX1ExJ90e
mnkzcyrXY83cyfZb8dN4f9hBcpFw0dObZoIw3xz5g6UZDLUKFgk/dQS5YXumJ6xIlZM0P7iG91PW
Uh0/IEnOttxAaQr5aPJy4odLhDZ5eBwfoLlMSZIcEaxEh8Y2+kkbPo7lPbzxbLGHOVHTVuRn5+/3
SNwKIhvnMZZL8Riy8wa8uyriwC8ubLkpTDaUBJJlKzFNAGM9DWEWz942v5w50Qk0A5IsRDXxV+TI
h6YX1ymO+rEu62BujpQze3jcsAtBR5ZM8EBfhV8bje4j6jJ6OTIb2CFB0RZ1SdD0/IIXZMo9PO3R
BrTK+NPG5Snk8Bbth8UHmT2JFNHYEkJPjpFV4/dSmyidTKQYgxCNfW4mfO4/yOrTR+7WRmAE5Qeb
xtzKFAaxrcmjkYn9dXDQ8NBzloT0I76niiXPDwZtIfHJAwsx7AkE+N9uLXqrtPEVQyTF5jolgSVv
hHArpdbdlxc03ezYW5PGcfxyCApCpo6qjgJtzX0NKz30f2KXh07wpubO2zXTz4jymfFDlaThhDvB
ufv/gsBFbLF7NhqJo62ciitbutpEnJHxtGKy1NG5BeJD+gfNmFr5QTnXDZ9MiTd0wmhSzodSt7q4
WsbtQ4if/TiCw7XiQ6Sr8kQglDA8/i64cXo6iK9MyhXP31nXOC5uHDihFvBQd1+3aX2MuGdv1NCJ
f1xNBUA5Bk20MjELSiy6XQ+yOj0DT8rIiNGM03cMmGa0jtHzhqplZJbcugRu5QipS4/Nh6HGiTf+
bJn19WFsccUpIwrC5xqB81MnqghV83MooF4LR7oJFJDYsN0yAXWNSUySUL5/fz9/Otx1bhGaPe9H
3jMKgkijIMk9SEwIVjVr23lQwVrxBbwsVv0zPc4HqsGXdNPoEE7Xig9c4JxbwxDBnQz04w+myNEE
asY5XSmobzIgwp8AoW5XpP2BSITnRWf5xtDX71wy7nGNDTh/LqLFoMHwUqI/d6YZM/pawrvirIk7
8uxfIcm58mqIePq4jFoKNZDiRtdRu5BTWrSm9hNRG/7iFOFYG6UVBuI6kMLru31qOgBiQOgpJVYz
Jc+FDXpNCsvZExoOsxL6RhIbKqVClXUBjpx/6WaaCk/cN8+5L6lCTwg5SwwH4URMrmlWAaAepS3I
L7WDvM3jUrQhHlhdC7nZZXRx/4oPuSzGru7tX9SitY7L2idzfVbk9KCc/xUpNw2f3sZ80UPxyuLY
DIAXyZ/bfOONeHntmzsUCNJKfQREb4y3Ep6HvfFLLlLhR+iwXq4DOuRDmO5qze/eK3kO1xsC9q4G
HHVhIYDJDgSYIlXDGAf2XtAeh8YJkcV5wEB9sVWzkOTksk8yzz7edYaIjd5qVqUQiEryUwIpjj9C
Miktb2V9GYAIZgtfzZ1GK69ullXAc5MEvaG7kR577s7+a3AmyJrCmWWQWcfgEAQN3drBlMbvLN0G
Hmbk0HE21NVRLbD5nl/ppjvRJ6b+pvY0qOk5WGkLWLm7t7qAUcos/BYel7m0IChS+9rBfiAjYWs/
TzC7NvcK/FL9AUt9zm047YedG8X+gOTEBZHMhgZAyUAxiHmlV4EG4hCcZ0gRK1gb+mjtYflyZt7+
RpEkpt78Ddoxg1SX7o1bBE5gVvAfKhvJDh8qUdzXaMrfOdTFFoob1uMJ9ku4eGWFAJccGDyxzF0D
A4EASaICfbeDpnQPqt33zozzZ4fpUeqcqU3NbdyYNaDFniLtz5K9Z0qcgCmddH8kqZIY/yFUTsm0
b1fiHDM+7VFd++u7rm+DkK8wHjdWNQbx8XPx0PFy5Mq3BCbTNg5DAi8ojCVzItirTEGnMcm2nEWq
+TkrJpmofLerdhHAEeOccmwSm8Y8gu2atUq10pwTX+5J1kyTqFDUywGdPZjiVouZ0aohL1TCH6/7
UVSuTCkdpV+XH7axfOrEJ8SlzJv4Km1R+HWbow7HGzkXPwAwq+i0UYlxbD34B0KUBKCzpGnP6atG
G9wzEeHaXyk9TX0reI8nCRR981wWQG/BozB5Xy1Cb+HZz12ERJG2CyTugpmhP8pJJD9JV/GUvAcq
TyGwZSFd+ZLpNKuupEvBXxnXt/4IhQzgX70OmAhOLnABPPUOwLsmcmi/SRgoRUjOUumMtC5yUHBX
hDm0XzVYqsaiZKBGBUkquJVoy3EOb3Iz51AbTKgYR3K/gTRC9Np1lLJ4vGFenlZ4OYnFGLmqB1EN
nyCXuet1xtnzLTHWxyHkLFx7BV9WetViwJi6352TPe9GnZ7UOL2KOTQ/KTeS1euYJDg85i6sSkjm
UE56yG7Nl2gY7wLjdOZrQOTR/lR+Blm79jeeol9RxPjpbDX0phS2Q+LxYVYHh4huQDc52tSQpGl3
d7pqnaKz7lUuDoDnokO7aqabIP9zOC4SZeMGZ34HM3qRzWqgosWiKzIDvE2pVvhGHD5fTiPdfegz
mvqT5Yay4vzAtkX5eTl5ZEv6C62Aunv0EGtwWxK0OZKp2zhFZXqfiHdVN+POo3jav90jkgusbZfd
EBTNvvHbWcljXKfCkFgOwWAp6MRid+9sKAk642/A7fCEV5iKI31t6QyXcSIuV3hJR2LQ107IcqUu
5FoB9omrEsTAtY4PwbwvJh1pNmKzEoM4F9xMAGhTpezJ44L/SwDYmcdrx4QWBzZoFXyFg2FtObYT
m//QmZnI70USd8GMg+tldsp7urC+eDO2oe1qnwyFUI1PNIYP8pG1iJpMGziBt6G4Zx+keKZxzyGJ
SVQ9WVmnYJAr2a2Fa/1YoT1QIX05EtA+h/aOf7YxiqmwqGUNLRVMbCu6xq/rjXDpOEozRdnQKJ5o
cQZ1ICUcY4qdKEYIVLaKPFE8SXVOYsgo/0nhzvpQL7zEDDhrKgFW2/bNXZbPULyXzUSHLAz+rlZv
7PmK92KzF9C8YLxMYf1hObdUIr3JgrJ2+JzDCO44ak4zEkbysLvQYswOnn/EyIWSoBvihdbu6Vem
M7sR2p+18Yd5aaW7AkNfP/jGrMErnFaJVwDx7RH3i5sv8yJo/90JKCCtKh5RtSPR87F3ctR7qGK6
cGCkTIK088srZiiar1RW6uxicymHTkSPdXeBFBYRA4jeiIYvP000mdZ8DVOvY+iYERy9gle6/COi
VC/imh9iyKojBugCRbtt96v41zSANlLxq3ROW0R9BmzoTqo9qDr8khHUiYv40h1rqL1dI1bxQ0Cx
WITYyXCqG7XR+FhogyibTHDB9xC+c4dCY7AOUFnjZk3ZLxZ7sS872vv71DjNCbL3yuJ7XouEVuiG
CdRBg02UNinX2fUyu0HkoUVkjkvjm3l/dCRAnZKxPfRWEBKML+G9xyg4omNPxkuT0oic9I4zM5Cu
rkIjHLjf5huomVuFVOmiZkBW2f1S9iV5bhqZkv3cnkcUZFsuynf4FD2VQ/5mbJ2dNmPYL838OvDM
xCNGz7xhlviqFQBxvo7xFsGxeCyWdl5L2YyNoZr++S8S8t76soaQkTBAkHM84Lo9BlH1QxsTi7c8
hOMAe8BSWdy3kGxcqThMb82SDF70Of2IvPvXNCx9+BeSsgKdb9etC2jBJPc5AeeWE5J13bkBpw04
SVnuItHc7A0kExDjwgWimxS10Uvxr2yhEHmpASG7n7AHKKqOGvVfi0BLURUwoyOEwAxuMrWixWdw
IRfOnxGbjcTjyx7Yc8OB88NlDNjSsKgLVml5DxiIc3uRmNUcaMUNfKR+zqNqAoBsh6KuJi4jUOE4
hUOhMHe8rado72LLPCrenGhYhRFgKylYiCrbzMz/oVfuMunrxaVBVdWB1tYs2jv11CuBvRYR9GWO
3vjIOXp1wj5j8bg5/J7cihssE+HZ9TR0oH7fQ2umfRWWtlcijpqaGFOLS9s9MNX2FDrEwha819k7
AFTHkuq04gx8wSt7vX79bTqFwMNxBeiSzEhmO9bZ867CQie4gBYc89+NkbjMuUPuAj3T/qqSJd5J
A5oEehTUtgOKp1VhD/k6JkbImI3epJ0tNjP6CNGTg4gdudDfrRGyeqt7QvJKO4LlFykUcJd3zcWZ
99usq2Nkw6JpYIPhTGm8AmTJHIlxuvAdfBcLRkiIS2YS1YhpGmLXIo0oQ6IiKTG201ah51zMpe5a
TCxHV3Ap57tAj/0+qS1CCGCwnAQCc2VgJy5hUIWCXKbad4KGagMiu5mnRXgD2hWBoae0Zp2NKdGg
mO7eFcqtgVISAWDGR3TJJnyv4uK6LplCuuLn0WaFlaou9yKSmO8MkNIRhcSvqIOoQOkm1k2mtPCH
KKgWotr3h6hR35YG6d1H0NRwaJhacE0nuTU2GwMYQLmy+CmGKjqxnnyZ9tngDZJDszMUFi6geZkY
EijFDZWWFeG/W5ZSrKlGOn9sn/wgoWlyNedPJKPlQFVL9z5OfQKEQZBDORZiaKXzSAdLpZcUaf4b
lvcBsXRMLjFA7tkA9Blzwqx9k1Ib8W+K9esiswt4s94e/jQaDN09aZX0ldgD+pTvGd7lxs2hp2x5
wCuuWqG3L97AcjyGTLp5IbIgbRY3HA4Uk0HyvXsuTWv7xHb/r7ZQSjusL0DGcMZ7sUjFUqbVMTql
sK+xBLyP8gMC5RParpupkqgeBcahq9SQ63kCN7dZqI4a5Ak0xHgOiMGPbDAGz297PseCnUFopICI
24bp6r0VeUdJJPLfY9LJ8KM2rgWjwckG8CTLOtgMpZzhTFQRRL2/E4Y+UocIBH09mN20y6DiIxuK
4n5gxfL8jF+kQv82+WhMRxucR2ntbvFPHOWhGtrXD9wDe6IS8kBqzwQgLS5ty/OMHpcll5zT+M7N
DcOZ7D7FRBzrrhtUXZhegM0h4q1SGFj8zoEHllZcwbroIsdWJzdr3V2MUnbhmiTlV+s1OKgbtLgl
lHQB7vcxBfiRINo0I5USy+801uxubIJ5Ne8RMGTOz2HfwgGrT2AsXiMVs4lEq4wGLfOriFZltBkx
bzVkONoDKDVaxpvs66BuoyDZ+6YYgmAxPKNVZYDlHlZvrJ+9DQMB6WSVNDeAvPr7ACKNR1RVvQQb
8FeTYzwWlPp0scDSqBTUvURbzTHOAyINDLNAAr0S7HsHTgcA1VZ2ZLNrvJbkNxtmzEa6tD+hDl0m
ofpKc/LZSkizoUtIJ/0VY6EoOqMp92u0CaeAFgjkwBRxu2xPZpHG3n+hIXvl4tLlpjEZYBuhkVWj
IDuYARPRI4WCjggIKR7xWHeQWDzAog3KM6Kj26QiJHt08F/pnxGznOeL+yaDCcZVVCw27BhdjK2D
YLPStGUIxu+SN6CEyY+cVyjPVHhwSv/Kw0TNNtHlrwokhiQIWyWi4ii/pLnDpwS2VN+Q1O/kZw61
eKYwRIHFvGi0ZOyphZ50qXwD6v3LrFcGtCBV2w55/7cdiqe00rB5MDuMih7s6adzm5wGwVop7oXq
JlxUBAFPqztlAhbCD+0QA0yA98Lzkih53im8/xaMeGJ5zeAeghOsA42YewWslWXoYJMLea0/mvFV
qmhIc7cqTfgU6JUD6Navpdke1Tkn2p1U9KBj45UfVGAX850Oh8DOWmQrM8y6R97RdLC0sseMJzRS
Qg6EiwH3uVOvSHaqKpimHJCRNfhaFyfAIQcGI/yKa+XDN2WnHskhqMv1REPmTCtMa4h4pruttW4V
XQjoDZQ1TLcRIN1CpQJMCw3ogCGs/HCK3jo8tF2IhVSJUeTLXlYD51c4o8YrMQRzBZ3UXwW5Xs+P
rZARJUCiZ9qMSUK6or0iPtzOAexHIm7KgkU8J0A0z+ZieFq/NipiBnLGXs0hou1D/Eyp6+We27rC
vEaZXNErRiE79KgjhHucfpbf9mR+lhCTVz7h5aGvyWuh+2Mf8WnlWZjrc7LciB4lDImAd8Z3TGQQ
lY28ejpnW7wsh1TWBl8b4tQPu+p7s6pQPIr2CnJ8xU5UfF8J5OX3mRlBhEHSuhgV4XCFeSIHu9oV
Cjx15kOX0fBbiVkPqVuSF7L/7w1cQNFTMkcq8NqUmnidGElzaPb2ASlJn8ug27F4mex/4fA5BCdJ
JayzDtxUzwppJXDAvezrZY5t/Mk3pcoFHfC6rHBroMSSHoFEW+LStR66kDN3rCSq34vRktNA1Ww6
QfXqLYquDPPpNjXASriSKPXcrZ2NLCiUMp6Ja9Gf9M8DT1FaotD8akquAiJzZ5415TUsRR1dPu7x
3pjN0clUzqDMoOMMjI7k5/DHcQ3qY/d2enzarhbQ0/8UVHYQia9mvjJLjDy8ioUvu9ZZPDulhBqw
6O4fyovn9fDXrIqp5+jY17kj8R8BheJn/snQYwD3FDJ5kdqOWILpY2WuYAI6RMbg4mWYYbDkMv0Z
Sjplksvn14UGpPhwID/OtcuqBh5m0+vCOa/urNVsTLAuyW9LjSmwVfuptgvm57XnIu7nnNXYTM7A
gTFzrjprrxqY+uFY3AZCOQMnlUKb+A8kbIuMbZxnex3j7RB2jJYOIV3ngxvgFo2pw0xU3eQd9gBQ
F0xF5MVmhTpKWB8It6jSymAZghH7DXikUigOHidHojvtfOgBrmLtxJvXDaNBMukzFntAYps/7yQb
5u/la9jaA0nCfgq9gBt7R4lASGr+pbAvAYM+u5XLD7hOHqRzt0ECXwJvmhK7JeTR3aWmN3qsi9c7
HFJW8wZpt7oM5GSgUQ7dHboiThitlDapfw7PXcL/eEuRP5hQbqK0QYszssRDgWQlYjMUs0Y+Al2y
GE+HQnoBFiyTIVMYhBZMa0QA2Ij+yj7BVE539YCsSARwG8frAQ0mBIxJDnnxfKCXmwQAqQm5IjDj
tDmruh2WKX1lCbol/w/PUlugcQMXoKGwv07wMRX+QkES1v5IyC5NtRmKI0rWIHPFqLL6fqArNRjn
AdiqauXKRBt7fbvVnp1wxvhsWEDjeJqd9ow82OaqcIep2oZ602OaJ2pUZoWS2v38m+FDZfvHYcvW
YzoalRpHKyHWVNzuHsd1HXbuHqzW7V48hvHlzmVheivKWZK4yVgAwJ9xWedc74YeCwBJ04H1TlfH
O0jUeun6Y/dq7/9KKV93HjMQFL+UwRgWv1Nz7eqimFIxVTK4LXqsR0nbfOkg408IZzdBUJ3muLKd
81tlJpX3uzWG0rmA/rVVqe/sB4Y65pyJIQ5q5jcwalyVqQS/oAv7pxAcBAVjxGVEHw0xP5UaOlbU
x+2zjhpA3NgJqlvmQwlNVWTrRyxRyPuMNcl1fn3p2487Vz5vmgD0bsOHxVy+8B5ebMUVvVQyiOqr
rJ3C3z2mHLrQuUKbq1JUeNE4QUw6FWRsDIJxaUa0RHsk4nRquOz3Umg1C9no5uor/Evl3RGkHUie
pomQcsNL+Kx2DcNN6aHDooxOer3lzdLqZL50vEeCJ0+FZBCH78L+2nc/rTIccTQ7HOJIXL+5A07s
dBC4kdIGSO1ayJxPwlx1pma7YHgDO4qeRPmvd/WvvD+X1ts8Z89A3wLyErSo5a6HSueb/trZD5gi
UQFWPlFuSJRD6X4GwRKyMc6nLkG1x8XjuGz9V1eXvrmZwhNvdJKWBAhLZzCvzbw9Spa/Y/DAvbod
U7Ejxa3cRjbOwvaNMzDUOed0mLO3WvWSYPUVHakbGyNzn8HR+A80yGclVdreqU1Tiie+imuMOGSg
EuiTjVdPQxkREq/FL0aIH/9h3Q9sgvrMnQlr20MGFRn9Ywz+ewHKSBJaE+sRGpkeb4WriJR+albm
8Oy8UNSPfeOH3yEBbi1O/fa86CepZhzyq3uCPtSvQ7gRW7rsHubEzRODEwa9zY4V2Mox7sWWM1Li
ZLS1fF2b6GmgMG2S+kEItBp6TQMw+YQVEtk7tYD01ip62L4UGzB5sCnCWHUpDyncySuDucYFd9Jj
JJ1wkKWKtiudbQaUPuvxRNqH06AmXsbp19VqUdYw/pzxlcI/qYUCU1WpwlKTMjgqgPeq8G3o4yfc
8SJbpTfoG3Q9TtbtgbhLBU5+NJsk2T+umHfZ7MN9eSaN8k18NTpHHOHwMZ8E+2UzD/ocRTq6/jCd
Qk1bHFEtwJ8x6hpRar+C0PiFDfkpvt3i6n2AVZTXuI5XaGqayA+2l1rHgWDZEL2RwkomlN9xyub4
gdYaJpCC8f+5VkK4SmJ+yNImqSXmIWpVzcnaWt6t5gqnVj3vhG6zUk7k4xkicDt/dODp+34uOgKP
87KsYWKy58q/j3MiiNXH2MbFjMB3APUIV7H1RK+TpnS+G7vsl2qhOoOlpu2YFGMmOMRGzSAi6qwx
/HrKrdNQJ1thJf7smw9KdmHPAe7Aa55Grlhb71WtiipYB4gvX2GWq8qlxi6ccrRzvKzyARKftFs7
/e5bjRDhEAwnehIGynH0s9oiiggtwjBPuo+CziWSMOmkGge1AAt8eNfubM31aE5eQUnhDXPTrdRp
NfEAjBy8otVrM8pDVEKPKXuM/Zo2r78OpHvMkOV4HDGWICS8xZAVVDgjwTqfrJKtiACXHThdi+jQ
XEiDofGAjUXWxec4iyJ25c4Hm7gUIjgG2O2AlhilWmR11IyVn0t3eNlgbXvGh6deAPRP1oUvWo8M
lSdFhbV3oUbjz/TBp5uxRWrPXsLMUEqzdWvbcg8UcjtnBbyq5ykjVQHgGYFekbagegr7QM392Uf1
4wk5dBKO0O+vymraNYBhWduEl37MYNFAT+17zgaUrZFN2z9rvOf3mUotAFHQkOhZXnzjbFFGBSei
rJbNgCLf6neSRd0iptJ71qcrIK0lPF8Efu5Vx26yWSlGuizo2pgSWl2awbEPZXXOapt4vW5c7hqP
63IF7jKxD5Cwa05fSvqtwLdZIOLMF1eA0YwUvSJVx7E95gp7SXcUymy279CzugdCCK7D+I2+DxKO
D2yV+5X5SfM5mmhbt8JEj31ycQNfAEcak2m3PM+GpMEQQL8MVH8p0htcnmnXg/c8pAEnjS7iIKmo
X/TGUveC2W3t6sJ7foMNn2lcAMDS71lkJdYF2bJkJoSrE2QrigLUS/q9MZkJ07cuTClIXZvWMFCC
8QID0lFZQLEAm9jvjkd/ylMjh78aonb7RU2CZyahJMPqPeKgsHxRWOmLw/JTg5iGFdklFuH/M4cP
CNPlYJHJx+YiFKRc3nLFpgwH+GG131/Z
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
RhrbwOyJB1EkxOJx3ABqRk3Va+7K3EJHZVPGIcCoGsSMnOOGWH7q6VzPOfjcK/djKPO6aFBoil75
jQwswaRRUQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
LCTlbuF/Pe5PDxJKJwDmFdDkdDk19GHdt378mO/YQltflOygDhr11gCVrBzfYS02NHqaPd5/bySu
7JQ7BQOeRxRaz6kOAXIywiBhmVX21ozJpSD9YWX++cpoX2Hzx21vie7VHdBuVCd3dcSrAK02PIh3
KQYQ85S2o8AzlKpsFk8=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
o83p4yh0oTgLDG7Xfc1wgs4jILGH1Afuo6ZEi3g5oOtKQrlkia8l0l+AzK0CZN6geQVbN9v3By8i
WzYycokm0wzcIz9ice0LtKeT+ax0xhsgQnz9Qm7joJjyaXidfkKiDSXWs9qUO/5yg0ocMCtuV6Vy
X+oPc9kihxC2JoIOAIk=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qFbja/sHwn/4C9HJKO6mwiiXixbKvz/pY0uQwgBSvdDvsJnVpURPIZcd/6cPrjI7jCb2L2ZYUxjo
OD7e66fAIQ4Fg//zuIIx29BHdcBxENfBwvxV9WMdbgO5JbeM8TDH7sUVg1FYVW1Cj6XD20DFLK2d
vwOuv58tfuLH1qA2IJy1LreXjKAfnSYwXNNgkWsLHf0HNlF1BLaq0ZYOS35wQ0+LX50oyZIXCr+N
JkR13JyuCDomGP7fERuhdzE04K1CdRn3rjEcsxYOwLOnB0SPSbBj4lBx4ONU0cfvWBzoVcsVMIbP
m/ybAvJlXM/GrDa69R8Y8Ovx05heeJoR5H+zQw==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
fvKvImhKuX4Y0Y6AUieBoEW5oZj1O6zYwY/+HHrKkKgaM1CnSrcODNJTpm8quvRi1mZX7OA786d3
2FySSCAI7NmYiW1tWydoja+l00gQTFMgW/UrwN5E4V0JowxqUF1iu1epVZ+6x/e25PvEtYJ6tlHd
B50G3sCwsdy49pORs80wHiIjPV81HJpnQ5cU2wNr9Sym935FvXHSrzPAmhKxjh0sRZWkS8X8pJFE
3vES6QHURg+O3x6fyl1zEzCdtoS5kk4U4rMYiK4DGLZiLIBWYSb7RUzVsPxP0Ad6390hx+wSZ+hX
AIvESkLWW8PZxdjlqiH5uMh6bSBOcXXXu8FeRw==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rx21WDVFigb5iRNmq/GF+n+tT8sAt0anxbVCjDKiva2zVerqHXLBxWwmIo8ZDwgQwl6kPSNATurf
wsLl3xuYZbupRQiXSV62L2j7uhoTg5gdexW3J3ZgJbqydyznH8end92RJqs7XFidLZ11oY+sBEX2
WZZFU8tlC1UZmwKKu4UKUHOIm6wu0Nuh+yeD4yP6OiKmRBn9y40bNX6p56LkCggypHithHpqzIuX
hkij3oeZERvwFCR1LaKtiFF2zdqXORGlBWM0qYixWDF+Q8LzHHgalXIl9W7A8JdruB/VjFtsacGQ
bADNP9K30JY7Cl4D9OCU6Jq1EhIksCcjUkhB3g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 119040)
`protect data_block
aI7bWNlUNY7c3ZGc2pBm9hopUS7X9dogWjraYv5tIlivzz9gczwsyTYslt2YnJ+/LMUD0nXdKdYR
pIOJo/aWGlROGQNyxtDvDPMgCW7a4DPe4d2FZKyxCYU+CQOcwKyYKPMu//M4Nk07v5nerSVaQ7Le
OdKRx8fLib7Mqz+v6M2QfuG4WiAH5mEZMrMYGvNc6cM6lzrDDv3Vo7a4QH+HgtmYndaMRsWTsgUV
LCdDYAfRyVZLLHoT5OUk/Z+g6Wev9BpvlH1harOy8yu2V1ObxlXarhHEAUtInUsg+xmZa3/gDaEd
h0y4u1D1dYYk5K3bwsKZ7TqH9qG0MuGogByVHGubD9Wbf6bbWI+tfdCRfFRkuAlRANSEycVNfo3P
dvDLoCKNv+fqlqATA/DirJlE4aeX1FGHg/Sy0vJnD4eqTf8y4RO34KE6Pvb7M0PRmAy5XsRDV4Zz
ZUHzpVCDy0rQl5XPvf30t9DFPzgQ6FM+B8uy3eZDgxX+LPa3HTzWL9755yXRXxMtu8bA+7kuAIQe
w2vRvE9w3z8vs0PKdYqKQprhC+fJMG09cL4BrJdykfHiJNBtr/bBq+WSSVPZfZb3NZri+LVtlQ5W
jHJMYlSNitgjITDwAPMvlQQPz629GFt5O2ia7KgOuPF+6iQuXxZY1RCnj3kp6HEugTHcoaH4w7Vj
JXDcb1BaaqKm+Yai4kOYJmC+zhD59QujL5xgv9Rck1BDQgnz/s0hnxDtXCAVBiVUOinMSofPVpG3
Oh2elmXIbFm6Q73lpwzNFJEtQl5cQRg1up1wHrTJ5aZHJSP05vyv3UJQxKd6uQd/o3uRyBgiHWt0
65f89jvOJbql9IsL/CjV+STNpy9RICtYTtbzPVXcxodX8MKdhg2RA8UC+WYoOGc2lMAi1lH75FC4
LP1jaW8BNDH7US+A58TU+vyCzp9xaemgiaHwAYTUj7Rvh/K0cljdPIW+FZmDXdq/YiiR7yHG4S9b
UwpePm30esrpmCzC4N+NWeuhdgHFuYCfP/IfyDP2jtD4vyiEB2evaMbpsSMPK2jbwI/thbF5ZesW
FOFifXwxCksovXO8BfY8ss7Wtmwg/ZGOr78cnYtbJvTKoGIFklrHDTzADmyqQVnBclXwVcWdG/oL
BWoUPqGuQ6ICIW638WeVvTLsShCmHFhE19G8gETeeBqmaiN9OwIuBx5Wbh4W1V0HF3iGSe3rGRxm
h01hav/EkgtONJYaIq73OYEH/5d+BvW94TomD7n4YQvzARdLreD+xrHNKOlnPBP7mWiNiRpR+MUG
0utyazgOV/G8ymwzMEVXEavYeXP0sVR9PAvJOvm/56pM+q3i4iYZ0qJbHgA0hoKf8L83AghefJwu
4bYMPpHTLsAAnMLQsKtuwcLTmYKsiCZBl0lAPGoh2R76nFVB53R9rx1L4sKlAbUV2pxWQRGDpPNy
IquA42Tm5Hc6cLxV22yKiugnVBmKxq3bphkP2K5Bf7iHhSM+MjJJ5PMtMS6C6bQqdoMeV6Gt1c5x
gl7fcm97rx1LiFjx1m8K48Mznqs9zgH0t4NUU2QjTy0gNYiTx70fny4lBuAHVAknqUvzZqUKfXrz
D18b/rSoCRLFHNo6zLqi9d+6PsJSvctXBcm990cHlx9gNKrz8hKpbLQLAeLxtIq9lfFvSesEVTPI
HAj6jqi818uv+cD3r0HmWj4Mj6WzLQqgFkEUtfB0vUl7HKzYdKaTcDq5aSmsRj8DFP5Ry8K/c0VF
4LTTdrG8vPku40J4p6oH6LDVs8n6J0+FPbs+B8cPSJJoF+ebe9Fg1xWIwNzRVYS3Ren8vMxtjka1
nX6eZOa99Ll/+gYuxI7vXo8L1LhsBhBUyOjBvGjZOZcV1VqwqYvuLlUxEwsYWGxl0rj1cbHiaJz2
lLq5LNQKn0FESAOs620rUNwEtn08Z3Cg7VtBd+SdFQomlmpzyDGFU54j39yIKP7EFPhB5FfSzIUU
lsaAF7qCCucRTipNYbD5g+vmeTiD2X5HDgmgoc3aBw5RG4T0/CiZzPBNIcz7NFNyTedmE+1HJI3q
x2gIoEqfmbTKzw9h7pokjXsPZB5CplrStcimcWaiASptWEISNoonrCKFffatvIbK/QVumWT2yOrp
J0AcwsaExOxt9CgrNtco2RZrszF1Vq3bTB/KLwQATNoNYR4N+S8WAYfUyM/CK6dObGw6Nzj0Y0ML
6eAztsoaDfnsVo3N+gVIOFNA4Itc0tQA/dWMeNt9phrAX6LJqWZi48I0rjpIw1dYq/LGsr0M0D0c
ZIPqb5fWAf1fnVCIgr5MP7QIncykiPJ7Zs/J2Lo+gLrGCs2FvhACYdl7ub1a/Pe74Pn3HdytiBsm
pMPA5WhXo9j4nTnt1/CsELRA6JoduqGWStAQdcyr8GUWo0Bg5NrGU8X+9R3AXd7L5F0RDpqOxblq
GldFv6ZaB2uBsfPqNYtiwonIPClfUYbvDFUSzj3e3LK6by4aKV910o+qsaBtfkOyz4/i8s9ETCJG
RhYTq3EeGvg6Ql/5zjFyslGTZm0C2vFxM6V20BttR1vV6Yw1JA1pLBr8vod6tDA5/2qgRWN03r/a
W/tswr7+KaqiOW19hmvweCAGiHkH+eesnYCTZuzfwI9HMAwhfIdikIuvxv6k58vS42oFcO8td5eB
EMFTLMcmiJoXMbm0nS0zbrZA7GogD5oSRH02bW8KXeT+T/GOrPP+MgGxpSr2fWe+3tUXIXpy2qG1
5zkweA/aY2Dz+dPz7rFEUnR/oIQZV9ngVa58o0xQ6EcbmhfiqCPaa19WaMFnon/dwIs1E7VtpVO3
bHgLCwXMoizr3J/ZZZSy9cdUr3hdjNFqnOO1zgIrBbcU8b+rTr2Fbwkr3yF0+iruXhYMTmv6je1H
OHoFYAfzrcvr2K0ha8TOXU35kQ4iHSzKXOScp7FSWizIjdrwoNDg5STCdV8YRLVF+QClpOeNuIOg
yx66l7Ok5OATJdfxQymZNxhDrLM0PnouDA6jJd9yrDcrNEja404uFQEB37OFNhNSJ+5/OVnXB7VQ
+v3kBBU/iWLwSYs4+JSQur2H/cHVixyHYBKWXgiH12k4wNOPhGRx8sIxk+xZfuHhwg6r1LBq+2L1
5Nh6mEx58l4tJdy65zh/GexHxdBFB5eZh5mBHss0MrHZqu0EL1JgiqbSzcs3QX1xZXerdyNUnbHx
diLMmSGhKR+ZLiPnx2cItejFRM17SYDc5t/i5iCM46Ei0I8U+v/Cpe3Yw+OTdNhvjt9QQKuhLubN
8+pxnX7eRCFN5Zdp1p5S1YDucsGnYI0hudU67Ot9mDH9N8Lh1Pqlj4OnUoY9ak2ZMC6zESPdL8Ey
UyFwljmHNbCd2iH5tutiOLc5qkJtgjbboZj0bWEo/8yWvQys7mmp5Ts9gDFcRPkpMkizITlxkbBC
I7VGbgagUttzL6TJgA5+T3YcbEKDbYjLMFkQL3LWljL2pvGZzF+HecWv0dLltcGqjlQPmUPwJwoP
bq7lF17szD+91/FS4YDEAZhRJqORL3uz+o+d/pFFetxQiAImbX7IZ4eHMCYV3j8XIHjyJJcKqTRB
0v7pAPV1bX9yb0dOZ2oDwf8GPRGRvo1RRkCzhwa5G6Kfn+ScZywr4IGXHkQ0Pl2yRTYEdC9yz4qU
3JK6lKgqmqOcaLfp2YSg190BzeQeJsEGRf2A9cHdZkTakngKj1xHQO9+E3uMkJjJv3jXho/aZN4w
EFaT0XYgkCEfU7oCkUn0Obv5oQ0oCuxQ1PkVL7aqeiUL8QhoD0RkGOCt7faSpw/tUuAwvBA1icKR
Ia9muGExd88VN3TjbcvaTruYnCZ7XE3HBNcJw3UB5En6gDFDGBJ7ktJpAHTBQ9/uFawBi79Q38VK
LQYoLCn4WODfNyy9Ang5RxojMcZcBXSziKyZL6HlQ+9C9kitYesx9juQHr4G57CoAFBteKlMFrxr
Ki19ujOxu2lwnESO6Aev4kvlg/8tB85vt4cmG9l1SPPNlvi2J2eGZVBFRyTZGETF+YrdMAmV9s5k
95hjAWGG65R1rA9XQEImyazL5An9vwweUzsbj1WSqfH9KSHE7cx+y/ONtcJ+VeC7MD8qQCaEUJ3F
rnjSXu4D48d8a52/deybiqEp8eQaZ3wd2TeTs96gE78mlWFy9bx0x0jUhfUrzOlsW45frs3YARbj
p3tKehq3Y2bg2nF8YDaRYpiRTFYmVWSrI79zvQ2BI5j/RONzH8EwiDVNmjrNeC66AXCx7MKcp7ET
tsV27AL0GYF7w6bTTv4yLi3flNr+6MkIJUCVBbvhUMQvGYG70rZ4uK7uxtBpYCQO8KrJjju/569U
Cl239/ROV0qTn5ieoy9xqus+YKR7QzooxY4jlxgU/Pf4pJeLsrfKtqepWJ6KgNk50/9NtNmBjK78
FVBZbN7INXVlcgCWmiTh7fPp56wo24PEd3XbrEbtfPprjr3HsC/dYuhfaTrpFSy3PrtzeiCkanBX
JO9TCiEWsSvnu0oxEUhW1g26Uphm2zTw8s1+3rI7oRd06bkcivoIqJhXtv2F/fnGGxfT/1jCJlm0
BkscXgBjN47TLc2Qk6fVYhUMr4I5F99Poy0eG4IfUqi1lXuSg2bQNI5HZLQAhdl4jIWh6z/REovV
1/z0OCSbudd3tqClDYwpsefk6SYLSoWDH1Yb2NPlAyi8jkdsXoG65kn7vunvc5xzeEU/FXc1q8Wm
vEUS/F6faHae3qnD4Hb+jo8hzZX6BIhTyVfootR6yJccvZRdR3tUzNMUYTAe25WrB1lCIGh//7gR
n23/fOPm7fNLayIqxpwOLwJeghnqZSljtSsi3EE7aY+we2wS6pRn0g1g7ZzhRJD2r6KzBKLUIihR
B04YZgM8wcX2ddArD5ZrwNvRbwxuYj7vu1cWVmp6+sBD3bktfkCqhIx3b0ZF8a6I7h9x5V+cGjKK
VzkICzY8350nkEutXEIp/jwByf9Y9hXJWbaGOxba8lF14FvXU8ZqV9H4ZWXR2HwpBafxkQegr5cd
U4XIiIpwwvMwFDhqgRe0S0AEvDMfhQQ9EHyUDH1qffSqaUR0nc6F+Po2QJaK1QHzsPxmx5oHUzFt
a8YN9YdPwh6pg5NqNCoxdogyx2uhZx1j0uiKuAcmkGWn1WvucC96WzfMxLSbNhJnopWQg3eSoVJr
bDJilycM0+Wom/CwM1GC5IQwEim+6Q+NTtsw7m1tHCvmBCWsF0Q8oSxw1tjMsapk2RY9l8j2kP7w
6uPP7IQnHq+ha+/7N2eMjYhzouEtL29A9/4np1XhWDgYZ5pBJq8DDRSGOdNJqcy2HbQE/fKTDfds
FAc4yACFHGG22yxD5OoD/ibLGR+zad4WSIKT4sb4b6si7wXptvekygVLb8i0/honnC40zopWpEQb
/xVhFEh34169FdeG9mW2s88L3lQQGS/NkuRraV4ZZkdZTZ//nN0XanGxoePB8TXNjK1Z6HSlcX2a
f8yrVJs47WXgj/pWPrDawMdEHeUGBecMfUmgWJIDQ3eGcihaz3XvbDz3GT/I3WFcElGFWf2bmbV7
esBQVWUzLrQk92AqueeRH0fPz8yK9l6Q1oISDVMnP57DxhaXlBUINa1tzzzY5CcG9DHKYBUcT96T
idRrxNJ3lAlpz7g5/KIP6yHgvhJYxpdrPWQNxVEOqjxJM0jrLEYcnPBteFE5j5Js3DO1vp9JGm7M
GrH32j5berycy4I7THaGj702gmwsv+gomgl28sZYBbD+MnwUnJZmWjcdltvosp077NXZH+62AHe/
RGDqXM0woIcAHEQf10BZEr03vecsHCFKE1PbSyWKVTw55qF7zfViwvHbvsQ+cnzbGqGaiU4yuZGO
tqVtc7d74CcKkcuWWqyJ12AtceV94Qzox0vj6kdDx8FNTyG4x8hFluzRdPPOJ5JTWsI0U2SdOWwg
hzUTytZ8MBMlogWSArWswaPX5TwVEgcLVtTv3STzy3b9UQaT3W3gZg00LUPXQJ1dyMyHf9T4BB1E
YzsLJkfWykMFXRUy9Kzt3fBD5qhFdL0d+ow4Qj4SaU2p9+BNGwIWNnjmvbzimamM+FPk7CYsmg8i
PXcPDIicie7+xEkq5LaY1EdKcayDBjkFHxKcQyQ+1Ul+I04IdMRXvH/s8bqaMxtOxxxfrIl5aaDl
6x6U7kaLTkJEwzi/X19JfIlhfZJLQa+fy24n70Eb8fSBIbmSBedmRtj192zN+Pc5UCaL/Eh1MkAP
k17rsPlMxQXGFk72T0Y+4mMK9c0c786/bVPbHAsc+jlu58vSatBET3NLH/jPNRys55a6f/vihN0F
tI/3DYEjdKl3Pvx6JUcLAcHWVkSf+MV68XgmCnv2G+tPEf6jJvORsExBvM84QhEoRgqKCFsV2TfM
wuSVa0OlFShzTy2iZNd46IEu8thpoQ83I1x4TceCr481lKbmiO16bgXt9u9hApDkix35vY08jz+Z
tLZ9zwr4hpjvGHh8/WDtkQBlJw5Bu/uks7BbDqIZAmLq9UcMtT5BsfkleyJTYGKRmuSLLRn5qpOG
3B4R8YT2AsNtakYRh97PQcIwQAkWCa7PvfKHGyAlp9G4IlKH66aYAHWVDlxMtqVcDBXetY7BWclc
8tlFzOVOKwPJ3Vy97TS3AdR4nH7Ga0PcocRdGMk7YE1z5M+bEfWPG5Yt4Ou8oaEUkuPC8bPDRdzZ
VMIJDc2KG856QKUJnFAEgJTLV3zHwukr4Xf1ip2PrHIA3jtyBXXzKOvd58kD0xdvKJlmQmZ7LSdC
CNzImHzgpH+n6OniwVQvDY71qwJST85PsYRzHzUkpUNyF8UNrNbzdrXfrmCDCkPtJOYOQjc2hHc9
RC6OJd3Q4eXz9vfuIC0Tuq8sBlQ0VC+QTfKZ3Qd41sWceMemw7GlUjiZ6O8+YMOwL48/zi8ScvTw
KRVzz3qWtVoK/By4o4K/QWD1BHZzSpNrvHUXuc/7TvYj9oeluYYnn4H9tZ38PYPjE6bEg5z082MJ
usy0WdhZPuhNxI7U4wbUkOf+gxajXOQ2DNpyzDh8XGSXIb8FRNClrYWQJMSQ9pirNiA7vAlxFvqm
BAkEYzh+JlhZeL0YJzfomofEX1DOatO8s7ysexTTovEnVzm26AjipWiPHT4vP2mRmYHcfDZmAYwR
wV1xPvsh2BPcbVa0sM2SErEXgOQ2ESk8vRxw4I3+q7n2rQ1NrkHBeJrveRcnFfLUpPbrUi44Jb+A
LH2XeJoTeZHHFkTpL3ejttjiKuCE/sJTQ6jq9FKZJcmMJVqftLkHCaC4hNi4ciB4vk6xuYzzU9Nz
8YlkHDfz13/5zZnmr3p7sjD1ZqiXnyH5H0nkPkbtYGbHwKDYUa6dKN/8vr3UgLZda/JPnKDacNxg
OuEmdRcZzyJWix0ct1OhgMMDIBBX/FEEYzw504SgSzbrZynHMmm9O90jPNH6yriqJLwHxZCsJXeq
wSU0+q4R27w+C6hvYzMgZ40/l73kMujW26bqvuuSdO3p8lspsG4oZOTK58PiGW49V2uhWRdZrpDc
d/PnPzVLlDghuUc7QRz+0gOxpNkdtJVx3Xznr4Gu011/hqiJrtnIfGh7qaAJbzR1Jjc0mgy3KhnE
7FRXIVD9vBDM5sm6tmLUicj/nfCIXRGb8b3BTy1j7Q0P4TmAEQvLLCQDeCN8Sscr1JMsAuCHE343
ECJkCufLaeiS6Jbl3Fvb5fr5+pzvIXEcvxxV3jqx+Xsr1RuYg4Hi5ucChWCijJQB6SbXjRtBdX4T
sqbnsQ7gX3TbNSYqJ4mLyMDIuOyALj+K1fUmGygqNbLgZOXunUCmoObi7j9z6/BIKJYGBAmMiN86
4mF/acgqnaLS19mg0jz0dX42CqGbjcjW6fIMTt7YTpPJLC1cXLOlDgeOcFku1xX/OQovP3DBrJXL
ZIC/2H4YPA2zFExyZNYZw68oqYXjTU6T+quxWjxNfZIhqpv5ksj80mOj6Y/npijNX4ioAFQQThb0
hNkER46/JitttNytSCS3htueteG9WLcMTuF73CM9pRPeOpImc5gBpNJzy2JJLNBBO8lPjh79zF2m
X/tBAFx8rAOzE25NBEW+8w5txt5/eHPgCk1diRQEkIF9ehIPp1if6JnTv6xJ0lSl4k4LpZ08KBbF
ts4FaCGOR/w96auZ2OmPTTJAl6lIGxKDVWiq4s5SXkiXhJx24xj/uZxm2XD6zFCI/K0VLFrZnQLI
9r3qEOQ6ppmQ4HUn+CCIMGOxBmInw2ggdrhsJpU1pHe97sNqDY283o1NcVGLLgkPsqAtOA91tRDT
0Kcb10TSCyGwxC0mj6b1UV1G0FA7X9vvvMh5/DbEjKySYeJ0mmWV19iz65ae4hymVvMQ6pwirLS8
BuVwbWnePtnYkPgbVSf2/7i5XGqqGuHIG5xtSq1lklHvr6UCMwTFHpGy9O4KdPXu0nfF95rLg18f
5+N/V20jLN2wFpp8ghVnLEshKl8ZXROqfKUrVyAg8cE69bKo5WS+DEF1geTKD9EOYhQ1ak7YQ7Ur
/p4/DJV+UTqZkCIdbN36u37AkHjVHhavXZ18Ow23pfmN5AAt1oMqkf6JPhl2YYBGW+BamrpTwIgK
m+8Ggg7p3RuefqqzoCeLftKykmtiIRo2OFvwBGyWsA9NAWfJ71vkaJmap4ztcL8+9ZcTk3gR/SyW
T+8ArRz5dBAt4cmaAkYlOEGHwk7opoaMFcd+1/Z5lWzMXtijCIH3LcH5LWv3XHGoRCA0BV4pdgBY
rQru7DXl0jF1+qb78c/thAIjH6vxOAZdEGXqd+yd39ZREBYxPfOUxL+5vo5eOJ4EoZ/q5+OBxYpq
ImtQkuphewVyWA+HIwGIYyM2tTZ9GUNtdwp5bXJBf8Wnvqeyjo0RVxnc9VOBU1mD+q6gTjEMy8q1
HpvJGXhhJutjSqdBA/gc9jgkov46n2OPp6zH7tW58yPEZRxJ+6hK9GRXlWWt1GilIjBs2yAgLtr+
r1Nk1QJzQQgTtskI6227lNWvfODYHK475Bu2OOizg9ebPVhRWZ8IQpjEGJRR62BigqfOkZYG1Sey
3Ud0IPanDWDPvVISnQFOOnyxM6hU8JkWjAbkcfI70fK0E22tpZCFQY+ZY+e4WYaOTmh8DpLRYt2r
tnjl3ohePF5KhpOEjA/CVuAxpAzWb+L+qr4XJdoaKEmzxgcMJAzLEW/E7MWkS+fUlSjEh1BS5OkR
Mn9/BP5LEbhrdqOU+E13NApyFySq5a6aiR8UotejM4ZrnM3olh9F+YVjKNIDOv2PQUCgWlM2GW5c
yKPvbcgrFokxCtR7BFqysbJQ8BUCflmBC0dbfNkX/+YSn3Db+NkGch1pfxYrKs+lrCBdUV6GCFwQ
eyYooW9rYF2N83AKa8wWMrLTzovRIK3vswuPwpJoLsaDe0zEaN4rekfQJdjzma50GLgaS0sBkxpQ
Pf7Fh0uDc7PCIDbw0fktpOzd1daBkeBW1eq5gcU5veGgwQcRM+qf1g7crpLQ6E75Gk/pWGGZOn5v
JKY6ft32IWOcp150g2YnlLHEX30JhniVl+yF+/LKqNc2M7QM8NSuxoQ/ika3/IV7ScbJD4yPFNNp
g8cEBx/Kgwg3Kcg6UObQJ80hxKr5xoGhf/OKguVXxoMrwZBYr7kCQf7fnOw8v500bl+R5/5vxnSZ
WvGVC62kvORHraYeuK0lOXKHum4T+gY+ksO6+dauKl5YTNIO0DRwybHi0bey5Ti8KZia3uEvcuCv
JP6hRmVXbNYpkw8GNybKz398d4Llh7wb+whmWafnfN2C8uGmGQFF6HtuB97Ec4MTzHx4QslQIB6I
H6i1vybIdSHRv1U+Cmq+8J71jsisoa+1GnrT8Yb+lMpeAmv3KqZuRay5PfiSbqMRxzGp6aejjlPc
VHSLLD+VpkHZLuZozXhWFdiAeTzL+XQgjegTvspZlYvoE2kdpROwZRFr3FVms/2IlQ6zY3r6x2Xp
lCBd/e7jRCQq6sO21oGq0s+tZv/wzrFnpVMBhyvsSYZYgyUvXHoq6En7nXTbYlbHZbPZ2GoZ5KBg
13kg76ZkJQxd3qAZ288rdvufzqnvMNUAoIBhJkTT+tDC6fOnWqlV+8/cvHdkptiFYPfUWljkX1Yw
xYe7Gq7cET/eNFKC5LXOa9xQ6DML/oU//q+AYHAJ1244c6cHZ+kjQcJkfMrf8A+7KllC4tcjcMyX
5sLCQo6mDIQM4LduAoLfVt/GxHbQKqm7iHCjcd8T7bPXmDc4E3VHZKKk8DjyPKHEEuxYStY84ph2
MAx4Y6LOM6osOKnfiuvh8mI55vHVKbEFQudXSEnTGpYJULr21WbB152XyDGua8SuKFRalcPdmAfm
vCcrWUuiYjA7JbkChp97JjsVzJo1Tq1N7Rj+thiL4tZN0bnbtv5XSIAxukca4GDPYK7emYgl2KvQ
MSlBOOnzK8qtwLnQb6hKbWjYVkyXY0dlHmGcEfzLhzYWcXg5PgUqmM8EIpSf02ZusYIOe+IsOgXR
1PDrPDqFzAr65J/Mo3ISLGO73KRSG46HgAIIUNLSwqRWJVjGtZuTvZzVg/E2WTBO3tSRKHu0E6oo
NyO344V5/ejUNyl7vrSYzWUSkAybPgq2i0NC93VMuHOsxA3XyJTo/GmPD1RLp31SFIRNi3w+KQ6g
a93acJYyBJ1N95Kzvaj5iVwaqOkikvXC3uUKfE1cQjpbDnRapxwG4zGif5IRqiT1csymObzFoP14
qaEdfY3BwU8d7kHvruwYJ9xgoeFjmPLZChZX3IoInleWb8lj3O1zMNsfMOWtbwFuf+dm7lubXF1I
/POsqnPxlm5g+o3bQ51SOD8pueWg/70xlL4ZyxLUAJIBduScAPb1afDTxwKlcHLYC+49+3jb0BcX
GKgoEOLagXe6FCOqfO0qddWr7E07rReYN8+6sJOtohqZvmh9l4jSvcIghrD8yB429/jbpC68b/0W
sBYNiNhrGBF4NyBMgF3qS+gp0tmTfsqOgmxWKxgHEgGmn4IA0ybepnhvlRTPhIa1UnIzdzjoNbNU
5pl3vKc8+P/Pe9qcNzfzQ+A9/LCUV8S+u9ewSTX6HiO7mV1UpvdwIV48Hst+a3+K19yxnJN2//6j
MpZ6atbrnToS7BLsEHmq4GRFwzmCCX4jM+OcTMwyqK9onsfKSIAKqfpGz26YuUNd2ArpTkTrsleU
4Y6JbH7csJDzPvgqx5QDMkdwPoqHNOQnPshcXV6R8jxVv4nx7liDXKRXhwO2yoMhD41gY1bbIc0o
g8m3JAHjlZRGuYeWklmHAQ40Rx+RZlndUW94AhrDearvcF1VYVldQlGOeZ5LIMi0g/e8kU3rTj6d
neGMKXZztNbPvcvRNF3QdADZOcCI0PqJuGRdlJkeF4XG8ZjhoNLnAkGg2TBvvzVAFXCH0wyZOy5s
uEBNKQ4bUyQlDVae44xMas6iEVl9C8hNHg9xM+gXFXWCUI5nRVwcaXLgPoH5IkAB5u/y/Xx0c90o
tYfFiH2bnF9WgMrBnBzcTYzgT6yFSy/DlO8RHGbyFtOeD5KMhWvxqcPvWguH/BPTJcn2Aro4+p75
NFn45dD5gsCv+dkcM54G6DRQO0pkqdQwWGiW/Z6Rr20Hv7vJm/WQLBeJIkpMvVhMFk3s2Z7ItdXw
wPRe4GWYjb9T/5+NBfPAZH7PTepqTnpJUg6yNUNcIOAZ2DVPlcV+B3qUZrWHO2h8ZCgnMG/JAAJ0
EqOm5tmV0ludQzJQRPRJ6BoXTIE3PiMEmJagICyCKXrSSeAVfJDVWxq2V7eB3S1XPmn2CCWnV5tl
4Hw1sYEIduj7fsGkIabPXKunZLOsXjQvLayd2HxBu8Px9SyqTLb3HezSaaBdZei4FZISwIPoHsqz
6rpD3Dt1X4qFCIKDH9qKihsvLWmElviK5AobitJe8Zmu1yroq4WAcC9ncKBztzQAf5Nvcaqjdm7B
O8FScs9YHmB7qN+5hQCkdVzIKJ5z+GoAfEaqYZTEH9fd8DYeSBdV3wH4OfLs0LaoG8J0zRBsD+LC
Mdax+fj2KSaMIKEcPTsdqMpQ4ijZ2EUiVx+W2MLLEtiPuN3CPutYFKvSIvN5+gPgZXTVfK3PajH/
9kU7PjMDnODotj0jmKliecPRPwL7cLBBTiqK1KtnFJrl9ArXhp42+RirkyDqTpJxx2cpgCnSlRiY
iPN3Krm7LyP4zKOrhqO+oHDZ+lDlSc+qKOrYb+B76HoPF09g5vOpgMO0eGAyH+6jEBpQDw2y+0Xh
mbg5vewuqeARrSlhi4pkE6GBspomE+6mVUJl2TsE25SWQeT4w9BWB3m8thVnhPBKeyCCLs5djBpK
XqerV0EwpBcxgmSQxLNtuFYKRVvabszoXIJOWVn0YtYbsoEBZIYKbkzo4WbpOmGLxyEHmqTKt2A2
yrabyHC7J3dEzebue41WntW2B/54VFDdP531m9twllyQz52BkEVPzftq+6NpgZXAgr7tE3Iuhr+K
+F74LlVaSFZUvUdyKdzTJes5zoVcQF7Jv4/mcN7xwd7xnpgFigZq2SRBZqMIUvjgSb6mrudPMMGo
Pt8jIA+jYifF7Oreg2yeO440E50roN6w4VU6ys3amuXvqVxvu1pZc8DQKBATG2awItQO4g4znL4E
Bg3DkYY19KLbEon8GvP+vPeevf0c4CFESU8HDgNT81bv3TZbvbps6VoSm+w9bpYTsZ8N2FXszHN7
ryoYhIY9QdlPqjSK37LS/d4NBETPkmVByzBNhQGLe01x6RRhALyhi5dFD7Xn+1lLINaGxI1JDhXg
orJQy47Zm8RL3l3aVCk+696JP3y6F/WFYncmuKfQc3ptBibxjLV75tvELnEAujDv5lzRmSLiSkZA
+fjFnS0i6/J4CN496INwzIS0MSigqKf0Q1y+6N8q0b7xz8HpIRU3GqLivbzktdc6jY+6GX72HbQD
JRLM7eKA8AIoc5tI9lEIVslhjaZbQht8w0e4Fzor0bX6ZMTkUOP+KFmR/0DZYS7nvRqdnOfMkI1r
cFeDy7Kl9dcJKTh6MmpkumIebOCa6t4WTQ8RfngB6xsHKE0AxXcFQKjtUg32JnR4eIJiOeksKOwc
2Jrd1aXuEbVeSlpKGB2yAkjWJcrh46YHmbUDucz5TN6Y3r4A7cMv4xmpay7wawrC7RbxpT9VMF58
Wll1n7+U8sBNd6hUD31O8UN+Mg7pADq6lFgJ0qXeGedU/8dQ2Elxb/NkLjBMABT27LnBwyKiegrf
upmp2x5fXkOaYTiRF1/1619/xQN95aPeEGMgdRInFBEp2HoUjZ6IxnFGst7gOoNqquFV8yD4Mqr4
XeWcgcUpkTEb7DNN3XnA9I3HTs6t8SrR9TLjAHVK+ksgAyWNsmeF6urpRZEDcK82sHKrg3drm4ya
ownR5oUTGkuEDUM6UrcGcPxV7l3+bFAVMLhJaQK+yLC2OV7VANV+EhalYQW1cyBgly3GospDc0nn
IG2/nXr0rhCmd093zDZXK0I/jyoSiXeFGGDCCJU4CybHEcuHZIQEeaK0DiB97xogvTkvS7RtzHUt
fvYFGMh+LeztMXe2iUcUYgLXxRj15Kow8UQlaLNGkggwoS0JWNiDRp8TpZ7BqnWKOEGirpWXdp1n
6J5z9aawIEQYRE0OlLfapwNsnE7dP9s6O5qbHO3fvWqaoOxKeGEkFZ8+XnumhTlDzzKN3BqHZ1kH
lrI96GPZKyE7YUy2wahz+Oh/BnMpy4vQkNb0+fTo3Zni2IZgkfbGb6FgARIAhZEQ7orVhGLdqQ7j
dertFwq6UH8nNPs5jnB0Q3JXKztkqXhXQJFetHAeZHdhVdr2BEXBjH48BLhVPKcVjTzZ4dLcSlXF
Tyl/29EpZsXA7X2a77+HyMSkSdhCYZH42r72VEa6fLmEY4ifHbLjUg5750/3KANQMyXxYGwMPP5L
wfpZfYuEqhUnOOsbaqR9wDZyMmsVSWdYX0yD7SQwevFEkK23G7zn+e6MD4p49QjODnIrMvYgWwAf
a7hk3+D3qZYh/jLLrkHS2mrJGwUte2XbTroYwH7rO3vGpnkfMivr7szesbrGOEhq5sKXrORSPqfR
YLMWZhlyk7HUyF6HGCE7IKBdqmWvqQ/XdqLO3ZXqKNMp1dyAR+Wci1/P9X7PenpjdJOPQ5NYVQIE
QhC+PKjXypRFN8pD9JYaGkDyREEtaAQobqQgrci87ioC0v67ybJwjXe5gLt2pN5pUEldmKA4D5at
Elq1ILcCs3o0kApJIUU4tIeORxsvaBYmRErHpfeG4GWzzoWIurfLNB6Ssi32WRkf9ILP4QUTEeRR
6tBF9C7DkVs4RGZy5ngBaFgn5OIKxh6Bl0WVNemxnLHincvMy2ckXS095FQRwdriwo2vNWG4Jp0a
eAyz8cNR94f75qOihSl1EaFr8hIWZYTQf87B9DlPsKA7CGmNiH8mgApIKzAsVw8UwHm2I522d3Go
7jZsaGoUJneR0g1Vf87xBJ6l4svzadAWeoFM4sCZ9YQZSDX8zHGPHXnzbggQefzakfdnylkruTYQ
5ZJLfq/iRsB5gBg7CmHjya1CdNeYce1l5YFy9LolNB8LbZ91rLG649GPp9M9lHgn61IxTDq2iWFG
1oGrBu/URfAIqnvAfNDpNUWPn49sBl9OSsn+D5L9NdxDu4KIpnmwOob4t0OlKjnNuNCy1f5XklQ3
E3YY3/D1kV5y/XqTdpTmRoAuT2eSIu6KGa3+vT3ODwzQsR7YLKPJjFFeV4q+mPlsSFFgVyMDJwbF
FSIquAUECZge4nwHopb38sxawgTV5C5oa3c0+rjaYR+zwPthIvKapIot7nc1loMDcQh/E0NonoRg
bFRIH8uwB1TK39EqadsjV3RFU1Aa7U1OiRCot+EutRvZgsRT7SXFIKYNXtqjlHrvaA5NOa9LTvcs
JgUQiC8R8wtA/xXvm3jtyFuABIkUGHofHdg4qRA3JIWYXvjxEJDQvfsP8SaLg5Igof0RqJdKJBOj
VSNIT6aOubtY52vUltsIw7UYmQGzifM07XUXiEBbM8WopwCfrGfdnw8LgH5tTUBB6CBqOwh/ipT4
l7G9SFGMf5F7kehnqU6etNH1vcaQSxR1SeYCNhfNdf03dPXGGJ5GyYUYe/v3GbYWYCzFK1CvGKMG
G7nMX5GKli0RY11r0LfqQQII/YbPuCNH6Y+qRc2Q94kxz+PYMcPEq6KTABNZVu04lZUS15Ntd8UG
7bqTq76H7SRq/UlN4w4Y+XwaWoQUNKzb9mvUk7b4V3bR1VropOLxCOyELHSVLnCawSgANVNadVeZ
KKPEVC+MkKCEsA3Sk+7yypDK3/br+1Xz4xkcs+5fmFkm+8OQ78JHVOAzpgmzkNkqAqi9AAWP/96b
aP/SwJAt+hmO+y7lBaT1cXw/2bAxbHWrTVrbAVzPcvCMRPQ/KtEbIeWpMl102LDoCKcIOS3PEHBd
k5EHeqQbKHA/k0FBeiEUR/FKS181T/goJ3Wlwxqgfsink88bvwjx3zdRVhxO5KUIDiGG1JDZ6AKo
sFdEIHkeBlLKfWeiS4z1ycs2tXFx+WiDQ0w7axwHLlucFHbhQo/NUCjYRbOog0dxkwZOesqgszeD
MXOpbxYgaCGc61CFK+YlAYY87I/btkyOjtMUuAp19jBuB4nakyjyCU+LjvlbFKQD4LXU1XHKzyxv
riZWsblSnqvPw2Tb/COuUGIbhBYHXzbrCmyj58+t6AovyojTjqS0YhpT885XMJWVEV5Z1FkicoFU
I789bBSVhTNDTdTn3Asd6g5nzYGHVCz4J3L/bk6itb2Ce5vaYV7+Ni1Inr+j2Zmj5a7I2r/PXY4+
hVgDt4q91TEYQog9bIkKePf4Fu0zLuW7kt9pGN+fOY8ZSftCOH/+udV/BuzbOWCnIfHuFtOgFmgZ
iUqCm5sC0EKj+LOy9tA0kmrJRcK3boaSlSUwY/WPfPrXj0ErEI48OpVX+S7Cj+wllU3sdG5jBFJO
9G2gBJEeEo/ao2ZLjUV9KK0ymQiiG4bgIIVf+3b4jfSaCpfhWv3SddzWrFBYlyIZJ7rjQaihk+or
nQptKvKoZBfEk65ckHXx7JO6GQDy1817vcvbhvWucpcV14sNSZohFrMMCvAUfKi6n+7beqbkB1MG
unY4uT7u8AVasJzaRfEyfLc/WAHeHkh+gjIiIXua9dybRsJY7m42QFs4/gE2QeP/EnW2KLo2vQIo
O3J99nLfM3p8DxNBjul7ncWX4XuJT54WUjEySCFP3nnTf2vc5Fq41bor+8zfg9x9KaBglJLSP1iH
MIBM8LIMwf99nhFQuZdIlU6OFTYc0KRK5khYqHTr5G5sZNloqIFOxawp8cjvoy+0dYEcZr5a2QJn
05x4A5NI7jpoypIMJe2mfszfzoVjgMPyX3uuIgTsWxMLmAt9ASokqzdF1B0INHKsEzFldbxzFgms
jntihvMtL5VKUG/mUU6rE+whKwd0gs+4gsEL4fWrROwvICaN6x6xDezhX6/AANdUAa3xOyA9Izta
hYd1M0RKxV8/TngUvGEeW7jjoZ5g7ZEyySu5aCD5M/YKEk+qPR3Eb9yOthHzPXUkFW9xDncCa9q1
6h5VAOsKBCzxBsGZQSAn5VKH6MEvAE8ju3bq/2lv58QjuFqIFNW1oLrSuIX6FQ4tqaib4CCNAp+n
kcBIjzS0xdsGsitFEQqyNKYBr1iAIm1B4Rmugi2Uhn5gjhldr7yWPrauC/2lFe6JM6b8ac7/F2Md
vw9JmAj3BVFHnhBjifSWGN71HeLadKf5FZKkkh7ET0dYysdfduBL8q/Sg/uZSURb9RMyu89ftAR1
j7QxUDioaEX9yR4ubKze5C5I0kAQT0MgSsgrMjEJcLRtfJ3Hb8szEC6CrPB8B4qOAyKeM0eMwAs4
KHw3cdRCegpqeA0RJBjSUsHKn4sV1uk/7kBQ6zNcSOux/V3XZ0cy8kJ/q1pK87lmoG3P56zcIOnf
7sgb9gb/1TATBPShYxvZlIG3la9tiP6BFWcsQeHVjwDpJIQR7hEtaetTjMlODFg2HlvWJK2p32Ur
7iutF5fBQdpEhpnsHPsdt84KxeYRQoUZsBBkWjeYvZ5Ntoaqy8Wst/LnMC1duIoxScvGMEZndzaa
FS5xZ1IM6LbMEPkSeJbgzcryU1eDS9HoBGfPWjc0anQV0kKCMilIL0/G8PyP8kBdlRddILbEoTpm
dQVK9uPiNnSjeo6whW2KAAw1BivTOgX3RKjyYl0WC/h54IF2Gj9QsuocujJYZk3+pHYGpzWqtAqS
vfndfpXGWmnHM5k8jQF2/GZNUbHG74hNBqjJIhU75k0shLDDvCO/bkcNS21ij82H8MdOe+PrBy+k
fuLEQWGsktvCVowzhYVoajy9q4NmIyVIa4t9KFJrdI4VxybauiKMSN0Ct3JHqF3MMBwxJp+IQR4B
I0IO1xNrjasU2ohIK0aysomYpJ9oZmMfyPuBPvONbRhE0TloANwD/IC46oy+JLf+xaZYM3PPf/gd
uGYSJ3BPx4yo66hT5Um6yIsUcmIP1lr5ZHwaGSe6/sjg+6gwa37nIsX/HlRYDKTc36gFSsdUO0/X
WSya2j+jSGE8gdE9LqlfLJo+X12h5JMsjAXyfIrN9JUMSajp+0/DW31KNqVnDGe7D4Xv/u9JgNlR
A6cDu9I3gQQYQ3xWXEjyfHnRxRE3poxtoN7sMG9q7WyK6BddPYLqXjakbhPEuZ/1ejXrInCSCXNd
vwkEv1L+jSjVNwP+0wpicQOg+FVO7XBnXOipPt6O9IrcOzTM9Crav3CKjOrIx2o28W9L/trc1PKz
izKD9Hha1MHSOUyPl+4sh+AepL4ki750yMMIMh2ciERKetouc6cfDDoQl9hPSJlgxYCbPULDAy/W
7dlCPOzr0um66myTOmRHuP6R6d6mCC1Kii6GLgAtzoG+VSPw5J2bNLZV7F0sb9qDCGWtQbHdMfeq
Kjw1DJ8heO4Suhfwb1A0jn2C2qQzpa6auIl1rBWF5I/xofqlqnkYgZGOWQne/E1qrUjai4+axhmQ
L/szcP3kbf9KMZXaPeNjvqZa4LSP0KK7mcz2Qg/FVUsgXayvEjLle/qHoNq4JlYn3a5trQKSRYgj
pQmmWpsUE+RA5jT32nFzwlITm3sgbodGL2VR0+n21VE6YQv6BXyUh9pZZA4mrULwNaTHyvOobzzI
c9IAM3tmTaZsqWSnOxzvGZmR1/nNN+Hht7jHAFqZqLdatYbu0AtARjQ+zit5ZEzUraZBiVhyl2Ol
v1lAWFcLU8rmJ5/yDAgjGx2p93IQSG5p1+n3xNsE2ZpZKFioCltnD8uCmKnFnv/tz4nfADwILSgd
NvUXmDDnt36Kkds7VQpER/qXHlqrKTRspZJNhMsA5DUJwxEjgGydYRmtSTPPSKdFMCGfLCq+p/yG
MVJyTFlDcoPtE2AjY7B8mL6uO26hhLn3avifpKp8nwGuWn7Eqh3uCASDXTPKOtv/xY1ip0yyp49i
b87A5p76+AnqJTXFNFPxkulbr8gnkVt4SvaxaQZBfdhnN0hUrmCkJchL2P/939h4kGj6pgo1wfuC
ZWICTpnWeSh0fAUt65cx9OE08Vf6O5uryplYsq9X91NF93THaxqhuL64zKXnfAK53IQ8D3ONINor
Y71WSGBF3gipsSsrt9vdUEDJpeDTKcuJz4TE+KH2DVDpRS6cbQ1/u0nqd0Cv7mrUqFvS4p9F7400
izIr5Bllv1fSTpi+ObPTfzWZcx0FHirN5uBMqoRSc0JpUolCQHAEXyxAbwwGqwjct9kRwpt5ogrG
WZG/VrX/S03Een9TuW0lMKnfthMFZrZOA5YTEzJhYBwTirDlFCsDGdEBKa6xWwMpX34X68CWxC2E
fJEJ7icG7h22Xz6tCBJaPp7E+CQqaC5lvmUwuEk9XtJ2MzcBCbS9AIfw/MxRLtZWy0zpzGaRciV0
Vd1lMILV7ZF17r1NIL7fmTnepuTfUJAf/nOLdFeoe4BA4LcjSC/ec/u2IEzmEXIZTnRR/d4iB9Io
oh+r50O9Zy3qnuQGQeCMDdQTd8gf7wDhJ+rbon///DhBNHHD/fdGvDE0GxZzPBhZbCv8bNPULoG1
+cBDQfd1KdNbmBH3+X7vESzdC4Ype8eBUsAZ+mzyQ4dvj0uGt45OjLVAhQuEtDa0oM7x1XHWaSkj
4G+B27vHvOPRFg5WORbvDKiRahnyywAFtW1UzZ7c4fuv12yRQsc/eSkDorinZ2MIqksCZh8aNjx5
5/xygRgV0liaB31Y8+75tMy2frcwfasstYnvdaJn3Rz1DTiD9Xj+S0bwQraDginay+Ct1n189zC1
pDs2WIaJZgVR/+z2upxcALwT87Ck1Pj3Jc7N0HdxKBd941m59+QCKjpbBoe2N5cEDSnBrW8LE8sd
c3V7DTCDIdanKDjfV7PPYHHu5qbOwkua8udYjqupyx433coOZD1xfPaL+biG9UgjW4Fhblb1/mUk
lNERwPnWKL+1+s8DbVc6puWISYzANnPRwscrhxSzw9E5cb8ZjpqcW8SzP3FDkewGn8yxUrMSrC3p
m9b9KzYa7x+StIEqn/jCWQmqLClDo6sqAHfk7iRiNo9GDvFDr+z5kMQ2a16+V+sMMXhKNsy/JUpe
UkuFi7KXKYifTOf0jGdyyn/Kv3UbBLImqziv3drDXSe2Feh+uMpt/9XZ5VJOgn1/RrHb+mg8WUS1
XO0atp8ze/BF70CAwTyGcN/Pto8xsJFTHy2ZKmmz2hzPd24KT+Ok/yX2Y04vJSL6BMmTwrRkefr/
RkEqirtlz5A5Fmmvcn6T9JvDA+H44VdARyDeGADtK5aMWUb245fCCgK2GePb9L6zzsdgQKiYTr15
SzR/cbW6Iaj3AXPks5iKhRQdbTv40zYksQNdbTJwv7JOt0+e8yytFuCeH0zeQgGIhcf0Nyr8EO5S
3iR32LCqv6lW3BWfuzMQsVN7Sphc7q4EslLS08qkpQGolrVRRtqqZKyfYoH1zMv83zWRmok2urIY
LhiSzfgMm5xtzMLL95N4uCJFdYKoeykEHXWeZgkUKD959KnewdR0FLoOwSCSMO8fnZp57GbxUvdd
jRPbK4fdPTj1ozgztIva5sQdO2arWAb/cwsQrI0TlZUMp8xG6A81X+8nSlmUWxJLjaQa0+WP73si
wqvNYINzMxclFVPTKA2MWQySwxn/CKNSZ16kI2PlWP6keuol42U9uA/1eFvnfFFGdlUi7z1NwF3l
ZbJbLrU5SA7G25WyyD407gvRXRo9A/g39A3XzPMTk067tCczTpA/rBQsU+S3SJIHx+wQGd/2xGEk
+H2Rr1KIxeJZqQWllT1elJsRgIs3DH8RyqcEuHvvYgOAwtVyHiZ9yOTOHyNN8P2Tx0+HxZVq5Oix
PYH6WvhAUyvxbJZ4jI6nhjuHhLUR8+E5zh//WmS07zPYzZYFAmHAGiv7a93Kxp2ffNNgnOodSdMF
1HWaASSqvHd1E9S/ljVwdL8q82FdXLVbQRVd0ZiTJPoXi+TXoSeFn1dDkRKQz0JDDsjFoBKbyeFm
kNeNN4gdxep/XkPmFR54JZYLUNLv4eqso35ernhnvlhBJm4F2aRuTbtRyqCHCDjiVfkODYIYoXbG
+eHbr4wFnxgjTpY64qNOj+0zk54QNrcnzQ4b8sW3UUY6RIEGqU7EnX+e6ovbWqQSicEItELN8L6V
mfyepdmTcBHao04GXQSrW0LldttNHJ811ExvdU/oOeq26RY7+YzcwzMSLergr3/zjg8OWeAW3szm
f6aYoYPMkj8JBQzrQ2Lp2Sw/ADcOvJ655OsNBgaf35AB5cyHr7+5OerpYxP2MiJP+2jFJ7EyT7F6
xdhIqv4sr/3heKxTcZMDNUI+uj6Z/VhcABOsXAwwtEBKHmqcqRnhA7DmDM7m4Vrm8kAvm1w0XWfw
IPMlisi8fp15h0PlkQCBLWTOPIg/QEHf2NqYdVNWwMuWiw07K75nzjDSWUWxnQ84KMLbE/pn6HqG
h5PgzEHdWu1OF8wC1g1r6wsVThtNExUnANqBcRQLNscxVzgFG7Y6OuZ1kgmz8hCn2+IALaY/3e+Y
HhCncvnjbC5RJekdjkesbaGSzXEhILIcK6cuX27WMkTkJ7RGgpHCfxFMi10XrnHA3L5rbZtcV0qV
WmL8yCqSLW6iABAhD0eLF22fHYCJdzWdR31XJ7UOH3OodhvPK57cZtudhCkkF3XdGFvpK1DaYqF7
rLJNB80TOo4Pn5e4w/d9kmlpnZ9WwdYlD4+GuR/JJQvXAxkuWqR6CTz4wHaFdpL7HS1OVXWaua5c
HOF/cq6QElyhs9Xktj9MvED0hq54W4GwzdtXM+PTJKZFrNMDHAuUbbtuXYNzaDxvcNwNSMGIMZUP
fIaNXM+nt6Ib5AUZH5tnZISnKnwtj5JZHCSzE9W9diC+iu3lpWYGLJwcKCtGPmitm6S1Q/jquOC8
4uDvFn1+btsiVgdQWFcF4bPDyWUmvsB3F0QoPyPxuG0ow3IBrVZdN3DYYUw3fcTxvtRSTR/Df4+B
CtAr/5+o5CCO1kR9/pyPQJQyQl6/M/k+fnb8WZPkyEpORLeT0nkG10omQNHGzFMy5n+OqbCtVEWo
145LoE+kypxQf6BF51GaXdoqBF2FUdNVJ0KjXscOj6KQz7WZFv5PCzL4DXt7/lgQaNosEUX7gTuu
JLPR5YS53Nql9CUulmrjjR9tS7XQyta71Vy0Nohzl7HrPKD0G7IcVdgTLL+DR5lfwPj7KzmO4Tx+
YSGTXtYUyYLyVW/ymDwcgzzmYWI/iYEVqzpl5L+C9PTj6lhirSBqDa5vJey718JgF6XPX39M1tsj
5B2XrvOXf8IGcwbn8kPg2UxeQsuWYV9MOIMuW4+/91q2V4/Riggh0sHVyD1xFLnAHQ11euBmfBBC
HTDXnBo9oMqsQL2Z8twvjgRd0zbnGnS0G19Wy/sXTAxFhBZk9gQa0TIqb9Xvj/LBeKTDOsSo2Ris
Pb4AeZ3Yr8eTiiUgJaMdI17PA2AMvUelOdJ1ynzwcHriVcBIQR7699mF0qOSpdT6m7/S+aooAB1m
oI5dWtDZqGTlGQSjUOy28XOGulEOEf7G+Tg1/eGs12+rjtrU0aEU16BSFCyQSI4JUzDv3RInj7BK
FAkQyv0TCPkxZjJtyI3gZ552OSWZQpO1oBhQ8WTboJrTrCgLjbOZZHfI99Tt6u1+nVwz5RLXOFrk
SLVrsAAJTBITQRCqVqD0C+dCu6OruTzDKAPv+Ga5vGLv+snffZFN4vRbFC0fzwxNE5yGdHLYfbqt
GGEUh9NT8J1pn+uZNy8YEl2ZHOseTDhrLVdECsy1hOJPzQusW7Om4W2ZcmYNT7LcABVMfQKHH0Q0
too7xAhcVpQKtVhRWcXcNg+vB29XWtT4oe14UvWOjC0WO/3x8csRDHejDml7+fKgKtzjeEGcgTLP
zOlyEjscJjNzgYwvrW3ftBSth/Pr0mSSLwyDjIxGM5ANnDkbA7fS+qSmjl3Ab55jntpNPEDh1l4R
OLaWDNw17np1aMMZCNINBeGfs8VNbbz6GiGd/HW+TrXA+vSDxs1PQPmYWJjogpCK5J2PzbPWdlhF
WkpoES0n8A0HA+7AvAQ1EK0ipHldPkwRXEcErnPqYMkXEYJyCX6HHuBy04aEeswRh19c217fDEYb
ZmU5H/2tUdT5GuB4NAgwAj9PxwJe2Z0/7EQd5yaYd/t5rMR8WsKuANYHSmm2NAHtDSt1eEe+iLhV
JhR1n63T9kkHE5t1lsRwxT7KqCnQu8jGjozkKTW1LdyB2Rqh7CI2rj/6HM5t9jHDylVF/QTItW0X
OTwDzPYcdDsl8Y4MqufpP24q0qDL+g+F2WRahvF8yY+D8XNE+9POWlRGe3dMnCrBGg+hoQa9t6Hu
Lob68cyx97uund3uekYkDVrEpGue8Nu0aEGoRzk4q6zwRLxTCNCM9ih3VZn2ANspXGOEC81BWrql
B0aAzourpZiNgj6dLeqQ5q9+Njq8/Oyhbu9IgfraknwUnsWAuW4hRKKQf+N0jTKN/nlTw5vNCXMD
ba/dowkPHpi58ZZ+5DLAla3j2sPmg2cRH89esy5Y9o3EwJNm6MjeUiDln5Gmn5eFDguVwr97UYO3
RBYvltMTwvowMsd8+DiE41qPiqiXYiK1eZEHD9kpIyOl98yRu+34CvOgmz8TRZdBsuKmDnSvNo2r
VKscKnDRBuZ4ep04oyySVXoMl0nXvcEqXNRrRBhV4G2uSQ9o5fiaBthDXfPnUNW25sjQkmJa5mzK
oV+XrzO4aMIevx5i9HsPxOS2Zab85DxdAQBo1uE9ZG7P9O1JImCQYAtkWznqcGtAPQEbS3cfraAb
vGH30oSei7s35mvXZDtm23HJUMOGKgwCWu9Dcw5M8u5rzvCNM/iPXReDXUWIZIo0jc1+bFFMfhgR
W5rNSmsc1UUBnMATI1+qY5QBAArmR0QMF6zcgCul1UHZiGHBU4uZCFpkPFVkU7zwqBx63D0QaPBv
XWuvTZye27F/z+VikxuSAbk6Cveisxo9K1odfyH8NhYY0kQtzo2lGJyDNcQD7gvXfTAqyKudgoAY
94cwpZW0a87MubPpyLoYIRe7MhOvP8dBe9pqgBRTIrU2ryNP5PuHtKBJ7zTdFEYG4PPdsTHmC9ol
mwN6PJqDqWvr4zHJ7PuAM6YxacDp1Lkm+wXY3XKKR70AADhlIpMj2W4tivlxUUXR6YidBtU4O6tf
29mlb70Uro0aybxbR/088pxf43oI8vEnUQfT7LlgIEOPbbkIeNO2PdkIaUAqbS4Mjvd7+Zvd2l26
PJMhETATKZZH6k9+e+ZUlekpCqnm7HY0h6q5BY0umKdt/5aZjsKb+iisBZJZgJ7/8OKJQ88GOAMc
uQvom5OKZbnVXNPpG5HkyQ2KfGt6iTi2SMNAxv4aefkcSj3Nd8cWLDzUz27caEyCktzbCxW+sjNN
EJRvS2YlY0ec5uWZhkkx7JgUmmol9yDjwL8766l+OY4/s9xxIoQZYGMm6PI255W7Wk2XOpitMceM
A48VwPoYh5fyuj7GzFPF4X2aEgvzfkMGNltuilsAza8Hk4Z6FESLtSItnwSxPVxYzlzSwL0R2LPy
8zQYcHXkuTpzPMyNg0lNZbcHledqPhfMqVWfY3poC15dYWWbGC7bIkYkf5oxBaHC20lTWtsLTZgB
pJdGtBKPLAfZhLBWFSstqp7zhp+NmyXTtxOnrLqvOqAlWCYi4dcRvjkEkzt0/TSwcjCflxSA3IWL
lpf+enKMfrY4aKPSz1O07+Ey/qr7k9d0UNrqbWVb+BV3iiU+XO+3fkeF7Yfn+6wsdlAQx8pnk9U1
e4EJu9DndKl1157PCVB+FT1UuxhSu0fCZKC48bmjVLSBihf0joDpFVg+Gg64Exn9OW0t50OaXAyr
p8ym7kD3/n5Uupt6WxwmkeTuwFnWQCgYthchEgXxZPdSXOvm5TFUnYjf13SeRUjTvhKErY8/a2VR
YEQxHOEDElu4r8vGkZEt2KPU+wpS1dcKaCFWitHEnLNALbndyNS51IeYsad2cp6bVM6P4oPPS2Ix
ulAG64TtQdmyBogMnl6qXErGyM78EPv0oF7OyaL47Z8pMpdaglNWde0jKH2TozOtCAfSRT2dSs7x
vbRpzhFbvJESNm2kokmd85c2ONCe9zYKh327RNg99/e2YUHyQecaAsWvGCJm0rwpO8bXq8xq5rsU
vEH009N6d4gLA3ZXXxepBINOkwKpQKf3zKia7w/88QAlwP5dHtYmW4YuScmSjYjr8NNwM1vNgWeY
GXvXH32pleM3zDcYw2nRqb2TfUJ6mV0Fv9G1UZ32EMMEzpahL7cfIICgY5SebnCmOk/WTzU1l/cg
FngdXa1M1QgQS3S4aLwwYMi57LoiWdMxIT1gijhV0vDMuQNu/ZamqJTgDEUy7CTGDV2R5fWDLzd3
sqYjCsvV3MN4NVlnJVvUJE3CBLfRonUtqTN0xna+JR+5a3UMMeUyBeuRkZcziKmFB7dZDdBVP66L
+WtjsfJTatUd0HmVOLR7d998dhXrPWVsjtunKEha+kta59x0gEI6fGUZQ6rQ4VzW+S7ne8DkpVeH
X56/ryR71TGDD5Lzour/9g4NTwMO6SzO0IUJNjd7GNF3NfMYbMwbHnF16iCY0JA+G8AKMbBYincT
sYyMNIWhw2lZA4dFFMCFjcLKTpKTvz8PX8WzHgl+2xUGPvX/MTGnX0WX/z3AYH8JDSASTu84kZXy
PE75FvftklbFK4kQBfYIPm3wRbz+ofaGA+Aebvah0FfhPj8XV0UlggO9qkBYlFthmDCPC/FDVHr4
Vkdya0uy4i1BxOerRHIlSh5rq6w5ML973JVMQ1Tk2W/7O+4opiu7QYS00pb+3ivl1ugnvCFn5IFy
Ge5McqmgtMybMlV0xw0wOnN/cPRXpwHEpFNT08wGl8JJYmBL4gjAq8JWCqnNOmnvBLBOl0t9YLCc
06QkXSdoG8M/9CsOchOr7nSI8E/Y3pDUabm6rg88edLID3dYcwDxoLoCYMBhaFmLCzbvwVctmE2z
Ysv2PaSYNLhxeOJvxlQDXOVV6jB/plXjcrwSuXv0KdcRJ33G83pPCTeCyBRje/wgjHDtdygIWwpf
pIjN4m6po8tzvtZQgJ2mvT8+A03RzT5Tq2IFtOApgS0lpP6OuIv0rNIjvk0zC/tk8hd/O6hf4qFR
lbzBaPKRcP+3ZuAegUkk0yGgKfpG5u73TR+1Lv7f1MZh4REWbYDzrzvzWg79NG8FI7UDP+w0jxpT
VqNslMaCyh1otXqlqfzK3nLdmKqgJYRWydayRGg9cG58+mpUS654YyFpzSq7k+IrtEn9uEcmOzl4
/4sgy0Rhe+4053svrdQ4FPksqW5dGeA9CgsZSD5Z/PdZnO9bABTxxTsfCWK1nqfnHwJz+v3djJEI
Ums9sBYPkCha4L2E/T+6p41mZMKFZ+CxyIeULsv5NNX522+UHjRUmLS5lhHMjFAs0U0N4mu6Fmh1
epQE/ePTj8FQ/8l2u4zs8KUcUZDkvxRjCZurS1nJc0mgg//bWPk6wyRGD5jpFzrG9cGHzcQmXP+k
CsYQpyhei1tu+6IeRHuR+P9H8aqZKmn+MvFN9Nmd7Y3lnGdMDbo8tw7koe3/tjnOo0DBrIY1LY8i
2RcQbifb5/BrNBZ2QV05UMNLV7ZpFoTEcNYhRtZbX3U1A5iFmSTTBqxFgI5zyO5cCvUeIQoGOPMr
3eYQIFRCAQhHWVIU8YD5k/8m5XNNkQvorHAcuTCQMBKEYNQagtjvMP3mpp3a3RyDh05lws2XycAj
6nKMuVeWEWAEJTXB1oAo9AgdbseoTjevLceRLgQ30BfrwT+BpfymA7FGJAI5KGV+FRz7/v1UdeLB
BM0GQV+NTgZ4bBJHnRSGCrfKdkt6Ht3fL9KY9+/bxiXOW6NT/+wXj8scmuCZjMeQqATDOulVkdBB
13CoAYfSFHGU9F7xbM9o3vQKVDRb9/2zYxAhjQlc8NRy/+ceJb8JKv+sAQPMeD8m2SXKzTBRuAzK
WbNZjt3XyWFYjeldEiyda5g459jeZWImooz1oBWUN+GL88cIXX2f1hOH43uNFyXdDs7l+SYw1BgR
zoeLvvJJMeial6TKSlmBThlClbEgXeJeavkpVqlnx7rPDYpIxEDhLbr0kB9gAF/nycZjgs/z7zOr
ia0VTLiuMsaYNONSKHl7fGCRl24dSRfSeFjF1dJBXdC8N+Uusy7Oiai8wb2vP9F1HeIwAm0zYArO
jupbeOirac0xWvn0AP1I/K1dWKaKNX8u5YeqftKw+reOUfKGf0mKRhkaZktdHtlJQMjg9vCxwdl2
zJNfDVFujPaxqO3fw59op23S9KxEu8iJQHH1rFpocTYqUdVhT4KLaBsPCfGs2rEt01MWfFlZyPVN
Jwx24zuKHt2KHRX6vIUxUdzEumUuThkxUBv6CxD67X2pDy6S6yUs2+JpTQbDDMWdpzjwminDnLpz
0a6IUh5ose8kAdGh9+KmwpQWSZ1l31FtY9ipPsbPCsGY0/r0T8IjryRA9Mrnu2reeWlUN9BcX6Sn
00n/hanpTkQ+FOT/NCVrFZOMKqKbZ9do66lLPqrqY2XNJNseyC9nJostH0mS5vUozZXNpNSTV3KN
noYWx2VWew0X6DnMY8W0NG+38IRV6PYtFcJGvbdTLGv4inQJsDdLglh/yGgXtQdWzdDzC/5SZMwP
r1nqAkS/Pu6ZrX6dq1amdgBDl9G59xHc+OKWLzHDCF6yNKSxTc0ScU9tL0hH081hftyXznj86XSf
IhQ8wEl2n3Mg+zlneERtGJ7jGYWp+TeITmSdccjKbiS0fMKTEco8BJvd+TP0xhseG1giBsqpTyjx
g4u9k3cZPrKEUr4gCfa9cleQByJ1no5jwwHiaYG8OL7/pAiX39IVt47JvgZx6iZJxbfZpxQ+sZuW
WW9gatN9i46djhlRutej2Tkus685Ozht3mFlCLP/gajlaParrN6RRlADPoOzwChtptFm1gou9vX1
WDPXJWX5SfqlScpIm5VlPbdFcZupmNAB/mofHlD5lu7C5iJb3drHB1+gKO0kuuYmSQtEVvc5SVBj
FeqoxY8PceCd0vqswSrEQAAQr7QAMGM/j5CGNnPsZMkOGoYI4MooKj83Gel/FdFo3+Uxr+m8htGf
2YFrkEjmySusJN2sUFwoOwN4q1kP7bX+4idzng5DA2ujMJ6lE9pqIa8PuEsVv/N8HqjyJQN0GzIc
GOmBO6gfgudsqqkIifvw3HD2LIGRfZTOSl3MBxIxkrUzZCKwcYvkO8dBvmByHPGcawN3U5qQBQLi
1E3zbrEaAatA1mnhXmkKtSnj/HddrcWiBlR6Od63S0ZF+NdQIjcVVKd4l8+I9yJl27ro7mRARvtB
+XtMru+yfg6eX6hlO+Dn/WzwmO4z8IO2+c+jZqzfn1yFj5r2++X4rya5tAznkVR5ulUHPOeb1/d+
bcqKeCaolCmR6RsbOKJhTx/qI7VztW3iZEUV2+8mT8BhrZaRWS2y5mNINGB+y7pAOxKhdNacW3ef
pH3wWXZ0oXDR5GDU6eZe/MEUz5FE8AMbGvocrX4n3LJ9TJLzYmhhGIgN8A3teD7K7Npc2F5lhs2n
n2xq96k3Gd1JhF/Y4xlfgsQGMDe/FrZhgsVsFt+Axwq6BVOW47uwShfUQNmIGVTEyrfTCtDqgiv9
jV5skvxKchePOUMkr4VNAwVDaoiZtn6Eim2XdtzU/oR3pqTicBm0wCYZ+rCPGvzpPSWLr+kwJwdO
UM6WCZSioGSUEW27IIo6tKq+GpJCxxUFNYxwaAuupcWbK/4PsymUV0Q9jT0okittrbbTy16tPaSN
1s055WX4BEE0Hh4OcKYmmxQCouF3UbljPynvult+UQF7EkKiGQqM7qD19wkeu1m1WC/P66NP1Q1C
n9nA2NpCAi9cTzVVQtKEPPOfj+XqnjWa8Cg3ZLecLJe4piy/Z0OPzUieuKGwKKBDBW8L0YQXBXEk
b9xUxNCK6QX3xab+IzYXFEfhW1JpP2I0A4gcBJDBKeXli8/IHQ7s/9C5NilBT+2K4cOF+7S6anPX
viyrnBaCEXwrmwvcFfh+oiKN2GwpCi2vBCXNPZGLKm1DBOo6YM4DBJtUdMdNiwn4hdLz4UT0FzFz
4CcRE5ux2QPZfsXFF7TTng/+J0dehG0CdcqkWbSCEdeRnf1xGtwOJ46a0Sriw5Rm+8b3FQX9YoTd
+dkqHbIEGxhFN2LzsRzuJ9Hf4Xk/TniBDK6xdthY7wIOkHxR/v4Wi4Dcekon86Mxox4nRsjEx3mn
4EOilAMS8nKkA8pdK+j5gWdQnHhKZ8hRn3mN/YDrlgzUe849vcz5jcW8mHWoBQJ6nZUFdI87aG4U
kfsmHzm7Sz+1oV8yUhRqtM1Jq1MM7iyyixWNNpcoyvpsJCzwUlmS5Ht2kAbyZHmhq1r2BaQ2J0Oh
X6lu7R7j0y1U9QSOMuMRczf5XQQGAU8v+5dufyaa3ACnAHh2JBxaq1c6nRNI56hxP3AeZFCZEIME
o1JFwS11F9y2srpY/UDDyHFIw7dCXYO78uq5QJX9rR0LuZ2PR3U9+9z5uz6noMxpoQWHBP0MZFvC
jldqnRUgu0aNk/VzepnMtQxFL3+sq4gbBnSX3/AF9pNLKD+beBg6pmYPbPzaaySQ3BBndvYnSDiC
kz7/WZWYL6KMfHnneJaxG6uyQyS84l8eDmFdJAf0YC9CETm8iLHzVqmHgFx1dNWcFd8viwz8iTwW
zwWhlg5FAXGTbJ9MSytQzWlN9SNLDtWEQHK6YXv1kF/x6BVdR1nFoHOm+wcrM1uufZAFT9lZSNFs
NSSe9JfTm8RnM9M4UAkp0kbD88sfcJDVIA5EkcSDsECWMMjkKiX/u6SXCSzmB9m/vr1DjepBM5AG
a1pfV11aSTTSQ/g1WjfzYTgdscj/1DvQZaCZYoirrAbLRAZW3jtsdsJhlDoCoq3VknFjC71JAkoW
ipjUvZJ+VhaaDq79Uyu1nVqImbQl/EoIL92zBSEO8Yn3x33ejYksOz9KskUDON5of8SKECKK4eR1
jK7Ea+6WqwWfZ1m7HJCeJ/tfs/rnRZuG01MLOOznJH7BbdgP9DG5q1u8c4+AItrLkvgMIAdmD+6h
VCUDxM24njYv2TZkb1RYpApu+x+YRZPmk7e/iYXbTlR5+IS8+Oan3Ehlk21R9/c2UN3bLqegsfDV
p/1ySsSDAqKf1V+BasEnfb6j7o7E06FZKASOAczq14Zlh+ibA0h5rHFZyeJhOIPc11t3RiYJDUXs
cgOTjUJ61+yBAgATzungHdgZgqLHHocbE8dJN3lGx4GYOGcjf7d6Vri7dnSv6sXZAVpO0xelOYOu
rJ2xjJqCGOANvTGWen46K5D8MYnxxIADWJS2i+6giOf+DBZwmZbhZ3k9alCOo4LIHybwnGMQiaPf
u1yautR/OnEVHgI95ySEH7SvLJuENQbhgAQ61ZFPAz1d2nzKmnxEexK+5Jj/Tq0OPD8dIjzXSgrt
JxocNuOpVjK6KPwfF8FC8cPbjkgfSq9fQpdUkzeVLPWY4wW2AngJAQxMswDqgAo7lIDVnwco6vUU
PwrtFR6d+vzKERbmde0vQU8DqGPAf2h/hdqmmD9OGvxaHJ8b7k4AiaOONI5bIMZW3uX87EokpbGE
O1SonR5JjweeXKRWlV2i3NhvtmQToVEexR1XBI4zmVCWhb6JkusKch4gmQ/5Qa6rosef9UoIO3o/
pjUNbidB9zDUJ73jfYDUWATj4ULLGDKG4ViG16OegHFMrZCtsc4yE3pDBiI7w0XyXfH1tyPK8/GC
OKa80Hj5qaTSHB1m1nbPkjf9EZrHXTXRFPciamkZxRsrFyERUjPoFgDa1UKuvP8RQaS5gzGWemHq
aktJaWeXo1NAK+ujiOCpqp6rJP9HSrQltxeSRH9tHPMmV5JZhydTuTiUBykCPnv4vsdZPg1SD40O
eyU+S5zEUmD4bHm95WKK9Xcst+i1fZM/SSHrxXIqUKxyq5hqrd4Axk+SV1DBfcRFimdQgX8VTITY
1kYqhzr1pAnNbZvz/MXi7cCPPZCCaKiFDN5FTFBqk7hY5jtz6CRut63dIOKs6Y88hASd+6/yrZni
q8hfNAO+dOvbgobw0t7s3DiTY7qZVZPG6TNww8Kdn1p/mPTF5OmSiGv3ao6SI5AXB8UvhaTmFVtO
GupobYs0gtbkOPVZs+6a5+UdcRbG7r9JHaXjdpE1M91TpNqO7IqZuiNEaUikOMx2Gs0j4WJEmFw3
mlSeGChJlMDhNR5avP5/hOa/ytUx39oNW8C61vbvrZ1MXkVB5HE42y/1+zjHOduGm2RsyDI/p/EU
8Zqr4F7WD3284d8NnAhMDT9yL7NGLc5DwOAcLp5KdzZW9JSjekCzEwXdqqHG6V1EU05Cq/I0JjBe
/APC6bX8Y5CLjpHk5x+i5ihFhVKQ0u8RWhUWdWtjPYX5wTa8ekqdrE8x/SOfgvrXYPbdhIvJmL7b
6QP41Wva7pYSgBxTt3VTE4fzfzPae1qxcGmEGE5qdM5qoaf+Dq9v7UO7pVUYBvm9MLV2ZRaPQ03d
Zs+L4yXwMSLPki8ie3pkCWLYvRVbnPSfMyuBvGpUf1AympDy1F11+XlupMxjgNx9xWL1xZRi3Mm4
1KfSL/opNw6DhDq/5ZknjrlsY3k+D8MzYnVQSt9gnFGhnkLnrecfqL91li/p0P0Q9AS1pGS8CLXy
uOo7wbAndhVtJ1BbfsTnsSoLGKxvAjvaydn7HS9Fg9LYduF7EUNkLUSNxbhuPr5Ex2Ni5y3HwVX6
Sr1hGV3JM9+SqlyqRNKXQaqVGezivfqmhjOcJ0j1qcTWe5rO9flefnmlZFnuPIWxEzpnvoYmxm4e
TQSCGsVjrMC16frfNUKB+m9Nn5BVPhLPVJAwU7nC1mHS+MB7vzuIxUZQNy/0+83DL0ryjtGMNC9j
Q3j+qfxJNTxLmNPFGHRZ4s47bZ08WwFXPMca+ON5BQ33ZqPG0hsKYQ0RSVlqeTyDQG1EgHmhoM1V
pKsgUw6BSV76JpWnGu4EHyofnHpYa1/JzVdBQXhy+yrnUAcj3+UxWQLuu0+1UD0gpF1shya0VJ3H
zQv3UFzekGyK1XHGjTthS1HB7oPTzKAz6L7bWtOBHEn2JTX2eVkXYCwn7/bsH6xMjO7fFP/kQ83s
8dNL1Y6fGshtdvSyDsXg2xJyvHbnuN++Jqapeoni/qAIB8hLtx5j1B/aiHBrISjW0FnRTTgYGDnu
OI1qsuQY0TEv65v9czPh4jQIhSaYP9XyFF+BZ5OTzLCeu12OgodLpQZBW3aeNRvFmZcya4CGtARV
Tl4oMwhm4P/Zgot/mBy5yoEwIsaJny/uI9aSUg3cOMs4mXBtmE7MmkOCJ08479Yr+BsFUaWEq0j+
9kN8bBGvAZnM32WYaSkc7LijZiTX4hLy2G4If3y+UdpbkSty7I0gdTzIAtOYfxPH4a1TnsDcwx9U
QKei85QGKSDiDNgO471Sistp35CVi+zeDgQyiDq+7vssB1a7TMKKV+XvuPJgTg2jB92HaVdv4DtH
i6yiMDsRi9SytO/kvQIISZ862mPEa1FSxCMcGnCooV7EWEqCYDlFFo0WwWEgkoaJ4NqPV8VBRE7S
qG9eAKHYqCJufSlrst7d1e3MSl6ZDInmDwZvOQWpaMCxDO5ZVcRu49E/b3xUvOaMHjONOMC5TVyl
Se/4COJ04akKJ92J9zss49Ib/6R57iTiy7d1mXsu6+z3F0tAys6tOKrBvkVPIaJtFvL9sojXTKBK
15lnwaYe4nhunHZ13k5blfAYLqhT8UdOEZMQ7yBII8mH6Hcw+aXtuXnqC5CftXDevlS6V6qTolZc
9k8JnU1S4n00XZkwCKnDT/JC/2PWMnA8v15botMohluW9rcY33elKhuoNJ/BWpb89tusIMNSPMRY
iTXKXD+PQ6FIYQYEacoPtxSaumZTUzozjOiFcnpFro67U7LLNGjtgHZbAlf2P7oimC2QvhVxMQnX
c6/SvlBmjx/Bd6hLHE0oP5h3anHP99NRR76WnAc6LwGRZ7Zeq1liLbpl8yQ0sE8NX5NZQiHhpHj3
8v2RB6dqoONgbRxu0EoUQjmeVMq8upe6fwbl62ZwdpZVywshl9jw4T3RZwN1gjZS5aupiSK4KUrN
9ok6gp9l3N31DjUSk2LPGNL6KxojASCPm+zBndCvJobyzVjctQykFr00tBh/f4LaSGQvt5KKmRQv
8+hSFlJtgRNCU69fxcau4Pf083jI8Mfs+fZLJxoiUm2/EDy+1XAJT+lg4fopLQyzE5WHt5zPTxhN
mZK3CPnVmflekOgZpsdjhsqwmmtKettjdcTmDc8t1cgnZzq6K02kJ1XbQfM0lvUWH8GCaxUZebCD
NDNUOUp3nLf9DjXj1vjCq8sgtzXAR2kRnHbIrthj7rF4AkCYAgiiHhiUSwItYOoN8Yb3zdn818ER
ozqTa0VHzxe8YGQbjCl7lL3RXw8G4xNau2h7+lUEfpOGvSWx09x7/cjHOnJxdFMlowS9IOV6WksS
29OxkG8zLqP5HH3xGzoh6PGHd0CmuLkOmGcdvndoOBfG68RuMMQ1NNroxT4hT3GmywhlFfKqnA/1
4GDXa2cLIx8ZY0rpj5Gbo3IyIv4K4zvD7vBPB/u+kmn7NEYuXyOE4pL3CeDbriA/P5boHIyLkxvt
9fO01XKxcq9CSfLivc9il0gp8dn9HIrnHh3OaXViQgx403qr/+Kcfkd/BeqQUCvF9GzSyucYCGG3
wo1z5deFrSsoxM5YARts90LV2DjuSb6YDOo8Cjx0jsjIuQKTx9SykfTy1fnqXmp49a8IwYZwhC5N
aMUXl8SqVIQSXh4IihRSSgqb4aQSjT4Rq57EWTacdVp2LAN3AjWErbnbuOOWkcC7XoeWrd4EmDdP
RkbMGctOZIXJ6o9Tp/qJt7VTvfz90sM+0k6aOwJ0GoQq6HmVWVKO5vHJoYnlsw26Wh35BQxvxGFL
T+AP2nUjfiBqLSnxXeOM+Nu1OnlEF8BuAXB8l7E8j3Rbrhn+2fcXqBrRos9lPNGFtYd1Gp+NyL5z
5l/jqSQa1PwwwE62kJwfHn8ogfyxMN+j3iQe8C00+FmhvOc6tffruXd5rrtxMkpGI7m4Q890FyDE
fmxC+jJwQvae6J+ADMAxQFgS7xqnX7go3WNnH19pOTndHj7xpK7IqTwVURHeTvBWWytjjMOJrmg+
ZSyMBjtQS5N6cJyMYu/rTBAr2qwChVXQcUcln+I+meMAu0ZFMwD88l1y8wOnkzJ4gqYRypXLB97j
ZI4hCGif40dXssrlAPHWmRajInXsfx5QnoVlunl7r92mnEIWj0yDLmvC9Y89VAKB3lUff67Z/E6h
4IITiVPCiAc/E4l1bCzcq6ShmADJctvWL22wcc54kYF8+b6ZUtVAzHeAkoS7Xv/YlH+dOc/zpYXj
eNG8+qG7NGEe96vUQMWXNvGicqoVdw4ZbGIrLUVRgq9M9HPMluJ4FRL+B0wIdp3a84dQTtiZDS/7
k2y6T03JMXRxuez9hBMnqiochbqdmTC4nWIHKZEV+Js6+caFBM6xm8lhX5jCXHmTtBf4t4OCTW94
XRfTvOywwJ2/4+UJVJhFJ3IJW2kcNuIgyBz+esT40aeUQU8uriDTouCnG1p3kpTrakByugL/c3+n
NA61I8LtLtiyNxR2Q5nfjhqe9yUt8ewAftmy7VXNZKIs6paB8EtxrYxCEzbh856C/R6P0h057CY+
R8O9rmO5HzB35TZhZe9QoOR9hB06RPWziqQJX3yP3x5UZgNBIDvfFa6z5vuri/4xukeyj1vGmTu+
/kOlPNCy1vf1vfdmZKkYA1znDAYF+eiWD13bkKdoj+awudirGgRlk1jiPWfE3aKhSwTh4RWltbCY
3mWWoPIb+tJEaSmlcEtX57lwJ35CPfgMmgs8B22OuPbZHpEcWm8lUz36dExNVOiI7BmDuKHk8rWJ
bt9An8HF2uv5yq5sBrEd3xdc95KoJPJ5iA7JSdDykVZmL5T+RQzNrS8DDCAV7HfKzcSzoHwLdY1p
hGnlMkyBXRNjiWUNMP3jr2GDGzUhJMocoTO6mZ+9D29AAReqA04U02DfEzK7Kow0EysbKG5Fk5yN
Vo3EtOjCkddeC0BwHB4jLIQ5fALmQduRVCqWTWQbHdbIzd5DgetzPRHcxc12ghoa589Nsq4I/BYl
c2WkhgEIV3KIIT/KQcF7rUCc0PbbkRYOqUuVtdftTrIN0NhyKFo+8knfoN3tMSpjmK5GjXqKZe1M
aABYZ/lDU0OazSlHilU5inCfusIf4tqopqlF5SSa3gtisxQq1VjBCuWmNQy9RclvvFwNshYS/4Dh
Ms8YQquDID/JKKYiYgT8fB1qaKHy4lW5qa9iQEW5HxtZF3Ta00sJUjU7eJ+cNUJzL8WGiy31+QCv
ZGpwbj+5XSYHMglemtXbGfaKcFnD2pAetFudB52P8FHlLOwbSdtehSl8ln/NPzDj8keC+CBaEnmA
apv68dTBdyrgpGqImyGx86kqCm9591xzp57selVO3O/SxUZoNyOlwHr1l0ezmWlR5uHV966y9UPv
fBk5CPbFNOJowezXtnRxIMglhcZsTBSj1fRuNCzOUtgxIwSZNZkuUoh07QhrV8KMgKJ7ZmSqh6Hr
7leWjTZBZIxtVm66Ivm/aL9Gu/sl73JkJ5VDQ0cd6iUwQnLpgOWRJ5VY9UnhiE4XbRZuv+TAqWr2
DScG/dkVHNwXKeT+iTM250FKyxDs/QUKKtSQ3XrZOb9NMHYj32CDLz+cRNTYSxXBwDiKY27qpx3z
OiPrUTk4tv2Efy2ImnBiPWNK4Z6eWD615bSXLh8xniHxV/z3wRdYUJtbsnPW233NBFDNca6OuHGQ
qosK8nlGN9zacw5NPuUoFG+XgdOkTpyVCLnVTAM6Xh4PD4UHDWuY2crGCDujlCQM4Cqtsz7slPx4
riVV6qqNeQ0PfIeAQB0rfm0ykVLLslBWvmDIMGRah1NWx13od/FyDXnog3gSEngu1IyEimHJNIyp
bK0b/2YFjynPBDSgRE8kHbULJ4f+RPsdgwesRFNvGHU5c0LMM4Wky23JkjVFgimrX5OFo3fPYyci
MRJcvA6TmdRSKBpj+cwIRigB/qSwqTG9dqHzYLIS86FyRWzGCXTQBfw7QuLcdZp7UFYegB9fp8Ov
0h7zfZ99fpps36ug00/aKErRVhEFG2Yovbyopzw7IoFXlPoEDGgMF9fAFYdTV5kcEyzpz49BkhoV
9uVR1577uGD8rp590GxwZXwJcLneIEGYU/KQfMW6pazGfMQPW+fwZPN8N7VsyP0AdnS29b/4eYiP
3rbV7+evv0QkSQ+6B3Q2YXULigCTU4oUmyQP/KNsb7b0HsfDptXvl3UxpeNvYJeUV/Yw8z6TLUyr
kIjVJO3UsN9AvRydWeLLRwSGD4uCPcTsFQ4OOM2OFs7VOfdHkzZsAna0d+zJmv/mAhiH/k78/h3Y
g2N4nRdqsGBaPmT6Jj5XuJ7/JUEfneX+EtcWRceNfDVJVNnnkjROGtXwhQcWO/mxpT2YoJSrHcmb
81VxMeqC3wcHqBmQusbQ83hDDSf71sbqHM3rMR1LWKaSYjJq5uENZnY3k3ZT0lRj5vmL7ELo+RuD
0R5kbf1qwHMVBuFPBZB2YUFsVCLxhoiAvCnSfVmxjiQuR2wL+s4rQre99WL2WiRFMaIOEAKhxyTn
2p6ndASHN5a6CfrE0QPg3pm626TRDW0truhNFkZr0/wK7RWr9yDwEh2q4QlgvfpOMLbxGQpSjbAb
m1RVwqqTYxjqlYBa7vorPFOCGSfNnLRnkkUbmD4ER7AWRq7Vns9h6Waa3VHS2cEdoHcqMrnIdOKN
/6an8fyNeYfxbxaGRpocJT0L+vbI0V/fccN2KNBevOlMyGmiVRzz5k2RZWfEZM6pLudLF01lt8hq
FUJocj16NGU22Apnv4k4wfBh0LY/+uM3ECBbsB9Vql4HZAh6o0I2x0AyKifD1ynqT0s2UCxdunDz
TcDfSuQwpGiKaQafSbvqe99Z4+IKLrJi0IlyB+HWywjYXh6/dnTWcb6+jX780hnTOwBBzjQQxqoU
MxAv112u8tuiFnwe4xcMXEnxOaM8vCAiwW4/mD2gPCufTxrskxkQ6xNukoeJIlY8oL7J/Eihc3J0
iZtkG1VtueXZVK06zsSzHb8dl5iwoTmcdEg3pbZt6g4Y4A4LaCqeWudQ4futJa/qiF/pGxw/VKg9
6FeAqqlcRnN3aUcbHp9+paf9xHAuVSZu9YOaMxzn8+eigA6p0hOVY+CLnAcFaFC7TeNnGt99JiRM
gJ1iTfS0oE3le172U37KYATQhcDl7dDHo1m9jFcNIau7gLXLfDk1JTRga8Okol20/86rRRfdVbY+
zLjarmoSBBg56Feb//yvEwmGa1iZkFj7AoQUB6LCVqz2H7zZN5Q7gF8HoKU2kIUgJl6Q+o/oD8d/
ixIXG5fMnu9HkbnUiVTgxz0LXXvmdJZ8kwiEEGlmI28H6yiKnIN/AE5zlqofy5Zq/aXvafTFX5Vz
Fl2++78n+hBkxM7A5CI0nda9wBt/G6dCQpCng+S7nrYZtpdi0wh18p09LWfSqx1PM5cufbi3W0Ty
YIdntFSWMXX+2SGQ502QEPAJVsa4hJesGgPsMTpu8jAPyRNoQRG9KyXz30B1m4EAWtBlO+VGuOST
gdHOdZRWr0WqhB3Gx+fqCUcIkD+NuF5fJxzzLQk2/D/kYEK4eugP0/qyj/wYKBLSkZR/K/CmKRKX
Cjwp0f06fOOCTRpIhXPDmh2WZ8A1gjnGkDJYasXYaJ4+d0rYXbaWBgrySz27V+EEsNOXrrO0FRhW
gzKRI8ZKLRuwwZt16Aeg2W/FrYfaN1llU48lG8GZqOBcYF0uR45DRZaHl+LVkTptb0+hW/Vr/o1B
jdY7sWFRC14qPKUZlCf2UodxIaN2u/Ox7WdpUjsWnQweSRH9bL6N4xbnJBXx+IOa2CFW8EvnmSY6
w+xJWB8l/zV00pB2DaoYLKMELwbpXE3OCCz3wlGm7R24EY3yKziqQ2dwdDuI8SR+rF/rzBZdvvAz
hw4F7ubWqigo/Fm8o6X9UZY3cs44Rk2pg8ofCAGeAbqTCpBIG28ECLFid0/LWNMuONqo0f8ETS2h
UC2CGmW2K/MrC+nFLJ8BhtV9ALP3jKyGLSoRIS1SXb+HJhSMNEC4xZIbV7oQUvSZb4C9hiC3p334
Kuw0PB230EfHoYQZEmnMDL2gscMp6APitI15QZ+pdS+xPjw5InFN9OWG4PmfWsOo9RGJIc23cGju
coMdMKpOAcLKx8qPhomx6rdiNU0D3xv+6kjkV2VwYxlKNI8PHkhboYiQTv+LV6FyvVXUirXP3Sax
Pq7mRLlKMgM9PHddW++ZCyjt78BnfMe7GlbEb/WYTs2AMcmcm/Cdf278B/R63MDUv8vFRPb53vUe
CzmgGmFxotG1WVLDJEkMSte+UKkP6UIXIPxD6U+8MRPpRgSHILtKsai2jVZtPXF66TtNsU+TbB2O
MF6h/r1JtKGwAoe/CPb7Z0ccr6Vzm/ocrUc9Rd/AyTCINQzA1WJSCLgUuQKDKq6Zqv+ctogjGjcQ
h7uuJFbTiNyeF8E/kISITmontc/nh0RRgIEni3n9SKusV9iHTaXVIQeQJmhYjlCwcI8u7x6GSJBL
WErhS2hVwDVooVGqmLlFkyvnBZEfFx9iQujbUxLfUmumc1sB0EXCzVqAk02iLzapQY8Kv9TElRid
YR4Pxq4uyn38UQCaNV0mCXp3mrjxIpCW6NIgsaqnvyEikk7lWy8B9nWgnTfj1jFkVDEuUmDjZIzM
kDhFzd0ImEqQz6N8ksHO+gK0kp6+Po0X7N0bLDMjH33MNkPuPfLUPpam9KT6zhPxNkCUfmJN+ju6
iUG6dOJL2v38xksLK/6Sx0WtgnE/xxsSliSumVnJLGL/+wvwvbve9ozSyM2+Y90UoSpUoanvDK09
VKlis9ivB85QkNsiGPPjWM27nLCWdi9gRNb9Gxn5pOOGf4Y9h2OTrIXn064ehkWMsvjFPZFFnVXb
T/JQDSbMB+3s1mULoWPZxH1U3buvDd3zSIJknY+suQs7DOjz2x1WpsGiu1U3NE89QBXewgG54eyx
pg07IXANC5HhfI+EHd3Czw/JRW9BJUCFHvRZ7wfe5+IwCDgx3W8aZjge3gRdlyWY4VxdAAbEiSRf
ERb00/QZUXhcKwV+ol2sNDtX6eLD5pqZpr+goWRXiH3XKdon/3EHa0AkUemd48FjhiTzQ2X2kWA+
T+Fli/tuuDLaqkanXil6gedStUo6NhZ3XMdR2aKyBScUQZq1H0/JqpTQWe8hXNVxmLjLsLxZJez8
dRHd3Xi7oXk+b3oM7kuTgl06IYjZ8oyXbDkzLECMCL+0vaDD7aWgjzPnCnKydSFQzHMnUoNGUxG0
zEjyL9XaXkSk7ArDF/F2lycUzKivWCuFiiVqZqJDRRYJiUL6EM2Mfplzst/SaImxjbh6z8EuaL41
bPChAJDZNat9xUISBzvkefGambOOpYu+nSWPPv88SudLa23vGGiGmZumjK17pzkPKesiQDxZr8s8
jsImpLRlEbnOs2nnwC7EgmO9uXi4JE+Vb3B810pMNIawcd+Y0hB8Pq7IilOe3wC3avCuEIpK2WQo
S0szYa7CyW7GcuuvrH2uM1yT5B1nm8iqLxxmYsaD95Ikd5A2nUox8m7NRptnYXCdLxtRybdmholu
Cpzb9i3Qm95Tkrb8OqZBiw146FnpcOMFO34dcVV/ctlVdno/kZTTFbQvGRvDUJiHj+q943k8zFro
5V+abMFtjG5erEnAuM3ELHo3kfiW2kZXeKMLPaRyHaUTvKxWs5FFue+j0sRVjV9R0p36p6DIPv+1
DZXUy5DVWNtbT9/YM85U2a8VwBjS1LvULWodWffJgWDake3p6x/CQ3Mk7O+CK4UxgDPLuqhos8hz
C/YEtieYjMuTTHPoGevCNG/HVo0JgM6EBRvhitttk4Mk6OiaV4NdVJiwxNCY7ro/6PEuoJy2YpKc
uTm41wz9bGqGlu0+MgKX0DAeL2fz5Q+/aBqTY1vl2dlXtjSb64AzdlBlX0bDLO604GJblYTgZUja
OYeSmXhKCK2XyJ93ba0SEvSZnU4wCGK2UTNzNuB3S6UPnJZU1vZjb/C0EamYLqI7NuAnJHYjgExJ
51lwyyghmE55baDS9W9hHYAJhLDCCrVDBBLZT4GfVhJbBo0zmRCAv4rpPz/+V8JtsKnPHe6LbeMG
OoOUNnwT08u0DEDPYjlGSz4itoB9Js+czCAUiDLeBerwTmK97czEj8vqp7EueD4KLlsMS584jZF8
4BeU7YbwbrPe2jf+4E7+V9RkoZxMKEBlQ+8kaCP/E57GqylmYVZH5I8soiY3SP96yZctZ/W0r34o
lWw41qbKaggjElcaFIaRPGdVnQBXD77vuFrHtlc4/hAC5dsgJTR3VgSJkfZ583DwUvxCfaCS82pR
OJvUqk0xMTFqLnp/s4I0xvTb87W5BsVq3ybegUZrENx9law+drHdBwUpcrBRRjDtD4jwYDcckjfa
2K5xMf1b/44D9RTr2FPrlk8FJ//ScLtLoKzHZ2QfoCxBR6s81Wb8spZX3HwtmCc1mjIlB0W/sQN/
pSEqQaxBYElDoaSqTjY/lS+VvpP2pUScKIJV/tlZvVl5/P9DFau6DmrT4Q331lQtaTgOEV45p7eC
99+WGfkPGCs+FUR/LNrhsDOHZupf/5EJXJhFy/tkY+OEhFtPB/HZ//nqxvhxjSzYSG0F0GQvHpP0
rPjh04T+jbfKUoKToYg9AtS51Hp1RcOLeH17RN6Rc8++6S2cKZaMkpA4QcQmvm9FmyeCfQCjlpFN
SDaBkuP0CT/mZEx4k9MWUdj3I3XP7uC6HH0iepomRUicOhgXl2EQfGxD9x0uNgcXnqEABDwMLpnf
Dlo3dm6C/ShBdUP+QIQZwSaE8vr7FZa+FI04FKkyWo7JdlrKY+cA/LuTJsXfeKiE+fRbrHVZtYUB
ktuxv0JWquLn9uA98whMJ/1XupSVGRkey9Hv9umj6N6bJ/9KV/w3pz2f6w0AMxZBpq/8DAEEcVVr
Xe4cpwSyUVLSRJMKkEfms1tzyMKz1ir05VWNcx5gqpZTR5J5mqPmnB9k8eE9VwikZ47ffRzyvSUz
eMQLeAhSEqn0WiB+/dL8VazEK73658E0b52wHv1DvHwT9a+u5B+H0rlfCNGNFTbOQTIcQraZjnu+
koZy5xoUeCAxIeuq5Nhe/AJsV/tMJUB2AIY/3LkOvycXiNC38DH9s0uwyHfdPcP/yp2uBAtrJ/b0
FTCtzLOeeQPrKwZaPysAPPIxz0MmPmZ0liVmP0h0RWPnkQzR1jGD0fHUVfI9lTtV/H3amRSVvTTv
DssRBC/EXMPW4nZLwZpjOLLX5/NR0yP71GuEN6tPbw2wAUAJgLTgOKApbMmoryLQB+uv3Xgi+J4H
NUYM0FDOJAaaOb5n/kSy1VrqRX18WGhhMJn6MM4+bweeLrLwvShu0NtGMCPv0y1DflQWtXy5ZJ08
bUHpeqlCp2ISEjo/SZeX56MsbZS/w+TCWAPBuXKNS8uYSMQNbzIgl3yEug8+eYbO9RMU2pwGlH9T
9vTtBaoUbCJcbdhDXhfx8Q7gZ1U5yZk1QAJafNofE7QElebdaHak8Io/CQtda+cDUMMC1mpHJ2+z
qmg0KZw+j2FlRzDLZOlNYWyok/wag6H3iBO8s3MjzEpW4/O3b07SNFN3sgqSkvaaJcdJfv8hpOna
KbDcDnfeUiu5Ck+AhA1oKF7GeD3jfraCCzfsujZtldq4/pjY41Bdzq/4I9dPNLeaILvSVyH5pQrl
j08SFrrbJL63A5pflsBYU//dwTe9Qx4UWvrLpM2bUq5yVEU+fx7KRU4pTbqnu5gtJtBiqS5Ij0rw
2j7B46WeXs+KnyCL9Tg4AvLf+pXBYsWDWYeq5Sdkl7nZkHo8nqmtno5apylk362Gv3AOzbyVgs9P
Bpxpfi3EgyGihFTkzIF9lcNVBL4lU3DF8/ohXgYj/WjvtqIJItHXEF53//Sg0QQ09rdOojokQRSx
zp1AVmCr0h/zkgZIsFeGgRQ7Kj4gtOTEEapLxnYiNBlqOQL5HPLec+qfIfUbN7PiFsF4++3Rit/c
minwlktpsV3n5zA8QGNwrTnAU/O3NrhZAKMY8SiXnwpIE4/G6VGwWGBlmZCIbFCKukWj4RQG49UE
Yl8y6twFn+wLm3pt4NvyOE6+e8iMo7Q4YdmbJeb8C3HLxB9PJffm4rkbD2D8B411g2i3JpLZfn4i
CuiyfPa5FldPs6jF8SDrBswZpodKsFUgHTwG4VtRbuQYGeJ2KhAL4ePKCwcPQ0Bchtg2OAaPAIHW
0X73WBQ7iDuVInzRmxX9LN3koS+G8pXHkt8n2K1o6fv/p3mexDg/L/oZL/1OKf7kX2pzchgCnsPj
2S4W3vBcJRrfGT3UUyzU/xPYTfAruDqXrj00DWiJLL34Z3paRp+xPYkpI3sj5S8XV+CxXudr39Np
/PulNW91MznqlrSSto18ldSZnZ/GuhY17y1iq/lop+UrJe9VBSiAMcfIcw+j8Or7njc5nhscUMUJ
K2e6lBfCF2+3nv+5a4rMdZ2VVsKbvei1ozIcXHoWce0fYcACcz4/KXJNpdcSZl0/UKYMWtaGZMLq
qmSd7UaoA3cn5VC6+VIBdgmZQ20gj3xxTCjfy0gbKmjYeoNKZC5Jd+6pw1HUExcsKLkhj8Zj4VLz
jWkJMz9jU6fdXHqRCM5T6tD4ptXnEnVK1UbMD8wk6WcTPli8CtJDuts1A9rNrgJ41U+8ZBTBZ/U1
kl8aJ2pKDBUZCxgvL9EFuDagREyUcGQ7QXx+JESYI2gqXHPmaNEiOuF6r6SGrLTdvNK3N+YM4Jm3
FQ4BKz4gi9DlrwxegtfrEjHwZJ4FIIuGk4QScuxQoU6mjX4k6OiPi/CZ4hWg68cnzt+LePEZpydA
nQ3qZwwf5AkSbXE+NDPS9icEZ6UZjp4fGuHQBgiSLzi6lrA+RMVR7Yf3OmywMn9Uwhq0gLssY5TX
XYimP0bMl+mnaVBElnlgCJe5sGj6P+2g4nZylfZ4HBzWcWNHw7yTb/Tkq8TYunkbyYiwOmWySa43
Fp4r3fht+pEvNqiHtWF3AAwtG0QP6v/yVywy+hKSaYMoDdmHSLKMQqVgi4vCs9lDENzX/Y2txpHT
sWMiYh6YGcxoZ+5eGt5SWF6JnJ0zmyiPt9qIX7DzOTPjSDh+d5LERbdl8HNvmSw/7BtSyoFzyuXP
jZD3ZLKLs4irdqiOLINiWf6YGz1EQhXwdUVP7abOVjVO94fuKvY0PBzap4U64oTgN8tfc2WVRCjs
xgTGKSWveAwu9t21Bb0ypudHyelHvb0q/dfByUGzNa4dy+1eQ/WRzrlKQcIYNUCaJcvLJMGl2ogp
S3UGHeXaMckjup3bntVZ/6jF7awijFpMiYssBvurhxuoz+/h3E5XK5+1O762pTVk4b+YqygDQjxv
oZicZQYrfB/1xAVHJCFqicraQHzmLtWPKt0hxQyxUljSjL6sJxo9e21gY+qBGvsDmBA/Jodcb2eg
cdlHqhHfgXK74FTgE7UXg4F5Qab0r1gfy5SNsXMSzih5ci1HFS9zinnPlVWu2HVmcFVqQ1iAQTOr
in6fNCzARUd/Uvj1r67gXOi8lY3ygqUsSKD9hFqCvaLTALp0sko46FpTRHhxP8vzMRlzrBbNgjC6
nPv66NeZ+fiwTeSgpthrmY4AzcfUcE06zAjaAksOxf5vCNkyxWqbFqZ1NHUtrFrHMlfKYMR6MYI6
gGloIr2jad1to1FhEWkKPFByK4wSE0w2vhKZhhgYAYYdSiYXFYvnDAs8KdYuBROn3IbzTOjb4DzJ
mI2sQj4khXSz4YQj0KvwP6+BDR/kwm7fG2qSvoxZU4xNsuKzyu3TmABa+dUfqnVsF1cFRu5QOiAC
/0PTq/g3pPEKbU7P7bWWl6C+X0CDVPH7kWMItaYso4qjkhPzpjqSHKX46qYNTbNDbwV3PTzWjUN5
TmDLYh8j5ZRCwTnG2KsS6UArEhVFJjfgkextIDOw3wMV5YvW/kGAyNfmdRONVse25XxN++Lv2Cma
qt0OPjy7oYGJe425YpFcdzF7ixl8AZtwY8pSspkV6me2P1v4IAMOOjsIUwRzGDTbTHO1bryDVpsQ
kCda+VN7H13avNrS+wCMPWXs8F/ZBS6DEazVLUVu9Y4QIg68FviVWBHB8ymn7h6AOk9IuOs4C1Dw
bZfE0f7mufUT4LU2ynnawt2GgrCdJ+kjKBDwxUTgZ3S2CeiZZ2af8/ePclR3q86jQBwf65cgI6Om
InsWE1FiEQOu0Uf/1PbRKKn7fuqIuix7+WteCMe3WJSmQu37iZLhTls4J+vqTgA/sw27ic/cce7j
Ek5mNGs6kjRUpDjWf2OnJQog+EKwk9KhZh/gtrsgo4yx2IF6/HOL+HMEuumWd9jusa3ZSl++f1Pv
G1SHuIlv09USCWfNDR1RaQdOQ+sZRy3rmnalhOWwIBxbS+QJSWVBMYE9wtGqjYRv0YLPEFZLc4bx
lSag63wyXJjqHVWndYLPArVYcODF9BUPMkxJbyrcP3SukgewunVjFQkXClXC5ItAeIvkaAkeBxUG
xPxRUlPFOCpNdpsrE9DtAL2Asm6ASv8ePPz624VQeEAqfW/aeXDcRti5dJo+IAhfflVZYCi+9f2b
K21XFa5N79h2F65dpzcK072Tc/eX7lUJlUKE97mndt10Rj7nwspRpRTN5yKZPsPG0w3JtVeaWgAw
7ORuD72YszaDD2iyNGA5/Q3wyX6BEHwHr5WLLMP0dBZo1OTiaLbzcb31XZ8i8BD1vnsBrzhEk5/e
nmX/7NKYSLW6psv7Etwqe9AX4sF9fd9BY6mHa238NQ78I1edAwP7fZb5RC3+3K/mRqlyWNOuQEtX
QfSp3IpN9pM3Duy/6rZ60SAuTorvAigQluLZOZ32SluPVc8lUSRbQjiiPqxQn6xdZwQfbbpI/Ayy
0SedA8m6Mn1uacuDMbKbfV6GBfhWw1OEHKRuyQhgmVUrmwWGmqDE2kj7/EqS3DGL9f7sjXFiricY
a2F2wDP4NpezH/+4R4ODAfct0xTD/DE+ZtJLyX9gpf/sa0fsla95QTRt9X95/Kq4nUP96HLAdYiX
lGEMqcPqDzBeF9PFEJjDeP7288xC4uKs3XTSnhrCwP6GTU55SNbwjbSLFUniC3FR+m75eXy+QZnf
SVAHt0TFNCJmr6h59UIUdE3YdnGcUcJQvhYbbWZGxyWSUn7uJEKQZQmri37Obx+4PMPvwDztVVR4
1PwPwR/anviEKhh2EV8FRmV0eFh/w+P49E1EzpKj6AkHf/AGTiuneYmzGQmU1jYxy1JANi/gF1jz
CI/A+EwZknnIlaMWr9K2xOXJKH9hit5S7EIygLGtgA1vw+Tb8JdbQVwXT8CLYqHEP2XotqDg1+Wk
7Mmjgsrhgu5x6UIK0n1v5Ik20qYvwOmX3NTcwE5zxXo1pWs9fiOtg8+tS8YU9Masp0fqzjhbqksv
rW+Sdeed2U9aeGbsTDDVNJ+78mFbYAxmaZwPnG17XyL/LKdbPeWyWrKIlK5FBfrRxduoc40QTJiZ
S4m7OvsP/Y0ag7VX4mIU5ft3qVX7c7vVG0gj2IQrtiV3jC0WWFTDSQPFse7N1D5pXgkeSvCVXdHF
9UqYnFI+2600IXLrsqPb/Zz7nqUckqhZvBMmlMfJX79UziFDo+k6kGOKfRaEOgE952iZq3StzxwW
g39VWyOE0peo/FMYq7cn+EXFdAgiiwA8fq+VMeUHNorO4TuNEeJHzlfm9VqipU5mmPizIjS/8kZp
WH4otR4Vq/yWlycZo0NTeK+jXUULh3YORp1sO5MpXdihfc913IcBFYC8h13F8rgB405kb+msdTn1
yM6xeMDWDE2sWbsVMgEXZRQN97aM1cdz6esbquq8+bMIghWlH+LiKID1QgtwfSPKNADHXrIe39JC
wB4lh6jvzj6hVZBCLW8iMYK7xF8bq6QEIkR6d3KRh4RPmATf3wJrxAvwsrft+iegaWtOzKgaBaHs
yVl+hj1crUpt21knN41TQy4Jl9GsX1Mv3uaXwR5/CxF0s/pvxASMnorPU7TfxFzxiVvjfzuKnzpZ
Z3seR/Lf76u5d9Vg1aQHe7i8zPMD44OPYFonleitxkJmt0nY3aO1F6y6JnawQGODi2pw06hSOZUr
Hv9Se8KyFz06M4ZgiahRM4UAVOK+gvWg21MB3xmk2bh85IiXuYFSMUL+q1bWjI5/3UeLisIEOjN8
rohZ7AuXmfQDo/u46m8ZmmUEIjwVw9U9LVAPBqtZlxGbzDvpGcZ4R0Ri5gbwYvFqoG7Z0C980mNC
7VfrwZ9349Xuxz92uTIitbVVN5FE88W+eyOyQvLPrlPJ9zzz2K70unVCNeEH1ghai/TH0513mfme
nFqkx6zPc0Sts8pSkE4u2c1J9hf3t7Cm3fgmDEPoy5Z3iqv0OVrghX1x5l865Ry5tgbT0eEsNUmK
UykJxkvQRtyvOFtmhpCpBpbXrrc5XJtXFJoG5AFhtBP7hV43s7n57uZPIvFeEHvskumUUjcvnyFn
b79QJsTZerNZvgQ95vjkt9hyiHwGPb91WIjeilYejq5+mX9AIvS54vjMHqkesysJC6s/hB8bHfD2
bbctq5Q3mZETsBgvq28nN6MHAUs8Yq452OYXUxpbZov5nYHG85rreBfrUHfJeUAiKqQuSbJ4kSLD
79+llqtNxDBrsd3s4Qpj6/lQjXUfLdv6tgPCZ0ffKKyQgm6X64C2Y5Xb7/Qz0+uCfPavBYQVH+Du
NbEh6bsRi9BpBaziiHOuMLD7uzL1CGGGwB1bIcH+73HvJUx3cpIB9pOIRMBcB/8ETQJv5ABL5PPA
TSk9IGIZPjziUm5JbN1JlRwpkLMtsWF+yP86UuM/iD9X+C9yMpAFohhbvvvSh205PagNcp+QQmyi
Vzw3Ete972DqNh3Ss1doLxSCgaSnpo5FRz7ZhcMfMSnaUYD/7HPPqCB/tkSn7AcX69yTjj9YNwpe
Swg4nfb84DcY3svF2VBPTjR8dSyzXDc/oE6cuoGFuUQlxlz7Oq5JFQFIdOK2dL0bv7hTJR8NZgne
7PYDpF2OQYWhq4elBc1UUlDhCQzm7LpGXMOuRn8y+sRePTMoC3TwN2EA2eDb3x4oAkLfZyWVTxM2
IhQclKNpcUwcxqseAT5xMKpdm6EIfDcMSAKE0hqW+zlbmYTkNC9pauGtE7tjDHIKn8hKe+cX/5TW
VJLQS3ZsqGdc9t/TeDJtG0vplJ8UKbHm8AhRPKZq8fH55k5xo+2QSH15WX8qD8aDiKq8c+lMASjE
mbRkqJn9B0vPfoG6t2BBbjNy8GbanAlf+2nQ4+XV9qo5twJkoGryKL4zYVpGs6DBG72t07cIVTog
EIQPPMqj6I6VUcUo212KBwb+dKLHnRCyRvgQiDW05B29zfw8pOmolpEZWC+3BRdwo62HBYGCWIKi
Tn2c4O4veLscz3U960O4LHD/bC/7xNyklXJCzh1PxApiNrnCI6BZmF7OXFewaXS7d/WkIzgofg8n
yQxDRKVHIjYyI2GGAHduEEC1l+1DROAmM+VCbA8X2r+E0ixYnyZpEsv9hUqjjNaplpYrjTxvTwCN
K26ytWR8h1sxsota1SuMeGuWojWKc9k+rxaqtA2FoAqeJyoiAGIqV/QEEPT2wCAq0pUxUSibQHai
LritFyOH7L6WEwvmELiODhhyfxL0SteNf8X0DwkLyVQObptQxRCuDuGYjZJrnThZApH85Clucjk6
GoJXjpFpxGI1UgFzPZ4xCt57UHvsKZHYiKIZ9ARKuUODaguSkGGKduOp9AaZreIDE8sBecb+hY4R
ZSxs/rgxiUqbKF/2fRCaerLg99rI8MgWSj+R53144iD/RENGmaVcfEMByHYvqkKgu0Zdz3q1/CRK
NZGQIkqXo4wDGhqSdGafXfkJFCwiy8u8baKr86lt6Wegpr4HHgvl73+lq9palLL6O6WqkNC6yI7M
C/c2eGcpQ3JV8aQK6WoNNiII5setelIXgAFfDFyKaRAQWswmG0p68MWT/HdCuJfxNfhVzUWB6DTR
0Rn17a9gXOCfRDY9XYf1AM8FYR6rsPVzDIsaPVL/RHNZTM3y4ITBUACgJ48p4Iznky2a7rleKfhR
hOHQzuSAoYQcNIWwtOzRbv0YRKDbh0/qlkoeyFbcWdI8Iz/VxuwKUg/SDnu5sZCWHfI3/9mZzgKO
AWLSWWjhgMtjNu6eXlJDC4gaVOQrkFX31xLzpUVAdplAPPwkNa+yqY9pCXcVdwkt3f4tBrdQO+TP
9ktYGL8ryCFgj8HMzrcKBfvSvnhdU+zwRfEnobFI7Sg8D5oPSBQoX8Py8l4OyCVCqF0YyWV0Eb4A
M2i8jVlebFv8sopoIvc54y7FTAYpsQsxByNKA0IoYgweR177IN89EiTZDzYln18ezzk/Lki0Egd2
v2Nm9vVXP7rFljhUrL/L++YgrNXQ41THddxBw0P5Eeu+yGksZBCAXnPePyUkXXNGmKXMCcTOi5rJ
NFhvOzCyjh6sNYQj6+vMZiHWLBPzdG7DRrOlXrOBDgi53B+Wq4JcemDzZxZ4y2Yp/vP6YmVg7BZ9
TT7+7WLEcsF4AsieiVyT21fpv5hKovW+z6QdgGZOdEiLjCaB7ZGmgri+OyZmz7Fv1RqVOehFVSbB
3oe4IunQ4wzNGHxNjFffaYKLPeWSuNpBeuGHj60mBGYQ7YSRPiziAUD/C3l8H9hV3EtGVJWVTbId
xWrmsao3axdhTcIlnjk+LQ7224VfchnHDBmm+8zlsilmBeCQMQvRcuXyA9VW8tuVcHcm5ABVlFDE
kmQwMtFS9Gg90U0GvnG8GQGUXYNJuy2ag2LooxmNXX7jvqtxdnhMs+Cwcx7KFItvo+jDbPLd1HIJ
MG84eORuoJYWezK1R8S7+xcLHi3SwygrIfpx4N8uZ9BDtWPF8c9cRE6jLO4li1uk3nsrt8dhnC4S
jX9/7QYSvv/Hm1JbI+p114rii+NnH0Zgjnn7lVjukF85h+WibKFny5nCBfZtGVonYTqD+bZkmAVE
Ec1rbRB07WoDCSHUNpeDa6KVbWtqmKg9hEpc2ucbptLc7JjsKa3aH3HSle4ynMZk4xHjBN7aF08y
DZ3ux1QX454dV5iu3c0JIN8YEhRzZ3Rgmh54Aa/cXyc+w9Zv4O7+XbLEfFKumNjXx+UMpzrzMZHB
T6y3LpSy9ZDJye1akQ7gR7a9wNlmmkql5R9hpoEo3sVTLryfp84FdXX/nc7+dXRs6/4JH2HElz+B
CE2Tm7/7crv7xehEVOQrVls1iH7jnIh65XTVeoC1cu2ZFTMlqUDebqU7aYx7l+DYZrvJlvzZucsh
uLHjmk5FTogFjvZlh/wymugpZ/WifgaiTAe092Bbf3c/s+Kqf3J4zQKi3gf78EWqoq3D1jNjdbwy
evrjor9CJe6pucNsspfCxZYMifItqsx4XikS2LTim1v2oDl1v+7V41aZdWYRqcGlR4NAwNVL3VSA
mnGjjulVwgc79yZxzZNdsdeM4eNtLlOHdlu1UbiWXqd6h6LUMx8syA2136keLM4tDbW+l3kex8M5
2A3/wxQFtmw8aGo9OCcUGYo6tRLkSaj4vQqUH9ZwcrznjRQ+12qcDYLO37sFUXKWnlxpwLATbPiU
cRU3eSunGBg+bhqvfYF3Z+R2srBjnTJfitlJGuki5ITL6JhHKF1b5Hsc0EbWRuX4I0Xb/GpcocGq
i/99AG4tep5ToM3yMagQlX+uvXsbR2z9YLNe/wPqzfyK7XfhrfzWMhIq1WShqudFHGjxSKw2YRTj
Ly16ImDXJNIJuGc2KNrVx95/OYZzekYzorwiPY0VoVomp8dHrssHhSabfFQo7pJQlWSAdXhLiXZr
9GOzkZq3P5UrVEIkYRek23NkqT2S4zDF6iRYepVhxF3ERn0H7ESv80pUHBfNSj5U7XhS2nItTCNb
9nmkpgz6kFMGGff+INVBjLhv0H+PthgLc4tgKVbUAXHiVIiZfj9gBJHMWDWSMTUwc23Qpe2UZ/dK
Y/Bd2k6cR1I5Rz0qC45BRZ+yAfyaqqXDMWghPc/0zIe1EWyDiWA4A6aSKpo/oRjVslVhBn1HMelx
4C5N3gXLhchAHTX6QY80M0BfIaXrKUvtVsGv0YEVK2+T2fQSjeNteamSKqRg/TFY0nN/Swb+eL7h
mw2xwoPlh4GvjXu06ORa38xSmJ3xo13pdIRR1t2/viLONL6kyzlbZ2a7/wm5ueXTMSLjC6dqqapG
ZHLYs849JNdqB8kTSX0y45JLKrUW6vCIooHdknRxo4BodoGvOO6e/Knn+4Nd9zHoXQw/ayZwYFg0
aOxocH41H9fN12CgRpZh/UxmZmp6GFGxyxu3r0AY3OOkfMZBRt8pi+K6dLePvCsZdy+lxEJYl5Sq
RJfnhf9OY9rk4wf8NHVl7Jv2h3itqIZoE+r5KPJsxR4Dj8Jl5KlM/eY7fXOqHz/6dTBilbr0KFFh
gzaHcNnugE0GmZne7G0OhkL6EfyIPfmlK6vHkdsx9CRxB1w6vgVgPoJ1THnB+/0XnY3Fo43mZfyH
KPQQeH9yJ7T7SXhfCTYzLb1QJiVJflnOZZiUihnglzB4dNsNEFb+MVTRJLs0T515uSpL7R9MuIBK
+YN2EIkQ/D/7wEHrAN0N39YqtgA3rUdhsnzB10Afnb12yruL/zyzEQ4AuQ/Cvnw5LJhqvvmh6dF4
wYSAUNbLKU00kknglrKYathQmQ3vJ+u2GDWwlHdlr3d0FtwPSDuPNycKNbOfpZOdDNPazyabdZ17
nCbU5RAwemcxyWIgfkg6IL2DAgJ3FZq/oXU3V+w5EB7aWXPOKbxXm+E5OmJPR55TyYWZbxM6B1qk
iUnYyHqLCLCmXM/QjmKWN4XrvaM8v3c6hmIB5QlAab4h+pKA085gLB91d081NTknaC4b52kc1lZK
Fwzy+2nOLMTYo1mRx7b5VYhxsCfXSx4htrCxtYPKiSgiwR6kQj3oTgpT86vL+OtA+YZ2bDmpdqE3
zYaKBFJsU8ejc/3oFij6+FtXN/4y+Md+WgEI4txfcVReeneRdLK+lLDHoIH+xCZtxyv47T+ubNbq
5tAkeGV0DCxq1AjL+9Ge0XCF+ReSJecPSwwDr6KVLyKOYftUlKO5HuQd3oa0qhCF9TeY6D9sVp91
g2sGhebJq71Eft7xXZ4SlOFly4R0ZhQnUqYidGkM9hoUU+45foVV2EBt6zn/fI8Krm3eZKEkYu/p
sfKdu6dOp3jdS7FeVGC7EHfITiyNMzGiG1C68iu59/A8SclwvzC0smJo6E6u6+SMAecWBqQ7ve8h
OFDFYtQ/svCm1FniqFtTerF5grzJy7phIqdlh+Cc+N+pbghvk/anUmcwKfW+rvVJJcA/IO3zEJU1
panYoNC8ADTfmZScOECXC7ojdCygIvg9cSPjPYSQlt5Q9QgFijUf+9PZWdgYFE3w5kZyqinFEpgX
dYXuaTzETo9CEywMGvKj6/R9fhI1kaG3bk0+uWnXiOo/Dr6pNyAhR0g3wejk3KzyVUFto4i8VjKt
YiiQx5aNFnRFgfFWBRdRQInZoxQ4gB65W0npCVa6YyB7VMfpyoy2JKQ8WsfMm61YpPxUqwMdqQfk
ynyMpgTGqhZSIScGYMhSd74WPKeKXvdykYbwidu17hdl+pr1ak2dgDs5EZgtUFAQurcPcCJr7XME
C/Kj30SY5ZXIRNcRaMkDvQYVgfgo9vKTxzoWgd2J4/WWqfZ7rMG84IbexMW8i6La5qWGNId3sjLT
bl+nRhz0w4aZiqz5V5+W3rAb2w6jUgS4cn1to0klEeZYYklfITuMlGODBZLrcmLBlRfZ2ujuCAaO
qPqUS05WN5KPB+4aB2vu5zCXf1jho3qFNzv07JfNelSzcuuUw5XrL2pruzW8/jQjqx2YQR8m52hp
YWyEUksx6nkQxKk6cl4txwhLYt7XBvzH9DuRhMdmBdmoWHp/Y7o29BkPKirrXCBRwzWUlA8oSl36
tYoa0roMytV7jzc4bG5D7DXM93SF61sYwsz+rBenuXFWtXihvzzEvo+ax+DTP3pjmeAY8rBG1IdZ
SsBnpUy0ZEeeK4RMfrehl/RDBgPug9ELO2tZaNgB4VsIRmPHwsZqTB8n1mw6/CvVzWUH4r9tiDY1
LXYFtcMUzlHsr8ctWSTALQhJHPKprcQLTSPdJ0ngFcWUrohZ9bDKVAl+8odwk2I/k+TWRZbgaCYU
1SprgLyenQ78Q1jtGXV48vv1yOv8RWn8utm0wYNbJxHK40gNTxWmjSwvmKjWorn9LgEehZbm2EZd
PXZpzliXUyKKqlZ39APl70Afxx01v7hQVIkiErjFYMTBugf3Lfh7bgreZEr1r8l4QB0OYUdSNxNt
JkFEhy83f2zFhIEexRiDzOatyzilC0p/Amq6EUK02lO9UA4mjoyfiPWc9G4hOiziaozmcVt9TmDf
z72AXjQCho4cAYX+MFkhDoEnkUbQ0AHx3g9UKH0FG5tidm1qdyFmseu73I1C4KRsLuXXHT6lkQ+M
KrwT+xObkJ/JljMlTBpXxeHY9fU0i5FFYHVa/BSjI+dzS6dVrkJhcA5tERnfYUJMa+1panf63qJj
eWfd8ugjBOen0q24R4QE4+NSA3OO+kT7KV4oa/rP30SwpHAt+e4+AOxsA6VOPwCq/8lk5uEYkZ3v
viOEJgByGACiMtmpDTX1tF+Ed2sC3L6MJshuz/+hilGbP6nZgERl0abGRs8VGg3h9p07r7sPGhIP
EyN10uqoGnHyDk8X+dZVN86ZdA07t68j3Dv6bmrd1iEZdwRNMbxlLytbRVBb9LJmPytckhiIXYKV
9QpFFZK2n0eHryNbaDyapMsMLzqkBOP9xi7ED6MtY3BMb85ylh1NT3D1vIMqjmIOXpO0BqATKEQx
0UHx1NoZ99f9MD0BAUNSr/IvGCpU+66y60QJM7JtXGzVQkLDuGbcyD1sTqJn8HzrIwmUvFJ41z+i
aqsICIbPwNEt7TGifRmuvxvysycSaU3e+pgwils4vWGBI84loBDBUbOLv/sUPvFiGxAKw5H/JJCc
afHeEeE7zV+LeV9juOvNVfli6CqZGcg+MSKjsLBCM3xBZdJ4pdKwC7D0RX437hJ5QXzTVNPtb/Tr
2K7PQjhGxGFdO4PrcUdXD2XH7d43PuMsxScobjD7QvWwBnEZ4njSx0O5kOxDpgqbL3AqSkUDbOvX
UgZ7wKVUqUdkoa5dmx9PYeaRMYgzz3Mrsx5a9KRBecN2Y75WkzpyHpk+8hiAemeFqWw8+T3LYcM1
1OHI4Am2Gj7j6iC//rywXVqvabhY/2rJ6OX8zR9A5zSzocjF6mH1uz5O0vuAhkEpzs4hSqkUHaAj
o1rSCx8NpGXLno1ko1jH8Z/Z4tySvlP66YsgI+Y9AiC/rg6m/jL+Xb7j7GdiE14tv3omHkPgrr7d
iAehAWhXN9TQOIyZLuFlENaawMHwoCVghfz9mytxqB1txhUH26IJbn3YvjbuatuNa+djlps9KMb8
37UbNB6rOdako5u/31kjO77bts8OFrEbas/rEW3ISWqx5Uv9QupGuK0MN7uWSO+Z1axFGRi/Rttr
/3ZY9U4rAJl5vC+F0ryAK2txb7ZsFeOc6HITSTNq1QzQrlleqXBMfRDthP2yifN724ZIYVpaA3bJ
wG+QZoUF0r0bNirQfAXKYkaCJcdd8UBMOthcNJ0vYQgCy0XUKg9RE9xBCw3JFK372PfT2wGkycvW
vFdn4486+o3t8wueZVuPiChMgrzgoZOFfWc+AdKTkML0HxJmiLfbGSOz1ehF7VaqawDfJWHp21MT
aSFna1B1Nq8hvj7pFUB/+tgxYrR+GeSFYo+QJUqE+CdL7Y9MhAGZgVxoAru3+7ma0UrGiP4XPrEV
FyxQ4rhGYJW08JOEte0wHwuRnNeE6ePb580i/XU1BbSPiI5TMdP3IME2UZzjqbKbyihhjeLqPFhY
IE1tR1vY2fnJltt9vgttNKpzZGKTgpu1YiMUv2ZsOhQAvpvKSzwXsta4FdqXAozmnwaDJl1TDZe1
XdBgw8ufZcwxlmqogbfi4kSL6v62zQz9YYi0wu3PZ/xdkjA5zxFL6bRD90AoJJkncdh6CUz/kdwz
LHV1ZbfYwLJrvrjvI+uAX5F9Z+NJiAUnztiIhqvLDBdJorL+KEngSxIR216VoBqWMyyzHZYB+oPG
cU6aNSzWGJOtTucbWAfOsPSkxaKCLJm6kbrhp7eCAE3AWe3AWTZNArJv+a9FeJRv+mYhgPaTLAz1
AA44atStiXdugB2M+Oq7wrYLnmkAcdaqR5/LsG/X8CYhIJLtN4pDAWnuwOURZZlEpIcRe76RstFl
hPHl2EeCwaAR5z4dNj1FFTqimS474PU51eSJJGW4tTMzncfi6KNCzJ4zjrPv2h9bWy7BeyuGuPYM
FpsN/OfJPrRt/nYmhNBeCJVFRuHwyBmotPUQMqGoY6+HS7Mm9NrEKKDM8vj8/fisZy2N2wtzNYtP
lR66meJEUPQypXw6WcGtBpJGJX6972hz1qAPOfskzaag6RWYPnZsQaXM0uXhI9aB4xsvO3C7k4Po
DqxRRn9cyO2yv6RkXl1B4W4ksm5vFBA0e8FbKSXoFIGv2es0O1R8eISc6j9y0xeKbgYjfwvZ+q2W
fTWSvHqqZ5Gi/vaFVhuW2jZoidPKZoFo0fXFH0oR1WurjSB/ohwuZRPqVrr6fua3ETs+4XesL+9v
nNnQ/xxJhhqTmhE89ORl/KoJHN40pzSWCBygxtT0U8SgmifqvwGLPil5Ie3CQektsZHbRP0qBr0l
w2SoLzBMRvjAR7D2ApIMKYIQqFMqokXTn7Hz3pkdec8muANipg9AawDtshyqDSv7gwMltvTQ3ckB
l5vk6xwKmGe/GJxwgxbV8iNTx2CyKtN1Sf34Bsejfm7Pvlka8RwCNzApbmRetVvQ5UwwOHBiQwpC
gA9aESSCzQndIMTJDnf6ZLSKk6K1QW0gbjroJ/Fns30okZLlgFJa21hvm/AEb1QENpHeckwA/vl+
niAXj+z/WL6XoqcfuYp1sqxmfY2woaBXIAra2CH8Il3mm7/c263C3JFrDbFMpuoqjfVOEJx5q7wO
SMRQ1dXkbGWtu3IsLI7Uuy2imLF0B2RYJpRVnPOcPEj2KusBqEnHDxScMqPjhwK1GH/pkN5uLmye
ytjTwgzlQdHiEOdLJNpAuQ+f++aj9MMAnOQo8Be47wuqSofpPN0D2JVIZ5kcnUy/wzlIwCPIpdLE
rh7OBRyoemqa1fewyb2E2h7T2UhghY7koEGkwSCgd6/3YHaznI3jw0blDkKALIxpwQY3cG6/5aqi
95A+2lJop+0fJK3MZuwxosBrFtcAK3zkooqpPS95sAox3VrPmf1axreeSbupYra+SgrSBtu2Ym5c
5gtMCBFs0oIVEU5R4ddKsaNIXFVEH0GHx/edYxzsNK6lCX0FL2UbdiRiUI0vz2fVi49x7VtNJOhz
gPrLZKHskkDD1U+IeSLV8HKF78sWegkSpxrnShQ7nZzvuU0jt30inbPuDOJFMGpEUm0hXMnWZErx
qR/PD0vzBbdXFRusJfw1r8IiwbjZHmBqSxSxY8klgMW5hPgED1ONBq6xRQN811CjiG3wy0vxZEPF
hSa/uslSFLkWd7f0Qe/qdy9MVmbhvCO3+Aw/F1UfYs2fWfa9cOk25IQ5kmAwMJmPQRrknhLiNFHm
Pf6ePKJDyx+V5hnCDr74i4kxBkyeU5QaH+LO8Rz28NcWKqhXE7y17LGAZ3aK84tZ4tLWmMwunRng
OJxBeDnHr2P42MGwwkg7DZWGqwbfra/sO8HhWLtBjwYppR/gn/uSfLL3WTB6wvKBfxqCMsMZT4fS
YFqr1An7hCufq5yQrbkiruWUsGmlPZ1MhNR2WG0xh7JyLPC+Q2jAoPB5w4HSXLGRG7ABMQ5oTsmr
Z1awra1wBarIZ1GLFquDE6qa9DYyIRaOQwhveE9TBNMW+DmfOtdnaIZfPMLSzhONYx0cQ5ZjsGWA
ip7v1fMYl+qI23JTB6pyBrDcHopIx9wQJtYtbXd8yY+vq//Js8OaqejB6pp9O8wqGkaGS8CCRaKB
wFGK5E8bumDaoFgG+snxJwuB96/vdkM52AdIqpyl+x7ueckSabtzqrK8V3H0sTheD5FW4HCUjZzV
93tVEN1xjM49/nGxS7EHHUxCZiD2ymtkt/30kSgcZn00DoO24gk4eRSzoZlb/IE2h/7O17gHkel6
3Rn6vhXEaR0SD1Vhn312NmzJYTbJPWW6i81vbzmqq/EbSXLSpZ1V9+NHMk+Qa3NL6TndlNsDsMFI
u6clbsgORp7dJFlCr4zB93zpSto/kFQBxvUsiqZPVXmeYvFXK/7r2hvw3i5igQvQ6LG6uo63IJvL
x88ux0qYRpsFt6BzVDqXq/eUipWoegPuMxrh157IgcX4TtVjXPvWhPBcr+Q50hXHi9V/CUXh86FN
twgszcr7eepc1R368HbCGOEv5zCrih/XxZiT1zM9YszungO+1RFWtXKj/MjxkzYJUXAwWgM9sSYc
nxYqJA5E4iXgnP6YjJibHe5pWXzkrQGAoBJi+Yq4cxzw52c5Qx31Lb6WbEUmbaNtW2uvmnrmFEnx
LNDoAVAywnH4Z00JEGFsOk0eUYgxdkC5f0HCWJ2RNBWQuPqf7DgVNZuBer62PI1CwggAl4YYAahq
jHfGnxuCaF0Lj86Z7xVEIGgqX9v/8TLA0SoLe6/32pDpI09HwKribLzhYjIAC9X1Z9JHCDLeAdgb
BwPNnXWwH14pBR7nzwRb/xSS5b4FSIYC7lVv8Fr1OhVCTjKGA0zWVZ+C439SHAsV5nhMJLdtNrrU
jHqM3OACSJnBJEB/NGVDVS9/psgRUQHJlsUsJjcl1jnAksIXCSa1pnhSlBmyYUgZChehXdvhLwh+
TAYWsFyg3ys1c2DL8XkR9AFPDuIUvxj8EufTFqHTf3fzEedmtcBaNySjyzvqCL4eqHhI1fSaDm2L
sXyHWcFR+tJ3JykpiusFLFfnc2v5vLI6WktNNk+6WH7+hUODSc5ZYmglGjW1lkXiEbYYBTgXchDg
hhNPqJ5PVydzKTg4Aa2zJ2YWVgH9jylYnq1JyfUAqEEMn5mJteed5U7jJw9Z5cWzfrT9I9xBewPq
Hbd1cnj2od0+I+mvKTJbB+E2mZpcF2phoh0s3jX7IDp5bqJR2z8uMaIzqKgw8cuBZ0UE0hQN/Q4x
k5OZ3E8vmdNkNfsC/EX+d3p7k3emmgC2i0IawO2qXxaQTujQLqfNT+d89tLmlBrNMYDJsrsj45NT
4fo6fykr/bhLeSY2sbp8YLHU9/Sr+6idWGXHX0ZFu0atPzAyWKZIgDHrwhVlGqFv4qyNSzNqnqXp
4SEULbfDnqa+s9deB4dExcl1rdFSGtWbNWhyYQLu+62465iYUWRmVZKGl+U/i+bZyEtq1hnBduJ4
gL6T+WiRwr1xQOaBdPLfAnZcWmzctpvoIDZO0yg4SdiHbzU93Bj2chWNsvr1PeGdDmqnxcqFaQX3
R3STv94ZCuEmmYN253OdliTJFTDrjp1cLLP9V5E0K76sS+1BQBlYqWb1eTEO+KZ8ty2J63OVOKWI
OVidNHSL87+LWCg8r1ModydCAcMucpr8PerXoM97FXBTl2JTnR7fS8MXY8oFlpZwdHph0lCA0XON
8OWOTRTVeg9f2X95EGREYBDr7KVJLC5//tTmmB8b8O7LbM+XnBkq8qPduDljyBqwutbxncq49Jb5
1PcF4EjH5RRa98D7aFAnKTO6NNv28qFgUBz78JnznK9XgwNk/XTagPA65AB/lGFoIbdbs4HaSwdB
HpJtvc7HY816mxVG76/9hWqAWjvSfpg60rAV1rtzwC+wpV1cUzrHa3ivoU67M2BthpqAzxcdgQMw
baHTVsc9841XRYlj039A1yqjj2b3tC7TGwF/UzRAx7SQ33WeGv4M8pwGE0A9T9PV4Tw7tCI9meod
CYlZ12kcoza+tWF3TJ95GXV6OLVpunnBD2+paALg3HkZERPoaMKmoXZiv4a5JEWftHBjCOyZv0DQ
1ZiLYrxwLSmvv5X3mAOh4AwXZ/fJBuOwO79R0z+caZjrrsDKzdK5E1VKXJyRG5rnXbDYKKAjH8uS
2auf21GmUFCjPM/3BDAqUTJEzG+CmSA5LB+QXNcOHkkwRI+JDkUfnh3mL/91x+bJjKPNA+MnRvv6
pnVH7nLbrxdfCnymfXGtLptZbEtwVWWmxmFalFlWoUBbthup6AgoQy/F8jffGJRT7IPW877KpaMf
KXpF8KGrv9nzope2CXwqeE0iTJmXFPReJTafEoD4Nx1WBB28VGQ4aSgdDzEAnKTL1Ac50dPggEZm
WdK4KB7WXwIEklZVSvnkbjIFwBGyj4AYQpYZw/XfzVSB0hBgmTYuq4PU4wjOibMi6EO/NMmVgxIS
kAAAT0YTvs7JYMdyaqIDerxE9BsnLA0nyPd5S5rIofF6QIr6IDhevQx/TZ6oNUuAO6KQRCa87FCc
EXYH/3UJIKnnQiDllEmDZiwLz9ICEtdQBElojUixpFkgh1UdP2geCD9hiNRblJEf8LqnXXvEQw1h
TWuD9iBT6KNXzXhAZNU1yvLsWcstzj2luU9Am1ulF7jTBNoRhzxc8OmyLs1aqxIR4Ivu5cAaEpXr
m4fAbEL20oSFD8jhO7lnFXAzWS1qx6P26bc1EuuV6RyRIZX16txsidHZx+eBqe6bESMuuapEQTY8
cCAl53pyQLubpHHf2EgHcuDb80aGZX+NgzB0n8RolKujTSE/yFLKfyJwSVCcg71WA6/h07m0vXIM
CjzZtSh0SeWykKjzR4kHrdfRyYD4NaZBR7IXJ+g3AqVogCtAPqYyKVjorMW2tehgdfxSjR3Lm2F5
7Lirt2EYiii2P0dbl7weT4GUV0IU3Rks9SHkRLW+RG67maDwrBizEndzbFt883hUWggUs9nUL7XN
is2QtG+xZC0SUh7RePPAGzXvJFoNp6PuBImLbk9HGlBspp9HF30EcccI8G0mbsLMuTzH3IAkX6Ze
JEXuCnr0ZpwwwVl0POVCct7Bq0PrZBrWIzFaHcOsG7N/AfjwDyN8rnFqfUXZs/9prQlUHXVNjs5A
itDz78G7/ouVPJ+AckO81SnC9gUqf2dGGBDf3liPI8paszv6q8LvftpoUYwysrjsy3KB5Lr7BMim
pdQ/27L3ExiLzesBD0sJwvhc3PsFcMZey/ZrQmAwu7oJE9dGgt3YGylvv5GNikQw2yET1+CUXGT2
EksmnMiqK86BoGgybFgnodusKR9Y2shhPo4sG6mdsuyid8KF1WTSttvrpG7MrB0ZLXeldfVJINt+
W2ipeXKmyp8P4RQrYFf7zMPny9FCym1bokuAqzErTeRQ4QtkfJ6QKmbke/RnBXrbk1w0p203ySS5
o8gKsE1sbAPICWzmTh7VAUhNS9MtFlHIrCNAtQ6GW+aCZSJ7rxH2VXl1Lm2Vf0m43E9unciiSZdX
KdMTGm7b+Lw3AMzVlLZBWbOFglacWrAtPzAfd4rHOpExMHScrKM1l8LlpvtbyopvtqcHdL/AuQGz
mZAv+9I7TvpSc8YNEi+FVI4taJWI3vZPA6nY6r7orrvKVMxQooWarxLgGDslQ1KSBess0/pGP/sM
M9S0LWiP8mHARvcYNNGW3umYg8WXuCwnIXmE6dGiJAiWaK8eyJxkkbXZ/36QLxW1uo42MhuL/FRQ
t8jFsT1Jx+cT6DpLjykXarQD5ZSYIDfuixCWWsu8GYE8OYiWI6zy8N8lfTA+cngBRv4bM5m0MnDa
mq3dWxhx1hHY3GTUvXidurUn0+RxQVA/b17nlUCoTYCJiLamVFzFG3ClZfOP/mYcUpkWpYlLybgy
v8IZXK3fFKFrYbF4ZtFkudv16Ex1FqJpllAHxcatVXJZQc8qNWhglwlYTdxtjf6BqK/a0Q4DiZ3t
xrK2pyrGzIvqz9yUJIFoVd++iqYRX1px42mYGLGIuKELJRY2gM8QEbPDOAA68vpWt94N2hVxcS3c
EXGzLAqHecUUDBJqKIOrsub5r/44TVo927zB/vLeAGy+YINxAtoW3U3CQnE8KR6duJpekPIKo0Lg
UBUFr3be9Sx93Od29oFizhcpLedIvOIBMSENSHu5zEThFyHps14QbauztRG//TghrYYEEccPt+s5
TVT19DFMIO3PUaSjxd1VblxpCd3ydt3LiWlJxTsI6pkv9StMnHnHPTy11RmCeHySZVI+5Zgx6lyx
S/57nL0dl+wkVjVJGo6v8FE9uWMsd4tdS3CQ6BQiLXbRb7uXMSMt5wxHSL0QDW36cpC9GvjOQygS
cMTaYYarTcGhdjxaUtwAvBWZYKpmN4oX6W/71nGpTbO+x8J6Ne4sPl3hSguIRHhY7Nw14a9fp2+l
reRA+a55pSky+f3aJX9bIIz4CcRRaYbdlHo2CWwshH1H5SwrIA4Yqu1VfZfRmt2zo3wnAodFgFoh
E4kqqmrOk0QsP6w2rG6SHdflfDdN+jQ6PgXiX+3Uw6/5Pt61X92PDPW06iUe7OSIUtceQrnqcfNU
O/jvv/RBWEcj6Sx34acylcIxE2W5caa5VAShR7h15RBV25QnhG8Vwss9DYz4oVfHazeIHhgQRQFV
ANLvtQk0tNy5EkDMI57GzE+PjCJprtPkQuCGYv8voEwvigbkOhhriOWrH3lfnXw8EB6YCloFOQsZ
/fl0mw+MR8S6O8+SkiA+Ap6eqzTmo36Wg0lbTyRvLSHM+X1UURmcbIiCJYMgXbhcdqlQsEAFTVWH
1sGVqHO79Lhx5Bj6MEY65a9UQBJJltttpojY3tH22JX3HBrcCCcSDJ3R2yOSgxNUdk4Ke8oAd7vl
wceMJiR3mqYcS1NE9NTJ/N7aFgPzGtoJcn2/y8t4hfVPRXMfW5wXOsZnia6gYFSu7n0eM1WTLyoz
7ibOBVQVoFp2FLsE9mjukRQzgaBfvy5frtIg0oD//wXS6gontpdROpYuX7X0cO7F7bp070/zhG9C
qxGnWvTQwO/5ix1GqHT/UcpdVnuqpwV6tKqvQYLW/bnmybRCo7wp2uImG4fcZNafzoeYwpSpQAQC
bSizI6SsGpda7QpnmmehqB9xO0XIYl9nVDTVyWYlfeWyYRWWUwS+idvNqb60Kj8TXV2BTIJm7GSi
8fdGh7e0gzzvxqdb/5khSgExzCGpyjgdvFdygU/CdJOeEjLk3pVij0FrofTimUb9HLkKqWc75pbE
DEPym03RgzS7WUdO+4CulmSlaxtwDssV9KIpRVYvI5j0GleESIo9E3GpegIyx7QTiBKbdeWJfHSe
u5evUcOmWEPN85lU4ZIqgEwO9065IYTAR0M6nSSXdWdRtb7GIW9/QsG1/hLIQu7qyhL5j9Z6EHas
F2EqOx220l/rHKulL+dH0CvzYM73SdkXe5dBNbyvvlma4xWvRM99vYXDbZ28yFXkGsiK9ez/uSg4
240TdrcvZTbNATw32RupdBH9jd5If+Y9hGbboVDu/4cRs0qm/iF9WV8xot/Apq3u09c2p5cR1JFf
WE27h5u7AjrKAdQt/OaL+mzvKS6wF02HD0BB820RcJQFmopedqZB13u0jEj8dFf6o7WGP3t/GhTn
p9b+UFYLbi48tjuFh62gVKYl5KbpQo5EDf7yceWyfsOKQcKMuAZcFGwFd4a0j0RfBkSetqEdjL4Z
KAG2PPHFFcDjQqo6mZikLJsSxbuOHD8HUsAVHB7O2d3C8O7NcKqp9F6Nk4jM+Slq08/Ng/kxJ93v
lWG708pEDjmb7+1NkztVY4/B6B1qToP/P82p84XNjG+0Nn+LwLC/i36TVlF9YEeOwyHg1xk/e11L
oGoQJI4LCvXjXftOT0ONaEjVrzJmdESSCSjLpaqQDk0JTCmr/+KiBduVnhbzR9onZugKW9UBmIH1
AdM9ieQLGGq3n9Ewy3ZmuFB2YF/jT0TFXhc/DKefjnxwkNjSg1gKXXrYMEx5Fd/BxwWhpdkjiMqc
BW8dbgKz35M9trf5eS5cXf5bqT9jGmarYjcSFgarr/Pk79l2KDAtLDMj1J6kQFtf8p5iQDE/+jAm
iPcoAE/bwZVdJk1k/3XOJyS6jB560WIQFGtuOPFcFqJQcvOtYBByBSFnNlsXPqdHkyfOwIehvetz
COkliEMhQkKJ0AdbOVMA4QLz0V1dqhhTE7rVWm9tm4qxUJO5b03qBb330djowoUNG5pkjsgCr0CA
Eczd0ZdZQQEtlwGFczWii22M0xnzAplcyrMwwiI9YirrZ3fGW8VhoLOqJjvgznX4LjfGecHUDyGP
CEuscdc2dCK/ucG0B/BAydrhMmRnHAZnFkLJds1VAlblwfDu4GIyldSgSrq/lCkfJKZay8vNeBB+
yRCxGoyF+yokiSAPGF3BV6uDi6syUneuvWEU6sUu+XX32QteDa8l1QmJBjJ5AsBs8/zyToKwiu1U
qaLKfgoAiqklPXNRJAZfV1cKon68HLFTcUgFf7Ih/SX2LQRjlmeQhQb5RQa7u/tetrpQ097g+5LQ
IP9QnrSX/heVIink5fZFXY1DyOk6c2SttANHyaQd1uwYmrfHF5ZOWd7OzzEk5+8OLjB3oFLfTOP2
rY0sjQZlcp/CyosyDgtNg9C+hawZXWC41jwFAlXPi2Y93Gi0iwx0rRW5N6ljLBz4lhy4hBCBHbqV
uuPwWpaNEpOBW8roeHjkQGUbnJ09CJrckZcmxXFcP0eWPDE8RaHVKuSbez364wT7319soZ4gHJ20
lwgxY+vR+fm2yOs5A8Q7l1OTbHi/EX8CVXMsbglZEb/bWOJuSnIMO4bUfztCPKEsChOgE+jepw+r
aqvjdkIp/TbasybA9F924xprLEE9R+wtpN8DgnIpc5IKgKciSONNsqkfgE+fTFhvPFj3f0R56+VN
R6TqdxN5KAVZNxEOkg1CCdmja7u1VpzyQ3vZthVRjv9QbDdw5FDY/Yu3/gY2+owXZiaXwdvZ4LdN
brWOG9/X8rN1jIxth3wHISGL2pzfbcLr9OxPquMnt71U9Er/qljNSmpLJQydebSiCuJrYJMXei3u
P0O1/f/mXbj5WEPXGWwgJAqRfayEduZqyuMaD/nez3hW3Ax5zKxJ+NLqMqkTx5tg76HybqYE4Wpy
sP9ZJTBjeWXRMXQjmEBCmwcYiWcL9+yPjX4GVJNDblcGbgqnEj+yXtvAT276VHRC7TytcbfD3Z+j
2YC1SkTRS9lT3p4heMiuLHcT8N6uJOw5RNwpNZgJU5vayUJhWM4xadmSCxvla1QPd7Jzcn3PF+a4
5Nb4YTSbIG1JjSNpCOE8K4/U7IYkmFMwp7Nl2/42ZgMUT/mLRFkCtkSqWjg+3AmIRwwWO4j06x70
+2Q79csXDIkk6axpNm7WlEIxEdVhJFyD20XjvFqgaJDbTtUDRVC0GCpMAd2mtqIZ/JeB8L/SFTSr
KU6zYdHxKR/cYWKFS85P6WKvTfvO8ExbNqL6PE82KBUT1h3TMRQo4ZJvUiVa9OibfMwK2bm7XNKY
R3tSvdlKtbx2ekDspd+PgbQbwOX5ACeoiWv8NNvc70AGlYjw0ApP1rvd/BnzRuOVYZPjxpp0+j18
oMOlUw0X8VVXpbvKZQwEpcmTVQhDxwUZnumxkj5lGZhdKKJN4wtIysFE5KN2EqqnB4tMh8Xaqo3t
QzuEPxxHld4EG3/SXALtsJYtAijmF2hR75K1qgSvj/8MdQa2qcwEQG+EG64wjUyzRocKCLALfdbS
RUli2RFTrnqAOMuTXN9CHTB/sk2x8NXQJ9m3Y5TJWoCmGulJHdzIWU8txfR64CBEw3tvQn6YfiA1
JdoygfAd1gfwTV5pGHC0TO2O3bCu+TR8YE7UpLrnCWWXv+oLDUDDaFnjiFf3NC6K9008kM4lPJ2D
smyMhIyWsvj3Gecl95l/vzI7ddIE7yCtKSzNO0FMCm+t7zzkIBVMxZLp7WY0KY3AxeMXbP3j60AC
9BN+BjLC6M0KL9LPUgcu6v1KrOzdd0Uu8kzukik464x5RcePTLE6FDJhMplMVwAM2ITBtEYG4Ia9
iGGdjl8GYK1bSiWZbpYCA9YpJ1AFsgDw5d/ZUrJLnseJ3glTRfhlxdXF/PVUDvYSf5TAgqAh8l3r
0Ggm6kxIzFJL+GdVoUdKu2Zp2BIGdfbd2oYaem1z0Z9KRPjTznHorm/HBVwYnIRPVg2KBuUu3Ih+
vofqMeMQJ5unhX8YZcFsSkQPX0aWA6EnRDTGZHMyE6F4jToPM9jhbCNVyqVesA3l8XN7PSecrDaI
pfUjrShVlGKYISdvbo541MILJcJahrt0M/NUdfKYe5r6fGg292MTCC4kfejSM0XBDp9UkbCfkV6y
wPI8SiXeD98pugVY4GcF+FFzx3/5Ri1+B+laxBwdbrqfuCjU3bmnU3upsP9K+AKz8Woldv7p1CJ/
obXiP+KoydseUhU27d40OT2/hqS0xkRYuZ3lvUuP09TQYcthmvPhRBL0491CJ2FYfx/ogdkjZW48
DiwQS2FBijBYIRakE+z6samMhRLDenxMuTUTsbBbVxP8de5Gn9CTSR9FeL6erwOpTsM6EdzB5FLz
9RCPiPG3iaYEKwxp8PYCA0oHesjiRI+ilkpe4tESU4e3qZmyoewXEllnr1uNHZB7TLyCGfrBznbj
+fKC47uqqTZlQ34KMeqCn38YFjVHi9IM2qCD0XFOhyBgLaSGHZcecFvaKjB9qJ7ORXa6kfW1LWKT
jSx3i4qKsKnUd7PjaEdE4FklbDsFEbVpehR+M3e9nR4BBtSZ6NOHb+EmnUinxDF0V97CT1NjBhom
eWvdGlaThrAgJyWNLQEyktmcz+6dvtOLMhAX04pWjE4k1F1XhHzm1yXJ7Wmm2xbn2OwfpcE4RL5k
NTUFDBX78/uB9wjGFs+n2RRvY63DPj9tOywlXkgQso3KOPyLqszLs15JWE2nyccwDmnuA2yKvCVY
60qtXPiY83r9NlA8/0i9AHwbiGxRaMf+HcHXpSDLUC4CdeHjXorLvxPzKI2+B53CqdAKakmuXWYd
76NiJnxygCFKnRAjYLjII7F4QldQRsaFHjmg6PB3lpvP9px8u+5bPjNjLMCow0dBlzLgWtSd+aDE
qMAotNO1/OlBegH+6aAkjzKH8FCFhazlONoLrIiVsoR/9zRWT18VolSr1485+3s2EQirfKwRsLab
7pJ8asXKQy4xEVhlNJr/ybKVYVt6gKh86XxCrG9ap2rTXyZIh0HtKduF15xVc1DWNprctKNstJJB
R4UB0/Y/hzU7y+eCAhWhJ4SlaxeOl67MkDAwc/GVZ1kFCXSCRUdJRQJGbcq3yNwd+RuFglrcS194
kbfFMj8Z1eqQon3293ge18r4nEVHpnVOJ0l7LzNm5zQiERFsvmA5LSq5OjkgBkww3LvNtnVdiAjv
+mKRUhLt07gXYh6ursVfXDMM0bS3EmjWPwu8waL5TsiSP3SAsVAI/qhGQ4IDnHP0obA9iotWEiTG
4BOHji1Pj4BSKkjfC9jCcEjfF8ZSocf37fw7VMKhJtKstDsQTa1k6bbJGSP3g18rzm2TXlHWaVVB
hUDGjUJ94xXaZ5WHQsGntPRHZcAKZVoeHmJd7H6UdU0zJDGW7oxbVVqEHdAY6AwCdm1S+MVcXveH
dvnet0eMMX3r7a98nsq1g1VDvGRVXwy8eWDUA5AdKSoi1BsKS4bAqejIDvG8Q7g9hEQgLSqnlC45
gVB9bmweS7yRG8uuVCiw/+2GSAoNgxjRzXKVIV2WllTFrh9x7PzumbjkeDMo80qK9lJSeHDMJJad
JFNvn6WwhwKoLcEjvyY7idGm4MpjNQ0aineVIv5rzTiSCysMeox4ExJ8sk6+uAiSTaFjEH6LzL3P
YmS20B/zCE7U5KFA+QJtTztQPO2t5yWnHe76UDM5Sk/ydlZbma6LjPC5BVpuleZxb7RCbfgJWxcQ
0FHiwH24EOjPku4d7VSDhyBO+892ycbrbLWr28JPV+oI+Z2ETlZxSOWaVkgke1n7j/n8ZKdN2IuA
x6PqlAnbgeHU/2lXuWvcVPg/8rCTSB9W0tkr3H7k9B5JdV56JSN+xE4Ovabg+yHOyRV6FT3DwY9S
iGY4abVTA+J23xMtIpfJVwbjh4HdWvXMrdYU/09mn5StswUTRlOsuU4sbMLwzK3V1xmnXJnytodk
cF0adUhTJfJtZIYdMJwMhPHDd2PKV+cdtqSpqjtYX0HQxtDqGD1HLyOcHaH0Zvm3PhKd+rpizpYx
+sJHOuZVLSb7X4ZEdIMU9Bszhnac/MAWVb3wOtWuzbnMVMG85q4u4wVsq/6v++hNwvE/1lDibC9N
InCVfRCXZ5RsellRaIbtQ7coQwb5Nz0Jkq6PSX4Jfn1/Rerbi66J+7xhHXAVOwc7Lhmq+APWrxGA
y32KJNgJ3UXId6UC7zghmWLh2MWYXGlNiGTOR+10uLL3Dk2m9d0alOPX44iy7Aykz+P6jh8Ht8v6
SOiQ5kcLEhvQVOCu7S/iS0buBKNrDuN6A4WnMs54kBj30nT3os9HKVaMDLv+sF/CvhO47KTcacgZ
xDjNO89wuAHDhcLZFfuSySjysG4GexNIFPZnfsbBIu02oKGATilciC8VskdY+90EgKgQNKlGwWZC
whym7tPdqGEWWTEBrl4WVejYtQS6CVmStEM1LWQQ3OPbWkl4FZnD81lMJjIHKvMiv6Cm3xRg4ij9
XSb61SW8A6BMzEljcqRakpOaZlfVJNhbAHIFszo7Jhk1u2AU5jJTjsuJGYm8uSyqTGSaB+0Hfczw
ruouKkN+DN0uurAOYyk2lzB+HU8KSxtLTjcwese2r7UMf9OWzQwfRPFFhkOxoTvzRfnm+NWtLgwx
8qIbDiXaoVbCLgkn4+u/Yt4P2LpUPd6cK+0CE9fO5Xjfu8pK6A8doKcidoVQW5FC7gwMhKFrjxfy
esI0gcTZzNSLwU7dixD+moDirUlS9/Jv5KGTbwJt1kiPqMyaYfHMz6ZeNLXsYRvCLYGBp8s1NHKb
gygFhIgzMNvEioCSjnebUEqXO44vsJVEQiE24WIAFlTuDQfHpIpGGC25CKIDtCVPYRpL3KTkfZ/L
GT0qf6LTTBmnPEP9lOOW6YuBPff9GNVsxoHdnin2ro4YHmLmEvrbROhe1YZ0tBin2barAtw4GaoX
wY1lODcDU6Nnal9FEKbkVpoRB7pekxN4Y4AnBX8s7MMBQJSx5RKQ6SREra3VbBBWdog0nI3oIPCI
ZcfTVGlioivvwqfKVQLTNKFFveMlCvRvvUP+85ZFL8ZCGbKTNtqrgaF/BBVWTelqO+FjxYLEqIV1
AWRcU/y2EqbKyFwLn9k7pxjJSU4exTgSj/vt2b02c53gJ6Wg08XvriZhT2+0LIoWUh8cuE04ug/7
Wv6Lj89/mniMXogaWr5fsvLb36j6bmTw1p5v+C8jIqyjTLA1wgG1b3z+Iz/f8Pvk4L3w237Dgnde
FjpkX3JS/XH/oynJzL6UTcj9KYMU6Wh7Jk+xR9/7EJY889+86ZMZJHK3Ks9EnpeWYEWPmAY09tai
8fWdkV7NmGIwokZ9ixnpldLFVSxY1yDXJsHEMqhK8dHdB/ORelKqKk3HBicEjE6YMkbCL47LSDBL
iU6rUGVIfU33/B31VbdKtdJDHsPTrE37x+jGbw6obMcqLtI1ZcOf//IcwDkgie+JouM+EnkZDOlw
b1K2GoH34JLj5w2wvUlfsqRGzg8CwqVpyaOXYqx0BB8tNQ9+x30VQugc3J7mpzdhxugbMhqALwid
YXRAWvwaGsLlYh6c9qX/owDiyH4p4AWZzmHJ4CIh1HilFruwTZhN+ubPCT7frVpMMK7Cr6qA+xl1
Zq/5a2D8deIQJmchpRC5O1kQMZc3vAVkqpqZbh24JtrxCRufOJ/7yAYbAuBxTM4ZRpdAIIn13aBH
4rsQrcMLYRLp2et8+JeJ6DUZLohxHXToH/YVRyt566SNE4XHqQzfhFh7fax1CSkyRr3+jzb2O6ke
U6zrvoa5facURKDmMCFLb91XPYWxt6L+JRv2K0CjwPUkSQ3b7jpSt8LzbNwHvoeY3TyFI+l4Xe09
uT6QI/6OyRYCbBX+B/zy83ojxbdG/7zjchOs7kQiE/yb6Q0qb8goWpjlDMUbAwm964RBwgzDLRFJ
8rF64xqKmvpJO4J37ZKfT45NUUztLigbc/x+/EINj0e5RDhkoXRkeugqYtsonMW0HcNoRYcM3pyu
/1JPW4uB3FNULnW8I7tDvNT0xVXT+wGu6t0RbRF1PDS0SOP3cO7205+Gh1vDsrrtWnZRl8zGHaTt
u+tfiqLtDdQku/gs/POs/QYInFpBgtbjzxqHeHew5Eaf3NrYRSGE2sFD0qT0pHwHDq4o4OUpJZTQ
LIBdnv92Co/iNBrSdliIL9dcQh0RY1QOTTiGuY50wo3XXhELhmzvjjSD5mkbfAyfr06OWyjtx11I
24/qUOW8y8u6VSJcVH1Tf8fJTwRsostLrjBsjASD1PKo9pu4XQiold0vHbQ5kxNmyj0dGQg/loG+
X1qnZs8+BfH/t4J/foY7ahnbKuk+RH9vufZusbh9uGecXQ1yAhE5gdB5Q7TY23tc+WDiGLeaAv84
I5DGTQQ1aDooxt1iiqiAZN/Qt/ltHad1a5u4Gx8oF25xa/V7/Ywtc/Mi/tKG9I+ZkIdu+zjkdFwV
QpVY/t4jrzbcdKDY8qWoBIACdUMi2uecUKdjfGTZi5asVjZKdP3pmWGabCaMDeXwlGHxV+eoCycO
u+FAKTB/ON995ap1QWeI/5uWyyyUO5HNtyp/1ZJFjZAOPM3E1CcUOAVain+5iPU0+UAty0yCs0dX
8vq/SxDlxndeAchvF5sJE6z2/MTg7jQ2VRWcY6GJSvYj8hOX+WA2+AIYq0o0/MjjhZQpj44L0RtL
Jdhxyx7YNngYfH3GtKkNQUqK1jJyy0qjoPU57FACimReRZZdqZ9dqVx2L6RgaS+xeK2eyP8BSGsN
MJ+fWekTBxXzbSNRL37rFhmaWKi/HVYKBrNBAKI/9rhVO7wBHFqFuKUpQxEdwnrnZK6+B4zubOTv
ZAoHKc1sRsAef3C3W8M4f0XZefhdt7hpcsW61TNRx/hMDy8AvZ6BLjX49ZVBQsHF++FG/sS3g4av
YQv3govY+Yc/NkjgRwThwtayyBge9jhnwHQnEINONcMIwUEPJl+cSdQtlT+tEUKouC7/6M79+10q
J2sL8qYly9O3eds+eviOmVygD07xZOLi8rWNcQpeG1aipe9GKGAkaUpyO3bOCS1BXzdmwv2vZ50E
rhH9wt4Uo8a4UmTxwLKFtTAYX4cANBdJGYmmI5Mtc1jFDKsgi7kY9sbzx9Dz0SEVpEGyYXjykPEQ
l4V78DOkRVaF/ZSQQuY4PXIUq3YhKq3YWBKYm56EYG5Cf5I0HloMHazB62FNKZZb6QhuC5n/z2G2
nLSOg63XdsFWzM7qaDGJ6XqEXgSfibKuMX72Vjt8VA2FQSRd49LsUNFt+rHVENAHkwSOjC6pmpQO
Aqt6BTJ07UfOTcWnAwDVq3rYJtVmNQMjmpjgHIcltMJ9Ff3ihFQPoGq10jW8iCJzIXXTLx8EQHL8
Dn8PaBZ9oquR/Z1a39jmtzkqPvTxS3XD3/nhvxw9Hxw+4WLwB8U+HQYJN6vdXwzJiKdp94BXktBI
f2xyXu8pT2Oy3x8OqG4EmCxtpgAt63p3S7XPpBpS9RCoAK0GJYibAOALNDWTNxTmDH/wiiHKSOcR
HBfbEIk5xAiUW89U+uIHWHJdeQVC09bkRzPs+6GesadsO2WcQCmnD1TfyGcdawPeAFb+/HUVAejZ
maL9qCdsARDn86oNEX078nLerC5HZEFoACMatIGUvsuWX4Aym+4Tf/l3THFop1yu+Pb+d0qDMxej
8/wkwyNM665v1cgFNeA2qgP/zxnsXKOIO/dzadyWq7mNID0nxAZIhGmQnBzYX25QguTBFEsGtY87
W5LBNq8ZiDzk3DhMUtsGtgv7lkSv6jz7JG/aG/Aulrv1OaG1G1o8SrlC0dU4sJnkwh/2a8Hu96LJ
93MdYGz0DaY0io4i8bjGF/W5ZQ/YGRZJTcv5zk+yw8465b/wy09H6BDD1jN8G88YHYY2zvJpnVZV
vZY/m3y3tgTGTrY5rD/TGp2dy92QOYHmFrPFJ/3Y5NbDoPthXtAtChFMW0uZ7fMvKWd4YFd1udvE
NUiy1Ss2yugY1IRI2fpD47blbS9CLb13ukBEmXlIjkpkZYnL9JMGaORK7xOv5BPVmHhX5SvvM66y
2gsLck1XAn/baniaddKRtmfwCY487owXwO7dmjpHc7FOvH8dXZDKcQYocQMDvTDj20Y9JVzOCfOJ
mnu2gYYZi98MAOvR07WQ3B8Q6DXegrPrG7P60h2RUao7bRdoJlXebbrPqFdxZyLycOaiI7yj7w9o
FF5RNALjl93Y5IdpkUXhEwTTHnwH4F2bLBFqntV5XKK1tIH1dhUzSgHn1Au59kb99TbOG9vU4bIz
r9rBOkwce3BaGtsRjLqNv07o6WqHVUSybszrnGIIkO1mD39geWpWtFq50YOrawI5Y5fIXxUKpUlj
z5Ciq0ckUiGLUZb2oHm7pSA6X3mvg2q9+3zszVzWwmYf71sU1ZJDIkJs9TJS/P++KEhO4qvck8kv
qzBXNg9YtpM8GHzNI1w20H1vHs3zVbWIAHwX9DhGAMzhhoxF97NfTrBUIloJz/ceH4mGfQO9xaAO
nWpefET8zj2NNyTvzXyMdumVY4Jva/vSUYxbyiZCb+R/RElclq+ssDHt+QRYMUNro0zb1xvZUQDx
6RxmUmwPnM3CU9mAT8CtNiZDHC6FEmfsNZZXym3EkUdZKk3aXEMoYy8wL3w9YlwkH7DurxKRMNaY
eXU/e7dyTFR3zJTE+M7NxjStfZYQRW4cuu4EYeVomcCCtVW+ZHjbBX1TA60nNAcbPq68ffIcB64J
bnY8V0HOSIyXgNfbQ6TN05cFSGEp1rW1TwEL4QOsVwQuoMR3CZz/s2wnB6eMvCrNH/3Ot37ZZi/K
b5Rzv614M+4oBmlgydo1mf6xX+sT6JdQ5luLh9sO0Y5kbIJYANkNbHlJwmGWnilqiJNIY0WiW9xG
aPQSTP02OWWHtgA9d18ATK1/JRSTzvR+B9pZ4VI1CZws93Ob173xhw/qRNN/JzT9X3I+4uLlRKIY
UnPBD9chUiSYcpveN3ZNaxkNauuHYTuCiRoWddykieaCkSm8lyP2r/7dKxMxX6DcGFHbVHpxTwwv
jGkZQ9A9+mxhVA0ZMwB9wcL3u6S6R+B6RfAOCln6nyKUgIX6pTgyIE3dUuXYk2gzCx6WNcAVCi7e
24Wf1mFM2ORkei2KEZv5yrllO2tPSJD1Pbc2tdp2hySuMHA669pTiYuD7V6HCYaQrubgg3smRNxn
U60B9LZX8XCJHtum7QeGVw5ULZLnLBtJdxP++GI+IxWaLUQNd0QBwt85jtLyAv+4EfwTHyi15y7M
AgQsejF/ebD0jCvfCqvgI9kt2Fm2xrDRfD3Q4hB8AJptLnrLz0TbGC7cMMdSJZkMBWHAr0cDGXS9
/V0tbhOJL3+xAk5q2qx6dQDafl1hwhR98giirom5v6dxA/2ycQB++X+hu7OxxFxMnyXv8KZlCnuc
hStRzBCS/mE+uQj8G8Ns04247AFGBrizXPvGpqfzognslRaBi0rpTLOEYRdAuI9+TadYjPAJG+wE
Zp9cLMepjx93MUA/ovZ01WiPEjt+ELgIFmp+cXj07FDspGH5Bn0QsW6ZQe7OkMXUSWOPc+WWW8KF
v/HQs+p8y7ak9aszalCqJKjoKSpmTKBCPCz/Mi/I2ITpPdwDE2har+cWexlpi0fSwT5MpG9FOt0o
y2oUU6GjoCMD5Y9GwM5dn8wVSEs4NqIAmWwBvCEuxRJX9qwjGzud5BZSPRTsmWqw4xGkmJ4jjGbk
J82OHl2PYniUIIgT2G0vpvqHFPNIi0VYIgDWQ+Yiz3Ejoq8qh9liL2+INH41vqkHR7kyDViy7njg
6Q7P92TJ00yQgivTAbXQ3n2CsRtt1A149DKBuRn8TyvOPMY3a/PLZc2VqBqL3/f3sowNCECkppAy
fEHEBa110mexo0VJDZOp5/CjRkjUNrLqxSqwBPJaeS3z5UxD8xlCd+HBkNbriuL7zvegfjJj9CvI
tdjjcqwcge3gZq0FasUYfUSV3ljwG91Jg90xUI0TbnnB92OyakE2CYQfx/FLrVW5XaDa2hDgy2tF
itaU5HdRhH3Erv4QUAqhsDKU4xHbP8PZHdmIQJKRKzdzU9ooR+ZBeSFoY2diaH+3kPOIT6mIQUIo
EhBtT77qfy+EsdXVG7qmkKrLx1AS0ALZS0Y25bj/VO9R0v4ReAUhPNkKNE6Py8HGqmj2gNxQpKNy
GtUoMn3DDSQ1hRyUFVvXThxbTotvROLImuTo6GQFGFT97v5QhllYop7UKVO3Uc7fZE81wD4B04Pj
IXU/gT6T+TrmsnbEZeixM5a1prBnqr9drf55Py8FjvgRnvD983yXOiLajeknsQG9leytLJ3qyrBH
g0S1D4exF+NroQVw6xDtu+stlcmR8sb9u2yH23gSNpmvExblt7Qg1BZI4Zfuuk+cNCDMWsm+fof8
fjmH6qgj7jx6pZjiJRXymL0FccvOpl4T0zJekkkBEdm2SCFCrOyThzkR6hNftuf/ZR54rIHrOdEv
ogyuoNIvkGSTYx0LSVu3OK5hRtg2zbYT+USLud2HZkXafg1LUe1ExCSFsYgPBbNRiAh6MkrXcq7o
5XYwa+8FERB83sGqe9aaFrNcDKOgMIxjjia0IYcD9kZfXBhqpOEmMJ98cjXu/crWthKNbZpAKE4n
fQLJGCCUJ3j2WYJSHeBy7C9ukOUpQgLeyLtKlsGnYVRom3AC2oAL1F2RI3XkXbQmokQSray0NFin
pzlbESjeoN1UU+MekUIAPRvuXXVuBPs6LLG+2Aej+HFk4O23zzHUJiOulBXl4sT1g+s3FFCwXew+
MB0XitxvVg58CkPDhSCZc7rJgaEMhrjFw0H7kTUMN3duyior00l/PMAOylEjq3PLY+aAXXYCZ2zc
fVSBtRveqRKESx8K5B9Z3n90QCK2JJjQ/Ak6vy9zYI4qePAapuVSpQL6gLHxe51Mmk2Z8ZnKFH1/
v/X4PmZrJiRTv3hOH6nULy6qqr8GCgHm9TSICjTehxNxlStUIcLz4pUcJ7HQavj0SSra7HYr/Wrp
vS8momG5IiMIQdpR9NjSfSMNxkCd6L4AOfrXi6sqGm39a/0sZ/nr19FDdBTRLhEhaxGscU/tyBZU
74YJYCFYoK0PWQ1imCy9YxOP9jYkBKTvMMzyqUdhGwnHDOfWByF7ZH1fFqDiTzfiHoW7twjvPyv+
Hmxow41SApv+29MmAZ//c7rqMzOZtWy3/Pt09UUQOQioO7TI8mc9va394q2/hct0LAA8jYgXgXPD
R/09ViJQORgk5/c9iosCM1JfNwUnSrNXX50ADWVwD6VNwE2X5TwrerjZ8duzxNHdpuJ9+GJRshyz
Y1ok4Vpw3p/H762d75ryDmWQziHnuPYSjzT1jLXJq5bln7R7i2THgqrBZZLsq8alPq1NPHHDZ6pv
HjLbRvwcSctdQBPw7iE2CWg03rzT5GE37ArIirdb/2fLGcstYlLeIQkK3e+S7mnADHWD304i5Klf
9Va+EXPnO584IFRmJWBEbOYmgVgUQ8TEO7edXtFLhze8hs4IrFRqj/eZeTyRjTP7vQ3fOYKroNih
MsHDd5UUVFnARszeodtPHY2kqaxJ59bwVO8h6x7JFCwDE2E5xf7jEr9ierMXybpnCpI4TcQXzL5m
IA3ba5+Fm5Xd5iLqhMiQdZWXcz5/tFXX3m45JG6J3H3fqO4hM3V6eV5xae6QbWtoSgN2MQ5gQ/3r
AOer0Y6dFumXiSR/A3gpJ1kN0xDIa8jVOtnObWzWAwr/x/IYPsz0sqscmykzyAwDoSV9KN7hXNuN
vLjR0KtP7zrZym/uqqJFeJ1rf5e437wc7Kml4JCl4Ld3ecNOr8rm2nrXQaRWax8x/Tr7WgJ0XOvZ
+weeYtx/Pwvzu652KqtFM0xm+8yTPelvGdw1vEQ48zWOWam+uq5nBCJjP0VURxSfGM/2V+HBmDVx
KC2lDtTHe440CAN/s1/MAMArRBcQvYYC1py4qTB/R1ETvq+aqQCVV6P9WvWjB+F7GJj1+/zvaszj
qjK54oohnKm95IFFYaaDfIwx4otQ7OyT31qYukL1B50HafwnJ1jnuCBpd25aMWBdYgLX9CKngXJA
dFm1hw14t/h/Ib5ZRprMtXTUhg86Jimh3axXqCW9gAUd8hwdmKc+yBW72f7TL6VJm5zA05wr5moe
Qt97DIQ3GjbeY/QmPhculY9mlaeaiG/jAiAd7v1Q7cFLXSsqNfVurx/ayv2yJigbYgfMra5Cy/Fm
mp++lMjFu7BqbMvgMegAh5+Va7X8qbsZuM7dwNscdD1V7qMHk50HegU3bX7ctGiWpbZktTJkadhi
5Ucd4Pk87kuGpU6yn12Wc9C+w4tGRt4sOjdFaDMSN59X0j9uz47uNkYwhZ9peT16XOoknxldNg9z
6wH4SlzlJAfyyQTOxXan7VSM4QzIbZvwVULGtNvZcFyqKEjzHs0FBz/iUJ/EyltToqN/iG0cl08e
ejLLas5f4bhtpxcDdgf/IHwnAExnOkpv6a1DCcB6NfkssQruGBUeRy34LlmDQo3gtiqm+wfj/+3m
33OVsYwR8lC9hIGZGjSSYm59PIBPzvxi1b8hCWenHZxKt+owzA4cVATz2I18gfnRHOcOI7cnazUP
zDoYLePB8HXyx513J7UmG+OQSubWSwN5YHv32JSJ/BAAq1ygt8EmOdFu0QfXvlsDGSmLRQC8Romq
DjEDbqAwebEdu09HMLNzeObxeWzC7CGepadlnk+6XRqXWmYUk9YXgACThiYxpmkhYQelN7OciFo5
NVReW640+8RSoJj8JucJ5Ae1HONRRGdUXDQmz3U4SJWo7MkaqbweX2iIoTk3UXkW6dubxvMKiIFf
w6mb4mnGKawbmvIXv60cJSZEAlVegf6hgkUnu3QE4X1gPouY8uuaJtpiKLcNGfFLIGipcXsTbIuJ
n4NoXVhsrQmN0j4j7Napo2Az7eJNV0O8Et0YQIkSbkRbEtY2Y0u2/ia6swyQlx8HawbhwWzY3Pew
I3+qOpuTlnveeDhiXtEIu8Cme6J5kngIVPfV9zXGiUQI64neVToOKp6UwYbIDoSn/9DRQNJSVfPX
Uk/J0ummrbtGcKg8Xcv+O4RAiMWC8WqMEg8g0oBsY9ZshgIAXERza20bU0xPKzlGJKr6iWxpFY0r
5yXjh003vlFyjpb1KILk7BVi3Umd4yh2yJ9Cq96JyNFafuwKZk4VgdpCZYhhOdZi21PYuyNl49gR
fDsTHqQmuHlbSKLQbxkXJBwa7DQfqaSp1cJCOjB76ioGnheA+ysCB9oZDtFkpl3NpP7reUusQ0jQ
lm/Mu0YtqdCrMeLz4dhwbMtd3UTrO3IQERNLxEJvUjwQoaZmg+FV9QRKmYUGTL0kgXuHcC7QEEUD
dHKeX8rTykYbkAEWwuvxeNB+aahxkCyOcVGf2bdKN4LDrG9jsfKD+tJ6sQMYTjhOfVT8KG6H1J5W
GVId8wEVtyEHBW0zxf6VNhmev30UYEaqxB7cZKGSDjLnCXdlcLFzNYCFhvBz1BPoyyB40vsCpm1A
p+HfNoh0AguX+iJAQbyLcTadBvMrQnSBRbs2KJ6QD70EIakRldsL22X/WQ36PAhIUuTAuZ3JbtoX
6Itrkr7bD0s1Th5evL3nH+QrCkfX1BlG069U37osX161AVdcqIhpfIVKw1ssyEFXtVz/17Jw+4QT
v4Wk+hJNVojpnmt0Z+ftlbL1smyiEa4EnLeMX+7ycDdO+Va0MwBleyRjwZWe6wAdObDyIc/I+Pnn
H7tCH2Psji7rumhvsAbeLxM2XGC51OZ1yVJlH15kNxyUWiGOyeV6zUcNO+CeyxGh5y/DEJCjLb7+
oeoop3EEAUKLeMqvOIfOWx86q13CdJDIqTfShVWSMIj/gugifVX4VcC9wDKbPrxA/8+uY4qbansn
IpaBmNIc7iEFG8hjQEOYIUJsQ8+B9VbMUW7NtUZOi26S6nLjDXRmyJ3PjJLFb6TSGlETJO+ZTBsy
6ZYQAuBmiW0gnTt7U1ltAeadbWam/M0Aa98TsoBaXz4HMsEJtk+hSGQgQqctMTy3Z4WI7kWzhkkp
RhuIG7VWvcsQzKMdIm5WwFoyBCjpAYS7oWF9EijB7eOrUQw8lwJHOXKT+2eGXQ0/i+ZNlpq0Eh4Z
04VIIokizp7/ToYvGCNQg7R8ZGDG4q+zhTKt4T8DFRKcUHc2fu1K5/oBtb3iMuZt4F87jNLX8d02
Ge/kdfR1bTLwy7SDVIBhpjydPcRt6b7ncW2gTMiQ08r2JpJSnscoXIL9La895v0dU2nBTlAifgpB
y5iaMSUONl4d9+cGFKHrp/+qJdr5A1o1XxyoRTqlhPqJ8n9P6ewlk0/kJGCHlaiYYZN6IsL9kPaU
l874LrbvUWqJ8Pen4wmB5y8yBN2yxvHiT6fVNEW3zuMXY7QEIrhV2bNNVJSicekRhhEVrpjGPq8Q
9vK53yHxuRwz5tBnSmhVOsk5OUi9ipy85UXGdGdEsG7CIYjTTZRjKl44Oky/d2hrvsxSTGM/RDfN
k6RjRS6oJy1bXCsfDc0yhuiGwZkP8pz2Yq8k0d13p084au3GPcF+txCsXFGYATma/Ci5nkkng0ZX
ACrKW1JhKXVAwwnw94RKzaaT3X/UiyLpQZ+i+srzisUpTLea91XQuUtCF9sDMBFA0RWNnzF/saCV
qqXkKVaWgH+m/gvODlykQsYG6+C19o+kCPjLnXhGtAt8DzvGAkRv8eW/UnIij/WBM+uuZRQIk9mU
huKqB0KRZcFQDPx1dNn6IfOovse/oJLMsxu/YtJXQM1culThs+AaY740xIzol8GcCEKkg/Z1cEPf
kdarDfAhQMk0UTA8yhsCerlIR0KabMP+RchaIyWYe3ybv7TyYkwCRTGZHEtK7RrZL8tLkndyfDa4
C/lQZhWbOd3q4iE8hZqWEEq8HZiWT9rC7z63mSRD8gPE9RQ3dd/BsZz9yNqwKwb4UVBgmc+4E1/C
F7OMPE2JX6XGEoRrxStFjfsi5laA+w9+++6AKq5+Wl+BgbPkAClF5powvQ3KaUNt7GzGv8Up/pT1
5rzy+C32Xs19xCs8JBmcBYorrvyww2+kN5YowvCyvgJpqrbnyOHlOCCX+DM7CsNWIENsEf9vF56J
Jwxu4O+Y1bcKoatW9SV6xPBgg07k5ruYus0dxBbDC47tVDAWu4qS4oCRvSiXxvEZmW7tM/wxi4iY
20PVHLjUVdtr78BkDpBeIr3sEKwb+qF5RiejFhUoAz8Cw57tXiSeebLcXapBHJZDdYUL1oTy1yVg
NQJLuBYYIqbhkRfB4BYqAo1aaL/xoOQteFyI4iCe8OI8ZN0wF2icWKwBIZ93zlk3VOdYaD5J4WJf
cJVMAiLIws1N+5cFzEXpyKoAKIawQ+suy9ylBPbwb1bIGsl1W0x/afsfSo0b0WX88NM//Iw6fRAG
MhYJxOmwi/7uSQWfaiRX90F0azSLErlYpxtik8olJlLPaTwFRnpR4Ify8k+PGwiz/q0HWq28Nj6d
hg6I36Kjtz7o9BESYip+3wpXtMknRoUWNdpF1SKKZG0RcySNFOLahc3Zhg/mBz/AJ6U32kfidl9y
BKE3Nl+HrPUCRx/oR/695oQF+jTPXo0LA3su/Urn7V1LHKWn6YEaenqH51ivMyIl+PISBbhNbbLk
yyr4FK7z7QeyJahMqz4I0yI6KCcBEE0U1uUcDlvJsWJL6v3V5Y4JIl0QvUPCp0+TDlOQrqZ5m6aW
YQAynlWlTYHrpGP8OsmvWlo0H4ADGY76JOA46h+triQGdQgoZcefScL9b+w4FcB6Q7h7yqEsDiYa
lrqHxdyOGRq5WZJNcCE7l8eeOLceEKwLwdDs9jWGIZZuDwW30It5FmSMTv0NpzpcY918c6uWdgoo
QzONzYrckacmpdFbMkZoABK849AAh4tJkXBFyrXjX0DzSmyelfc8mA409RFNXR9IeKeqSpzMzLAK
a1CQGAMav3b7EoSZqF5EHCi5OaQfkgg2kZ/ju/+DF3/GnbPLHnJ1sTqs3kBa9JEmt+HgoB5pgLV7
+rVECp1Jr087ccWkJ8wJiJYkD7oIkY3FkB4LQ79Hpp5qCzDCfHiqgdQoiSbZ6JzcfEpDuiahD1f3
OWfybGsZmveJTNq+maEwmLO/wspcPmLN9Vq2nRUCYuOpNWbn3coI48DnIQQyvtrd4FdDQGjzZieo
8MvAX1cGSTCvvmbrDUO2cTFq0UtH9dle1fVmRD4a8lCvASlBIbi27sGjb3W7Krq9eDsLHcJRT38C
0eksWcwD5Vn562bjdSs4gycIFk57vmqsto+tubq/+TKzADatxwhrM9VZ3mM9qvutd1kp76LfFw8O
/GYjStZrRRUzn1XJovx4fYdSWK8E+6TGEQrHQozq/+UiH2ZZEpcWJ91UB4ejO2sZmeav4sAWd+oK
zNLEDEzgpf8WdSdmx5zhPhdHmzzYAIBdDI0iItEVv6wsDCGg7jEFsKaSVjBkrGV9TiopwqfXZunN
oTWStcKof4dPTY5KUxhePsfxX6ixqu/kDzsu6kwEMAMyn8PpJ5uebblnwmGPDUl6/KkdZFdp9Ku1
xtGke92uWw6XpFO85iK7sseRmuMA5yowhjDNaVI1wi2RaT/Sq1HYRHRoCXiFP7C1yGrisqbZj3se
8Hxp/EtLF/QaycH4Jq3I4dAfQ1N3C/khbBJankl/0B8MdW3xr6Rpben4qVO1mo6USBPoicyF6AhK
yHYppNzzw0Mf76rIr0zXBGOeYPOMtr5OcG8mt/x4LyDcP7Y2Z4GUBAUmd1OzKJXwL010eobyO5O/
0nGfrYsG/a/OO/UkAAf1DG15nG4xQWCadUcYuz/Ev2b6cKZwHMrmmMGRH8OVKlN6vtqVN/S9tX7R
KQT1mw8ofh3rVBovTpa9e7F9Kf+Da/KCD5kfi74r+zNQKQWoOu76bxndb17LqahMxBaOHYNRSPi/
VitcGPSMW3le+J2IzSimTiQMQTiAnlowNvG97K1gVYXe/CZrDxYcwpsnK/LeWcSQLFkQ80Wz0caL
2EzLHWtRqF8rhXTEEVoQNvMo3UDsLDTVMDAUhaW7XeC5BRo2M/ybYQBEIe+PpLcL5ZMIsCUtGjIl
wMgbYYqPtiiadlmlVZ22OcR4fOotQFLM35K2BqAEdAcBNNLRWpa0XG6msSv1JEwPGMXKLgNclxt8
eN38NzoKlBwISK73h4czBMtA6FJOlfbdhM9WVNAC+MI/BCj6ozxtZdnPketKjoV3TaYUec+CUhfb
UmVZ3+2O86cMMSGpg0iDzvRLnNPDrqd+HyJSgMdiyDwHiQtu9ZYjmYWKBdZtX4Nd35gUgAaaMum6
DT9MeFc1mZN+Vxq9+LkUIRH0Nyv1mmTMpcwJ+oP9rpYiM8jgDlz3sKaIsWQoyjSeo/oEHqbpDE2P
x6ypPDT3zgDyU7ViPDE24niHkcWaN3Yg5cTDuOz3Dl/2Gm15PUFIkbLECbK3HPO4Wa824WN2ykRC
XFCX7GNnK0hD/J+Py+MRPmBCJ2mCv+7GlCKgrZwEyAJ6ALrZvGTbCkbOLk29NEZN6i+/fYot1shZ
AkCNUJSQQc9QIOmzsZZ5Pifsr9/G8YqUJgGVcEVxSk5ooMo0W0qadSyW8mpwoj9FmkPdWaKfQs7a
sj1FJg8NrsYj6l0Bq8xHs5L3I9vQFUZRQ9Bi4PQlNUPc7mGjbIQaP5G8mru3YgRvxXceSBMZsE8X
LG6ufMwCWBRcEmyWCbJet8MBz3Pz3PwAxOu1PyOK6jg1Qvq+qCsAf+SPIOSIWuToTteRfQulURil
Ov1X7UUSiQtVyJSYilPxoLxPnEeC+gJuvOibUc4bjyIGImYJJsOveCBzOGyIZm3tnLXNESO+jcoZ
409vjuQtoewWraSbaJG4KzDKQL3sf446G1xA6rbhAa7ghW7+nw7ixMN1BtKeUVvt1rgJgqIC1eYO
xUK77PRrPoiav4leSQNfaHANHpmtowBiFNk5v1P3O+iNiNhLE7yIrJcNQTHrtrSPc03M0oakzpPW
szShkJCHOP5aEP9p30JJWlFEJ8pkmPNPiiMU+pNWRQapGPpG5bjh1t4q0V2BoaZYtcAwP6ZO7GFb
IH/pwN3PT7HtEVj0LLD1FhTd0Qv8XQPOaiG8Mf9eoa+4OrCqKs99F1jAcKqpKU8t4+MbTH8KkNiY
9HFybJOmhdYYU18QJADUJwpPpZV/uPaTPguiXVgx8rVqLS61lDl9zwXsWS6ZBxOzB2BXyPSFAHtL
/+Zd8D2XfaaJf1rV9VH2toIO4jbSwu7S+K0yvU9B7cQ9I0FQWc9/2oeu5MPxvq8cwQgsIcV63FRR
oLPSb+zTynm72LXuqpBB5Uz1F/B9iYRlggjaMoOvnOQWScAGdnDlGkeYR1ymtLfqO34rCJ1/WJNR
VebFz0xFpo3fEv9ILEx0mLL/E9oneRtC502/5cOzmkrOt0+e+et8R/xv9zjou6F78g23TXOd+/+z
80bxPhRwS5VaLyyWhtSDBha5EkuiUAcACvQG2BcgFiFNJ+rvMt3714u1ltg63Lq2x3HJnmnB70V4
O2KTiUnz9pw9vM6MP3rvH9P0VJ2bgfdWvLQaY6tLjyddB07jl7O4Bo3gN7JAJN6VUKXrpvT9YSUS
Kq55xyxcR+NY2sGR9NXa+RWjwmsFH0J5iq7/fs24KwaPiHufXYBIKoOKfI++MA6oPuci5Q8FhNd+
g+fqu6na1J0R2LUIhI2zcjlg3wkOhqUtLwRIyWsF73E1AsQwbDGgBifs3lw0bAUSGQA7aiRy4Hyo
y1EsnP+eLiMQcrReYzjMcZktqZSyAH4zX/faOXLCV9g7rDHc786BDNBG3ETuUCn3q7dR2nrxPH7p
Kyjq6vJEF+nrOBMA5/T1gSdWwEu9XXPm9vZbShgCMRR4llmjzrKPDxrOANciJcKyWqe+81ci/rjb
mlKgLubY9WD7vmeP/wzdj0IqlvJUMkbhq1TyqeMN/B0lUJcY7vIMoPLffJq5ZalcDn6topHwvhfc
5JdbEaj3+AlurLsJlLnkEGYHJHTiD2OWOOOfjOVy7oOUmQtcAF+JEJHYVhzND0VdJqCVqL4Nr8kj
ceAx40L5l46nuv77rg1qFZ6YqMUvEfzFnAxxMhsQz4hykBkDX9KNoZqCWguVKPG5+6xwIdrXr2nj
l0EmRZqZrPjRrqzPJShSuR05Zo4pu+ETUY6rEPp5FDYTXJKP2di9AL5/HLj9qGjKdr8pw7XfcKkk
tQbzFkfcLAC4xpAHojP4Q5zgkIEGp5he2Zw1W3i6H3aMWjxYyi0GQffPFL9X9wLSdvbaZ9L5w9Lm
swehdarIsCw9k9ZMSgIDzwUMRN/0o5Yj0QuaQrkORZbmJA4YllhrYTjLCYn7EwGnvRkezHso1Qx+
VuoNThbwbxIsQKfkLl8UkYAYe70bkSCfrb8b2/YNJK00gsaco6wR1IQcuNK+whFXSaEkapH/o/OC
UDb2fh+n4T3hEMGzN0fCSIIOOWME9irEe5fSxzOMFI1n0tNTImSpppLeytOfV4ZxaOJaV/FiYYeu
0Mung/AYnm857azdYGBiWGRbK6hy38kGgfhRomCmJ7alxJRzx647l6jZhOBvj1R+ClwV/HVUkZB4
xP2+Gu2VLRb2Z+wG5Bbmm2XO+TllTHGZV0zoLgsVOq8b1Syiwk+B7BeO8xWbiXGizJ/1+CFdHBic
Jq4nEw8vOhvp4vmm0mLjZtknVuLz6PtYfKPzXQjFM2cmqKf1th2FKxfvc65rX6kQTfss7vFwxufw
qQG9gJsTqoPGRPuN+w0WZ9tpqvddXSacm51G4mhpcJuzO95Jp4eBOCDtl10/AGNDp2ULVD7CxL1K
lAQDhKHP+WjTYq9IOtQTcXSg4KanZCOL6UroYekdqqQV+GPw6+7MQDZLHHWv8vjhuk6r3f/4SMbD
80wHTkTLRrkLgFINT5ITDoxybErYrTSfmaZ6HITygfItHykPWB494QMKvLQ362ya2Yn8hW3vP/q6
5r5+4y40qEBefx6OkA9UyQOWDtnpkx8ScjBs0gEQgmEpDBcQkUtVQ3K1u/1Ok/yq02qGuVDbV+Cw
DNQnkXeLig3jpChbBMkkifcy0kRhvXy244DUKIfCAtPs39giA0UkwurgmNmehTwqbCGWjmgunTyi
b16/JJuPRRo/6NSYqEO+i9wwgVF04vi5rXAm0CaENGEJKi3T8Q52fhvhcn627r/VWD2vtElAKMfx
7/ZDuGWPnKzzJ/c2HwuPxUOQTubvnfz9Bd2zKQsE0uC280KnBQunlbcPtVJcCIz+J822iMIFM/80
Akb5wsVlXHCa0aJVryrt3Itc12jwd4G9l/CguHM2oTj3B6Mn3egZNXD20lmOmKXYx8Rb0ZKB4FWw
XCU0v43PgMWzIfP8mc8wg8dSHv/PbSdF4dRoZzg/92/roI3mE7/xAjBVTUEai6Gwya0dXimPUfCb
CbuTOzvased7UYnUUpVMNCnzn7SRotO7X2LiBZF9a1SS1D9BjIqnn9w5zfiBteezT78+BzQ65Mt4
OE05PSzKQq2ZBdEoEczH7JY3yf8HCdiHirKhgKBoTOV367D9qZ8UNebT9lC76Ywi/mecq50azktu
aX5c1Rf7Gvx5Hr1gpwvsxTkkOAIrdhv0SyAu+jYosv78yU6luUMO0jaFIrUtf4R0P1s/r56N9zsZ
SK6jro4itxYG+o7uMc6ixuyeX978TZrTYO2HRObN8wSnttkqmLVGbZ7th5d76NBWlXxXskOFdykR
cAVsdneVW88YArUGFuLB82MY8DrLdCN8ooBZQNbLWR0cZibJWX83sPC36pjtGicTBui97A16vNiZ
dszCq5orh58T/4Xf2Ms5oihYIahuH5IkgBJLaPdbCUaAih5vfGzdPv2g5R/KtMiW1s4h3ORh3CH5
GWpDznU5trS2+YzWvGiQRy1v6nQPUNtfxMfVn/UpdJxlDrB0zm8jZsun4KLCDMO5f9FCxOOednWB
DkcuqF3yNUpwStRFJaxCOC37DQwiQiTnVYlE5JLAf2bG9Bio/5qaM7XrbADU5UnjbvFTAplX0Ea1
Eas513MeoWxvZEv4CciTwV9zR3wkWTx4So2EsYURD7Nn04ebAgdV7Jx0XdpLkCRRhl/ZXYXafFqP
3cxHfthFiWR/Iwljv0J0odN8d9zaZ5jYEn03Dc+DpPdB+Lx6MarJNuU+1g0so+Ivc/CDJiTe6eBk
yvzC0J6GNYluKS+P2bDawADEmzdDhWy/4qRFAMfo8RXCS/+UsdUv8Nh/Xu99YPWav7x0j+VlCHk0
4oicqaLsk6QC5kU54v1t7PB1IGVtixGrOQejuF2T3uqez2b6qcthjlFYqyZD61V6OaU9LMhoINpD
9S+fzi3+FAjFlfnG4yv9h2hAqg9+TyxUrgf+9t46TsyhO0qgiulqkHfllSu1EU8Cxu97fCNFfLK+
5iGgv8OqRSfMjktdxBYhxSqhgvkLe83ug1QLJvixlUBnLABKUVD0GePYAC/T99VKweFccCUsu30W
i229wQIHIVF4IXlWKMd4qJHJuko2dWb/Zwr9pvhhQNnmXAldfohcf9qKYuhNPdqC1fFLCXfza9sp
Snh9rSW+xNOMWKcgG9M5BeFZ9XqomtQ+AbwyindpW9fy3MA8NnYPuWus7n5G9eXkb6yzvff9vRkZ
7jzK283OKW/C6IyIWiQObPYhS0DedTC5PbtU57wPBXK96DrHXGIEjF3MSyDawnId7BUeIpqJESR/
5xMA3oBv1qhl6DbWxS2b5BvLuhLAneGU2DhTuoUdJKqlIm2GOoqPFM2BdGQl7GKRgJHt4ULBs8P7
LfIMAgHiosVPD1KO9PRd5FUobbqW6qhsv+n3UBqwV0nD7Ybbln39FCU01DozGwvCWgvGrp6MK717
WK3gLsXcpMk7ybM/EdDT7AR3mAaBAwg1YSEDxDq9dTP/K/hPgzZLW866ZKdTIlLZa/1Al9bAzX7L
PbRx1HGn2oYIzIoeHQCzl676oUT0grs58J4Ve9Ry4pWlhlSTJRfNaqyscjeIv1+yp7ylRZi7xFbY
p/Ua2OVAdDcQhMp5tM8nVbGiNkCiRmwg+7ub0KH4IFUbW8p796/neuvIQNgzX477U9F1dzE1HQrr
DZxeqYR3ME0K7CKZ0FR4PAFvwqshW7lZD3IELl6JLOmFY1qnDwzLPI4ZEq9ULYrCZErhjgSQWDHL
qmo1dWdgDZG5Ib26oyw27Uw5KbHGJOst6B1nxMaFfMpRaESKgW1hpMXoM0mjGKEoMliDnxpAjDFh
SD/cCZ2nJlwDBSYf1cV/oqKZV4ek6L13e3kp+SIf/fe4uGTUDPgpyuOHTS3UBAInjKlsMGA2jFt3
k8eWk6NmX8zLTv0oa9l01AWoHlgI9uR7Wr9NDluH1aZ19pXFUnHxr1sOgiJrtebWKk3e+83PCP/J
m/OgSnG+ikr6gvnR3rSAefgLVLT7FFu8CLnigQS73F93z4hwUQxTmDXgjBD+rOsWrwVW//e6zXK9
djzhFHJ3MEJ3jlSg0BK8CBqDileSt/MdCpsdQqGDRpIMnxlzELzBmO8yo3r7A+oK/whVpi2RFXTm
xXdNFnSagogJzWqh6LwsORhsQjRx9Do5KhhXhDNcw6SUnNlt+G2ODHFXZoRpwzvPWXUp6TP84FUq
OQPiqt3W/mKcvvca6DKbjvUX7we0fRobiQO9cmARJAhl6FoKGHRPrslVxqLNygCc7Qbo//Q/RKBH
hO0deaql/7znELAIX1KKhpN7HzweQnz3Hlt2dhguM1ekK1+p6BBtfsCk6k9cJl539YNDZ4hLhRrH
+UezoB4fZY4aw5SmiGpR2wElkcM9z6PRLA7KArST51bmKHgLau4arGx/T1I7S7A9InzsnayECtyP
svnOImx5acD87iZnEXCIKDufOrQhBIL3jwPbLiAXnOmIHXNHybEvcXfbGI45EKSCMo0mvvdGLu6g
usr+Ca2TSgubruc6HeP3UFPf3IORq1ZJO6yQ40fh57hUTWPersPGkk6xIzjLUWqHPVgkB2ItTV9c
vgim0SF9tz3WHTx2CKJ/+pcjZfa5/tPllj75uEfMvhKJNk8x6WBtXWwDK1ZUlQ1S6A8Ju1skGUB9
2xfRAzBY1XNPzozULMKEV31wjfsJXMnPEZU3e9QApFhxMuW41U2f5kN4vu8KI5+KAY6lk9gSBRox
Xr6HNw1B4mgd+3BYdihkx4uSmxy2Fn9sNvJxxhk9WWSgFdK3BiJYrLsZyc/7g3Pj1PbO+b+zj/mz
TcLiWvqmxtibwY3Gbs0+iT9ah3ty+Z1qV45lZg4NeGO3WhuzxP6cgklqRsfoGOstLzBPmnRhRsUf
uBmMC1jFuIbeeBrSfeMCbxWvynRFPFxQzv/1UtsyE2E3CIY325F40PneCTWy07w4Kss/G8xmQrwc
CG/M/HQaHno1LY3MUl9zgvztK3/M30VDLn3cTWjYu7UXVuabY8SusL/G8PJQDA8I6AZO6RRkHMTn
JeQvseythbjE8JNx8gAHiQVHbRsuxnlH4J8F3w0SG++iyevM782iyh0zVpYj5zkUvlnE04DDSWak
bH3UcOM4Q7w7/zC8JG5OsnuwF1jgE60up1A8IapyJTDF1I2/nf+G8IRNvbNXSAM+Vg2JFwb9h9D0
g5vFd0EX+fm6jRXamYftcm/zQ7EygeFtZi129yfjJPZnROvgvmgY3QAnvbnhTK0WHDZMMnLaVGpm
2H06SSoDwIukE+VChAMAwkWWI/ssWEPUid1Qaoldpl+ihV6EKzxeV4HLSC2T8nCXXd6Dz8+YGC7b
ATzHB4ceI4mUcix5rQC+6AAZDumjVYiko3IncKcxoPeGKC7CfsiwcPlvrD/09/QBcKFsQa/MoSfn
1+n+qUgHL8eDmYnjtOhvy8VEH0VcbWoCJCxnW8afsZ4RtZwPu94aFXF9yw1/QNOSlj1c1rA2EuSw
WdChwTt7kZkKOKrun/WHEYt0a38IeUgIIXKAoqoOJWewGE9RPIkCCHyi1N31tVo53YKU1JeQTANW
qbrXWiabqwDiL8TTDQtUzXXShYZ1oSHlQxSgd1B2RKrRd9Yxpjm2rFxRBW0bgo4xg5H34ZrBPccD
NbO47K+eQ0cePpuvKIO3PLiYTiTMQRStYP63h3j5yDQhPvsWJ+o7ExO2+8qESdPKcdm8JSzgSNkm
sMT/Gygnn360P/FVrN2AfHE1r/xmY6IVldJbOSQnF9A67UONBGqrbIRJOfac/5FhYVwho11qMQhC
DTF4s5DYCi5PBAKGVK+p09JDaLQjwbUQJlAUtjE/0OYEPQLTdZyt0OdItm4ZkRGVkfXqpFWW0JEU
y0Gcr/o09CX3SRFIMY91r9n69XN0GLTG0vJHEzy3lPWx4IEPly83N+WboYdgtk8jN/nprbEsqutM
/fKIjUW2WUR6w0QLRjB6jr2hj7ZpsJITLYgV78VHl5yTMRTqh7LwguS+VFOS8boxMy6cu4uXE6FM
hjS8z7crXy03IFZKVNFJdd4pnyQtXI7XZ8JU2rZd3Zm2nY6+qJWlyI/Ephyb8zQPM1FfdCWU0Ucm
JHjl20b4wLh3XGJiEUzDKh+aS7y/2gA/pTeh4OB6DtgbT3w3A2M15ajLhRn9Q/dqDEx1WhTA3Nfi
4Y/m6hF5gArOHYQInFmXpY/dIH77uV8W8UvAWfj7lv1QhCMQCLmHgbZg4keGWUrnaVt44BPZv0vA
FhL/y0vUe4DWCt1gHZJbb7tkFUznMZ/BtoDG6+lKVW5BNIQ533ZlMUvVZ6khlu0QTN9nzSkrGqqE
I2+VPvTpZLHs8t5Qp1DkVchG4EJYnMG27t9j3Kva3OLLX2rSzy6siKUL3abTwIWTYBBkboInTjXY
oSh+v2A+sG4xOeBRxLsP9RlWBvzkvvakZwjzUB95oFzVGN28y7GylC25bFIqdZJhKtrqpOL1apiL
T267iuMHM1OfEaGALbk0+KFE2Ynq9LmLwFwdejTWHR4iRMWSwp/gfV0n+SAWFZMORisYELP28ziR
2Eim+DZf1NWPQKQMJ02/GyCZJI4huLzdNKEh9oC7YmDAcmhGmso64oLuxfdub6zKCOOeiQEEW5eS
TYkXGDrG9CESnaBEZZ9R7Cx+/EkOHUEBfpRpCx0gNSB4oj+Gw8kZ9EoJVf5qHfZNjvFP3q5msbcs
WTr/KyYZdK1nfGspngVqgkxHc9fIxRixk96ja6wCIfLccvDHR+apFt4a3+DHsn7DRseFydEA7cGQ
dvZ7AoCqF8zaTc7913fgjKkclYQTh3/X4EkFcOGoAyuVbksLy2cK8okHL/c7Q0B4y8sy+o8ypacQ
rtYBEXN66c2SuHvgrDuYXBlmTzcwU2vqGJfzjCb17eFtuOqstGhj5lwVsKU0ZpGBN3woBWtuMpy6
oabHdKuPcO3Zyk3LDPWDHyd38JFjXUWsEyAlt5Tj8yPBAhY2MEAdrf4c4VAxmd+sI261HSJuXqDu
USAWQe1D7tqZBk/LZedCP5HIreQ2BfBUKaXRkLfKP0+ud0t5w0f19aXj68LKKH4wbAN4H9XqnkcX
F+vfdpWexPNqTbcNXUtiphIoLcsiIDONedL3tTswzK+iM2ALh3aWsHnfui+vnLX+jqsasp9eT/+A
1XUYYejdMTpCOffDWTacMmMMXbYl95kyZ5hh0SNTg6p5MzzDXinVynLVEuqilX0mdy+O1BOoBB4G
cN4l7C5uFnbyOGh+eqPp+q66x/vup+5S7pjxjlT2vCDDt9r5pTPm26LbfdDat27JO5guE2hDQGSR
+qjx2H8Unzf/ghp4T7aGf5EcmqZgeKR+XhS9r7bUtOL/TScwEnBi3FxVo4iRSN5JkWa49wFzzC4x
XvNBbAd4g/XGuivdNzLf31vc0JU0cJok+t07yXjFi544CHuiO0Xvq48CGzu3VZhggcegiH7PRfSf
lWTZMkxXU9HTdwAa1RaYF7xC/IQNig+uxXdoZrfQhgaTg+OBk/617JaBCVTqYFkAM1PHCE2lKqjx
Zr+i6GV1K8BTN+q1HFHCo22W5z6mKCLilyqtQp9LO/SlSLcBQ23q/Zi0O0onzRFvNVjnTA98Z18J
NlSHbZkPTHbIDnsltYNZaRynLOiaEP7QzsXg4feyUVW/6pbIQsZWrblweF4NEkEXS8q6jGR2jAN7
oRrxA6XChit4NNKabJw/xVgG+ECgqs8iKcWyrAFVneha8eoIcnq+/8ZHejSvrnz1L/PouT9KQjHL
fZ/8AqMg86kxsAB2lVCYeRf72zzZk2SXtFD67iIFa2wLqUkgeGvu9a+o8LPDWq6vs7x+ALkOabS0
Hw4352M0n5CIZJXqlGPkdFu4lGeJatnO31ptmJMh2Zy0lVztT3q0iXFEViegzapEYqyLhFFulF8m
BU6dWuTKRBCumbq4hOPitfe5fv0YO2NmopCJHu50IS3wIS8nitha/RNkfU8Q5/NLuAGMkbPvPnIf
HSTIkSWoeG/GQHH/Ll0EfLHOLjCqd0pVygemK2JYqpqDFpoYAV9DJC0/nvzptrFm/blLW6JJWoQn
8yGcBQBxlxFNe5nKvqQpRLqvvdjBe87VYlitm1Su6vSIIPbeFI0tcSMyLIl26TS3cR9X2BaEgFfo
/48bfgPO80P5vsPnRtZuZoChmUz3kRAcUgB/C5c3dUHq0wRZh3UJLnXPsAiO5H9sAKp+XiXr7W/s
LUnPGK2ySWli0axA15skNb+Y/Z3x3ofWTLa/Nk5HYXJzXTO4xPx+3HolPxWgEjAqCLtpCYgtsZqm
NLU1eSnMELcGyA7wBde5JTPJrD97qC0x2XE14R05gnfNrgoDmGnucU5pH6PNWWBDMMHcJ65DtA4t
dF2Yf+l8/36LY1mO1eVeEDT84UqwvtlXC52sbJ+7+4N59/8DcfAUK5snY/cCa75wry9v3WOiar+U
OJGsn2YTxxh0zaIoV2Tz/KlUOoe95hXVyPqooU6v+EW3ou0wQhpepXyx40jTYbk06CwU7XuTrM6t
/GCuV2Wmw6c8oxf8fjkYy1UpOLki/EyyjDLteuD0hgfHw9zn1jav1sZxXUa1M4o5Z3S8mqg6am4T
Bb5saGNNecKLkyEiojVvVA9QnBR1uiEZCNRxQO1t1fmTRRik6gGz2OKccY17JYCdXH+C79IRYtPd
LCFLbz8f161z0vRXyQQQFkNJyCZJr2lYR6iw/XA+pD2kJ/4ReRpywz85V81UmwUZd/3bD0eFz9If
+ABVoVSKY0hRjUoFKXFqdM2ClCfO0Llv5hkOHb6GZOUSCosvNP+cVX0EYykrJaCHhDhUrY31SuJ1
YAmmRQyP1jB1kJvsCU1eTVYupjdk7y/CGURdcZytD7MuvsjIhuYfrt510LTyu7Y5lwr0jvXB2TVw
RczFcS5uM6MxDPaEnBhISCYVLWaZqtORnXpnnA7NlUiK4KkRRF1HItIVvEWHW7pLBGd4WSoBzeLh
e8pt4j57Fb4VlZ380Vwhx7tvGwKA1BPy6w6wfGj7/LMCIuU/HDF5UTdo+LT0c6e1S3d9tY1zliMF
svB2etXmNe0f+90qr5dGVgD0bE8pvQiPIufvB9r9hdklnVPd0NZm0KmkaDPM24c75HKg9b6r+Oh3
1Agia3Mem8IjHscGwTAg+NipcsbO5zYG0s7QoY0WCEhYxJEZDj9r5Ncw7PPXH9jC+zJAMB+K2tMw
cSKhxXeddCrZIBpe2XPkUJRAPqU9BXkiHJSRk2NyjM39N0eHlN7FuNGjpJQxDl1jC6o7hQbWfSc5
ALARhhPY6WxvwzaveAQium5MlJRMD22Ov6XMYY85eZHaesLpchX1kqgQb179sJMW49y4b/ZQAc+h
WVi9yKVyzQXMfdOctr8wi+Fp8P3rsdLRKdpmZuvtW7eSiYDG/mkOJ1nQlsjjpmLP194DS3S+uDJQ
b+3n1NVgvoWefjnJRfJlv8y/ekLlt47tphu70DwyJz9zPhip4KFDkvXHM+v4+o/SxZrW02hHe6Lg
XOcFyd2W2TCZ10Esvdpqi392qzKajuilQb6HJUI575bzjzpVMXXq+qtxYqVYH5yiD1BJb++NzQS6
Qu8jfodu2+JOImMvrEeKvXmRzsvu2DGul6rLGQfEoPrzc+gq/4JHaMTKQDShTsfE4LGm04zC0QvF
BbtjEGp6aCXGLJGtDnL5Jah5q1Y7ssMo4MMBmaAHaXB8G/tSiy+vI2dDck86oeSNHMIY0pQegJmo
YPnJKm+lzZLJGDFZ2LJqZ9cadmAJuXvh0b9k4GSyODBjGpJ982wgxUrW5y4104ot1PVto/yHEBBW
w8BvxD1sBoY6wW5GPPEVsu8vJu9LoYOVkxQ/kFt8T0aOFG8ack/ZOazr1vvHQNgAUgNK8EOlK1XF
CRO5AQoCTmibv9VcbJIY/q1xKIkovWIt1raYqkwzyv1NPuPluJNUIgE4wR4Xy986744OM5DnbcN7
G6je6jCsVoWfy839f5UWQ6XdwfqfZWQDODCwgq8kwoNrjYjGZB+HfBPSZ26Yn6YFP0skp1tfVw9i
ZLklnlCP8I3Q0b+BFXhEdLrbAzsPDtvKONa/XAS25fTAj5BOz3V81ESXeHuX3Q7mEjdtjmuDU84Q
9PV1Rdl01NZ08gzLSHAsmDLfT/mV5EXj01PcvRxDuw9SnqLNIJm55aVmTHRcg1QuW6/S7s3BJGlf
n8FKiZVb7oCVJ5uvulmH/XeBIwu4sRvKZESUhnSlP/WwqltZ/8eXHyQa5ksxjBCevlI3viEjbOuN
WaHLucwAd6FM/yrSAzS1QEZtQgUqCU+Abq/mfiRWnePDGUvphI7zMQBSYYGqNHQIIyFowJr492Jz
nytTilwAHESm6vLF41tDtvY2NQHCw/YxCS3LZ4RZIQxUIKN/BXkUB/jokOeRYlVUOI3ZITNbmFl3
P7UET6RZOa71pD1o4pnRgmnczCKI2kCWe1KfohAw01bG9pJ45yPSvgGMpdM8GaLLd5sH6sxVha+W
GTPrQ8a+XIwj49q1q8b0RSdubJIVc1o8mGjXA6En9vOT7EsB9hRHvKOVV6w6QEWT7f8Gv/ju6Klg
LJZ05P6faidApf/g9YbW78ID4+r28vNUgt5WESkt/hQBCEJMhgMiCvUuinjC7pj7A603RmJ84hu0
KHkQGeJqZcLNImzdQM57StKIqkRjK97Y2T2R3YTRnBKnZtqbTmcwKflp86hVwdRdbdVkhDb4DPOx
Yj+QxCAGzSK19y0xrxUiI8jC5GQsHZEeHXDVE7GQYvPbUaTtwRahdflwyqArOehMgTgH/xI654x/
VER9Q5tnrjwnW6exRDTYVOvOKrGYfnpIWABfiJHpn7+p5XIwDAloIv7F2j3OghrmXEQusyVe3cTz
V4zYituxGEoPAefGZrc/KxJNeS8BaHzUeF1rWLlgoM7kWpvq/KLgWZfYu20Bkn7cUoGfzISJvIBg
KglnJMGOz4BlxKIFZtrBuc9KnqtndTcdaKBS8L/txFUdC0P7BNSOpzvQoCw9yPawFuN/51rAnU9g
9F9NhM88FtmOM1KAQwkrjjz4f33NBqNZ/zwYzc88siaswvHetTkf1KfWtgd6PrzkVvVPfSYy1vk3
EkDRWDyi4YURSfgK9X67XmL4FK/qUi7/mbkuovde9+C3EHB9o06ViX+/Gs/m7T0iwgfy03GIkTYt
7xxZJLa0dPd4pD4+CLUfrfH1HH+7RCGZ4wnTQbI2RYY9cHVML3+nNysP6xbvvkHFdlmFc3aC+gtF
WHJxcvPL9TlbA+2khgXqH1bV2c2Zn7j4cjdBqu9E6CZ94Iw2DVnBVhoQEKVm8fCbUKq6NMI7if6a
KZvIh6hmPDx60CLV/fyrDbxvwOOhu69MqFcm3mPTshYsSC5guaao2355pBuJZt2J4VVu0xX056Ks
vdZnxnHWN4Mw3Unnc7QiiaL90uP0gURAYUKmGgSJaRHbhd3HVq363RAwhu8VfBhcOCWyAPj8v2F4
9jZWRriYn2rgVdiL8zDi1w5VcpRWqCBgdpOAu05UHKv349pk3jWgAp7oW3Iymb8DrrCbwmDCilvZ
eHtd4roZgyDQglvXlSfS2yeofgrrbYQlx0AwNbJHex0AIqC58/8FivkaccojFejPc3VCQqpu5yLr
eE8Z/zqklFZoQBVhjwjfjKplV8NdIwXzRanP3OMp3xTZWPgaGrtqsbDHXKVGXi+VDBXNQnnECUG+
jeSHtD1Idde6aT11IqAXQnhAN3ZVhemaYHamU6PSuMWXRAHRmLYImDHYaFchrdImFu5cPbEXiYYk
7hvR8hcztY+eraIROg6A4dTqZfD3360Q6pTmntTqLyz+duPCqcAvWm6QW1WmYn2TD0/p4QZPE6RG
pWqtiv3PkFQ8T8gED8dcrmxhBlRC1M7gMmLwclH27PuwUNdfpRpdCLSEtjL+K8VRsj4OKaa8p+3o
kE0fIL1LhLzedqQPWxaovyzaVm2kgxfS3sffaNO+v0H1Osh13bg/vsflaP/j76IwF3hTlzZIuBFB
pcUypgjcg4Ql7ysNboIiwoECbbStWkqmdaTQ5enEOVZig+DKYvZKRlD+32mDuY4bIV4/UpVXp86e
CZB/2GIeMlC0kALtFpH64MOuWF9fpgX9BPnPFpv3rRV1TZ608GNtG58nCEv+x6Xetlbzes5Z4FO/
AwQ32h/Q1MtH605vzEsQQpqhdTex8/rq2Rzp4GKcOhtSUuYbzQOge94WJqCK2QXx06mzv4Msl42y
V+ivj+c6jAyhw0vtbjHklr7ZXF2n/DCH3ee8y/yUrcP9twi04rWOHndi0wchMri0S65/jTflE2tb
/j6EewHvP5SOcfQWyZlVTGq8BsEWS+Fo20raggYsXviAmdS90Sx++UcbmiQHvYX8OamlRvrh32F0
muBzyT6o2leU7Q6YP5uqw05c998MxLs8IdHlPpLx0ua4hYoUEPPzautNtqReC/czmpc6lbVzRXhu
UQFdNcXd+/TykT/4EOlSMvUs9YSEiAlMCVY4ctRa7N5MqCq2l9vX+Ji34VQqYXRkbDZZojk1Dr70
MXtHSaNbwcNy22Gwy72tRevTu/A6OZQE9dFrjhZ/v1uNvePDMAvSkE+WyD6qxFFBh40ssLuAFIws
XwUjhB4oo3HRBilj5Wu1mAHtvDwtfUSAcZZ6L2u5D9F9FrSEYdM2hkNpR39roVY5XxENzdA6qLb+
QXj+nRF25uRY8KXcyWdOsmb74+NfyboD0yM53OzzKnw/MtZSRGjwiQ1SToGFJe5f1fR363HcdXc2
aOVInF0B9PO2Zr5aeoBSNO8FLXpjR5IYWicvfFIkLQc4cEouqj8u+PBXK9/b/mo0Ov6AsQHCu/oA
Ewnd8TtFnFVs65qaiTm63HTniQH/iWRcSBbLe9sMtBYATQ9GuKfsGQcVCe6REaytmdYCT1CvEJv/
FyAHHNp2pMX+/lZAI1GC8MTKiUWbVu5gX7bG+Y290p2/mdIYBdQJ06PkLMPmCLPXg406dY9NVNcr
EhrInQjJt/d1YjJ46fjcU9vM0xO46gJR4Z5CYiMvDehwtNel/P4FLw4J9gdwFESnYUu5p6Fm/b8T
VcJkm8dtD3l/fUMttirnd5Ta7X8BgzEG0L7EndjaMlyABS2G+vkW3OnUA68mMoKHzoG+iycr/zls
8YrxW6hwS1XKVh++HMB6RsYsWvTkj0XPR7YRuNJAvTfUTPS8woVNj9XpvL0NX/PilHiKBn/Bjpwh
jZnx0DG09t/dmisiXnYhdQERlOX0RGak62hlTa3Sarkerh2FJJEaNS2HiUxyuLtbylzjgns0tp2d
uGd48L0UK4h4bJqbaqfOganNJ6cRwel3MW3wXDS7At3B5ZntPZ0B3V1vK85/mAKBeUHBr7EusLHY
rFdGQXiVI7PxKYmE94Oje26nPzkH1XGtYu85J54vLGTyQDVIo8KkAL95LeBMZKNFzyef8qPJWvr+
A96a+/kae1/45DFKNTYXK21+FaoR/bqmZ0cOqXZFRHUMvQ81sm5pvptf1zhb9m7ajKm/LXOgYLR6
e0aafzzX1jIXrG98sCvhlRaNqeJqggmciC4xJB/mSJk5gdhQovzBwRLvmDyuYJQV7l0/ciseQ7gj
uQ0nlPFpOSBPHgg70CSTtA6JgZdSWyFJf+aavGyT2ZotImdSby1utvybw2T4AjKwiqw12VWXYMf6
8+Ya/pIF3vca87JOiNY/UQxmHW+A7wyN+GumdsNeQh9vY+Ga7WbCZSxcN96sXfk96zY1zssnfhhw
yehdGqvTMtoV6ql8prpqhXcVQx93Uwed/KRAkL4a34B/S+pxDg3i9JlON1UOKLYc5gEBF8nNm98T
twYOneM2OpR7yQnS+UOX2Vf//aCa830Z5d+iyXgctfWBK3rnYdaNhPeYgn77DprHWrZ70D13w+MB
AY4c6VekAb9DW+udx4u0CXxmK6d7aHWCmXYRmv6a+bZRZqv8pRDVqRmyqdKtc0WNhPWlWkeVEajq
c7vl1UuNkkoNm0prVIZxonnKYAzX555kFTxM8UgCKhFyi7j+9WuJNUtK2FfaGkhBaOxE4KtwkHXX
8pwKi3m6HvR9ULvfKYzaiBlOHMz6l0zj06W6GkRhQPSMy400XyHt6sp1VwnTa+WIzMrSUXQJ+AUf
NWJ8ufyUziHX+HK84lx7EVyeEEzq41pfSR1mG6P0k6MFmEE9wKzLhXoVylXi2djFVPjn4f6IwzaV
vdXIouyQSoKqvLfjtl3xF8hP1iItazJ6EhmrIzjk2Tyb47MSDHMI4qtQB1wrNtPPdFoKTyU1syH9
JOqUfms1WXG06e5sJU0t0iTxFOcigMrmlHC8Ea32/3ybrbb2OiDt8VC3sIXxTCxcPmRMzA3Hmrvj
+TQoydjzmLe7+GW7NKrAxhC5YRzTWoENsQlMktM8D1bTelM0PW8CcyoWZMUDTTzHil1VseNaj2/0
cpkGbrsBPalXzoiUGc1euZd3bgd/u+twSDJcpYYHIMFeN4vRzhx9OjSYuG30vS72CCtfq/qnhRyr
rNPI0EqNWrMTS82SfCqhbG7O4AU5M5PRHfKLwaKTC2ECPh1bUnz7MCp4LBw9ddAciLBFItAZVSYo
sTZ43rFXVr6go87Fdz7c9jv0QfiQdpd31t20UCfJdFlSokKR4kavta3t8lVUMfg82hJ7kKFF1Yew
bKgqkuGmppn3gHGneWBt0pAsc1zy10Zff40XENkovWQgJLSRcvmgLzizHjeYix0wbgFL02weenoa
4SPNMeX5M7JUx5sMWWe5v3YyAXZ6x+j1Dlwy2jCd5WU8fOwrlFhMObTfxY+tL/gyMQ/93k8SWjcS
I6jgvhfuMQ7mQ4k2jB/afoJLN/kCGv8/53GrK1BdiH/XSwaFhfbxlDPQm3JS3hr3Vnk2nzd9rtSu
bCryPh42YEG8wjcjmH92FwfoG7tY8pwmpK4wHf3I6VSlLPS6a+jPHei6dSBRju4j17rRWQtnnfHl
mahXd9zQ14Iohtaazl8fY+eRoZy7aUenVCkIEoRPIQe+doaYF0nNbqhfVOg/OZMU3RHKN69FBySQ
F1iY3oemrkcNz5Gad86LxLM2FFbcu0roOesc8J/RcHvD4oZJqVfUZZfdc5wPE7H8bO4RL+GbBVPj
OE+27MM4p7kJHUw2OH4MUFzyMCDwyskbXrrtM4bp8nIs6YTt6MTh/dR1sCox5UPxxlgwCmLgFwUL
lr6yYeGZ1rCm/UiBjcYtU32C+2OVH0pvKSoP/rlclesu90Y9dmegtXabBLL//I1zQ9NPEg7VPhyn
1a4OzEirSWipwxwbzdztwhcdmXBnX2Fwb7nJ1A03aNOmV0Muw9uZVSVFNsvFAGCtLBn4VPveUcSW
aRLv2xSoD+5waZTWUKgq1MDE+bIcGPmYFkGHPVNDO04U/FgSt0sXjabh3dyedco52HbUuX+emCYe
EzOfFxBZXAP7SOf41p1kcmcWV4J9LBQ+wc6diOJeaxTwc+TJTUpFjXQ63pFAc9JD9xzhjLllQt2Y
jtsk0PMGtKwkzw9a73xiFYqxJbf0EPaWm0vSopa+lFBRHI+Nd1LkzXU/slboeAnNE4vL1uj2S1en
tjMTTZMIY4Jij3Myprd86xLGyAscSLsF8AkXZxvIgxlXWQHumEN7uc7vcYuy3tPNY1KkPH2cl1aV
uZekgI2U0/20Ddy7IfNVeLjynqjTbriD5wNb+6hLz9ToxJLj20dUk0JXn86WNb+VEQvNV+cOGwne
pXPMX/I7eSG6Nl6JupeRSNgGguRENHT5HA6xj9BgS8Pbvj0uj1l/F+aDzSfu9rLT6ITZEuI1K/K0
8DJebr8EzhYYrNyrd3rnLm1cRvU2u6KTgE4hNWet1sbtEzDnJj5avVAb8l7rvrJVfE4mvgUXxT0g
Ao8XQroIxCVo87rUFGJbp3i7lu/G+4DBykRqrml92dAZlYLH5sGIL4ndrcc/k7Whjrg/NXwnQsiD
1K50j7dA/D1Ug90t+XV/SOgcUt1B7D10fGqQDHfJbgYtV2CJ308hB3dnBrsDJHR3hcM4Wnlx46lP
iJA81tMWee7LRaMaEtSk070b3Hej+mq4jktzKBCOt5U+F8R3Cvx+k/3eliAgdfjjz13JhK3KI4Lv
h+7oHCCNSJxLdTtrACrjVgjAJrTDbX+JDT36HlDGfO3G0I+lJhv5479jJTtK6RfVXIme9wpVtr+R
tLVTsw2TUcOqJPvaw0IEXPxPO6ikUDNgfCpKyOpC93AihfOyGLxIMOIpq/gx5vGxur1pvHoWAray
ApPrfZnCpqxVEJL+qAGuIIATNFXVaqPwml62NPO0TWNccq0lPD2W1dtlKfE8bVQEVex5hqQzhxtr
uyb9pfyEIA9vo0BqwMgFEGZq0phdoWpSG90ie3OkGQxHB2S9n1Eqjnj2V5r6NCUfPX3cH8t/h8zE
V3Ke+13kH1bgMc+aSGKBuRR25WIfnYKaWI1XkDV3UdSXVEmS81wY/SQEkBUCF+ibZR3o4lBNdnoi
YPy17VI7rSB4ZkPYhWsTIYljhG+kZMcvAHa4+6V5hACjCEQnDfaWU+hMDai/7zzKmadbVEzJO9rQ
cSzma7IR7fQCvBiFmSFGvnyHCBLJ5F1hSis66l2piNW435WqLHLbuNZPLJkKVuosYOtMrLJoepcv
+i6CqRDLMMAmR0jRoBlho1Tgi6YGRlf6LNgAiSNc9dFcnvK7zrLxsdp8Ogip0PJJfudX147uFrbt
Bn8eyrhyqW2coYer/AJjwun0AleAv9xOvSr+ZTY3Bo+c3HB03UglkGhnOwz4dGmQjJmsUMYlETQM
o6iEPmL63dJJZl+rKe+a9VH2PnHhDauV3nILSOVY7OEMrgwflglnVQzrIsCDVEdJr11JPiTwQtGv
G3GF60E9DhHICgllE47N4LYVOHl4o4RUsNmjIzs0SCqd9Yw+F0fuy0xzjH7e8g1m7FLLCniHVsaZ
E26KbPwz7q/C77P3zPJ+U+ptNbrCALY5Z5ya8nwGSvKlX/02gjw7TIEYdpoPZ4NyWSs2ygpY1+aI
l/F0mYLNn6Ay6xK5FNQPoinPPgkLvkDugaWmhy+MMiB7c0YYGTyE58EeV0ieRcFwHapV5J/ZO6ly
Z/XRyajzTzuenlNuqo+Tx1MZ6iUlrN7th5Yqlur0UXZhIllCYlr6wMvJtErXPNOms3hUmDozuuXk
a+F4+tq0k8jF18JNAXJX4dEeZD0ljNdhf5byKOx67Kc1K9Co+fNamjJMo5yKUsyr7TGjiOGOlM6X
LV+hE9QfyLER7gZC2pmS2yzXKwgCGmCYvzyokzR2n/QFKhIX1MQgTpGqvul4sNDrdTVTdv3f4rMG
mFM7iZkCgIQcTpQ2JfbswFOcaf+ZslunC/WoEB1R8JUFWTn5mHEMR2pNT8uscn8CDaqfyuL/T031
J7EG5448YuUmzwWDzzz0+SR6RwrDRuEzhOFctxVMGBDMODQRZVdP8lQ8/ftSMn9+s/AJ2ETwc8kO
dgVpNvEofGoXO2mptujvUsoxqOnMv5eMC8m8lLrZnkaREghrYdx7yjb10YiFLqZfl+FuHUV2s2AY
PnzCxLZUgJig0uqiRE2SJh/FgAeEzd1Du9Ic+/X5Rc17q8/PfpOwIBL3UW3fThm2mc7XZai0CaxB
a/Ln+bp3NHkDQSGMzKSyq/Fu6f7A28grsunf6+QIAa7Csx0InioqVLRXHzsWP4LoU7l8TAgwTc5k
CMk7zBADj8JNRFcQdJFI3+w0/OxHaNgwBXzknMApjTAvPkH398nm7E9LbUflrg+2P5swV/AEl2Ds
jrnP/9r3cUyqlydUpA4ZT7Ww9u3sXGlQZ0Fin4dECwU2VbVIVdRlz1ClRE1mLGNBxeAHFoMk8UAN
08HS8sLcf3/8SlxTVJrT3/Zwp0uLXYTkEdakYwE2yAr2kv2RYTh3pVadPiCssi516u1lldbiWPed
JP9QPBKVfw4JC2eCniCuI7jdo+x5qD19HMB4a/xJ7pqUiOtxz3N0TpMHKue24NP0du6/wZNKX0bl
TXnSpv2MOg6sKvCxZ8e3CgKU7Pw6Yymzj7IZThYjmWMgS+3zwrCcZDNtKTm9JCDJVDAgG8fPTz+4
bJQOrrxL+K9BSIIGgtZVrvmhr3FPabzPFDm4XjIm24c3Fi2jethM6OMJCCX0yo+SieuasKyJuail
wFtRB67oS1RAQTMDvvdert5v1be/u6kYqvBBi6kqvqkhT5xL8minxcDUjr9eB7Wg2ddcJKkaGwHb
R7ZEGSj+YheMYiEPANcVEzWXw4yMxRWEJQjenGIYVYiR4mXakcYn/DWsrlJ7EKF2TwSvmogiFBru
Jum3NqGQSmRh2UEXsolohSRjTEoeANP5/JsYFWBBph4WnJRlzZAiHOMquoClStpH0uDzvWdMJWJU
fKUa6sdqBFjwCUp4Hppha1wCpEFpIylN+Y0ywXFwRdCCuvLT68gF1+Sn6iOEhlI2/ryQ0HqFNixO
DfLp+bTO8JNSYCpOs/NjzXBMJcg8NB9iQtVmB5ENUxw51FR18FVafmzrywhTPn+bU5m7WOd+rF3M
W72pMCpRIBvxngbAXksJBc7YfRJC0oZVZGtPyjEuQbCsMJZbIdbNazhHx/RsiFqWQ7xv/WkUV6qb
TqUxqsOyM+y44iyEJusD0Ia011B6gKy9jDPQqyHSJDFFM5OzhZ5yMKyZrfCqEnT5H3HIyLlHl4JN
tKjbyaUEh6fpHZWjaExJQf2wG3dvXK47044i3uFsb/uv0Ah4WMlx8fin7/1mAAL1MKBfTMcF3ipL
8ObhmLJa6M/pVeXQ9S0ufn4EqeX4ET3Sfkzk7HCa4JeHG1Ma338swx05g3Pupwl8QSBG3nOIPQCO
taY2N3WoMqZ2LeO6sYwc560vAX6CpQT1ojo1e5EF3CaepZnsAi8OvoCHzTTa1OKrlg0vKdl2gn0N
6VRURvQT3oeZl7bbDFEnR+nHP0pGcJqQiLWtgdCOhgwMGyra9kzFOMoX4gMjJ/xknGN8RUQDdsgR
tlBJQX4cZ5cQ/eXOuDQmVKRg2iSy71mMuAiDANn7GnMBOrMS+XsadblpmMTZmgx6ALb1uYQmVuzA
2kQGYHKLcjaJ2qQjPx16b7QoJn3wdT+cCCBDMcEqjaeaNk0r/yFiPWkKW5VIZgxOKvKDwdW76+js
8YWlG8NzAR+2d8mqhjDLgn4XnJka8TZZ0wnT7MRfu9/eOCLi03jyoAvku7azEV6eTSTRC8ea9OcC
JEqxzsj7fA2+RIi7Y7cAy3t5B5DLa8XYoVVHpu0nN71V05Z1pKl2BtdzfqmywMkl8AlL9MWYzpnJ
4G6Z46efAQ42qoBW3HzJBJy16i6eDb/0ipIMgGFSlOsfKPgNeBG+e2oPcRSSfTmFaOgMP2lb41Hi
CjZXjC00+2e+xDTq8wtr3LtHo1DzIXG4s563FJBQ0eC+FsKpqW7vR2lLUU9semDzxiQ9+/h8XEZW
+1F4ozr+TANFHlFeB9XhO0aHGfSy6+92pot3L6rJrNpPWtX+JD46+OqRXDhXosWy9TKPzK6sISEV
DB7EF+/Zq3hlK4Fv1T1jQffRjwCjAKjnGL1Bg/1U5ru+wsUQoMh9MTJfEtJhC/f/A/FrAf2RrtHB
vKxgUUqJrRh67dWehHyybsJmCWITiYJd6dZ9KLsK8MezIgxOLjPNYvy6taGoOKCMEOyTn/9Az4Gw
FesvAD6ksFNXaL8TZtVVu9k+DW85lwhiKtWhZjhexX3Rl9pRuf0JhUNVpCY2+OpPWFHi8S7mipF5
iq0uUmgvYy6mynv/GORuLSJvv1W212AUzXwuPAqRrJe4I7MhC26ADz0gCsr0o/fFXhGwaa67Vrj3
S7gq16JEgJj+6N2Gr65KdnAE4haWEZgvAY897SYeog9IN6pZWUOK7r46OWsk9M1b++VORAkW3S3/
LtD5l3YTI5632ndpt1jxL+FAMNUNorJuIVF8Ldd7BcTCTFUIncVjCBJM5frDtyxJypCnna8kEZuo
cGkKHCPARE8ZB0Du7j+rcWRBE/Su6sFWrV7eoeMpj47LujdJ2Af7s44uILOhLfvE8SA+WA8sEwLk
6Fid90EnQhwnfp11bnu2dWJBKZn43A62s9Q5I56Ez6vpGA1ErjZc0tYCl8MnbKly+GcM0XGXAZYw
W4v67ekEBAW1os1LDpNb3xs0XmKQCYtF3DRu5LxnKAMqWR0oI5dSupBbbYhlI2Dow5XauFSUlLDB
6F6ZEG2mlpNlxiYdQQpNH8s0eEVu2GZCIONkthtw4vQh6t4neK3zTZK2EFiWvoYXymLSf1pqQ5oB
7QKQ6EPVzDtw+kYR/8pATeUOPdAupYYIIx2L4RrL0koQm1bWd2XLbJI54gPYa4S8EqFvIjzXBCqR
t4W+wYiNVlJ53flmgYEc8s76LvS5iN0LuvCDgmVfvCaO4ZdemaluBdYGbwmamWMeTLv+NXFSwMhT
QckrggqO5emT4fa6NzlRFE5Q4jAHm0LrLJdfmbX9kFRC9R32eXlELAnpu4myVHv/DhVCTLu6hSUA
M52eRLXfKD4m81i32g4yHSlW/7HSUAa4ys4fu1FCmGOfrP3Gaz05D1qJttqpToG+6q/7N6wCdBVW
4DVkbnvxeDAVOCXs3wNd19nyNdBqXRY8LcPMXs948tD8cxTapF5gdSleBQwdynACqgJVxJsO/EaG
DGRiaxRKc6HAVWruZ7Qwy+7GYwyJetVQ3Waq6G0pXouj0spDg5cWAA724wNlX9cbzJlsQt1HQeTP
vDUgTwzcaCcuOHoWxysmbsAZUraQK6zmSSrFItjYuyQcJe71fBlkPusB8apU1gZctpNmOp7CVG2j
p8sQmPOZKuX+pCd/pmqLCgDFpwoJRACzbVvdZ7CoeRU0sle6wognSI8peM3uICH9Lj3pQcfkVAI5
dhrNyfUz+Eay+pQiBfq0T0N1FRfhZU1BSDoz/97GaKx7JU7sxPpDPiYS49KleaOfy/j9HhN6YpsW
Kh/QPMRtL5DFtrmDMBiobpWh5OukCNOqM8blOkcm94gimjgzwQgakX8hWOAE9NsFLvxvbbDFvrOo
RMWuIfhoHB48KmHDgRutWU93b540vpwPGPgL3VAh6gfORTZAZhlRMMm9tsuVq7ugpOP6ZwMWIhHv
sVF+I7NowjUw81R6s/BS4WA69ILSEa4i6lwqIL+dzNGCLJtkCHK+6Xkn4aj1scYRNJPMJOymu1LV
nMQ3ssNy26yo6RQoxgcUdfgDM15Pr3HZusYuXpGenlrbDx0TAYpu1/zhnaC+frjPQDOXlxzI9nUR
s5/PIctRIfgl5MiZniMoSVGM28DKKyaX0WWJMb1sSmC6dyZjXCXFYzOp9gOjWb8Z/tnCplMsf85n
t/YeITStYNwqfyjYR64UANz9U6X+5gSMRomxRHD7sDz3ykaaAeip/kWoqGea+9fOXGzJAYlmXMo7
p1DSYXD5ziTGnx+GO9pRx1RSyI1T6+/Vi+bovBp6ldae1r4O9vEO3bDPVDmffL++er5iv0qco70F
h7qyPIHJtCxl7/ySLvB/BgMK8YO3cN2Raqygeg1Cjd8uSbkAYkCR4/SOM2Z1B4YHOYi5fxzPemP+
ssI1/VHS6raj33247fQHKIO8hr4QOjuVk6yiqR2mFu2U8smbR+M/fpW7OvM6ZLpkIQaCu6OkKF8x
f3ywmuHcJq7XBbwuG97jLqVfD/2bF0tBFMFow4tdnKMLu4pt0ekah/1vLq2tflmfHO3Vg6BFhTMk
aEz8UEtF7+1veH79QOpzeDh1tkmxEVLZW0GPpwMsd/BaEPIjfFl9+3ktAk7RD93ctP6nrKSeWVp9
R+9hWnsh9ymNlQR0s6i3NShb0IDampKCzrFccip1dnMIetYAzWnKwjfdx1Trnjoh+TSqp7oepTVq
qNkQhrgG5SHYBh9s+RnkIThyY7cS3pJiI4oVsJ0z8VA51sn4ij+BLzJN0kVuUly701r4B/8Imxm8
rEzH1KobhBUCRm4ifJs0i793Wjq/0ZwDjtRAAxp+Yvp6gPm+Z3DGfN3qZW3arG89ouBSNUT0WUjI
CHX/zPIwh+mV9UF07WUxd+lEWOkHoKD0RbHlCIEYmo2RNq+W7k1ysaAF+uJ3NKnbro5eavJQ7q80
rr1lwdNRMAc0BS8lAd2FrEevATaysGi9Dd+w91NSi9iAyWsRc3HUwH2baNm0IkXZs+3R0qSNxJ3+
rRZVozvaZoTo8FMikds3gJs2QiX+f5p2QUDpysiPhMDpEDhvW9gPsSpLzc9rV3i8nwf4IkP9tQbg
hNDY+tahIWgn2Us8A+X3fYHAsApg2wpuigyucQIDJ2g3jw5YiwDttYv7zsuAyru3RtAbl7wBGLMw
b8VZZH597WJ/dG9JVkm5CZjihhSTiGzUKAW2GRpjiWGBBow6rIKf498c/0oMQ3kobvzN//mdwSg/
rJP2sRJYO6+TDOZsB035pNcFglOEoPYHxmKhi92KY3XEK3i/Yg5uzkfW8MqRgWdH6+UEV+g299QO
dEwVwYoNK/5fqh8A10o7vTDaDqesL1hwc9FgQv/As0n7sD151N8XL4vkFbAySG5LKlgod8AKOJam
HdwKkvOJPau1Yx8SYVSZ2Em5Ef1rALEZtR4BqRaIxYlrPLTupqQvnSmsnH6W5v23dg+I95COtde8
AaDdo27zAFGwC7HCNrZxX8P1TpR7lctn+u2WdBdmdUXpZvzXNAJ9+VF+eNYApTADem3zqejecITp
EpDNcCSYcSw6Ujw0L7iEUR6uozcea8p/NsaaDOzyZIdXMQS23xNTc7YcU/j1BJCCQvdXGxl0GeBE
STJ6hp8QVtCNrnMB+x+qki+sVkzSbq66SuB5d7qOUIVzDsNMvxoIHxET8j6uBdg8FVrbqvIVXH2b
+Ydy4EeOiDhe5QK8EjFDHUJb656CJ1Txlsp0suFw4QDm0Rwiz0agPCjpAIAEJIhk8WL1tNHNcc2n
zP0ZCwivabuP4zs9n1jYgJvpAiO9ibEu10H34wVbI8hy2tFW1Zj0iafZGbVcXx/byB5jKJ6imPc9
6KB5b8kGJpkT/LwpJ4WMIKNaI/XOoENJZDRVP7RM1trEuZ8fH/7wsfja3dF8NU77Hi4QYQ5by5zs
gZWGhGR1fy66cD8zmPAV23jv1xeTqcZ052rayPyGqmAMBZ9f5v88uyXY8ebmxvEprBek6gj1cPKl
tZ7bAoBypfgUpalxGKxC3TdhmRNElkuitFSXt3xPLfvTZ6GKEpImiI8G0LYIwhyhh9eGn0wbOSpY
ntDoFVAyz9PKzZLXQlSxhOMrIdLlspCJTVTwG9iClEXsob2/Z7yd3Htv1ZlccBa/zI2PAbLqq+d0
FHfzcCaUsr8w2AT5es1OKCcSxziSFu9T1PmvJYD7kGzZXDKhvx0s+INvjtzM8NW/HGfl0lAvNq3M
HcaFblYIWRJqpc5bTX8ziVHmDazti3lCx0JcKEprlosHFgulmJyfUN3DJXfAcPfpVySmgdWY51TK
X4ZAlbL0TE8JbC4QxH4t4wr8G3H7eqj0wsdnYd+nSt3KgH6D61qQR/oA4BGA9dH/o15Yt74gMzuq
Fq4YumGuTTUb1KBfDUnEc5H6Ti7S3xqisuaJUe0DmEHSUbRfYD0jcyJUA22ybEmCYiLH+fsRTMsY
iPSJU6OFThU8mCdpOrxW9ZY71ZHR8Pu+pPb/vxiOnTVRaHnEUn12HZA0A1rK4BptQB3ZdSSRK7bG
hLD5eaUHwLHoaXcm20+nrxKQZ3zJlcZ7ZmF8FmAjG5ctZBiWWaxrUBpjaKSqrxGGhpdLlFaSfT8d
ODcbkvb136O+neuNDRKv13Ojqz4tgcOpNy2wlSBPRqWHCfZwB/QpDlefLANGnX24upLP3U9DLr+T
/cMvWVhXAvek/wOiGJGPLJ37D5lCqUo0KDbswugRJiw+l3a7fZ2eK45Spzh+C4H2Y86fx0909oAT
KmuCeptzl8wE+6iEgaUzn2c/juiiKzUlOaz8Eg9IrQKD6PMD6+Zkv+b7VxuOVkR/GiZRr52eRbFk
JQVEIC83QJ+uk32/B9DaYok84fJMs897xupxDr1aC6Z5B5IzTXMeDHm4wxDprC+NcSdXEi81IuG5
q0xgPrMFksgSG8uwH1Ggi5JAkkHWedR9nDH5p8KRJX30XcSS3dFl0ALthIYuyDb03RqaWN3OoeaJ
aD5YakbP1myqynuuEDYpVZzQbyPmvTKdf/PqMe2AeZ+DF+S7AoR3pTG688Y5HuuvO7vPTtELrcko
tQ0miS7Ss/87QCmDphU3VWuV/XanOXHnGEAvcn7H/PDin4sxVNvFnlo5Dx4iCG76Nz+RgLpdTYRc
BSPrKVdghwXAYhY19DWVzJ0/nbiiP2at24AqOSTK8ME89s9yODJSgT8f9KrSWYVQHyiumztzLa6R
ed/k4dkqnqp0u0FZ9qGoSQk45aiOS8EhTdXqCIOQDvu6yeBRDxhbcx18s9EmpYRQfXh/jvnLZHA3
xZHN/mdo3uMjnd90hSmc4ooHSu8GXn6JzOidWQECK1lkDtR2BKikArS/GaNwG4ZvMIPSMi83N5Af
AgFEEqFXRXzHtgFGJGBLjAi34ywWYt3A9sKriBHMe7G3ic88TtAnK84sw0uRLk7a8q23tCYZUujG
7t9xbuv7V2eWoMTwZZLWcGJJObxHFsFkGDa63pXhDtJTBCZe2gYgRPRdjrOIiNN+PM4dSqZnZnEo
2X+Q06RbFgdV+wYrGBtQTzLz91J0NZDj5XL0aEpR4n/NzsdSd9PqicumyHzWYSLQJuYsXSHFCf0V
A20NFs0OpWkHvkJmUQVDfhajRhlKTamaHOJVNjdGIjdVL8WjBNxQJCql/4clSab4xWGaxsqm2SnR
2JsWjayReUPJOsuqm7luHVTMzoKc9QuvoM34NVT5XzOXYPrHDUTfurnqnTI0G6ggFUOkQKe6LPkx
KQov996xz/vxMJO1jzHpjOVCUVh8mSndI27M20qLtukL3C98igXjOe3M4+vAKXIctu4M/fFZd1Oc
za09RK5B+d+zgTwQEIPLA0G5sOfJgXI0YAru5gzCv+bb8BEm+rW8LT/ybUa49SF1KGSbxDLJiae0
NXNDWx6v/Ot7WhscKLZxZFkh7uLqtU7reCGDSsEert8WFfjLY+9QVE4oROvuW6OucZJccqp9FG4v
Uk73jvi8DvXL3dRqs+WFebkNUZMn5iUUlAbiagNPFo/oaZz6SMBUkoxGDFvKA9D0plAfNdOGUa7X
iL78IXWfMrSLup2PfeTaNrgzKwGz5KUo2kUbglAnKfiTkKzKT4PhL2ycbtsqjUetgop5bPUN2Icl
+yqu8GOHLC4++2SvZh7XFC1FEzJRbK6TFgNpfzFmCK61tnbGtrWBlCidT4R4TU1M1DMfO9cfjr4K
eTQR/f9v1s4q7Ih6TeB5vonYu82ZTXWfTVoPFTI2wwwzFr5NHmU7DM+UAUR77NkSh17K82pGJYOE
WqhbAYWJFRaUX0Ew3wOHrU+oqQnJ3Zq1954VzCWBn3PsWcO6qgljdxE/d1hkEsMMyX79FKQpwptN
oy3bcuW5EaPIlh0TuZtIhx6JPlEOExyzNzbdod4g5JELfzgRAfgHXcevfaC1UpPZ25EdOi+qTdwS
4MTiyMdEu3WCui0pgcPnASmGEVMIaAYvuRERw0wD/ueZqdZU8JKykJeb5EVLODYaPb+iJXsujSRV
Pi4A4o0pL7a3BGvrpOCT/c+GdSJsO7Wd0yfQXbI6DWqBtDjl9F1DU4++F2pfX0MdKKQsbXRwAouv
vSbqJe+Jo4fS7BhLzUCI/NPhYkW6V597BH4inX5SGcCRS3hE7Lmh17ZP0Yk1/cZtBpQapUXPDxDn
JVQuslkHjkyDuDrrAogGWZy5BmB+sVK8ZeaXcdEztaKA3DYGXB55I1cKMgzvjqrTuw9k3V7dML0g
yPTQnS/6bY1EwcVuJqhMNi87rGnNsJhFTtxvea2H3435GpmYuuS6NLztcBSXLM5b38K+/dcGGfHF
OVghMNEOGXVCOP0z/tM9Oe4cMN6LwY9SkPbIOPeYqFYQSb1gFY5Nx8N8Le8r66DhimmQwj9BO/xL
bs2eur+M3vvrVyMOk/4JqaVdqY6QIFtoSwbRLPKf8WY+YOYvnpR1Fc+NG32iYHv0oKuNDHBwkJYT
uANxHyX+dyEOm3s5XEQgGCgcSrVRLi14l8rZ2uWT7bGupgxkzl72lXWW51/mKn3VL21H9+GazGj+
rmymhaRcDMbWSpZh4Ecx0RhLrMbo3fPTz+RJHkqMg7bL9a10KziNP3Fgtf6pvAOCsq2tpoCkX/Of
oWMbNq1oO48YvQLcbx+YOBAhOr1PVcmxS71S9L+yndUFoBBbdPO5kdz3DtXkkPxJ1GOfr2EKWT0e
/yOEGfV6/fLexbCY5LKCbVCgpFW9W8JEKf86IkJPKNedogiW0jM/l0Rq37ThvoSfRR6nCVw1G7kY
aGyuQSsApNbFpN3ybHOWRtpiGkFlYpzOFBnMaW12gSehOWG6IacbNjDWCBoyCBkiYbtWmubYNThW
+3CZaUnimTIZz/UgOLZ823JFwLCpxGS3IRf7+4unA58s5FppSMKdcmCslOrMG1XVlT0/377+ytkK
WtbXY9qkSILpb7i4EPVsQBc+5Ty+7E6InPQQe4c3tIT7ZOyI9l67PrZ0iDS+vypiqT8IiCPSAOJO
eVsVVlsFKHeXOIyuUc1SG9yD8kmT47e1Hc73LYaVaMLGZqsXelbjFfPKLefhxuuio48akHMjfMw5
ymKThEDjQ5iV611xWUYGKzgy+PC4ex3i60FUxd+n+JzNMD82mwEtpZr/u/GiF3rDcjjgL9hSt9Dp
qcSEJA2uhq7yMnaZ/z3zaKtxf0fOJ9YR//HVADc2v/rEgDdUXuBlsXdlVzfna2iR6jgj0OsmGbog
9GFcNJR4u3Xh881ikQTJ7USCwklpndeWiUo2AXUkHs0qu4F+r7pjzGzcHSwRJHqXLblK1TxNJdZ3
ie76AKFeERrCo7UOT/zDCwgKSSCKeCf+1prKKp3pesblfD6Ezqvf0jRSEEm8FtfgHhIBIu66zgxw
17/xtkj4xraa3OU1HRn4ON2k3OQKLHlAtgDDMdcpdQB9ErMxsGzKbsnPCUnOg0QhCpr1rXd/crve
/rfqaMjs3I1RFr8Peto2ornnW6xmV1LMhhIEDJA1wyMmUnkGjgEeH2Bbhw8Xi4BoFtsoz0j4zVm4
JbrLQGRKfsv2RP+n58qALz3PcAGe1IkLk1yO+7QevMfTQuMG0TXsND36dyviylRGEBpZiCz7qGxn
ZXwTkvGXBGIJMVTaQqSIUq7LBFhqNblHue3jhaMx5/hWKJzpjzKN3XZO/k4JXXMR5+yNnpFMzPdr
1aU7aUJx3VX52cu7j6IhaVPFo9bUkHV3wQuSIHuYFbXjBfnzoHDENIb3Jx31xL/wqqf1cFxLWsPv
q1SfAAx+cnVUAYyWCf9P1nj2zc+liTp0MJ46zAc7vkd4RDBDDvakYbwdSri+erR+/Kgukm2YTumC
IKtOTbrsE++TI+QpSlPlEZPdHT2hRwzXWNlPeX9M+2aqKjIE+LP57Ucblj2BlP4tCSHQkgnG7H3t
qqIx8atXonkriuodu+H3IVIDP/SMcvkrSu3BxfjTXyJkjWf2v4eL1AEzqurnikLkpHbO0nD0wh0J
dGZJXsrk68TXCIRVXcV1sta9SmjkgGOeZ/miqqfuv61FxO0FSSjCiUZAHjX01JvBtRP1gEwCvVaJ
Sq5mxlqafi1tb255/hzp+Ke+9LHx798tzcugxHvQFWSpKpUYMPl2z4Dnoa0BGWP0QDxZMtV3pjCa
BdJikRiUeuAKVrw114yxEzk30mAB3ekf6yqb0cB85kjYLzPiHR5BtmydINFES1Gp0eCKqX2b+GAa
9RSq5peutQRXfzV6VLKdt2HrsHs3l85Hiji6ZMbZtnsia4Tj5aetsFCw4pStzps3KEJqZ3djdoIf
UYIBU6EhsvyuK1npzwLWTvEEpMjrRvmlg3P+zdgAuze9tyxjPxcwxoFTW4ePlKyzniJpTiECtD8F
ehO+xyTfzlM/z7N0neYdt61ANqiYv/STusr9ffooLQi4Ye0A42kJyb7rokfzAYB11imET+Pi3wrP
YCHy2IMx+q9mrKnmWF/d19Vfm92sLrhbSGz21eIMtJBZoOgeijOmhOZK2aVScvy2tzadI9nlppid
goRd957C80eBgPd5jFNiURgyYG3QE27s3pv3XzFze5YJhbiKm1KmZvOnhg/wWrJjXs+GQ3Pc25x4
gjvc87zsPx2dNmYhvirsXSqpxNbCKWnGTdCmby2ucDDVXzXFdkv1QFXgzotgexSu6gmdxucA4GNB
BP8L2rNGTHQUMTm2duzxvROHZ2iUzk4vKMCyy1z/rSKRl1DHZ6VrJhqEVfqYWa6Xm4WhyFZ/08O/
BpuiCRVXagsdGnHcNLpTs7GbVjRx0LGyeKgcE6BmkIDta76mjTHrXx+CIHi5WbFQ632HYC0Z977s
tadFuIkAY+nJaIkTx67Zv+gULYmG5uqGQyPOZWnAEXH5+Vf270jht4s7hlm08Nl4s+J1C+vfLMLQ
3SzwD26VFeH4ExN5pi8HHPe8p112Uskz7BmYO8vZJYvS+egF0YSgPbvLrtWj/NQ9ppZkpGR+2p+L
c+dRmPLTj0HYfeHSFTiUndswZ/e3rQaTfW6P5ziGzfcg0Bn1MfIS0NFI8yzOF3Xd9mvG+QotT0Dn
8aTCQICNonI5r6i67WPrZAU+QQBh+4WOyGzswc1xpS4XmJkRg/mqiMBAADYwaBdPrdBoeomqcKAn
z/+xvhSM3e5VqMp4Wnev8OUsEPzJH1DPoNrOq+cWYgqIGSzIFIXTk1AQsVuIzimVa2qtGj7jVtTU
pZ7nUL3FcehQonUcpWNas/E8CDEMqmh16YCAcK78jV23Qh5Qgz7GKpnWCRhF/N+UIjonDRUBrR4Y
eBaSB9wVlKcCdKtYr9N5b6+5pLwRBUQHcDNKuGatpwPCAIqE+Q4GohqJpMybktD7p4gJVIWlAAcI
gIq3Y04zyUyLyCQSzqafDArXUt2HYzd8F+no7w2tmWrFOfmWTetVKCvtDe8fPvP+G7nP18HcNYcU
0iJ5IXz+frzfmnyIE12BCNIT8oc2vKL1v8qw6wZAvXQBL8Ona7dlML58xVnPWp7ksyvYyxGhP7Ko
zxJQQGZc5BU851j+uKepBxjEtB2NbVbDlNlLDdMinoRsOIicsqCTKgsQH0PesUSyWAHpqyq41XeA
JaBQSW+1lMFj9Qj9Zmxz6oR4A/ieaFhnl+gzCkfGaJ4VRi45NZ47NjXAjOVXI4qbIf8zClxWoyMT
VseuzR2h8thfHCsNbo0cJNLN7FEPWJHz8N/vMF1aBapFngBALg7tTLVYhXIkESnUoRW0zD+rMfwU
AMq2Pwh78VtlvDq4I8lnoNCY+spaOvfDYLCxasOghla8Mkq0yNDbKP/HsRnhzZeZzRhQqy1pkQU6
uL6iL9LiAr1eRMY8LtRdo+i7dDtrot8d8sXHlTn7tgSIFTcw4BA++AHuF5J/W5XX1nT6aL6VsaK3
1M1mLMPPr9ippOKmrSRByQ4/HpT6ZZgppVjtsTNiB4tpbsWTfIbJVygpiEDIEIblQhHsK1FenHbT
qBA4022d4mPNyVznyzZM1aYEVG+RgdMoWhVr8CULqlHMMsg8h/+v+sOgllY6ao3X1M1RpqJUdLmU
vwXXB8rpnbvnxOPrO9Fp0aYHDfCYFkmcgTi8auNLANrJuqzIjxnWNtp5V7Xver5RFRQUqavq+eGi
4Mk3zeeVO4kbzG2qBNHXXmP1Avr1OmDHd9EGsJhJGj7C53KBI3PoP28FdD8fA9ufhOAedXepfrkq
fvLC89vbQZXNbdaIlNcaZHmMIF2B7Vw12JsR5A4WeY9zs29zUGInzxFncbR8hsH5T1LqXN0AlvV1
s+lH/NdAQxv5wd68vdcK/1i0yRNGzXsvpJfS3x9ebHq+9AwojT13yunH+HTw+bB5fwzo7Tr89JoL
++Xb5Wqw6MqiMouwR+UJ+g2ry/ARqL2G+5HGlPAjkRqWIS4cOw0kZONBOKK5faTJYRA7KDZEWKWr
E4ByaKBPrDnzdRuf4WLyiaQgW/OiBQWYcvYP0FVBXAFgPt0ySiZDqpum6BmyQ4te6NNddHLStcKE
bkYJmALHkergtO+Blio0YmR23aBXNaX75APDQCktnb7dJwBSxNZ12QpwET2MAE9bjfqdhefBOlPu
kAbdyFbW6ilLbBIsecDhRcQbYEpOikCelluSmhzQIg89kYFhxw1q6y1AKndR7AhLDCSUUJlX4xj9
wQEkQRg8cgq++PQ+4RGBh2hrIJWrzu+wA8k3T3NILKLyVCUyb4y8O4lmxk/qAdPE9Waya+yzw8Hy
O2rJ3qHMiQc4exr55pm22MzzTImKx9HcPheH2r0Yk7i815ClM5dAIBh8EJFr6jMyy0AzjYBmfCnB
XVKDTrMTrdhIiHPv4Efz6t3gJePGbi9dn68DveFdrFkmT6bAT5c+2O+1qoa5ZPAYRBI8833M/auU
oCtw8tEYmCEVifks1z6eSdfYkb67apQcpPZzH5olmrXHGx06X2Ygguvq2Ug/5zmMlNec6ZPpplVx
GaD+XjBdB3o0NgtJPNYx7FA8IinaoFhrRgrBomQISvokITqZXXe50cynOYJyRlTR3ZW069QvirDp
TwQrYsJ1EQsm0mIvtWVkvb7zHmOYuuB8JgTOf6wFSB1+A+LgiN9bfYV+3kF+Hl3DJQcR8Sk6SIbZ
rUIdAoW8VOflOaOJ0k66KoXPN95jDXFmLNTY6A1u0LCbxloWHtPmtmxB0Ar/eAVwi7rfQ1U6+bww
rdW9BjtDnHL9EgaX2k2dWDQkulkGzBSePCAJecXhRjBviM6srkaWxaoaJu9mReSHT5pAkeABUMdX
gdYoT73Jvfvc6M5zk1fMrzi21+0b/NTdFnhMz2ACyOcsAzucyC/8fEPeC+vRQRsJV5UMPw0z0iyR
/z1t1fY1SH1TjOqeIu1/lRgGP/TM3tZLWTsalIW1GRLWYFjowvE5G/dzEquiH8xMK2ikewoZWO2s
aeQm00/C2Ys/dkj05jo+Cz7dAO/HHUrbNqxzHfP8AqSDYHZGqxdsnTfpELoY7QJD5TAKBFQHkvcm
b62Tyg/A2fvd72QX1c8VpsS1VM7eoKqg4UBkSwqwTr3lwqy6uSU7ihRpRli7nsTIJOWMO5Qw7sBn
9SgO5GD7utX1hxtCBu7+B8sQAOa9K+tfhnoT0ZRECA93rbkT1fTD4VOJ1qOrrylb0OhC9lEeEwCW
ov8wRmdsrAzJ3UG0c5lXbzo+FNmbshlKhy3hb+Vd1bkCeDnztQvVIoVyZkGo14omyj9Z+X/Dw0Ts
mO6WBbhk5NAm/SphPmki4tTvKsMBSzSYPr8ObLWKZj4ewcdGh3DYQW4Fx3Ihqc3lslg4vHuVYjHE
9toS9+GmH1zUn1TSkc/EUMZd93OXY6MxskT2oFzYs/2tB/QPfFSG7N27gQGvC201ki/9iANap9un
IZW11Gs0Q7JYI/PWt7heiUe3rHDzIYMZj81cvhrHZOAYi1bBcrDr2bzUDsU/RJQdctLPilHNWixi
bCCS53c8LmtDLVxKa3/sU2H453woM5Ck6yGLvDXfcGHUVjhTR0DapvOf5a9F4lpYWNXEBOOBuGA+
WUInB/DTDWA36s80ftnu4UEugva2IcNk0sq0wIpvcPFbNhA+U0jOPB8zflJvvvXnx45M7ijlXgG9
QTg80crbjJsVJnkreu4gbID2fvEJvly+pKnk6EPARINkVb6lBTMqpnl7+TQY/dSzEAE/q6XaOCvk
QATc3OLqNJUhDsi8WFftn8agioTTZiQNqg2UKMnKoJdbLUzhHT1K1P0HQp+uaMH3psF8ZOI29Ekw
V9bpQFGNKCeJv1JYJOhnnH2Ta9xcEhcwVEGx1Hp0iW8mZq5wP7GxeXmrOLXygmObPD1fFwkrEYuc
YoED5o/F3ckzaq8FRWWqxIW6u277vNPAK1rfuis0Xt+HwgZSSlnoqSA3cd/7wBGvuCgbhhgn4kNj
igNspxwTx6oJLkMt5sO6SjyBnWGbH+956dBcXraqSo6f7Gmve2Ox0ZZsJJiGU7ZTC4XZUxiJn4qv
yoiFO2b09YlP6iVIopBdUfcbwy3etz3C6D8/p2+sOoyOfCIRuxONJgk2kEDVwZOtQlVOl5d31rAG
nEardgxhkUmG8ukcNq2TUKyq4G3mepRTRaxvewwUybi0KO/QAvQ6IEKs/fEYTixRkjiPedYv0W7Q
0f3amjhhVyp+8ZFyjzWv7+RwpZhD7Y6ipkifsqdHoTUw51cnNoTQUqh/AqPU/VRvlbB8Liw6VsTs
9SCSI27dgEjNEkj2sM+GFaDIAESN+HvtefKdPV9zCzcbRrGL1XpvPJjlVy8fHf7+YGsecNtsurCP
J3amGoe2BonxHjaB4hIY00HVeYVjC0gcESTOfaMj4W6SGcw1jGOc4M89NyKi3GdW9bNaWFahbKaA
AxqaRJ2eg1s5PulaLVmHTxHWSXZ+k8S2fpO7DsqbToB1KBxHHSSRTrfYDIgZJeXZKQ8HsBMO8JVF
1CcANxsgFG41DfL3saTD0oUDn+OG4HIyq7ijv99IctiTkAHo8jfPwaQrPmcFp/BlFfIxUj0Ytcwc
UesIJPR/TYXm2aQY9hlQLzgERQNJniUQDSqxpk2y/wf3Rwvnne8j9LtVLhgNU3ZoK6EHcXaQ5Rf8
JSNdV+3LR+pte/Jy0gTdQSbE66LXEZFWqHfnwBCgCX5VrzAadtcpg4CGbH+j84K2eusDR+cLxeF7
vIFbEvPqqxyURoLwn1lL2u37cffJuQF3Ejjte7m2K/UhP0AjVkjro88OdUVFgQACxrOJJcT/P4rc
+0HIvHtBQiKo61sO68Mi0kaeJ3MdUA8JUV9A6byAe1gBcaYybGEZgQ5Pj37iazQ074wrWLk9xbDm
p38xAZtEqF0up2z5tRQjNo9PzKcS/mv2fWwYvASTet1CmZe9/buBOlGwjlJ6jnc0T6myHxHBbV2v
zspDLfP04u/6KXLFb7ZR4AERsYj5g0QUZ1ctObLD2t9/rQqlOk9jXxLYxL23SYRh+ils4+IDpIhR
d0WOboiEuDyB3Pza+y3YVCFG+cW3xjP9Gh2AnEtKurCaESmteIFb3ZVOAFcLl+t8w5Cmu8dyXbQz
rBxFkSRE62/4Y0+KRlSqOy5PYpFUdXG5GTUgP2uF8tqoCLdXFrbKTxVRf5UPCOLyA/IYzhaRdMLV
js/Q7unwuCu1ydoIa+n+gTvfj8VbPHV/qb7tkuDGquafBQoXS1JBMc5LsZg+iiEWp7Z0FEuIw6kv
14so29HkP4lQQqwbtNS8qygzgWGqNEyapCsCRpz/8KnYeDTDtaQ+56SM7QF/3YxZTn6mayTw7FoA
32oIpP0RvME7hfvXmqX+JzntVMsyiFdTczUQnJSKdCOw0CEvtg1KqkSRZB0gxowB0NEb9O+VcxAQ
RdjixFLuFHW3/g0U9WZDKxMCI55hegVkNL7Gj0PEPcH6H2L3GC5i5P3E8+bnUkSBmOfv0yQgmPwb
E18UNK5eDEPzyQOi5b7V73jRjkmIXiZbBz5b+jTG5v5lImW3tcA1rOrkcRwoSrUwedtXrljFvzus
fsY+52R2LMVyqH8+Hd5pxxodKI/PvetYYY/4VCVv6dZgT470CPI4ZzCJtgs2Sjsq8fe4tU3ajHWJ
vtyXYmDXzLvsHJvLICuQRWJksxNcnZ86aK5BMZEiPXAYwpLMPVkDhf0+tpSyYHU8fT7K4qHTkOzm
j1Sx+HlBKoCIcnyC0FQuLCNXmoGJBPzG1z1GPHPoKlVr4D6NbxAaKQaDS5e0tQN40KTi5Byt6H/v
FY01Qve3jDRWumgxIkMKOnab4QOXd6mnNFUkCZoqvn4SOjVV/o/kZf7+N0niu18J/dM1B4wD/FHf
edCK1194NtQeSnWZ59oekOVgJAVLpRu6P3Bo6Jchsz5PWkZlpf/j3wOKa3tQdy5nJaJFo/kmSQ5h
gLCnytYgz8apl5CiQ8N8tPYDDYqzYNx2tHA/xOQ7IFlVgMLifBBJrg248BMMPPO+UDvvpJib3LnO
9OwOgtnocpGYA6L42iAcBwpY9nJ/HWSte8tAI0PzOg68EHOg2LinvL9TPGY05bvAuHyqT+6YRXAg
yyVs4RUXyBY8wlYpiJ88oMqM04IdQavkzm7oiag4qWZZgperY/3zw7tBikllJt4bYkvYJ8I8seLC
hOkCfIrIcZcR7Ua2n6NZDSyPbZv+l7JUcRrl9SwSi8vQ7XBuJs17rMIhsdsPY8jqhBWlfL7gMYLg
r/JC1mX9gG122iUICyc0DWdtHqlW9R8s5f9nMF6av/VlRrNElfizAkexTfyGj8bRH3Sg41ZENs8L
FdZVH3dEUY7mLNVlncQDFu7dd2i/uw++y7qV/YBWASB6P+Smd6aiq1MrvvgFZRmGAXSVs4KPhyDo
w6/2JOmH2PHYhTzIiWAhrXBecm60nS516DHogWVGD33IRSVd0yoC0ar90nalNhWC6+wDq4Q0x83h
cKpD7RbfvtvEO4RNGywp1202y8KBbWTF0FEkiqNvcM7oQUTYXWJsjV9h48lCrJcJ7SFzutLoAHXR
MHKk1qjiHBZb3Q0hapvqXIXkCWkkdhpadzxriK8tRp5RFJf798agfEtKEjqtxZR8rPGPyRKmt2XO
jjyV2iQqqkdjBaybtQ91yX400H7LNcNmIOmyGYhJ7j3u7LjM+PH6as+nEIgoUzu1V7/ALXP+ZlIC
pJdn6R7SlOp9D0iYNcDWea/i4xjy+qggwy2KvIqB58CG679jAn0/Ow7Xy3AUHg+V2P0NCTtadYbh
9sT8aq+xlsSJ71vsx/x0M404Mj/FRAcjXPhf/JD7TOfQngK1bi8jCgfkrcwPuFgYpJWcFEIKXFmK
LuHwpCJoeWwQ4/7nvNBexPgASNfH8W9WbEzXzcEHDxkg+n3xP+nLcyv58J5PnXrBkdoQMuEmEu+9
k9J2gLeRt5Mw5vUwkaaCuZd8bFdrGbRd+Lrg9rlsH9JHSi89zKxUbQ5UMFBGgArYIPhhXzDrFFxr
uahzkJa91B5/6TNHTyUJz+6zIAwQvQLIrhiS6gXMz3v+NOIn+nnzhZcACPT7Dl4MdtyYxNIyg7wq
bfTP2Ed/h5+qgAT6Og5nd7aVM6ZjcLHN2S9G9fHUBuNPUKro9KE51BYOrovATBCvuWigeqtsD22Y
sWeNUzmZ9KnpHZTXC29x/9eY7JjKH6706gvoDU1eoNowZKqAqldYoPMGjRBkW5sV5/ym7rUI+9ME
iK14osXS3Vmgo7c7wkfA69cQ1rp3xjSvzStvLOTIB69VI68qbDWB+34kFEguEpkG1qQXKPyMGbYQ
vQJKVpuk2Ywxq0OqpQw9uD/N5k0Fmo3y2ohsD5oU/y/bBsCaZkiveFXDNMqajX+b831LV22Wgt8q
f9U68BSFU651Plq2aKmimD9Bbr3GEMSDrUkTQeFt5d3B1I5FegFs0tBM0Rk2bdOveh058GZ5pnep
m+jkj1l7RMt8yz2Qn2Y7gjbpEwS4uyY27AUaV+dA9iwxRscXboPTPNMjZuMLZwSe0njp2oysZ/+p
LziRh+83MyP2qdEoDTKApnQR/dLosTxcu20ddEk3KHAj9Z0I5qhlbOHN/CavrBUXF8PZ7HeyF6R+
/1Eq0D9QRVdr+SFqA9gbBnxLpxuJl8mXUERQtOwDEkSagQYJCg3nt9K7d4o+dymqcbn3mHvManPV
jOyVzyhWPecUA2Q/tEU4IA1oeEyr06JrR9HuSJ5LLQhWFRcZkhOFwN6JZ0M/r66caWVEZm3G5zyq
27AtAT/PHEOYVyD1wl/arnoUhHvCigKEIoEQ+89hVcx6bkTmjvpEqCzbydmWW/t8dvVCEVNPa9l3
+JtlEsGhomsjVn6CyNfRBSfDao+DUW/zfHthRZ+V9BNFTO0itwC6m8O+EymMTxo4Pi3lEs+9O7jw
7wJg6uq7hImhRmle/VwsIqW6N/N0DX2hUp8ijckYd7xmm7U/OVVBlP/LoQcWjPPmmCAZIiwfRYMG
8icpKDEios9A2NZ5topzi9isbVYD91ClePg+g8siv8K7sh3A3pcJ7djbKBJ2ibNfjG58wgWQI4CS
zcTLVRdhi2liykwHPwaAYnHfhUUBgCsUpre8csvk6KKuOKzyX//4Aqr0ituD8m7ChNHBpmfZcYGH
sdbfpigDKhWI8iONohdyDVVwN1xiABBmAk/XqZvkBhIvdECIpcPODu0EQ+0MU4gLw4sIY9MHrj/5
GaMf9xwNs/BT0CRgxYndlx3uwtOWWLhHPhaTBgxa+8ADzQ71r5PNzXPPKKGNl3g65+ZnsKkuvz39
ImjrHj0BDU9hZzuo5eY1DrDD9PWN3VUsm5SIo7YGpNWpojdWvAURW8tk8auOlRLVGyLRCLI24/7X
rIBKGlX6uJE86sm+aCGWXfJ1g3/ZCfgzrryWfuzm7MzpeyY0ocUSXYYJ8xO/DsHlqNr9L0YFuSx3
8gyzPI2A3fVNobdrMzpO6aZxSm+IpEN6cPgRNUmKuP/enObna0hsrQsxjRbPSd51Toc98+m4cs3D
wjafa23tvAY8HWEmbJYyNxgqsQRAEPC21tYZrPnsWS3ASLEHPVZizPapREUU+Vuamq2HkGhRNnwV
wu6CNOnE16aya/R9TFKA+/FhKc82OVZhBYalEoZuftt5bChHHCxNQJYV8J5lyZO//sKaoXoz5pHW
qnDkSFF/3e4YaM6JLtrKa2r3UFenwAKoPmmWQV+bqxpgO8Ss2THRGlWTQreoPjkWgwwlYWwhLchi
3WMOHREpJpJKXXcaG/yiTARBq01N4dp+JjZ6lGuoo9tbd6cudB13AzaGj9HTCW8eKuRdF3NzYPiV
A5qEBTu5J3cyoAXD9y7YxEt4ItqfANsRUF8KH7dQqmclqD4ZJaoORy/KCGb+UZHKWYg0eZZ+n6ZI
Nkh+FWNweXH6MAlYOcpu/xaS6b2W6sPA21Qq+QhE/9M0fw7DnNeS6Mj4H8S88EA3PcaNYenBuOnU
4mobMVcLyHkLvePtTJB5OzY4qvSd9FXDDWf76k1HZAvPeEK7TdApKwkrVBZJSYtYbvBRYk4BgAk1
JrJG2k1KtuwvoT5FnZjKTT6I0FWKGdmEg9TG7Lyr9l7C4lP2FM8MHTny0PnHoseHTixYneQ9Er1o
F3TqG29xkcB7aWWN4oxlFKk98IHzE2cesf6J8dJREwQlSoglIYBKWAXQd6s0IZImh5UXGn2m6e+I
lGI2uaSvb8fiYWZrp9xApcPf4xjarATDMmciPcXsnhIovk9oKP5bYM14DQe6eMRA1hmY1NCccrWg
slLKzoykQOMal/pM7YLVQDA0BOhUmQqMeMlmFK+6AYqwncWJG8H6W49ulhjVaJGfCuXWt4lUP4nJ
Qfs0sale6Bsen+EkcFuDhQniOW1jo6C8FjqcldZ+e8PzeQg8mH5fibb30Yw+RviRMmfHmgNspnV/
nmbPB1Z0DlRLo6pytyVMzppcQZtxXLw7urMklvAp6xTJDJyw3E0+r05BIKkSwkUpPw9RuFnLpW1C
YkrG1E+4orj7PKL95w7W0aQj7UKlJ5Aq6UPtYIQNNIZ+0VRCDb2on8hkS04S23hJQ5bRVufvtPJ0
l7A46sTcqKA5UqQn8XAgODX1wCKsGqd8rPzbtLsHOCMeXEzK03kXMgphfKHw2NVg0/UMR9XkdUKJ
AuVB52TAKjGE8aQPq4oUkzqXsI8kUz2prM14Xupq8P1X5WAopBqcRS7nZ2/VnccQzNxr4GRteGPz
LBDEWzAXZOBCHn8dtETHEkoggTt4Js3ZjNXMSBdIG139cIlRkhZSpiPd0rtLvJMTThfQnUMzkAAm
JVfbCA81xVDR/NO8CH3/Hxtdo+U7tmPBwD27vawmCsU21XSd+ZTDeKNdzWtRpL8o986F4yeZObkd
1T14kUaE9MQ72xhkg0tAOuxgzy24Bllke8GICm+OS/QjmDMpDW+Y8mlkvtT1cStZDtRmTAkNkeMT
CuX7GoYCCoJTvXGrI2/XJfz9JMoFr6aulpwAuckmFVoHEwH/kaknDAEi6QGZaVYfkvVGV4NXV8aC
rbaPzj05pCNjm/Tdc6Ag9fbJUY/tZ7K+7RUSUrvQezP6rQYkxxQz6wgpBVvSdl3yP8Mf4wj8A2af
ST+Nkv+3HFemdzXgewi/+c04FTLZ03sVmPNXf73QGr/qSf0pqsPpckMbAvB39kSfU8iYpp+QPNo6
mNfHA3FUN7+zEnH3S0AxFVaQIFrqewp1se01+KilrjJPQxkMiPLLibe27kbpQO6czw1nbqCq57sV
NEDpyLgW/OPzzoAcDWSZVotbCKaobmJx2VdBwXRh83JBdHtkYLlJTiDv2e437AsIRP7tgVLFf0oo
D4Kc6SX441Vm+W0127P40rggIl6ksGItJonMKCoxMv4Ky4DAy1Gm+c9HhVuCY9Z3sTDxf46Nuhs6
dDPJREijJZDKLN6H7nBg57fwh1lbiddGDO6VZpQeET2NrGbeRypPzc/irec/Hq+tY06RZkJNUfqS
kRojv586YfAlrSzRrIVO3W4uAQenYQ+ADJttViqw+B8bYbxYeWbqfmT6o9HYKW+uXYEO1u76xD18
c6yduJCAKL5fyeBN92GxIrbb1HmomB21LrVmCPB+qzEa6/TIUxUoVyleRJkMzPa31atFXxKKjrqb
70R4cFt0BrAAZ4J5OBs/TB2XwGo8mqMt9AAoijn1gAFs9Rr/QFIWb4bk6e8M6S+PhVcThulfVbg3
IYXrgyNYx4nWLRVbNGXcFQvFqC9osWDFr74QOo9uLxYRq3oFvl3e0MscsLVjyFGJqkNIpAOssK3l
mmR0ANjzYpPjV/0khqLuygxgAxPQGHeu9dHHGaq6sgW0GbCiDcHkB3ALLSonDejp/gu2wckAEqLe
Fgy40OwOwHHgfc2cnDMuWU2y7PsirkhxrDpwzSHQ9FVWo34tJJy9xycbfYTwBMPOF6HZM4BkJkLE
i4ct+LeZSqCuoBCyCq1wS8RJKsdlKoFYcGx5V3AgkTczc4gg6cgdOd3i51FC64AWdhD/5N4/MwzC
nsW37dY+5qiMBkCutNqoS1m3KwMeMuUN7oS7Oqw6k17f+oWrayCrOAqqcM/Czin0gBm1IlgNNytt
XdeVWonxMMvJzIc5Jcfe5lZOXclyqDoHgPDfWPuNqyfe/OtJrFcvQ7GA0GTVDJ5fbbpKyw7z9H+1
EGveBCbDDDwEDbQEO+kNNr9uP4bJpkVuEOYvpGfVSCykmoJZMdVtV9Lljrn4Szo80NtQNBE3+z++
yeJBUuhtrhsDft8QXl/JAYjUW7o/v5nWY83TNTKX61pO8TYCQvxtgQ5BsAKFlA0m9kDPdi50FUG6
vudSYb7NMfdrKgAy9JuqWit92lV3AFLxvjaUlFWdLr5kOqv4p6AyRHlFVfs+U24ca2AojVFPQNMd
M4qJPG0KWwUB48H8VjrVr/l/yEvkPASTU6lcwDr6faI+jHk0HVrBciSqcgonRXqvatyB9MmrtOjI
bNzqD62Oi9Dh2ZVEkWZqoI3LGBCLbzE0UNO8CwXX0LRyBmU6PtFiF3uCr4qs3A+qeIGhOriOM7RU
1HIUfzOGHu78o3nW03B5cZZVzSioKnbr5LlCepm7ChMwjbHiQdEFA5ZHBJfl6/nTVuy4KkKCk8Rd
/yo0AJcyuEf2BSQNriOGtNjjsYXPHU7D4enoWNpCPb1LHd3PfD4Lmz4X0OxarXYoK+WycDTe/0Ph
UUGKYVx03x4UsBKYT6W6jDuIi3gEgMPtJio7c+jvWJRk7DZ5Hhr83K166RVCaBhWYcnMfQVzJVPE
R99Nk4iizTPuky5ROof+MVk413ttfo/sC+cO5JuiZHk1I3hO9zSv0u2Nd4xF1wV+2FtVkqbs9iqF
mu4l0KPtqoAe73QzeFp4zRXLyLvaG63zhc+BKjNV+qbL5hfhdJ/a8bEwvV687bzmxxls4rYQR3a6
xVL2oPFQubA3peFkfNiV6SJf6RDQqD8D505seWEyf1nAqJqkkxlvNpV1z8JWWA6ij8clVmvwF56P
GZN4YGDVXGwYVtwaLtvK+EGsO11Oqdqu32dDojeaPy8FxOXBmRnIMj6Uzmv9EMZ77rzLjUOJYC1z
SYImAiYOaLesrTOrXcIZ4pn/GWx4mw2aVJQ9GF53jxiKXD4qI8DPYZZwb6kvZAW8U/OqPjcQtfuK
eUhyInh2aMwbfhbFnGMVBl5miwG7/YUhYg1q9ulLC7hyxHhIEJZaUOeb3VTazszF/MwqogcSVCIs
q9f0XwPtm0BpbD+ndmFQGVXM5iZGP424eUNy57uzfGlbktdCj3rcL5o5GuGZZ86egIcNjM35oJzz
oJL6wQTAgsDZmyssh7SwHjjueh/xpRfq2Q2ilA6D5gp/YJqUPgbb+0spCgJ2tUH25/ndsi3x0yeQ
IR042F2FILO9uC4U0Ju2oXFnuI9KBCeBNAQYTFk7FoUwM9eYeb3Rkt9r30+MMkx0F3d77Kb7IPYJ
ftCXTu74DScxMNQyI0WvWqJA6B6ZLZJ9TwqLTGlB+aIyoFNHDfC61LnkODhdLwatH1J5jbY7w81g
7PRoNXzsUl92hXQ4ehgTt6Sf2ua13A7Zjl1cCxMsj07M7DtuWI4bGDxhTyyrxlydUZYkJeelgKxz
AEZW2H+6dZZAENfIzGafyiYx1hr6vyZZ/tub1TCxcT8WgqZrnN2gh0f/0UEOLovjXMxHQiRwNFl/
1u3nJIWL+fbw1eBSdIHzdshaZPvEes4Dd56mRdIvAC1FYvAelbkdSV9tYRbYHCkEw4Ctqs5lMPJt
AcHbl1pZ2aa+FB45LiBw0qBAxOsnvXF3Ri3h8SGER8yIyqWbz2RJkPLvceYnAIQCo5Md9hQ8p4vV
qWBOCZr373jhUtG596J82IcnsfiGb87FariiKnGKJrb4Y5K+74XO4+l6zwPJh4jXV6scxm5DYVsf
JNYQZ1+vwjNGl0dAt30aed2WNtd7VT9oXALlV6FUbkp5X4tQG1lS4conDT4R6ER//3qbj+uPxsoh
PiScVQJY+siBXj5P9QXtGXguxUGKS58EsoT9NNBdPl3YweyrjhzBsPY0Di/DKFqLEqrNJ+a2Q3ix
xju7v68r4fBo0/3bj1ZkoVbMY8aUOklTpwfCWpfFmeUdWC5WPaLyf3DMXAY7i3Oy7pJLQIsbJo3z
Bm/ucLK8bcUBxrZ54virt/v9hEbhfjNb0ib/baJlN6lDoLbosyn4GCrs8wBBwuhzY7iy6QVeoy0j
NfNBsz0bFXrV1ZVMhKBVv9D9SrEypStE9qPoD2cbjRp2b7aLycCB2RQY5sjjvNsy0QDXR5eyBXlp
M2lWjAeBCJrcS/KC7hz6AjIOfrT4NfwndghXZj+c9BcRJM7wKYDpwKbNou44Yh1DwUtZQU5E7tWC
usIdtCdbMRirPYs3WCGzVsFGsG8ShhSjV/JGC401EA3c6EZa21Abj09Z1i5No5Re8NCy2R69hRb2
vu+XKLgFLus92QbdFhaUl/FYjZd/8BK6fVQ12Myz9Q1an4b1G2MJZiqSxTHtI+z3hnC9hp7C9SQi
Ix56/1YTphePuA6+vHs2KLXbac8CBnufd8nakwFCe3icQmsi7n1xDqjPu1PbcpmKIIg3F4UWuA9A
kiKKMXxQq8EYcv1ILGqTpRDMiFtAJkPgN8KWPt/s40GaVDvwHH1M2SkgGuclZDJJaMPwDeMNxGGI
ddb9FbmXosE0ml3/rfHf9PILgYrRxVW5hiz92CzsUUx+fFQ1YYof34a6wlpO7g8pqohILTWh+jxa
d4TKPZyy/LaRUEqwIqw/J+3URApJwtmb3RQIsKgMkeQwzQ4BwT92dFhGPKhcnnJyRR50Ge16wkdV
5qDc6fY0+1zsf7mHZ2ATgIujIgHi9uipmx+Aq5iXYMOljc2GtPxkTpcH58toibGpXYERXuNU+lp3
LJRhVB1bB9aKdKjGpeNllkLxIPc2IiGqf1G23uhfau+reWJ/84zYPFMZbeGQtrw3pQZ7oEnT+2kT
n6nYCTUWfr78SKpLOTcp2a8z6GcMlj1Ejb/jvGU9keT11SBSSKJxcy7tEO3azjmtENLhjo2Zop7l
bzIZ8We3yTqzxeNf0Wj+LnB5BcSEGbATOV55LgARZwIzKf+hMLO1ULG6Jv5LZI1r/IMbc5Q6f+m5
gA2JJoi1CJ7jdXRDSdnim23Kr8jqjU0NnyWE/4PION/VW+4xKDi4Dghm2fnZpGx0jtMkN+59uJuK
3Bnuh/y5d8V3MulB8JURhfgn3YYo5JjUlUuHXLOS9M/6KBs7IhGi7eQloudFLvmzVQjqKUK6Lh2M
5acA5/c4F3txCyPU/PECbuyU+tb9Gdu2Iztc8KgM/XWHbU0simk6fso4Ep8wZzeSAcRP5turNlmI
ngPpAPHPP+uYH0jyBLynVLw55Je2XUws5orP+wD18ilM2CUgSzn18IYQylz581sxZdcd6JY5275y
e/TnxMr+C7ZDsl2rfYExSISTCpepMhEbO5WHEeg7OqtLYtOsLNk2r04Jy/PuTUlzVKODZZT3JOvj
CWsQRU8U4RWQXaIn4T5aaVF2EzNDMda5/5W1ohgEzXX0QTLBk6kgd8spF8QZlwTOUT9LKFs7+J1Z
hCoQDqw2SweehUYlXAj3WMF4HNzsGD+XHBTM5LiDb32FUamBHU6KzC2DRnOg/KC9SNOfcRbRvgpv
BsTziqVg+rDYy13pNJJbsJWfpYC7HU1N5q1EeqySDcoKFah2IKhqiWwYPE7zBubeEK0ZDsMC/uT0
kmlUNw0st+03hmsbXX7m/CIHETGSe3Jw1S8c3kvgWC9w6JoGRe7QB8E+JCwICcvTpj+o4Cka4V54
elZFK/L+UnuF9TmiQAMhhqZbn6eCollF04wLzd2KSTxLWiTUK/6yu6c9R4uD7aXO1wdqqU5cOj3R
luaHDCjrdtdBF1BjJ76HFPbgNGl4QVnpjHyno1dXXlX4RVpOUZHre6uw2MEg1UIrBg4FJHcGiiAk
MJiqPnC494zgDxveLFM9QJdcadV/EXl8WUW8Y+Jq9HXw1Nz2E6vbssWHgQ73cEPLnh3tf619aPqC
3Ls6MogQiQtKjlfKTnqiv/UUwCaS7Gqdpp+U5NS3pN1uLaLCcLw7rJzD9wd0DS8nH/pL8CyNveek
OU+wv7DLJLHSGeAbPQJFFLoA0c6c8Cs53yl6B7stwOiSrK/q8jUzEF3zZ6IGNKjsIbnJdjMjZDKw
WQRCKLjB4QA84cWlFIxlBI92iOrvzU1zr26LmN7dpPgHbZAikmC0mWnGWAkbFNcek7WaJ/4IrGJI
zsvRjXCB96d9ZYN7StCKu0aEOcDJ5WiIlK+xFDfRqKu4zOTp7bXYsJFEhO1h8XcFy2J8EqB7YzjO
FDgbvz6n0MqmtRinlR88D+yqeHrsl2Skt0zXJPeUiubJUsFsVwEBFvfT60iClSuzo6FboMnfa/od
z1QUvRQttfvyBgswaOJVoQZRjHr0THva1+STE0mpKBZCRET/o7dlbT5jH3Aj7FRERrH2BkXot+wQ
GD9Mv4dqf7DTbVplFAHzBXOIIM/oPKC+N5hyTujVpdvxrbxr/qaJnlIQ35keZYfi8gasyF8WyfJb
oz4FbdfJ8ggwVIZ3w0kyt9TTTflnximZ19hk/+Q+1tXz1ISCuB324kXC/V9kH3ceXRzM88/s4M0g
zFaxL2zyHsSStt37uKvSHyFe27VtwPpnfmwozjY/6K31Ne414TEqnqxydEcmZkGJjfLqDN6KSvIt
b/HMZL3xQ3sa9jiglyAsmgjd2OFziosRSLrqNpS6dP4E4h7IU0Xb+OmlY6OwovLIcqZ4U71YmHZI
b5EMijih+LCic5ZETKmWVOL9nFKL7wO+Nxu2CkIInuLi6x6WnI5MlTlAgY0zpFEPHDUSjCsO1u/8
GMHJy+CvK/I21i1z6D66WU9o6XbM37WigAiVFb5ceuw3H/6eS1IFX64ZlA35CXADJP9syOo3idme
5ztWIxCqioCeiP/cbPYydclBO/930leYgOiUo4Y8as2A/NP9Px17oiShzyuY4zO83dveVSgQ5iRk
Oc5xxbgBdbA16prDTQQRwmlKYeBzYVA53antwwVAV5T93Vc+YrHNjjZQn4qMmouo8piGmCiYwCiv
Y3YwDrYNcn3GozWDbN9FmsFd+8jIBSRpP98ERuN0B5vxiEbl2mPB5z0IvDQab6v2l1Li1ODfIRcx
DRm8mC1h2oqwdYh2lmy21hx+sFJmsMlJJ5dg+SgCiWIiq6pr5bXqCBUnwUcFmB6MwY8u6R6z6tZd
7Xa6Enb2Je/ZD/7jpDe2Q2OSsJ19iwFCwMaJY02PfppLuWRKHANKJk5CDIKOKnmGepth3SIfhkOM
X4q/7tm27rTxuv9XVBMleS6+Snaki1022/QOwmeG9ZhVQaDh16QxXDvDtRPLtTpn7KdE+5wdUcb3
GaLRdK91ZCHSdi//ZFZUfOcCJCHd9a0mbmDIeqrkcLMajQk8007WpmVkrVljof5xHIGRc0DSmt56
oLRRAbTWHXq65LbgwnzAh4UshLtUDwY8uUe6xPyPb7SM4X3IqeeCajPi6xpUADG0pXUhx4vZDrwY
S3b28BRhaxTB5k+M+qJ8XDjWRT69kg+10pcGIG+ZlkQl7eQaZvc2a5OR6I4UISWKaoRh+K0mXm0X
wEPgBZFaotm+oa0kkDOaopkESx+mYP/vW+gyyVqJPhBmy5B9Oh3rqbVf7cD7JC1NqoGZYiQpD2KX
2QwTVnfHmtgX7laOnk9dsYGNUH/G0QRR6jxCkgmg488e2736gkWLR5/YPqMIQDhO6ofSNX/b7c34
Vsz0QNfXYj5hBCWIZzE44nT300wpzbiU8FGUC8k6DXF94grzjvAxlexogVakv22AwOg2yN+v6EgV
KBhYxSwcGZK5nWG4N8qbe/v2HBB0CV3ooIBT1k4RWIhI+6t3siacro0nTnm64KjG5bZnyZcvhFrQ
4ZNYnMwATQS6mbC0us4ZTuSKHjIkhqp1DVLZ/654ghkHX8sGByvNUHpKYVLMWuj5dOa0grr3iJeT
tzzFxz8zi5O6+3zTZdgxt4JZH9yGAhTRCZR3GNvwwrDRsZk621HjZ5Wt0RaoB9Lx5BeTfRH06mOZ
AuNWHLRwPS02XVMIu9Mjz7G4K38QUNoB4viA7OAS2y/guSeCNNqGR6BnVtDPzFqB6ByqNR3xSYaj
B93mSqqwbEsdEZigkCYB2exnqx9o5/+3fgrDa+ZUFbJ3xRHk/Ry0S9ptTStGCVRbidGOHMcIkufz
dR7CHK6Vwmxyu3KhfYqtdNQhYtbhc1LUYp+g3WVEu7fCTOzLRcHzOQUSkgulB0kTYbLB34e59o6e
9HHOjin7HkpJWp31aAhGfUNPCMi1E+PFpxy03X810YR89Ruo9ZNaAmx1p/e0HqVCocqr10pHX5LX
4cEwOc537P4QyWxbfi/FlApXF43kG/1typpYnqDGWXTokKNXkk5ESUaccJipGky+Ow6K5XOQ4dst
11KRQKHQs62NuEuUxZdSFLxqYqaGfTBiaW60LTXCOPrNAZoJQduMn07WzZwBeAyIJJpRL97EhnX3
IfzW8sf6eWj2FscwLGzBMo9LM5X4mRsUFpG8cZEGNwTvkzKgzQ7gMGLGgWacUj4LtloWNvhqvEEU
+fKA6qeAmBy26E8tlSffJ3zEju41GNBBjKBU8huEvWn5zYIpnYpcO7jfbfa8t1Jcfv1XbfTD1pWv
0zh2BjooZSyIHcoZDI4oMeTGR+8i2kFJKm/sDcVPIxPOKZKZ6QAPXmaaTiHhkBWaJUthTAYU5POK
Eyw2l+iHDzATOzQi3RYioeztLACmrKa7q0EE/ehTydjUAcipHNm/NOMWUB7/MqkwYVW48U4hCnjm
UFzhRjaDPoeVIFEUI7viGvlCBuuoES9LXb62/GoD5ahTvWua2UqkGDtohGVVV+MbDMNw1cJCtdo/
8L71CfHumRx0iE1FK8mI2hslkNZ3KpyP4p9XgowjE8Oy0DvrNQv1NW5OmvSA4PB1jCmshK6VMiaF
AV5pzc6ax+VAMs+la/8M3K2pijceMBC19+i8w/LRc7Tszz6TqtrQKg5Z/Nc7KJEm41z9GMgUjo96
30eXxdvm0DIm/IySJ3zBx2o+J8MdehMD8iJFWnEh+pmHjq9OtIveZfuNwLxLfSVakWtc1TF1LTsC
y41PST8/R9XR8IERbIxXfkpWgm7X5BRt5oHUq2zRlVuJqimohLNAhagD/hviJkGSGdNv49x4uO1p
Mr1NZ8fi9BfymgwXwURBm7vvPqctkx9jIkQsojUilFYNQKEPrlSASZiJM4XcE/PVQSrcBoR7EV98
ZM4+CFjuclF8Xaj8LLbZ1icbUCjDBhsoaHuLN8E6x7zfQhzLgMPgQT/osgkerPxtEKTtypjFsKtq
N8G3+uwBr1Ow12RJRw92L0RITRvk3iTIAtr7A35PDvznw2xlCWWRrB8q4/jbjuNrsouM83cgBGFX
vIKDWIScCR+jG1LASSc8kSfOjmGUYnU73t27X2OYIfsWSVIwVX9dXl+dwoXzwChT/DaRfzArdZZ0
lugSJd8YxYxb9WzkkS5LYihxTM7qP3LoDRwRD9E/wq8Ux9BuXccvb3DYUXn91hefCm+WnoYpD1Rd
3bJkHCvXGE1nSZg32O4BKFhQqx1sO8bVSe4ivaFw5tBXIHAh3GWcvDlb+XBWiGROIcnZC/rYCwQm
pXyiXV1DZDxbHTLb5JiYxduvv+YRrs45Kt6egMkZYKFEOBQpOGIP6bXgTZF8XlF3DmIDXZ7QyDFg
CLg/aAN3tCsJnFwDJu/Hql94houNLrZY+leQmWF2OjG0YbHqueHodUrEQr9BdBEJoaGt3Dck1Qnv
OMf22zPUTi3GBDDoTJEXDnrwVaPKnTKOEIFfRSkYih9bwRNgepnZX/gszoFM/+CWmPnquaGg39mQ
Ylr5creuhVjbONWJEFHjnSf8/iecu8ec2nGZ1Ij2H1/znOmfmkvoGn0vx3Sf1FCYDcC/BUalog+2
eXH5GSvfdD27J2GHZGxlVul+/fBHD2tfkEJsOliI/Lv33Ny7Zw0zWr2GctD6sTvJ8f09Tl5BAW51
1fcJhZFI9+8OAGx3UZb+ymH58/P3Z6h7CnmxhCCfHsWa4TPTGONuRr/TWqQnNF6UMS2GXLGBdWNA
KS+b36wEV0XxBSIyq6IfMyfTk87MNW3668ApIfXIg5XiBY8XIw14fkGYoiE6iu/6sG3ScsPDIdWj
/pV5630xhgdwHEN6ZMgwOnxBqd46dUDiP8Zc5sRvgCs5md12pxG2qeadwcqTiwNZyGMlB+PoMEGF
iZkkXd9SHXl7i51w+ZyMjETeXxapJkQDr/60z32tJ9JIAD6ZiRCsJVwVRaXcMn58/9jT1KXCjdus
qny8Xmu8wPoYFTVjqqmrheHwv0hQM/QE8Xe3LwKQvfbnGgepx13DP5aAXi/pswuOMHdcT78aN894
zSErRVBLk+V7tykvmnRGeaoPsudbkkzc1GpL+xUZZF/ysxbRP0/a58eDPITlNciuj9QWfxVCfdJ0
2OD/zgQxaOY6Gt7g2ZdYolDJklzgLnopWgIvejKyuJSaGSvRmEULd4aEhTb20BrXFJEdEsx2pQRr
nCW9CllMwuSYM9U6Z1xowyjgLX7m3eqDU7V1dFOP332lqzUVHR+5Rzd3JzcrSlusjj0ggfWOy3eI
VETiF7UMRouyQndDyJwQfpIfVqKVFhW7LKVObI9mO3igPk/J6oid6tdBQEebjqW+zOEKPaIC7DFO
zT7A/BdCJEArf0WeWOwgddyiNUCgKQVkoj2JCtQ9RxX8tJ2N3ATrAL4d+kOtOEdRI8AwchyWUxUn
zs2/c3FULbcmnbmxO5ny7ftdcybiVJPFXFVo/lTFKa4hUdzsNbTc6HzMws7gNyMcisR6zO+V9vFZ
SYO2J9YbP2qI96lcXWx/wVSyszcWYrXpnPqjrzmuB7jFMqPaGs+w2peGSCXXflYHssTM+iUmK8Ig
2UEYxRsDXRddOAxxS4AxLiESpZmbj7AzNfL6OXyxQf6j/dYHvEaa3n3QscpDrANkkQ66O3jfo9S1
UDqUEUDCql1V3fCY3Z0UdPwv4zdSqpZlOM0dtjdqkFvloTfQAtwLg92WHRoS0Fx2tIj9o8unYPfC
4y2Kn1KOWydjlcFuOXMzZguKjCkoQYUGsqxq9jSKafYMrq2hPx7UalXX8GVhhAWju/jDnP5zq8W0
4yn84xQYL8+mjK2LJLDw75/kW9hZTHTxPWrGoQeWg8WtzUvTaNT1fbw5csB96Ldmw4o85326rXum
jITAv+MuWJfCZu/C3cz0WINoAf77MiAX4/1zVr1KSLvbc2IlPvjzhwBW4TaTuBx6DvbqRyL6hfmo
iDHdtTLp07Mvuwx+Gfp8qHrPCxZiLVEmqNNbBf0SCpXt92ztpR4VxyMnpvfrS+m09zwFkwgZoRTk
Viqi3WrElC7r20nZUzr6lMqFslo0G4+d4axamZvdQDM1+R5+Ncn3n3yIwTHvsUB3iAHsAwQdd2Ll
ccwExU18iviSazqRjYKRLDSKkTEtkiDenPEBdgca4PUCBzoySy7rjCuKC3+VAaY4drOkdlssFynW
hwwE+nRbii3NooPCd3SbHXZYPrnia6HeIJpi2jE3sqJtEZjUyNaY1fJhrFxMLnv6dv/kLdsgFkHA
Hz2VZRCl6bby5cuBA6gAfxVecyAqP7AeYjrGyrM2GzGuuf41C0xTMpbiVnR1pAAQuLUAKDLdqOZT
pvBc3wUNEfa2KtPertlPf0hw4jFqiKRFXXBsROwHMAv0Gc+so8VaFFzpYy+A25i8aOPOsRlDUnL/
M3ftLl4GrL1wkFnmSAQTte3oQlXXyItREskaJBAvqPWDM++ozaiRTh0DKhYRKPIfeSsU+gJ8rUKc
pbqx0FjcqpG+YMfvpdXR9CXahFIcn372ovlplh1jVnFpnIinS1Ng63cYh9+EL9Vj5rwPk44qd/X2
j8ZDrzPU83Wec4V8b5grHjgOXDkVEqAKRk8mqUMYgW4LkGYM+ar5ieOonB6oWSKkET6DK+a+ZQ+Z
cUJH+WDiV4zwRHytBa9EmmpOwzqsoG/yR60YWdL92X4iLeL5tWDc5z6hNXIZgYq0l8tnbGaeKubl
bhSTRlcZhXU4jYWRw40dJe4sJclp0oNg04ywykqLuHxCf9urTd2bzQ1+4fYG0A2+roeuphp4BSqq
fyK+kcnZ7MhXvFsOxHqkSkjYv0SUNwqsDJKw9pOdG5gFLmqWoCVqEm8/hAFoypOWR2SPQoUnjpoJ
nf95S0Jpslg1Yv8GSJfZ1/H04904tbbhkZJ7qhegH7NL65+pQMTcrVNzKtSkTPmbMWv06A0t0Wph
pKC6ZzpE1/szR3Qjs013FhMq5aWEj1RCVDQjcry+zhTZ2hP90B89fSQmv6Wupu/Oyf5kenSd4e7Y
kuCQVTG7bByP/E2tP9OEvf4V0u5U4ENeah+aEKiCkUb/j+90TF2Qu529yWzFPglXKZrHtWpSEQCX
yeT/gprZvd2dq1I5W7sX7MfIJyTN8FGKs5CIi/z/OzhjLe/SHmmJu8HP32yBfMq7IsA4DVjALsE1
Iv5VY0YXb+Gn99zcBgyv2hy6jSNk5VyVoHn5As/vzX1HvfENG7Xu4KUcQltPF4BEzAEEX/HyZdKA
IMi639CRyXXISLnVVI6n5y2wxbVRFyP3neOWs7JRv8wPdrL1f7yi3xSSLOvROwG7n3V9wy2TKW1i
GoAXWWF0tMesItllPPh/Kik2skZalvC1/DodpPA8wOeJAvbUukOlFPNNZ0z6cGC1b8KpXKGWnvhp
GZflDCySaahTDhWowiwXPfn1aX5RNAbGPxe9eaitBTWi9rU4mcoddXSBfoKPBQ5+s3heRX5xMBut
0WNYK9lzTq2o0PSZN7xYc0eqT4TgqSG6u+GOb5R2mLz2A+/VfnbSVVaLH7SQBmVj/5/x3Pf9dBoz
MekY4nQ1QbnNmI6oxESsqDOuLRAvrU0MbUZPxxZxe0Aok8cFDqJ/Gv/R9jDGrHT9H2UGs6WaNXgj
WLneyKgOSiguYllqsduKf82/aekV8w1ejy/cYtSJzA9i9rM9bOTDGRcyiC4+zJYwHkxbCOaYqvzp
rFF23x8pQuscohUygB8jeSnc0KOgs0qUx9oX4B2cY5AlF+cCDnZkOc8yBfYNkbz493Z65VxpscH1
wyg4TzCjR41gavz+9AH6CyfielY/Tr34TXygQS8/JxnhvQ13q5SUKuyRXpBXoFeMCOUqTnW0B0SI
YwRwS54HACjx7fmIsLC6HzdPUhgIL88rt1hYHTjxaImaygBk/RlJselHwe7PCJslrAMP2tWFjgdi
Xq9EMfz0jTbjgEMxbsMb1pLd20AINhkm1tw5RXhaiRPVzSeBggLme2hF1prNqd23aPzroCM1Maqi
Upp+SaPIYPeYNGCUG1nEcZ6glWUJyPM29zmKzBn4WHL6czCT4HoNjJy6qyY5RlWkSGEnbgx0s7dB
+MddJ5FvdmEslk2lnJoPuVvYHFKZjjTzHls0LWQHq8kSraoK/VBcheMH9bupQ5mnhanO+2lCYpjI
G2xSJNEmVOvDiu2CteLh2bgScqPEuamu5C/uFlfyuNa8582l42RMndGwU+v1QOiTRCu7JPhHW5VU
9bj1ax7RCGYyare4YKYt+krQHm+J9NTmX8KAVCLwpM6Tg4zXQf2dsnhx4WKuU/Dpy1ZG5x9mnkNj
0qc+flzzZMXPz7bfzobJflAncjh05qV7fMSzm9FftgSPlhHxmKgkt9G4EkXTpgUf/CDZDwsI2yoT
M84xwzTVtZoOrFcNOvc/G5qIbf/Gy6dUiljPsLoJnsC0T6w4oOHA/4NtMPJOs0uqhq3xyx5ISrvi
MWuSvwYZzPnzi+9s268DXJdEvDqLzYaPF0A/XfUx73f6Bi45aS/pVqPqeS8plgPjKEnq5BSpa17C
+fnLE4lBubE8nFIOB/DBSKW/ic/zrruM575jBGY/sNqZThA5iQABznsRJl7zGcDWHtpyJaqg9pLZ
EiV6xt2qry7uJpaH6QBp1a7NXbWOquuFXJIPFVLnVWyaiQKhkQhK85vkdzZbbQJ85vV3ZFwSbQnb
HzLGZnv/RHjLQy3AjFWoKMeFr0KkQhPg5PUKuW6+qHba3xdotGZfC4KTjFy3lpO/H/D+uoBNt61G
RZ5TfGV+hGCzljk4++koFZ8+Z62oBKwOq684NbHxsHF34NATan8nm1q/K+WaQb1v1N3mfnPdHLq5
9JVrR2xqVudRLnpiCifE/4YSjg5XNsPdn7ucwooEIIh5ToDJJ8TXPZ7tix16hossBt/vIfTvG7iM
Y9ooC2aUxSBMYvdJMk4d/vJxlzhA6X5Z9y6SftlqJquu4eXmLRcoI2kiUa48r5fVjjztdkhIQUj1
NQ5y4TacaXbsQOWoVW0WO/jfDbU3Hag1UEgHZ8eF3x84BoDz3vfMAyVPNpc1pf8ODu7pYEOp+uJj
e5n2JZcw/J9VMijwM/J+GuLpIKhpzkg9PSyybONaanifvAuWE+1OKQWKehLutw+DxlYklLF34JHW
sJmCfvOBCHQCXPirj8knrRyqCluBYmd0HuWzYQlo+f4TCKKZWE+3rd9grdlWcafPNRTOjNUnitQ+
lM2muiSA9TvyT1U699UL0/9v3Ta122VGCNbsENDzkuQ6Ol7Yb0CKrjJC1f87bkoOhkef+oGMFKpw
/7AMH6x0kjZQ/mogRnNUaJgKY6GHR1AVC7T/ua2Z1z3lDQrBMyG+zl5Mew/Gd+evdsMTnphpnHE0
9Ma0BH7wEH7/Id0cuTwzGDymR8qUCQ+diU6xDw1TCrZ3Wfj2E+kzmN14UJdaQnDsv80ccAaXvgeA
n36uknYhNfWD6i4B+OKufjXM2pT866eA48TOtFrISEUx9DPjAv1bnDA5IXIhmI8EQ3Lzi7Xc/UmC
BkcgM+BnX/w0ToHBKp4ki+nrFcPXpljvVc/y2ExJb+i5gZvQDQD2ZrJ0gZtnGUyzWr3B0zVNa4zH
x2xveJ4x4aPS03wJS8l9FmcXdGHsCkL7lJu2Yh8uXGGlMk57Ble3q14J0U/0Z7fOg9wcE5CjJHCx
WIb4dauQO7K1erEzRc+MpBUfp2QPHbizWsPtmR7DjMZ3Lp8Lu1UsBe2h9kIyVJvbqLCVfPJQW9nG
+lwuLc7nuaM5F27wx7kU23XIk4l/YV3KNPhIt3Ww6Nc8UADaDKtavBgc6+InARrAa28hXkyFKxBV
wkr5S2Qp1TvbGkMQbfDBxFQ8ByuInVad4u7KGl/4lRMjL+tXrkJrJem4pss1wEsVF2KjSvPcSXGj
Mtkg1G6L3g3laPJFFvPAQREdYNWQwTzkFZ4QLm/cvVSRQTKOfBukrei5HxJt9Bh5ggt9Y4vhBuTp
zCnnrESghZO7Z9JwcHDWL0tXOiPi2v+ue1Ll16gOzmlkqaOoJcgExdXVIszRjvsGj2paZ+gmDucA
hoC6aeoMOD1btmEnUUNIgcx73SL8uRCvpWy19WQsggf8PB6prn5c0n8AzqOJMQ0fiB+hToAqeJKq
bMSPUX+OSfNF3mjQYAz6oTUucVfreIw83bvPb3E/UsRXqrHaocTLVTpFvCajNopwxLyrQTGYfSH1
UqiB5ZhllA4pRTCAbI8X09OuL9SlXS1s8M7xN/1ABSA64+i+ObWC4XK4fW6ID4NWR1r4VpaNZryd
Qw5JQMlRzGWH9/sM+o+tS0HrgYwdFGOV+ZECPxD4OFfEmZPeYWZMbQvEmKoCeM0eKT4Zd+C4b6iV
Z33ZyzljzHMosw8rzU8DPzj9GQXTdtyaGAruC3UdP3CbM7eD2FZl/wyBuiui6wGGVxX1HRCk3zV+
qMBRLlKsXnSpIWFatcWgV+WPFDTcpUA1+NXAKXGYsxKi+072M8NrntDs9UH6QcIoADHBTxkgLFgm
f9yRJD2rNepOtpGCp8I+0Z/LqbGJBeFfo0EBKF/pnc0yIkIw59X2HEzTRpgtyeNuJfd7oirbaFN+
VXXuiYef3aiQFz0lOzJ0khteiezsKR+KK2QzpG7pap440H3gz9RdrJt0YLfxiR8bZK/hXuzFzp8e
RnOSKlk23Xx5BwO5rYddfxpYqZK0dYrhZMpxMudKrLuSaUoJobPR36vCCoyNGvKSndDnIwPvRufw
ZXTj7jlm4JTw0WW/6d3HSvCaAKENljoLZ0lKtlCNfO40C/0OBdbiRu5X2lhBSoNcaoBXTQ+sAxDG
/z6M/jw8jhaNJfybcCAAgt6GAzTDOun1G1UzyizQqgV1iz0oQFL3u/p5ap9UCj4WuGgay+G9aZLs
/dY9J4cIS8wabcngVWfw+YlKln3cjTthkXVDkV1D4RdWuJGz8mWagiCxQlcR2mNipJal+XiYL5Sy
7OpcLUcIcvdjLsb8ZsiOs9/CXginvlmb4qTZgOMAs6CLm7tDk+BlUGyFN6m3k8QkhiB6HDX2ylv7
rcXDIm3GotthWcyruiNBQJO3a4er00CHN3ILPUKEpBlWjNtZjoxL19LWdwDOEBvgZQdEORvfbIC9
AQ/7rzh5HROmpbDXEFeEiN+ajCwPnIadS8KEOC4f3T4cs8ZvDjkYTs4NmqdB7ZBJAlm5ujC1st+M
OVAPqGNCmZqmxCU/o6DyCcTHEyW5aR2SW+xd6FiFnsmHamLestpQkInLg/9Hq3Qc1XTJWP7BqAM5
TDKIc1U2oom5hHTHfBC3YDWH3ngr5OG7QBFuXx63E546juohePtjF3G/Ja1aFf2OLAXB6j+3Be0V
4gIvA4TMkE3kLBe8SDQkEMpVEHaRKKYpBiAPNlboicIrlv7LEJW4nhLh0bMd2pKJMMbXSsQ3JTsl
CBxuhm0F42OtdegJFggU2VCR9RLlj69hVROlkiyZ9II5va2/+LJ97bjexuJz2bMpuBn8eSRYJ8Rn
hm00VxO7wFsZXwf7m2TyG90XoT7dS4wLfkoBfX2+xH9DuT4SKHLOizmjXryCM7XUgxE4PuXrDXek
2/XIK4Wap/9s92SPySN0LXHLigArauBbJmM8FOzQK11JNOmpY4wLaGdE42PDccdIGpdkMKRWdlQk
Exr4nomPRtlaqHVLox172x5cJGemjAHrXWSHlmHKuqBBKF1+ALmJHngsVHOEXJNaAOQCoz4lhBf1
Dv3zuyN11ku2ZciHrFUMwiUFSbO1KvgPuBk9NTdbQEVstFGcv1vLmHuZDerUk14IpxI5PWSR1qmi
rMMDsIKEX/PqMKic2mskj/dTybHhCApToBvdOS2eGieq4POyWN1laFBcNpbl1Ji5b0U8I0K6K6gm
b5xW5q+LL46pcRMc4L1nobqYkIMAyGxWAjhYmCxYW2ntMfPpTIMj0fk3VkcpXVOHv4UAjB1zs9g3
tiCts/KqXftcZJr2fsuO9JZhi1FECykHQwFyl0fp+HXe+Z2HTaNQJ6MLlHFfzdBuoVJcXZvP/aO7
4DmEzmizwnQCwJUgtHEnz8hJZqOuTKKLcZtAWBX1mR9Z8hdB4g/G2Asf8QrEVKSGRTBDf5Tp0KQF
8D3mr4ix1g5OosRLI8oxqs+8VIwP0tmvHNTS6w/qIckr2QftfnGlso1Dst29TQZkG/AGIsIL9mqd
EX0H4ZyNXndQbo/za7aWCNkWtr8uNQ6nFoQqdptzJDtAwA6fFkznyQmJuMml+5l6t64dBiNSX/Uo
7taUonh/UM/86W11o5k75T3uo5EpYcm7NP0wf+gWzMZcAaHum/uMa24Vl+3HrHQFIG1tX2TpnFar
ad/IgFdFfOY5NMWY1j+o36LH2CG9AYXOzYQ+cbWdF9kJHzt/W+/aFYAKTj68ZP2rA3GwkJjru6Hz
LMEQ1bEo5KvdgRiZFMSVzIgErJSO1QhzeBlL08jOw+5Qzers8+p4R1lBj00tViVPDmFo/01hEZeo
IvXRzNgOWMiVmiTTBQs9V+ynNOmmJnYZr9f3brkvWF+g81UIHy5vadj2vW2OdVMLO0Z2f5KkknX5
el9WtJQe4o4u44RQAvDUXaHWCRRpYxt/PE1IVnZKI62YmCliO+ByNfm6b4EW2ZieuqxOttkYQH11
P5Qf6Z86wb8FATKVS4BLegHLsXeONR+d1h7CZYI+/tVW23alQd4bm+aAZydPdcR8xNULYpu67VTt
mdsjPab0RtQNHQnuc1uoAaUuhQiYe27Cv4j8xHn3tqhDlE0W4m/7+WvfCJB1gIt2U9tVABj7jrnp
X67tgRYU4mt8vKPIwflnSNy0r2guU0I72ZRtlnKPeXgN5jGb1CJf0mMew62cCZpjJX3+Ir78z8Cb
0bDkW+v0RJnfskuwFsF2YRdEF3fMd8IyLP0ruYhSyriwnH1TYKLGbsr+nfOzwFPfxjJ6MVlf3rub
GlEaQljCV1v3kXXHEoJ8fQcD5Y/tEH/BjpAa5tEVg2cjX4Tc44FDOx0gIz4TdsjlCmK4UMAgPuSV
mDQWukY0CP1oKHPsYS9m/J73o32AllYsEW5/5afUgi1CUXObeAeETJe5pPTXU1fOSGZZ98V1fSbF
/ktpou6llFfsVIBjJKPO7s2gBDE+aZ1dEQ25IhK5Rv3cJSbbHCbjAchaQwZwuZ7OG+lWpYLnXZKo
R7+7SxqaRN3RF3m36mmhJLj7k1oNZjRsuM6P4ZHG8IETWK5wcYLp0JBxeS2ZlJ8z40K+1euqLugz
jvkQ1t3O6qU9phPnBvRF7HLM2x33SydJ9PkrzLK15Zgg2y2klfSDWCS7UfGLKvxqVLIo8RzJ8ghS
IJENDmon/0SZdWmZc8ixKBoJBRDKKuL0isvyddx619YbzQVq7K1A0g10RP+wFZomGUn1gN9BMmjz
XLPu6UeyV/wM5t3cByqWt5+iwyjQt0mAdSC6NMQQpLEc5agCFR8aBQdqTIkH5eum2zeA59+oXHb/
OGoEn6nX7nrvujcMLc8ey3+8gohdVuFr/TRWAt/xs7gXdIZop9B0nvHaeyUDka1i47R+TtN6fQOE
JiWqFC5rvBV7N537mfjHg5n/Lh4clqbRglS8hulFE6iUQBslI1jRXSjv8NJYYXuws6CAp85euxMG
umGEuHKhVSppbkfz8bOz5cH6I2SMbM+nwmex2+3cj2ObYJQrQpsGj4UA9d8WDAOQP1ABTrnVbOc5
qrJsCoyll/uz1ibrDiGZbxpMEvBovmClhiTuncj7RIQ7dE9cpSmy2iBU5E1WiGxFgogmP/PEH1f6
ZC5bbWj7pvxaU9f/36XaxPPYvC0L3QzpXeba7jMNZB+bqaCYrR66Dx6nNxisT2dlZS3SwosIooWJ
qiiQjjPabRahFDrmlR49im4MMKeH9F334mYHH6NL/flIjlNPJ4hgZf/Pkr5ltHMXVnp3sv/UTyX6
4Q+56h1mZA5Lfouy654CZXiE/wqMgqtACZ1X5Lk77Jfj5DntWrRRdTlFi70lHYlKlFnT4fKg0Lvx
lQnZzKpEwwQrATs8c4IztWB15LTAn/mQrNhZ0LLcUTNi5+SDuHYr//8yZlCn39OqkocLGcEdHt8+
E4H0DiN6V8bASNIny04kGnWBKlcAL38tuCZM4yvEthF21hjPeNNKEgMjVNCemrqx478EelMSea2a
fFjK1lwquFS0NQsgi8fQCMGe4eWlWJqhxPuU36wYx+x+f88sMsYZQiiBVGQoO8CBMpEmYqMnJDGj
EPGIRBJ8NIKiujNr5TgH+AMh4mY9KMZS7Ecq7Sh10MtTDicd9zz2WQdBmBIszvE9YjrNsXgv3+/j
VZ8K6DcXjItxcSZWC88vGbKp8Hefjmg6aLAN4B6SM20vP9rc+hlIS202CtthIKuDhMNxwEXipk8S
srv7smDTIuaJEc1Qfpyuo1zf9Z11BJm0zVkVy6p1kJwcY3sDW52p3PM26l+QO38JNyL+YWNKqlo1
QJF0/yMz0Yl096FmvG84EU4j9tqcsREw0HLrXQJSc9Sde90tpqckLmEManYL4n/oBvy/jU9sT3G8
plQITPuICMdrRGTF2CIKIiZ3c4g/ypnDoL1bsVfu53Qsry0WOfhA+MwiHcj9AQsFzSi9JEBKLmq2
VraZ526z6sexfw/vpI7t8p83dSyPX+FmyO3lTgIPZNowFX8SkPZxBQtLuyb0M/Vh9aZBhC6kdKax
cOW9E6GYw50YpOrhBPdNvKkXoKdxuOzmcXtJc8BKgP4PR5/md7fNUiQYfcbiRSbxXN8pw/IYPowf
T1l63JbYxQ0t4my11miIOpe2GgLWcEvgi521vsZnoZO4O5hxK0ZgvQm1TYeMEnQ7EbNfVN25RN0C
JFQjFbt/flCSJ4VUbbMdsimNARmsQ+Ue7x7BfZuS8zCMfadrshhViPqbT1K6NQPbUBRt8Z4iLDHg
IxHd0y0I3/vuKAdnTxHN1AxXUhgTuZzKKsbj9uxBgc2pG2F3UfXl+TgZN5ideya8otxx6ZAmDcIG
dKt175n4M8+PAfdM1PxHrFSykxttpy6IsR8GIVKpgUU+IQi7Pc40LRPuhg17VnNRD5Hh67CHh0j7
gat1JNsYVSjqzjn+oSlenklfEtgypjgBLEm4lfQBLxyE2RHDkBt0QAlcjaL6V6gbUfmRnfxGFyxY
AQPakmsscVPmaV1rr3+/oHH6fK55me8B/3Mi2z1KnDkUrrsyRBJ1ch4PNM1W46OkFyD0KBV6WAhA
jrWTvXXdeXQh3BZFFRVYFwHyCu3FD0g/SqQP2SC28GXVGCCGIncjrwdVpwspl8bqWk3EqoHc0of9
/3pZ268wlfRSCeT0UUPttrgjrAS6cb5Py08uBTQcuhz49LaDZeC78GxCuqmlVUHXUw6S54L8mwk2
75IHrDT2JfoEPjBVFC7xCGy9YZen0Tn858cXKStcZ7HpZ7Ntlg+QN7hfHKpuwq/LPE1M6Bv9x00E
A0j9qHgCZX02WaCBAsTazTKzawDysQZnRNm6KKz9cdDjfz3WhblK3cVrtWpmPjMv9T9aRBHtFVHC
KOhb+bqCMxTs/PHQbYwy83cMT1BZfZi0es2iqd84tExrGKWk8n55Tiyt+7tECNy4HqdikGi3Md9H
GjOSo5854KFdSHw1pWz4061Y022bljRuUMLQAGtwkwTy8e4VqFH4RpdJyAJObHhOsvNk/hdWd8dC
Qx29lyMm3RWTMo4zQHqsThrMkUDBd3NAZxvdblEnamtzdGA2vgesLuT5Gn/4iXvXetg53hrOBNEJ
g7q5dWDLqxqLtvEGkTmwQ+kp4OEqGscl9xLIkRYcMwLhlFlYUACZIccEW/c3rhINQA1EWuSy65ab
vG1HyfSZj7F7NrU7n4W+6DgBJuGx8ItqO27dtiKvu06OhPp50aYLTYx+cNG/iiph4Tw6epyXexfh
R6YjE+gu9EB+fwbLNEmCUDx7BtHuQmXb0YPbgyxMGlBNYKHrefNC9gy0ok0TcHvcRa8vLp8WFRrU
elJYMQF7Rp6gCGdentdrCo3erysCwVUiGcbC1sxP+p8Qx66lObiMrByKgLeEQCjc3N453gIZWpPm
PppucknSE7cJxZVSg6hcP99Q6iHKo/ais+Mi5YH7DYhxcF/nshCFZO9uWa/CdlOs4PEw/KDkQ8gK
yzoOxMey1BEjrDfNNNbvkrfioHMazqibmAvemZTFapGPZoyarxLrv19RTf4tQXepZew07Tv2WPtq
14xBkfQ3iC6yPPMQJ4zMtmuuPEz7CPMsm89bWPjYHUsMQL0XPm5NpxRYhPNr5PIlHN1tbWNNX4fK
WBo0HKNzBBtpCBHPflwABMZjlWYH8WQAycEG+3X8SuSOwYWwwZcx08W8Hrfxc3FgndixPujZhrMm
PDNX/WHJEt9jSGCO0PvqntiLdc8ISct4kUzpek0bWMIu4+LjoJHU0e8CDw0RX7bJ666hMUEUbvq1
u1TR/7gNmYIl+joK/d/rGdwJ1ifuJxzX6ZuzGOgIa+V4tAl0M1GWNv2qXNDPdIjKmG5pbDXdNXwm
dNEsTNSgPKhupTHtLonWguFHx19p59RWdixoroCdeMfZt4fBUR0RYOZ1dQVUqNcZi/HIq0/cGIMh
TNoL0xG93Es2bIPKttwznO0guk9/SJMM3qMaoS81rO882zs/8vCJrZrPq9hsMGcxWOAXzZd0b5Ae
TSMHdIqKPqtVAPlJRTS5MkeK//EQdP8vf7EOvBx2L3vakdKlNojR0vTpSgUDth5dGEWPWdiFOAk8
4lx/KPDzKF+Wus4V0KSXP4eV0mW1oUWc3eiGCCvnLXwO3I64g8I/lDgrjlTBxorm4q7xYRNequbc
sRa4hx0+1pl04/a7kmZ+zIMibcPUEd94IxXzkRvHAj1gmBpKBABJnRnE821Q02oxRJxYxMrKM3Bj
sHjhecpvoYE2DqxoAxaTL2EXnrhsbrWZEsFILAxj3TeytudKnILs3hdYMsNS8WM9/oEqJ8PVTSBn
ITq29GZGw2GAtAPMaYU7941hGwwKOc81NgmwTTCLxu5t5K+1JGzymuUCoJusf+dVqB0lx3VSZn03
/6bfd7luxct/15w73ZX9fJO6Pi87cdo3s1BDQw4gwkq1gDBSq9sczhg+XNACEKjknieYxTYZN0Yx
AhpOovTAAQEJdg0vfYRVdbUAzibxhlH+k3P6oTkWZRnCyaTq0FFFZ8pEgVE0Y/ev1oXxfATdY4WW
k6xxNtbMbcsHOl59Lj8bDV4DomCCVJZy9hcyJRlPwmDvTAtA5eOrgMrprsxw93dRCgNUe/YkPUsC
SC7K+i1QGSQMdLW+mrq4JANHzBIacwcpNdVpazSgTJ7j6M+BANwJwQOfC7+bU1+XECoz65uqID6D
pLLaOlprtvv9YtG/yTxV4RxtuoJqJWEOE3IhOeQHczQ5ndYhgltU0/dPdpNyYwg2K+2eM/g8BJxZ
0erdJ7TdUVykRhCt+wlUiu7p83m4lcVraGx1DX9A1RrU4jxELHcOCEc0wRxuN/lEB1VABfkVShgh
uzJRUTjuedMxemmUfKv2eOpYVg1/eEjD08AWqgmRlhUFlKGwpRoG7hfpgVHWLu7Afq8AL93nm7x+
j/Sc7YgwDCdfGz6AZVoUa3UdJyeWQvRtUvhJALhUW3GsMVjEpzsUeggwZEmMrYIGEAK/H/vYBFYR
oVL4M7kbsPBtBcCJ0l6zUa/+iojjsQsF1sJKzg148EpNjO+QYFzBp61lnYwpMpt/W7mj0lxar1XE
yzIV8cPnObgUTbfFWoyaLLeZtgQcjncHBd73clFvyvHyHcnMjiAxEABLKRinamjjc5DnKEngiAmt
ictd1WNhJkxwj+B9mFH0uMJhuuzUJX4EoFMngNjrwQufAfu5AxJ65mrKRZaHauVgD6ugCtC7MDG5
5tIoLokUlJdfJDaAY1AA7qRLgKcp0hfhBVJSsE8zA+GGVPyQk0BfaEdEy+PDazPHILXIanxuHMB3
i71Yo9pQm/Wv1mjF+Dmgx/iD+JNY7aLQXa9ASBC2XjF1zwf83ZCMzStI2sYAKhPQmtq+zpDNnC5U
TD+fezYNx8vMZZ4xZCTc05YEYLv2rzZmgKMU3y+9oPWd32KhnCX6gE0hpLle2Z6Ylpi4qHre0S+N
xdGTBbEshwZWTDzBVHhqqiKVX6TOYMaoFn8Xqk9OAekczV7jXvECQngwcJWxtwcrd89Tad1dYdQt
4/9ZngDkzpTMTgPN5Yxa/h0BM8mo+aIZw4IJNj7mvBX2+3NhyICqB9ML4XGwoIg8pbV1VqkKe02d
QwC7k9z0Bhh+y9KpVF1pHCqRcMDoSuFORXfwk5fK/b+XAhyS+VWsQXQByv2FN68SEiJfsc9TyEof
ETW7QsT48qnO5E6iYoh05A/jXLFojJx86X43MD3N4dFikhyFTg0Et63yKrDPb3X9AXoWWYE15jhX
5UHELi9q4yqSPry8aAeZsuxBwHaULDvVczckx4aYBXrN6Sgbu/MhzD+VHvLin2gbGfjSk2IhqT3Q
LkhKn18mceqahJdq7Yw9LrDVwUzGg50VvDMo/t7QIvta5mg+K25rcY/uuTN/866YKTEJu6bp82En
coodjf9GvdqihfotU6OqfSAELwKfml7bizPTWMgh/b2aI1NHDNROp+IS9Obx3Q/KfIMOqGUCPPrr
cvcid2+zIw1mVKkJ9ZN4O7luZDS5rQ61UXF1pQWaYfzN5cx4DQprqhGCU26+AAlOKGsKCUZPivWR
GG0kGCnVn6uRR1CQk1H1EsfYXj7AirsAnO/LmepC73mkalFxSgFzOsK5h6vj58q/qKN4DwvYlfgp
G4dktOlvb8nPbepZpKmaCLDFlAxFCf2dVPmneQlJLcR32H06H5fYznJrPuBmslciN3EnjcRzU5J3
Ewbk7ei1qZC/KbkPg0qbyATM4VvEtVDrwvCsBKQdPpWMPYa4xSAqoL7kXmw1pIyn3vBkbUIuK+z0
8wXYD56c+i71lEfUPYEPJBz3UKA+W+gRlMwKl7gVvB1QERJCbN9IvTTDMYladbfTxldomNtgR3Sh
gKVHuneoz+OY7y9TFVwYQZR/a9vzHMDkaa5r7PLUOGjEyaWXrzcs0TAVwyUxX5ck+1sDeaE2TQF0
MRm2l8h8KtYRST+4tuWbRNgF5ArJYez8T/rFvKVSQ8KtAn9vGVv5CXnnT8B6VUnlpL+WqxZXy4EQ
fSm+gK4SjFoDNBEYakor3hEep0f/voQFilUIHaAdsBrNPke4L5ekGu5Z9Ud6eo4Z1hK1fpJCjMOK
FgTObyLbGCIeaWvhI5dT/hyQGEO0/vuX8uXSgVozUs+IJGJ22F9EzaFtsL4h3sh5KHQxOqv3PkuT
ywzeJIZd90rfoO60LMKgiyrGUQ9jAuhpLjYOD0CYmcDu4PFFEAqcdBTvIhoXsRC2sMf//83UX1oB
xvWAA31aEYHVb3lYCgE85hIvt8X/hD1JDjR9le3+VcSE+1wOY/3OuGuWy5/ggXuG1yzlGnQD2hw1
O6U8toiK3Mzwl/72cfS1rjyV8JwJWO+mjulzj6GDLEWBGL+EoR0rnyrtEtVwH0gY+/ifZjG/xdbI
3WOKv91WR8nmdrSS9+1qDwe7jBVCvzzSN4zO+gK9GLjYO63LeeOrSuqfAIIyMUjxrrAwLGIYFxHF
2e3dQMWIW/kG71wO48lILnimyHhzpmZE+gCIWFdskGqpXhpWZFw+ogBqHk5oMqpiVqL7Iu5pyzbg
beXvQy2EWj9QeDvpKRbmrwOM5yTzoOLlugCUnIeuupia+KSQcDFv3t1XQaFqfIZVspJhnVvlhz+d
pqL+QgPlUYubKny7Pf0rz+C5CJUQsgXjlnbtV/veHknWhLaZreSZDZ5R1QRfnZ4OOdOfFr6Fbi9A
rQcCyHYHkYR91khntE71ULDY/hUlkRHlQ6bF2fGNXi9R3uMWGFwiqlDl3Iihipq5nhtD+/08JYwU
trha8EuL5Tf7TYouAEhXTUdkReD0WaBfk3aAHuSh/6qXfEILYyfBbTx4Bwe6E0RQjL2O+usUY7om
mx8z7lUrIOz+S7maXoRk10Fmt/MikxC+/aNlgha446If8vV/iKBptnuBjnm8be6E2Ate65ap+4gh
2fGtmM5IOK48rgQFP3WIQz40/dywDVyQmvAn7SzF/r8ZLzaqxOarGCL1B0nsIV2LnrESMI1k+y8o
bYO3d8Lsabm0nxn26ln85Ts93Yl+x0bfy+qxjoR51qxbIST0a9tzdKb/ZKbieLViZ6LisbGsM6CO
iwm+gGfggljT/NiZh6xgEj0r0c8lqE81efnWNzJw9lgDj8HLSt0XjCf7dVr3apYT6yuhho9XMR77
bX5ojp++OYrEolYDmZ8oliL0s83vvduoqzOZ2bNfUdg4aOJTvSqkHn4TCA5q8CZA5JepTUhi8gAe
Mh2h2s4iHPssPb6h6hC6e5CjdfVuTLlyGX7kOtko6OZzLT7eYUOLZSm4ft+5K7o50cbXjJD4Lgdg
l/Ben3+Ays3pLKI7UvgxB8/4VAuiwrxhnzE2zG2lgQYZMlYZbSQE/CN5f9NKMpvlzuMK+R0jAau6
JnzPKTlFjM7pNv7VdtAxMXFXa6TH10DSG49D+tR1AueUDVv9hx2xD8Gfji7gcxIX1GrqjMaUxXWf
Kcd/lwHJ2J8/UGXCykA1IC5g5/Pv6TG5IZdTEQXPtE587natpQ3ec0391y7Q2CA92gGMY/UyuSL8
hyJK6rLJCLfDDQVFsH50HZyOBFDjJcsemS9ga3c3I8gEbekuSsKMLcgJCRraSRJf6tU0KdFEb1+s
6t4TeASJUnvafSIYTzJ8wXn0lYKEgVusurwJ54QIWf83v2iZOb1RsbuuuAvQw6pQOtxMhntjSW5w
PS9KSwD3SGcp4jkKJ/SNrRsOXLRTVi76VhquTRATDBDYhSKQhlX5RWsG83MRM5jMp0hhQrVQZfuN
Ko+1AuDPyrvdX8AYNh7+h8Fwm+cp3EWQjEgl8QSyJJ8m+x1xrN2bIvvsGwvcyR9CrWdgXcgXOnoI
M/Pi0yIVCjU/cNcwAOBgU/7bLqAt6seOV2ZcFL2mvkiuiIxLx+eG7LcaGjz+Kbgvoma1MJQ88Z93
Ruq1PqgKpKIbWCz6S+jDXQgnYkf0VmwwvJpa9Fau94W6Sf5K9gzjl9g6wv6t7u6VFop2VjVqDZPF
P8/IdOYQCNINWGa802fwky1H5nO/DqyOIRntxMSCCPW9PShQwhBMN06qZVx4SiHZs8O4Q9CEkrZ6
KyrIMqjhCzoS3Mn3MOOx2gF4GB/g5z8c4IHwL+fRlTfjJjBRyawjLE7wRxXhCyzTAHii33L6Cx1C
jVXymvmbYQV1TOl6yLxFjdI++RLLS1Cd0exXGNpryfZ6k9CjzvgJXExojFENJbXMe9ohacQ/UChb
PlwNTa9MxDRASfv2NrAaXmhW1ipmn7e7lOYRH7O9c4M3zZDgxgYMyA9dw474eD0rsSAIXXnLT3g+
nuL5q+g9f9HWbhBDBKJVFjUJcxQ0e3+jm4KM2+QDJ2OB/6yx9dzUVMObNDY9Q1RjwPxir0uNvHa5
Rf88V9wyf451aZUxlpmmXm5Sk3SvVzzpTWTGVdtzi7wWBkAk+C+Zh4R1VqrhRlVgyzexP8gtvRlC
TTc5+hVVja+VFCqyBN5NXNuk+SGZL6Ra9vsLe9aVTpJGH1yOAEMnA3D3+G5NbpkQm8yjtcdWJw0Z
AyQTCZZcdgNCIBvz64VZQpF8Waz1Tpp45VJxadxF3oe9pbO0YfUcAi+gwX7n/G4xdXkTvAn+y48M
qJNpj688QLaHntVu7lTgo6SdfRMxiEZqdTvjS7NMgoS0XYXaR3H3Dtr3VuSJu0cGTvIzDElvJSgo
mF5BHeICeoTEcdGdRx4AtTJ5HyxBziG3RqcE4ojzaMZhyREqELT/Q+0ZtezEEqJLXLomMIuTiHWn
Zatzx87I13RXc+txcTFV5vWTsWSTLZPW5bFNklDAIrA8uM4/5rM+GfJyylBk2aDQdB2Q1hUjPTmx
mm0mv02HFDauPszqBnc3XKAOgGknOMh1tkt+H7Wp5X/wsVaZ8R3/2rCx+OpYfplYxzxsiptLILXT
qNw/mygHWzaE5sOFYsuNLpULIiEICRLeaCflkiMXZc6raaF6mptqnKUiapE5m4R4TktLavQjVAYn
VJv33eZWvrj7Nk24xH7cNqgmagvydJvf2MNmYhd++95CgPGbV/+cFu/rjJpiGMAFIZOh5dALj+F1
tPXiXViX68lnbyyU2nB9uzGM3CUvKKuF4VooEIk4u0f9NeUB9rCdJQTCr52e0b6VE1zgR+Hxm4vy
ObcPRpwLAhi/uJe2Blmj6mqoOkP3IBNEunpvgyjYWNEhX1aBz8mdlj0yvPKRauCmlWTY5YBybU/o
SbddzQDX1nLf0ZwF1Jiny9n6DMgde2WQxOXwUYp/ETsMvQ3M5DeykYvq+vJ/bG2ZyjpxgHuxW8Lr
kR2Tz2docyrOcvveqO44ekkbkkA0uGg4D8arjIL2B3xCQmrUVC+i991dC8gIemj594hlusRW/ZHz
tSaL22np3bWQ3gYWS8zcU63znq62hN6z8a5XoN+W3DUUk7bfRHvcKywvT015+SfGRxW1y5lu+kV7
wV3XNUbNVFUNVsfCVICranWv0gg61GL8tQ7Bso/+wl7VfZRs3V7lzhD//0hHem/0xyqnOFvdZ8P2
99L0iU3h7lKFhksfvEbyFD3P5ACGLV6K/Xv9W1tqPKoM4UIDNHxsh1Vsl+ltRgUhwH0l+GUGzZ7t
FUiKR7pMM+Viv3dNY/JETLr2AyQuKzrRWEpuJIMBpETm6yl6XllKpSt+akz2OIyuIFUmYzs1oZn7
MQJR+dRHHullFGJDkMSxuR3tkNkWVJdvm1jWckbv1Yqb6U5jmm+WyCCfTSnA+T/KsEQq86u3PxkO
0ZbOi/W3rtVhxlkx8eZ6/Im226//XtIpABDUuUm2yMZnGcs8VG8jCVQFCIXOfXkW+fhRnc5ATiJg
GIJBKRdS6eqY7za6saWpUrEG1ZwBwhd1Hu1qFsZ3Oq4xxEPAuVF8xxPUL6oHu2utEYsnD/kB+rva
db9Q7IEb+nmyYpHnoAnez2g+WFYLS7YIHeQNhjZtBn550hQ4jGbHhpioDz/lXTTf0OHg6POeMp6Y
bNqxOcNdq0JDNZi9KMULnEMq8vPRr3CiFpBIs1Dc0rxOCyFkYXWqFQF5GSlKE6Ea56sUiAbjBVg4
ggQ60QlkHxZShbLXVGynBYdK2nWxHyZSnDAhSAxd/Uok1xAhwrzkMVJur+OCfZ+lONdXn2xIuRIJ
30BOKdjljy3S+KmvHFJ5Kcce4q6pLA910rX4Ck/8V44kzqsW/DilN5SHri+XGFyXeIffp3ytwwPj
pFO7M3r+rJ/hl9jT0T3hsG49EmK7iHPGnHXOsifoDXgrUxLSk5WpB1Mwv+5iXIf7K5kmYqVaD8Cl
ys2fUvumaCrLAHkRmm91fvHqbSrquJ3pHKobJBO09BEg6GOC3cMIk00+W+LYSxpJXunG4LDwOSxc
yS0q1SxBS/iMoUW52gYJWeqOUSgSXCRjILDVF0gIeQpp4cJxim7a9QtY+sqUNrLVIPt8NZDcHosT
GAUcGTtGOpVa/LErNn2PgN7yUNvsGbH25FHzw03cYbjhas7Jll8oqn3ONT/65AiZGR0mXQrAP1/f
LMLl/y5LbhIgi5tsNi7GEJilaoYh7ngnbynnW+fSMLRL8xg/0eZaVX7cwnjfXjjt5Ckdh7ALBc2i
aPCQIqilUR5SwebxF943RfyZkhtAe2MX5ngz7/V/HDSDUs9PdpmFjxu3BccL+HcajVXR93nWmG3n
u9v4I+HndVkEYhJnDoJh0kif1uVTKUmBJXf7GiFxmZsp3NfrvvfnMr8G5atgj3lF1D9xhEcM2e4G
fNK/4BdA+o4wsBtm5HCyaz7OVPCirGkI5I51OAZ4TMef3AwWfhRzPQzPteOakzibL4ZaUrFEDXrU
fpkj/qmZiXc4w7fmNahhEfOR0UryFCSwSiLyiiKZnCSiU8XxDgLB5PosOrQtpOMgaaFHAlSty5oX
je9+zXpaAnSEVkT7xUUEEAW/ipiwd/Gt3ABx49TibFr6RiI0O0n7r7XNC8EyyXRqDFWE98zy4s5b
LrmCdyv7Q7KiEXo7a+Ko9tpNN2GJ1kW9LJ2xzo8refh4l4HKYUxCOJW2rXh13vaTrDLAhE+lYo5o
ijVAvfxpjVub6YEd4vkm2szpG7TOj9luDUbFVVOTJ7R4TFT/NQi+lvETriDyg7UoOA/XdWa7hsYI
rRp2iqjfSMMfDx+1RmBquRPIOL/mCUDKnUIACNJTHLafdOT8nk7DrEe3M248E5/B4hj41i6yr/cg
QOYFDIrq8ZpWQ2ky/ZJrv1B8dwEl3rHYVHaZ1OUT6jlxwkNsCcpDkNhY7tpRXTC6RxQNjGIfTZ/p
7uh584w5qVTa627XUsdSacNvWQwQcFR43VjK+Q6lDV5CN6vJaQaTkLj1LA9g9y+c089H/ddeAUQY
7/v7nyoIsI3is3GwaHxx9Aln65EXUZJu57kxI99U70L0Unbf3YA6+FZhfEuL5VXy+/iUTJMbzgKD
VlDI6YjK3S0RhNuLdzYFJoKBCqLkNKjI9rpSqDVw0ie/TMMmu3rmeTUogE7E4jiVdwKlCYc0GC9g
C+9G6S1WLVtgP8Bm04+/EhDX4JU9uFQ/O0c+llU6DE19/TMsAqMSKiGrKaN2yJdzQNMcp6yvT8jo
eU8XzcBlfm7VMF9Tn37UI6gdphToKhvyJcOxz7S+CDd+Q9aHwA7ZnpHSrJx/Nl1kngnPxjQ7ZzHo
TvdngQOXT/qFcnNZEQOBbsZuNxL3qQCKNqOrY1s3Cp0KJpJfSn7FbjVSSD/Z1odBptEHHsdHbyQs
uDY+WO8XdbzFymYYj8hLaUuJM8FyR6FndcASnJ6CE886GzeKBHyn/qbbinx2f2+AummyGQxyJf7S
eTM2Vrss/xoWc2b7e5VDALncaHQUC2Y1+46ZYEjbyL31UmXzQLv1F1WJ//ThNru9dDYWjvJqAVxV
9GhstaTc92bO8VYspS9GnqdyNCFk0vpWV5Kl3X5a+Tt/XmNpj2NIDJD55RuuzXLLk29r8siNO6ch
ioV8MfEXIXhVv63Qz6If2TRsJVvx4A4yJDzaAxOWxepOi53P7EjkFlPuzp/u1HJy/NZJ233ilTIt
H58nqNc3Tm3QaUicO6qsA5UdXYJ0ouDP6TU9Bzis9bTThaoImRgJsjjJyBxtsJIHYdnAguez1uIz
/No+Q8ah0AHtOcBO9EswmGa285UbpS8yA5j0Jj0qKunopOOU7L6bEvxHsofxRi3JpswT/gV0eXb5
Tdgm1+DQyHOgDoGdefPHd6lkVYWmAdP1gB4bV69m1J+JAEt+kejAclQwTbX0HlvxjO/9qGO13g4a
ffmxxL6Fx5qUyngPGDQ+DGrWcTwnBzTR1DtykSI2tSdWTmNMOj3gIinXIsl+7MJ/hQrLSKIf8Fss
+uycaO6KekwAR323pkIBUOikDkqaqM3DX0ErfoL3t8enuRpieZHoK9qZox+VXE5BhDd/VDY9+mga
5r0E+OQar1JX50v3IkAKigKcqvU5Zsd2cA+jbSbVVEuHkAs234ChX0UfRFgy0Y53Pgpdd/HfFZoN
LmuTTcZN7jZaet4HykQqJ0SukAoLs36RDVk+pyH0b9gjmv5p+bDNWZ+S7kTfmpyVQ+HtBMcEs580
apauM5/1IgCg79PbaT8LlJD2Pu/HLMO6Rjw/P2laj+edzigzkZ/hWwdh5ouX2ckDjt4TGwnvzFsG
dJu0DAM4lJzqzbz8VqhnhpWsS86JoyR1w/ZpfyqM63qRtRkc/S8LyhLBoIc0dwXb0h/43NbYyBvd
dN4fcmHbJLLu+Atz07ejaPxsDb242pjyGuWApNf1/IAok69nyzaBFsdUu87mRluehAVY9LvQBSdv
WcMk/H5VZPwXphhI4v6AJuLHDjWFVuPwOkZEfgxdXTzIryV1ufSsyHjkGjiMdpfTCfMmK4pV3z1n
avZaDUXlRvojkp86Set5n9eop2SipuB7NdkmliA5wnqbBAkPjWC3FbJzZQi3o4xdew8WUp+bEYRs
1TZZNFoXq/2RUd4IKD9jSU0xtGtPw4uWzp+bcUnLiGqESYjHmCB7cDDc3R1seprt+VVvnPI7ghkc
LdosRYbfWQFMkQA+tQhFke3s1VVh7ef5oGmGnTDmUxiHEs3s+hXvUa6y8cc+BdgRx898HoALemEB
RvmS5MOsLtAkNtJ2DUEzMdrGBlUNiFV9f+RENqQD24H2gJx/eEZFoLNFxejUecue3HGxtacWotCR
kXRGwJOjzL4fdrz8kgnsQ14OIC4nWawJuyTSeB9amEbQ84nDlHvHsRZSRsgjozmTgjiSklQDQ15N
0ovo9vmgF0FgjoWbVpXoFm73QLMobdFAD7mVFnkKjnwAsS4Vr9s1yHsdv5zcE92jZis6j9Je31g4
a0mbfCrw8ECFWtm6j/dXg/EY0Am7wq1K5MIWipYu4hUMh8fZORrKcLVf4Bpk1LQGpZd1mQ91kwNN
H1cyiNPdBvQK4GXAV4diTkxvH9euVIEnnWCKO1WsAagG6Yy44hXz6QALtytZwofsQTK5+sBSjvxM
kt/Zm1D16u6T7JDHY1OOmWh+Pw6jKrUowjn+rdzr/d4U82r99f3+515AQe4sGWrSL5OeX1ExJ90e
mnkzcyrXY83cyfZb8dN4f9hBcpFw0dObZoIw3xz5g6UZDLUKFgk/dQS5YXumJ6xIlZM0P7iG91PW
Uh0/IEnOttxAaQr5aPJy4odLhDZ5eBwfoLlMSZIcEaxEh8Y2+kkbPo7lPbzxbLGHOVHTVuRn5+/3
SNwKIhvnMZZL8Riy8wa8uyriwC8ubLkpTDaUBJJlKzFNAGM9DWEWz942v5w50Qk0A5IsRDXxV+TI
h6YX1ymO+rEu62BujpQze3jcsAtBR5ZM8EBfhV8bje4j6jJ6OTIb2CFB0RZ1SdD0/IIXZMo9PO3R
BrTK+NPG5Snk8Bbth8UHmT2JFNHYEkJPjpFV4/dSmyidTKQYgxCNfW4mfO4/yOrTR+7WRmAE5Qeb
xtzKFAaxrcmjkYn9dXDQ8NBzloT0I76niiXPDwZtIfHJAwsx7AkE+N9uLXqrtPEVQyTF5jolgSVv
hHArpdbdlxc03ezYW5PGcfxyCApCpo6qjgJtzX0NKz30f2KXh07wpubO2zXTz4jymfFDlaThhDvB
ufv/gsBFbLF7NhqJo62ciitbutpEnJHxtGKy1NG5BeJD+gfNmFr5QTnXDZ9MiTd0wmhSzodSt7q4
WsbtQ4if/TiCw7XiQ6Sr8kQglDA8/i64cXo6iK9MyhXP31nXOC5uHDihFvBQd1+3aX2MuGdv1NCJ
f1xNBUA5Bk20MjELSiy6XQ+yOj0DT8rIiNGM03cMmGa0jtHzhqplZJbcugRu5QipS4/Nh6HGiTf+
bJn19WFsccUpIwrC5xqB81MnqghV83MooF4LR7oJFJDYsN0yAXWNSUySUL5/fz9/Otx1bhGaPe9H
3jMKgkijIMk9SEwIVjVr23lQwVrxBbwsVv0zPc4HqsGXdNPoEE7Xig9c4JxbwxDBnQz04w+myNEE
asY5XSmobzIgwp8AoW5XpP2BSITnRWf5xtDX71wy7nGNDTh/LqLFoMHwUqI/d6YZM/pawrvirIk7
8uxfIcm58mqIePq4jFoKNZDiRtdRu5BTWrSm9hNRG/7iFOFYG6UVBuI6kMLru31qOgBiQOgpJVYz
Jc+FDXpNCsvZExoOsxL6RhIbKqVClXUBjpx/6WaaCk/cN8+5L6lCTwg5SwwH4URMrmlWAaAepS3I
L7WDvM3jUrQhHlhdC7nZZXRx/4oPuSzGru7tX9SitY7L2idzfVbk9KCc/xUpNw2f3sZ80UPxyuLY
DIAXyZ/bfOONeHntmzsUCNJKfQREb4y3Ep6HvfFLLlLhR+iwXq4DOuRDmO5qze/eK3kO1xsC9q4G
HHVhIYDJDgSYIlXDGAf2XtAeh8YJkcV5wEB9sVWzkOTksk8yzz7edYaIjd5qVqUQiEryUwIpjj9C
Miktb2V9GYAIZgtfzZ1GK69ullXAc5MEvaG7kR577s7+a3AmyJrCmWWQWcfgEAQN3drBlMbvLN0G
Hmbk0HE21NVRLbD5nl/ppjvRJ6b+pvY0qOk5WGkLWLm7t7qAUcos/BYel7m0IChS+9rBfiAjYWs/
TzC7NvcK/FL9AUt9zm047YedG8X+gOTEBZHMhgZAyUAxiHmlV4EG4hCcZ0gRK1gb+mjtYflyZt7+
RpEkpt78Ddoxg1SX7o1bBE5gVvAfKhvJDh8qUdzXaMrfOdTFFoob1uMJ9ku4eGWFAJccGDyxzF0D
A4EASaICfbeDpnQPqt33zozzZ4fpUeqcqU3NbdyYNaDFniLtz5K9Z0qcgCmddH8kqZIY/yFUTsm0
b1fiHDM+7VFd++u7rm+DkK8wHjdWNQbx8XPx0PFy5Mq3BCbTNg5DAi8ojCVzItirTEGnMcm2nEWq
+TkrJpmofLerdhHAEeOccmwSm8Y8gu2atUq10pwTX+5J1kyTqFDUywGdPZjiVouZ0aohL1TCH6/7
UVSuTCkdpV+XH7axfOrEJ8SlzJv4Km1R+HWbow7HGzkXPwAwq+i0UYlxbD34B0KUBKCzpGnP6atG
G9wzEeHaXyk9TX0reI8nCRR981wWQG/BozB5Xy1Cb+HZz12ERJG2CyTugpmhP8pJJD9JV/GUvAcq
TyGwZSFd+ZLpNKuupEvBXxnXt/4IhQzgX70OmAhOLnABPPUOwLsmcmi/SRgoRUjOUumMtC5yUHBX
hDm0XzVYqsaiZKBGBUkquJVoy3EOb3Iz51AbTKgYR3K/gTRC9Np1lLJ4vGFenlZ4OYnFGLmqB1EN
nyCXuet1xtnzLTHWxyHkLFx7BV9WetViwJi6352TPe9GnZ7UOL2KOTQ/KTeS1euYJDg85i6sSkjm
UE56yG7Nl2gY7wLjdOZrQOTR/lR+Blm79jeeol9RxPjpbDX0phS2Q+LxYVYHh4huQDc52tSQpGl3
d7pqnaKz7lUuDoDnokO7aqabIP9zOC4SZeMGZ34HM3qRzWqgosWiKzIDvE2pVvhGHD5fTiPdfegz
mvqT5Yay4vzAtkX5eTl5ZEv6C62Aunv0EGtwWxK0OZKp2zhFZXqfiHdVN+POo3jav90jkgusbZfd
EBTNvvHbWcljXKfCkFgOwWAp6MRid+9sKAk642/A7fCEV5iKI31t6QyXcSIuV3hJR2LQ107IcqUu
5FoB9omrEsTAtY4PwbwvJh1pNmKzEoM4F9xMAGhTpezJ44L/SwDYmcdrx4QWBzZoFXyFg2FtObYT
m//QmZnI70USd8GMg+tldsp7urC+eDO2oe1qnwyFUI1PNIYP8pG1iJpMGziBt6G4Zx+keKZxzyGJ
SVQ9WVmnYJAr2a2Fa/1YoT1QIX05EtA+h/aOf7YxiqmwqGUNLRVMbCu6xq/rjXDpOEozRdnQKJ5o
cQZ1ICUcY4qdKEYIVLaKPFE8SXVOYsgo/0nhzvpQL7zEDDhrKgFW2/bNXZbPULyXzUSHLAz+rlZv
7PmK92KzF9C8YLxMYf1hObdUIr3JgrJ2+JzDCO44ak4zEkbysLvQYswOnn/EyIWSoBvihdbu6Vem
M7sR2p+18Yd5aaW7AkNfP/jGrMErnFaJVwDx7RH3i5sv8yJo/90JKCCtKh5RtSPR87F3ctR7qGK6
cGCkTIK088srZiiar1RW6uxicymHTkSPdXeBFBYRA4jeiIYvP000mdZ8DVOvY+iYERy9gle6/COi
VC/imh9iyKojBugCRbtt96v41zSANlLxq3ROW0R9BmzoTqo9qDr8khHUiYv40h1rqL1dI1bxQ0Cx
WITYyXCqG7XR+FhogyibTHDB9xC+c4dCY7AOUFnjZk3ZLxZ7sS872vv71DjNCbL3yuJ7XouEVuiG
CdRBg02UNinX2fUyu0HkoUVkjkvjm3l/dCRAnZKxPfRWEBKML+G9xyg4omNPxkuT0oic9I4zM5Cu
rkIjHLjf5huomVuFVOmiZkBW2f1S9iV5bhqZkv3cnkcUZFsuynf4FD2VQ/5mbJ2dNmPYL838OvDM
xCNGz7xhlviqFQBxvo7xFsGxeCyWdl5L2YyNoZr++S8S8t76soaQkTBAkHM84Lo9BlH1QxsTi7c8
hOMAe8BSWdy3kGxcqThMb82SDF70Of2IvPvXNCx9+BeSsgKdb9etC2jBJPc5AeeWE5J13bkBpw04
SVnuItHc7A0kExDjwgWimxS10Uvxr2yhEHmpASG7n7AHKKqOGvVfi0BLURUwoyOEwAxuMrWixWdw
IRfOnxGbjcTjyx7Yc8OB88NlDNjSsKgLVml5DxiIc3uRmNUcaMUNfKR+zqNqAoBsh6KuJi4jUOE4
hUOhMHe8rado72LLPCrenGhYhRFgKylYiCrbzMz/oVfuMunrxaVBVdWB1tYs2jv11CuBvRYR9GWO
3vjIOXp1wj5j8bg5/J7cihssE+HZ9TR0oH7fQ2umfRWWtlcijpqaGFOLS9s9MNX2FDrEwha819k7
AFTHkuq04gx8wSt7vX79bTqFwMNxBeiSzEhmO9bZ867CQie4gBYc89+NkbjMuUPuAj3T/qqSJd5J
A5oEehTUtgOKp1VhD/k6JkbImI3epJ0tNjP6CNGTg4gdudDfrRGyeqt7QvJKO4LlFykUcJd3zcWZ
99usq2Nkw6JpYIPhTGm8AmTJHIlxuvAdfBcLRkiIS2YS1YhpGmLXIo0oQ6IiKTG201ah51zMpe5a
TCxHV3Ap57tAj/0+qS1CCGCwnAQCc2VgJy5hUIWCXKbad4KGagMiu5mnRXgD2hWBoae0Zp2NKdGg
mO7eFcqtgVISAWDGR3TJJnyv4uK6LplCuuLn0WaFlaou9yKSmO8MkNIRhcSvqIOoQOkm1k2mtPCH
KKgWotr3h6hR35YG6d1H0NRwaJhacE0nuTU2GwMYQLmy+CmGKjqxnnyZ9tngDZJDszMUFi6geZkY
EijFDZWWFeG/W5ZSrKlGOn9sn/wgoWlyNedPJKPlQFVL9z5OfQKEQZBDORZiaKXzSAdLpZcUaf4b
lvcBsXRMLjFA7tkA9Blzwqx9k1Ib8W+K9esiswt4s94e/jQaDN09aZX0ldgD+pTvGd7lxs2hp2x5
wCuuWqG3L97AcjyGTLp5IbIgbRY3HA4Uk0HyvXsuTWv7xHb/r7ZQSjusL0DGcMZ7sUjFUqbVMTql
sK+xBLyP8gMC5RParpupkqgeBcahq9SQ63kCN7dZqI4a5Ak0xHgOiMGPbDAGz297PseCnUFopICI
24bp6r0VeUdJJPLfY9LJ8KM2rgWjwckG8CTLOtgMpZzhTFQRRL2/E4Y+UocIBH09mN20y6DiIxuK
4n5gxfL8jF+kQv82+WhMRxucR2ntbvFPHOWhGtrXD9wDe6IS8kBqzwQgLS5ty/OMHpcll5zT+M7N
DcOZ7D7FRBzrrhtUXZhegM0h4q1SGFj8zoEHllZcwbroIsdWJzdr3V2MUnbhmiTlV+s1OKgbtLgl
lHQB7vcxBfiRINo0I5USy+801uxubIJ5Ne8RMGTOz2HfwgGrT2AsXiMVs4lEq4wGLfOriFZltBkx
bzVkONoDKDVaxpvs66BuoyDZ+6YYgmAxPKNVZYDlHlZvrJ+9DQMB6WSVNDeAvPr7ACKNR1RVvQQb
8FeTYzwWlPp0scDSqBTUvURbzTHOAyINDLNAAr0S7HsHTgcA1VZ2ZLNrvJbkNxtmzEa6tD+hDl0m
ofpKc/LZSkizoUtIJ/0VY6EoOqMp92u0CaeAFgjkwBRxu2xPZpHG3n+hIXvl4tLlpjEZYBuhkVWj
IDuYARPRI4WCjggIKR7xWHeQWDzAog3KM6Kj26QiJHt08F/pnxGznOeL+yaDCcZVVCw27BhdjK2D
YLPStGUIxu+SN6CEyY+cVyjPVHhwSv/Kw0TNNtHlrwokhiQIWyWi4ii/pLnDpwS2VN+Q1O/kZw61
eKYwRIHFvGi0ZOyphZ50qXwD6v3LrFcGtCBV2w55/7cdiqe00rB5MDuMih7s6adzm5wGwVop7oXq
JlxUBAFPqztlAhbCD+0QA0yA98Lzkih53im8/xaMeGJ5zeAeghOsA42YewWslWXoYJMLea0/mvFV
qmhIc7cqTfgU6JUD6Navpdke1Tkn2p1U9KBj45UfVGAX850Oh8DOWmQrM8y6R97RdLC0sseMJzRS
Qg6EiwH3uVOvSHaqKpimHJCRNfhaFyfAIQcGI/yKa+XDN2WnHskhqMv1REPmTCtMa4h4pruttW4V
XQjoDZQ1TLcRIN1CpQJMCw3ogCGs/HCK3jo8tF2IhVSJUeTLXlYD51c4o8YrMQRzBZ3UXwW5Xs+P
rZARJUCiZ9qMSUK6or0iPtzOAexHIm7KgkU8J0A0z+ZieFq/NipiBnLGXs0hou1D/Eyp6+We27rC
vEaZXNErRiE79KgjhHucfpbf9mR+lhCTVz7h5aGvyWuh+2Mf8WnlWZjrc7LciB4lDImAd8Z3TGQQ
lY28ejpnW7wsh1TWBl8b4tQPu+p7s6pQPIr2CnJ8xU5UfF8J5OX3mRlBhEHSuhgV4XCFeSIHu9oV
Cjx15kOX0fBbiVkPqVuSF7L/7w1cQNFTMkcq8NqUmnidGElzaPb2ASlJn8ug27F4mex/4fA5BCdJ
JayzDtxUzwppJXDAvezrZY5t/Mk3pcoFHfC6rHBroMSSHoFEW+LStR66kDN3rCSq34vRktNA1Ww6
QfXqLYquDPPpNjXASriSKPXcrZ2NLCiUMp6Ja9Gf9M8DT1FaotD8akquAiJzZ5415TUsRR1dPu7x
3pjN0clUzqDMoOMMjI7k5/DHcQ3qY/d2enzarhbQ0/8UVHYQia9mvjJLjDy8ioUvu9ZZPDulhBqw
6O4fyovn9fDXrIqp5+jY17kj8R8BheJn/snQYwD3FDJ5kdqOWILpY2WuYAI6RMbg4mWYYbDkMv0Z
Sjplksvn14UGpPhwID/OtcuqBh5m0+vCOa/urNVsTLAuyW9LjSmwVfuptgvm57XnIu7nnNXYTM7A
gTFzrjprrxqY+uFY3AZCOQMnlUKb+A8kbIuMbZxnex3j7RB2jJYOIV3ngxvgFo2pw0xU3eQd9gBQ
F0xF5MVmhTpKWB8It6jSymAZghH7DXikUigOHidHojvtfOgBrmLtxJvXDaNBMukzFntAYps/7yQb
5u/la9jaA0nCfgq9gBt7R4lASGr+pbAvAYM+u5XLD7hOHqRzt0ECXwJvmhK7JeTR3aWmN3qsi9c7
HFJW8wZpt7oM5GSgUQ7dHboiThitlDapfw7PXcL/eEuRP5hQbqK0QYszssRDgWQlYjMUs0Y+Al2y
GE+HQnoBFiyTIVMYhBZMa0QA2Ij+yj7BVE539YCsSARwG8frAQ0mBIxJDnnxfKCXmwQAqQm5IjDj
tDmruh2WKX1lCbol/w/PUlugcQMXoKGwv07wMRX+QkES1v5IyC5NtRmKI0rWIHPFqLL6fqArNRjn
AdiqauXKRBt7fbvVnp1wxvhsWEDjeJqd9ow82OaqcIep2oZ602OaJ2pUZoWS2v38m+FDZfvHYcvW
YzoalRpHKyHWVNzuHsd1HXbuHqzW7V48hvHlzmVheivKWZK4yVgAwJ9xWedc74YeCwBJ04H1TlfH
O0jUeun6Y/dq7/9KKV93HjMQFL+UwRgWv1Nz7eqimFIxVTK4LXqsR0nbfOkg408IZzdBUJ3muLKd
81tlJpX3uzWG0rmA/rVVqe/sB4Y65pyJIQ5q5jcwalyVqQS/oAv7pxAcBAVjxGVEHw0xP5UaOlbU
x+2zjhpA3NgJqlvmQwlNVWTrRyxRyPuMNcl1fn3p2487Vz5vmgD0bsOHxVy+8B5ebMUVvVQyiOqr
rJ3C3z2mHLrQuUKbq1JUeNE4QUw6FWRsDIJxaUa0RHsk4nRquOz3Umg1C9no5uor/Evl3RGkHUie
pomQcsNL+Kx2DcNN6aHDooxOer3lzdLqZL50vEeCJ0+FZBCH78L+2nc/rTIccTQ7HOJIXL+5A07s
dBC4kdIGSO1ayJxPwlx1pma7YHgDO4qeRPmvd/WvvD+X1ts8Z89A3wLyErSo5a6HSueb/trZD5gi
UQFWPlFuSJRD6X4GwRKyMc6nLkG1x8XjuGz9V1eXvrmZwhNvdJKWBAhLZzCvzbw9Spa/Y/DAvbod
U7Ejxa3cRjbOwvaNMzDUOed0mLO3WvWSYPUVHakbGyNzn8HR+A80yGclVdreqU1Tiie+imuMOGSg
EuiTjVdPQxkREq/FL0aIH/9h3Q9sgvrMnQlr20MGFRn9Ywz+ewHKSBJaE+sRGpkeb4WriJR+albm
8Oy8UNSPfeOH3yEBbi1O/fa86CepZhzyq3uCPtSvQ7gRW7rsHubEzRODEwa9zY4V2Mox7sWWM1Li
ZLS1fF2b6GmgMG2S+kEItBp6TQMw+YQVEtk7tYD01ip62L4UGzB5sCnCWHUpDyncySuDucYFd9Jj
JJ1wkKWKtiudbQaUPuvxRNqH06AmXsbp19VqUdYw/pzxlcI/qYUCU1WpwlKTMjgqgPeq8G3o4yfc
8SJbpTfoG3Q9TtbtgbhLBU5+NJsk2T+umHfZ7MN9eSaN8k18NTpHHOHwMZ8E+2UzD/ocRTq6/jCd
Qk1bHFEtwJ8x6hpRar+C0PiFDfkpvt3i6n2AVZTXuI5XaGqayA+2l1rHgWDZEL2RwkomlN9xyub4
gdYaJpCC8f+5VkK4SmJ+yNImqSXmIWpVzcnaWt6t5gqnVj3vhG6zUk7k4xkicDt/dODp+34uOgKP
87KsYWKy58q/j3MiiNXH2MbFjMB3APUIV7H1RK+TpnS+G7vsl2qhOoOlpu2YFGMmOMRGzSAi6qwx
/HrKrdNQJ1thJf7smw9KdmHPAe7Aa55Grlhb71WtiipYB4gvX2GWq8qlxi6ccrRzvKzyARKftFs7
/e5bjRDhEAwnehIGynH0s9oiiggtwjBPuo+CziWSMOmkGge1AAt8eNfubM31aE5eQUnhDXPTrdRp
NfEAjBy8otVrM8pDVEKPKXuM/Zo2r78OpHvMkOV4HDGWICS8xZAVVDgjwTqfrJKtiACXHThdi+jQ
XEiDofGAjUXWxec4iyJ25c4Hm7gUIjgG2O2AlhilWmR11IyVn0t3eNlgbXvGh6deAPRP1oUvWo8M
lSdFhbV3oUbjz/TBp5uxRWrPXsLMUEqzdWvbcg8UcjtnBbyq5ykjVQHgGYFekbagegr7QM392Uf1
4wk5dBKO0O+vymraNYBhWduEl37MYNFAT+17zgaUrZFN2z9rvOf3mUotAFHQkOhZXnzjbFFGBSei
rJbNgCLf6neSRd0iptJ71qcrIK0lPF8Efu5Vx26yWSlGuizo2pgSWl2awbEPZXXOapt4vW5c7hqP
63IF7jKxD5Cwa05fSvqtwLdZIOLMF1eA0YwUvSJVx7E95gp7SXcUymy279CzugdCCK7D+I2+DxKO
D2yV+5X5SfM5mmhbt8JEj31ycQNfAEcak2m3PM+GpMEQQL8MVH8p0htcnmnXg/c8pAEnjS7iIKmo
X/TGUveC2W3t6sJ7foMNn2lcAMDS71lkJdYF2bJkJoSrE2QrigLUS/q9MZkJ07cuTClIXZvWMFCC
8QID0lFZQLEAm9jvjkd/ylMjh78aonb7RU2CZyahJMPqPeKgsHxRWOmLw/JTg5iGFdklFuH/M4cP
CNPlYJHJx+YiFKRc3nLFpgwH+GG131/Z
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
RhrbwOyJB1EkxOJx3ABqRk3Va+7K3EJHZVPGIcCoGsSMnOOGWH7q6VzPOfjcK/djKPO6aFBoil75
jQwswaRRUQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
LCTlbuF/Pe5PDxJKJwDmFdDkdDk19GHdt378mO/YQltflOygDhr11gCVrBzfYS02NHqaPd5/bySu
7JQ7BQOeRxRaz6kOAXIywiBhmVX21ozJpSD9YWX++cpoX2Hzx21vie7VHdBuVCd3dcSrAK02PIh3
KQYQ85S2o8AzlKpsFk8=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
o83p4yh0oTgLDG7Xfc1wgs4jILGH1Afuo6ZEi3g5oOtKQrlkia8l0l+AzK0CZN6geQVbN9v3By8i
WzYycokm0wzcIz9ice0LtKeT+ax0xhsgQnz9Qm7joJjyaXidfkKiDSXWs9qUO/5yg0ocMCtuV6Vy
X+oPc9kihxC2JoIOAIk=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qFbja/sHwn/4C9HJKO6mwiiXixbKvz/pY0uQwgBSvdDvsJnVpURPIZcd/6cPrjI7jCb2L2ZYUxjo
OD7e66fAIQ4Fg//zuIIx29BHdcBxENfBwvxV9WMdbgO5JbeM8TDH7sUVg1FYVW1Cj6XD20DFLK2d
vwOuv58tfuLH1qA2IJy1LreXjKAfnSYwXNNgkWsLHf0HNlF1BLaq0ZYOS35wQ0+LX50oyZIXCr+N
JkR13JyuCDomGP7fERuhdzE04K1CdRn3rjEcsxYOwLOnB0SPSbBj4lBx4ONU0cfvWBzoVcsVMIbP
m/ybAvJlXM/GrDa69R8Y8Ovx05heeJoR5H+zQw==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
fvKvImhKuX4Y0Y6AUieBoEW5oZj1O6zYwY/+HHrKkKgaM1CnSrcODNJTpm8quvRi1mZX7OA786d3
2FySSCAI7NmYiW1tWydoja+l00gQTFMgW/UrwN5E4V0JowxqUF1iu1epVZ+6x/e25PvEtYJ6tlHd
B50G3sCwsdy49pORs80wHiIjPV81HJpnQ5cU2wNr9Sym935FvXHSrzPAmhKxjh0sRZWkS8X8pJFE
3vES6QHURg+O3x6fyl1zEzCdtoS5kk4U4rMYiK4DGLZiLIBWYSb7RUzVsPxP0Ad6390hx+wSZ+hX
AIvESkLWW8PZxdjlqiH5uMh6bSBOcXXXu8FeRw==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rx21WDVFigb5iRNmq/GF+n+tT8sAt0anxbVCjDKiva2zVerqHXLBxWwmIo8ZDwgQwl6kPSNATurf
wsLl3xuYZbupRQiXSV62L2j7uhoTg5gdexW3J3ZgJbqydyznH8end92RJqs7XFidLZ11oY+sBEX2
WZZFU8tlC1UZmwKKu4UKUHOIm6wu0Nuh+yeD4yP6OiKmRBn9y40bNX6p56LkCggypHithHpqzIuX
hkij3oeZERvwFCR1LaKtiFF2zdqXORGlBWM0qYixWDF+Q8LzHHgalXIl9W7A8JdruB/VjFtsacGQ
bADNP9K30JY7Cl4D9OCU6Jq1EhIksCcjUkhB3g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 119040)
`protect data_block
aI7bWNlUNY7c3ZGc2pBm9hopUS7X9dogWjraYv5tIlivzz9gczwsyTYslt2YnJ+/LMUD0nXdKdYR
pIOJo/aWGlROGQNyxtDvDPMgCW7a4DPe4d2FZKyxCYU+CQOcwKyYKPMu//M4Nk07v5nerSVaQ7Le
OdKRx8fLib7Mqz+v6M2QfuG4WiAH5mEZMrMYGvNc6cM6lzrDDv3Vo7a4QH+HgtmYndaMRsWTsgUV
LCdDYAfRyVZLLHoT5OUk/Z+g6Wev9BpvlH1harOy8yu2V1ObxlXarhHEAUtInUsg+xmZa3/gDaEd
h0y4u1D1dYYk5K3bwsKZ7TqH9qG0MuGogByVHGubD9Wbf6bbWI+tfdCRfFRkuAlRANSEycVNfo3P
dvDLoCKNv+fqlqATA/DirJlE4aeX1FGHg/Sy0vJnD4eqTf8y4RO34KE6Pvb7M0PRmAy5XsRDV4Zz
ZUHzpVCDy0rQl5XPvf30t9DFPzgQ6FM+B8uy3eZDgxX+LPa3HTzWL9755yXRXxMtu8bA+7kuAIQe
w2vRvE9w3z8vs0PKdYqKQprhC+fJMG09cL4BrJdykfHiJNBtr/bBq+WSSVPZfZb3NZri+LVtlQ5W
jHJMYlSNitgjITDwAPMvlQQPz629GFt5O2ia7KgOuPF+6iQuXxZY1RCnj3kp6HEugTHcoaH4w7Vj
JXDcb1BaaqKm+Yai4kOYJmC+zhD59QujL5xgv9Rck1BDQgnz/s0hnxDtXCAVBiVUOinMSofPVpG3
Oh2elmXIbFm6Q73lpwzNFJEtQl5cQRg1up1wHrTJ5aZHJSP05vyv3UJQxKd6uQd/o3uRyBgiHWt0
65f89jvOJbql9IsL/CjV+STNpy9RICtYTtbzPVXcxodX8MKdhg2RA8UC+WYoOGc2lMAi1lH75FC4
LP1jaW8BNDH7US+A58TU+vyCzp9xaemgiaHwAYTUj7Rvh/K0cljdPIW+FZmDXdq/YiiR7yHG4S9b
UwpePm30esrpmCzC4N+NWeuhdgHFuYCfP/IfyDP2jtD4vyiEB2evaMbpsSMPK2jbwI/thbF5ZesW
FOFifXwxCksovXO8BfY8ss7Wtmwg/ZGOr78cnYtbJvTKoGIFklrHDTzADmyqQVnBclXwVcWdG/oL
BWoUPqGuQ6ICIW638WeVvTLsShCmHFhE19G8gETeeBqmaiN9OwIuBx5Wbh4W1V0HF3iGSe3rGRxm
h01hav/EkgtONJYaIq73OYEH/5d+BvW94TomD7n4YQvzARdLreD+xrHNKOlnPBP7mWiNiRpR+MUG
0utyazgOV/G8ymwzMEVXEavYeXP0sVR9PAvJOvm/56pM+q3i4iYZ0qJbHgA0hoKf8L83AghefJwu
4bYMPpHTLsAAnMLQsKtuwcLTmYKsiCZBl0lAPGoh2R76nFVB53R9rx1L4sKlAbUV2pxWQRGDpPNy
IquA42Tm5Hc6cLxV22yKiugnVBmKxq3bphkP2K5Bf7iHhSM+MjJJ5PMtMS6C6bQqdoMeV6Gt1c5x
gl7fcm97rx1LiFjx1m8K48Mznqs9zgH0t4NUU2QjTy0gNYiTx70fny4lBuAHVAknqUvzZqUKfXrz
D18b/rSoCRLFHNo6zLqi9d+6PsJSvctXBcm990cHlx9gNKrz8hKpbLQLAeLxtIq9lfFvSesEVTPI
HAj6jqi818uv+cD3r0HmWj4Mj6WzLQqgFkEUtfB0vUl7HKzYdKaTcDq5aSmsRj8DFP5Ry8K/c0VF
4LTTdrG8vPku40J4p6oH6LDVs8n6J0+FPbs+B8cPSJJoF+ebe9Fg1xWIwNzRVYS3Ren8vMxtjka1
nX6eZOa99Ll/+gYuxI7vXo8L1LhsBhBUyOjBvGjZOZcV1VqwqYvuLlUxEwsYWGxl0rj1cbHiaJz2
lLq5LNQKn0FESAOs620rUNwEtn08Z3Cg7VtBd+SdFQomlmpzyDGFU54j39yIKP7EFPhB5FfSzIUU
lsaAF7qCCucRTipNYbD5g+vmeTiD2X5HDgmgoc3aBw5RG4T0/CiZzPBNIcz7NFNyTedmE+1HJI3q
x2gIoEqfmbTKzw9h7pokjXsPZB5CplrStcimcWaiASptWEISNoonrCKFffatvIbK/QVumWT2yOrp
J0AcwsaExOxt9CgrNtco2RZrszF1Vq3bTB/KLwQATNoNYR4N+S8WAYfUyM/CK6dObGw6Nzj0Y0ML
6eAztsoaDfnsVo3N+gVIOFNA4Itc0tQA/dWMeNt9phrAX6LJqWZi48I0rjpIw1dYq/LGsr0M0D0c
ZIPqb5fWAf1fnVCIgr5MP7QIncykiPJ7Zs/J2Lo+gLrGCs2FvhACYdl7ub1a/Pe74Pn3HdytiBsm
pMPA5WhXo9j4nTnt1/CsELRA6JoduqGWStAQdcyr8GUWo0Bg5NrGU8X+9R3AXd7L5F0RDpqOxblq
GldFv6ZaB2uBsfPqNYtiwonIPClfUYbvDFUSzj3e3LK6by4aKV910o+qsaBtfkOyz4/i8s9ETCJG
RhYTq3EeGvg6Ql/5zjFyslGTZm0C2vFxM6V20BttR1vV6Yw1JA1pLBr8vod6tDA5/2qgRWN03r/a
W/tswr7+KaqiOW19hmvweCAGiHkH+eesnYCTZuzfwI9HMAwhfIdikIuvxv6k58vS42oFcO8td5eB
EMFTLMcmiJoXMbm0nS0zbrZA7GogD5oSRH02bW8KXeT+T/GOrPP+MgGxpSr2fWe+3tUXIXpy2qG1
5zkweA/aY2Dz+dPz7rFEUnR/oIQZV9ngVa58o0xQ6EcbmhfiqCPaa19WaMFnon/dwIs1E7VtpVO3
bHgLCwXMoizr3J/ZZZSy9cdUr3hdjNFqnOO1zgIrBbcU8b+rTr2Fbwkr3yF0+iruXhYMTmv6je1H
OHoFYAfzrcvr2K0ha8TOXU35kQ4iHSzKXOScp7FSWizIjdrwoNDg5STCdV8YRLVF+QClpOeNuIOg
yx66l7Ok5OATJdfxQymZNxhDrLM0PnouDA6jJd9yrDcrNEja404uFQEB37OFNhNSJ+5/OVnXB7VQ
+v3kBBU/iWLwSYs4+JSQur2H/cHVixyHYBKWXgiH12k4wNOPhGRx8sIxk+xZfuHhwg6r1LBq+2L1
5Nh6mEx58l4tJdy65zh/GexHxdBFB5eZh5mBHss0MrHZqu0EL1JgiqbSzcs3QX1xZXerdyNUnbHx
diLMmSGhKR+ZLiPnx2cItejFRM17SYDc5t/i5iCM46Ei0I8U+v/Cpe3Yw+OTdNhvjt9QQKuhLubN
8+pxnX7eRCFN5Zdp1p5S1YDucsGnYI0hudU67Ot9mDH9N8Lh1Pqlj4OnUoY9ak2ZMC6zESPdL8Ey
UyFwljmHNbCd2iH5tutiOLc5qkJtgjbboZj0bWEo/8yWvQys7mmp5Ts9gDFcRPkpMkizITlxkbBC
I7VGbgagUttzL6TJgA5+T3YcbEKDbYjLMFkQL3LWljL2pvGZzF+HecWv0dLltcGqjlQPmUPwJwoP
bq7lF17szD+91/FS4YDEAZhRJqORL3uz+o+d/pFFetxQiAImbX7IZ4eHMCYV3j8XIHjyJJcKqTRB
0v7pAPV1bX9yb0dOZ2oDwf8GPRGRvo1RRkCzhwa5G6Kfn+ScZywr4IGXHkQ0Pl2yRTYEdC9yz4qU
3JK6lKgqmqOcaLfp2YSg190BzeQeJsEGRf2A9cHdZkTakngKj1xHQO9+E3uMkJjJv3jXho/aZN4w
EFaT0XYgkCEfU7oCkUn0Obv5oQ0oCuxQ1PkVL7aqeiUL8QhoD0RkGOCt7faSpw/tUuAwvBA1icKR
Ia9muGExd88VN3TjbcvaTruYnCZ7XE3HBNcJw3UB5En6gDFDGBJ7ktJpAHTBQ9/uFawBi79Q38VK
LQYoLCn4WODfNyy9Ang5RxojMcZcBXSziKyZL6HlQ+9C9kitYesx9juQHr4G57CoAFBteKlMFrxr
Ki19ujOxu2lwnESO6Aev4kvlg/8tB85vt4cmG9l1SPPNlvi2J2eGZVBFRyTZGETF+YrdMAmV9s5k
95hjAWGG65R1rA9XQEImyazL5An9vwweUzsbj1WSqfH9KSHE7cx+y/ONtcJ+VeC7MD8qQCaEUJ3F
rnjSXu4D48d8a52/deybiqEp8eQaZ3wd2TeTs96gE78mlWFy9bx0x0jUhfUrzOlsW45frs3YARbj
p3tKehq3Y2bg2nF8YDaRYpiRTFYmVWSrI79zvQ2BI5j/RONzH8EwiDVNmjrNeC66AXCx7MKcp7ET
tsV27AL0GYF7w6bTTv4yLi3flNr+6MkIJUCVBbvhUMQvGYG70rZ4uK7uxtBpYCQO8KrJjju/569U
Cl239/ROV0qTn5ieoy9xqus+YKR7QzooxY4jlxgU/Pf4pJeLsrfKtqepWJ6KgNk50/9NtNmBjK78
FVBZbN7INXVlcgCWmiTh7fPp56wo24PEd3XbrEbtfPprjr3HsC/dYuhfaTrpFSy3PrtzeiCkanBX
JO9TCiEWsSvnu0oxEUhW1g26Uphm2zTw8s1+3rI7oRd06bkcivoIqJhXtv2F/fnGGxfT/1jCJlm0
BkscXgBjN47TLc2Qk6fVYhUMr4I5F99Poy0eG4IfUqi1lXuSg2bQNI5HZLQAhdl4jIWh6z/REovV
1/z0OCSbudd3tqClDYwpsefk6SYLSoWDH1Yb2NPlAyi8jkdsXoG65kn7vunvc5xzeEU/FXc1q8Wm
vEUS/F6faHae3qnD4Hb+jo8hzZX6BIhTyVfootR6yJccvZRdR3tUzNMUYTAe25WrB1lCIGh//7gR
n23/fOPm7fNLayIqxpwOLwJeghnqZSljtSsi3EE7aY+we2wS6pRn0g1g7ZzhRJD2r6KzBKLUIihR
B04YZgM8wcX2ddArD5ZrwNvRbwxuYj7vu1cWVmp6+sBD3bktfkCqhIx3b0ZF8a6I7h9x5V+cGjKK
VzkICzY8350nkEutXEIp/jwByf9Y9hXJWbaGOxba8lF14FvXU8ZqV9H4ZWXR2HwpBafxkQegr5cd
U4XIiIpwwvMwFDhqgRe0S0AEvDMfhQQ9EHyUDH1qffSqaUR0nc6F+Po2QJaK1QHzsPxmx5oHUzFt
a8YN9YdPwh6pg5NqNCoxdogyx2uhZx1j0uiKuAcmkGWn1WvucC96WzfMxLSbNhJnopWQg3eSoVJr
bDJilycM0+Wom/CwM1GC5IQwEim+6Q+NTtsw7m1tHCvmBCWsF0Q8oSxw1tjMsapk2RY9l8j2kP7w
6uPP7IQnHq+ha+/7N2eMjYhzouEtL29A9/4np1XhWDgYZ5pBJq8DDRSGOdNJqcy2HbQE/fKTDfds
FAc4yACFHGG22yxD5OoD/ibLGR+zad4WSIKT4sb4b6si7wXptvekygVLb8i0/honnC40zopWpEQb
/xVhFEh34169FdeG9mW2s88L3lQQGS/NkuRraV4ZZkdZTZ//nN0XanGxoePB8TXNjK1Z6HSlcX2a
f8yrVJs47WXgj/pWPrDawMdEHeUGBecMfUmgWJIDQ3eGcihaz3XvbDz3GT/I3WFcElGFWf2bmbV7
esBQVWUzLrQk92AqueeRH0fPz8yK9l6Q1oISDVMnP57DxhaXlBUINa1tzzzY5CcG9DHKYBUcT96T
idRrxNJ3lAlpz7g5/KIP6yHgvhJYxpdrPWQNxVEOqjxJM0jrLEYcnPBteFE5j5Js3DO1vp9JGm7M
GrH32j5berycy4I7THaGj702gmwsv+gomgl28sZYBbD+MnwUnJZmWjcdltvosp077NXZH+62AHe/
RGDqXM0woIcAHEQf10BZEr03vecsHCFKE1PbSyWKVTw55qF7zfViwvHbvsQ+cnzbGqGaiU4yuZGO
tqVtc7d74CcKkcuWWqyJ12AtceV94Qzox0vj6kdDx8FNTyG4x8hFluzRdPPOJ5JTWsI0U2SdOWwg
hzUTytZ8MBMlogWSArWswaPX5TwVEgcLVtTv3STzy3b9UQaT3W3gZg00LUPXQJ1dyMyHf9T4BB1E
YzsLJkfWykMFXRUy9Kzt3fBD5qhFdL0d+ow4Qj4SaU2p9+BNGwIWNnjmvbzimamM+FPk7CYsmg8i
PXcPDIicie7+xEkq5LaY1EdKcayDBjkFHxKcQyQ+1Ul+I04IdMRXvH/s8bqaMxtOxxxfrIl5aaDl
6x6U7kaLTkJEwzi/X19JfIlhfZJLQa+fy24n70Eb8fSBIbmSBedmRtj192zN+Pc5UCaL/Eh1MkAP
k17rsPlMxQXGFk72T0Y+4mMK9c0c786/bVPbHAsc+jlu58vSatBET3NLH/jPNRys55a6f/vihN0F
tI/3DYEjdKl3Pvx6JUcLAcHWVkSf+MV68XgmCnv2G+tPEf6jJvORsExBvM84QhEoRgqKCFsV2TfM
wuSVa0OlFShzTy2iZNd46IEu8thpoQ83I1x4TceCr481lKbmiO16bgXt9u9hApDkix35vY08jz+Z
tLZ9zwr4hpjvGHh8/WDtkQBlJw5Bu/uks7BbDqIZAmLq9UcMtT5BsfkleyJTYGKRmuSLLRn5qpOG
3B4R8YT2AsNtakYRh97PQcIwQAkWCa7PvfKHGyAlp9G4IlKH66aYAHWVDlxMtqVcDBXetY7BWclc
8tlFzOVOKwPJ3Vy97TS3AdR4nH7Ga0PcocRdGMk7YE1z5M+bEfWPG5Yt4Ou8oaEUkuPC8bPDRdzZ
VMIJDc2KG856QKUJnFAEgJTLV3zHwukr4Xf1ip2PrHIA3jtyBXXzKOvd58kD0xdvKJlmQmZ7LSdC
CNzImHzgpH+n6OniwVQvDY71qwJST85PsYRzHzUkpUNyF8UNrNbzdrXfrmCDCkPtJOYOQjc2hHc9
RC6OJd3Q4eXz9vfuIC0Tuq8sBlQ0VC+QTfKZ3Qd41sWceMemw7GlUjiZ6O8+YMOwL48/zi8ScvTw
KRVzz3qWtVoK/By4o4K/QWD1BHZzSpNrvHUXuc/7TvYj9oeluYYnn4H9tZ38PYPjE6bEg5z082MJ
usy0WdhZPuhNxI7U4wbUkOf+gxajXOQ2DNpyzDh8XGSXIb8FRNClrYWQJMSQ9pirNiA7vAlxFvqm
BAkEYzh+JlhZeL0YJzfomofEX1DOatO8s7ysexTTovEnVzm26AjipWiPHT4vP2mRmYHcfDZmAYwR
wV1xPvsh2BPcbVa0sM2SErEXgOQ2ESk8vRxw4I3+q7n2rQ1NrkHBeJrveRcnFfLUpPbrUi44Jb+A
LH2XeJoTeZHHFkTpL3ejttjiKuCE/sJTQ6jq9FKZJcmMJVqftLkHCaC4hNi4ciB4vk6xuYzzU9Nz
8YlkHDfz13/5zZnmr3p7sjD1ZqiXnyH5H0nkPkbtYGbHwKDYUa6dKN/8vr3UgLZda/JPnKDacNxg
OuEmdRcZzyJWix0ct1OhgMMDIBBX/FEEYzw504SgSzbrZynHMmm9O90jPNH6yriqJLwHxZCsJXeq
wSU0+q4R27w+C6hvYzMgZ40/l73kMujW26bqvuuSdO3p8lspsG4oZOTK58PiGW49V2uhWRdZrpDc
d/PnPzVLlDghuUc7QRz+0gOxpNkdtJVx3Xznr4Gu011/hqiJrtnIfGh7qaAJbzR1Jjc0mgy3KhnE
7FRXIVD9vBDM5sm6tmLUicj/nfCIXRGb8b3BTy1j7Q0P4TmAEQvLLCQDeCN8Sscr1JMsAuCHE343
ECJkCufLaeiS6Jbl3Fvb5fr5+pzvIXEcvxxV3jqx+Xsr1RuYg4Hi5ucChWCijJQB6SbXjRtBdX4T
sqbnsQ7gX3TbNSYqJ4mLyMDIuOyALj+K1fUmGygqNbLgZOXunUCmoObi7j9z6/BIKJYGBAmMiN86
4mF/acgqnaLS19mg0jz0dX42CqGbjcjW6fIMTt7YTpPJLC1cXLOlDgeOcFku1xX/OQovP3DBrJXL
ZIC/2H4YPA2zFExyZNYZw68oqYXjTU6T+quxWjxNfZIhqpv5ksj80mOj6Y/npijNX4ioAFQQThb0
hNkER46/JitttNytSCS3htueteG9WLcMTuF73CM9pRPeOpImc5gBpNJzy2JJLNBBO8lPjh79zF2m
X/tBAFx8rAOzE25NBEW+8w5txt5/eHPgCk1diRQEkIF9ehIPp1if6JnTv6xJ0lSl4k4LpZ08KBbF
ts4FaCGOR/w96auZ2OmPTTJAl6lIGxKDVWiq4s5SXkiXhJx24xj/uZxm2XD6zFCI/K0VLFrZnQLI
9r3qEOQ6ppmQ4HUn+CCIMGOxBmInw2ggdrhsJpU1pHe97sNqDY283o1NcVGLLgkPsqAtOA91tRDT
0Kcb10TSCyGwxC0mj6b1UV1G0FA7X9vvvMh5/DbEjKySYeJ0mmWV19iz65ae4hymVvMQ6pwirLS8
BuVwbWnePtnYkPgbVSf2/7i5XGqqGuHIG5xtSq1lklHvr6UCMwTFHpGy9O4KdPXu0nfF95rLg18f
5+N/V20jLN2wFpp8ghVnLEshKl8ZXROqfKUrVyAg8cE69bKo5WS+DEF1geTKD9EOYhQ1ak7YQ7Ur
/p4/DJV+UTqZkCIdbN36u37AkHjVHhavXZ18Ow23pfmN5AAt1oMqkf6JPhl2YYBGW+BamrpTwIgK
m+8Ggg7p3RuefqqzoCeLftKykmtiIRo2OFvwBGyWsA9NAWfJ71vkaJmap4ztcL8+9ZcTk3gR/SyW
T+8ArRz5dBAt4cmaAkYlOEGHwk7opoaMFcd+1/Z5lWzMXtijCIH3LcH5LWv3XHGoRCA0BV4pdgBY
rQru7DXl0jF1+qb78c/thAIjH6vxOAZdEGXqd+yd39ZREBYxPfOUxL+5vo5eOJ4EoZ/q5+OBxYpq
ImtQkuphewVyWA+HIwGIYyM2tTZ9GUNtdwp5bXJBf8Wnvqeyjo0RVxnc9VOBU1mD+q6gTjEMy8q1
HpvJGXhhJutjSqdBA/gc9jgkov46n2OPp6zH7tW58yPEZRxJ+6hK9GRXlWWt1GilIjBs2yAgLtr+
r1Nk1QJzQQgTtskI6227lNWvfODYHK475Bu2OOizg9ebPVhRWZ8IQpjEGJRR62BigqfOkZYG1Sey
3Ud0IPanDWDPvVISnQFOOnyxM6hU8JkWjAbkcfI70fK0E22tpZCFQY+ZY+e4WYaOTmh8DpLRYt2r
tnjl3ohePF5KhpOEjA/CVuAxpAzWb+L+qr4XJdoaKEmzxgcMJAzLEW/E7MWkS+fUlSjEh1BS5OkR
Mn9/BP5LEbhrdqOU+E13NApyFySq5a6aiR8UotejM4ZrnM3olh9F+YVjKNIDOv2PQUCgWlM2GW5c
yKPvbcgrFokxCtR7BFqysbJQ8BUCflmBC0dbfNkX/+YSn3Db+NkGch1pfxYrKs+lrCBdUV6GCFwQ
eyYooW9rYF2N83AKa8wWMrLTzovRIK3vswuPwpJoLsaDe0zEaN4rekfQJdjzma50GLgaS0sBkxpQ
Pf7Fh0uDc7PCIDbw0fktpOzd1daBkeBW1eq5gcU5veGgwQcRM+qf1g7crpLQ6E75Gk/pWGGZOn5v
JKY6ft32IWOcp150g2YnlLHEX30JhniVl+yF+/LKqNc2M7QM8NSuxoQ/ika3/IV7ScbJD4yPFNNp
g8cEBx/Kgwg3Kcg6UObQJ80hxKr5xoGhf/OKguVXxoMrwZBYr7kCQf7fnOw8v500bl+R5/5vxnSZ
WvGVC62kvORHraYeuK0lOXKHum4T+gY+ksO6+dauKl5YTNIO0DRwybHi0bey5Ti8KZia3uEvcuCv
JP6hRmVXbNYpkw8GNybKz398d4Llh7wb+whmWafnfN2C8uGmGQFF6HtuB97Ec4MTzHx4QslQIB6I
H6i1vybIdSHRv1U+Cmq+8J71jsisoa+1GnrT8Yb+lMpeAmv3KqZuRay5PfiSbqMRxzGp6aejjlPc
VHSLLD+VpkHZLuZozXhWFdiAeTzL+XQgjegTvspZlYvoE2kdpROwZRFr3FVms/2IlQ6zY3r6x2Xp
lCBd/e7jRCQq6sO21oGq0s+tZv/wzrFnpVMBhyvsSYZYgyUvXHoq6En7nXTbYlbHZbPZ2GoZ5KBg
13kg76ZkJQxd3qAZ288rdvufzqnvMNUAoIBhJkTT+tDC6fOnWqlV+8/cvHdkptiFYPfUWljkX1Yw
xYe7Gq7cET/eNFKC5LXOa9xQ6DML/oU//q+AYHAJ1244c6cHZ+kjQcJkfMrf8A+7KllC4tcjcMyX
5sLCQo6mDIQM4LduAoLfVt/GxHbQKqm7iHCjcd8T7bPXmDc4E3VHZKKk8DjyPKHEEuxYStY84ph2
MAx4Y6LOM6osOKnfiuvh8mI55vHVKbEFQudXSEnTGpYJULr21WbB152XyDGua8SuKFRalcPdmAfm
vCcrWUuiYjA7JbkChp97JjsVzJo1Tq1N7Rj+thiL4tZN0bnbtv5XSIAxukca4GDPYK7emYgl2KvQ
MSlBOOnzK8qtwLnQb6hKbWjYVkyXY0dlHmGcEfzLhzYWcXg5PgUqmM8EIpSf02ZusYIOe+IsOgXR
1PDrPDqFzAr65J/Mo3ISLGO73KRSG46HgAIIUNLSwqRWJVjGtZuTvZzVg/E2WTBO3tSRKHu0E6oo
NyO344V5/ejUNyl7vrSYzWUSkAybPgq2i0NC93VMuHOsxA3XyJTo/GmPD1RLp31SFIRNi3w+KQ6g
a93acJYyBJ1N95Kzvaj5iVwaqOkikvXC3uUKfE1cQjpbDnRapxwG4zGif5IRqiT1csymObzFoP14
qaEdfY3BwU8d7kHvruwYJ9xgoeFjmPLZChZX3IoInleWb8lj3O1zMNsfMOWtbwFuf+dm7lubXF1I
/POsqnPxlm5g+o3bQ51SOD8pueWg/70xlL4ZyxLUAJIBduScAPb1afDTxwKlcHLYC+49+3jb0BcX
GKgoEOLagXe6FCOqfO0qddWr7E07rReYN8+6sJOtohqZvmh9l4jSvcIghrD8yB429/jbpC68b/0W
sBYNiNhrGBF4NyBMgF3qS+gp0tmTfsqOgmxWKxgHEgGmn4IA0ybepnhvlRTPhIa1UnIzdzjoNbNU
5pl3vKc8+P/Pe9qcNzfzQ+A9/LCUV8S+u9ewSTX6HiO7mV1UpvdwIV48Hst+a3+K19yxnJN2//6j
MpZ6atbrnToS7BLsEHmq4GRFwzmCCX4jM+OcTMwyqK9onsfKSIAKqfpGz26YuUNd2ArpTkTrsleU
4Y6JbH7csJDzPvgqx5QDMkdwPoqHNOQnPshcXV6R8jxVv4nx7liDXKRXhwO2yoMhD41gY1bbIc0o
g8m3JAHjlZRGuYeWklmHAQ40Rx+RZlndUW94AhrDearvcF1VYVldQlGOeZ5LIMi0g/e8kU3rTj6d
neGMKXZztNbPvcvRNF3QdADZOcCI0PqJuGRdlJkeF4XG8ZjhoNLnAkGg2TBvvzVAFXCH0wyZOy5s
uEBNKQ4bUyQlDVae44xMas6iEVl9C8hNHg9xM+gXFXWCUI5nRVwcaXLgPoH5IkAB5u/y/Xx0c90o
tYfFiH2bnF9WgMrBnBzcTYzgT6yFSy/DlO8RHGbyFtOeD5KMhWvxqcPvWguH/BPTJcn2Aro4+p75
NFn45dD5gsCv+dkcM54G6DRQO0pkqdQwWGiW/Z6Rr20Hv7vJm/WQLBeJIkpMvVhMFk3s2Z7ItdXw
wPRe4GWYjb9T/5+NBfPAZH7PTepqTnpJUg6yNUNcIOAZ2DVPlcV+B3qUZrWHO2h8ZCgnMG/JAAJ0
EqOm5tmV0ludQzJQRPRJ6BoXTIE3PiMEmJagICyCKXrSSeAVfJDVWxq2V7eB3S1XPmn2CCWnV5tl
4Hw1sYEIduj7fsGkIabPXKunZLOsXjQvLayd2HxBu8Px9SyqTLb3HezSaaBdZei4FZISwIPoHsqz
6rpD3Dt1X4qFCIKDH9qKihsvLWmElviK5AobitJe8Zmu1yroq4WAcC9ncKBztzQAf5Nvcaqjdm7B
O8FScs9YHmB7qN+5hQCkdVzIKJ5z+GoAfEaqYZTEH9fd8DYeSBdV3wH4OfLs0LaoG8J0zRBsD+LC
Mdax+fj2KSaMIKEcPTsdqMpQ4ijZ2EUiVx+W2MLLEtiPuN3CPutYFKvSIvN5+gPgZXTVfK3PajH/
9kU7PjMDnODotj0jmKliecPRPwL7cLBBTiqK1KtnFJrl9ArXhp42+RirkyDqTpJxx2cpgCnSlRiY
iPN3Krm7LyP4zKOrhqO+oHDZ+lDlSc+qKOrYb+B76HoPF09g5vOpgMO0eGAyH+6jEBpQDw2y+0Xh
mbg5vewuqeARrSlhi4pkE6GBspomE+6mVUJl2TsE25SWQeT4w9BWB3m8thVnhPBKeyCCLs5djBpK
XqerV0EwpBcxgmSQxLNtuFYKRVvabszoXIJOWVn0YtYbsoEBZIYKbkzo4WbpOmGLxyEHmqTKt2A2
yrabyHC7J3dEzebue41WntW2B/54VFDdP531m9twllyQz52BkEVPzftq+6NpgZXAgr7tE3Iuhr+K
+F74LlVaSFZUvUdyKdzTJes5zoVcQF7Jv4/mcN7xwd7xnpgFigZq2SRBZqMIUvjgSb6mrudPMMGo
Pt8jIA+jYifF7Oreg2yeO440E50roN6w4VU6ys3amuXvqVxvu1pZc8DQKBATG2awItQO4g4znL4E
Bg3DkYY19KLbEon8GvP+vPeevf0c4CFESU8HDgNT81bv3TZbvbps6VoSm+w9bpYTsZ8N2FXszHN7
ryoYhIY9QdlPqjSK37LS/d4NBETPkmVByzBNhQGLe01x6RRhALyhi5dFD7Xn+1lLINaGxI1JDhXg
orJQy47Zm8RL3l3aVCk+696JP3y6F/WFYncmuKfQc3ptBibxjLV75tvELnEAujDv5lzRmSLiSkZA
+fjFnS0i6/J4CN496INwzIS0MSigqKf0Q1y+6N8q0b7xz8HpIRU3GqLivbzktdc6jY+6GX72HbQD
JRLM7eKA8AIoc5tI9lEIVslhjaZbQht8w0e4Fzor0bX6ZMTkUOP+KFmR/0DZYS7nvRqdnOfMkI1r
cFeDy7Kl9dcJKTh6MmpkumIebOCa6t4WTQ8RfngB6xsHKE0AxXcFQKjtUg32JnR4eIJiOeksKOwc
2Jrd1aXuEbVeSlpKGB2yAkjWJcrh46YHmbUDucz5TN6Y3r4A7cMv4xmpay7wawrC7RbxpT9VMF58
Wll1n7+U8sBNd6hUD31O8UN+Mg7pADq6lFgJ0qXeGedU/8dQ2Elxb/NkLjBMABT27LnBwyKiegrf
upmp2x5fXkOaYTiRF1/1619/xQN95aPeEGMgdRInFBEp2HoUjZ6IxnFGst7gOoNqquFV8yD4Mqr4
XeWcgcUpkTEb7DNN3XnA9I3HTs6t8SrR9TLjAHVK+ksgAyWNsmeF6urpRZEDcK82sHKrg3drm4ya
ownR5oUTGkuEDUM6UrcGcPxV7l3+bFAVMLhJaQK+yLC2OV7VANV+EhalYQW1cyBgly3GospDc0nn
IG2/nXr0rhCmd093zDZXK0I/jyoSiXeFGGDCCJU4CybHEcuHZIQEeaK0DiB97xogvTkvS7RtzHUt
fvYFGMh+LeztMXe2iUcUYgLXxRj15Kow8UQlaLNGkggwoS0JWNiDRp8TpZ7BqnWKOEGirpWXdp1n
6J5z9aawIEQYRE0OlLfapwNsnE7dP9s6O5qbHO3fvWqaoOxKeGEkFZ8+XnumhTlDzzKN3BqHZ1kH
lrI96GPZKyE7YUy2wahz+Oh/BnMpy4vQkNb0+fTo3Zni2IZgkfbGb6FgARIAhZEQ7orVhGLdqQ7j
dertFwq6UH8nNPs5jnB0Q3JXKztkqXhXQJFetHAeZHdhVdr2BEXBjH48BLhVPKcVjTzZ4dLcSlXF
Tyl/29EpZsXA7X2a77+HyMSkSdhCYZH42r72VEa6fLmEY4ifHbLjUg5750/3KANQMyXxYGwMPP5L
wfpZfYuEqhUnOOsbaqR9wDZyMmsVSWdYX0yD7SQwevFEkK23G7zn+e6MD4p49QjODnIrMvYgWwAf
a7hk3+D3qZYh/jLLrkHS2mrJGwUte2XbTroYwH7rO3vGpnkfMivr7szesbrGOEhq5sKXrORSPqfR
YLMWZhlyk7HUyF6HGCE7IKBdqmWvqQ/XdqLO3ZXqKNMp1dyAR+Wci1/P9X7PenpjdJOPQ5NYVQIE
QhC+PKjXypRFN8pD9JYaGkDyREEtaAQobqQgrci87ioC0v67ybJwjXe5gLt2pN5pUEldmKA4D5at
Elq1ILcCs3o0kApJIUU4tIeORxsvaBYmRErHpfeG4GWzzoWIurfLNB6Ssi32WRkf9ILP4QUTEeRR
6tBF9C7DkVs4RGZy5ngBaFgn5OIKxh6Bl0WVNemxnLHincvMy2ckXS095FQRwdriwo2vNWG4Jp0a
eAyz8cNR94f75qOihSl1EaFr8hIWZYTQf87B9DlPsKA7CGmNiH8mgApIKzAsVw8UwHm2I522d3Go
7jZsaGoUJneR0g1Vf87xBJ6l4svzadAWeoFM4sCZ9YQZSDX8zHGPHXnzbggQefzakfdnylkruTYQ
5ZJLfq/iRsB5gBg7CmHjya1CdNeYce1l5YFy9LolNB8LbZ91rLG649GPp9M9lHgn61IxTDq2iWFG
1oGrBu/URfAIqnvAfNDpNUWPn49sBl9OSsn+D5L9NdxDu4KIpnmwOob4t0OlKjnNuNCy1f5XklQ3
E3YY3/D1kV5y/XqTdpTmRoAuT2eSIu6KGa3+vT3ODwzQsR7YLKPJjFFeV4q+mPlsSFFgVyMDJwbF
FSIquAUECZge4nwHopb38sxawgTV5C5oa3c0+rjaYR+zwPthIvKapIot7nc1loMDcQh/E0NonoRg
bFRIH8uwB1TK39EqadsjV3RFU1Aa7U1OiRCot+EutRvZgsRT7SXFIKYNXtqjlHrvaA5NOa9LTvcs
JgUQiC8R8wtA/xXvm3jtyFuABIkUGHofHdg4qRA3JIWYXvjxEJDQvfsP8SaLg5Igof0RqJdKJBOj
VSNIT6aOubtY52vUltsIw7UYmQGzifM07XUXiEBbM8WopwCfrGfdnw8LgH5tTUBB6CBqOwh/ipT4
l7G9SFGMf5F7kehnqU6etNH1vcaQSxR1SeYCNhfNdf03dPXGGJ5GyYUYe/v3GbYWYCzFK1CvGKMG
G7nMX5GKli0RY11r0LfqQQII/YbPuCNH6Y+qRc2Q94kxz+PYMcPEq6KTABNZVu04lZUS15Ntd8UG
7bqTq76H7SRq/UlN4w4Y+XwaWoQUNKzb9mvUk7b4V3bR1VropOLxCOyELHSVLnCawSgANVNadVeZ
KKPEVC+MkKCEsA3Sk+7yypDK3/br+1Xz4xkcs+5fmFkm+8OQ78JHVOAzpgmzkNkqAqi9AAWP/96b
aP/SwJAt+hmO+y7lBaT1cXw/2bAxbHWrTVrbAVzPcvCMRPQ/KtEbIeWpMl102LDoCKcIOS3PEHBd
k5EHeqQbKHA/k0FBeiEUR/FKS181T/goJ3Wlwxqgfsink88bvwjx3zdRVhxO5KUIDiGG1JDZ6AKo
sFdEIHkeBlLKfWeiS4z1ycs2tXFx+WiDQ0w7axwHLlucFHbhQo/NUCjYRbOog0dxkwZOesqgszeD
MXOpbxYgaCGc61CFK+YlAYY87I/btkyOjtMUuAp19jBuB4nakyjyCU+LjvlbFKQD4LXU1XHKzyxv
riZWsblSnqvPw2Tb/COuUGIbhBYHXzbrCmyj58+t6AovyojTjqS0YhpT885XMJWVEV5Z1FkicoFU
I789bBSVhTNDTdTn3Asd6g5nzYGHVCz4J3L/bk6itb2Ce5vaYV7+Ni1Inr+j2Zmj5a7I2r/PXY4+
hVgDt4q91TEYQog9bIkKePf4Fu0zLuW7kt9pGN+fOY8ZSftCOH/+udV/BuzbOWCnIfHuFtOgFmgZ
iUqCm5sC0EKj+LOy9tA0kmrJRcK3boaSlSUwY/WPfPrXj0ErEI48OpVX+S7Cj+wllU3sdG5jBFJO
9G2gBJEeEo/ao2ZLjUV9KK0ymQiiG4bgIIVf+3b4jfSaCpfhWv3SddzWrFBYlyIZJ7rjQaihk+or
nQptKvKoZBfEk65ckHXx7JO6GQDy1817vcvbhvWucpcV14sNSZohFrMMCvAUfKi6n+7beqbkB1MG
unY4uT7u8AVasJzaRfEyfLc/WAHeHkh+gjIiIXua9dybRsJY7m42QFs4/gE2QeP/EnW2KLo2vQIo
O3J99nLfM3p8DxNBjul7ncWX4XuJT54WUjEySCFP3nnTf2vc5Fq41bor+8zfg9x9KaBglJLSP1iH
MIBM8LIMwf99nhFQuZdIlU6OFTYc0KRK5khYqHTr5G5sZNloqIFOxawp8cjvoy+0dYEcZr5a2QJn
05x4A5NI7jpoypIMJe2mfszfzoVjgMPyX3uuIgTsWxMLmAt9ASokqzdF1B0INHKsEzFldbxzFgms
jntihvMtL5VKUG/mUU6rE+whKwd0gs+4gsEL4fWrROwvICaN6x6xDezhX6/AANdUAa3xOyA9Izta
hYd1M0RKxV8/TngUvGEeW7jjoZ5g7ZEyySu5aCD5M/YKEk+qPR3Eb9yOthHzPXUkFW9xDncCa9q1
6h5VAOsKBCzxBsGZQSAn5VKH6MEvAE8ju3bq/2lv58QjuFqIFNW1oLrSuIX6FQ4tqaib4CCNAp+n
kcBIjzS0xdsGsitFEQqyNKYBr1iAIm1B4Rmugi2Uhn5gjhldr7yWPrauC/2lFe6JM6b8ac7/F2Md
vw9JmAj3BVFHnhBjifSWGN71HeLadKf5FZKkkh7ET0dYysdfduBL8q/Sg/uZSURb9RMyu89ftAR1
j7QxUDioaEX9yR4ubKze5C5I0kAQT0MgSsgrMjEJcLRtfJ3Hb8szEC6CrPB8B4qOAyKeM0eMwAs4
KHw3cdRCegpqeA0RJBjSUsHKn4sV1uk/7kBQ6zNcSOux/V3XZ0cy8kJ/q1pK87lmoG3P56zcIOnf
7sgb9gb/1TATBPShYxvZlIG3la9tiP6BFWcsQeHVjwDpJIQR7hEtaetTjMlODFg2HlvWJK2p32Ur
7iutF5fBQdpEhpnsHPsdt84KxeYRQoUZsBBkWjeYvZ5Ntoaqy8Wst/LnMC1duIoxScvGMEZndzaa
FS5xZ1IM6LbMEPkSeJbgzcryU1eDS9HoBGfPWjc0anQV0kKCMilIL0/G8PyP8kBdlRddILbEoTpm
dQVK9uPiNnSjeo6whW2KAAw1BivTOgX3RKjyYl0WC/h54IF2Gj9QsuocujJYZk3+pHYGpzWqtAqS
vfndfpXGWmnHM5k8jQF2/GZNUbHG74hNBqjJIhU75k0shLDDvCO/bkcNS21ij82H8MdOe+PrBy+k
fuLEQWGsktvCVowzhYVoajy9q4NmIyVIa4t9KFJrdI4VxybauiKMSN0Ct3JHqF3MMBwxJp+IQR4B
I0IO1xNrjasU2ohIK0aysomYpJ9oZmMfyPuBPvONbRhE0TloANwD/IC46oy+JLf+xaZYM3PPf/gd
uGYSJ3BPx4yo66hT5Um6yIsUcmIP1lr5ZHwaGSe6/sjg+6gwa37nIsX/HlRYDKTc36gFSsdUO0/X
WSya2j+jSGE8gdE9LqlfLJo+X12h5JMsjAXyfIrN9JUMSajp+0/DW31KNqVnDGe7D4Xv/u9JgNlR
A6cDu9I3gQQYQ3xWXEjyfHnRxRE3poxtoN7sMG9q7WyK6BddPYLqXjakbhPEuZ/1ejXrInCSCXNd
vwkEv1L+jSjVNwP+0wpicQOg+FVO7XBnXOipPt6O9IrcOzTM9Crav3CKjOrIx2o28W9L/trc1PKz
izKD9Hha1MHSOUyPl+4sh+AepL4ki750yMMIMh2ciERKetouc6cfDDoQl9hPSJlgxYCbPULDAy/W
7dlCPOzr0um66myTOmRHuP6R6d6mCC1Kii6GLgAtzoG+VSPw5J2bNLZV7F0sb9qDCGWtQbHdMfeq
Kjw1DJ8heO4Suhfwb1A0jn2C2qQzpa6auIl1rBWF5I/xofqlqnkYgZGOWQne/E1qrUjai4+axhmQ
L/szcP3kbf9KMZXaPeNjvqZa4LSP0KK7mcz2Qg/FVUsgXayvEjLle/qHoNq4JlYn3a5trQKSRYgj
pQmmWpsUE+RA5jT32nFzwlITm3sgbodGL2VR0+n21VE6YQv6BXyUh9pZZA4mrULwNaTHyvOobzzI
c9IAM3tmTaZsqWSnOxzvGZmR1/nNN+Hht7jHAFqZqLdatYbu0AtARjQ+zit5ZEzUraZBiVhyl2Ol
v1lAWFcLU8rmJ5/yDAgjGx2p93IQSG5p1+n3xNsE2ZpZKFioCltnD8uCmKnFnv/tz4nfADwILSgd
NvUXmDDnt36Kkds7VQpER/qXHlqrKTRspZJNhMsA5DUJwxEjgGydYRmtSTPPSKdFMCGfLCq+p/yG
MVJyTFlDcoPtE2AjY7B8mL6uO26hhLn3avifpKp8nwGuWn7Eqh3uCASDXTPKOtv/xY1ip0yyp49i
b87A5p76+AnqJTXFNFPxkulbr8gnkVt4SvaxaQZBfdhnN0hUrmCkJchL2P/939h4kGj6pgo1wfuC
ZWICTpnWeSh0fAUt65cx9OE08Vf6O5uryplYsq9X91NF93THaxqhuL64zKXnfAK53IQ8D3ONINor
Y71WSGBF3gipsSsrt9vdUEDJpeDTKcuJz4TE+KH2DVDpRS6cbQ1/u0nqd0Cv7mrUqFvS4p9F7400
izIr5Bllv1fSTpi+ObPTfzWZcx0FHirN5uBMqoRSc0JpUolCQHAEXyxAbwwGqwjct9kRwpt5ogrG
WZG/VrX/S03Een9TuW0lMKnfthMFZrZOA5YTEzJhYBwTirDlFCsDGdEBKa6xWwMpX34X68CWxC2E
fJEJ7icG7h22Xz6tCBJaPp7E+CQqaC5lvmUwuEk9XtJ2MzcBCbS9AIfw/MxRLtZWy0zpzGaRciV0
Vd1lMILV7ZF17r1NIL7fmTnepuTfUJAf/nOLdFeoe4BA4LcjSC/ec/u2IEzmEXIZTnRR/d4iB9Io
oh+r50O9Zy3qnuQGQeCMDdQTd8gf7wDhJ+rbon///DhBNHHD/fdGvDE0GxZzPBhZbCv8bNPULoG1
+cBDQfd1KdNbmBH3+X7vESzdC4Ype8eBUsAZ+mzyQ4dvj0uGt45OjLVAhQuEtDa0oM7x1XHWaSkj
4G+B27vHvOPRFg5WORbvDKiRahnyywAFtW1UzZ7c4fuv12yRQsc/eSkDorinZ2MIqksCZh8aNjx5
5/xygRgV0liaB31Y8+75tMy2frcwfasstYnvdaJn3Rz1DTiD9Xj+S0bwQraDginay+Ct1n189zC1
pDs2WIaJZgVR/+z2upxcALwT87Ck1Pj3Jc7N0HdxKBd941m59+QCKjpbBoe2N5cEDSnBrW8LE8sd
c3V7DTCDIdanKDjfV7PPYHHu5qbOwkua8udYjqupyx433coOZD1xfPaL+biG9UgjW4Fhblb1/mUk
lNERwPnWKL+1+s8DbVc6puWISYzANnPRwscrhxSzw9E5cb8ZjpqcW8SzP3FDkewGn8yxUrMSrC3p
m9b9KzYa7x+StIEqn/jCWQmqLClDo6sqAHfk7iRiNo9GDvFDr+z5kMQ2a16+V+sMMXhKNsy/JUpe
UkuFi7KXKYifTOf0jGdyyn/Kv3UbBLImqziv3drDXSe2Feh+uMpt/9XZ5VJOgn1/RrHb+mg8WUS1
XO0atp8ze/BF70CAwTyGcN/Pto8xsJFTHy2ZKmmz2hzPd24KT+Ok/yX2Y04vJSL6BMmTwrRkefr/
RkEqirtlz5A5Fmmvcn6T9JvDA+H44VdARyDeGADtK5aMWUb245fCCgK2GePb9L6zzsdgQKiYTr15
SzR/cbW6Iaj3AXPks5iKhRQdbTv40zYksQNdbTJwv7JOt0+e8yytFuCeH0zeQgGIhcf0Nyr8EO5S
3iR32LCqv6lW3BWfuzMQsVN7Sphc7q4EslLS08qkpQGolrVRRtqqZKyfYoH1zMv83zWRmok2urIY
LhiSzfgMm5xtzMLL95N4uCJFdYKoeykEHXWeZgkUKD959KnewdR0FLoOwSCSMO8fnZp57GbxUvdd
jRPbK4fdPTj1ozgztIva5sQdO2arWAb/cwsQrI0TlZUMp8xG6A81X+8nSlmUWxJLjaQa0+WP73si
wqvNYINzMxclFVPTKA2MWQySwxn/CKNSZ16kI2PlWP6keuol42U9uA/1eFvnfFFGdlUi7z1NwF3l
ZbJbLrU5SA7G25WyyD407gvRXRo9A/g39A3XzPMTk067tCczTpA/rBQsU+S3SJIHx+wQGd/2xGEk
+H2Rr1KIxeJZqQWllT1elJsRgIs3DH8RyqcEuHvvYgOAwtVyHiZ9yOTOHyNN8P2Tx0+HxZVq5Oix
PYH6WvhAUyvxbJZ4jI6nhjuHhLUR8+E5zh//WmS07zPYzZYFAmHAGiv7a93Kxp2ffNNgnOodSdMF
1HWaASSqvHd1E9S/ljVwdL8q82FdXLVbQRVd0ZiTJPoXi+TXoSeFn1dDkRKQz0JDDsjFoBKbyeFm
kNeNN4gdxep/XkPmFR54JZYLUNLv4eqso35ernhnvlhBJm4F2aRuTbtRyqCHCDjiVfkODYIYoXbG
+eHbr4wFnxgjTpY64qNOj+0zk54QNrcnzQ4b8sW3UUY6RIEGqU7EnX+e6ovbWqQSicEItELN8L6V
mfyepdmTcBHao04GXQSrW0LldttNHJ811ExvdU/oOeq26RY7+YzcwzMSLergr3/zjg8OWeAW3szm
f6aYoYPMkj8JBQzrQ2Lp2Sw/ADcOvJ655OsNBgaf35AB5cyHr7+5OerpYxP2MiJP+2jFJ7EyT7F6
xdhIqv4sr/3heKxTcZMDNUI+uj6Z/VhcABOsXAwwtEBKHmqcqRnhA7DmDM7m4Vrm8kAvm1w0XWfw
IPMlisi8fp15h0PlkQCBLWTOPIg/QEHf2NqYdVNWwMuWiw07K75nzjDSWUWxnQ84KMLbE/pn6HqG
h5PgzEHdWu1OF8wC1g1r6wsVThtNExUnANqBcRQLNscxVzgFG7Y6OuZ1kgmz8hCn2+IALaY/3e+Y
HhCncvnjbC5RJekdjkesbaGSzXEhILIcK6cuX27WMkTkJ7RGgpHCfxFMi10XrnHA3L5rbZtcV0qV
WmL8yCqSLW6iABAhD0eLF22fHYCJdzWdR31XJ7UOH3OodhvPK57cZtudhCkkF3XdGFvpK1DaYqF7
rLJNB80TOo4Pn5e4w/d9kmlpnZ9WwdYlD4+GuR/JJQvXAxkuWqR6CTz4wHaFdpL7HS1OVXWaua5c
HOF/cq6QElyhs9Xktj9MvED0hq54W4GwzdtXM+PTJKZFrNMDHAuUbbtuXYNzaDxvcNwNSMGIMZUP
fIaNXM+nt6Ib5AUZH5tnZISnKnwtj5JZHCSzE9W9diC+iu3lpWYGLJwcKCtGPmitm6S1Q/jquOC8
4uDvFn1+btsiVgdQWFcF4bPDyWUmvsB3F0QoPyPxuG0ow3IBrVZdN3DYYUw3fcTxvtRSTR/Df4+B
CtAr/5+o5CCO1kR9/pyPQJQyQl6/M/k+fnb8WZPkyEpORLeT0nkG10omQNHGzFMy5n+OqbCtVEWo
145LoE+kypxQf6BF51GaXdoqBF2FUdNVJ0KjXscOj6KQz7WZFv5PCzL4DXt7/lgQaNosEUX7gTuu
JLPR5YS53Nql9CUulmrjjR9tS7XQyta71Vy0Nohzl7HrPKD0G7IcVdgTLL+DR5lfwPj7KzmO4Tx+
YSGTXtYUyYLyVW/ymDwcgzzmYWI/iYEVqzpl5L+C9PTj6lhirSBqDa5vJey718JgF6XPX39M1tsj
5B2XrvOXf8IGcwbn8kPg2UxeQsuWYV9MOIMuW4+/91q2V4/Riggh0sHVyD1xFLnAHQ11euBmfBBC
HTDXnBo9oMqsQL2Z8twvjgRd0zbnGnS0G19Wy/sXTAxFhBZk9gQa0TIqb9Xvj/LBeKTDOsSo2Ris
Pb4AeZ3Yr8eTiiUgJaMdI17PA2AMvUelOdJ1ynzwcHriVcBIQR7699mF0qOSpdT6m7/S+aooAB1m
oI5dWtDZqGTlGQSjUOy28XOGulEOEf7G+Tg1/eGs12+rjtrU0aEU16BSFCyQSI4JUzDv3RInj7BK
FAkQyv0TCPkxZjJtyI3gZ552OSWZQpO1oBhQ8WTboJrTrCgLjbOZZHfI99Tt6u1+nVwz5RLXOFrk
SLVrsAAJTBITQRCqVqD0C+dCu6OruTzDKAPv+Ga5vGLv+snffZFN4vRbFC0fzwxNE5yGdHLYfbqt
GGEUh9NT8J1pn+uZNy8YEl2ZHOseTDhrLVdECsy1hOJPzQusW7Om4W2ZcmYNT7LcABVMfQKHH0Q0
too7xAhcVpQKtVhRWcXcNg+vB29XWtT4oe14UvWOjC0WO/3x8csRDHejDml7+fKgKtzjeEGcgTLP
zOlyEjscJjNzgYwvrW3ftBSth/Pr0mSSLwyDjIxGM5ANnDkbA7fS+qSmjl3Ab55jntpNPEDh1l4R
OLaWDNw17np1aMMZCNINBeGfs8VNbbz6GiGd/HW+TrXA+vSDxs1PQPmYWJjogpCK5J2PzbPWdlhF
WkpoES0n8A0HA+7AvAQ1EK0ipHldPkwRXEcErnPqYMkXEYJyCX6HHuBy04aEeswRh19c217fDEYb
ZmU5H/2tUdT5GuB4NAgwAj9PxwJe2Z0/7EQd5yaYd/t5rMR8WsKuANYHSmm2NAHtDSt1eEe+iLhV
JhR1n63T9kkHE5t1lsRwxT7KqCnQu8jGjozkKTW1LdyB2Rqh7CI2rj/6HM5t9jHDylVF/QTItW0X
OTwDzPYcdDsl8Y4MqufpP24q0qDL+g+F2WRahvF8yY+D8XNE+9POWlRGe3dMnCrBGg+hoQa9t6Hu
Lob68cyx97uund3uekYkDVrEpGue8Nu0aEGoRzk4q6zwRLxTCNCM9ih3VZn2ANspXGOEC81BWrql
B0aAzourpZiNgj6dLeqQ5q9+Njq8/Oyhbu9IgfraknwUnsWAuW4hRKKQf+N0jTKN/nlTw5vNCXMD
ba/dowkPHpi58ZZ+5DLAla3j2sPmg2cRH89esy5Y9o3EwJNm6MjeUiDln5Gmn5eFDguVwr97UYO3
RBYvltMTwvowMsd8+DiE41qPiqiXYiK1eZEHD9kpIyOl98yRu+34CvOgmz8TRZdBsuKmDnSvNo2r
VKscKnDRBuZ4ep04oyySVXoMl0nXvcEqXNRrRBhV4G2uSQ9o5fiaBthDXfPnUNW25sjQkmJa5mzK
oV+XrzO4aMIevx5i9HsPxOS2Zab85DxdAQBo1uE9ZG7P9O1JImCQYAtkWznqcGtAPQEbS3cfraAb
vGH30oSei7s35mvXZDtm23HJUMOGKgwCWu9Dcw5M8u5rzvCNM/iPXReDXUWIZIo0jc1+bFFMfhgR
W5rNSmsc1UUBnMATI1+qY5QBAArmR0QMF6zcgCul1UHZiGHBU4uZCFpkPFVkU7zwqBx63D0QaPBv
XWuvTZye27F/z+VikxuSAbk6Cveisxo9K1odfyH8NhYY0kQtzo2lGJyDNcQD7gvXfTAqyKudgoAY
94cwpZW0a87MubPpyLoYIRe7MhOvP8dBe9pqgBRTIrU2ryNP5PuHtKBJ7zTdFEYG4PPdsTHmC9ol
mwN6PJqDqWvr4zHJ7PuAM6YxacDp1Lkm+wXY3XKKR70AADhlIpMj2W4tivlxUUXR6YidBtU4O6tf
29mlb70Uro0aybxbR/088pxf43oI8vEnUQfT7LlgIEOPbbkIeNO2PdkIaUAqbS4Mjvd7+Zvd2l26
PJMhETATKZZH6k9+e+ZUlekpCqnm7HY0h6q5BY0umKdt/5aZjsKb+iisBZJZgJ7/8OKJQ88GOAMc
uQvom5OKZbnVXNPpG5HkyQ2KfGt6iTi2SMNAxv4aefkcSj3Nd8cWLDzUz27caEyCktzbCxW+sjNN
EJRvS2YlY0ec5uWZhkkx7JgUmmol9yDjwL8766l+OY4/s9xxIoQZYGMm6PI255W7Wk2XOpitMceM
A48VwPoYh5fyuj7GzFPF4X2aEgvzfkMGNltuilsAza8Hk4Z6FESLtSItnwSxPVxYzlzSwL0R2LPy
8zQYcHXkuTpzPMyNg0lNZbcHledqPhfMqVWfY3poC15dYWWbGC7bIkYkf5oxBaHC20lTWtsLTZgB
pJdGtBKPLAfZhLBWFSstqp7zhp+NmyXTtxOnrLqvOqAlWCYi4dcRvjkEkzt0/TSwcjCflxSA3IWL
lpf+enKMfrY4aKPSz1O07+Ey/qr7k9d0UNrqbWVb+BV3iiU+XO+3fkeF7Yfn+6wsdlAQx8pnk9U1
e4EJu9DndKl1157PCVB+FT1UuxhSu0fCZKC48bmjVLSBihf0joDpFVg+Gg64Exn9OW0t50OaXAyr
p8ym7kD3/n5Uupt6WxwmkeTuwFnWQCgYthchEgXxZPdSXOvm5TFUnYjf13SeRUjTvhKErY8/a2VR
YEQxHOEDElu4r8vGkZEt2KPU+wpS1dcKaCFWitHEnLNALbndyNS51IeYsad2cp6bVM6P4oPPS2Ix
ulAG64TtQdmyBogMnl6qXErGyM78EPv0oF7OyaL47Z8pMpdaglNWde0jKH2TozOtCAfSRT2dSs7x
vbRpzhFbvJESNm2kokmd85c2ONCe9zYKh327RNg99/e2YUHyQecaAsWvGCJm0rwpO8bXq8xq5rsU
vEH009N6d4gLA3ZXXxepBINOkwKpQKf3zKia7w/88QAlwP5dHtYmW4YuScmSjYjr8NNwM1vNgWeY
GXvXH32pleM3zDcYw2nRqb2TfUJ6mV0Fv9G1UZ32EMMEzpahL7cfIICgY5SebnCmOk/WTzU1l/cg
FngdXa1M1QgQS3S4aLwwYMi57LoiWdMxIT1gijhV0vDMuQNu/ZamqJTgDEUy7CTGDV2R5fWDLzd3
sqYjCsvV3MN4NVlnJVvUJE3CBLfRonUtqTN0xna+JR+5a3UMMeUyBeuRkZcziKmFB7dZDdBVP66L
+WtjsfJTatUd0HmVOLR7d998dhXrPWVsjtunKEha+kta59x0gEI6fGUZQ6rQ4VzW+S7ne8DkpVeH
X56/ryR71TGDD5Lzour/9g4NTwMO6SzO0IUJNjd7GNF3NfMYbMwbHnF16iCY0JA+G8AKMbBYincT
sYyMNIWhw2lZA4dFFMCFjcLKTpKTvz8PX8WzHgl+2xUGPvX/MTGnX0WX/z3AYH8JDSASTu84kZXy
PE75FvftklbFK4kQBfYIPm3wRbz+ofaGA+Aebvah0FfhPj8XV0UlggO9qkBYlFthmDCPC/FDVHr4
Vkdya0uy4i1BxOerRHIlSh5rq6w5ML973JVMQ1Tk2W/7O+4opiu7QYS00pb+3ivl1ugnvCFn5IFy
Ge5McqmgtMybMlV0xw0wOnN/cPRXpwHEpFNT08wGl8JJYmBL4gjAq8JWCqnNOmnvBLBOl0t9YLCc
06QkXSdoG8M/9CsOchOr7nSI8E/Y3pDUabm6rg88edLID3dYcwDxoLoCYMBhaFmLCzbvwVctmE2z
Ysv2PaSYNLhxeOJvxlQDXOVV6jB/plXjcrwSuXv0KdcRJ33G83pPCTeCyBRje/wgjHDtdygIWwpf
pIjN4m6po8tzvtZQgJ2mvT8+A03RzT5Tq2IFtOApgS0lpP6OuIv0rNIjvk0zC/tk8hd/O6hf4qFR
lbzBaPKRcP+3ZuAegUkk0yGgKfpG5u73TR+1Lv7f1MZh4REWbYDzrzvzWg79NG8FI7UDP+w0jxpT
VqNslMaCyh1otXqlqfzK3nLdmKqgJYRWydayRGg9cG58+mpUS654YyFpzSq7k+IrtEn9uEcmOzl4
/4sgy0Rhe+4053svrdQ4FPksqW5dGeA9CgsZSD5Z/PdZnO9bABTxxTsfCWK1nqfnHwJz+v3djJEI
Ums9sBYPkCha4L2E/T+6p41mZMKFZ+CxyIeULsv5NNX522+UHjRUmLS5lhHMjFAs0U0N4mu6Fmh1
epQE/ePTj8FQ/8l2u4zs8KUcUZDkvxRjCZurS1nJc0mgg//bWPk6wyRGD5jpFzrG9cGHzcQmXP+k
CsYQpyhei1tu+6IeRHuR+P9H8aqZKmn+MvFN9Nmd7Y3lnGdMDbo8tw7koe3/tjnOo0DBrIY1LY8i
2RcQbifb5/BrNBZ2QV05UMNLV7ZpFoTEcNYhRtZbX3U1A5iFmSTTBqxFgI5zyO5cCvUeIQoGOPMr
3eYQIFRCAQhHWVIU8YD5k/8m5XNNkQvorHAcuTCQMBKEYNQagtjvMP3mpp3a3RyDh05lws2XycAj
6nKMuVeWEWAEJTXB1oAo9AgdbseoTjevLceRLgQ30BfrwT+BpfymA7FGJAI5KGV+FRz7/v1UdeLB
BM0GQV+NTgZ4bBJHnRSGCrfKdkt6Ht3fL9KY9+/bxiXOW6NT/+wXj8scmuCZjMeQqATDOulVkdBB
13CoAYfSFHGU9F7xbM9o3vQKVDRb9/2zYxAhjQlc8NRy/+ceJb8JKv+sAQPMeD8m2SXKzTBRuAzK
WbNZjt3XyWFYjeldEiyda5g459jeZWImooz1oBWUN+GL88cIXX2f1hOH43uNFyXdDs7l+SYw1BgR
zoeLvvJJMeial6TKSlmBThlClbEgXeJeavkpVqlnx7rPDYpIxEDhLbr0kB9gAF/nycZjgs/z7zOr
ia0VTLiuMsaYNONSKHl7fGCRl24dSRfSeFjF1dJBXdC8N+Uusy7Oiai8wb2vP9F1HeIwAm0zYArO
jupbeOirac0xWvn0AP1I/K1dWKaKNX8u5YeqftKw+reOUfKGf0mKRhkaZktdHtlJQMjg9vCxwdl2
zJNfDVFujPaxqO3fw59op23S9KxEu8iJQHH1rFpocTYqUdVhT4KLaBsPCfGs2rEt01MWfFlZyPVN
Jwx24zuKHt2KHRX6vIUxUdzEumUuThkxUBv6CxD67X2pDy6S6yUs2+JpTQbDDMWdpzjwminDnLpz
0a6IUh5ose8kAdGh9+KmwpQWSZ1l31FtY9ipPsbPCsGY0/r0T8IjryRA9Mrnu2reeWlUN9BcX6Sn
00n/hanpTkQ+FOT/NCVrFZOMKqKbZ9do66lLPqrqY2XNJNseyC9nJostH0mS5vUozZXNpNSTV3KN
noYWx2VWew0X6DnMY8W0NG+38IRV6PYtFcJGvbdTLGv4inQJsDdLglh/yGgXtQdWzdDzC/5SZMwP
r1nqAkS/Pu6ZrX6dq1amdgBDl9G59xHc+OKWLzHDCF6yNKSxTc0ScU9tL0hH081hftyXznj86XSf
IhQ8wEl2n3Mg+zlneERtGJ7jGYWp+TeITmSdccjKbiS0fMKTEco8BJvd+TP0xhseG1giBsqpTyjx
g4u9k3cZPrKEUr4gCfa9cleQByJ1no5jwwHiaYG8OL7/pAiX39IVt47JvgZx6iZJxbfZpxQ+sZuW
WW9gatN9i46djhlRutej2Tkus685Ozht3mFlCLP/gajlaParrN6RRlADPoOzwChtptFm1gou9vX1
WDPXJWX5SfqlScpIm5VlPbdFcZupmNAB/mofHlD5lu7C5iJb3drHB1+gKO0kuuYmSQtEVvc5SVBj
FeqoxY8PceCd0vqswSrEQAAQr7QAMGM/j5CGNnPsZMkOGoYI4MooKj83Gel/FdFo3+Uxr+m8htGf
2YFrkEjmySusJN2sUFwoOwN4q1kP7bX+4idzng5DA2ujMJ6lE9pqIa8PuEsVv/N8HqjyJQN0GzIc
GOmBO6gfgudsqqkIifvw3HD2LIGRfZTOSl3MBxIxkrUzZCKwcYvkO8dBvmByHPGcawN3U5qQBQLi
1E3zbrEaAatA1mnhXmkKtSnj/HddrcWiBlR6Od63S0ZF+NdQIjcVVKd4l8+I9yJl27ro7mRARvtB
+XtMru+yfg6eX6hlO+Dn/WzwmO4z8IO2+c+jZqzfn1yFj5r2++X4rya5tAznkVR5ulUHPOeb1/d+
bcqKeCaolCmR6RsbOKJhTx/qI7VztW3iZEUV2+8mT8BhrZaRWS2y5mNINGB+y7pAOxKhdNacW3ef
pH3wWXZ0oXDR5GDU6eZe/MEUz5FE8AMbGvocrX4n3LJ9TJLzYmhhGIgN8A3teD7K7Npc2F5lhs2n
n2xq96k3Gd1JhF/Y4xlfgsQGMDe/FrZhgsVsFt+Axwq6BVOW47uwShfUQNmIGVTEyrfTCtDqgiv9
jV5skvxKchePOUMkr4VNAwVDaoiZtn6Eim2XdtzU/oR3pqTicBm0wCYZ+rCPGvzpPSWLr+kwJwdO
UM6WCZSioGSUEW27IIo6tKq+GpJCxxUFNYxwaAuupcWbK/4PsymUV0Q9jT0okittrbbTy16tPaSN
1s055WX4BEE0Hh4OcKYmmxQCouF3UbljPynvult+UQF7EkKiGQqM7qD19wkeu1m1WC/P66NP1Q1C
n9nA2NpCAi9cTzVVQtKEPPOfj+XqnjWa8Cg3ZLecLJe4piy/Z0OPzUieuKGwKKBDBW8L0YQXBXEk
b9xUxNCK6QX3xab+IzYXFEfhW1JpP2I0A4gcBJDBKeXli8/IHQ7s/9C5NilBT+2K4cOF+7S6anPX
viyrnBaCEXwrmwvcFfh+oiKN2GwpCi2vBCXNPZGLKm1DBOo6YM4DBJtUdMdNiwn4hdLz4UT0FzFz
4CcRE5ux2QPZfsXFF7TTng/+J0dehG0CdcqkWbSCEdeRnf1xGtwOJ46a0Sriw5Rm+8b3FQX9YoTd
+dkqHbIEGxhFN2LzsRzuJ9Hf4Xk/TniBDK6xdthY7wIOkHxR/v4Wi4Dcekon86Mxox4nRsjEx3mn
4EOilAMS8nKkA8pdK+j5gWdQnHhKZ8hRn3mN/YDrlgzUe849vcz5jcW8mHWoBQJ6nZUFdI87aG4U
kfsmHzm7Sz+1oV8yUhRqtM1Jq1MM7iyyixWNNpcoyvpsJCzwUlmS5Ht2kAbyZHmhq1r2BaQ2J0Oh
X6lu7R7j0y1U9QSOMuMRczf5XQQGAU8v+5dufyaa3ACnAHh2JBxaq1c6nRNI56hxP3AeZFCZEIME
o1JFwS11F9y2srpY/UDDyHFIw7dCXYO78uq5QJX9rR0LuZ2PR3U9+9z5uz6noMxpoQWHBP0MZFvC
jldqnRUgu0aNk/VzepnMtQxFL3+sq4gbBnSX3/AF9pNLKD+beBg6pmYPbPzaaySQ3BBndvYnSDiC
kz7/WZWYL6KMfHnneJaxG6uyQyS84l8eDmFdJAf0YC9CETm8iLHzVqmHgFx1dNWcFd8viwz8iTwW
zwWhlg5FAXGTbJ9MSytQzWlN9SNLDtWEQHK6YXv1kF/x6BVdR1nFoHOm+wcrM1uufZAFT9lZSNFs
NSSe9JfTm8RnM9M4UAkp0kbD88sfcJDVIA5EkcSDsECWMMjkKiX/u6SXCSzmB9m/vr1DjepBM5AG
a1pfV11aSTTSQ/g1WjfzYTgdscj/1DvQZaCZYoirrAbLRAZW3jtsdsJhlDoCoq3VknFjC71JAkoW
ipjUvZJ+VhaaDq79Uyu1nVqImbQl/EoIL92zBSEO8Yn3x33ejYksOz9KskUDON5of8SKECKK4eR1
jK7Ea+6WqwWfZ1m7HJCeJ/tfs/rnRZuG01MLOOznJH7BbdgP9DG5q1u8c4+AItrLkvgMIAdmD+6h
VCUDxM24njYv2TZkb1RYpApu+x+YRZPmk7e/iYXbTlR5+IS8+Oan3Ehlk21R9/c2UN3bLqegsfDV
p/1ySsSDAqKf1V+BasEnfb6j7o7E06FZKASOAczq14Zlh+ibA0h5rHFZyeJhOIPc11t3RiYJDUXs
cgOTjUJ61+yBAgATzungHdgZgqLHHocbE8dJN3lGx4GYOGcjf7d6Vri7dnSv6sXZAVpO0xelOYOu
rJ2xjJqCGOANvTGWen46K5D8MYnxxIADWJS2i+6giOf+DBZwmZbhZ3k9alCOo4LIHybwnGMQiaPf
u1yautR/OnEVHgI95ySEH7SvLJuENQbhgAQ61ZFPAz1d2nzKmnxEexK+5Jj/Tq0OPD8dIjzXSgrt
JxocNuOpVjK6KPwfF8FC8cPbjkgfSq9fQpdUkzeVLPWY4wW2AngJAQxMswDqgAo7lIDVnwco6vUU
PwrtFR6d+vzKERbmde0vQU8DqGPAf2h/hdqmmD9OGvxaHJ8b7k4AiaOONI5bIMZW3uX87EokpbGE
O1SonR5JjweeXKRWlV2i3NhvtmQToVEexR1XBI4zmVCWhb6JkusKch4gmQ/5Qa6rosef9UoIO3o/
pjUNbidB9zDUJ73jfYDUWATj4ULLGDKG4ViG16OegHFMrZCtsc4yE3pDBiI7w0XyXfH1tyPK8/GC
OKa80Hj5qaTSHB1m1nbPkjf9EZrHXTXRFPciamkZxRsrFyERUjPoFgDa1UKuvP8RQaS5gzGWemHq
aktJaWeXo1NAK+ujiOCpqp6rJP9HSrQltxeSRH9tHPMmV5JZhydTuTiUBykCPnv4vsdZPg1SD40O
eyU+S5zEUmD4bHm95WKK9Xcst+i1fZM/SSHrxXIqUKxyq5hqrd4Axk+SV1DBfcRFimdQgX8VTITY
1kYqhzr1pAnNbZvz/MXi7cCPPZCCaKiFDN5FTFBqk7hY5jtz6CRut63dIOKs6Y88hASd+6/yrZni
q8hfNAO+dOvbgobw0t7s3DiTY7qZVZPG6TNww8Kdn1p/mPTF5OmSiGv3ao6SI5AXB8UvhaTmFVtO
GupobYs0gtbkOPVZs+6a5+UdcRbG7r9JHaXjdpE1M91TpNqO7IqZuiNEaUikOMx2Gs0j4WJEmFw3
mlSeGChJlMDhNR5avP5/hOa/ytUx39oNW8C61vbvrZ1MXkVB5HE42y/1+zjHOduGm2RsyDI/p/EU
8Zqr4F7WD3284d8NnAhMDT9yL7NGLc5DwOAcLp5KdzZW9JSjekCzEwXdqqHG6V1EU05Cq/I0JjBe
/APC6bX8Y5CLjpHk5x+i5ihFhVKQ0u8RWhUWdWtjPYX5wTa8ekqdrE8x/SOfgvrXYPbdhIvJmL7b
6QP41Wva7pYSgBxTt3VTE4fzfzPae1qxcGmEGE5qdM5qoaf+Dq9v7UO7pVUYBvm9MLV2ZRaPQ03d
Zs+L4yXwMSLPki8ie3pkCWLYvRVbnPSfMyuBvGpUf1AympDy1F11+XlupMxjgNx9xWL1xZRi3Mm4
1KfSL/opNw6DhDq/5ZknjrlsY3k+D8MzYnVQSt9gnFGhnkLnrecfqL91li/p0P0Q9AS1pGS8CLXy
uOo7wbAndhVtJ1BbfsTnsSoLGKxvAjvaydn7HS9Fg9LYduF7EUNkLUSNxbhuPr5Ex2Ni5y3HwVX6
Sr1hGV3JM9+SqlyqRNKXQaqVGezivfqmhjOcJ0j1qcTWe5rO9flefnmlZFnuPIWxEzpnvoYmxm4e
TQSCGsVjrMC16frfNUKB+m9Nn5BVPhLPVJAwU7nC1mHS+MB7vzuIxUZQNy/0+83DL0ryjtGMNC9j
Q3j+qfxJNTxLmNPFGHRZ4s47bZ08WwFXPMca+ON5BQ33ZqPG0hsKYQ0RSVlqeTyDQG1EgHmhoM1V
pKsgUw6BSV76JpWnGu4EHyofnHpYa1/JzVdBQXhy+yrnUAcj3+UxWQLuu0+1UD0gpF1shya0VJ3H
zQv3UFzekGyK1XHGjTthS1HB7oPTzKAz6L7bWtOBHEn2JTX2eVkXYCwn7/bsH6xMjO7fFP/kQ83s
8dNL1Y6fGshtdvSyDsXg2xJyvHbnuN++Jqapeoni/qAIB8hLtx5j1B/aiHBrISjW0FnRTTgYGDnu
OI1qsuQY0TEv65v9czPh4jQIhSaYP9XyFF+BZ5OTzLCeu12OgodLpQZBW3aeNRvFmZcya4CGtARV
Tl4oMwhm4P/Zgot/mBy5yoEwIsaJny/uI9aSUg3cOMs4mXBtmE7MmkOCJ08479Yr+BsFUaWEq0j+
9kN8bBGvAZnM32WYaSkc7LijZiTX4hLy2G4If3y+UdpbkSty7I0gdTzIAtOYfxPH4a1TnsDcwx9U
QKei85QGKSDiDNgO471Sistp35CVi+zeDgQyiDq+7vssB1a7TMKKV+XvuPJgTg2jB92HaVdv4DtH
i6yiMDsRi9SytO/kvQIISZ862mPEa1FSxCMcGnCooV7EWEqCYDlFFo0WwWEgkoaJ4NqPV8VBRE7S
qG9eAKHYqCJufSlrst7d1e3MSl6ZDInmDwZvOQWpaMCxDO5ZVcRu49E/b3xUvOaMHjONOMC5TVyl
Se/4COJ04akKJ92J9zss49Ib/6R57iTiy7d1mXsu6+z3F0tAys6tOKrBvkVPIaJtFvL9sojXTKBK
15lnwaYe4nhunHZ13k5blfAYLqhT8UdOEZMQ7yBII8mH6Hcw+aXtuXnqC5CftXDevlS6V6qTolZc
9k8JnU1S4n00XZkwCKnDT/JC/2PWMnA8v15botMohluW9rcY33elKhuoNJ/BWpb89tusIMNSPMRY
iTXKXD+PQ6FIYQYEacoPtxSaumZTUzozjOiFcnpFro67U7LLNGjtgHZbAlf2P7oimC2QvhVxMQnX
c6/SvlBmjx/Bd6hLHE0oP5h3anHP99NRR76WnAc6LwGRZ7Zeq1liLbpl8yQ0sE8NX5NZQiHhpHj3
8v2RB6dqoONgbRxu0EoUQjmeVMq8upe6fwbl62ZwdpZVywshl9jw4T3RZwN1gjZS5aupiSK4KUrN
9ok6gp9l3N31DjUSk2LPGNL6KxojASCPm+zBndCvJobyzVjctQykFr00tBh/f4LaSGQvt5KKmRQv
8+hSFlJtgRNCU69fxcau4Pf083jI8Mfs+fZLJxoiUm2/EDy+1XAJT+lg4fopLQyzE5WHt5zPTxhN
mZK3CPnVmflekOgZpsdjhsqwmmtKettjdcTmDc8t1cgnZzq6K02kJ1XbQfM0lvUWH8GCaxUZebCD
NDNUOUp3nLf9DjXj1vjCq8sgtzXAR2kRnHbIrthj7rF4AkCYAgiiHhiUSwItYOoN8Yb3zdn818ER
ozqTa0VHzxe8YGQbjCl7lL3RXw8G4xNau2h7+lUEfpOGvSWx09x7/cjHOnJxdFMlowS9IOV6WksS
29OxkG8zLqP5HH3xGzoh6PGHd0CmuLkOmGcdvndoOBfG68RuMMQ1NNroxT4hT3GmywhlFfKqnA/1
4GDXa2cLIx8ZY0rpj5Gbo3IyIv4K4zvD7vBPB/u+kmn7NEYuXyOE4pL3CeDbriA/P5boHIyLkxvt
9fO01XKxcq9CSfLivc9il0gp8dn9HIrnHh3OaXViQgx403qr/+Kcfkd/BeqQUCvF9GzSyucYCGG3
wo1z5deFrSsoxM5YARts90LV2DjuSb6YDOo8Cjx0jsjIuQKTx9SykfTy1fnqXmp49a8IwYZwhC5N
aMUXl8SqVIQSXh4IihRSSgqb4aQSjT4Rq57EWTacdVp2LAN3AjWErbnbuOOWkcC7XoeWrd4EmDdP
RkbMGctOZIXJ6o9Tp/qJt7VTvfz90sM+0k6aOwJ0GoQq6HmVWVKO5vHJoYnlsw26Wh35BQxvxGFL
T+AP2nUjfiBqLSnxXeOM+Nu1OnlEF8BuAXB8l7E8j3Rbrhn+2fcXqBrRos9lPNGFtYd1Gp+NyL5z
5l/jqSQa1PwwwE62kJwfHn8ogfyxMN+j3iQe8C00+FmhvOc6tffruXd5rrtxMkpGI7m4Q890FyDE
fmxC+jJwQvae6J+ADMAxQFgS7xqnX7go3WNnH19pOTndHj7xpK7IqTwVURHeTvBWWytjjMOJrmg+
ZSyMBjtQS5N6cJyMYu/rTBAr2qwChVXQcUcln+I+meMAu0ZFMwD88l1y8wOnkzJ4gqYRypXLB97j
ZI4hCGif40dXssrlAPHWmRajInXsfx5QnoVlunl7r92mnEIWj0yDLmvC9Y89VAKB3lUff67Z/E6h
4IITiVPCiAc/E4l1bCzcq6ShmADJctvWL22wcc54kYF8+b6ZUtVAzHeAkoS7Xv/YlH+dOc/zpYXj
eNG8+qG7NGEe96vUQMWXNvGicqoVdw4ZbGIrLUVRgq9M9HPMluJ4FRL+B0wIdp3a84dQTtiZDS/7
k2y6T03JMXRxuez9hBMnqiochbqdmTC4nWIHKZEV+Js6+caFBM6xm8lhX5jCXHmTtBf4t4OCTW94
XRfTvOywwJ2/4+UJVJhFJ3IJW2kcNuIgyBz+esT40aeUQU8uriDTouCnG1p3kpTrakByugL/c3+n
NA61I8LtLtiyNxR2Q5nfjhqe9yUt8ewAftmy7VXNZKIs6paB8EtxrYxCEzbh856C/R6P0h057CY+
R8O9rmO5HzB35TZhZe9QoOR9hB06RPWziqQJX3yP3x5UZgNBIDvfFa6z5vuri/4xukeyj1vGmTu+
/kOlPNCy1vf1vfdmZKkYA1znDAYF+eiWD13bkKdoj+awudirGgRlk1jiPWfE3aKhSwTh4RWltbCY
3mWWoPIb+tJEaSmlcEtX57lwJ35CPfgMmgs8B22OuPbZHpEcWm8lUz36dExNVOiI7BmDuKHk8rWJ
bt9An8HF2uv5yq5sBrEd3xdc95KoJPJ5iA7JSdDykVZmL5T+RQzNrS8DDCAV7HfKzcSzoHwLdY1p
hGnlMkyBXRNjiWUNMP3jr2GDGzUhJMocoTO6mZ+9D29AAReqA04U02DfEzK7Kow0EysbKG5Fk5yN
Vo3EtOjCkddeC0BwHB4jLIQ5fALmQduRVCqWTWQbHdbIzd5DgetzPRHcxc12ghoa589Nsq4I/BYl
c2WkhgEIV3KIIT/KQcF7rUCc0PbbkRYOqUuVtdftTrIN0NhyKFo+8knfoN3tMSpjmK5GjXqKZe1M
aABYZ/lDU0OazSlHilU5inCfusIf4tqopqlF5SSa3gtisxQq1VjBCuWmNQy9RclvvFwNshYS/4Dh
Ms8YQquDID/JKKYiYgT8fB1qaKHy4lW5qa9iQEW5HxtZF3Ta00sJUjU7eJ+cNUJzL8WGiy31+QCv
ZGpwbj+5XSYHMglemtXbGfaKcFnD2pAetFudB52P8FHlLOwbSdtehSl8ln/NPzDj8keC+CBaEnmA
apv68dTBdyrgpGqImyGx86kqCm9591xzp57selVO3O/SxUZoNyOlwHr1l0ezmWlR5uHV966y9UPv
fBk5CPbFNOJowezXtnRxIMglhcZsTBSj1fRuNCzOUtgxIwSZNZkuUoh07QhrV8KMgKJ7ZmSqh6Hr
7leWjTZBZIxtVm66Ivm/aL9Gu/sl73JkJ5VDQ0cd6iUwQnLpgOWRJ5VY9UnhiE4XbRZuv+TAqWr2
DScG/dkVHNwXKeT+iTM250FKyxDs/QUKKtSQ3XrZOb9NMHYj32CDLz+cRNTYSxXBwDiKY27qpx3z
OiPrUTk4tv2Efy2ImnBiPWNK4Z6eWD615bSXLh8xniHxV/z3wRdYUJtbsnPW233NBFDNca6OuHGQ
qosK8nlGN9zacw5NPuUoFG+XgdOkTpyVCLnVTAM6Xh4PD4UHDWuY2crGCDujlCQM4Cqtsz7slPx4
riVV6qqNeQ0PfIeAQB0rfm0ykVLLslBWvmDIMGRah1NWx13od/FyDXnog3gSEngu1IyEimHJNIyp
bK0b/2YFjynPBDSgRE8kHbULJ4f+RPsdgwesRFNvGHU5c0LMM4Wky23JkjVFgimrX5OFo3fPYyci
MRJcvA6TmdRSKBpj+cwIRigB/qSwqTG9dqHzYLIS86FyRWzGCXTQBfw7QuLcdZp7UFYegB9fp8Ov
0h7zfZ99fpps36ug00/aKErRVhEFG2Yovbyopzw7IoFXlPoEDGgMF9fAFYdTV5kcEyzpz49BkhoV
9uVR1577uGD8rp590GxwZXwJcLneIEGYU/KQfMW6pazGfMQPW+fwZPN8N7VsyP0AdnS29b/4eYiP
3rbV7+evv0QkSQ+6B3Q2YXULigCTU4oUmyQP/KNsb7b0HsfDptXvl3UxpeNvYJeUV/Yw8z6TLUyr
kIjVJO3UsN9AvRydWeLLRwSGD4uCPcTsFQ4OOM2OFs7VOfdHkzZsAna0d+zJmv/mAhiH/k78/h3Y
g2N4nRdqsGBaPmT6Jj5XuJ7/JUEfneX+EtcWRceNfDVJVNnnkjROGtXwhQcWO/mxpT2YoJSrHcmb
81VxMeqC3wcHqBmQusbQ83hDDSf71sbqHM3rMR1LWKaSYjJq5uENZnY3k3ZT0lRj5vmL7ELo+RuD
0R5kbf1qwHMVBuFPBZB2YUFsVCLxhoiAvCnSfVmxjiQuR2wL+s4rQre99WL2WiRFMaIOEAKhxyTn
2p6ndASHN5a6CfrE0QPg3pm626TRDW0truhNFkZr0/wK7RWr9yDwEh2q4QlgvfpOMLbxGQpSjbAb
m1RVwqqTYxjqlYBa7vorPFOCGSfNnLRnkkUbmD4ER7AWRq7Vns9h6Waa3VHS2cEdoHcqMrnIdOKN
/6an8fyNeYfxbxaGRpocJT0L+vbI0V/fccN2KNBevOlMyGmiVRzz5k2RZWfEZM6pLudLF01lt8hq
FUJocj16NGU22Apnv4k4wfBh0LY/+uM3ECBbsB9Vql4HZAh6o0I2x0AyKifD1ynqT0s2UCxdunDz
TcDfSuQwpGiKaQafSbvqe99Z4+IKLrJi0IlyB+HWywjYXh6/dnTWcb6+jX780hnTOwBBzjQQxqoU
MxAv112u8tuiFnwe4xcMXEnxOaM8vCAiwW4/mD2gPCufTxrskxkQ6xNukoeJIlY8oL7J/Eihc3J0
iZtkG1VtueXZVK06zsSzHb8dl5iwoTmcdEg3pbZt6g4Y4A4LaCqeWudQ4futJa/qiF/pGxw/VKg9
6FeAqqlcRnN3aUcbHp9+paf9xHAuVSZu9YOaMxzn8+eigA6p0hOVY+CLnAcFaFC7TeNnGt99JiRM
gJ1iTfS0oE3le172U37KYATQhcDl7dDHo1m9jFcNIau7gLXLfDk1JTRga8Okol20/86rRRfdVbY+
zLjarmoSBBg56Feb//yvEwmGa1iZkFj7AoQUB6LCVqz2H7zZN5Q7gF8HoKU2kIUgJl6Q+o/oD8d/
ixIXG5fMnu9HkbnUiVTgxz0LXXvmdJZ8kwiEEGlmI28H6yiKnIN/AE5zlqofy5Zq/aXvafTFX5Vz
Fl2++78n+hBkxM7A5CI0nda9wBt/G6dCQpCng+S7nrYZtpdi0wh18p09LWfSqx1PM5cufbi3W0Ty
YIdntFSWMXX+2SGQ502QEPAJVsa4hJesGgPsMTpu8jAPyRNoQRG9KyXz30B1m4EAWtBlO+VGuOST
gdHOdZRWr0WqhB3Gx+fqCUcIkD+NuF5fJxzzLQk2/D/kYEK4eugP0/qyj/wYKBLSkZR/K/CmKRKX
Cjwp0f06fOOCTRpIhXPDmh2WZ8A1gjnGkDJYasXYaJ4+d0rYXbaWBgrySz27V+EEsNOXrrO0FRhW
gzKRI8ZKLRuwwZt16Aeg2W/FrYfaN1llU48lG8GZqOBcYF0uR45DRZaHl+LVkTptb0+hW/Vr/o1B
jdY7sWFRC14qPKUZlCf2UodxIaN2u/Ox7WdpUjsWnQweSRH9bL6N4xbnJBXx+IOa2CFW8EvnmSY6
w+xJWB8l/zV00pB2DaoYLKMELwbpXE3OCCz3wlGm7R24EY3yKziqQ2dwdDuI8SR+rF/rzBZdvvAz
hw4F7ubWqigo/Fm8o6X9UZY3cs44Rk2pg8ofCAGeAbqTCpBIG28ECLFid0/LWNMuONqo0f8ETS2h
UC2CGmW2K/MrC+nFLJ8BhtV9ALP3jKyGLSoRIS1SXb+HJhSMNEC4xZIbV7oQUvSZb4C9hiC3p334
Kuw0PB230EfHoYQZEmnMDL2gscMp6APitI15QZ+pdS+xPjw5InFN9OWG4PmfWsOo9RGJIc23cGju
coMdMKpOAcLKx8qPhomx6rdiNU0D3xv+6kjkV2VwYxlKNI8PHkhboYiQTv+LV6FyvVXUirXP3Sax
Pq7mRLlKMgM9PHddW++ZCyjt78BnfMe7GlbEb/WYTs2AMcmcm/Cdf278B/R63MDUv8vFRPb53vUe
CzmgGmFxotG1WVLDJEkMSte+UKkP6UIXIPxD6U+8MRPpRgSHILtKsai2jVZtPXF66TtNsU+TbB2O
MF6h/r1JtKGwAoe/CPb7Z0ccr6Vzm/ocrUc9Rd/AyTCINQzA1WJSCLgUuQKDKq6Zqv+ctogjGjcQ
h7uuJFbTiNyeF8E/kISITmontc/nh0RRgIEni3n9SKusV9iHTaXVIQeQJmhYjlCwcI8u7x6GSJBL
WErhS2hVwDVooVGqmLlFkyvnBZEfFx9iQujbUxLfUmumc1sB0EXCzVqAk02iLzapQY8Kv9TElRid
YR4Pxq4uyn38UQCaNV0mCXp3mrjxIpCW6NIgsaqnvyEikk7lWy8B9nWgnTfj1jFkVDEuUmDjZIzM
kDhFzd0ImEqQz6N8ksHO+gK0kp6+Po0X7N0bLDMjH33MNkPuPfLUPpam9KT6zhPxNkCUfmJN+ju6
iUG6dOJL2v38xksLK/6Sx0WtgnE/xxsSliSumVnJLGL/+wvwvbve9ozSyM2+Y90UoSpUoanvDK09
VKlis9ivB85QkNsiGPPjWM27nLCWdi9gRNb9Gxn5pOOGf4Y9h2OTrIXn064ehkWMsvjFPZFFnVXb
T/JQDSbMB+3s1mULoWPZxH1U3buvDd3zSIJknY+suQs7DOjz2x1WpsGiu1U3NE89QBXewgG54eyx
pg07IXANC5HhfI+EHd3Czw/JRW9BJUCFHvRZ7wfe5+IwCDgx3W8aZjge3gRdlyWY4VxdAAbEiSRf
ERb00/QZUXhcKwV+ol2sNDtX6eLD5pqZpr+goWRXiH3XKdon/3EHa0AkUemd48FjhiTzQ2X2kWA+
T+Fli/tuuDLaqkanXil6gedStUo6NhZ3XMdR2aKyBScUQZq1H0/JqpTQWe8hXNVxmLjLsLxZJez8
dRHd3Xi7oXk+b3oM7kuTgl06IYjZ8oyXbDkzLECMCL+0vaDD7aWgjzPnCnKydSFQzHMnUoNGUxG0
zEjyL9XaXkSk7ArDF/F2lycUzKivWCuFiiVqZqJDRRYJiUL6EM2Mfplzst/SaImxjbh6z8EuaL41
bPChAJDZNat9xUISBzvkefGambOOpYu+nSWPPv88SudLa23vGGiGmZumjK17pzkPKesiQDxZr8s8
jsImpLRlEbnOs2nnwC7EgmO9uXi4JE+Vb3B810pMNIawcd+Y0hB8Pq7IilOe3wC3avCuEIpK2WQo
S0szYa7CyW7GcuuvrH2uM1yT5B1nm8iqLxxmYsaD95Ikd5A2nUox8m7NRptnYXCdLxtRybdmholu
Cpzb9i3Qm95Tkrb8OqZBiw146FnpcOMFO34dcVV/ctlVdno/kZTTFbQvGRvDUJiHj+q943k8zFro
5V+abMFtjG5erEnAuM3ELHo3kfiW2kZXeKMLPaRyHaUTvKxWs5FFue+j0sRVjV9R0p36p6DIPv+1
DZXUy5DVWNtbT9/YM85U2a8VwBjS1LvULWodWffJgWDake3p6x/CQ3Mk7O+CK4UxgDPLuqhos8hz
C/YEtieYjMuTTHPoGevCNG/HVo0JgM6EBRvhitttk4Mk6OiaV4NdVJiwxNCY7ro/6PEuoJy2YpKc
uTm41wz9bGqGlu0+MgKX0DAeL2fz5Q+/aBqTY1vl2dlXtjSb64AzdlBlX0bDLO604GJblYTgZUja
OYeSmXhKCK2XyJ93ba0SEvSZnU4wCGK2UTNzNuB3S6UPnJZU1vZjb/C0EamYLqI7NuAnJHYjgExJ
51lwyyghmE55baDS9W9hHYAJhLDCCrVDBBLZT4GfVhJbBo0zmRCAv4rpPz/+V8JtsKnPHe6LbeMG
OoOUNnwT08u0DEDPYjlGSz4itoB9Js+czCAUiDLeBerwTmK97czEj8vqp7EueD4KLlsMS584jZF8
4BeU7YbwbrPe2jf+4E7+V9RkoZxMKEBlQ+8kaCP/E57GqylmYVZH5I8soiY3SP96yZctZ/W0r34o
lWw41qbKaggjElcaFIaRPGdVnQBXD77vuFrHtlc4/hAC5dsgJTR3VgSJkfZ583DwUvxCfaCS82pR
OJvUqk0xMTFqLnp/s4I0xvTb87W5BsVq3ybegUZrENx9law+drHdBwUpcrBRRjDtD4jwYDcckjfa
2K5xMf1b/44D9RTr2FPrlk8FJ//ScLtLoKzHZ2QfoCxBR6s81Wb8spZX3HwtmCc1mjIlB0W/sQN/
pSEqQaxBYElDoaSqTjY/lS+VvpP2pUScKIJV/tlZvVl5/P9DFau6DmrT4Q331lQtaTgOEV45p7eC
99+WGfkPGCs+FUR/LNrhsDOHZupf/5EJXJhFy/tkY+OEhFtPB/HZ//nqxvhxjSzYSG0F0GQvHpP0
rPjh04T+jbfKUoKToYg9AtS51Hp1RcOLeH17RN6Rc8++6S2cKZaMkpA4QcQmvm9FmyeCfQCjlpFN
SDaBkuP0CT/mZEx4k9MWUdj3I3XP7uC6HH0iepomRUicOhgXl2EQfGxD9x0uNgcXnqEABDwMLpnf
Dlo3dm6C/ShBdUP+QIQZwSaE8vr7FZa+FI04FKkyWo7JdlrKY+cA/LuTJsXfeKiE+fRbrHVZtYUB
ktuxv0JWquLn9uA98whMJ/1XupSVGRkey9Hv9umj6N6bJ/9KV/w3pz2f6w0AMxZBpq/8DAEEcVVr
Xe4cpwSyUVLSRJMKkEfms1tzyMKz1ir05VWNcx5gqpZTR5J5mqPmnB9k8eE9VwikZ47ffRzyvSUz
eMQLeAhSEqn0WiB+/dL8VazEK73658E0b52wHv1DvHwT9a+u5B+H0rlfCNGNFTbOQTIcQraZjnu+
koZy5xoUeCAxIeuq5Nhe/AJsV/tMJUB2AIY/3LkOvycXiNC38DH9s0uwyHfdPcP/yp2uBAtrJ/b0
FTCtzLOeeQPrKwZaPysAPPIxz0MmPmZ0liVmP0h0RWPnkQzR1jGD0fHUVfI9lTtV/H3amRSVvTTv
DssRBC/EXMPW4nZLwZpjOLLX5/NR0yP71GuEN6tPbw2wAUAJgLTgOKApbMmoryLQB+uv3Xgi+J4H
NUYM0FDOJAaaOb5n/kSy1VrqRX18WGhhMJn6MM4+bweeLrLwvShu0NtGMCPv0y1DflQWtXy5ZJ08
bUHpeqlCp2ISEjo/SZeX56MsbZS/w+TCWAPBuXKNS8uYSMQNbzIgl3yEug8+eYbO9RMU2pwGlH9T
9vTtBaoUbCJcbdhDXhfx8Q7gZ1U5yZk1QAJafNofE7QElebdaHak8Io/CQtda+cDUMMC1mpHJ2+z
qmg0KZw+j2FlRzDLZOlNYWyok/wag6H3iBO8s3MjzEpW4/O3b07SNFN3sgqSkvaaJcdJfv8hpOna
KbDcDnfeUiu5Ck+AhA1oKF7GeD3jfraCCzfsujZtldq4/pjY41Bdzq/4I9dPNLeaILvSVyH5pQrl
j08SFrrbJL63A5pflsBYU//dwTe9Qx4UWvrLpM2bUq5yVEU+fx7KRU4pTbqnu5gtJtBiqS5Ij0rw
2j7B46WeXs+KnyCL9Tg4AvLf+pXBYsWDWYeq5Sdkl7nZkHo8nqmtno5apylk362Gv3AOzbyVgs9P
Bpxpfi3EgyGihFTkzIF9lcNVBL4lU3DF8/ohXgYj/WjvtqIJItHXEF53//Sg0QQ09rdOojokQRSx
zp1AVmCr0h/zkgZIsFeGgRQ7Kj4gtOTEEapLxnYiNBlqOQL5HPLec+qfIfUbN7PiFsF4++3Rit/c
minwlktpsV3n5zA8QGNwrTnAU/O3NrhZAKMY8SiXnwpIE4/G6VGwWGBlmZCIbFCKukWj4RQG49UE
Yl8y6twFn+wLm3pt4NvyOE6+e8iMo7Q4YdmbJeb8C3HLxB9PJffm4rkbD2D8B411g2i3JpLZfn4i
CuiyfPa5FldPs6jF8SDrBswZpodKsFUgHTwG4VtRbuQYGeJ2KhAL4ePKCwcPQ0Bchtg2OAaPAIHW
0X73WBQ7iDuVInzRmxX9LN3koS+G8pXHkt8n2K1o6fv/p3mexDg/L/oZL/1OKf7kX2pzchgCnsPj
2S4W3vBcJRrfGT3UUyzU/xPYTfAruDqXrj00DWiJLL34Z3paRp+xPYkpI3sj5S8XV+CxXudr39Np
/PulNW91MznqlrSSto18ldSZnZ/GuhY17y1iq/lop+UrJe9VBSiAMcfIcw+j8Or7njc5nhscUMUJ
K2e6lBfCF2+3nv+5a4rMdZ2VVsKbvei1ozIcXHoWce0fYcACcz4/KXJNpdcSZl0/UKYMWtaGZMLq
qmSd7UaoA3cn5VC6+VIBdgmZQ20gj3xxTCjfy0gbKmjYeoNKZC5Jd+6pw1HUExcsKLkhj8Zj4VLz
jWkJMz9jU6fdXHqRCM5T6tD4ptXnEnVK1UbMD8wk6WcTPli8CtJDuts1A9rNrgJ41U+8ZBTBZ/U1
kl8aJ2pKDBUZCxgvL9EFuDagREyUcGQ7QXx+JESYI2gqXHPmaNEiOuF6r6SGrLTdvNK3N+YM4Jm3
FQ4BKz4gi9DlrwxegtfrEjHwZJ4FIIuGk4QScuxQoU6mjX4k6OiPi/CZ4hWg68cnzt+LePEZpydA
nQ3qZwwf5AkSbXE+NDPS9icEZ6UZjp4fGuHQBgiSLzi6lrA+RMVR7Yf3OmywMn9Uwhq0gLssY5TX
XYimP0bMl+mnaVBElnlgCJe5sGj6P+2g4nZylfZ4HBzWcWNHw7yTb/Tkq8TYunkbyYiwOmWySa43
Fp4r3fht+pEvNqiHtWF3AAwtG0QP6v/yVywy+hKSaYMoDdmHSLKMQqVgi4vCs9lDENzX/Y2txpHT
sWMiYh6YGcxoZ+5eGt5SWF6JnJ0zmyiPt9qIX7DzOTPjSDh+d5LERbdl8HNvmSw/7BtSyoFzyuXP
jZD3ZLKLs4irdqiOLINiWf6YGz1EQhXwdUVP7abOVjVO94fuKvY0PBzap4U64oTgN8tfc2WVRCjs
xgTGKSWveAwu9t21Bb0ypudHyelHvb0q/dfByUGzNa4dy+1eQ/WRzrlKQcIYNUCaJcvLJMGl2ogp
S3UGHeXaMckjup3bntVZ/6jF7awijFpMiYssBvurhxuoz+/h3E5XK5+1O762pTVk4b+YqygDQjxv
oZicZQYrfB/1xAVHJCFqicraQHzmLtWPKt0hxQyxUljSjL6sJxo9e21gY+qBGvsDmBA/Jodcb2eg
cdlHqhHfgXK74FTgE7UXg4F5Qab0r1gfy5SNsXMSzih5ci1HFS9zinnPlVWu2HVmcFVqQ1iAQTOr
in6fNCzARUd/Uvj1r67gXOi8lY3ygqUsSKD9hFqCvaLTALp0sko46FpTRHhxP8vzMRlzrBbNgjC6
nPv66NeZ+fiwTeSgpthrmY4AzcfUcE06zAjaAksOxf5vCNkyxWqbFqZ1NHUtrFrHMlfKYMR6MYI6
gGloIr2jad1to1FhEWkKPFByK4wSE0w2vhKZhhgYAYYdSiYXFYvnDAs8KdYuBROn3IbzTOjb4DzJ
mI2sQj4khXSz4YQj0KvwP6+BDR/kwm7fG2qSvoxZU4xNsuKzyu3TmABa+dUfqnVsF1cFRu5QOiAC
/0PTq/g3pPEKbU7P7bWWl6C+X0CDVPH7kWMItaYso4qjkhPzpjqSHKX46qYNTbNDbwV3PTzWjUN5
TmDLYh8j5ZRCwTnG2KsS6UArEhVFJjfgkextIDOw3wMV5YvW/kGAyNfmdRONVse25XxN++Lv2Cma
qt0OPjy7oYGJe425YpFcdzF7ixl8AZtwY8pSspkV6me2P1v4IAMOOjsIUwRzGDTbTHO1bryDVpsQ
kCda+VN7H13avNrS+wCMPWXs8F/ZBS6DEazVLUVu9Y4QIg68FviVWBHB8ymn7h6AOk9IuOs4C1Dw
bZfE0f7mufUT4LU2ynnawt2GgrCdJ+kjKBDwxUTgZ3S2CeiZZ2af8/ePclR3q86jQBwf65cgI6Om
InsWE1FiEQOu0Uf/1PbRKKn7fuqIuix7+WteCMe3WJSmQu37iZLhTls4J+vqTgA/sw27ic/cce7j
Ek5mNGs6kjRUpDjWf2OnJQog+EKwk9KhZh/gtrsgo4yx2IF6/HOL+HMEuumWd9jusa3ZSl++f1Pv
G1SHuIlv09USCWfNDR1RaQdOQ+sZRy3rmnalhOWwIBxbS+QJSWVBMYE9wtGqjYRv0YLPEFZLc4bx
lSag63wyXJjqHVWndYLPArVYcODF9BUPMkxJbyrcP3SukgewunVjFQkXClXC5ItAeIvkaAkeBxUG
xPxRUlPFOCpNdpsrE9DtAL2Asm6ASv8ePPz624VQeEAqfW/aeXDcRti5dJo+IAhfflVZYCi+9f2b
K21XFa5N79h2F65dpzcK072Tc/eX7lUJlUKE97mndt10Rj7nwspRpRTN5yKZPsPG0w3JtVeaWgAw
7ORuD72YszaDD2iyNGA5/Q3wyX6BEHwHr5WLLMP0dBZo1OTiaLbzcb31XZ8i8BD1vnsBrzhEk5/e
nmX/7NKYSLW6psv7Etwqe9AX4sF9fd9BY6mHa238NQ78I1edAwP7fZb5RC3+3K/mRqlyWNOuQEtX
QfSp3IpN9pM3Duy/6rZ60SAuTorvAigQluLZOZ32SluPVc8lUSRbQjiiPqxQn6xdZwQfbbpI/Ayy
0SedA8m6Mn1uacuDMbKbfV6GBfhWw1OEHKRuyQhgmVUrmwWGmqDE2kj7/EqS3DGL9f7sjXFiricY
a2F2wDP4NpezH/+4R4ODAfct0xTD/DE+ZtJLyX9gpf/sa0fsla95QTRt9X95/Kq4nUP96HLAdYiX
lGEMqcPqDzBeF9PFEJjDeP7288xC4uKs3XTSnhrCwP6GTU55SNbwjbSLFUniC3FR+m75eXy+QZnf
SVAHt0TFNCJmr6h59UIUdE3YdnGcUcJQvhYbbWZGxyWSUn7uJEKQZQmri37Obx+4PMPvwDztVVR4
1PwPwR/anviEKhh2EV8FRmV0eFh/w+P49E1EzpKj6AkHf/AGTiuneYmzGQmU1jYxy1JANi/gF1jz
CI/A+EwZknnIlaMWr9K2xOXJKH9hit5S7EIygLGtgA1vw+Tb8JdbQVwXT8CLYqHEP2XotqDg1+Wk
7Mmjgsrhgu5x6UIK0n1v5Ik20qYvwOmX3NTcwE5zxXo1pWs9fiOtg8+tS8YU9Masp0fqzjhbqksv
rW+Sdeed2U9aeGbsTDDVNJ+78mFbYAxmaZwPnG17XyL/LKdbPeWyWrKIlK5FBfrRxduoc40QTJiZ
S4m7OvsP/Y0ag7VX4mIU5ft3qVX7c7vVG0gj2IQrtiV3jC0WWFTDSQPFse7N1D5pXgkeSvCVXdHF
9UqYnFI+2600IXLrsqPb/Zz7nqUckqhZvBMmlMfJX79UziFDo+k6kGOKfRaEOgE952iZq3StzxwW
g39VWyOE0peo/FMYq7cn+EXFdAgiiwA8fq+VMeUHNorO4TuNEeJHzlfm9VqipU5mmPizIjS/8kZp
WH4otR4Vq/yWlycZo0NTeK+jXUULh3YORp1sO5MpXdihfc913IcBFYC8h13F8rgB405kb+msdTn1
yM6xeMDWDE2sWbsVMgEXZRQN97aM1cdz6esbquq8+bMIghWlH+LiKID1QgtwfSPKNADHXrIe39JC
wB4lh6jvzj6hVZBCLW8iMYK7xF8bq6QEIkR6d3KRh4RPmATf3wJrxAvwsrft+iegaWtOzKgaBaHs
yVl+hj1crUpt21knN41TQy4Jl9GsX1Mv3uaXwR5/CxF0s/pvxASMnorPU7TfxFzxiVvjfzuKnzpZ
Z3seR/Lf76u5d9Vg1aQHe7i8zPMD44OPYFonleitxkJmt0nY3aO1F6y6JnawQGODi2pw06hSOZUr
Hv9Se8KyFz06M4ZgiahRM4UAVOK+gvWg21MB3xmk2bh85IiXuYFSMUL+q1bWjI5/3UeLisIEOjN8
rohZ7AuXmfQDo/u46m8ZmmUEIjwVw9U9LVAPBqtZlxGbzDvpGcZ4R0Ri5gbwYvFqoG7Z0C980mNC
7VfrwZ9349Xuxz92uTIitbVVN5FE88W+eyOyQvLPrlPJ9zzz2K70unVCNeEH1ghai/TH0513mfme
nFqkx6zPc0Sts8pSkE4u2c1J9hf3t7Cm3fgmDEPoy5Z3iqv0OVrghX1x5l865Ry5tgbT0eEsNUmK
UykJxkvQRtyvOFtmhpCpBpbXrrc5XJtXFJoG5AFhtBP7hV43s7n57uZPIvFeEHvskumUUjcvnyFn
b79QJsTZerNZvgQ95vjkt9hyiHwGPb91WIjeilYejq5+mX9AIvS54vjMHqkesysJC6s/hB8bHfD2
bbctq5Q3mZETsBgvq28nN6MHAUs8Yq452OYXUxpbZov5nYHG85rreBfrUHfJeUAiKqQuSbJ4kSLD
79+llqtNxDBrsd3s4Qpj6/lQjXUfLdv6tgPCZ0ffKKyQgm6X64C2Y5Xb7/Qz0+uCfPavBYQVH+Du
NbEh6bsRi9BpBaziiHOuMLD7uzL1CGGGwB1bIcH+73HvJUx3cpIB9pOIRMBcB/8ETQJv5ABL5PPA
TSk9IGIZPjziUm5JbN1JlRwpkLMtsWF+yP86UuM/iD9X+C9yMpAFohhbvvvSh205PagNcp+QQmyi
Vzw3Ete972DqNh3Ss1doLxSCgaSnpo5FRz7ZhcMfMSnaUYD/7HPPqCB/tkSn7AcX69yTjj9YNwpe
Swg4nfb84DcY3svF2VBPTjR8dSyzXDc/oE6cuoGFuUQlxlz7Oq5JFQFIdOK2dL0bv7hTJR8NZgne
7PYDpF2OQYWhq4elBc1UUlDhCQzm7LpGXMOuRn8y+sRePTMoC3TwN2EA2eDb3x4oAkLfZyWVTxM2
IhQclKNpcUwcxqseAT5xMKpdm6EIfDcMSAKE0hqW+zlbmYTkNC9pauGtE7tjDHIKn8hKe+cX/5TW
VJLQS3ZsqGdc9t/TeDJtG0vplJ8UKbHm8AhRPKZq8fH55k5xo+2QSH15WX8qD8aDiKq8c+lMASjE
mbRkqJn9B0vPfoG6t2BBbjNy8GbanAlf+2nQ4+XV9qo5twJkoGryKL4zYVpGs6DBG72t07cIVTog
EIQPPMqj6I6VUcUo212KBwb+dKLHnRCyRvgQiDW05B29zfw8pOmolpEZWC+3BRdwo62HBYGCWIKi
Tn2c4O4veLscz3U960O4LHD/bC/7xNyklXJCzh1PxApiNrnCI6BZmF7OXFewaXS7d/WkIzgofg8n
yQxDRKVHIjYyI2GGAHduEEC1l+1DROAmM+VCbA8X2r+E0ixYnyZpEsv9hUqjjNaplpYrjTxvTwCN
K26ytWR8h1sxsota1SuMeGuWojWKc9k+rxaqtA2FoAqeJyoiAGIqV/QEEPT2wCAq0pUxUSibQHai
LritFyOH7L6WEwvmELiODhhyfxL0SteNf8X0DwkLyVQObptQxRCuDuGYjZJrnThZApH85Clucjk6
GoJXjpFpxGI1UgFzPZ4xCt57UHvsKZHYiKIZ9ARKuUODaguSkGGKduOp9AaZreIDE8sBecb+hY4R
ZSxs/rgxiUqbKF/2fRCaerLg99rI8MgWSj+R53144iD/RENGmaVcfEMByHYvqkKgu0Zdz3q1/CRK
NZGQIkqXo4wDGhqSdGafXfkJFCwiy8u8baKr86lt6Wegpr4HHgvl73+lq9palLL6O6WqkNC6yI7M
C/c2eGcpQ3JV8aQK6WoNNiII5setelIXgAFfDFyKaRAQWswmG0p68MWT/HdCuJfxNfhVzUWB6DTR
0Rn17a9gXOCfRDY9XYf1AM8FYR6rsPVzDIsaPVL/RHNZTM3y4ITBUACgJ48p4Iznky2a7rleKfhR
hOHQzuSAoYQcNIWwtOzRbv0YRKDbh0/qlkoeyFbcWdI8Iz/VxuwKUg/SDnu5sZCWHfI3/9mZzgKO
AWLSWWjhgMtjNu6eXlJDC4gaVOQrkFX31xLzpUVAdplAPPwkNa+yqY9pCXcVdwkt3f4tBrdQO+TP
9ktYGL8ryCFgj8HMzrcKBfvSvnhdU+zwRfEnobFI7Sg8D5oPSBQoX8Py8l4OyCVCqF0YyWV0Eb4A
M2i8jVlebFv8sopoIvc54y7FTAYpsQsxByNKA0IoYgweR177IN89EiTZDzYln18ezzk/Lki0Egd2
v2Nm9vVXP7rFljhUrL/L++YgrNXQ41THddxBw0P5Eeu+yGksZBCAXnPePyUkXXNGmKXMCcTOi5rJ
NFhvOzCyjh6sNYQj6+vMZiHWLBPzdG7DRrOlXrOBDgi53B+Wq4JcemDzZxZ4y2Yp/vP6YmVg7BZ9
TT7+7WLEcsF4AsieiVyT21fpv5hKovW+z6QdgGZOdEiLjCaB7ZGmgri+OyZmz7Fv1RqVOehFVSbB
3oe4IunQ4wzNGHxNjFffaYKLPeWSuNpBeuGHj60mBGYQ7YSRPiziAUD/C3l8H9hV3EtGVJWVTbId
xWrmsao3axdhTcIlnjk+LQ7224VfchnHDBmm+8zlsilmBeCQMQvRcuXyA9VW8tuVcHcm5ABVlFDE
kmQwMtFS9Gg90U0GvnG8GQGUXYNJuy2ag2LooxmNXX7jvqtxdnhMs+Cwcx7KFItvo+jDbPLd1HIJ
MG84eORuoJYWezK1R8S7+xcLHi3SwygrIfpx4N8uZ9BDtWPF8c9cRE6jLO4li1uk3nsrt8dhnC4S
jX9/7QYSvv/Hm1JbI+p114rii+NnH0Zgjnn7lVjukF85h+WibKFny5nCBfZtGVonYTqD+bZkmAVE
Ec1rbRB07WoDCSHUNpeDa6KVbWtqmKg9hEpc2ucbptLc7JjsKa3aH3HSle4ynMZk4xHjBN7aF08y
DZ3ux1QX454dV5iu3c0JIN8YEhRzZ3Rgmh54Aa/cXyc+w9Zv4O7+XbLEfFKumNjXx+UMpzrzMZHB
T6y3LpSy9ZDJye1akQ7gR7a9wNlmmkql5R9hpoEo3sVTLryfp84FdXX/nc7+dXRs6/4JH2HElz+B
CE2Tm7/7crv7xehEVOQrVls1iH7jnIh65XTVeoC1cu2ZFTMlqUDebqU7aYx7l+DYZrvJlvzZucsh
uLHjmk5FTogFjvZlh/wymugpZ/WifgaiTAe092Bbf3c/s+Kqf3J4zQKi3gf78EWqoq3D1jNjdbwy
evrjor9CJe6pucNsspfCxZYMifItqsx4XikS2LTim1v2oDl1v+7V41aZdWYRqcGlR4NAwNVL3VSA
mnGjjulVwgc79yZxzZNdsdeM4eNtLlOHdlu1UbiWXqd6h6LUMx8syA2136keLM4tDbW+l3kex8M5
2A3/wxQFtmw8aGo9OCcUGYo6tRLkSaj4vQqUH9ZwcrznjRQ+12qcDYLO37sFUXKWnlxpwLATbPiU
cRU3eSunGBg+bhqvfYF3Z+R2srBjnTJfitlJGuki5ITL6JhHKF1b5Hsc0EbWRuX4I0Xb/GpcocGq
i/99AG4tep5ToM3yMagQlX+uvXsbR2z9YLNe/wPqzfyK7XfhrfzWMhIq1WShqudFHGjxSKw2YRTj
Ly16ImDXJNIJuGc2KNrVx95/OYZzekYzorwiPY0VoVomp8dHrssHhSabfFQo7pJQlWSAdXhLiXZr
9GOzkZq3P5UrVEIkYRek23NkqT2S4zDF6iRYepVhxF3ERn0H7ESv80pUHBfNSj5U7XhS2nItTCNb
9nmkpgz6kFMGGff+INVBjLhv0H+PthgLc4tgKVbUAXHiVIiZfj9gBJHMWDWSMTUwc23Qpe2UZ/dK
Y/Bd2k6cR1I5Rz0qC45BRZ+yAfyaqqXDMWghPc/0zIe1EWyDiWA4A6aSKpo/oRjVslVhBn1HMelx
4C5N3gXLhchAHTX6QY80M0BfIaXrKUvtVsGv0YEVK2+T2fQSjeNteamSKqRg/TFY0nN/Swb+eL7h
mw2xwoPlh4GvjXu06ORa38xSmJ3xo13pdIRR1t2/viLONL6kyzlbZ2a7/wm5ueXTMSLjC6dqqapG
ZHLYs849JNdqB8kTSX0y45JLKrUW6vCIooHdknRxo4BodoGvOO6e/Knn+4Nd9zHoXQw/ayZwYFg0
aOxocH41H9fN12CgRpZh/UxmZmp6GFGxyxu3r0AY3OOkfMZBRt8pi+K6dLePvCsZdy+lxEJYl5Sq
RJfnhf9OY9rk4wf8NHVl7Jv2h3itqIZoE+r5KPJsxR4Dj8Jl5KlM/eY7fXOqHz/6dTBilbr0KFFh
gzaHcNnugE0GmZne7G0OhkL6EfyIPfmlK6vHkdsx9CRxB1w6vgVgPoJ1THnB+/0XnY3Fo43mZfyH
KPQQeH9yJ7T7SXhfCTYzLb1QJiVJflnOZZiUihnglzB4dNsNEFb+MVTRJLs0T515uSpL7R9MuIBK
+YN2EIkQ/D/7wEHrAN0N39YqtgA3rUdhsnzB10Afnb12yruL/zyzEQ4AuQ/Cvnw5LJhqvvmh6dF4
wYSAUNbLKU00kknglrKYathQmQ3vJ+u2GDWwlHdlr3d0FtwPSDuPNycKNbOfpZOdDNPazyabdZ17
nCbU5RAwemcxyWIgfkg6IL2DAgJ3FZq/oXU3V+w5EB7aWXPOKbxXm+E5OmJPR55TyYWZbxM6B1qk
iUnYyHqLCLCmXM/QjmKWN4XrvaM8v3c6hmIB5QlAab4h+pKA085gLB91d081NTknaC4b52kc1lZK
Fwzy+2nOLMTYo1mRx7b5VYhxsCfXSx4htrCxtYPKiSgiwR6kQj3oTgpT86vL+OtA+YZ2bDmpdqE3
zYaKBFJsU8ejc/3oFij6+FtXN/4y+Md+WgEI4txfcVReeneRdLK+lLDHoIH+xCZtxyv47T+ubNbq
5tAkeGV0DCxq1AjL+9Ge0XCF+ReSJecPSwwDr6KVLyKOYftUlKO5HuQd3oa0qhCF9TeY6D9sVp91
g2sGhebJq71Eft7xXZ4SlOFly4R0ZhQnUqYidGkM9hoUU+45foVV2EBt6zn/fI8Krm3eZKEkYu/p
sfKdu6dOp3jdS7FeVGC7EHfITiyNMzGiG1C68iu59/A8SclwvzC0smJo6E6u6+SMAecWBqQ7ve8h
OFDFYtQ/svCm1FniqFtTerF5grzJy7phIqdlh+Cc+N+pbghvk/anUmcwKfW+rvVJJcA/IO3zEJU1
panYoNC8ADTfmZScOECXC7ojdCygIvg9cSPjPYSQlt5Q9QgFijUf+9PZWdgYFE3w5kZyqinFEpgX
dYXuaTzETo9CEywMGvKj6/R9fhI1kaG3bk0+uWnXiOo/Dr6pNyAhR0g3wejk3KzyVUFto4i8VjKt
YiiQx5aNFnRFgfFWBRdRQInZoxQ4gB65W0npCVa6YyB7VMfpyoy2JKQ8WsfMm61YpPxUqwMdqQfk
ynyMpgTGqhZSIScGYMhSd74WPKeKXvdykYbwidu17hdl+pr1ak2dgDs5EZgtUFAQurcPcCJr7XME
C/Kj30SY5ZXIRNcRaMkDvQYVgfgo9vKTxzoWgd2J4/WWqfZ7rMG84IbexMW8i6La5qWGNId3sjLT
bl+nRhz0w4aZiqz5V5+W3rAb2w6jUgS4cn1to0klEeZYYklfITuMlGODBZLrcmLBlRfZ2ujuCAaO
qPqUS05WN5KPB+4aB2vu5zCXf1jho3qFNzv07JfNelSzcuuUw5XrL2pruzW8/jQjqx2YQR8m52hp
YWyEUksx6nkQxKk6cl4txwhLYt7XBvzH9DuRhMdmBdmoWHp/Y7o29BkPKirrXCBRwzWUlA8oSl36
tYoa0roMytV7jzc4bG5D7DXM93SF61sYwsz+rBenuXFWtXihvzzEvo+ax+DTP3pjmeAY8rBG1IdZ
SsBnpUy0ZEeeK4RMfrehl/RDBgPug9ELO2tZaNgB4VsIRmPHwsZqTB8n1mw6/CvVzWUH4r9tiDY1
LXYFtcMUzlHsr8ctWSTALQhJHPKprcQLTSPdJ0ngFcWUrohZ9bDKVAl+8odwk2I/k+TWRZbgaCYU
1SprgLyenQ78Q1jtGXV48vv1yOv8RWn8utm0wYNbJxHK40gNTxWmjSwvmKjWorn9LgEehZbm2EZd
PXZpzliXUyKKqlZ39APl70Afxx01v7hQVIkiErjFYMTBugf3Lfh7bgreZEr1r8l4QB0OYUdSNxNt
JkFEhy83f2zFhIEexRiDzOatyzilC0p/Amq6EUK02lO9UA4mjoyfiPWc9G4hOiziaozmcVt9TmDf
z72AXjQCho4cAYX+MFkhDoEnkUbQ0AHx3g9UKH0FG5tidm1qdyFmseu73I1C4KRsLuXXHT6lkQ+M
KrwT+xObkJ/JljMlTBpXxeHY9fU0i5FFYHVa/BSjI+dzS6dVrkJhcA5tERnfYUJMa+1panf63qJj
eWfd8ugjBOen0q24R4QE4+NSA3OO+kT7KV4oa/rP30SwpHAt+e4+AOxsA6VOPwCq/8lk5uEYkZ3v
viOEJgByGACiMtmpDTX1tF+Ed2sC3L6MJshuz/+hilGbP6nZgERl0abGRs8VGg3h9p07r7sPGhIP
EyN10uqoGnHyDk8X+dZVN86ZdA07t68j3Dv6bmrd1iEZdwRNMbxlLytbRVBb9LJmPytckhiIXYKV
9QpFFZK2n0eHryNbaDyapMsMLzqkBOP9xi7ED6MtY3BMb85ylh1NT3D1vIMqjmIOXpO0BqATKEQx
0UHx1NoZ99f9MD0BAUNSr/IvGCpU+66y60QJM7JtXGzVQkLDuGbcyD1sTqJn8HzrIwmUvFJ41z+i
aqsICIbPwNEt7TGifRmuvxvysycSaU3e+pgwils4vWGBI84loBDBUbOLv/sUPvFiGxAKw5H/JJCc
afHeEeE7zV+LeV9juOvNVfli6CqZGcg+MSKjsLBCM3xBZdJ4pdKwC7D0RX437hJ5QXzTVNPtb/Tr
2K7PQjhGxGFdO4PrcUdXD2XH7d43PuMsxScobjD7QvWwBnEZ4njSx0O5kOxDpgqbL3AqSkUDbOvX
UgZ7wKVUqUdkoa5dmx9PYeaRMYgzz3Mrsx5a9KRBecN2Y75WkzpyHpk+8hiAemeFqWw8+T3LYcM1
1OHI4Am2Gj7j6iC//rywXVqvabhY/2rJ6OX8zR9A5zSzocjF6mH1uz5O0vuAhkEpzs4hSqkUHaAj
o1rSCx8NpGXLno1ko1jH8Z/Z4tySvlP66YsgI+Y9AiC/rg6m/jL+Xb7j7GdiE14tv3omHkPgrr7d
iAehAWhXN9TQOIyZLuFlENaawMHwoCVghfz9mytxqB1txhUH26IJbn3YvjbuatuNa+djlps9KMb8
37UbNB6rOdako5u/31kjO77bts8OFrEbas/rEW3ISWqx5Uv9QupGuK0MN7uWSO+Z1axFGRi/Rttr
/3ZY9U4rAJl5vC+F0ryAK2txb7ZsFeOc6HITSTNq1QzQrlleqXBMfRDthP2yifN724ZIYVpaA3bJ
wG+QZoUF0r0bNirQfAXKYkaCJcdd8UBMOthcNJ0vYQgCy0XUKg9RE9xBCw3JFK372PfT2wGkycvW
vFdn4486+o3t8wueZVuPiChMgrzgoZOFfWc+AdKTkML0HxJmiLfbGSOz1ehF7VaqawDfJWHp21MT
aSFna1B1Nq8hvj7pFUB/+tgxYrR+GeSFYo+QJUqE+CdL7Y9MhAGZgVxoAru3+7ma0UrGiP4XPrEV
FyxQ4rhGYJW08JOEte0wHwuRnNeE6ePb580i/XU1BbSPiI5TMdP3IME2UZzjqbKbyihhjeLqPFhY
IE1tR1vY2fnJltt9vgttNKpzZGKTgpu1YiMUv2ZsOhQAvpvKSzwXsta4FdqXAozmnwaDJl1TDZe1
XdBgw8ufZcwxlmqogbfi4kSL6v62zQz9YYi0wu3PZ/xdkjA5zxFL6bRD90AoJJkncdh6CUz/kdwz
LHV1ZbfYwLJrvrjvI+uAX5F9Z+NJiAUnztiIhqvLDBdJorL+KEngSxIR216VoBqWMyyzHZYB+oPG
cU6aNSzWGJOtTucbWAfOsPSkxaKCLJm6kbrhp7eCAE3AWe3AWTZNArJv+a9FeJRv+mYhgPaTLAz1
AA44atStiXdugB2M+Oq7wrYLnmkAcdaqR5/LsG/X8CYhIJLtN4pDAWnuwOURZZlEpIcRe76RstFl
hPHl2EeCwaAR5z4dNj1FFTqimS474PU51eSJJGW4tTMzncfi6KNCzJ4zjrPv2h9bWy7BeyuGuPYM
FpsN/OfJPrRt/nYmhNBeCJVFRuHwyBmotPUQMqGoY6+HS7Mm9NrEKKDM8vj8/fisZy2N2wtzNYtP
lR66meJEUPQypXw6WcGtBpJGJX6972hz1qAPOfskzaag6RWYPnZsQaXM0uXhI9aB4xsvO3C7k4Po
DqxRRn9cyO2yv6RkXl1B4W4ksm5vFBA0e8FbKSXoFIGv2es0O1R8eISc6j9y0xeKbgYjfwvZ+q2W
fTWSvHqqZ5Gi/vaFVhuW2jZoidPKZoFo0fXFH0oR1WurjSB/ohwuZRPqVrr6fua3ETs+4XesL+9v
nNnQ/xxJhhqTmhE89ORl/KoJHN40pzSWCBygxtT0U8SgmifqvwGLPil5Ie3CQektsZHbRP0qBr0l
w2SoLzBMRvjAR7D2ApIMKYIQqFMqokXTn7Hz3pkdec8muANipg9AawDtshyqDSv7gwMltvTQ3ckB
l5vk6xwKmGe/GJxwgxbV8iNTx2CyKtN1Sf34Bsejfm7Pvlka8RwCNzApbmRetVvQ5UwwOHBiQwpC
gA9aESSCzQndIMTJDnf6ZLSKk6K1QW0gbjroJ/Fns30okZLlgFJa21hvm/AEb1QENpHeckwA/vl+
niAXj+z/WL6XoqcfuYp1sqxmfY2woaBXIAra2CH8Il3mm7/c263C3JFrDbFMpuoqjfVOEJx5q7wO
SMRQ1dXkbGWtu3IsLI7Uuy2imLF0B2RYJpRVnPOcPEj2KusBqEnHDxScMqPjhwK1GH/pkN5uLmye
ytjTwgzlQdHiEOdLJNpAuQ+f++aj9MMAnOQo8Be47wuqSofpPN0D2JVIZ5kcnUy/wzlIwCPIpdLE
rh7OBRyoemqa1fewyb2E2h7T2UhghY7koEGkwSCgd6/3YHaznI3jw0blDkKALIxpwQY3cG6/5aqi
95A+2lJop+0fJK3MZuwxosBrFtcAK3zkooqpPS95sAox3VrPmf1axreeSbupYra+SgrSBtu2Ym5c
5gtMCBFs0oIVEU5R4ddKsaNIXFVEH0GHx/edYxzsNK6lCX0FL2UbdiRiUI0vz2fVi49x7VtNJOhz
gPrLZKHskkDD1U+IeSLV8HKF78sWegkSpxrnShQ7nZzvuU0jt30inbPuDOJFMGpEUm0hXMnWZErx
qR/PD0vzBbdXFRusJfw1r8IiwbjZHmBqSxSxY8klgMW5hPgED1ONBq6xRQN811CjiG3wy0vxZEPF
hSa/uslSFLkWd7f0Qe/qdy9MVmbhvCO3+Aw/F1UfYs2fWfa9cOk25IQ5kmAwMJmPQRrknhLiNFHm
Pf6ePKJDyx+V5hnCDr74i4kxBkyeU5QaH+LO8Rz28NcWKqhXE7y17LGAZ3aK84tZ4tLWmMwunRng
OJxBeDnHr2P42MGwwkg7DZWGqwbfra/sO8HhWLtBjwYppR/gn/uSfLL3WTB6wvKBfxqCMsMZT4fS
YFqr1An7hCufq5yQrbkiruWUsGmlPZ1MhNR2WG0xh7JyLPC+Q2jAoPB5w4HSXLGRG7ABMQ5oTsmr
Z1awra1wBarIZ1GLFquDE6qa9DYyIRaOQwhveE9TBNMW+DmfOtdnaIZfPMLSzhONYx0cQ5ZjsGWA
ip7v1fMYl+qI23JTB6pyBrDcHopIx9wQJtYtbXd8yY+vq//Js8OaqejB6pp9O8wqGkaGS8CCRaKB
wFGK5E8bumDaoFgG+snxJwuB96/vdkM52AdIqpyl+x7ueckSabtzqrK8V3H0sTheD5FW4HCUjZzV
93tVEN1xjM49/nGxS7EHHUxCZiD2ymtkt/30kSgcZn00DoO24gk4eRSzoZlb/IE2h/7O17gHkel6
3Rn6vhXEaR0SD1Vhn312NmzJYTbJPWW6i81vbzmqq/EbSXLSpZ1V9+NHMk+Qa3NL6TndlNsDsMFI
u6clbsgORp7dJFlCr4zB93zpSto/kFQBxvUsiqZPVXmeYvFXK/7r2hvw3i5igQvQ6LG6uo63IJvL
x88ux0qYRpsFt6BzVDqXq/eUipWoegPuMxrh157IgcX4TtVjXPvWhPBcr+Q50hXHi9V/CUXh86FN
twgszcr7eepc1R368HbCGOEv5zCrih/XxZiT1zM9YszungO+1RFWtXKj/MjxkzYJUXAwWgM9sSYc
nxYqJA5E4iXgnP6YjJibHe5pWXzkrQGAoBJi+Yq4cxzw52c5Qx31Lb6WbEUmbaNtW2uvmnrmFEnx
LNDoAVAywnH4Z00JEGFsOk0eUYgxdkC5f0HCWJ2RNBWQuPqf7DgVNZuBer62PI1CwggAl4YYAahq
jHfGnxuCaF0Lj86Z7xVEIGgqX9v/8TLA0SoLe6/32pDpI09HwKribLzhYjIAC9X1Z9JHCDLeAdgb
BwPNnXWwH14pBR7nzwRb/xSS5b4FSIYC7lVv8Fr1OhVCTjKGA0zWVZ+C439SHAsV5nhMJLdtNrrU
jHqM3OACSJnBJEB/NGVDVS9/psgRUQHJlsUsJjcl1jnAksIXCSa1pnhSlBmyYUgZChehXdvhLwh+
TAYWsFyg3ys1c2DL8XkR9AFPDuIUvxj8EufTFqHTf3fzEedmtcBaNySjyzvqCL4eqHhI1fSaDm2L
sXyHWcFR+tJ3JykpiusFLFfnc2v5vLI6WktNNk+6WH7+hUODSc5ZYmglGjW1lkXiEbYYBTgXchDg
hhNPqJ5PVydzKTg4Aa2zJ2YWVgH9jylYnq1JyfUAqEEMn5mJteed5U7jJw9Z5cWzfrT9I9xBewPq
Hbd1cnj2od0+I+mvKTJbB+E2mZpcF2phoh0s3jX7IDp5bqJR2z8uMaIzqKgw8cuBZ0UE0hQN/Q4x
k5OZ3E8vmdNkNfsC/EX+d3p7k3emmgC2i0IawO2qXxaQTujQLqfNT+d89tLmlBrNMYDJsrsj45NT
4fo6fykr/bhLeSY2sbp8YLHU9/Sr+6idWGXHX0ZFu0atPzAyWKZIgDHrwhVlGqFv4qyNSzNqnqXp
4SEULbfDnqa+s9deB4dExcl1rdFSGtWbNWhyYQLu+62465iYUWRmVZKGl+U/i+bZyEtq1hnBduJ4
gL6T+WiRwr1xQOaBdPLfAnZcWmzctpvoIDZO0yg4SdiHbzU93Bj2chWNsvr1PeGdDmqnxcqFaQX3
R3STv94ZCuEmmYN253OdliTJFTDrjp1cLLP9V5E0K76sS+1BQBlYqWb1eTEO+KZ8ty2J63OVOKWI
OVidNHSL87+LWCg8r1ModydCAcMucpr8PerXoM97FXBTl2JTnR7fS8MXY8oFlpZwdHph0lCA0XON
8OWOTRTVeg9f2X95EGREYBDr7KVJLC5//tTmmB8b8O7LbM+XnBkq8qPduDljyBqwutbxncq49Jb5
1PcF4EjH5RRa98D7aFAnKTO6NNv28qFgUBz78JnznK9XgwNk/XTagPA65AB/lGFoIbdbs4HaSwdB
HpJtvc7HY816mxVG76/9hWqAWjvSfpg60rAV1rtzwC+wpV1cUzrHa3ivoU67M2BthpqAzxcdgQMw
baHTVsc9841XRYlj039A1yqjj2b3tC7TGwF/UzRAx7SQ33WeGv4M8pwGE0A9T9PV4Tw7tCI9meod
CYlZ12kcoza+tWF3TJ95GXV6OLVpunnBD2+paALg3HkZERPoaMKmoXZiv4a5JEWftHBjCOyZv0DQ
1ZiLYrxwLSmvv5X3mAOh4AwXZ/fJBuOwO79R0z+caZjrrsDKzdK5E1VKXJyRG5rnXbDYKKAjH8uS
2auf21GmUFCjPM/3BDAqUTJEzG+CmSA5LB+QXNcOHkkwRI+JDkUfnh3mL/91x+bJjKPNA+MnRvv6
pnVH7nLbrxdfCnymfXGtLptZbEtwVWWmxmFalFlWoUBbthup6AgoQy/F8jffGJRT7IPW877KpaMf
KXpF8KGrv9nzope2CXwqeE0iTJmXFPReJTafEoD4Nx1WBB28VGQ4aSgdDzEAnKTL1Ac50dPggEZm
WdK4KB7WXwIEklZVSvnkbjIFwBGyj4AYQpYZw/XfzVSB0hBgmTYuq4PU4wjOibMi6EO/NMmVgxIS
kAAAT0YTvs7JYMdyaqIDerxE9BsnLA0nyPd5S5rIofF6QIr6IDhevQx/TZ6oNUuAO6KQRCa87FCc
EXYH/3UJIKnnQiDllEmDZiwLz9ICEtdQBElojUixpFkgh1UdP2geCD9hiNRblJEf8LqnXXvEQw1h
TWuD9iBT6KNXzXhAZNU1yvLsWcstzj2luU9Am1ulF7jTBNoRhzxc8OmyLs1aqxIR4Ivu5cAaEpXr
m4fAbEL20oSFD8jhO7lnFXAzWS1qx6P26bc1EuuV6RyRIZX16txsidHZx+eBqe6bESMuuapEQTY8
cCAl53pyQLubpHHf2EgHcuDb80aGZX+NgzB0n8RolKujTSE/yFLKfyJwSVCcg71WA6/h07m0vXIM
CjzZtSh0SeWykKjzR4kHrdfRyYD4NaZBR7IXJ+g3AqVogCtAPqYyKVjorMW2tehgdfxSjR3Lm2F5
7Lirt2EYiii2P0dbl7weT4GUV0IU3Rks9SHkRLW+RG67maDwrBizEndzbFt883hUWggUs9nUL7XN
is2QtG+xZC0SUh7RePPAGzXvJFoNp6PuBImLbk9HGlBspp9HF30EcccI8G0mbsLMuTzH3IAkX6Ze
JEXuCnr0ZpwwwVl0POVCct7Bq0PrZBrWIzFaHcOsG7N/AfjwDyN8rnFqfUXZs/9prQlUHXVNjs5A
itDz78G7/ouVPJ+AckO81SnC9gUqf2dGGBDf3liPI8paszv6q8LvftpoUYwysrjsy3KB5Lr7BMim
pdQ/27L3ExiLzesBD0sJwvhc3PsFcMZey/ZrQmAwu7oJE9dGgt3YGylvv5GNikQw2yET1+CUXGT2
EksmnMiqK86BoGgybFgnodusKR9Y2shhPo4sG6mdsuyid8KF1WTSttvrpG7MrB0ZLXeldfVJINt+
W2ipeXKmyp8P4RQrYFf7zMPny9FCym1bokuAqzErTeRQ4QtkfJ6QKmbke/RnBXrbk1w0p203ySS5
o8gKsE1sbAPICWzmTh7VAUhNS9MtFlHIrCNAtQ6GW+aCZSJ7rxH2VXl1Lm2Vf0m43E9unciiSZdX
KdMTGm7b+Lw3AMzVlLZBWbOFglacWrAtPzAfd4rHOpExMHScrKM1l8LlpvtbyopvtqcHdL/AuQGz
mZAv+9I7TvpSc8YNEi+FVI4taJWI3vZPA6nY6r7orrvKVMxQooWarxLgGDslQ1KSBess0/pGP/sM
M9S0LWiP8mHARvcYNNGW3umYg8WXuCwnIXmE6dGiJAiWaK8eyJxkkbXZ/36QLxW1uo42MhuL/FRQ
t8jFsT1Jx+cT6DpLjykXarQD5ZSYIDfuixCWWsu8GYE8OYiWI6zy8N8lfTA+cngBRv4bM5m0MnDa
mq3dWxhx1hHY3GTUvXidurUn0+RxQVA/b17nlUCoTYCJiLamVFzFG3ClZfOP/mYcUpkWpYlLybgy
v8IZXK3fFKFrYbF4ZtFkudv16Ex1FqJpllAHxcatVXJZQc8qNWhglwlYTdxtjf6BqK/a0Q4DiZ3t
xrK2pyrGzIvqz9yUJIFoVd++iqYRX1px42mYGLGIuKELJRY2gM8QEbPDOAA68vpWt94N2hVxcS3c
EXGzLAqHecUUDBJqKIOrsub5r/44TVo927zB/vLeAGy+YINxAtoW3U3CQnE8KR6duJpekPIKo0Lg
UBUFr3be9Sx93Od29oFizhcpLedIvOIBMSENSHu5zEThFyHps14QbauztRG//TghrYYEEccPt+s5
TVT19DFMIO3PUaSjxd1VblxpCd3ydt3LiWlJxTsI6pkv9StMnHnHPTy11RmCeHySZVI+5Zgx6lyx
S/57nL0dl+wkVjVJGo6v8FE9uWMsd4tdS3CQ6BQiLXbRb7uXMSMt5wxHSL0QDW36cpC9GvjOQygS
cMTaYYarTcGhdjxaUtwAvBWZYKpmN4oX6W/71nGpTbO+x8J6Ne4sPl3hSguIRHhY7Nw14a9fp2+l
reRA+a55pSky+f3aJX9bIIz4CcRRaYbdlHo2CWwshH1H5SwrIA4Yqu1VfZfRmt2zo3wnAodFgFoh
E4kqqmrOk0QsP6w2rG6SHdflfDdN+jQ6PgXiX+3Uw6/5Pt61X92PDPW06iUe7OSIUtceQrnqcfNU
O/jvv/RBWEcj6Sx34acylcIxE2W5caa5VAShR7h15RBV25QnhG8Vwss9DYz4oVfHazeIHhgQRQFV
ANLvtQk0tNy5EkDMI57GzE+PjCJprtPkQuCGYv8voEwvigbkOhhriOWrH3lfnXw8EB6YCloFOQsZ
/fl0mw+MR8S6O8+SkiA+Ap6eqzTmo36Wg0lbTyRvLSHM+X1UURmcbIiCJYMgXbhcdqlQsEAFTVWH
1sGVqHO79Lhx5Bj6MEY65a9UQBJJltttpojY3tH22JX3HBrcCCcSDJ3R2yOSgxNUdk4Ke8oAd7vl
wceMJiR3mqYcS1NE9NTJ/N7aFgPzGtoJcn2/y8t4hfVPRXMfW5wXOsZnia6gYFSu7n0eM1WTLyoz
7ibOBVQVoFp2FLsE9mjukRQzgaBfvy5frtIg0oD//wXS6gontpdROpYuX7X0cO7F7bp070/zhG9C
qxGnWvTQwO/5ix1GqHT/UcpdVnuqpwV6tKqvQYLW/bnmybRCo7wp2uImG4fcZNafzoeYwpSpQAQC
bSizI6SsGpda7QpnmmehqB9xO0XIYl9nVDTVyWYlfeWyYRWWUwS+idvNqb60Kj8TXV2BTIJm7GSi
8fdGh7e0gzzvxqdb/5khSgExzCGpyjgdvFdygU/CdJOeEjLk3pVij0FrofTimUb9HLkKqWc75pbE
DEPym03RgzS7WUdO+4CulmSlaxtwDssV9KIpRVYvI5j0GleESIo9E3GpegIyx7QTiBKbdeWJfHSe
u5evUcOmWEPN85lU4ZIqgEwO9065IYTAR0M6nSSXdWdRtb7GIW9/QsG1/hLIQu7qyhL5j9Z6EHas
F2EqOx220l/rHKulL+dH0CvzYM73SdkXe5dBNbyvvlma4xWvRM99vYXDbZ28yFXkGsiK9ez/uSg4
240TdrcvZTbNATw32RupdBH9jd5If+Y9hGbboVDu/4cRs0qm/iF9WV8xot/Apq3u09c2p5cR1JFf
WE27h5u7AjrKAdQt/OaL+mzvKS6wF02HD0BB820RcJQFmopedqZB13u0jEj8dFf6o7WGP3t/GhTn
p9b+UFYLbi48tjuFh62gVKYl5KbpQo5EDf7yceWyfsOKQcKMuAZcFGwFd4a0j0RfBkSetqEdjL4Z
KAG2PPHFFcDjQqo6mZikLJsSxbuOHD8HUsAVHB7O2d3C8O7NcKqp9F6Nk4jM+Slq08/Ng/kxJ93v
lWG708pEDjmb7+1NkztVY4/B6B1qToP/P82p84XNjG+0Nn+LwLC/i36TVlF9YEeOwyHg1xk/e11L
oGoQJI4LCvXjXftOT0ONaEjVrzJmdESSCSjLpaqQDk0JTCmr/+KiBduVnhbzR9onZugKW9UBmIH1
AdM9ieQLGGq3n9Ewy3ZmuFB2YF/jT0TFXhc/DKefjnxwkNjSg1gKXXrYMEx5Fd/BxwWhpdkjiMqc
BW8dbgKz35M9trf5eS5cXf5bqT9jGmarYjcSFgarr/Pk79l2KDAtLDMj1J6kQFtf8p5iQDE/+jAm
iPcoAE/bwZVdJk1k/3XOJyS6jB560WIQFGtuOPFcFqJQcvOtYBByBSFnNlsXPqdHkyfOwIehvetz
COkliEMhQkKJ0AdbOVMA4QLz0V1dqhhTE7rVWm9tm4qxUJO5b03qBb330djowoUNG5pkjsgCr0CA
Eczd0ZdZQQEtlwGFczWii22M0xnzAplcyrMwwiI9YirrZ3fGW8VhoLOqJjvgznX4LjfGecHUDyGP
CEuscdc2dCK/ucG0B/BAydrhMmRnHAZnFkLJds1VAlblwfDu4GIyldSgSrq/lCkfJKZay8vNeBB+
yRCxGoyF+yokiSAPGF3BV6uDi6syUneuvWEU6sUu+XX32QteDa8l1QmJBjJ5AsBs8/zyToKwiu1U
qaLKfgoAiqklPXNRJAZfV1cKon68HLFTcUgFf7Ih/SX2LQRjlmeQhQb5RQa7u/tetrpQ097g+5LQ
IP9QnrSX/heVIink5fZFXY1DyOk6c2SttANHyaQd1uwYmrfHF5ZOWd7OzzEk5+8OLjB3oFLfTOP2
rY0sjQZlcp/CyosyDgtNg9C+hawZXWC41jwFAlXPi2Y93Gi0iwx0rRW5N6ljLBz4lhy4hBCBHbqV
uuPwWpaNEpOBW8roeHjkQGUbnJ09CJrckZcmxXFcP0eWPDE8RaHVKuSbez364wT7319soZ4gHJ20
lwgxY+vR+fm2yOs5A8Q7l1OTbHi/EX8CVXMsbglZEb/bWOJuSnIMO4bUfztCPKEsChOgE+jepw+r
aqvjdkIp/TbasybA9F924xprLEE9R+wtpN8DgnIpc5IKgKciSONNsqkfgE+fTFhvPFj3f0R56+VN
R6TqdxN5KAVZNxEOkg1CCdmja7u1VpzyQ3vZthVRjv9QbDdw5FDY/Yu3/gY2+owXZiaXwdvZ4LdN
brWOG9/X8rN1jIxth3wHISGL2pzfbcLr9OxPquMnt71U9Er/qljNSmpLJQydebSiCuJrYJMXei3u
P0O1/f/mXbj5WEPXGWwgJAqRfayEduZqyuMaD/nez3hW3Ax5zKxJ+NLqMqkTx5tg76HybqYE4Wpy
sP9ZJTBjeWXRMXQjmEBCmwcYiWcL9+yPjX4GVJNDblcGbgqnEj+yXtvAT276VHRC7TytcbfD3Z+j
2YC1SkTRS9lT3p4heMiuLHcT8N6uJOw5RNwpNZgJU5vayUJhWM4xadmSCxvla1QPd7Jzcn3PF+a4
5Nb4YTSbIG1JjSNpCOE8K4/U7IYkmFMwp7Nl2/42ZgMUT/mLRFkCtkSqWjg+3AmIRwwWO4j06x70
+2Q79csXDIkk6axpNm7WlEIxEdVhJFyD20XjvFqgaJDbTtUDRVC0GCpMAd2mtqIZ/JeB8L/SFTSr
KU6zYdHxKR/cYWKFS85P6WKvTfvO8ExbNqL6PE82KBUT1h3TMRQo4ZJvUiVa9OibfMwK2bm7XNKY
R3tSvdlKtbx2ekDspd+PgbQbwOX5ACeoiWv8NNvc70AGlYjw0ApP1rvd/BnzRuOVYZPjxpp0+j18
oMOlUw0X8VVXpbvKZQwEpcmTVQhDxwUZnumxkj5lGZhdKKJN4wtIysFE5KN2EqqnB4tMh8Xaqo3t
QzuEPxxHld4EG3/SXALtsJYtAijmF2hR75K1qgSvj/8MdQa2qcwEQG+EG64wjUyzRocKCLALfdbS
RUli2RFTrnqAOMuTXN9CHTB/sk2x8NXQJ9m3Y5TJWoCmGulJHdzIWU8txfR64CBEw3tvQn6YfiA1
JdoygfAd1gfwTV5pGHC0TO2O3bCu+TR8YE7UpLrnCWWXv+oLDUDDaFnjiFf3NC6K9008kM4lPJ2D
smyMhIyWsvj3Gecl95l/vzI7ddIE7yCtKSzNO0FMCm+t7zzkIBVMxZLp7WY0KY3AxeMXbP3j60AC
9BN+BjLC6M0KL9LPUgcu6v1KrOzdd0Uu8kzukik464x5RcePTLE6FDJhMplMVwAM2ITBtEYG4Ia9
iGGdjl8GYK1bSiWZbpYCA9YpJ1AFsgDw5d/ZUrJLnseJ3glTRfhlxdXF/PVUDvYSf5TAgqAh8l3r
0Ggm6kxIzFJL+GdVoUdKu2Zp2BIGdfbd2oYaem1z0Z9KRPjTznHorm/HBVwYnIRPVg2KBuUu3Ih+
vofqMeMQJ5unhX8YZcFsSkQPX0aWA6EnRDTGZHMyE6F4jToPM9jhbCNVyqVesA3l8XN7PSecrDaI
pfUjrShVlGKYISdvbo541MILJcJahrt0M/NUdfKYe5r6fGg292MTCC4kfejSM0XBDp9UkbCfkV6y
wPI8SiXeD98pugVY4GcF+FFzx3/5Ri1+B+laxBwdbrqfuCjU3bmnU3upsP9K+AKz8Woldv7p1CJ/
obXiP+KoydseUhU27d40OT2/hqS0xkRYuZ3lvUuP09TQYcthmvPhRBL0491CJ2FYfx/ogdkjZW48
DiwQS2FBijBYIRakE+z6samMhRLDenxMuTUTsbBbVxP8de5Gn9CTSR9FeL6erwOpTsM6EdzB5FLz
9RCPiPG3iaYEKwxp8PYCA0oHesjiRI+ilkpe4tESU4e3qZmyoewXEllnr1uNHZB7TLyCGfrBznbj
+fKC47uqqTZlQ34KMeqCn38YFjVHi9IM2qCD0XFOhyBgLaSGHZcecFvaKjB9qJ7ORXa6kfW1LWKT
jSx3i4qKsKnUd7PjaEdE4FklbDsFEbVpehR+M3e9nR4BBtSZ6NOHb+EmnUinxDF0V97CT1NjBhom
eWvdGlaThrAgJyWNLQEyktmcz+6dvtOLMhAX04pWjE4k1F1XhHzm1yXJ7Wmm2xbn2OwfpcE4RL5k
NTUFDBX78/uB9wjGFs+n2RRvY63DPj9tOywlXkgQso3KOPyLqszLs15JWE2nyccwDmnuA2yKvCVY
60qtXPiY83r9NlA8/0i9AHwbiGxRaMf+HcHXpSDLUC4CdeHjXorLvxPzKI2+B53CqdAKakmuXWYd
76NiJnxygCFKnRAjYLjII7F4QldQRsaFHjmg6PB3lpvP9px8u+5bPjNjLMCow0dBlzLgWtSd+aDE
qMAotNO1/OlBegH+6aAkjzKH8FCFhazlONoLrIiVsoR/9zRWT18VolSr1485+3s2EQirfKwRsLab
7pJ8asXKQy4xEVhlNJr/ybKVYVt6gKh86XxCrG9ap2rTXyZIh0HtKduF15xVc1DWNprctKNstJJB
R4UB0/Y/hzU7y+eCAhWhJ4SlaxeOl67MkDAwc/GVZ1kFCXSCRUdJRQJGbcq3yNwd+RuFglrcS194
kbfFMj8Z1eqQon3293ge18r4nEVHpnVOJ0l7LzNm5zQiERFsvmA5LSq5OjkgBkww3LvNtnVdiAjv
+mKRUhLt07gXYh6ursVfXDMM0bS3EmjWPwu8waL5TsiSP3SAsVAI/qhGQ4IDnHP0obA9iotWEiTG
4BOHji1Pj4BSKkjfC9jCcEjfF8ZSocf37fw7VMKhJtKstDsQTa1k6bbJGSP3g18rzm2TXlHWaVVB
hUDGjUJ94xXaZ5WHQsGntPRHZcAKZVoeHmJd7H6UdU0zJDGW7oxbVVqEHdAY6AwCdm1S+MVcXveH
dvnet0eMMX3r7a98nsq1g1VDvGRVXwy8eWDUA5AdKSoi1BsKS4bAqejIDvG8Q7g9hEQgLSqnlC45
gVB9bmweS7yRG8uuVCiw/+2GSAoNgxjRzXKVIV2WllTFrh9x7PzumbjkeDMo80qK9lJSeHDMJJad
JFNvn6WwhwKoLcEjvyY7idGm4MpjNQ0aineVIv5rzTiSCysMeox4ExJ8sk6+uAiSTaFjEH6LzL3P
YmS20B/zCE7U5KFA+QJtTztQPO2t5yWnHe76UDM5Sk/ydlZbma6LjPC5BVpuleZxb7RCbfgJWxcQ
0FHiwH24EOjPku4d7VSDhyBO+892ycbrbLWr28JPV+oI+Z2ETlZxSOWaVkgke1n7j/n8ZKdN2IuA
x6PqlAnbgeHU/2lXuWvcVPg/8rCTSB9W0tkr3H7k9B5JdV56JSN+xE4Ovabg+yHOyRV6FT3DwY9S
iGY4abVTA+J23xMtIpfJVwbjh4HdWvXMrdYU/09mn5StswUTRlOsuU4sbMLwzK3V1xmnXJnytodk
cF0adUhTJfJtZIYdMJwMhPHDd2PKV+cdtqSpqjtYX0HQxtDqGD1HLyOcHaH0Zvm3PhKd+rpizpYx
+sJHOuZVLSb7X4ZEdIMU9Bszhnac/MAWVb3wOtWuzbnMVMG85q4u4wVsq/6v++hNwvE/1lDibC9N
InCVfRCXZ5RsellRaIbtQ7coQwb5Nz0Jkq6PSX4Jfn1/Rerbi66J+7xhHXAVOwc7Lhmq+APWrxGA
y32KJNgJ3UXId6UC7zghmWLh2MWYXGlNiGTOR+10uLL3Dk2m9d0alOPX44iy7Aykz+P6jh8Ht8v6
SOiQ5kcLEhvQVOCu7S/iS0buBKNrDuN6A4WnMs54kBj30nT3os9HKVaMDLv+sF/CvhO47KTcacgZ
xDjNO89wuAHDhcLZFfuSySjysG4GexNIFPZnfsbBIu02oKGATilciC8VskdY+90EgKgQNKlGwWZC
whym7tPdqGEWWTEBrl4WVejYtQS6CVmStEM1LWQQ3OPbWkl4FZnD81lMJjIHKvMiv6Cm3xRg4ij9
XSb61SW8A6BMzEljcqRakpOaZlfVJNhbAHIFszo7Jhk1u2AU5jJTjsuJGYm8uSyqTGSaB+0Hfczw
ruouKkN+DN0uurAOYyk2lzB+HU8KSxtLTjcwese2r7UMf9OWzQwfRPFFhkOxoTvzRfnm+NWtLgwx
8qIbDiXaoVbCLgkn4+u/Yt4P2LpUPd6cK+0CE9fO5Xjfu8pK6A8doKcidoVQW5FC7gwMhKFrjxfy
esI0gcTZzNSLwU7dixD+moDirUlS9/Jv5KGTbwJt1kiPqMyaYfHMz6ZeNLXsYRvCLYGBp8s1NHKb
gygFhIgzMNvEioCSjnebUEqXO44vsJVEQiE24WIAFlTuDQfHpIpGGC25CKIDtCVPYRpL3KTkfZ/L
GT0qf6LTTBmnPEP9lOOW6YuBPff9GNVsxoHdnin2ro4YHmLmEvrbROhe1YZ0tBin2barAtw4GaoX
wY1lODcDU6Nnal9FEKbkVpoRB7pekxN4Y4AnBX8s7MMBQJSx5RKQ6SREra3VbBBWdog0nI3oIPCI
ZcfTVGlioivvwqfKVQLTNKFFveMlCvRvvUP+85ZFL8ZCGbKTNtqrgaF/BBVWTelqO+FjxYLEqIV1
AWRcU/y2EqbKyFwLn9k7pxjJSU4exTgSj/vt2b02c53gJ6Wg08XvriZhT2+0LIoWUh8cuE04ug/7
Wv6Lj89/mniMXogaWr5fsvLb36j6bmTw1p5v+C8jIqyjTLA1wgG1b3z+Iz/f8Pvk4L3w237Dgnde
FjpkX3JS/XH/oynJzL6UTcj9KYMU6Wh7Jk+xR9/7EJY889+86ZMZJHK3Ks9EnpeWYEWPmAY09tai
8fWdkV7NmGIwokZ9ixnpldLFVSxY1yDXJsHEMqhK8dHdB/ORelKqKk3HBicEjE6YMkbCL47LSDBL
iU6rUGVIfU33/B31VbdKtdJDHsPTrE37x+jGbw6obMcqLtI1ZcOf//IcwDkgie+JouM+EnkZDOlw
b1K2GoH34JLj5w2wvUlfsqRGzg8CwqVpyaOXYqx0BB8tNQ9+x30VQugc3J7mpzdhxugbMhqALwid
YXRAWvwaGsLlYh6c9qX/owDiyH4p4AWZzmHJ4CIh1HilFruwTZhN+ubPCT7frVpMMK7Cr6qA+xl1
Zq/5a2D8deIQJmchpRC5O1kQMZc3vAVkqpqZbh24JtrxCRufOJ/7yAYbAuBxTM4ZRpdAIIn13aBH
4rsQrcMLYRLp2et8+JeJ6DUZLohxHXToH/YVRyt566SNE4XHqQzfhFh7fax1CSkyRr3+jzb2O6ke
U6zrvoa5facURKDmMCFLb91XPYWxt6L+JRv2K0CjwPUkSQ3b7jpSt8LzbNwHvoeY3TyFI+l4Xe09
uT6QI/6OyRYCbBX+B/zy83ojxbdG/7zjchOs7kQiE/yb6Q0qb8goWpjlDMUbAwm964RBwgzDLRFJ
8rF64xqKmvpJO4J37ZKfT45NUUztLigbc/x+/EINj0e5RDhkoXRkeugqYtsonMW0HcNoRYcM3pyu
/1JPW4uB3FNULnW8I7tDvNT0xVXT+wGu6t0RbRF1PDS0SOP3cO7205+Gh1vDsrrtWnZRl8zGHaTt
u+tfiqLtDdQku/gs/POs/QYInFpBgtbjzxqHeHew5Eaf3NrYRSGE2sFD0qT0pHwHDq4o4OUpJZTQ
LIBdnv92Co/iNBrSdliIL9dcQh0RY1QOTTiGuY50wo3XXhELhmzvjjSD5mkbfAyfr06OWyjtx11I
24/qUOW8y8u6VSJcVH1Tf8fJTwRsostLrjBsjASD1PKo9pu4XQiold0vHbQ5kxNmyj0dGQg/loG+
X1qnZs8+BfH/t4J/foY7ahnbKuk+RH9vufZusbh9uGecXQ1yAhE5gdB5Q7TY23tc+WDiGLeaAv84
I5DGTQQ1aDooxt1iiqiAZN/Qt/ltHad1a5u4Gx8oF25xa/V7/Ywtc/Mi/tKG9I+ZkIdu+zjkdFwV
QpVY/t4jrzbcdKDY8qWoBIACdUMi2uecUKdjfGTZi5asVjZKdP3pmWGabCaMDeXwlGHxV+eoCycO
u+FAKTB/ON995ap1QWeI/5uWyyyUO5HNtyp/1ZJFjZAOPM3E1CcUOAVain+5iPU0+UAty0yCs0dX
8vq/SxDlxndeAchvF5sJE6z2/MTg7jQ2VRWcY6GJSvYj8hOX+WA2+AIYq0o0/MjjhZQpj44L0RtL
Jdhxyx7YNngYfH3GtKkNQUqK1jJyy0qjoPU57FACimReRZZdqZ9dqVx2L6RgaS+xeK2eyP8BSGsN
MJ+fWekTBxXzbSNRL37rFhmaWKi/HVYKBrNBAKI/9rhVO7wBHFqFuKUpQxEdwnrnZK6+B4zubOTv
ZAoHKc1sRsAef3C3W8M4f0XZefhdt7hpcsW61TNRx/hMDy8AvZ6BLjX49ZVBQsHF++FG/sS3g4av
YQv3govY+Yc/NkjgRwThwtayyBge9jhnwHQnEINONcMIwUEPJl+cSdQtlT+tEUKouC7/6M79+10q
J2sL8qYly9O3eds+eviOmVygD07xZOLi8rWNcQpeG1aipe9GKGAkaUpyO3bOCS1BXzdmwv2vZ50E
rhH9wt4Uo8a4UmTxwLKFtTAYX4cANBdJGYmmI5Mtc1jFDKsgi7kY9sbzx9Dz0SEVpEGyYXjykPEQ
l4V78DOkRVaF/ZSQQuY4PXIUq3YhKq3YWBKYm56EYG5Cf5I0HloMHazB62FNKZZb6QhuC5n/z2G2
nLSOg63XdsFWzM7qaDGJ6XqEXgSfibKuMX72Vjt8VA2FQSRd49LsUNFt+rHVENAHkwSOjC6pmpQO
Aqt6BTJ07UfOTcWnAwDVq3rYJtVmNQMjmpjgHIcltMJ9Ff3ihFQPoGq10jW8iCJzIXXTLx8EQHL8
Dn8PaBZ9oquR/Z1a39jmtzkqPvTxS3XD3/nhvxw9Hxw+4WLwB8U+HQYJN6vdXwzJiKdp94BXktBI
f2xyXu8pT2Oy3x8OqG4EmCxtpgAt63p3S7XPpBpS9RCoAK0GJYibAOALNDWTNxTmDH/wiiHKSOcR
HBfbEIk5xAiUW89U+uIHWHJdeQVC09bkRzPs+6GesadsO2WcQCmnD1TfyGcdawPeAFb+/HUVAejZ
maL9qCdsARDn86oNEX078nLerC5HZEFoACMatIGUvsuWX4Aym+4Tf/l3THFop1yu+Pb+d0qDMxej
8/wkwyNM665v1cgFNeA2qgP/zxnsXKOIO/dzadyWq7mNID0nxAZIhGmQnBzYX25QguTBFEsGtY87
W5LBNq8ZiDzk3DhMUtsGtgv7lkSv6jz7JG/aG/Aulrv1OaG1G1o8SrlC0dU4sJnkwh/2a8Hu96LJ
93MdYGz0DaY0io4i8bjGF/W5ZQ/YGRZJTcv5zk+yw8465b/wy09H6BDD1jN8G88YHYY2zvJpnVZV
vZY/m3y3tgTGTrY5rD/TGp2dy92QOYHmFrPFJ/3Y5NbDoPthXtAtChFMW0uZ7fMvKWd4YFd1udvE
NUiy1Ss2yugY1IRI2fpD47blbS9CLb13ukBEmXlIjkpkZYnL9JMGaORK7xOv5BPVmHhX5SvvM66y
2gsLck1XAn/baniaddKRtmfwCY487owXwO7dmjpHc7FOvH8dXZDKcQYocQMDvTDj20Y9JVzOCfOJ
mnu2gYYZi98MAOvR07WQ3B8Q6DXegrPrG7P60h2RUao7bRdoJlXebbrPqFdxZyLycOaiI7yj7w9o
FF5RNALjl93Y5IdpkUXhEwTTHnwH4F2bLBFqntV5XKK1tIH1dhUzSgHn1Au59kb99TbOG9vU4bIz
r9rBOkwce3BaGtsRjLqNv07o6WqHVUSybszrnGIIkO1mD39geWpWtFq50YOrawI5Y5fIXxUKpUlj
z5Ciq0ckUiGLUZb2oHm7pSA6X3mvg2q9+3zszVzWwmYf71sU1ZJDIkJs9TJS/P++KEhO4qvck8kv
qzBXNg9YtpM8GHzNI1w20H1vHs3zVbWIAHwX9DhGAMzhhoxF97NfTrBUIloJz/ceH4mGfQO9xaAO
nWpefET8zj2NNyTvzXyMdumVY4Jva/vSUYxbyiZCb+R/RElclq+ssDHt+QRYMUNro0zb1xvZUQDx
6RxmUmwPnM3CU9mAT8CtNiZDHC6FEmfsNZZXym3EkUdZKk3aXEMoYy8wL3w9YlwkH7DurxKRMNaY
eXU/e7dyTFR3zJTE+M7NxjStfZYQRW4cuu4EYeVomcCCtVW+ZHjbBX1TA60nNAcbPq68ffIcB64J
bnY8V0HOSIyXgNfbQ6TN05cFSGEp1rW1TwEL4QOsVwQuoMR3CZz/s2wnB6eMvCrNH/3Ot37ZZi/K
b5Rzv614M+4oBmlgydo1mf6xX+sT6JdQ5luLh9sO0Y5kbIJYANkNbHlJwmGWnilqiJNIY0WiW9xG
aPQSTP02OWWHtgA9d18ATK1/JRSTzvR+B9pZ4VI1CZws93Ob173xhw/qRNN/JzT9X3I+4uLlRKIY
UnPBD9chUiSYcpveN3ZNaxkNauuHYTuCiRoWddykieaCkSm8lyP2r/7dKxMxX6DcGFHbVHpxTwwv
jGkZQ9A9+mxhVA0ZMwB9wcL3u6S6R+B6RfAOCln6nyKUgIX6pTgyIE3dUuXYk2gzCx6WNcAVCi7e
24Wf1mFM2ORkei2KEZv5yrllO2tPSJD1Pbc2tdp2hySuMHA669pTiYuD7V6HCYaQrubgg3smRNxn
U60B9LZX8XCJHtum7QeGVw5ULZLnLBtJdxP++GI+IxWaLUQNd0QBwt85jtLyAv+4EfwTHyi15y7M
AgQsejF/ebD0jCvfCqvgI9kt2Fm2xrDRfD3Q4hB8AJptLnrLz0TbGC7cMMdSJZkMBWHAr0cDGXS9
/V0tbhOJL3+xAk5q2qx6dQDafl1hwhR98giirom5v6dxA/2ycQB++X+hu7OxxFxMnyXv8KZlCnuc
hStRzBCS/mE+uQj8G8Ns04247AFGBrizXPvGpqfzognslRaBi0rpTLOEYRdAuI9+TadYjPAJG+wE
Zp9cLMepjx93MUA/ovZ01WiPEjt+ELgIFmp+cXj07FDspGH5Bn0QsW6ZQe7OkMXUSWOPc+WWW8KF
v/HQs+p8y7ak9aszalCqJKjoKSpmTKBCPCz/Mi/I2ITpPdwDE2har+cWexlpi0fSwT5MpG9FOt0o
y2oUU6GjoCMD5Y9GwM5dn8wVSEs4NqIAmWwBvCEuxRJX9qwjGzud5BZSPRTsmWqw4xGkmJ4jjGbk
J82OHl2PYniUIIgT2G0vpvqHFPNIi0VYIgDWQ+Yiz3Ejoq8qh9liL2+INH41vqkHR7kyDViy7njg
6Q7P92TJ00yQgivTAbXQ3n2CsRtt1A149DKBuRn8TyvOPMY3a/PLZc2VqBqL3/f3sowNCECkppAy
fEHEBa110mexo0VJDZOp5/CjRkjUNrLqxSqwBPJaeS3z5UxD8xlCd+HBkNbriuL7zvegfjJj9CvI
tdjjcqwcge3gZq0FasUYfUSV3ljwG91Jg90xUI0TbnnB92OyakE2CYQfx/FLrVW5XaDa2hDgy2tF
itaU5HdRhH3Erv4QUAqhsDKU4xHbP8PZHdmIQJKRKzdzU9ooR+ZBeSFoY2diaH+3kPOIT6mIQUIo
EhBtT77qfy+EsdXVG7qmkKrLx1AS0ALZS0Y25bj/VO9R0v4ReAUhPNkKNE6Py8HGqmj2gNxQpKNy
GtUoMn3DDSQ1hRyUFVvXThxbTotvROLImuTo6GQFGFT97v5QhllYop7UKVO3Uc7fZE81wD4B04Pj
IXU/gT6T+TrmsnbEZeixM5a1prBnqr9drf55Py8FjvgRnvD983yXOiLajeknsQG9leytLJ3qyrBH
g0S1D4exF+NroQVw6xDtu+stlcmR8sb9u2yH23gSNpmvExblt7Qg1BZI4Zfuuk+cNCDMWsm+fof8
fjmH6qgj7jx6pZjiJRXymL0FccvOpl4T0zJekkkBEdm2SCFCrOyThzkR6hNftuf/ZR54rIHrOdEv
ogyuoNIvkGSTYx0LSVu3OK5hRtg2zbYT+USLud2HZkXafg1LUe1ExCSFsYgPBbNRiAh6MkrXcq7o
5XYwa+8FERB83sGqe9aaFrNcDKOgMIxjjia0IYcD9kZfXBhqpOEmMJ98cjXu/crWthKNbZpAKE4n
fQLJGCCUJ3j2WYJSHeBy7C9ukOUpQgLeyLtKlsGnYVRom3AC2oAL1F2RI3XkXbQmokQSray0NFin
pzlbESjeoN1UU+MekUIAPRvuXXVuBPs6LLG+2Aej+HFk4O23zzHUJiOulBXl4sT1g+s3FFCwXew+
MB0XitxvVg58CkPDhSCZc7rJgaEMhrjFw0H7kTUMN3duyior00l/PMAOylEjq3PLY+aAXXYCZ2zc
fVSBtRveqRKESx8K5B9Z3n90QCK2JJjQ/Ak6vy9zYI4qePAapuVSpQL6gLHxe51Mmk2Z8ZnKFH1/
v/X4PmZrJiRTv3hOH6nULy6qqr8GCgHm9TSICjTehxNxlStUIcLz4pUcJ7HQavj0SSra7HYr/Wrp
vS8momG5IiMIQdpR9NjSfSMNxkCd6L4AOfrXi6sqGm39a/0sZ/nr19FDdBTRLhEhaxGscU/tyBZU
74YJYCFYoK0PWQ1imCy9YxOP9jYkBKTvMMzyqUdhGwnHDOfWByF7ZH1fFqDiTzfiHoW7twjvPyv+
Hmxow41SApv+29MmAZ//c7rqMzOZtWy3/Pt09UUQOQioO7TI8mc9va394q2/hct0LAA8jYgXgXPD
R/09ViJQORgk5/c9iosCM1JfNwUnSrNXX50ADWVwD6VNwE2X5TwrerjZ8duzxNHdpuJ9+GJRshyz
Y1ok4Vpw3p/H762d75ryDmWQziHnuPYSjzT1jLXJq5bln7R7i2THgqrBZZLsq8alPq1NPHHDZ6pv
HjLbRvwcSctdQBPw7iE2CWg03rzT5GE37ArIirdb/2fLGcstYlLeIQkK3e+S7mnADHWD304i5Klf
9Va+EXPnO584IFRmJWBEbOYmgVgUQ8TEO7edXtFLhze8hs4IrFRqj/eZeTyRjTP7vQ3fOYKroNih
MsHDd5UUVFnARszeodtPHY2kqaxJ59bwVO8h6x7JFCwDE2E5xf7jEr9ierMXybpnCpI4TcQXzL5m
IA3ba5+Fm5Xd5iLqhMiQdZWXcz5/tFXX3m45JG6J3H3fqO4hM3V6eV5xae6QbWtoSgN2MQ5gQ/3r
AOer0Y6dFumXiSR/A3gpJ1kN0xDIa8jVOtnObWzWAwr/x/IYPsz0sqscmykzyAwDoSV9KN7hXNuN
vLjR0KtP7zrZym/uqqJFeJ1rf5e437wc7Kml4JCl4Ld3ecNOr8rm2nrXQaRWax8x/Tr7WgJ0XOvZ
+weeYtx/Pwvzu652KqtFM0xm+8yTPelvGdw1vEQ48zWOWam+uq5nBCJjP0VURxSfGM/2V+HBmDVx
KC2lDtTHe440CAN/s1/MAMArRBcQvYYC1py4qTB/R1ETvq+aqQCVV6P9WvWjB+F7GJj1+/zvaszj
qjK54oohnKm95IFFYaaDfIwx4otQ7OyT31qYukL1B50HafwnJ1jnuCBpd25aMWBdYgLX9CKngXJA
dFm1hw14t/h/Ib5ZRprMtXTUhg86Jimh3axXqCW9gAUd8hwdmKc+yBW72f7TL6VJm5zA05wr5moe
Qt97DIQ3GjbeY/QmPhculY9mlaeaiG/jAiAd7v1Q7cFLXSsqNfVurx/ayv2yJigbYgfMra5Cy/Fm
mp++lMjFu7BqbMvgMegAh5+Va7X8qbsZuM7dwNscdD1V7qMHk50HegU3bX7ctGiWpbZktTJkadhi
5Ucd4Pk87kuGpU6yn12Wc9C+w4tGRt4sOjdFaDMSN59X0j9uz47uNkYwhZ9peT16XOoknxldNg9z
6wH4SlzlJAfyyQTOxXan7VSM4QzIbZvwVULGtNvZcFyqKEjzHs0FBz/iUJ/EyltToqN/iG0cl08e
ejLLas5f4bhtpxcDdgf/IHwnAExnOkpv6a1DCcB6NfkssQruGBUeRy34LlmDQo3gtiqm+wfj/+3m
33OVsYwR8lC9hIGZGjSSYm59PIBPzvxi1b8hCWenHZxKt+owzA4cVATz2I18gfnRHOcOI7cnazUP
zDoYLePB8HXyx513J7UmG+OQSubWSwN5YHv32JSJ/BAAq1ygt8EmOdFu0QfXvlsDGSmLRQC8Romq
DjEDbqAwebEdu09HMLNzeObxeWzC7CGepadlnk+6XRqXWmYUk9YXgACThiYxpmkhYQelN7OciFo5
NVReW640+8RSoJj8JucJ5Ae1HONRRGdUXDQmz3U4SJWo7MkaqbweX2iIoTk3UXkW6dubxvMKiIFf
w6mb4mnGKawbmvIXv60cJSZEAlVegf6hgkUnu3QE4X1gPouY8uuaJtpiKLcNGfFLIGipcXsTbIuJ
n4NoXVhsrQmN0j4j7Napo2Az7eJNV0O8Et0YQIkSbkRbEtY2Y0u2/ia6swyQlx8HawbhwWzY3Pew
I3+qOpuTlnveeDhiXtEIu8Cme6J5kngIVPfV9zXGiUQI64neVToOKp6UwYbIDoSn/9DRQNJSVfPX
Uk/J0ummrbtGcKg8Xcv+O4RAiMWC8WqMEg8g0oBsY9ZshgIAXERza20bU0xPKzlGJKr6iWxpFY0r
5yXjh003vlFyjpb1KILk7BVi3Umd4yh2yJ9Cq96JyNFafuwKZk4VgdpCZYhhOdZi21PYuyNl49gR
fDsTHqQmuHlbSKLQbxkXJBwa7DQfqaSp1cJCOjB76ioGnheA+ysCB9oZDtFkpl3NpP7reUusQ0jQ
lm/Mu0YtqdCrMeLz4dhwbMtd3UTrO3IQERNLxEJvUjwQoaZmg+FV9QRKmYUGTL0kgXuHcC7QEEUD
dHKeX8rTykYbkAEWwuvxeNB+aahxkCyOcVGf2bdKN4LDrG9jsfKD+tJ6sQMYTjhOfVT8KG6H1J5W
GVId8wEVtyEHBW0zxf6VNhmev30UYEaqxB7cZKGSDjLnCXdlcLFzNYCFhvBz1BPoyyB40vsCpm1A
p+HfNoh0AguX+iJAQbyLcTadBvMrQnSBRbs2KJ6QD70EIakRldsL22X/WQ36PAhIUuTAuZ3JbtoX
6Itrkr7bD0s1Th5evL3nH+QrCkfX1BlG069U37osX161AVdcqIhpfIVKw1ssyEFXtVz/17Jw+4QT
v4Wk+hJNVojpnmt0Z+ftlbL1smyiEa4EnLeMX+7ycDdO+Va0MwBleyRjwZWe6wAdObDyIc/I+Pnn
H7tCH2Psji7rumhvsAbeLxM2XGC51OZ1yVJlH15kNxyUWiGOyeV6zUcNO+CeyxGh5y/DEJCjLb7+
oeoop3EEAUKLeMqvOIfOWx86q13CdJDIqTfShVWSMIj/gugifVX4VcC9wDKbPrxA/8+uY4qbansn
IpaBmNIc7iEFG8hjQEOYIUJsQ8+B9VbMUW7NtUZOi26S6nLjDXRmyJ3PjJLFb6TSGlETJO+ZTBsy
6ZYQAuBmiW0gnTt7U1ltAeadbWam/M0Aa98TsoBaXz4HMsEJtk+hSGQgQqctMTy3Z4WI7kWzhkkp
RhuIG7VWvcsQzKMdIm5WwFoyBCjpAYS7oWF9EijB7eOrUQw8lwJHOXKT+2eGXQ0/i+ZNlpq0Eh4Z
04VIIokizp7/ToYvGCNQg7R8ZGDG4q+zhTKt4T8DFRKcUHc2fu1K5/oBtb3iMuZt4F87jNLX8d02
Ge/kdfR1bTLwy7SDVIBhpjydPcRt6b7ncW2gTMiQ08r2JpJSnscoXIL9La895v0dU2nBTlAifgpB
y5iaMSUONl4d9+cGFKHrp/+qJdr5A1o1XxyoRTqlhPqJ8n9P6ewlk0/kJGCHlaiYYZN6IsL9kPaU
l874LrbvUWqJ8Pen4wmB5y8yBN2yxvHiT6fVNEW3zuMXY7QEIrhV2bNNVJSicekRhhEVrpjGPq8Q
9vK53yHxuRwz5tBnSmhVOsk5OUi9ipy85UXGdGdEsG7CIYjTTZRjKl44Oky/d2hrvsxSTGM/RDfN
k6RjRS6oJy1bXCsfDc0yhuiGwZkP8pz2Yq8k0d13p084au3GPcF+txCsXFGYATma/Ci5nkkng0ZX
ACrKW1JhKXVAwwnw94RKzaaT3X/UiyLpQZ+i+srzisUpTLea91XQuUtCF9sDMBFA0RWNnzF/saCV
qqXkKVaWgH+m/gvODlykQsYG6+C19o+kCPjLnXhGtAt8DzvGAkRv8eW/UnIij/WBM+uuZRQIk9mU
huKqB0KRZcFQDPx1dNn6IfOovse/oJLMsxu/YtJXQM1culThs+AaY740xIzol8GcCEKkg/Z1cEPf
kdarDfAhQMk0UTA8yhsCerlIR0KabMP+RchaIyWYe3ybv7TyYkwCRTGZHEtK7RrZL8tLkndyfDa4
C/lQZhWbOd3q4iE8hZqWEEq8HZiWT9rC7z63mSRD8gPE9RQ3dd/BsZz9yNqwKwb4UVBgmc+4E1/C
F7OMPE2JX6XGEoRrxStFjfsi5laA+w9+++6AKq5+Wl+BgbPkAClF5powvQ3KaUNt7GzGv8Up/pT1
5rzy+C32Xs19xCs8JBmcBYorrvyww2+kN5YowvCyvgJpqrbnyOHlOCCX+DM7CsNWIENsEf9vF56J
Jwxu4O+Y1bcKoatW9SV6xPBgg07k5ruYus0dxBbDC47tVDAWu4qS4oCRvSiXxvEZmW7tM/wxi4iY
20PVHLjUVdtr78BkDpBeIr3sEKwb+qF5RiejFhUoAz8Cw57tXiSeebLcXapBHJZDdYUL1oTy1yVg
NQJLuBYYIqbhkRfB4BYqAo1aaL/xoOQteFyI4iCe8OI8ZN0wF2icWKwBIZ93zlk3VOdYaD5J4WJf
cJVMAiLIws1N+5cFzEXpyKoAKIawQ+suy9ylBPbwb1bIGsl1W0x/afsfSo0b0WX88NM//Iw6fRAG
MhYJxOmwi/7uSQWfaiRX90F0azSLErlYpxtik8olJlLPaTwFRnpR4Ify8k+PGwiz/q0HWq28Nj6d
hg6I36Kjtz7o9BESYip+3wpXtMknRoUWNdpF1SKKZG0RcySNFOLahc3Zhg/mBz/AJ6U32kfidl9y
BKE3Nl+HrPUCRx/oR/695oQF+jTPXo0LA3su/Urn7V1LHKWn6YEaenqH51ivMyIl+PISBbhNbbLk
yyr4FK7z7QeyJahMqz4I0yI6KCcBEE0U1uUcDlvJsWJL6v3V5Y4JIl0QvUPCp0+TDlOQrqZ5m6aW
YQAynlWlTYHrpGP8OsmvWlo0H4ADGY76JOA46h+triQGdQgoZcefScL9b+w4FcB6Q7h7yqEsDiYa
lrqHxdyOGRq5WZJNcCE7l8eeOLceEKwLwdDs9jWGIZZuDwW30It5FmSMTv0NpzpcY918c6uWdgoo
QzONzYrckacmpdFbMkZoABK849AAh4tJkXBFyrXjX0DzSmyelfc8mA409RFNXR9IeKeqSpzMzLAK
a1CQGAMav3b7EoSZqF5EHCi5OaQfkgg2kZ/ju/+DF3/GnbPLHnJ1sTqs3kBa9JEmt+HgoB5pgLV7
+rVECp1Jr087ccWkJ8wJiJYkD7oIkY3FkB4LQ79Hpp5qCzDCfHiqgdQoiSbZ6JzcfEpDuiahD1f3
OWfybGsZmveJTNq+maEwmLO/wspcPmLN9Vq2nRUCYuOpNWbn3coI48DnIQQyvtrd4FdDQGjzZieo
8MvAX1cGSTCvvmbrDUO2cTFq0UtH9dle1fVmRD4a8lCvASlBIbi27sGjb3W7Krq9eDsLHcJRT38C
0eksWcwD5Vn562bjdSs4gycIFk57vmqsto+tubq/+TKzADatxwhrM9VZ3mM9qvutd1kp76LfFw8O
/GYjStZrRRUzn1XJovx4fYdSWK8E+6TGEQrHQozq/+UiH2ZZEpcWJ91UB4ejO2sZmeav4sAWd+oK
zNLEDEzgpf8WdSdmx5zhPhdHmzzYAIBdDI0iItEVv6wsDCGg7jEFsKaSVjBkrGV9TiopwqfXZunN
oTWStcKof4dPTY5KUxhePsfxX6ixqu/kDzsu6kwEMAMyn8PpJ5uebblnwmGPDUl6/KkdZFdp9Ku1
xtGke92uWw6XpFO85iK7sseRmuMA5yowhjDNaVI1wi2RaT/Sq1HYRHRoCXiFP7C1yGrisqbZj3se
8Hxp/EtLF/QaycH4Jq3I4dAfQ1N3C/khbBJankl/0B8MdW3xr6Rpben4qVO1mo6USBPoicyF6AhK
yHYppNzzw0Mf76rIr0zXBGOeYPOMtr5OcG8mt/x4LyDcP7Y2Z4GUBAUmd1OzKJXwL010eobyO5O/
0nGfrYsG/a/OO/UkAAf1DG15nG4xQWCadUcYuz/Ev2b6cKZwHMrmmMGRH8OVKlN6vtqVN/S9tX7R
KQT1mw8ofh3rVBovTpa9e7F9Kf+Da/KCD5kfi74r+zNQKQWoOu76bxndb17LqahMxBaOHYNRSPi/
VitcGPSMW3le+J2IzSimTiQMQTiAnlowNvG97K1gVYXe/CZrDxYcwpsnK/LeWcSQLFkQ80Wz0caL
2EzLHWtRqF8rhXTEEVoQNvMo3UDsLDTVMDAUhaW7XeC5BRo2M/ybYQBEIe+PpLcL5ZMIsCUtGjIl
wMgbYYqPtiiadlmlVZ22OcR4fOotQFLM35K2BqAEdAcBNNLRWpa0XG6msSv1JEwPGMXKLgNclxt8
eN38NzoKlBwISK73h4czBMtA6FJOlfbdhM9WVNAC+MI/BCj6ozxtZdnPketKjoV3TaYUec+CUhfb
UmVZ3+2O86cMMSGpg0iDzvRLnNPDrqd+HyJSgMdiyDwHiQtu9ZYjmYWKBdZtX4Nd35gUgAaaMum6
DT9MeFc1mZN+Vxq9+LkUIRH0Nyv1mmTMpcwJ+oP9rpYiM8jgDlz3sKaIsWQoyjSeo/oEHqbpDE2P
x6ypPDT3zgDyU7ViPDE24niHkcWaN3Yg5cTDuOz3Dl/2Gm15PUFIkbLECbK3HPO4Wa824WN2ykRC
XFCX7GNnK0hD/J+Py+MRPmBCJ2mCv+7GlCKgrZwEyAJ6ALrZvGTbCkbOLk29NEZN6i+/fYot1shZ
AkCNUJSQQc9QIOmzsZZ5Pifsr9/G8YqUJgGVcEVxSk5ooMo0W0qadSyW8mpwoj9FmkPdWaKfQs7a
sj1FJg8NrsYj6l0Bq8xHs5L3I9vQFUZRQ9Bi4PQlNUPc7mGjbIQaP5G8mru3YgRvxXceSBMZsE8X
LG6ufMwCWBRcEmyWCbJet8MBz3Pz3PwAxOu1PyOK6jg1Qvq+qCsAf+SPIOSIWuToTteRfQulURil
Ov1X7UUSiQtVyJSYilPxoLxPnEeC+gJuvOibUc4bjyIGImYJJsOveCBzOGyIZm3tnLXNESO+jcoZ
409vjuQtoewWraSbaJG4KzDKQL3sf446G1xA6rbhAa7ghW7+nw7ixMN1BtKeUVvt1rgJgqIC1eYO
xUK77PRrPoiav4leSQNfaHANHpmtowBiFNk5v1P3O+iNiNhLE7yIrJcNQTHrtrSPc03M0oakzpPW
szShkJCHOP5aEP9p30JJWlFEJ8pkmPNPiiMU+pNWRQapGPpG5bjh1t4q0V2BoaZYtcAwP6ZO7GFb
IH/pwN3PT7HtEVj0LLD1FhTd0Qv8XQPOaiG8Mf9eoa+4OrCqKs99F1jAcKqpKU8t4+MbTH8KkNiY
9HFybJOmhdYYU18QJADUJwpPpZV/uPaTPguiXVgx8rVqLS61lDl9zwXsWS6ZBxOzB2BXyPSFAHtL
/+Zd8D2XfaaJf1rV9VH2toIO4jbSwu7S+K0yvU9B7cQ9I0FQWc9/2oeu5MPxvq8cwQgsIcV63FRR
oLPSb+zTynm72LXuqpBB5Uz1F/B9iYRlggjaMoOvnOQWScAGdnDlGkeYR1ymtLfqO34rCJ1/WJNR
VebFz0xFpo3fEv9ILEx0mLL/E9oneRtC502/5cOzmkrOt0+e+et8R/xv9zjou6F78g23TXOd+/+z
80bxPhRwS5VaLyyWhtSDBha5EkuiUAcACvQG2BcgFiFNJ+rvMt3714u1ltg63Lq2x3HJnmnB70V4
O2KTiUnz9pw9vM6MP3rvH9P0VJ2bgfdWvLQaY6tLjyddB07jl7O4Bo3gN7JAJN6VUKXrpvT9YSUS
Kq55xyxcR+NY2sGR9NXa+RWjwmsFH0J5iq7/fs24KwaPiHufXYBIKoOKfI++MA6oPuci5Q8FhNd+
g+fqu6na1J0R2LUIhI2zcjlg3wkOhqUtLwRIyWsF73E1AsQwbDGgBifs3lw0bAUSGQA7aiRy4Hyo
y1EsnP+eLiMQcrReYzjMcZktqZSyAH4zX/faOXLCV9g7rDHc786BDNBG3ETuUCn3q7dR2nrxPH7p
Kyjq6vJEF+nrOBMA5/T1gSdWwEu9XXPm9vZbShgCMRR4llmjzrKPDxrOANciJcKyWqe+81ci/rjb
mlKgLubY9WD7vmeP/wzdj0IqlvJUMkbhq1TyqeMN/B0lUJcY7vIMoPLffJq5ZalcDn6topHwvhfc
5JdbEaj3+AlurLsJlLnkEGYHJHTiD2OWOOOfjOVy7oOUmQtcAF+JEJHYVhzND0VdJqCVqL4Nr8kj
ceAx40L5l46nuv77rg1qFZ6YqMUvEfzFnAxxMhsQz4hykBkDX9KNoZqCWguVKPG5+6xwIdrXr2nj
l0EmRZqZrPjRrqzPJShSuR05Zo4pu+ETUY6rEPp5FDYTXJKP2di9AL5/HLj9qGjKdr8pw7XfcKkk
tQbzFkfcLAC4xpAHojP4Q5zgkIEGp5he2Zw1W3i6H3aMWjxYyi0GQffPFL9X9wLSdvbaZ9L5w9Lm
swehdarIsCw9k9ZMSgIDzwUMRN/0o5Yj0QuaQrkORZbmJA4YllhrYTjLCYn7EwGnvRkezHso1Qx+
VuoNThbwbxIsQKfkLl8UkYAYe70bkSCfrb8b2/YNJK00gsaco6wR1IQcuNK+whFXSaEkapH/o/OC
UDb2fh+n4T3hEMGzN0fCSIIOOWME9irEe5fSxzOMFI1n0tNTImSpppLeytOfV4ZxaOJaV/FiYYeu
0Mung/AYnm857azdYGBiWGRbK6hy38kGgfhRomCmJ7alxJRzx647l6jZhOBvj1R+ClwV/HVUkZB4
xP2+Gu2VLRb2Z+wG5Bbmm2XO+TllTHGZV0zoLgsVOq8b1Syiwk+B7BeO8xWbiXGizJ/1+CFdHBic
Jq4nEw8vOhvp4vmm0mLjZtknVuLz6PtYfKPzXQjFM2cmqKf1th2FKxfvc65rX6kQTfss7vFwxufw
qQG9gJsTqoPGRPuN+w0WZ9tpqvddXSacm51G4mhpcJuzO95Jp4eBOCDtl10/AGNDp2ULVD7CxL1K
lAQDhKHP+WjTYq9IOtQTcXSg4KanZCOL6UroYekdqqQV+GPw6+7MQDZLHHWv8vjhuk6r3f/4SMbD
80wHTkTLRrkLgFINT5ITDoxybErYrTSfmaZ6HITygfItHykPWB494QMKvLQ362ya2Yn8hW3vP/q6
5r5+4y40qEBefx6OkA9UyQOWDtnpkx8ScjBs0gEQgmEpDBcQkUtVQ3K1u/1Ok/yq02qGuVDbV+Cw
DNQnkXeLig3jpChbBMkkifcy0kRhvXy244DUKIfCAtPs39giA0UkwurgmNmehTwqbCGWjmgunTyi
b16/JJuPRRo/6NSYqEO+i9wwgVF04vi5rXAm0CaENGEJKi3T8Q52fhvhcn627r/VWD2vtElAKMfx
7/ZDuGWPnKzzJ/c2HwuPxUOQTubvnfz9Bd2zKQsE0uC280KnBQunlbcPtVJcCIz+J822iMIFM/80
Akb5wsVlXHCa0aJVryrt3Itc12jwd4G9l/CguHM2oTj3B6Mn3egZNXD20lmOmKXYx8Rb0ZKB4FWw
XCU0v43PgMWzIfP8mc8wg8dSHv/PbSdF4dRoZzg/92/roI3mE7/xAjBVTUEai6Gwya0dXimPUfCb
CbuTOzvased7UYnUUpVMNCnzn7SRotO7X2LiBZF9a1SS1D9BjIqnn9w5zfiBteezT78+BzQ65Mt4
OE05PSzKQq2ZBdEoEczH7JY3yf8HCdiHirKhgKBoTOV367D9qZ8UNebT9lC76Ywi/mecq50azktu
aX5c1Rf7Gvx5Hr1gpwvsxTkkOAIrdhv0SyAu+jYosv78yU6luUMO0jaFIrUtf4R0P1s/r56N9zsZ
SK6jro4itxYG+o7uMc6ixuyeX978TZrTYO2HRObN8wSnttkqmLVGbZ7th5d76NBWlXxXskOFdykR
cAVsdneVW88YArUGFuLB82MY8DrLdCN8ooBZQNbLWR0cZibJWX83sPC36pjtGicTBui97A16vNiZ
dszCq5orh58T/4Xf2Ms5oihYIahuH5IkgBJLaPdbCUaAih5vfGzdPv2g5R/KtMiW1s4h3ORh3CH5
GWpDznU5trS2+YzWvGiQRy1v6nQPUNtfxMfVn/UpdJxlDrB0zm8jZsun4KLCDMO5f9FCxOOednWB
DkcuqF3yNUpwStRFJaxCOC37DQwiQiTnVYlE5JLAf2bG9Bio/5qaM7XrbADU5UnjbvFTAplX0Ea1
Eas513MeoWxvZEv4CciTwV9zR3wkWTx4So2EsYURD7Nn04ebAgdV7Jx0XdpLkCRRhl/ZXYXafFqP
3cxHfthFiWR/Iwljv0J0odN8d9zaZ5jYEn03Dc+DpPdB+Lx6MarJNuU+1g0so+Ivc/CDJiTe6eBk
yvzC0J6GNYluKS+P2bDawADEmzdDhWy/4qRFAMfo8RXCS/+UsdUv8Nh/Xu99YPWav7x0j+VlCHk0
4oicqaLsk6QC5kU54v1t7PB1IGVtixGrOQejuF2T3uqez2b6qcthjlFYqyZD61V6OaU9LMhoINpD
9S+fzi3+FAjFlfnG4yv9h2hAqg9+TyxUrgf+9t46TsyhO0qgiulqkHfllSu1EU8Cxu97fCNFfLK+
5iGgv8OqRSfMjktdxBYhxSqhgvkLe83ug1QLJvixlUBnLABKUVD0GePYAC/T99VKweFccCUsu30W
i229wQIHIVF4IXlWKMd4qJHJuko2dWb/Zwr9pvhhQNnmXAldfohcf9qKYuhNPdqC1fFLCXfza9sp
Snh9rSW+xNOMWKcgG9M5BeFZ9XqomtQ+AbwyindpW9fy3MA8NnYPuWus7n5G9eXkb6yzvff9vRkZ
7jzK283OKW/C6IyIWiQObPYhS0DedTC5PbtU57wPBXK96DrHXGIEjF3MSyDawnId7BUeIpqJESR/
5xMA3oBv1qhl6DbWxS2b5BvLuhLAneGU2DhTuoUdJKqlIm2GOoqPFM2BdGQl7GKRgJHt4ULBs8P7
LfIMAgHiosVPD1KO9PRd5FUobbqW6qhsv+n3UBqwV0nD7Ybbln39FCU01DozGwvCWgvGrp6MK717
WK3gLsXcpMk7ybM/EdDT7AR3mAaBAwg1YSEDxDq9dTP/K/hPgzZLW866ZKdTIlLZa/1Al9bAzX7L
PbRx1HGn2oYIzIoeHQCzl676oUT0grs58J4Ve9Ry4pWlhlSTJRfNaqyscjeIv1+yp7ylRZi7xFbY
p/Ua2OVAdDcQhMp5tM8nVbGiNkCiRmwg+7ub0KH4IFUbW8p796/neuvIQNgzX477U9F1dzE1HQrr
DZxeqYR3ME0K7CKZ0FR4PAFvwqshW7lZD3IELl6JLOmFY1qnDwzLPI4ZEq9ULYrCZErhjgSQWDHL
qmo1dWdgDZG5Ib26oyw27Uw5KbHGJOst6B1nxMaFfMpRaESKgW1hpMXoM0mjGKEoMliDnxpAjDFh
SD/cCZ2nJlwDBSYf1cV/oqKZV4ek6L13e3kp+SIf/fe4uGTUDPgpyuOHTS3UBAInjKlsMGA2jFt3
k8eWk6NmX8zLTv0oa9l01AWoHlgI9uR7Wr9NDluH1aZ19pXFUnHxr1sOgiJrtebWKk3e+83PCP/J
m/OgSnG+ikr6gvnR3rSAefgLVLT7FFu8CLnigQS73F93z4hwUQxTmDXgjBD+rOsWrwVW//e6zXK9
djzhFHJ3MEJ3jlSg0BK8CBqDileSt/MdCpsdQqGDRpIMnxlzELzBmO8yo3r7A+oK/whVpi2RFXTm
xXdNFnSagogJzWqh6LwsORhsQjRx9Do5KhhXhDNcw6SUnNlt+G2ODHFXZoRpwzvPWXUp6TP84FUq
OQPiqt3W/mKcvvca6DKbjvUX7we0fRobiQO9cmARJAhl6FoKGHRPrslVxqLNygCc7Qbo//Q/RKBH
hO0deaql/7znELAIX1KKhpN7HzweQnz3Hlt2dhguM1ekK1+p6BBtfsCk6k9cJl539YNDZ4hLhRrH
+UezoB4fZY4aw5SmiGpR2wElkcM9z6PRLA7KArST51bmKHgLau4arGx/T1I7S7A9InzsnayECtyP
svnOImx5acD87iZnEXCIKDufOrQhBIL3jwPbLiAXnOmIHXNHybEvcXfbGI45EKSCMo0mvvdGLu6g
usr+Ca2TSgubruc6HeP3UFPf3IORq1ZJO6yQ40fh57hUTWPersPGkk6xIzjLUWqHPVgkB2ItTV9c
vgim0SF9tz3WHTx2CKJ/+pcjZfa5/tPllj75uEfMvhKJNk8x6WBtXWwDK1ZUlQ1S6A8Ju1skGUB9
2xfRAzBY1XNPzozULMKEV31wjfsJXMnPEZU3e9QApFhxMuW41U2f5kN4vu8KI5+KAY6lk9gSBRox
Xr6HNw1B4mgd+3BYdihkx4uSmxy2Fn9sNvJxxhk9WWSgFdK3BiJYrLsZyc/7g3Pj1PbO+b+zj/mz
TcLiWvqmxtibwY3Gbs0+iT9ah3ty+Z1qV45lZg4NeGO3WhuzxP6cgklqRsfoGOstLzBPmnRhRsUf
uBmMC1jFuIbeeBrSfeMCbxWvynRFPFxQzv/1UtsyE2E3CIY325F40PneCTWy07w4Kss/G8xmQrwc
CG/M/HQaHno1LY3MUl9zgvztK3/M30VDLn3cTWjYu7UXVuabY8SusL/G8PJQDA8I6AZO6RRkHMTn
JeQvseythbjE8JNx8gAHiQVHbRsuxnlH4J8F3w0SG++iyevM782iyh0zVpYj5zkUvlnE04DDSWak
bH3UcOM4Q7w7/zC8JG5OsnuwF1jgE60up1A8IapyJTDF1I2/nf+G8IRNvbNXSAM+Vg2JFwb9h9D0
g5vFd0EX+fm6jRXamYftcm/zQ7EygeFtZi129yfjJPZnROvgvmgY3QAnvbnhTK0WHDZMMnLaVGpm
2H06SSoDwIukE+VChAMAwkWWI/ssWEPUid1Qaoldpl+ihV6EKzxeV4HLSC2T8nCXXd6Dz8+YGC7b
ATzHB4ceI4mUcix5rQC+6AAZDumjVYiko3IncKcxoPeGKC7CfsiwcPlvrD/09/QBcKFsQa/MoSfn
1+n+qUgHL8eDmYnjtOhvy8VEH0VcbWoCJCxnW8afsZ4RtZwPu94aFXF9yw1/QNOSlj1c1rA2EuSw
WdChwTt7kZkKOKrun/WHEYt0a38IeUgIIXKAoqoOJWewGE9RPIkCCHyi1N31tVo53YKU1JeQTANW
qbrXWiabqwDiL8TTDQtUzXXShYZ1oSHlQxSgd1B2RKrRd9Yxpjm2rFxRBW0bgo4xg5H34ZrBPccD
NbO47K+eQ0cePpuvKIO3PLiYTiTMQRStYP63h3j5yDQhPvsWJ+o7ExO2+8qESdPKcdm8JSzgSNkm
sMT/Gygnn360P/FVrN2AfHE1r/xmY6IVldJbOSQnF9A67UONBGqrbIRJOfac/5FhYVwho11qMQhC
DTF4s5DYCi5PBAKGVK+p09JDaLQjwbUQJlAUtjE/0OYEPQLTdZyt0OdItm4ZkRGVkfXqpFWW0JEU
y0Gcr/o09CX3SRFIMY91r9n69XN0GLTG0vJHEzy3lPWx4IEPly83N+WboYdgtk8jN/nprbEsqutM
/fKIjUW2WUR6w0QLRjB6jr2hj7ZpsJITLYgV78VHl5yTMRTqh7LwguS+VFOS8boxMy6cu4uXE6FM
hjS8z7crXy03IFZKVNFJdd4pnyQtXI7XZ8JU2rZd3Zm2nY6+qJWlyI/Ephyb8zQPM1FfdCWU0Ucm
JHjl20b4wLh3XGJiEUzDKh+aS7y/2gA/pTeh4OB6DtgbT3w3A2M15ajLhRn9Q/dqDEx1WhTA3Nfi
4Y/m6hF5gArOHYQInFmXpY/dIH77uV8W8UvAWfj7lv1QhCMQCLmHgbZg4keGWUrnaVt44BPZv0vA
FhL/y0vUe4DWCt1gHZJbb7tkFUznMZ/BtoDG6+lKVW5BNIQ533ZlMUvVZ6khlu0QTN9nzSkrGqqE
I2+VPvTpZLHs8t5Qp1DkVchG4EJYnMG27t9j3Kva3OLLX2rSzy6siKUL3abTwIWTYBBkboInTjXY
oSh+v2A+sG4xOeBRxLsP9RlWBvzkvvakZwjzUB95oFzVGN28y7GylC25bFIqdZJhKtrqpOL1apiL
T267iuMHM1OfEaGALbk0+KFE2Ynq9LmLwFwdejTWHR4iRMWSwp/gfV0n+SAWFZMORisYELP28ziR
2Eim+DZf1NWPQKQMJ02/GyCZJI4huLzdNKEh9oC7YmDAcmhGmso64oLuxfdub6zKCOOeiQEEW5eS
TYkXGDrG9CESnaBEZZ9R7Cx+/EkOHUEBfpRpCx0gNSB4oj+Gw8kZ9EoJVf5qHfZNjvFP3q5msbcs
WTr/KyYZdK1nfGspngVqgkxHc9fIxRixk96ja6wCIfLccvDHR+apFt4a3+DHsn7DRseFydEA7cGQ
dvZ7AoCqF8zaTc7913fgjKkclYQTh3/X4EkFcOGoAyuVbksLy2cK8okHL/c7Q0B4y8sy+o8ypacQ
rtYBEXN66c2SuHvgrDuYXBlmTzcwU2vqGJfzjCb17eFtuOqstGhj5lwVsKU0ZpGBN3woBWtuMpy6
oabHdKuPcO3Zyk3LDPWDHyd38JFjXUWsEyAlt5Tj8yPBAhY2MEAdrf4c4VAxmd+sI261HSJuXqDu
USAWQe1D7tqZBk/LZedCP5HIreQ2BfBUKaXRkLfKP0+ud0t5w0f19aXj68LKKH4wbAN4H9XqnkcX
F+vfdpWexPNqTbcNXUtiphIoLcsiIDONedL3tTswzK+iM2ALh3aWsHnfui+vnLX+jqsasp9eT/+A
1XUYYejdMTpCOffDWTacMmMMXbYl95kyZ5hh0SNTg6p5MzzDXinVynLVEuqilX0mdy+O1BOoBB4G
cN4l7C5uFnbyOGh+eqPp+q66x/vup+5S7pjxjlT2vCDDt9r5pTPm26LbfdDat27JO5guE2hDQGSR
+qjx2H8Unzf/ghp4T7aGf5EcmqZgeKR+XhS9r7bUtOL/TScwEnBi3FxVo4iRSN5JkWa49wFzzC4x
XvNBbAd4g/XGuivdNzLf31vc0JU0cJok+t07yXjFi544CHuiO0Xvq48CGzu3VZhggcegiH7PRfSf
lWTZMkxXU9HTdwAa1RaYF7xC/IQNig+uxXdoZrfQhgaTg+OBk/617JaBCVTqYFkAM1PHCE2lKqjx
Zr+i6GV1K8BTN+q1HFHCo22W5z6mKCLilyqtQp9LO/SlSLcBQ23q/Zi0O0onzRFvNVjnTA98Z18J
NlSHbZkPTHbIDnsltYNZaRynLOiaEP7QzsXg4feyUVW/6pbIQsZWrblweF4NEkEXS8q6jGR2jAN7
oRrxA6XChit4NNKabJw/xVgG+ECgqs8iKcWyrAFVneha8eoIcnq+/8ZHejSvrnz1L/PouT9KQjHL
fZ/8AqMg86kxsAB2lVCYeRf72zzZk2SXtFD67iIFa2wLqUkgeGvu9a+o8LPDWq6vs7x+ALkOabS0
Hw4352M0n5CIZJXqlGPkdFu4lGeJatnO31ptmJMh2Zy0lVztT3q0iXFEViegzapEYqyLhFFulF8m
BU6dWuTKRBCumbq4hOPitfe5fv0YO2NmopCJHu50IS3wIS8nitha/RNkfU8Q5/NLuAGMkbPvPnIf
HSTIkSWoeG/GQHH/Ll0EfLHOLjCqd0pVygemK2JYqpqDFpoYAV9DJC0/nvzptrFm/blLW6JJWoQn
8yGcBQBxlxFNe5nKvqQpRLqvvdjBe87VYlitm1Su6vSIIPbeFI0tcSMyLIl26TS3cR9X2BaEgFfo
/48bfgPO80P5vsPnRtZuZoChmUz3kRAcUgB/C5c3dUHq0wRZh3UJLnXPsAiO5H9sAKp+XiXr7W/s
LUnPGK2ySWli0axA15skNb+Y/Z3x3ofWTLa/Nk5HYXJzXTO4xPx+3HolPxWgEjAqCLtpCYgtsZqm
NLU1eSnMELcGyA7wBde5JTPJrD97qC0x2XE14R05gnfNrgoDmGnucU5pH6PNWWBDMMHcJ65DtA4t
dF2Yf+l8/36LY1mO1eVeEDT84UqwvtlXC52sbJ+7+4N59/8DcfAUK5snY/cCa75wry9v3WOiar+U
OJGsn2YTxxh0zaIoV2Tz/KlUOoe95hXVyPqooU6v+EW3ou0wQhpepXyx40jTYbk06CwU7XuTrM6t
/GCuV2Wmw6c8oxf8fjkYy1UpOLki/EyyjDLteuD0hgfHw9zn1jav1sZxXUa1M4o5Z3S8mqg6am4T
Bb5saGNNecKLkyEiojVvVA9QnBR1uiEZCNRxQO1t1fmTRRik6gGz2OKccY17JYCdXH+C79IRYtPd
LCFLbz8f161z0vRXyQQQFkNJyCZJr2lYR6iw/XA+pD2kJ/4ReRpywz85V81UmwUZd/3bD0eFz9If
+ABVoVSKY0hRjUoFKXFqdM2ClCfO0Llv5hkOHb6GZOUSCosvNP+cVX0EYykrJaCHhDhUrY31SuJ1
YAmmRQyP1jB1kJvsCU1eTVYupjdk7y/CGURdcZytD7MuvsjIhuYfrt510LTyu7Y5lwr0jvXB2TVw
RczFcS5uM6MxDPaEnBhISCYVLWaZqtORnXpnnA7NlUiK4KkRRF1HItIVvEWHW7pLBGd4WSoBzeLh
e8pt4j57Fb4VlZ380Vwhx7tvGwKA1BPy6w6wfGj7/LMCIuU/HDF5UTdo+LT0c6e1S3d9tY1zliMF
svB2etXmNe0f+90qr5dGVgD0bE8pvQiPIufvB9r9hdklnVPd0NZm0KmkaDPM24c75HKg9b6r+Oh3
1Agia3Mem8IjHscGwTAg+NipcsbO5zYG0s7QoY0WCEhYxJEZDj9r5Ncw7PPXH9jC+zJAMB+K2tMw
cSKhxXeddCrZIBpe2XPkUJRAPqU9BXkiHJSRk2NyjM39N0eHlN7FuNGjpJQxDl1jC6o7hQbWfSc5
ALARhhPY6WxvwzaveAQium5MlJRMD22Ov6XMYY85eZHaesLpchX1kqgQb179sJMW49y4b/ZQAc+h
WVi9yKVyzQXMfdOctr8wi+Fp8P3rsdLRKdpmZuvtW7eSiYDG/mkOJ1nQlsjjpmLP194DS3S+uDJQ
b+3n1NVgvoWefjnJRfJlv8y/ekLlt47tphu70DwyJz9zPhip4KFDkvXHM+v4+o/SxZrW02hHe6Lg
XOcFyd2W2TCZ10Esvdpqi392qzKajuilQb6HJUI575bzjzpVMXXq+qtxYqVYH5yiD1BJb++NzQS6
Qu8jfodu2+JOImMvrEeKvXmRzsvu2DGul6rLGQfEoPrzc+gq/4JHaMTKQDShTsfE4LGm04zC0QvF
BbtjEGp6aCXGLJGtDnL5Jah5q1Y7ssMo4MMBmaAHaXB8G/tSiy+vI2dDck86oeSNHMIY0pQegJmo
YPnJKm+lzZLJGDFZ2LJqZ9cadmAJuXvh0b9k4GSyODBjGpJ982wgxUrW5y4104ot1PVto/yHEBBW
w8BvxD1sBoY6wW5GPPEVsu8vJu9LoYOVkxQ/kFt8T0aOFG8ack/ZOazr1vvHQNgAUgNK8EOlK1XF
CRO5AQoCTmibv9VcbJIY/q1xKIkovWIt1raYqkwzyv1NPuPluJNUIgE4wR4Xy986744OM5DnbcN7
G6je6jCsVoWfy839f5UWQ6XdwfqfZWQDODCwgq8kwoNrjYjGZB+HfBPSZ26Yn6YFP0skp1tfVw9i
ZLklnlCP8I3Q0b+BFXhEdLrbAzsPDtvKONa/XAS25fTAj5BOz3V81ESXeHuX3Q7mEjdtjmuDU84Q
9PV1Rdl01NZ08gzLSHAsmDLfT/mV5EXj01PcvRxDuw9SnqLNIJm55aVmTHRcg1QuW6/S7s3BJGlf
n8FKiZVb7oCVJ5uvulmH/XeBIwu4sRvKZESUhnSlP/WwqltZ/8eXHyQa5ksxjBCevlI3viEjbOuN
WaHLucwAd6FM/yrSAzS1QEZtQgUqCU+Abq/mfiRWnePDGUvphI7zMQBSYYGqNHQIIyFowJr492Jz
nytTilwAHESm6vLF41tDtvY2NQHCw/YxCS3LZ4RZIQxUIKN/BXkUB/jokOeRYlVUOI3ZITNbmFl3
P7UET6RZOa71pD1o4pnRgmnczCKI2kCWe1KfohAw01bG9pJ45yPSvgGMpdM8GaLLd5sH6sxVha+W
GTPrQ8a+XIwj49q1q8b0RSdubJIVc1o8mGjXA6En9vOT7EsB9hRHvKOVV6w6QEWT7f8Gv/ju6Klg
LJZ05P6faidApf/g9YbW78ID4+r28vNUgt5WESkt/hQBCEJMhgMiCvUuinjC7pj7A603RmJ84hu0
KHkQGeJqZcLNImzdQM57StKIqkRjK97Y2T2R3YTRnBKnZtqbTmcwKflp86hVwdRdbdVkhDb4DPOx
Yj+QxCAGzSK19y0xrxUiI8jC5GQsHZEeHXDVE7GQYvPbUaTtwRahdflwyqArOehMgTgH/xI654x/
VER9Q5tnrjwnW6exRDTYVOvOKrGYfnpIWABfiJHpn7+p5XIwDAloIv7F2j3OghrmXEQusyVe3cTz
V4zYituxGEoPAefGZrc/KxJNeS8BaHzUeF1rWLlgoM7kWpvq/KLgWZfYu20Bkn7cUoGfzISJvIBg
KglnJMGOz4BlxKIFZtrBuc9KnqtndTcdaKBS8L/txFUdC0P7BNSOpzvQoCw9yPawFuN/51rAnU9g
9F9NhM88FtmOM1KAQwkrjjz4f33NBqNZ/zwYzc88siaswvHetTkf1KfWtgd6PrzkVvVPfSYy1vk3
EkDRWDyi4YURSfgK9X67XmL4FK/qUi7/mbkuovde9+C3EHB9o06ViX+/Gs/m7T0iwgfy03GIkTYt
7xxZJLa0dPd4pD4+CLUfrfH1HH+7RCGZ4wnTQbI2RYY9cHVML3+nNysP6xbvvkHFdlmFc3aC+gtF
WHJxcvPL9TlbA+2khgXqH1bV2c2Zn7j4cjdBqu9E6CZ94Iw2DVnBVhoQEKVm8fCbUKq6NMI7if6a
KZvIh6hmPDx60CLV/fyrDbxvwOOhu69MqFcm3mPTshYsSC5guaao2355pBuJZt2J4VVu0xX056Ks
vdZnxnHWN4Mw3Unnc7QiiaL90uP0gURAYUKmGgSJaRHbhd3HVq363RAwhu8VfBhcOCWyAPj8v2F4
9jZWRriYn2rgVdiL8zDi1w5VcpRWqCBgdpOAu05UHKv349pk3jWgAp7oW3Iymb8DrrCbwmDCilvZ
eHtd4roZgyDQglvXlSfS2yeofgrrbYQlx0AwNbJHex0AIqC58/8FivkaccojFejPc3VCQqpu5yLr
eE8Z/zqklFZoQBVhjwjfjKplV8NdIwXzRanP3OMp3xTZWPgaGrtqsbDHXKVGXi+VDBXNQnnECUG+
jeSHtD1Idde6aT11IqAXQnhAN3ZVhemaYHamU6PSuMWXRAHRmLYImDHYaFchrdImFu5cPbEXiYYk
7hvR8hcztY+eraIROg6A4dTqZfD3360Q6pTmntTqLyz+duPCqcAvWm6QW1WmYn2TD0/p4QZPE6RG
pWqtiv3PkFQ8T8gED8dcrmxhBlRC1M7gMmLwclH27PuwUNdfpRpdCLSEtjL+K8VRsj4OKaa8p+3o
kE0fIL1LhLzedqQPWxaovyzaVm2kgxfS3sffaNO+v0H1Osh13bg/vsflaP/j76IwF3hTlzZIuBFB
pcUypgjcg4Ql7ysNboIiwoECbbStWkqmdaTQ5enEOVZig+DKYvZKRlD+32mDuY4bIV4/UpVXp86e
CZB/2GIeMlC0kALtFpH64MOuWF9fpgX9BPnPFpv3rRV1TZ608GNtG58nCEv+x6Xetlbzes5Z4FO/
AwQ32h/Q1MtH605vzEsQQpqhdTex8/rq2Rzp4GKcOhtSUuYbzQOge94WJqCK2QXx06mzv4Msl42y
V+ivj+c6jAyhw0vtbjHklr7ZXF2n/DCH3ee8y/yUrcP9twi04rWOHndi0wchMri0S65/jTflE2tb
/j6EewHvP5SOcfQWyZlVTGq8BsEWS+Fo20raggYsXviAmdS90Sx++UcbmiQHvYX8OamlRvrh32F0
muBzyT6o2leU7Q6YP5uqw05c998MxLs8IdHlPpLx0ua4hYoUEPPzautNtqReC/czmpc6lbVzRXhu
UQFdNcXd+/TykT/4EOlSMvUs9YSEiAlMCVY4ctRa7N5MqCq2l9vX+Ji34VQqYXRkbDZZojk1Dr70
MXtHSaNbwcNy22Gwy72tRevTu/A6OZQE9dFrjhZ/v1uNvePDMAvSkE+WyD6qxFFBh40ssLuAFIws
XwUjhB4oo3HRBilj5Wu1mAHtvDwtfUSAcZZ6L2u5D9F9FrSEYdM2hkNpR39roVY5XxENzdA6qLb+
QXj+nRF25uRY8KXcyWdOsmb74+NfyboD0yM53OzzKnw/MtZSRGjwiQ1SToGFJe5f1fR363HcdXc2
aOVInF0B9PO2Zr5aeoBSNO8FLXpjR5IYWicvfFIkLQc4cEouqj8u+PBXK9/b/mo0Ov6AsQHCu/oA
Ewnd8TtFnFVs65qaiTm63HTniQH/iWRcSBbLe9sMtBYATQ9GuKfsGQcVCe6REaytmdYCT1CvEJv/
FyAHHNp2pMX+/lZAI1GC8MTKiUWbVu5gX7bG+Y290p2/mdIYBdQJ06PkLMPmCLPXg406dY9NVNcr
EhrInQjJt/d1YjJ46fjcU9vM0xO46gJR4Z5CYiMvDehwtNel/P4FLw4J9gdwFESnYUu5p6Fm/b8T
VcJkm8dtD3l/fUMttirnd5Ta7X8BgzEG0L7EndjaMlyABS2G+vkW3OnUA68mMoKHzoG+iycr/zls
8YrxW6hwS1XKVh++HMB6RsYsWvTkj0XPR7YRuNJAvTfUTPS8woVNj9XpvL0NX/PilHiKBn/Bjpwh
jZnx0DG09t/dmisiXnYhdQERlOX0RGak62hlTa3Sarkerh2FJJEaNS2HiUxyuLtbylzjgns0tp2d
uGd48L0UK4h4bJqbaqfOganNJ6cRwel3MW3wXDS7At3B5ZntPZ0B3V1vK85/mAKBeUHBr7EusLHY
rFdGQXiVI7PxKYmE94Oje26nPzkH1XGtYu85J54vLGTyQDVIo8KkAL95LeBMZKNFzyef8qPJWvr+
A96a+/kae1/45DFKNTYXK21+FaoR/bqmZ0cOqXZFRHUMvQ81sm5pvptf1zhb9m7ajKm/LXOgYLR6
e0aafzzX1jIXrG98sCvhlRaNqeJqggmciC4xJB/mSJk5gdhQovzBwRLvmDyuYJQV7l0/ciseQ7gj
uQ0nlPFpOSBPHgg70CSTtA6JgZdSWyFJf+aavGyT2ZotImdSby1utvybw2T4AjKwiqw12VWXYMf6
8+Ya/pIF3vca87JOiNY/UQxmHW+A7wyN+GumdsNeQh9vY+Ga7WbCZSxcN96sXfk96zY1zssnfhhw
yehdGqvTMtoV6ql8prpqhXcVQx93Uwed/KRAkL4a34B/S+pxDg3i9JlON1UOKLYc5gEBF8nNm98T
twYOneM2OpR7yQnS+UOX2Vf//aCa830Z5d+iyXgctfWBK3rnYdaNhPeYgn77DprHWrZ70D13w+MB
AY4c6VekAb9DW+udx4u0CXxmK6d7aHWCmXYRmv6a+bZRZqv8pRDVqRmyqdKtc0WNhPWlWkeVEajq
c7vl1UuNkkoNm0prVIZxonnKYAzX555kFTxM8UgCKhFyi7j+9WuJNUtK2FfaGkhBaOxE4KtwkHXX
8pwKi3m6HvR9ULvfKYzaiBlOHMz6l0zj06W6GkRhQPSMy400XyHt6sp1VwnTa+WIzMrSUXQJ+AUf
NWJ8ufyUziHX+HK84lx7EVyeEEzq41pfSR1mG6P0k6MFmEE9wKzLhXoVylXi2djFVPjn4f6IwzaV
vdXIouyQSoKqvLfjtl3xF8hP1iItazJ6EhmrIzjk2Tyb47MSDHMI4qtQB1wrNtPPdFoKTyU1syH9
JOqUfms1WXG06e5sJU0t0iTxFOcigMrmlHC8Ea32/3ybrbb2OiDt8VC3sIXxTCxcPmRMzA3Hmrvj
+TQoydjzmLe7+GW7NKrAxhC5YRzTWoENsQlMktM8D1bTelM0PW8CcyoWZMUDTTzHil1VseNaj2/0
cpkGbrsBPalXzoiUGc1euZd3bgd/u+twSDJcpYYHIMFeN4vRzhx9OjSYuG30vS72CCtfq/qnhRyr
rNPI0EqNWrMTS82SfCqhbG7O4AU5M5PRHfKLwaKTC2ECPh1bUnz7MCp4LBw9ddAciLBFItAZVSYo
sTZ43rFXVr6go87Fdz7c9jv0QfiQdpd31t20UCfJdFlSokKR4kavta3t8lVUMfg82hJ7kKFF1Yew
bKgqkuGmppn3gHGneWBt0pAsc1zy10Zff40XENkovWQgJLSRcvmgLzizHjeYix0wbgFL02weenoa
4SPNMeX5M7JUx5sMWWe5v3YyAXZ6x+j1Dlwy2jCd5WU8fOwrlFhMObTfxY+tL/gyMQ/93k8SWjcS
I6jgvhfuMQ7mQ4k2jB/afoJLN/kCGv8/53GrK1BdiH/XSwaFhfbxlDPQm3JS3hr3Vnk2nzd9rtSu
bCryPh42YEG8wjcjmH92FwfoG7tY8pwmpK4wHf3I6VSlLPS6a+jPHei6dSBRju4j17rRWQtnnfHl
mahXd9zQ14Iohtaazl8fY+eRoZy7aUenVCkIEoRPIQe+doaYF0nNbqhfVOg/OZMU3RHKN69FBySQ
F1iY3oemrkcNz5Gad86LxLM2FFbcu0roOesc8J/RcHvD4oZJqVfUZZfdc5wPE7H8bO4RL+GbBVPj
OE+27MM4p7kJHUw2OH4MUFzyMCDwyskbXrrtM4bp8nIs6YTt6MTh/dR1sCox5UPxxlgwCmLgFwUL
lr6yYeGZ1rCm/UiBjcYtU32C+2OVH0pvKSoP/rlclesu90Y9dmegtXabBLL//I1zQ9NPEg7VPhyn
1a4OzEirSWipwxwbzdztwhcdmXBnX2Fwb7nJ1A03aNOmV0Muw9uZVSVFNsvFAGCtLBn4VPveUcSW
aRLv2xSoD+5waZTWUKgq1MDE+bIcGPmYFkGHPVNDO04U/FgSt0sXjabh3dyedco52HbUuX+emCYe
EzOfFxBZXAP7SOf41p1kcmcWV4J9LBQ+wc6diOJeaxTwc+TJTUpFjXQ63pFAc9JD9xzhjLllQt2Y
jtsk0PMGtKwkzw9a73xiFYqxJbf0EPaWm0vSopa+lFBRHI+Nd1LkzXU/slboeAnNE4vL1uj2S1en
tjMTTZMIY4Jij3Myprd86xLGyAscSLsF8AkXZxvIgxlXWQHumEN7uc7vcYuy3tPNY1KkPH2cl1aV
uZekgI2U0/20Ddy7IfNVeLjynqjTbriD5wNb+6hLz9ToxJLj20dUk0JXn86WNb+VEQvNV+cOGwne
pXPMX/I7eSG6Nl6JupeRSNgGguRENHT5HA6xj9BgS8Pbvj0uj1l/F+aDzSfu9rLT6ITZEuI1K/K0
8DJebr8EzhYYrNyrd3rnLm1cRvU2u6KTgE4hNWet1sbtEzDnJj5avVAb8l7rvrJVfE4mvgUXxT0g
Ao8XQroIxCVo87rUFGJbp3i7lu/G+4DBykRqrml92dAZlYLH5sGIL4ndrcc/k7Whjrg/NXwnQsiD
1K50j7dA/D1Ug90t+XV/SOgcUt1B7D10fGqQDHfJbgYtV2CJ308hB3dnBrsDJHR3hcM4Wnlx46lP
iJA81tMWee7LRaMaEtSk070b3Hej+mq4jktzKBCOt5U+F8R3Cvx+k/3eliAgdfjjz13JhK3KI4Lv
h+7oHCCNSJxLdTtrACrjVgjAJrTDbX+JDT36HlDGfO3G0I+lJhv5479jJTtK6RfVXIme9wpVtr+R
tLVTsw2TUcOqJPvaw0IEXPxPO6ikUDNgfCpKyOpC93AihfOyGLxIMOIpq/gx5vGxur1pvHoWAray
ApPrfZnCpqxVEJL+qAGuIIATNFXVaqPwml62NPO0TWNccq0lPD2W1dtlKfE8bVQEVex5hqQzhxtr
uyb9pfyEIA9vo0BqwMgFEGZq0phdoWpSG90ie3OkGQxHB2S9n1Eqjnj2V5r6NCUfPX3cH8t/h8zE
V3Ke+13kH1bgMc+aSGKBuRR25WIfnYKaWI1XkDV3UdSXVEmS81wY/SQEkBUCF+ibZR3o4lBNdnoi
YPy17VI7rSB4ZkPYhWsTIYljhG+kZMcvAHa4+6V5hACjCEQnDfaWU+hMDai/7zzKmadbVEzJO9rQ
cSzma7IR7fQCvBiFmSFGvnyHCBLJ5F1hSis66l2piNW435WqLHLbuNZPLJkKVuosYOtMrLJoepcv
+i6CqRDLMMAmR0jRoBlho1Tgi6YGRlf6LNgAiSNc9dFcnvK7zrLxsdp8Ogip0PJJfudX147uFrbt
Bn8eyrhyqW2coYer/AJjwun0AleAv9xOvSr+ZTY3Bo+c3HB03UglkGhnOwz4dGmQjJmsUMYlETQM
o6iEPmL63dJJZl+rKe+a9VH2PnHhDauV3nILSOVY7OEMrgwflglnVQzrIsCDVEdJr11JPiTwQtGv
G3GF60E9DhHICgllE47N4LYVOHl4o4RUsNmjIzs0SCqd9Yw+F0fuy0xzjH7e8g1m7FLLCniHVsaZ
E26KbPwz7q/C77P3zPJ+U+ptNbrCALY5Z5ya8nwGSvKlX/02gjw7TIEYdpoPZ4NyWSs2ygpY1+aI
l/F0mYLNn6Ay6xK5FNQPoinPPgkLvkDugaWmhy+MMiB7c0YYGTyE58EeV0ieRcFwHapV5J/ZO6ly
Z/XRyajzTzuenlNuqo+Tx1MZ6iUlrN7th5Yqlur0UXZhIllCYlr6wMvJtErXPNOms3hUmDozuuXk
a+F4+tq0k8jF18JNAXJX4dEeZD0ljNdhf5byKOx67Kc1K9Co+fNamjJMo5yKUsyr7TGjiOGOlM6X
LV+hE9QfyLER7gZC2pmS2yzXKwgCGmCYvzyokzR2n/QFKhIX1MQgTpGqvul4sNDrdTVTdv3f4rMG
mFM7iZkCgIQcTpQ2JfbswFOcaf+ZslunC/WoEB1R8JUFWTn5mHEMR2pNT8uscn8CDaqfyuL/T031
J7EG5448YuUmzwWDzzz0+SR6RwrDRuEzhOFctxVMGBDMODQRZVdP8lQ8/ftSMn9+s/AJ2ETwc8kO
dgVpNvEofGoXO2mptujvUsoxqOnMv5eMC8m8lLrZnkaREghrYdx7yjb10YiFLqZfl+FuHUV2s2AY
PnzCxLZUgJig0uqiRE2SJh/FgAeEzd1Du9Ic+/X5Rc17q8/PfpOwIBL3UW3fThm2mc7XZai0CaxB
a/Ln+bp3NHkDQSGMzKSyq/Fu6f7A28grsunf6+QIAa7Csx0InioqVLRXHzsWP4LoU7l8TAgwTc5k
CMk7zBADj8JNRFcQdJFI3+w0/OxHaNgwBXzknMApjTAvPkH398nm7E9LbUflrg+2P5swV/AEl2Ds
jrnP/9r3cUyqlydUpA4ZT7Ww9u3sXGlQZ0Fin4dECwU2VbVIVdRlz1ClRE1mLGNBxeAHFoMk8UAN
08HS8sLcf3/8SlxTVJrT3/Zwp0uLXYTkEdakYwE2yAr2kv2RYTh3pVadPiCssi516u1lldbiWPed
JP9QPBKVfw4JC2eCniCuI7jdo+x5qD19HMB4a/xJ7pqUiOtxz3N0TpMHKue24NP0du6/wZNKX0bl
TXnSpv2MOg6sKvCxZ8e3CgKU7Pw6Yymzj7IZThYjmWMgS+3zwrCcZDNtKTm9JCDJVDAgG8fPTz+4
bJQOrrxL+K9BSIIGgtZVrvmhr3FPabzPFDm4XjIm24c3Fi2jethM6OMJCCX0yo+SieuasKyJuail
wFtRB67oS1RAQTMDvvdert5v1be/u6kYqvBBi6kqvqkhT5xL8minxcDUjr9eB7Wg2ddcJKkaGwHb
R7ZEGSj+YheMYiEPANcVEzWXw4yMxRWEJQjenGIYVYiR4mXakcYn/DWsrlJ7EKF2TwSvmogiFBru
Jum3NqGQSmRh2UEXsolohSRjTEoeANP5/JsYFWBBph4WnJRlzZAiHOMquoClStpH0uDzvWdMJWJU
fKUa6sdqBFjwCUp4Hppha1wCpEFpIylN+Y0ywXFwRdCCuvLT68gF1+Sn6iOEhlI2/ryQ0HqFNixO
DfLp+bTO8JNSYCpOs/NjzXBMJcg8NB9iQtVmB5ENUxw51FR18FVafmzrywhTPn+bU5m7WOd+rF3M
W72pMCpRIBvxngbAXksJBc7YfRJC0oZVZGtPyjEuQbCsMJZbIdbNazhHx/RsiFqWQ7xv/WkUV6qb
TqUxqsOyM+y44iyEJusD0Ia011B6gKy9jDPQqyHSJDFFM5OzhZ5yMKyZrfCqEnT5H3HIyLlHl4JN
tKjbyaUEh6fpHZWjaExJQf2wG3dvXK47044i3uFsb/uv0Ah4WMlx8fin7/1mAAL1MKBfTMcF3ipL
8ObhmLJa6M/pVeXQ9S0ufn4EqeX4ET3Sfkzk7HCa4JeHG1Ma338swx05g3Pupwl8QSBG3nOIPQCO
taY2N3WoMqZ2LeO6sYwc560vAX6CpQT1ojo1e5EF3CaepZnsAi8OvoCHzTTa1OKrlg0vKdl2gn0N
6VRURvQT3oeZl7bbDFEnR+nHP0pGcJqQiLWtgdCOhgwMGyra9kzFOMoX4gMjJ/xknGN8RUQDdsgR
tlBJQX4cZ5cQ/eXOuDQmVKRg2iSy71mMuAiDANn7GnMBOrMS+XsadblpmMTZmgx6ALb1uYQmVuzA
2kQGYHKLcjaJ2qQjPx16b7QoJn3wdT+cCCBDMcEqjaeaNk0r/yFiPWkKW5VIZgxOKvKDwdW76+js
8YWlG8NzAR+2d8mqhjDLgn4XnJka8TZZ0wnT7MRfu9/eOCLi03jyoAvku7azEV6eTSTRC8ea9OcC
JEqxzsj7fA2+RIi7Y7cAy3t5B5DLa8XYoVVHpu0nN71V05Z1pKl2BtdzfqmywMkl8AlL9MWYzpnJ
4G6Z46efAQ42qoBW3HzJBJy16i6eDb/0ipIMgGFSlOsfKPgNeBG+e2oPcRSSfTmFaOgMP2lb41Hi
CjZXjC00+2e+xDTq8wtr3LtHo1DzIXG4s563FJBQ0eC+FsKpqW7vR2lLUU9semDzxiQ9+/h8XEZW
+1F4ozr+TANFHlFeB9XhO0aHGfSy6+92pot3L6rJrNpPWtX+JD46+OqRXDhXosWy9TKPzK6sISEV
DB7EF+/Zq3hlK4Fv1T1jQffRjwCjAKjnGL1Bg/1U5ru+wsUQoMh9MTJfEtJhC/f/A/FrAf2RrtHB
vKxgUUqJrRh67dWehHyybsJmCWITiYJd6dZ9KLsK8MezIgxOLjPNYvy6taGoOKCMEOyTn/9Az4Gw
FesvAD6ksFNXaL8TZtVVu9k+DW85lwhiKtWhZjhexX3Rl9pRuf0JhUNVpCY2+OpPWFHi8S7mipF5
iq0uUmgvYy6mynv/GORuLSJvv1W212AUzXwuPAqRrJe4I7MhC26ADz0gCsr0o/fFXhGwaa67Vrj3
S7gq16JEgJj+6N2Gr65KdnAE4haWEZgvAY897SYeog9IN6pZWUOK7r46OWsk9M1b++VORAkW3S3/
LtD5l3YTI5632ndpt1jxL+FAMNUNorJuIVF8Ldd7BcTCTFUIncVjCBJM5frDtyxJypCnna8kEZuo
cGkKHCPARE8ZB0Du7j+rcWRBE/Su6sFWrV7eoeMpj47LujdJ2Af7s44uILOhLfvE8SA+WA8sEwLk
6Fid90EnQhwnfp11bnu2dWJBKZn43A62s9Q5I56Ez6vpGA1ErjZc0tYCl8MnbKly+GcM0XGXAZYw
W4v67ekEBAW1os1LDpNb3xs0XmKQCYtF3DRu5LxnKAMqWR0oI5dSupBbbYhlI2Dow5XauFSUlLDB
6F6ZEG2mlpNlxiYdQQpNH8s0eEVu2GZCIONkthtw4vQh6t4neK3zTZK2EFiWvoYXymLSf1pqQ5oB
7QKQ6EPVzDtw+kYR/8pATeUOPdAupYYIIx2L4RrL0koQm1bWd2XLbJI54gPYa4S8EqFvIjzXBCqR
t4W+wYiNVlJ53flmgYEc8s76LvS5iN0LuvCDgmVfvCaO4ZdemaluBdYGbwmamWMeTLv+NXFSwMhT
QckrggqO5emT4fa6NzlRFE5Q4jAHm0LrLJdfmbX9kFRC9R32eXlELAnpu4myVHv/DhVCTLu6hSUA
M52eRLXfKD4m81i32g4yHSlW/7HSUAa4ys4fu1FCmGOfrP3Gaz05D1qJttqpToG+6q/7N6wCdBVW
4DVkbnvxeDAVOCXs3wNd19nyNdBqXRY8LcPMXs948tD8cxTapF5gdSleBQwdynACqgJVxJsO/EaG
DGRiaxRKc6HAVWruZ7Qwy+7GYwyJetVQ3Waq6G0pXouj0spDg5cWAA724wNlX9cbzJlsQt1HQeTP
vDUgTwzcaCcuOHoWxysmbsAZUraQK6zmSSrFItjYuyQcJe71fBlkPusB8apU1gZctpNmOp7CVG2j
p8sQmPOZKuX+pCd/pmqLCgDFpwoJRACzbVvdZ7CoeRU0sle6wognSI8peM3uICH9Lj3pQcfkVAI5
dhrNyfUz+Eay+pQiBfq0T0N1FRfhZU1BSDoz/97GaKx7JU7sxPpDPiYS49KleaOfy/j9HhN6YpsW
Kh/QPMRtL5DFtrmDMBiobpWh5OukCNOqM8blOkcm94gimjgzwQgakX8hWOAE9NsFLvxvbbDFvrOo
RMWuIfhoHB48KmHDgRutWU93b540vpwPGPgL3VAh6gfORTZAZhlRMMm9tsuVq7ugpOP6ZwMWIhHv
sVF+I7NowjUw81R6s/BS4WA69ILSEa4i6lwqIL+dzNGCLJtkCHK+6Xkn4aj1scYRNJPMJOymu1LV
nMQ3ssNy26yo6RQoxgcUdfgDM15Pr3HZusYuXpGenlrbDx0TAYpu1/zhnaC+frjPQDOXlxzI9nUR
s5/PIctRIfgl5MiZniMoSVGM28DKKyaX0WWJMb1sSmC6dyZjXCXFYzOp9gOjWb8Z/tnCplMsf85n
t/YeITStYNwqfyjYR64UANz9U6X+5gSMRomxRHD7sDz3ykaaAeip/kWoqGea+9fOXGzJAYlmXMo7
p1DSYXD5ziTGnx+GO9pRx1RSyI1T6+/Vi+bovBp6ldae1r4O9vEO3bDPVDmffL++er5iv0qco70F
h7qyPIHJtCxl7/ySLvB/BgMK8YO3cN2Raqygeg1Cjd8uSbkAYkCR4/SOM2Z1B4YHOYi5fxzPemP+
ssI1/VHS6raj33247fQHKIO8hr4QOjuVk6yiqR2mFu2U8smbR+M/fpW7OvM6ZLpkIQaCu6OkKF8x
f3ywmuHcJq7XBbwuG97jLqVfD/2bF0tBFMFow4tdnKMLu4pt0ekah/1vLq2tflmfHO3Vg6BFhTMk
aEz8UEtF7+1veH79QOpzeDh1tkmxEVLZW0GPpwMsd/BaEPIjfFl9+3ktAk7RD93ctP6nrKSeWVp9
R+9hWnsh9ymNlQR0s6i3NShb0IDampKCzrFccip1dnMIetYAzWnKwjfdx1Trnjoh+TSqp7oepTVq
qNkQhrgG5SHYBh9s+RnkIThyY7cS3pJiI4oVsJ0z8VA51sn4ij+BLzJN0kVuUly701r4B/8Imxm8
rEzH1KobhBUCRm4ifJs0i793Wjq/0ZwDjtRAAxp+Yvp6gPm+Z3DGfN3qZW3arG89ouBSNUT0WUjI
CHX/zPIwh+mV9UF07WUxd+lEWOkHoKD0RbHlCIEYmo2RNq+W7k1ysaAF+uJ3NKnbro5eavJQ7q80
rr1lwdNRMAc0BS8lAd2FrEevATaysGi9Dd+w91NSi9iAyWsRc3HUwH2baNm0IkXZs+3R0qSNxJ3+
rRZVozvaZoTo8FMikds3gJs2QiX+f5p2QUDpysiPhMDpEDhvW9gPsSpLzc9rV3i8nwf4IkP9tQbg
hNDY+tahIWgn2Us8A+X3fYHAsApg2wpuigyucQIDJ2g3jw5YiwDttYv7zsuAyru3RtAbl7wBGLMw
b8VZZH597WJ/dG9JVkm5CZjihhSTiGzUKAW2GRpjiWGBBow6rIKf498c/0oMQ3kobvzN//mdwSg/
rJP2sRJYO6+TDOZsB035pNcFglOEoPYHxmKhi92KY3XEK3i/Yg5uzkfW8MqRgWdH6+UEV+g299QO
dEwVwYoNK/5fqh8A10o7vTDaDqesL1hwc9FgQv/As0n7sD151N8XL4vkFbAySG5LKlgod8AKOJam
HdwKkvOJPau1Yx8SYVSZ2Em5Ef1rALEZtR4BqRaIxYlrPLTupqQvnSmsnH6W5v23dg+I95COtde8
AaDdo27zAFGwC7HCNrZxX8P1TpR7lctn+u2WdBdmdUXpZvzXNAJ9+VF+eNYApTADem3zqejecITp
EpDNcCSYcSw6Ujw0L7iEUR6uozcea8p/NsaaDOzyZIdXMQS23xNTc7YcU/j1BJCCQvdXGxl0GeBE
STJ6hp8QVtCNrnMB+x+qki+sVkzSbq66SuB5d7qOUIVzDsNMvxoIHxET8j6uBdg8FVrbqvIVXH2b
+Ydy4EeOiDhe5QK8EjFDHUJb656CJ1Txlsp0suFw4QDm0Rwiz0agPCjpAIAEJIhk8WL1tNHNcc2n
zP0ZCwivabuP4zs9n1jYgJvpAiO9ibEu10H34wVbI8hy2tFW1Zj0iafZGbVcXx/byB5jKJ6imPc9
6KB5b8kGJpkT/LwpJ4WMIKNaI/XOoENJZDRVP7RM1trEuZ8fH/7wsfja3dF8NU77Hi4QYQ5by5zs
gZWGhGR1fy66cD8zmPAV23jv1xeTqcZ052rayPyGqmAMBZ9f5v88uyXY8ebmxvEprBek6gj1cPKl
tZ7bAoBypfgUpalxGKxC3TdhmRNElkuitFSXt3xPLfvTZ6GKEpImiI8G0LYIwhyhh9eGn0wbOSpY
ntDoFVAyz9PKzZLXQlSxhOMrIdLlspCJTVTwG9iClEXsob2/Z7yd3Htv1ZlccBa/zI2PAbLqq+d0
FHfzcCaUsr8w2AT5es1OKCcSxziSFu9T1PmvJYD7kGzZXDKhvx0s+INvjtzM8NW/HGfl0lAvNq3M
HcaFblYIWRJqpc5bTX8ziVHmDazti3lCx0JcKEprlosHFgulmJyfUN3DJXfAcPfpVySmgdWY51TK
X4ZAlbL0TE8JbC4QxH4t4wr8G3H7eqj0wsdnYd+nSt3KgH6D61qQR/oA4BGA9dH/o15Yt74gMzuq
Fq4YumGuTTUb1KBfDUnEc5H6Ti7S3xqisuaJUe0DmEHSUbRfYD0jcyJUA22ybEmCYiLH+fsRTMsY
iPSJU6OFThU8mCdpOrxW9ZY71ZHR8Pu+pPb/vxiOnTVRaHnEUn12HZA0A1rK4BptQB3ZdSSRK7bG
hLD5eaUHwLHoaXcm20+nrxKQZ3zJlcZ7ZmF8FmAjG5ctZBiWWaxrUBpjaKSqrxGGhpdLlFaSfT8d
ODcbkvb136O+neuNDRKv13Ojqz4tgcOpNy2wlSBPRqWHCfZwB/QpDlefLANGnX24upLP3U9DLr+T
/cMvWVhXAvek/wOiGJGPLJ37D5lCqUo0KDbswugRJiw+l3a7fZ2eK45Spzh+C4H2Y86fx0909oAT
KmuCeptzl8wE+6iEgaUzn2c/juiiKzUlOaz8Eg9IrQKD6PMD6+Zkv+b7VxuOVkR/GiZRr52eRbFk
JQVEIC83QJ+uk32/B9DaYok84fJMs897xupxDr1aC6Z5B5IzTXMeDHm4wxDprC+NcSdXEi81IuG5
q0xgPrMFksgSG8uwH1Ggi5JAkkHWedR9nDH5p8KRJX30XcSS3dFl0ALthIYuyDb03RqaWN3OoeaJ
aD5YakbP1myqynuuEDYpVZzQbyPmvTKdf/PqMe2AeZ+DF+S7AoR3pTG688Y5HuuvO7vPTtELrcko
tQ0miS7Ss/87QCmDphU3VWuV/XanOXHnGEAvcn7H/PDin4sxVNvFnlo5Dx4iCG76Nz+RgLpdTYRc
BSPrKVdghwXAYhY19DWVzJ0/nbiiP2at24AqOSTK8ME89s9yODJSgT8f9KrSWYVQHyiumztzLa6R
ed/k4dkqnqp0u0FZ9qGoSQk45aiOS8EhTdXqCIOQDvu6yeBRDxhbcx18s9EmpYRQfXh/jvnLZHA3
xZHN/mdo3uMjnd90hSmc4ooHSu8GXn6JzOidWQECK1lkDtR2BKikArS/GaNwG4ZvMIPSMi83N5Af
AgFEEqFXRXzHtgFGJGBLjAi34ywWYt3A9sKriBHMe7G3ic88TtAnK84sw0uRLk7a8q23tCYZUujG
7t9xbuv7V2eWoMTwZZLWcGJJObxHFsFkGDa63pXhDtJTBCZe2gYgRPRdjrOIiNN+PM4dSqZnZnEo
2X+Q06RbFgdV+wYrGBtQTzLz91J0NZDj5XL0aEpR4n/NzsdSd9PqicumyHzWYSLQJuYsXSHFCf0V
A20NFs0OpWkHvkJmUQVDfhajRhlKTamaHOJVNjdGIjdVL8WjBNxQJCql/4clSab4xWGaxsqm2SnR
2JsWjayReUPJOsuqm7luHVTMzoKc9QuvoM34NVT5XzOXYPrHDUTfurnqnTI0G6ggFUOkQKe6LPkx
KQov996xz/vxMJO1jzHpjOVCUVh8mSndI27M20qLtukL3C98igXjOe3M4+vAKXIctu4M/fFZd1Oc
za09RK5B+d+zgTwQEIPLA0G5sOfJgXI0YAru5gzCv+bb8BEm+rW8LT/ybUa49SF1KGSbxDLJiae0
NXNDWx6v/Ot7WhscKLZxZFkh7uLqtU7reCGDSsEert8WFfjLY+9QVE4oROvuW6OucZJccqp9FG4v
Uk73jvi8DvXL3dRqs+WFebkNUZMn5iUUlAbiagNPFo/oaZz6SMBUkoxGDFvKA9D0plAfNdOGUa7X
iL78IXWfMrSLup2PfeTaNrgzKwGz5KUo2kUbglAnKfiTkKzKT4PhL2ycbtsqjUetgop5bPUN2Icl
+yqu8GOHLC4++2SvZh7XFC1FEzJRbK6TFgNpfzFmCK61tnbGtrWBlCidT4R4TU1M1DMfO9cfjr4K
eTQR/f9v1s4q7Ih6TeB5vonYu82ZTXWfTVoPFTI2wwwzFr5NHmU7DM+UAUR77NkSh17K82pGJYOE
WqhbAYWJFRaUX0Ew3wOHrU+oqQnJ3Zq1954VzCWBn3PsWcO6qgljdxE/d1hkEsMMyX79FKQpwptN
oy3bcuW5EaPIlh0TuZtIhx6JPlEOExyzNzbdod4g5JELfzgRAfgHXcevfaC1UpPZ25EdOi+qTdwS
4MTiyMdEu3WCui0pgcPnASmGEVMIaAYvuRERw0wD/ueZqdZU8JKykJeb5EVLODYaPb+iJXsujSRV
Pi4A4o0pL7a3BGvrpOCT/c+GdSJsO7Wd0yfQXbI6DWqBtDjl9F1DU4++F2pfX0MdKKQsbXRwAouv
vSbqJe+Jo4fS7BhLzUCI/NPhYkW6V597BH4inX5SGcCRS3hE7Lmh17ZP0Yk1/cZtBpQapUXPDxDn
JVQuslkHjkyDuDrrAogGWZy5BmB+sVK8ZeaXcdEztaKA3DYGXB55I1cKMgzvjqrTuw9k3V7dML0g
yPTQnS/6bY1EwcVuJqhMNi87rGnNsJhFTtxvea2H3435GpmYuuS6NLztcBSXLM5b38K+/dcGGfHF
OVghMNEOGXVCOP0z/tM9Oe4cMN6LwY9SkPbIOPeYqFYQSb1gFY5Nx8N8Le8r66DhimmQwj9BO/xL
bs2eur+M3vvrVyMOk/4JqaVdqY6QIFtoSwbRLPKf8WY+YOYvnpR1Fc+NG32iYHv0oKuNDHBwkJYT
uANxHyX+dyEOm3s5XEQgGCgcSrVRLi14l8rZ2uWT7bGupgxkzl72lXWW51/mKn3VL21H9+GazGj+
rmymhaRcDMbWSpZh4Ecx0RhLrMbo3fPTz+RJHkqMg7bL9a10KziNP3Fgtf6pvAOCsq2tpoCkX/Of
oWMbNq1oO48YvQLcbx+YOBAhOr1PVcmxS71S9L+yndUFoBBbdPO5kdz3DtXkkPxJ1GOfr2EKWT0e
/yOEGfV6/fLexbCY5LKCbVCgpFW9W8JEKf86IkJPKNedogiW0jM/l0Rq37ThvoSfRR6nCVw1G7kY
aGyuQSsApNbFpN3ybHOWRtpiGkFlYpzOFBnMaW12gSehOWG6IacbNjDWCBoyCBkiYbtWmubYNThW
+3CZaUnimTIZz/UgOLZ823JFwLCpxGS3IRf7+4unA58s5FppSMKdcmCslOrMG1XVlT0/377+ytkK
WtbXY9qkSILpb7i4EPVsQBc+5Ty+7E6InPQQe4c3tIT7ZOyI9l67PrZ0iDS+vypiqT8IiCPSAOJO
eVsVVlsFKHeXOIyuUc1SG9yD8kmT47e1Hc73LYaVaMLGZqsXelbjFfPKLefhxuuio48akHMjfMw5
ymKThEDjQ5iV611xWUYGKzgy+PC4ex3i60FUxd+n+JzNMD82mwEtpZr/u/GiF3rDcjjgL9hSt9Dp
qcSEJA2uhq7yMnaZ/z3zaKtxf0fOJ9YR//HVADc2v/rEgDdUXuBlsXdlVzfna2iR6jgj0OsmGbog
9GFcNJR4u3Xh881ikQTJ7USCwklpndeWiUo2AXUkHs0qu4F+r7pjzGzcHSwRJHqXLblK1TxNJdZ3
ie76AKFeERrCo7UOT/zDCwgKSSCKeCf+1prKKp3pesblfD6Ezqvf0jRSEEm8FtfgHhIBIu66zgxw
17/xtkj4xraa3OU1HRn4ON2k3OQKLHlAtgDDMdcpdQB9ErMxsGzKbsnPCUnOg0QhCpr1rXd/crve
/rfqaMjs3I1RFr8Peto2ornnW6xmV1LMhhIEDJA1wyMmUnkGjgEeH2Bbhw8Xi4BoFtsoz0j4zVm4
JbrLQGRKfsv2RP+n58qALz3PcAGe1IkLk1yO+7QevMfTQuMG0TXsND36dyviylRGEBpZiCz7qGxn
ZXwTkvGXBGIJMVTaQqSIUq7LBFhqNblHue3jhaMx5/hWKJzpjzKN3XZO/k4JXXMR5+yNnpFMzPdr
1aU7aUJx3VX52cu7j6IhaVPFo9bUkHV3wQuSIHuYFbXjBfnzoHDENIb3Jx31xL/wqqf1cFxLWsPv
q1SfAAx+cnVUAYyWCf9P1nj2zc+liTp0MJ46zAc7vkd4RDBDDvakYbwdSri+erR+/Kgukm2YTumC
IKtOTbrsE++TI+QpSlPlEZPdHT2hRwzXWNlPeX9M+2aqKjIE+LP57Ucblj2BlP4tCSHQkgnG7H3t
qqIx8atXonkriuodu+H3IVIDP/SMcvkrSu3BxfjTXyJkjWf2v4eL1AEzqurnikLkpHbO0nD0wh0J
dGZJXsrk68TXCIRVXcV1sta9SmjkgGOeZ/miqqfuv61FxO0FSSjCiUZAHjX01JvBtRP1gEwCvVaJ
Sq5mxlqafi1tb255/hzp+Ke+9LHx798tzcugxHvQFWSpKpUYMPl2z4Dnoa0BGWP0QDxZMtV3pjCa
BdJikRiUeuAKVrw114yxEzk30mAB3ekf6yqb0cB85kjYLzPiHR5BtmydINFES1Gp0eCKqX2b+GAa
9RSq5peutQRXfzV6VLKdt2HrsHs3l85Hiji6ZMbZtnsia4Tj5aetsFCw4pStzps3KEJqZ3djdoIf
UYIBU6EhsvyuK1npzwLWTvEEpMjrRvmlg3P+zdgAuze9tyxjPxcwxoFTW4ePlKyzniJpTiECtD8F
ehO+xyTfzlM/z7N0neYdt61ANqiYv/STusr9ffooLQi4Ye0A42kJyb7rokfzAYB11imET+Pi3wrP
YCHy2IMx+q9mrKnmWF/d19Vfm92sLrhbSGz21eIMtJBZoOgeijOmhOZK2aVScvy2tzadI9nlppid
goRd957C80eBgPd5jFNiURgyYG3QE27s3pv3XzFze5YJhbiKm1KmZvOnhg/wWrJjXs+GQ3Pc25x4
gjvc87zsPx2dNmYhvirsXSqpxNbCKWnGTdCmby2ucDDVXzXFdkv1QFXgzotgexSu6gmdxucA4GNB
BP8L2rNGTHQUMTm2duzxvROHZ2iUzk4vKMCyy1z/rSKRl1DHZ6VrJhqEVfqYWa6Xm4WhyFZ/08O/
BpuiCRVXagsdGnHcNLpTs7GbVjRx0LGyeKgcE6BmkIDta76mjTHrXx+CIHi5WbFQ632HYC0Z977s
tadFuIkAY+nJaIkTx67Zv+gULYmG5uqGQyPOZWnAEXH5+Vf270jht4s7hlm08Nl4s+J1C+vfLMLQ
3SzwD26VFeH4ExN5pi8HHPe8p112Uskz7BmYO8vZJYvS+egF0YSgPbvLrtWj/NQ9ppZkpGR+2p+L
c+dRmPLTj0HYfeHSFTiUndswZ/e3rQaTfW6P5ziGzfcg0Bn1MfIS0NFI8yzOF3Xd9mvG+QotT0Dn
8aTCQICNonI5r6i67WPrZAU+QQBh+4WOyGzswc1xpS4XmJkRg/mqiMBAADYwaBdPrdBoeomqcKAn
z/+xvhSM3e5VqMp4Wnev8OUsEPzJH1DPoNrOq+cWYgqIGSzIFIXTk1AQsVuIzimVa2qtGj7jVtTU
pZ7nUL3FcehQonUcpWNas/E8CDEMqmh16YCAcK78jV23Qh5Qgz7GKpnWCRhF/N+UIjonDRUBrR4Y
eBaSB9wVlKcCdKtYr9N5b6+5pLwRBUQHcDNKuGatpwPCAIqE+Q4GohqJpMybktD7p4gJVIWlAAcI
gIq3Y04zyUyLyCQSzqafDArXUt2HYzd8F+no7w2tmWrFOfmWTetVKCvtDe8fPvP+G7nP18HcNYcU
0iJ5IXz+frzfmnyIE12BCNIT8oc2vKL1v8qw6wZAvXQBL8Ona7dlML58xVnPWp7ksyvYyxGhP7Ko
zxJQQGZc5BU851j+uKepBxjEtB2NbVbDlNlLDdMinoRsOIicsqCTKgsQH0PesUSyWAHpqyq41XeA
JaBQSW+1lMFj9Qj9Zmxz6oR4A/ieaFhnl+gzCkfGaJ4VRi45NZ47NjXAjOVXI4qbIf8zClxWoyMT
VseuzR2h8thfHCsNbo0cJNLN7FEPWJHz8N/vMF1aBapFngBALg7tTLVYhXIkESnUoRW0zD+rMfwU
AMq2Pwh78VtlvDq4I8lnoNCY+spaOvfDYLCxasOghla8Mkq0yNDbKP/HsRnhzZeZzRhQqy1pkQU6
uL6iL9LiAr1eRMY8LtRdo+i7dDtrot8d8sXHlTn7tgSIFTcw4BA++AHuF5J/W5XX1nT6aL6VsaK3
1M1mLMPPr9ippOKmrSRByQ4/HpT6ZZgppVjtsTNiB4tpbsWTfIbJVygpiEDIEIblQhHsK1FenHbT
qBA4022d4mPNyVznyzZM1aYEVG+RgdMoWhVr8CULqlHMMsg8h/+v+sOgllY6ao3X1M1RpqJUdLmU
vwXXB8rpnbvnxOPrO9Fp0aYHDfCYFkmcgTi8auNLANrJuqzIjxnWNtp5V7Xver5RFRQUqavq+eGi
4Mk3zeeVO4kbzG2qBNHXXmP1Avr1OmDHd9EGsJhJGj7C53KBI3PoP28FdD8fA9ufhOAedXepfrkq
fvLC89vbQZXNbdaIlNcaZHmMIF2B7Vw12JsR5A4WeY9zs29zUGInzxFncbR8hsH5T1LqXN0AlvV1
s+lH/NdAQxv5wd68vdcK/1i0yRNGzXsvpJfS3x9ebHq+9AwojT13yunH+HTw+bB5fwzo7Tr89JoL
++Xb5Wqw6MqiMouwR+UJ+g2ry/ARqL2G+5HGlPAjkRqWIS4cOw0kZONBOKK5faTJYRA7KDZEWKWr
E4ByaKBPrDnzdRuf4WLyiaQgW/OiBQWYcvYP0FVBXAFgPt0ySiZDqpum6BmyQ4te6NNddHLStcKE
bkYJmALHkergtO+Blio0YmR23aBXNaX75APDQCktnb7dJwBSxNZ12QpwET2MAE9bjfqdhefBOlPu
kAbdyFbW6ilLbBIsecDhRcQbYEpOikCelluSmhzQIg89kYFhxw1q6y1AKndR7AhLDCSUUJlX4xj9
wQEkQRg8cgq++PQ+4RGBh2hrIJWrzu+wA8k3T3NILKLyVCUyb4y8O4lmxk/qAdPE9Waya+yzw8Hy
O2rJ3qHMiQc4exr55pm22MzzTImKx9HcPheH2r0Yk7i815ClM5dAIBh8EJFr6jMyy0AzjYBmfCnB
XVKDTrMTrdhIiHPv4Efz6t3gJePGbi9dn68DveFdrFkmT6bAT5c+2O+1qoa5ZPAYRBI8833M/auU
oCtw8tEYmCEVifks1z6eSdfYkb67apQcpPZzH5olmrXHGx06X2Ygguvq2Ug/5zmMlNec6ZPpplVx
GaD+XjBdB3o0NgtJPNYx7FA8IinaoFhrRgrBomQISvokITqZXXe50cynOYJyRlTR3ZW069QvirDp
TwQrYsJ1EQsm0mIvtWVkvb7zHmOYuuB8JgTOf6wFSB1+A+LgiN9bfYV+3kF+Hl3DJQcR8Sk6SIbZ
rUIdAoW8VOflOaOJ0k66KoXPN95jDXFmLNTY6A1u0LCbxloWHtPmtmxB0Ar/eAVwi7rfQ1U6+bww
rdW9BjtDnHL9EgaX2k2dWDQkulkGzBSePCAJecXhRjBviM6srkaWxaoaJu9mReSHT5pAkeABUMdX
gdYoT73Jvfvc6M5zk1fMrzi21+0b/NTdFnhMz2ACyOcsAzucyC/8fEPeC+vRQRsJV5UMPw0z0iyR
/z1t1fY1SH1TjOqeIu1/lRgGP/TM3tZLWTsalIW1GRLWYFjowvE5G/dzEquiH8xMK2ikewoZWO2s
aeQm00/C2Ys/dkj05jo+Cz7dAO/HHUrbNqxzHfP8AqSDYHZGqxdsnTfpELoY7QJD5TAKBFQHkvcm
b62Tyg/A2fvd72QX1c8VpsS1VM7eoKqg4UBkSwqwTr3lwqy6uSU7ihRpRli7nsTIJOWMO5Qw7sBn
9SgO5GD7utX1hxtCBu7+B8sQAOa9K+tfhnoT0ZRECA93rbkT1fTD4VOJ1qOrrylb0OhC9lEeEwCW
ov8wRmdsrAzJ3UG0c5lXbzo+FNmbshlKhy3hb+Vd1bkCeDnztQvVIoVyZkGo14omyj9Z+X/Dw0Ts
mO6WBbhk5NAm/SphPmki4tTvKsMBSzSYPr8ObLWKZj4ewcdGh3DYQW4Fx3Ihqc3lslg4vHuVYjHE
9toS9+GmH1zUn1TSkc/EUMZd93OXY6MxskT2oFzYs/2tB/QPfFSG7N27gQGvC201ki/9iANap9un
IZW11Gs0Q7JYI/PWt7heiUe3rHDzIYMZj81cvhrHZOAYi1bBcrDr2bzUDsU/RJQdctLPilHNWixi
bCCS53c8LmtDLVxKa3/sU2H453woM5Ck6yGLvDXfcGHUVjhTR0DapvOf5a9F4lpYWNXEBOOBuGA+
WUInB/DTDWA36s80ftnu4UEugva2IcNk0sq0wIpvcPFbNhA+U0jOPB8zflJvvvXnx45M7ijlXgG9
QTg80crbjJsVJnkreu4gbID2fvEJvly+pKnk6EPARINkVb6lBTMqpnl7+TQY/dSzEAE/q6XaOCvk
QATc3OLqNJUhDsi8WFftn8agioTTZiQNqg2UKMnKoJdbLUzhHT1K1P0HQp+uaMH3psF8ZOI29Ekw
V9bpQFGNKCeJv1JYJOhnnH2Ta9xcEhcwVEGx1Hp0iW8mZq5wP7GxeXmrOLXygmObPD1fFwkrEYuc
YoED5o/F3ckzaq8FRWWqxIW6u277vNPAK1rfuis0Xt+HwgZSSlnoqSA3cd/7wBGvuCgbhhgn4kNj
igNspxwTx6oJLkMt5sO6SjyBnWGbH+956dBcXraqSo6f7Gmve2Ox0ZZsJJiGU7ZTC4XZUxiJn4qv
yoiFO2b09YlP6iVIopBdUfcbwy3etz3C6D8/p2+sOoyOfCIRuxONJgk2kEDVwZOtQlVOl5d31rAG
nEardgxhkUmG8ukcNq2TUKyq4G3mepRTRaxvewwUybi0KO/QAvQ6IEKs/fEYTixRkjiPedYv0W7Q
0f3amjhhVyp+8ZFyjzWv7+RwpZhD7Y6ipkifsqdHoTUw51cnNoTQUqh/AqPU/VRvlbB8Liw6VsTs
9SCSI27dgEjNEkj2sM+GFaDIAESN+HvtefKdPV9zCzcbRrGL1XpvPJjlVy8fHf7+YGsecNtsurCP
J3amGoe2BonxHjaB4hIY00HVeYVjC0gcESTOfaMj4W6SGcw1jGOc4M89NyKi3GdW9bNaWFahbKaA
AxqaRJ2eg1s5PulaLVmHTxHWSXZ+k8S2fpO7DsqbToB1KBxHHSSRTrfYDIgZJeXZKQ8HsBMO8JVF
1CcANxsgFG41DfL3saTD0oUDn+OG4HIyq7ijv99IctiTkAHo8jfPwaQrPmcFp/BlFfIxUj0Ytcwc
UesIJPR/TYXm2aQY9hlQLzgERQNJniUQDSqxpk2y/wf3Rwvnne8j9LtVLhgNU3ZoK6EHcXaQ5Rf8
JSNdV+3LR+pte/Jy0gTdQSbE66LXEZFWqHfnwBCgCX5VrzAadtcpg4CGbH+j84K2eusDR+cLxeF7
vIFbEvPqqxyURoLwn1lL2u37cffJuQF3Ejjte7m2K/UhP0AjVkjro88OdUVFgQACxrOJJcT/P4rc
+0HIvHtBQiKo61sO68Mi0kaeJ3MdUA8JUV9A6byAe1gBcaYybGEZgQ5Pj37iazQ074wrWLk9xbDm
p38xAZtEqF0up2z5tRQjNo9PzKcS/mv2fWwYvASTet1CmZe9/buBOlGwjlJ6jnc0T6myHxHBbV2v
zspDLfP04u/6KXLFb7ZR4AERsYj5g0QUZ1ctObLD2t9/rQqlOk9jXxLYxL23SYRh+ils4+IDpIhR
d0WOboiEuDyB3Pza+y3YVCFG+cW3xjP9Gh2AnEtKurCaESmteIFb3ZVOAFcLl+t8w5Cmu8dyXbQz
rBxFkSRE62/4Y0+KRlSqOy5PYpFUdXG5GTUgP2uF8tqoCLdXFrbKTxVRf5UPCOLyA/IYzhaRdMLV
js/Q7unwuCu1ydoIa+n+gTvfj8VbPHV/qb7tkuDGquafBQoXS1JBMc5LsZg+iiEWp7Z0FEuIw6kv
14so29HkP4lQQqwbtNS8qygzgWGqNEyapCsCRpz/8KnYeDTDtaQ+56SM7QF/3YxZTn6mayTw7FoA
32oIpP0RvME7hfvXmqX+JzntVMsyiFdTczUQnJSKdCOw0CEvtg1KqkSRZB0gxowB0NEb9O+VcxAQ
RdjixFLuFHW3/g0U9WZDKxMCI55hegVkNL7Gj0PEPcH6H2L3GC5i5P3E8+bnUkSBmOfv0yQgmPwb
E18UNK5eDEPzyQOi5b7V73jRjkmIXiZbBz5b+jTG5v5lImW3tcA1rOrkcRwoSrUwedtXrljFvzus
fsY+52R2LMVyqH8+Hd5pxxodKI/PvetYYY/4VCVv6dZgT470CPI4ZzCJtgs2Sjsq8fe4tU3ajHWJ
vtyXYmDXzLvsHJvLICuQRWJksxNcnZ86aK5BMZEiPXAYwpLMPVkDhf0+tpSyYHU8fT7K4qHTkOzm
j1Sx+HlBKoCIcnyC0FQuLCNXmoGJBPzG1z1GPHPoKlVr4D6NbxAaKQaDS5e0tQN40KTi5Byt6H/v
FY01Qve3jDRWumgxIkMKOnab4QOXd6mnNFUkCZoqvn4SOjVV/o/kZf7+N0niu18J/dM1B4wD/FHf
edCK1194NtQeSnWZ59oekOVgJAVLpRu6P3Bo6Jchsz5PWkZlpf/j3wOKa3tQdy5nJaJFo/kmSQ5h
gLCnytYgz8apl5CiQ8N8tPYDDYqzYNx2tHA/xOQ7IFlVgMLifBBJrg248BMMPPO+UDvvpJib3LnO
9OwOgtnocpGYA6L42iAcBwpY9nJ/HWSte8tAI0PzOg68EHOg2LinvL9TPGY05bvAuHyqT+6YRXAg
yyVs4RUXyBY8wlYpiJ88oMqM04IdQavkzm7oiag4qWZZgperY/3zw7tBikllJt4bYkvYJ8I8seLC
hOkCfIrIcZcR7Ua2n6NZDSyPbZv+l7JUcRrl9SwSi8vQ7XBuJs17rMIhsdsPY8jqhBWlfL7gMYLg
r/JC1mX9gG122iUICyc0DWdtHqlW9R8s5f9nMF6av/VlRrNElfizAkexTfyGj8bRH3Sg41ZENs8L
FdZVH3dEUY7mLNVlncQDFu7dd2i/uw++y7qV/YBWASB6P+Smd6aiq1MrvvgFZRmGAXSVs4KPhyDo
w6/2JOmH2PHYhTzIiWAhrXBecm60nS516DHogWVGD33IRSVd0yoC0ar90nalNhWC6+wDq4Q0x83h
cKpD7RbfvtvEO4RNGywp1202y8KBbWTF0FEkiqNvcM7oQUTYXWJsjV9h48lCrJcJ7SFzutLoAHXR
MHKk1qjiHBZb3Q0hapvqXIXkCWkkdhpadzxriK8tRp5RFJf798agfEtKEjqtxZR8rPGPyRKmt2XO
jjyV2iQqqkdjBaybtQ91yX400H7LNcNmIOmyGYhJ7j3u7LjM+PH6as+nEIgoUzu1V7/ALXP+ZlIC
pJdn6R7SlOp9D0iYNcDWea/i4xjy+qggwy2KvIqB58CG679jAn0/Ow7Xy3AUHg+V2P0NCTtadYbh
9sT8aq+xlsSJ71vsx/x0M404Mj/FRAcjXPhf/JD7TOfQngK1bi8jCgfkrcwPuFgYpJWcFEIKXFmK
LuHwpCJoeWwQ4/7nvNBexPgASNfH8W9WbEzXzcEHDxkg+n3xP+nLcyv58J5PnXrBkdoQMuEmEu+9
k9J2gLeRt5Mw5vUwkaaCuZd8bFdrGbRd+Lrg9rlsH9JHSi89zKxUbQ5UMFBGgArYIPhhXzDrFFxr
uahzkJa91B5/6TNHTyUJz+6zIAwQvQLIrhiS6gXMz3v+NOIn+nnzhZcACPT7Dl4MdtyYxNIyg7wq
bfTP2Ed/h5+qgAT6Og5nd7aVM6ZjcLHN2S9G9fHUBuNPUKro9KE51BYOrovATBCvuWigeqtsD22Y
sWeNUzmZ9KnpHZTXC29x/9eY7JjKH6706gvoDU1eoNowZKqAqldYoPMGjRBkW5sV5/ym7rUI+9ME
iK14osXS3Vmgo7c7wkfA69cQ1rp3xjSvzStvLOTIB69VI68qbDWB+34kFEguEpkG1qQXKPyMGbYQ
vQJKVpuk2Ywxq0OqpQw9uD/N5k0Fmo3y2ohsD5oU/y/bBsCaZkiveFXDNMqajX+b831LV22Wgt8q
f9U68BSFU651Plq2aKmimD9Bbr3GEMSDrUkTQeFt5d3B1I5FegFs0tBM0Rk2bdOveh058GZ5pnep
m+jkj1l7RMt8yz2Qn2Y7gjbpEwS4uyY27AUaV+dA9iwxRscXboPTPNMjZuMLZwSe0njp2oysZ/+p
LziRh+83MyP2qdEoDTKApnQR/dLosTxcu20ddEk3KHAj9Z0I5qhlbOHN/CavrBUXF8PZ7HeyF6R+
/1Eq0D9QRVdr+SFqA9gbBnxLpxuJl8mXUERQtOwDEkSagQYJCg3nt9K7d4o+dymqcbn3mHvManPV
jOyVzyhWPecUA2Q/tEU4IA1oeEyr06JrR9HuSJ5LLQhWFRcZkhOFwN6JZ0M/r66caWVEZm3G5zyq
27AtAT/PHEOYVyD1wl/arnoUhHvCigKEIoEQ+89hVcx6bkTmjvpEqCzbydmWW/t8dvVCEVNPa9l3
+JtlEsGhomsjVn6CyNfRBSfDao+DUW/zfHthRZ+V9BNFTO0itwC6m8O+EymMTxo4Pi3lEs+9O7jw
7wJg6uq7hImhRmle/VwsIqW6N/N0DX2hUp8ijckYd7xmm7U/OVVBlP/LoQcWjPPmmCAZIiwfRYMG
8icpKDEios9A2NZ5topzi9isbVYD91ClePg+g8siv8K7sh3A3pcJ7djbKBJ2ibNfjG58wgWQI4CS
zcTLVRdhi2liykwHPwaAYnHfhUUBgCsUpre8csvk6KKuOKzyX//4Aqr0ituD8m7ChNHBpmfZcYGH
sdbfpigDKhWI8iONohdyDVVwN1xiABBmAk/XqZvkBhIvdECIpcPODu0EQ+0MU4gLw4sIY9MHrj/5
GaMf9xwNs/BT0CRgxYndlx3uwtOWWLhHPhaTBgxa+8ADzQ71r5PNzXPPKKGNl3g65+ZnsKkuvz39
ImjrHj0BDU9hZzuo5eY1DrDD9PWN3VUsm5SIo7YGpNWpojdWvAURW8tk8auOlRLVGyLRCLI24/7X
rIBKGlX6uJE86sm+aCGWXfJ1g3/ZCfgzrryWfuzm7MzpeyY0ocUSXYYJ8xO/DsHlqNr9L0YFuSx3
8gyzPI2A3fVNobdrMzpO6aZxSm+IpEN6cPgRNUmKuP/enObna0hsrQsxjRbPSd51Toc98+m4cs3D
wjafa23tvAY8HWEmbJYyNxgqsQRAEPC21tYZrPnsWS3ASLEHPVZizPapREUU+Vuamq2HkGhRNnwV
wu6CNOnE16aya/R9TFKA+/FhKc82OVZhBYalEoZuftt5bChHHCxNQJYV8J5lyZO//sKaoXoz5pHW
qnDkSFF/3e4YaM6JLtrKa2r3UFenwAKoPmmWQV+bqxpgO8Ss2THRGlWTQreoPjkWgwwlYWwhLchi
3WMOHREpJpJKXXcaG/yiTARBq01N4dp+JjZ6lGuoo9tbd6cudB13AzaGj9HTCW8eKuRdF3NzYPiV
A5qEBTu5J3cyoAXD9y7YxEt4ItqfANsRUF8KH7dQqmclqD4ZJaoORy/KCGb+UZHKWYg0eZZ+n6ZI
Nkh+FWNweXH6MAlYOcpu/xaS6b2W6sPA21Qq+QhE/9M0fw7DnNeS6Mj4H8S88EA3PcaNYenBuOnU
4mobMVcLyHkLvePtTJB5OzY4qvSd9FXDDWf76k1HZAvPeEK7TdApKwkrVBZJSYtYbvBRYk4BgAk1
JrJG2k1KtuwvoT5FnZjKTT6I0FWKGdmEg9TG7Lyr9l7C4lP2FM8MHTny0PnHoseHTixYneQ9Er1o
F3TqG29xkcB7aWWN4oxlFKk98IHzE2cesf6J8dJREwQlSoglIYBKWAXQd6s0IZImh5UXGn2m6e+I
lGI2uaSvb8fiYWZrp9xApcPf4xjarATDMmciPcXsnhIovk9oKP5bYM14DQe6eMRA1hmY1NCccrWg
slLKzoykQOMal/pM7YLVQDA0BOhUmQqMeMlmFK+6AYqwncWJG8H6W49ulhjVaJGfCuXWt4lUP4nJ
Qfs0sale6Bsen+EkcFuDhQniOW1jo6C8FjqcldZ+e8PzeQg8mH5fibb30Yw+RviRMmfHmgNspnV/
nmbPB1Z0DlRLo6pytyVMzppcQZtxXLw7urMklvAp6xTJDJyw3E0+r05BIKkSwkUpPw9RuFnLpW1C
YkrG1E+4orj7PKL95w7W0aQj7UKlJ5Aq6UPtYIQNNIZ+0VRCDb2on8hkS04S23hJQ5bRVufvtPJ0
l7A46sTcqKA5UqQn8XAgODX1wCKsGqd8rPzbtLsHOCMeXEzK03kXMgphfKHw2NVg0/UMR9XkdUKJ
AuVB52TAKjGE8aQPq4oUkzqXsI8kUz2prM14Xupq8P1X5WAopBqcRS7nZ2/VnccQzNxr4GRteGPz
LBDEWzAXZOBCHn8dtETHEkoggTt4Js3ZjNXMSBdIG139cIlRkhZSpiPd0rtLvJMTThfQnUMzkAAm
JVfbCA81xVDR/NO8CH3/Hxtdo+U7tmPBwD27vawmCsU21XSd+ZTDeKNdzWtRpL8o986F4yeZObkd
1T14kUaE9MQ72xhkg0tAOuxgzy24Bllke8GICm+OS/QjmDMpDW+Y8mlkvtT1cStZDtRmTAkNkeMT
CuX7GoYCCoJTvXGrI2/XJfz9JMoFr6aulpwAuckmFVoHEwH/kaknDAEi6QGZaVYfkvVGV4NXV8aC
rbaPzj05pCNjm/Tdc6Ag9fbJUY/tZ7K+7RUSUrvQezP6rQYkxxQz6wgpBVvSdl3yP8Mf4wj8A2af
ST+Nkv+3HFemdzXgewi/+c04FTLZ03sVmPNXf73QGr/qSf0pqsPpckMbAvB39kSfU8iYpp+QPNo6
mNfHA3FUN7+zEnH3S0AxFVaQIFrqewp1se01+KilrjJPQxkMiPLLibe27kbpQO6czw1nbqCq57sV
NEDpyLgW/OPzzoAcDWSZVotbCKaobmJx2VdBwXRh83JBdHtkYLlJTiDv2e437AsIRP7tgVLFf0oo
D4Kc6SX441Vm+W0127P40rggIl6ksGItJonMKCoxMv4Ky4DAy1Gm+c9HhVuCY9Z3sTDxf46Nuhs6
dDPJREijJZDKLN6H7nBg57fwh1lbiddGDO6VZpQeET2NrGbeRypPzc/irec/Hq+tY06RZkJNUfqS
kRojv586YfAlrSzRrIVO3W4uAQenYQ+ADJttViqw+B8bYbxYeWbqfmT6o9HYKW+uXYEO1u76xD18
c6yduJCAKL5fyeBN92GxIrbb1HmomB21LrVmCPB+qzEa6/TIUxUoVyleRJkMzPa31atFXxKKjrqb
70R4cFt0BrAAZ4J5OBs/TB2XwGo8mqMt9AAoijn1gAFs9Rr/QFIWb4bk6e8M6S+PhVcThulfVbg3
IYXrgyNYx4nWLRVbNGXcFQvFqC9osWDFr74QOo9uLxYRq3oFvl3e0MscsLVjyFGJqkNIpAOssK3l
mmR0ANjzYpPjV/0khqLuygxgAxPQGHeu9dHHGaq6sgW0GbCiDcHkB3ALLSonDejp/gu2wckAEqLe
Fgy40OwOwHHgfc2cnDMuWU2y7PsirkhxrDpwzSHQ9FVWo34tJJy9xycbfYTwBMPOF6HZM4BkJkLE
i4ct+LeZSqCuoBCyCq1wS8RJKsdlKoFYcGx5V3AgkTczc4gg6cgdOd3i51FC64AWdhD/5N4/MwzC
nsW37dY+5qiMBkCutNqoS1m3KwMeMuUN7oS7Oqw6k17f+oWrayCrOAqqcM/Czin0gBm1IlgNNytt
XdeVWonxMMvJzIc5Jcfe5lZOXclyqDoHgPDfWPuNqyfe/OtJrFcvQ7GA0GTVDJ5fbbpKyw7z9H+1
EGveBCbDDDwEDbQEO+kNNr9uP4bJpkVuEOYvpGfVSCykmoJZMdVtV9Lljrn4Szo80NtQNBE3+z++
yeJBUuhtrhsDft8QXl/JAYjUW7o/v5nWY83TNTKX61pO8TYCQvxtgQ5BsAKFlA0m9kDPdi50FUG6
vudSYb7NMfdrKgAy9JuqWit92lV3AFLxvjaUlFWdLr5kOqv4p6AyRHlFVfs+U24ca2AojVFPQNMd
M4qJPG0KWwUB48H8VjrVr/l/yEvkPASTU6lcwDr6faI+jHk0HVrBciSqcgonRXqvatyB9MmrtOjI
bNzqD62Oi9Dh2ZVEkWZqoI3LGBCLbzE0UNO8CwXX0LRyBmU6PtFiF3uCr4qs3A+qeIGhOriOM7RU
1HIUfzOGHu78o3nW03B5cZZVzSioKnbr5LlCepm7ChMwjbHiQdEFA5ZHBJfl6/nTVuy4KkKCk8Rd
/yo0AJcyuEf2BSQNriOGtNjjsYXPHU7D4enoWNpCPb1LHd3PfD4Lmz4X0OxarXYoK+WycDTe/0Ph
UUGKYVx03x4UsBKYT6W6jDuIi3gEgMPtJio7c+jvWJRk7DZ5Hhr83K166RVCaBhWYcnMfQVzJVPE
R99Nk4iizTPuky5ROof+MVk413ttfo/sC+cO5JuiZHk1I3hO9zSv0u2Nd4xF1wV+2FtVkqbs9iqF
mu4l0KPtqoAe73QzeFp4zRXLyLvaG63zhc+BKjNV+qbL5hfhdJ/a8bEwvV687bzmxxls4rYQR3a6
xVL2oPFQubA3peFkfNiV6SJf6RDQqD8D505seWEyf1nAqJqkkxlvNpV1z8JWWA6ij8clVmvwF56P
GZN4YGDVXGwYVtwaLtvK+EGsO11Oqdqu32dDojeaPy8FxOXBmRnIMj6Uzmv9EMZ77rzLjUOJYC1z
SYImAiYOaLesrTOrXcIZ4pn/GWx4mw2aVJQ9GF53jxiKXD4qI8DPYZZwb6kvZAW8U/OqPjcQtfuK
eUhyInh2aMwbfhbFnGMVBl5miwG7/YUhYg1q9ulLC7hyxHhIEJZaUOeb3VTazszF/MwqogcSVCIs
q9f0XwPtm0BpbD+ndmFQGVXM5iZGP424eUNy57uzfGlbktdCj3rcL5o5GuGZZ86egIcNjM35oJzz
oJL6wQTAgsDZmyssh7SwHjjueh/xpRfq2Q2ilA6D5gp/YJqUPgbb+0spCgJ2tUH25/ndsi3x0yeQ
IR042F2FILO9uC4U0Ju2oXFnuI9KBCeBNAQYTFk7FoUwM9eYeb3Rkt9r30+MMkx0F3d77Kb7IPYJ
ftCXTu74DScxMNQyI0WvWqJA6B6ZLZJ9TwqLTGlB+aIyoFNHDfC61LnkODhdLwatH1J5jbY7w81g
7PRoNXzsUl92hXQ4ehgTt6Sf2ua13A7Zjl1cCxMsj07M7DtuWI4bGDxhTyyrxlydUZYkJeelgKxz
AEZW2H+6dZZAENfIzGafyiYx1hr6vyZZ/tub1TCxcT8WgqZrnN2gh0f/0UEOLovjXMxHQiRwNFl/
1u3nJIWL+fbw1eBSdIHzdshaZPvEes4Dd56mRdIvAC1FYvAelbkdSV9tYRbYHCkEw4Ctqs5lMPJt
AcHbl1pZ2aa+FB45LiBw0qBAxOsnvXF3Ri3h8SGER8yIyqWbz2RJkPLvceYnAIQCo5Md9hQ8p4vV
qWBOCZr373jhUtG596J82IcnsfiGb87FariiKnGKJrb4Y5K+74XO4+l6zwPJh4jXV6scxm5DYVsf
JNYQZ1+vwjNGl0dAt30aed2WNtd7VT9oXALlV6FUbkp5X4tQG1lS4conDT4R6ER//3qbj+uPxsoh
PiScVQJY+siBXj5P9QXtGXguxUGKS58EsoT9NNBdPl3YweyrjhzBsPY0Di/DKFqLEqrNJ+a2Q3ix
xju7v68r4fBo0/3bj1ZkoVbMY8aUOklTpwfCWpfFmeUdWC5WPaLyf3DMXAY7i3Oy7pJLQIsbJo3z
Bm/ucLK8bcUBxrZ54virt/v9hEbhfjNb0ib/baJlN6lDoLbosyn4GCrs8wBBwuhzY7iy6QVeoy0j
NfNBsz0bFXrV1ZVMhKBVv9D9SrEypStE9qPoD2cbjRp2b7aLycCB2RQY5sjjvNsy0QDXR5eyBXlp
M2lWjAeBCJrcS/KC7hz6AjIOfrT4NfwndghXZj+c9BcRJM7wKYDpwKbNou44Yh1DwUtZQU5E7tWC
usIdtCdbMRirPYs3WCGzVsFGsG8ShhSjV/JGC401EA3c6EZa21Abj09Z1i5No5Re8NCy2R69hRb2
vu+XKLgFLus92QbdFhaUl/FYjZd/8BK6fVQ12Myz9Q1an4b1G2MJZiqSxTHtI+z3hnC9hp7C9SQi
Ix56/1YTphePuA6+vHs2KLXbac8CBnufd8nakwFCe3icQmsi7n1xDqjPu1PbcpmKIIg3F4UWuA9A
kiKKMXxQq8EYcv1ILGqTpRDMiFtAJkPgN8KWPt/s40GaVDvwHH1M2SkgGuclZDJJaMPwDeMNxGGI
ddb9FbmXosE0ml3/rfHf9PILgYrRxVW5hiz92CzsUUx+fFQ1YYof34a6wlpO7g8pqohILTWh+jxa
d4TKPZyy/LaRUEqwIqw/J+3URApJwtmb3RQIsKgMkeQwzQ4BwT92dFhGPKhcnnJyRR50Ge16wkdV
5qDc6fY0+1zsf7mHZ2ATgIujIgHi9uipmx+Aq5iXYMOljc2GtPxkTpcH58toibGpXYERXuNU+lp3
LJRhVB1bB9aKdKjGpeNllkLxIPc2IiGqf1G23uhfau+reWJ/84zYPFMZbeGQtrw3pQZ7oEnT+2kT
n6nYCTUWfr78SKpLOTcp2a8z6GcMlj1Ejb/jvGU9keT11SBSSKJxcy7tEO3azjmtENLhjo2Zop7l
bzIZ8We3yTqzxeNf0Wj+LnB5BcSEGbATOV55LgARZwIzKf+hMLO1ULG6Jv5LZI1r/IMbc5Q6f+m5
gA2JJoi1CJ7jdXRDSdnim23Kr8jqjU0NnyWE/4PION/VW+4xKDi4Dghm2fnZpGx0jtMkN+59uJuK
3Bnuh/y5d8V3MulB8JURhfgn3YYo5JjUlUuHXLOS9M/6KBs7IhGi7eQloudFLvmzVQjqKUK6Lh2M
5acA5/c4F3txCyPU/PECbuyU+tb9Gdu2Iztc8KgM/XWHbU0simk6fso4Ep8wZzeSAcRP5turNlmI
ngPpAPHPP+uYH0jyBLynVLw55Je2XUws5orP+wD18ilM2CUgSzn18IYQylz581sxZdcd6JY5275y
e/TnxMr+C7ZDsl2rfYExSISTCpepMhEbO5WHEeg7OqtLYtOsLNk2r04Jy/PuTUlzVKODZZT3JOvj
CWsQRU8U4RWQXaIn4T5aaVF2EzNDMda5/5W1ohgEzXX0QTLBk6kgd8spF8QZlwTOUT9LKFs7+J1Z
hCoQDqw2SweehUYlXAj3WMF4HNzsGD+XHBTM5LiDb32FUamBHU6KzC2DRnOg/KC9SNOfcRbRvgpv
BsTziqVg+rDYy13pNJJbsJWfpYC7HU1N5q1EeqySDcoKFah2IKhqiWwYPE7zBubeEK0ZDsMC/uT0
kmlUNw0st+03hmsbXX7m/CIHETGSe3Jw1S8c3kvgWC9w6JoGRe7QB8E+JCwICcvTpj+o4Cka4V54
elZFK/L+UnuF9TmiQAMhhqZbn6eCollF04wLzd2KSTxLWiTUK/6yu6c9R4uD7aXO1wdqqU5cOj3R
luaHDCjrdtdBF1BjJ76HFPbgNGl4QVnpjHyno1dXXlX4RVpOUZHre6uw2MEg1UIrBg4FJHcGiiAk
MJiqPnC494zgDxveLFM9QJdcadV/EXl8WUW8Y+Jq9HXw1Nz2E6vbssWHgQ73cEPLnh3tf619aPqC
3Ls6MogQiQtKjlfKTnqiv/UUwCaS7Gqdpp+U5NS3pN1uLaLCcLw7rJzD9wd0DS8nH/pL8CyNveek
OU+wv7DLJLHSGeAbPQJFFLoA0c6c8Cs53yl6B7stwOiSrK/q8jUzEF3zZ6IGNKjsIbnJdjMjZDKw
WQRCKLjB4QA84cWlFIxlBI92iOrvzU1zr26LmN7dpPgHbZAikmC0mWnGWAkbFNcek7WaJ/4IrGJI
zsvRjXCB96d9ZYN7StCKu0aEOcDJ5WiIlK+xFDfRqKu4zOTp7bXYsJFEhO1h8XcFy2J8EqB7YzjO
FDgbvz6n0MqmtRinlR88D+yqeHrsl2Skt0zXJPeUiubJUsFsVwEBFvfT60iClSuzo6FboMnfa/od
z1QUvRQttfvyBgswaOJVoQZRjHr0THva1+STE0mpKBZCRET/o7dlbT5jH3Aj7FRERrH2BkXot+wQ
GD9Mv4dqf7DTbVplFAHzBXOIIM/oPKC+N5hyTujVpdvxrbxr/qaJnlIQ35keZYfi8gasyF8WyfJb
oz4FbdfJ8ggwVIZ3w0kyt9TTTflnximZ19hk/+Q+1tXz1ISCuB324kXC/V9kH3ceXRzM88/s4M0g
zFaxL2zyHsSStt37uKvSHyFe27VtwPpnfmwozjY/6K31Ne414TEqnqxydEcmZkGJjfLqDN6KSvIt
b/HMZL3xQ3sa9jiglyAsmgjd2OFziosRSLrqNpS6dP4E4h7IU0Xb+OmlY6OwovLIcqZ4U71YmHZI
b5EMijih+LCic5ZETKmWVOL9nFKL7wO+Nxu2CkIInuLi6x6WnI5MlTlAgY0zpFEPHDUSjCsO1u/8
GMHJy+CvK/I21i1z6D66WU9o6XbM37WigAiVFb5ceuw3H/6eS1IFX64ZlA35CXADJP9syOo3idme
5ztWIxCqioCeiP/cbPYydclBO/930leYgOiUo4Y8as2A/NP9Px17oiShzyuY4zO83dveVSgQ5iRk
Oc5xxbgBdbA16prDTQQRwmlKYeBzYVA53antwwVAV5T93Vc+YrHNjjZQn4qMmouo8piGmCiYwCiv
Y3YwDrYNcn3GozWDbN9FmsFd+8jIBSRpP98ERuN0B5vxiEbl2mPB5z0IvDQab6v2l1Li1ODfIRcx
DRm8mC1h2oqwdYh2lmy21hx+sFJmsMlJJ5dg+SgCiWIiq6pr5bXqCBUnwUcFmB6MwY8u6R6z6tZd
7Xa6Enb2Je/ZD/7jpDe2Q2OSsJ19iwFCwMaJY02PfppLuWRKHANKJk5CDIKOKnmGepth3SIfhkOM
X4q/7tm27rTxuv9XVBMleS6+Snaki1022/QOwmeG9ZhVQaDh16QxXDvDtRPLtTpn7KdE+5wdUcb3
GaLRdK91ZCHSdi//ZFZUfOcCJCHd9a0mbmDIeqrkcLMajQk8007WpmVkrVljof5xHIGRc0DSmt56
oLRRAbTWHXq65LbgwnzAh4UshLtUDwY8uUe6xPyPb7SM4X3IqeeCajPi6xpUADG0pXUhx4vZDrwY
S3b28BRhaxTB5k+M+qJ8XDjWRT69kg+10pcGIG+ZlkQl7eQaZvc2a5OR6I4UISWKaoRh+K0mXm0X
wEPgBZFaotm+oa0kkDOaopkESx+mYP/vW+gyyVqJPhBmy5B9Oh3rqbVf7cD7JC1NqoGZYiQpD2KX
2QwTVnfHmtgX7laOnk9dsYGNUH/G0QRR6jxCkgmg488e2736gkWLR5/YPqMIQDhO6ofSNX/b7c34
Vsz0QNfXYj5hBCWIZzE44nT300wpzbiU8FGUC8k6DXF94grzjvAxlexogVakv22AwOg2yN+v6EgV
KBhYxSwcGZK5nWG4N8qbe/v2HBB0CV3ooIBT1k4RWIhI+6t3siacro0nTnm64KjG5bZnyZcvhFrQ
4ZNYnMwATQS6mbC0us4ZTuSKHjIkhqp1DVLZ/654ghkHX8sGByvNUHpKYVLMWuj5dOa0grr3iJeT
tzzFxz8zi5O6+3zTZdgxt4JZH9yGAhTRCZR3GNvwwrDRsZk621HjZ5Wt0RaoB9Lx5BeTfRH06mOZ
AuNWHLRwPS02XVMIu9Mjz7G4K38QUNoB4viA7OAS2y/guSeCNNqGR6BnVtDPzFqB6ByqNR3xSYaj
B93mSqqwbEsdEZigkCYB2exnqx9o5/+3fgrDa+ZUFbJ3xRHk/Ry0S9ptTStGCVRbidGOHMcIkufz
dR7CHK6Vwmxyu3KhfYqtdNQhYtbhc1LUYp+g3WVEu7fCTOzLRcHzOQUSkgulB0kTYbLB34e59o6e
9HHOjin7HkpJWp31aAhGfUNPCMi1E+PFpxy03X810YR89Ruo9ZNaAmx1p/e0HqVCocqr10pHX5LX
4cEwOc537P4QyWxbfi/FlApXF43kG/1typpYnqDGWXTokKNXkk5ESUaccJipGky+Ow6K5XOQ4dst
11KRQKHQs62NuEuUxZdSFLxqYqaGfTBiaW60LTXCOPrNAZoJQduMn07WzZwBeAyIJJpRL97EhnX3
IfzW8sf6eWj2FscwLGzBMo9LM5X4mRsUFpG8cZEGNwTvkzKgzQ7gMGLGgWacUj4LtloWNvhqvEEU
+fKA6qeAmBy26E8tlSffJ3zEju41GNBBjKBU8huEvWn5zYIpnYpcO7jfbfa8t1Jcfv1XbfTD1pWv
0zh2BjooZSyIHcoZDI4oMeTGR+8i2kFJKm/sDcVPIxPOKZKZ6QAPXmaaTiHhkBWaJUthTAYU5POK
Eyw2l+iHDzATOzQi3RYioeztLACmrKa7q0EE/ehTydjUAcipHNm/NOMWUB7/MqkwYVW48U4hCnjm
UFzhRjaDPoeVIFEUI7viGvlCBuuoES9LXb62/GoD5ahTvWua2UqkGDtohGVVV+MbDMNw1cJCtdo/
8L71CfHumRx0iE1FK8mI2hslkNZ3KpyP4p9XgowjE8Oy0DvrNQv1NW5OmvSA4PB1jCmshK6VMiaF
AV5pzc6ax+VAMs+la/8M3K2pijceMBC19+i8w/LRc7Tszz6TqtrQKg5Z/Nc7KJEm41z9GMgUjo96
30eXxdvm0DIm/IySJ3zBx2o+J8MdehMD8iJFWnEh+pmHjq9OtIveZfuNwLxLfSVakWtc1TF1LTsC
y41PST8/R9XR8IERbIxXfkpWgm7X5BRt5oHUq2zRlVuJqimohLNAhagD/hviJkGSGdNv49x4uO1p
Mr1NZ8fi9BfymgwXwURBm7vvPqctkx9jIkQsojUilFYNQKEPrlSASZiJM4XcE/PVQSrcBoR7EV98
ZM4+CFjuclF8Xaj8LLbZ1icbUCjDBhsoaHuLN8E6x7zfQhzLgMPgQT/osgkerPxtEKTtypjFsKtq
N8G3+uwBr1Ow12RJRw92L0RITRvk3iTIAtr7A35PDvznw2xlCWWRrB8q4/jbjuNrsouM83cgBGFX
vIKDWIScCR+jG1LASSc8kSfOjmGUYnU73t27X2OYIfsWSVIwVX9dXl+dwoXzwChT/DaRfzArdZZ0
lugSJd8YxYxb9WzkkS5LYihxTM7qP3LoDRwRD9E/wq8Ux9BuXccvb3DYUXn91hefCm+WnoYpD1Rd
3bJkHCvXGE1nSZg32O4BKFhQqx1sO8bVSe4ivaFw5tBXIHAh3GWcvDlb+XBWiGROIcnZC/rYCwQm
pXyiXV1DZDxbHTLb5JiYxduvv+YRrs45Kt6egMkZYKFEOBQpOGIP6bXgTZF8XlF3DmIDXZ7QyDFg
CLg/aAN3tCsJnFwDJu/Hql94houNLrZY+leQmWF2OjG0YbHqueHodUrEQr9BdBEJoaGt3Dck1Qnv
OMf22zPUTi3GBDDoTJEXDnrwVaPKnTKOEIFfRSkYih9bwRNgepnZX/gszoFM/+CWmPnquaGg39mQ
Ylr5creuhVjbONWJEFHjnSf8/iecu8ec2nGZ1Ij2H1/znOmfmkvoGn0vx3Sf1FCYDcC/BUalog+2
eXH5GSvfdD27J2GHZGxlVul+/fBHD2tfkEJsOliI/Lv33Ny7Zw0zWr2GctD6sTvJ8f09Tl5BAW51
1fcJhZFI9+8OAGx3UZb+ymH58/P3Z6h7CnmxhCCfHsWa4TPTGONuRr/TWqQnNF6UMS2GXLGBdWNA
KS+b36wEV0XxBSIyq6IfMyfTk87MNW3668ApIfXIg5XiBY8XIw14fkGYoiE6iu/6sG3ScsPDIdWj
/pV5630xhgdwHEN6ZMgwOnxBqd46dUDiP8Zc5sRvgCs5md12pxG2qeadwcqTiwNZyGMlB+PoMEGF
iZkkXd9SHXl7i51w+ZyMjETeXxapJkQDr/60z32tJ9JIAD6ZiRCsJVwVRaXcMn58/9jT1KXCjdus
qny8Xmu8wPoYFTVjqqmrheHwv0hQM/QE8Xe3LwKQvfbnGgepx13DP5aAXi/pswuOMHdcT78aN894
zSErRVBLk+V7tykvmnRGeaoPsudbkkzc1GpL+xUZZF/ysxbRP0/a58eDPITlNciuj9QWfxVCfdJ0
2OD/zgQxaOY6Gt7g2ZdYolDJklzgLnopWgIvejKyuJSaGSvRmEULd4aEhTb20BrXFJEdEsx2pQRr
nCW9CllMwuSYM9U6Z1xowyjgLX7m3eqDU7V1dFOP332lqzUVHR+5Rzd3JzcrSlusjj0ggfWOy3eI
VETiF7UMRouyQndDyJwQfpIfVqKVFhW7LKVObI9mO3igPk/J6oid6tdBQEebjqW+zOEKPaIC7DFO
zT7A/BdCJEArf0WeWOwgddyiNUCgKQVkoj2JCtQ9RxX8tJ2N3ATrAL4d+kOtOEdRI8AwchyWUxUn
zs2/c3FULbcmnbmxO5ny7ftdcybiVJPFXFVo/lTFKa4hUdzsNbTc6HzMws7gNyMcisR6zO+V9vFZ
SYO2J9YbP2qI96lcXWx/wVSyszcWYrXpnPqjrzmuB7jFMqPaGs+w2peGSCXXflYHssTM+iUmK8Ig
2UEYxRsDXRddOAxxS4AxLiESpZmbj7AzNfL6OXyxQf6j/dYHvEaa3n3QscpDrANkkQ66O3jfo9S1
UDqUEUDCql1V3fCY3Z0UdPwv4zdSqpZlOM0dtjdqkFvloTfQAtwLg92WHRoS0Fx2tIj9o8unYPfC
4y2Kn1KOWydjlcFuOXMzZguKjCkoQYUGsqxq9jSKafYMrq2hPx7UalXX8GVhhAWju/jDnP5zq8W0
4yn84xQYL8+mjK2LJLDw75/kW9hZTHTxPWrGoQeWg8WtzUvTaNT1fbw5csB96Ldmw4o85326rXum
jITAv+MuWJfCZu/C3cz0WINoAf77MiAX4/1zVr1KSLvbc2IlPvjzhwBW4TaTuBx6DvbqRyL6hfmo
iDHdtTLp07Mvuwx+Gfp8qHrPCxZiLVEmqNNbBf0SCpXt92ztpR4VxyMnpvfrS+m09zwFkwgZoRTk
Viqi3WrElC7r20nZUzr6lMqFslo0G4+d4axamZvdQDM1+R5+Ncn3n3yIwTHvsUB3iAHsAwQdd2Ll
ccwExU18iviSazqRjYKRLDSKkTEtkiDenPEBdgca4PUCBzoySy7rjCuKC3+VAaY4drOkdlssFynW
hwwE+nRbii3NooPCd3SbHXZYPrnia6HeIJpi2jE3sqJtEZjUyNaY1fJhrFxMLnv6dv/kLdsgFkHA
Hz2VZRCl6bby5cuBA6gAfxVecyAqP7AeYjrGyrM2GzGuuf41C0xTMpbiVnR1pAAQuLUAKDLdqOZT
pvBc3wUNEfa2KtPertlPf0hw4jFqiKRFXXBsROwHMAv0Gc+so8VaFFzpYy+A25i8aOPOsRlDUnL/
M3ftLl4GrL1wkFnmSAQTte3oQlXXyItREskaJBAvqPWDM++ozaiRTh0DKhYRKPIfeSsU+gJ8rUKc
pbqx0FjcqpG+YMfvpdXR9CXahFIcn372ovlplh1jVnFpnIinS1Ng63cYh9+EL9Vj5rwPk44qd/X2
j8ZDrzPU83Wec4V8b5grHjgOXDkVEqAKRk8mqUMYgW4LkGYM+ar5ieOonB6oWSKkET6DK+a+ZQ+Z
cUJH+WDiV4zwRHytBa9EmmpOwzqsoG/yR60YWdL92X4iLeL5tWDc5z6hNXIZgYq0l8tnbGaeKubl
bhSTRlcZhXU4jYWRw40dJe4sJclp0oNg04ywykqLuHxCf9urTd2bzQ1+4fYG0A2+roeuphp4BSqq
fyK+kcnZ7MhXvFsOxHqkSkjYv0SUNwqsDJKw9pOdG5gFLmqWoCVqEm8/hAFoypOWR2SPQoUnjpoJ
nf95S0Jpslg1Yv8GSJfZ1/H04904tbbhkZJ7qhegH7NL65+pQMTcrVNzKtSkTPmbMWv06A0t0Wph
pKC6ZzpE1/szR3Qjs013FhMq5aWEj1RCVDQjcry+zhTZ2hP90B89fSQmv6Wupu/Oyf5kenSd4e7Y
kuCQVTG7bByP/E2tP9OEvf4V0u5U4ENeah+aEKiCkUb/j+90TF2Qu529yWzFPglXKZrHtWpSEQCX
yeT/gprZvd2dq1I5W7sX7MfIJyTN8FGKs5CIi/z/OzhjLe/SHmmJu8HP32yBfMq7IsA4DVjALsE1
Iv5VY0YXb+Gn99zcBgyv2hy6jSNk5VyVoHn5As/vzX1HvfENG7Xu4KUcQltPF4BEzAEEX/HyZdKA
IMi639CRyXXISLnVVI6n5y2wxbVRFyP3neOWs7JRv8wPdrL1f7yi3xSSLOvROwG7n3V9wy2TKW1i
GoAXWWF0tMesItllPPh/Kik2skZalvC1/DodpPA8wOeJAvbUukOlFPNNZ0z6cGC1b8KpXKGWnvhp
GZflDCySaahTDhWowiwXPfn1aX5RNAbGPxe9eaitBTWi9rU4mcoddXSBfoKPBQ5+s3heRX5xMBut
0WNYK9lzTq2o0PSZN7xYc0eqT4TgqSG6u+GOb5R2mLz2A+/VfnbSVVaLH7SQBmVj/5/x3Pf9dBoz
MekY4nQ1QbnNmI6oxESsqDOuLRAvrU0MbUZPxxZxe0Aok8cFDqJ/Gv/R9jDGrHT9H2UGs6WaNXgj
WLneyKgOSiguYllqsduKf82/aekV8w1ejy/cYtSJzA9i9rM9bOTDGRcyiC4+zJYwHkxbCOaYqvzp
rFF23x8pQuscohUygB8jeSnc0KOgs0qUx9oX4B2cY5AlF+cCDnZkOc8yBfYNkbz493Z65VxpscH1
wyg4TzCjR41gavz+9AH6CyfielY/Tr34TXygQS8/JxnhvQ13q5SUKuyRXpBXoFeMCOUqTnW0B0SI
YwRwS54HACjx7fmIsLC6HzdPUhgIL88rt1hYHTjxaImaygBk/RlJselHwe7PCJslrAMP2tWFjgdi
Xq9EMfz0jTbjgEMxbsMb1pLd20AINhkm1tw5RXhaiRPVzSeBggLme2hF1prNqd23aPzroCM1Maqi
Upp+SaPIYPeYNGCUG1nEcZ6glWUJyPM29zmKzBn4WHL6czCT4HoNjJy6qyY5RlWkSGEnbgx0s7dB
+MddJ5FvdmEslk2lnJoPuVvYHFKZjjTzHls0LWQHq8kSraoK/VBcheMH9bupQ5mnhanO+2lCYpjI
G2xSJNEmVOvDiu2CteLh2bgScqPEuamu5C/uFlfyuNa8582l42RMndGwU+v1QOiTRCu7JPhHW5VU
9bj1ax7RCGYyare4YKYt+krQHm+J9NTmX8KAVCLwpM6Tg4zXQf2dsnhx4WKuU/Dpy1ZG5x9mnkNj
0qc+flzzZMXPz7bfzobJflAncjh05qV7fMSzm9FftgSPlhHxmKgkt9G4EkXTpgUf/CDZDwsI2yoT
M84xwzTVtZoOrFcNOvc/G5qIbf/Gy6dUiljPsLoJnsC0T6w4oOHA/4NtMPJOs0uqhq3xyx5ISrvi
MWuSvwYZzPnzi+9s268DXJdEvDqLzYaPF0A/XfUx73f6Bi45aS/pVqPqeS8plgPjKEnq5BSpa17C
+fnLE4lBubE8nFIOB/DBSKW/ic/zrruM575jBGY/sNqZThA5iQABznsRJl7zGcDWHtpyJaqg9pLZ
EiV6xt2qry7uJpaH6QBp1a7NXbWOquuFXJIPFVLnVWyaiQKhkQhK85vkdzZbbQJ85vV3ZFwSbQnb
HzLGZnv/RHjLQy3AjFWoKMeFr0KkQhPg5PUKuW6+qHba3xdotGZfC4KTjFy3lpO/H/D+uoBNt61G
RZ5TfGV+hGCzljk4++koFZ8+Z62oBKwOq684NbHxsHF34NATan8nm1q/K+WaQb1v1N3mfnPdHLq5
9JVrR2xqVudRLnpiCifE/4YSjg5XNsPdn7ucwooEIIh5ToDJJ8TXPZ7tix16hossBt/vIfTvG7iM
Y9ooC2aUxSBMYvdJMk4d/vJxlzhA6X5Z9y6SftlqJquu4eXmLRcoI2kiUa48r5fVjjztdkhIQUj1
NQ5y4TacaXbsQOWoVW0WO/jfDbU3Hag1UEgHZ8eF3x84BoDz3vfMAyVPNpc1pf8ODu7pYEOp+uJj
e5n2JZcw/J9VMijwM/J+GuLpIKhpzkg9PSyybONaanifvAuWE+1OKQWKehLutw+DxlYklLF34JHW
sJmCfvOBCHQCXPirj8knrRyqCluBYmd0HuWzYQlo+f4TCKKZWE+3rd9grdlWcafPNRTOjNUnitQ+
lM2muiSA9TvyT1U699UL0/9v3Ta122VGCNbsENDzkuQ6Ol7Yb0CKrjJC1f87bkoOhkef+oGMFKpw
/7AMH6x0kjZQ/mogRnNUaJgKY6GHR1AVC7T/ua2Z1z3lDQrBMyG+zl5Mew/Gd+evdsMTnphpnHE0
9Ma0BH7wEH7/Id0cuTwzGDymR8qUCQ+diU6xDw1TCrZ3Wfj2E+kzmN14UJdaQnDsv80ccAaXvgeA
n36uknYhNfWD6i4B+OKufjXM2pT866eA48TOtFrISEUx9DPjAv1bnDA5IXIhmI8EQ3Lzi7Xc/UmC
BkcgM+BnX/w0ToHBKp4ki+nrFcPXpljvVc/y2ExJb+i5gZvQDQD2ZrJ0gZtnGUyzWr3B0zVNa4zH
x2xveJ4x4aPS03wJS8l9FmcXdGHsCkL7lJu2Yh8uXGGlMk57Ble3q14J0U/0Z7fOg9wcE5CjJHCx
WIb4dauQO7K1erEzRc+MpBUfp2QPHbizWsPtmR7DjMZ3Lp8Lu1UsBe2h9kIyVJvbqLCVfPJQW9nG
+lwuLc7nuaM5F27wx7kU23XIk4l/YV3KNPhIt3Ww6Nc8UADaDKtavBgc6+InARrAa28hXkyFKxBV
wkr5S2Qp1TvbGkMQbfDBxFQ8ByuInVad4u7KGl/4lRMjL+tXrkJrJem4pss1wEsVF2KjSvPcSXGj
Mtkg1G6L3g3laPJFFvPAQREdYNWQwTzkFZ4QLm/cvVSRQTKOfBukrei5HxJt9Bh5ggt9Y4vhBuTp
zCnnrESghZO7Z9JwcHDWL0tXOiPi2v+ue1Ll16gOzmlkqaOoJcgExdXVIszRjvsGj2paZ+gmDucA
hoC6aeoMOD1btmEnUUNIgcx73SL8uRCvpWy19WQsggf8PB6prn5c0n8AzqOJMQ0fiB+hToAqeJKq
bMSPUX+OSfNF3mjQYAz6oTUucVfreIw83bvPb3E/UsRXqrHaocTLVTpFvCajNopwxLyrQTGYfSH1
UqiB5ZhllA4pRTCAbI8X09OuL9SlXS1s8M7xN/1ABSA64+i+ObWC4XK4fW6ID4NWR1r4VpaNZryd
Qw5JQMlRzGWH9/sM+o+tS0HrgYwdFGOV+ZECPxD4OFfEmZPeYWZMbQvEmKoCeM0eKT4Zd+C4b6iV
Z33ZyzljzHMosw8rzU8DPzj9GQXTdtyaGAruC3UdP3CbM7eD2FZl/wyBuiui6wGGVxX1HRCk3zV+
qMBRLlKsXnSpIWFatcWgV+WPFDTcpUA1+NXAKXGYsxKi+072M8NrntDs9UH6QcIoADHBTxkgLFgm
f9yRJD2rNepOtpGCp8I+0Z/LqbGJBeFfo0EBKF/pnc0yIkIw59X2HEzTRpgtyeNuJfd7oirbaFN+
VXXuiYef3aiQFz0lOzJ0khteiezsKR+KK2QzpG7pap440H3gz9RdrJt0YLfxiR8bZK/hXuzFzp8e
RnOSKlk23Xx5BwO5rYddfxpYqZK0dYrhZMpxMudKrLuSaUoJobPR36vCCoyNGvKSndDnIwPvRufw
ZXTj7jlm4JTw0WW/6d3HSvCaAKENljoLZ0lKtlCNfO40C/0OBdbiRu5X2lhBSoNcaoBXTQ+sAxDG
/z6M/jw8jhaNJfybcCAAgt6GAzTDOun1G1UzyizQqgV1iz0oQFL3u/p5ap9UCj4WuGgay+G9aZLs
/dY9J4cIS8wabcngVWfw+YlKln3cjTthkXVDkV1D4RdWuJGz8mWagiCxQlcR2mNipJal+XiYL5Sy
7OpcLUcIcvdjLsb8ZsiOs9/CXginvlmb4qTZgOMAs6CLm7tDk+BlUGyFN6m3k8QkhiB6HDX2ylv7
rcXDIm3GotthWcyruiNBQJO3a4er00CHN3ILPUKEpBlWjNtZjoxL19LWdwDOEBvgZQdEORvfbIC9
AQ/7rzh5HROmpbDXEFeEiN+ajCwPnIadS8KEOC4f3T4cs8ZvDjkYTs4NmqdB7ZBJAlm5ujC1st+M
OVAPqGNCmZqmxCU/o6DyCcTHEyW5aR2SW+xd6FiFnsmHamLestpQkInLg/9Hq3Qc1XTJWP7BqAM5
TDKIc1U2oom5hHTHfBC3YDWH3ngr5OG7QBFuXx63E546juohePtjF3G/Ja1aFf2OLAXB6j+3Be0V
4gIvA4TMkE3kLBe8SDQkEMpVEHaRKKYpBiAPNlboicIrlv7LEJW4nhLh0bMd2pKJMMbXSsQ3JTsl
CBxuhm0F42OtdegJFggU2VCR9RLlj69hVROlkiyZ9II5va2/+LJ97bjexuJz2bMpuBn8eSRYJ8Rn
hm00VxO7wFsZXwf7m2TyG90XoT7dS4wLfkoBfX2+xH9DuT4SKHLOizmjXryCM7XUgxE4PuXrDXek
2/XIK4Wap/9s92SPySN0LXHLigArauBbJmM8FOzQK11JNOmpY4wLaGdE42PDccdIGpdkMKRWdlQk
Exr4nomPRtlaqHVLox172x5cJGemjAHrXWSHlmHKuqBBKF1+ALmJHngsVHOEXJNaAOQCoz4lhBf1
Dv3zuyN11ku2ZciHrFUMwiUFSbO1KvgPuBk9NTdbQEVstFGcv1vLmHuZDerUk14IpxI5PWSR1qmi
rMMDsIKEX/PqMKic2mskj/dTybHhCApToBvdOS2eGieq4POyWN1laFBcNpbl1Ji5b0U8I0K6K6gm
b5xW5q+LL46pcRMc4L1nobqYkIMAyGxWAjhYmCxYW2ntMfPpTIMj0fk3VkcpXVOHv4UAjB1zs9g3
tiCts/KqXftcZJr2fsuO9JZhi1FECykHQwFyl0fp+HXe+Z2HTaNQJ6MLlHFfzdBuoVJcXZvP/aO7
4DmEzmizwnQCwJUgtHEnz8hJZqOuTKKLcZtAWBX1mR9Z8hdB4g/G2Asf8QrEVKSGRTBDf5Tp0KQF
8D3mr4ix1g5OosRLI8oxqs+8VIwP0tmvHNTS6w/qIckr2QftfnGlso1Dst29TQZkG/AGIsIL9mqd
EX0H4ZyNXndQbo/za7aWCNkWtr8uNQ6nFoQqdptzJDtAwA6fFkznyQmJuMml+5l6t64dBiNSX/Uo
7taUonh/UM/86W11o5k75T3uo5EpYcm7NP0wf+gWzMZcAaHum/uMa24Vl+3HrHQFIG1tX2TpnFar
ad/IgFdFfOY5NMWY1j+o36LH2CG9AYXOzYQ+cbWdF9kJHzt/W+/aFYAKTj68ZP2rA3GwkJjru6Hz
LMEQ1bEo5KvdgRiZFMSVzIgErJSO1QhzeBlL08jOw+5Qzers8+p4R1lBj00tViVPDmFo/01hEZeo
IvXRzNgOWMiVmiTTBQs9V+ynNOmmJnYZr9f3brkvWF+g81UIHy5vadj2vW2OdVMLO0Z2f5KkknX5
el9WtJQe4o4u44RQAvDUXaHWCRRpYxt/PE1IVnZKI62YmCliO+ByNfm6b4EW2ZieuqxOttkYQH11
P5Qf6Z86wb8FATKVS4BLegHLsXeONR+d1h7CZYI+/tVW23alQd4bm+aAZydPdcR8xNULYpu67VTt
mdsjPab0RtQNHQnuc1uoAaUuhQiYe27Cv4j8xHn3tqhDlE0W4m/7+WvfCJB1gIt2U9tVABj7jrnp
X67tgRYU4mt8vKPIwflnSNy0r2guU0I72ZRtlnKPeXgN5jGb1CJf0mMew62cCZpjJX3+Ir78z8Cb
0bDkW+v0RJnfskuwFsF2YRdEF3fMd8IyLP0ruYhSyriwnH1TYKLGbsr+nfOzwFPfxjJ6MVlf3rub
GlEaQljCV1v3kXXHEoJ8fQcD5Y/tEH/BjpAa5tEVg2cjX4Tc44FDOx0gIz4TdsjlCmK4UMAgPuSV
mDQWukY0CP1oKHPsYS9m/J73o32AllYsEW5/5afUgi1CUXObeAeETJe5pPTXU1fOSGZZ98V1fSbF
/ktpou6llFfsVIBjJKPO7s2gBDE+aZ1dEQ25IhK5Rv3cJSbbHCbjAchaQwZwuZ7OG+lWpYLnXZKo
R7+7SxqaRN3RF3m36mmhJLj7k1oNZjRsuM6P4ZHG8IETWK5wcYLp0JBxeS2ZlJ8z40K+1euqLugz
jvkQ1t3O6qU9phPnBvRF7HLM2x33SydJ9PkrzLK15Zgg2y2klfSDWCS7UfGLKvxqVLIo8RzJ8ghS
IJENDmon/0SZdWmZc8ixKBoJBRDKKuL0isvyddx619YbzQVq7K1A0g10RP+wFZomGUn1gN9BMmjz
XLPu6UeyV/wM5t3cByqWt5+iwyjQt0mAdSC6NMQQpLEc5agCFR8aBQdqTIkH5eum2zeA59+oXHb/
OGoEn6nX7nrvujcMLc8ey3+8gohdVuFr/TRWAt/xs7gXdIZop9B0nvHaeyUDka1i47R+TtN6fQOE
JiWqFC5rvBV7N537mfjHg5n/Lh4clqbRglS8hulFE6iUQBslI1jRXSjv8NJYYXuws6CAp85euxMG
umGEuHKhVSppbkfz8bOz5cH6I2SMbM+nwmex2+3cj2ObYJQrQpsGj4UA9d8WDAOQP1ABTrnVbOc5
qrJsCoyll/uz1ibrDiGZbxpMEvBovmClhiTuncj7RIQ7dE9cpSmy2iBU5E1WiGxFgogmP/PEH1f6
ZC5bbWj7pvxaU9f/36XaxPPYvC0L3QzpXeba7jMNZB+bqaCYrR66Dx6nNxisT2dlZS3SwosIooWJ
qiiQjjPabRahFDrmlR49im4MMKeH9F334mYHH6NL/flIjlNPJ4hgZf/Pkr5ltHMXVnp3sv/UTyX6
4Q+56h1mZA5Lfouy654CZXiE/wqMgqtACZ1X5Lk77Jfj5DntWrRRdTlFi70lHYlKlFnT4fKg0Lvx
lQnZzKpEwwQrATs8c4IztWB15LTAn/mQrNhZ0LLcUTNi5+SDuHYr//8yZlCn39OqkocLGcEdHt8+
E4H0DiN6V8bASNIny04kGnWBKlcAL38tuCZM4yvEthF21hjPeNNKEgMjVNCemrqx478EelMSea2a
fFjK1lwquFS0NQsgi8fQCMGe4eWlWJqhxPuU36wYx+x+f88sMsYZQiiBVGQoO8CBMpEmYqMnJDGj
EPGIRBJ8NIKiujNr5TgH+AMh4mY9KMZS7Ecq7Sh10MtTDicd9zz2WQdBmBIszvE9YjrNsXgv3+/j
VZ8K6DcXjItxcSZWC88vGbKp8Hefjmg6aLAN4B6SM20vP9rc+hlIS202CtthIKuDhMNxwEXipk8S
srv7smDTIuaJEc1Qfpyuo1zf9Z11BJm0zVkVy6p1kJwcY3sDW52p3PM26l+QO38JNyL+YWNKqlo1
QJF0/yMz0Yl096FmvG84EU4j9tqcsREw0HLrXQJSc9Sde90tpqckLmEManYL4n/oBvy/jU9sT3G8
plQITPuICMdrRGTF2CIKIiZ3c4g/ypnDoL1bsVfu53Qsry0WOfhA+MwiHcj9AQsFzSi9JEBKLmq2
VraZ526z6sexfw/vpI7t8p83dSyPX+FmyO3lTgIPZNowFX8SkPZxBQtLuyb0M/Vh9aZBhC6kdKax
cOW9E6GYw50YpOrhBPdNvKkXoKdxuOzmcXtJc8BKgP4PR5/md7fNUiQYfcbiRSbxXN8pw/IYPowf
T1l63JbYxQ0t4my11miIOpe2GgLWcEvgi521vsZnoZO4O5hxK0ZgvQm1TYeMEnQ7EbNfVN25RN0C
JFQjFbt/flCSJ4VUbbMdsimNARmsQ+Ue7x7BfZuS8zCMfadrshhViPqbT1K6NQPbUBRt8Z4iLDHg
IxHd0y0I3/vuKAdnTxHN1AxXUhgTuZzKKsbj9uxBgc2pG2F3UfXl+TgZN5ideya8otxx6ZAmDcIG
dKt175n4M8+PAfdM1PxHrFSykxttpy6IsR8GIVKpgUU+IQi7Pc40LRPuhg17VnNRD5Hh67CHh0j7
gat1JNsYVSjqzjn+oSlenklfEtgypjgBLEm4lfQBLxyE2RHDkBt0QAlcjaL6V6gbUfmRnfxGFyxY
AQPakmsscVPmaV1rr3+/oHH6fK55me8B/3Mi2z1KnDkUrrsyRBJ1ch4PNM1W46OkFyD0KBV6WAhA
jrWTvXXdeXQh3BZFFRVYFwHyCu3FD0g/SqQP2SC28GXVGCCGIncjrwdVpwspl8bqWk3EqoHc0of9
/3pZ268wlfRSCeT0UUPttrgjrAS6cb5Py08uBTQcuhz49LaDZeC78GxCuqmlVUHXUw6S54L8mwk2
75IHrDT2JfoEPjBVFC7xCGy9YZen0Tn858cXKStcZ7HpZ7Ntlg+QN7hfHKpuwq/LPE1M6Bv9x00E
A0j9qHgCZX02WaCBAsTazTKzawDysQZnRNm6KKz9cdDjfz3WhblK3cVrtWpmPjMv9T9aRBHtFVHC
KOhb+bqCMxTs/PHQbYwy83cMT1BZfZi0es2iqd84tExrGKWk8n55Tiyt+7tECNy4HqdikGi3Md9H
GjOSo5854KFdSHw1pWz4061Y022bljRuUMLQAGtwkwTy8e4VqFH4RpdJyAJObHhOsvNk/hdWd8dC
Qx29lyMm3RWTMo4zQHqsThrMkUDBd3NAZxvdblEnamtzdGA2vgesLuT5Gn/4iXvXetg53hrOBNEJ
g7q5dWDLqxqLtvEGkTmwQ+kp4OEqGscl9xLIkRYcMwLhlFlYUACZIccEW/c3rhINQA1EWuSy65ab
vG1HyfSZj7F7NrU7n4W+6DgBJuGx8ItqO27dtiKvu06OhPp50aYLTYx+cNG/iiph4Tw6epyXexfh
R6YjE+gu9EB+fwbLNEmCUDx7BtHuQmXb0YPbgyxMGlBNYKHrefNC9gy0ok0TcHvcRa8vLp8WFRrU
elJYMQF7Rp6gCGdentdrCo3erysCwVUiGcbC1sxP+p8Qx66lObiMrByKgLeEQCjc3N453gIZWpPm
PppucknSE7cJxZVSg6hcP99Q6iHKo/ais+Mi5YH7DYhxcF/nshCFZO9uWa/CdlOs4PEw/KDkQ8gK
yzoOxMey1BEjrDfNNNbvkrfioHMazqibmAvemZTFapGPZoyarxLrv19RTf4tQXepZew07Tv2WPtq
14xBkfQ3iC6yPPMQJ4zMtmuuPEz7CPMsm89bWPjYHUsMQL0XPm5NpxRYhPNr5PIlHN1tbWNNX4fK
WBo0HKNzBBtpCBHPflwABMZjlWYH8WQAycEG+3X8SuSOwYWwwZcx08W8Hrfxc3FgndixPujZhrMm
PDNX/WHJEt9jSGCO0PvqntiLdc8ISct4kUzpek0bWMIu4+LjoJHU0e8CDw0RX7bJ666hMUEUbvq1
u1TR/7gNmYIl+joK/d/rGdwJ1ifuJxzX6ZuzGOgIa+V4tAl0M1GWNv2qXNDPdIjKmG5pbDXdNXwm
dNEsTNSgPKhupTHtLonWguFHx19p59RWdixoroCdeMfZt4fBUR0RYOZ1dQVUqNcZi/HIq0/cGIMh
TNoL0xG93Es2bIPKttwznO0guk9/SJMM3qMaoS81rO882zs/8vCJrZrPq9hsMGcxWOAXzZd0b5Ae
TSMHdIqKPqtVAPlJRTS5MkeK//EQdP8vf7EOvBx2L3vakdKlNojR0vTpSgUDth5dGEWPWdiFOAk8
4lx/KPDzKF+Wus4V0KSXP4eV0mW1oUWc3eiGCCvnLXwO3I64g8I/lDgrjlTBxorm4q7xYRNequbc
sRa4hx0+1pl04/a7kmZ+zIMibcPUEd94IxXzkRvHAj1gmBpKBABJnRnE821Q02oxRJxYxMrKM3Bj
sHjhecpvoYE2DqxoAxaTL2EXnrhsbrWZEsFILAxj3TeytudKnILs3hdYMsNS8WM9/oEqJ8PVTSBn
ITq29GZGw2GAtAPMaYU7941hGwwKOc81NgmwTTCLxu5t5K+1JGzymuUCoJusf+dVqB0lx3VSZn03
/6bfd7luxct/15w73ZX9fJO6Pi87cdo3s1BDQw4gwkq1gDBSq9sczhg+XNACEKjknieYxTYZN0Yx
AhpOovTAAQEJdg0vfYRVdbUAzibxhlH+k3P6oTkWZRnCyaTq0FFFZ8pEgVE0Y/ev1oXxfATdY4WW
k6xxNtbMbcsHOl59Lj8bDV4DomCCVJZy9hcyJRlPwmDvTAtA5eOrgMrprsxw93dRCgNUe/YkPUsC
SC7K+i1QGSQMdLW+mrq4JANHzBIacwcpNdVpazSgTJ7j6M+BANwJwQOfC7+bU1+XECoz65uqID6D
pLLaOlprtvv9YtG/yTxV4RxtuoJqJWEOE3IhOeQHczQ5ndYhgltU0/dPdpNyYwg2K+2eM/g8BJxZ
0erdJ7TdUVykRhCt+wlUiu7p83m4lcVraGx1DX9A1RrU4jxELHcOCEc0wRxuN/lEB1VABfkVShgh
uzJRUTjuedMxemmUfKv2eOpYVg1/eEjD08AWqgmRlhUFlKGwpRoG7hfpgVHWLu7Afq8AL93nm7x+
j/Sc7YgwDCdfGz6AZVoUa3UdJyeWQvRtUvhJALhUW3GsMVjEpzsUeggwZEmMrYIGEAK/H/vYBFYR
oVL4M7kbsPBtBcCJ0l6zUa/+iojjsQsF1sJKzg148EpNjO+QYFzBp61lnYwpMpt/W7mj0lxar1XE
yzIV8cPnObgUTbfFWoyaLLeZtgQcjncHBd73clFvyvHyHcnMjiAxEABLKRinamjjc5DnKEngiAmt
ictd1WNhJkxwj+B9mFH0uMJhuuzUJX4EoFMngNjrwQufAfu5AxJ65mrKRZaHauVgD6ugCtC7MDG5
5tIoLokUlJdfJDaAY1AA7qRLgKcp0hfhBVJSsE8zA+GGVPyQk0BfaEdEy+PDazPHILXIanxuHMB3
i71Yo9pQm/Wv1mjF+Dmgx/iD+JNY7aLQXa9ASBC2XjF1zwf83ZCMzStI2sYAKhPQmtq+zpDNnC5U
TD+fezYNx8vMZZ4xZCTc05YEYLv2rzZmgKMU3y+9oPWd32KhnCX6gE0hpLle2Z6Ylpi4qHre0S+N
xdGTBbEshwZWTDzBVHhqqiKVX6TOYMaoFn8Xqk9OAekczV7jXvECQngwcJWxtwcrd89Tad1dYdQt
4/9ZngDkzpTMTgPN5Yxa/h0BM8mo+aIZw4IJNj7mvBX2+3NhyICqB9ML4XGwoIg8pbV1VqkKe02d
QwC7k9z0Bhh+y9KpVF1pHCqRcMDoSuFORXfwk5fK/b+XAhyS+VWsQXQByv2FN68SEiJfsc9TyEof
ETW7QsT48qnO5E6iYoh05A/jXLFojJx86X43MD3N4dFikhyFTg0Et63yKrDPb3X9AXoWWYE15jhX
5UHELi9q4yqSPry8aAeZsuxBwHaULDvVczckx4aYBXrN6Sgbu/MhzD+VHvLin2gbGfjSk2IhqT3Q
LkhKn18mceqahJdq7Yw9LrDVwUzGg50VvDMo/t7QIvta5mg+K25rcY/uuTN/866YKTEJu6bp82En
coodjf9GvdqihfotU6OqfSAELwKfml7bizPTWMgh/b2aI1NHDNROp+IS9Obx3Q/KfIMOqGUCPPrr
cvcid2+zIw1mVKkJ9ZN4O7luZDS5rQ61UXF1pQWaYfzN5cx4DQprqhGCU26+AAlOKGsKCUZPivWR
GG0kGCnVn6uRR1CQk1H1EsfYXj7AirsAnO/LmepC73mkalFxSgFzOsK5h6vj58q/qKN4DwvYlfgp
G4dktOlvb8nPbepZpKmaCLDFlAxFCf2dVPmneQlJLcR32H06H5fYznJrPuBmslciN3EnjcRzU5J3
Ewbk7ei1qZC/KbkPg0qbyATM4VvEtVDrwvCsBKQdPpWMPYa4xSAqoL7kXmw1pIyn3vBkbUIuK+z0
8wXYD56c+i71lEfUPYEPJBz3UKA+W+gRlMwKl7gVvB1QERJCbN9IvTTDMYladbfTxldomNtgR3Sh
gKVHuneoz+OY7y9TFVwYQZR/a9vzHMDkaa5r7PLUOGjEyaWXrzcs0TAVwyUxX5ck+1sDeaE2TQF0
MRm2l8h8KtYRST+4tuWbRNgF5ArJYez8T/rFvKVSQ8KtAn9vGVv5CXnnT8B6VUnlpL+WqxZXy4EQ
fSm+gK4SjFoDNBEYakor3hEep0f/voQFilUIHaAdsBrNPke4L5ekGu5Z9Ud6eo4Z1hK1fpJCjMOK
FgTObyLbGCIeaWvhI5dT/hyQGEO0/vuX8uXSgVozUs+IJGJ22F9EzaFtsL4h3sh5KHQxOqv3PkuT
ywzeJIZd90rfoO60LMKgiyrGUQ9jAuhpLjYOD0CYmcDu4PFFEAqcdBTvIhoXsRC2sMf//83UX1oB
xvWAA31aEYHVb3lYCgE85hIvt8X/hD1JDjR9le3+VcSE+1wOY/3OuGuWy5/ggXuG1yzlGnQD2hw1
O6U8toiK3Mzwl/72cfS1rjyV8JwJWO+mjulzj6GDLEWBGL+EoR0rnyrtEtVwH0gY+/ifZjG/xdbI
3WOKv91WR8nmdrSS9+1qDwe7jBVCvzzSN4zO+gK9GLjYO63LeeOrSuqfAIIyMUjxrrAwLGIYFxHF
2e3dQMWIW/kG71wO48lILnimyHhzpmZE+gCIWFdskGqpXhpWZFw+ogBqHk5oMqpiVqL7Iu5pyzbg
beXvQy2EWj9QeDvpKRbmrwOM5yTzoOLlugCUnIeuupia+KSQcDFv3t1XQaFqfIZVspJhnVvlhz+d
pqL+QgPlUYubKny7Pf0rz+C5CJUQsgXjlnbtV/veHknWhLaZreSZDZ5R1QRfnZ4OOdOfFr6Fbi9A
rQcCyHYHkYR91khntE71ULDY/hUlkRHlQ6bF2fGNXi9R3uMWGFwiqlDl3Iihipq5nhtD+/08JYwU
trha8EuL5Tf7TYouAEhXTUdkReD0WaBfk3aAHuSh/6qXfEILYyfBbTx4Bwe6E0RQjL2O+usUY7om
mx8z7lUrIOz+S7maXoRk10Fmt/MikxC+/aNlgha446If8vV/iKBptnuBjnm8be6E2Ate65ap+4gh
2fGtmM5IOK48rgQFP3WIQz40/dywDVyQmvAn7SzF/r8ZLzaqxOarGCL1B0nsIV2LnrESMI1k+y8o
bYO3d8Lsabm0nxn26ln85Ts93Yl+x0bfy+qxjoR51qxbIST0a9tzdKb/ZKbieLViZ6LisbGsM6CO
iwm+gGfggljT/NiZh6xgEj0r0c8lqE81efnWNzJw9lgDj8HLSt0XjCf7dVr3apYT6yuhho9XMR77
bX5ojp++OYrEolYDmZ8oliL0s83vvduoqzOZ2bNfUdg4aOJTvSqkHn4TCA5q8CZA5JepTUhi8gAe
Mh2h2s4iHPssPb6h6hC6e5CjdfVuTLlyGX7kOtko6OZzLT7eYUOLZSm4ft+5K7o50cbXjJD4Lgdg
l/Ben3+Ays3pLKI7UvgxB8/4VAuiwrxhnzE2zG2lgQYZMlYZbSQE/CN5f9NKMpvlzuMK+R0jAau6
JnzPKTlFjM7pNv7VdtAxMXFXa6TH10DSG49D+tR1AueUDVv9hx2xD8Gfji7gcxIX1GrqjMaUxXWf
Kcd/lwHJ2J8/UGXCykA1IC5g5/Pv6TG5IZdTEQXPtE587natpQ3ec0391y7Q2CA92gGMY/UyuSL8
hyJK6rLJCLfDDQVFsH50HZyOBFDjJcsemS9ga3c3I8gEbekuSsKMLcgJCRraSRJf6tU0KdFEb1+s
6t4TeASJUnvafSIYTzJ8wXn0lYKEgVusurwJ54QIWf83v2iZOb1RsbuuuAvQw6pQOtxMhntjSW5w
PS9KSwD3SGcp4jkKJ/SNrRsOXLRTVi76VhquTRATDBDYhSKQhlX5RWsG83MRM5jMp0hhQrVQZfuN
Ko+1AuDPyrvdX8AYNh7+h8Fwm+cp3EWQjEgl8QSyJJ8m+x1xrN2bIvvsGwvcyR9CrWdgXcgXOnoI
M/Pi0yIVCjU/cNcwAOBgU/7bLqAt6seOV2ZcFL2mvkiuiIxLx+eG7LcaGjz+Kbgvoma1MJQ88Z93
Ruq1PqgKpKIbWCz6S+jDXQgnYkf0VmwwvJpa9Fau94W6Sf5K9gzjl9g6wv6t7u6VFop2VjVqDZPF
P8/IdOYQCNINWGa802fwky1H5nO/DqyOIRntxMSCCPW9PShQwhBMN06qZVx4SiHZs8O4Q9CEkrZ6
KyrIMqjhCzoS3Mn3MOOx2gF4GB/g5z8c4IHwL+fRlTfjJjBRyawjLE7wRxXhCyzTAHii33L6Cx1C
jVXymvmbYQV1TOl6yLxFjdI++RLLS1Cd0exXGNpryfZ6k9CjzvgJXExojFENJbXMe9ohacQ/UChb
PlwNTa9MxDRASfv2NrAaXmhW1ipmn7e7lOYRH7O9c4M3zZDgxgYMyA9dw474eD0rsSAIXXnLT3g+
nuL5q+g9f9HWbhBDBKJVFjUJcxQ0e3+jm4KM2+QDJ2OB/6yx9dzUVMObNDY9Q1RjwPxir0uNvHa5
Rf88V9wyf451aZUxlpmmXm5Sk3SvVzzpTWTGVdtzi7wWBkAk+C+Zh4R1VqrhRlVgyzexP8gtvRlC
TTc5+hVVja+VFCqyBN5NXNuk+SGZL6Ra9vsLe9aVTpJGH1yOAEMnA3D3+G5NbpkQm8yjtcdWJw0Z
AyQTCZZcdgNCIBvz64VZQpF8Waz1Tpp45VJxadxF3oe9pbO0YfUcAi+gwX7n/G4xdXkTvAn+y48M
qJNpj688QLaHntVu7lTgo6SdfRMxiEZqdTvjS7NMgoS0XYXaR3H3Dtr3VuSJu0cGTvIzDElvJSgo
mF5BHeICeoTEcdGdRx4AtTJ5HyxBziG3RqcE4ojzaMZhyREqELT/Q+0ZtezEEqJLXLomMIuTiHWn
Zatzx87I13RXc+txcTFV5vWTsWSTLZPW5bFNklDAIrA8uM4/5rM+GfJyylBk2aDQdB2Q1hUjPTmx
mm0mv02HFDauPszqBnc3XKAOgGknOMh1tkt+H7Wp5X/wsVaZ8R3/2rCx+OpYfplYxzxsiptLILXT
qNw/mygHWzaE5sOFYsuNLpULIiEICRLeaCflkiMXZc6raaF6mptqnKUiapE5m4R4TktLavQjVAYn
VJv33eZWvrj7Nk24xH7cNqgmagvydJvf2MNmYhd++95CgPGbV/+cFu/rjJpiGMAFIZOh5dALj+F1
tPXiXViX68lnbyyU2nB9uzGM3CUvKKuF4VooEIk4u0f9NeUB9rCdJQTCr52e0b6VE1zgR+Hxm4vy
ObcPRpwLAhi/uJe2Blmj6mqoOkP3IBNEunpvgyjYWNEhX1aBz8mdlj0yvPKRauCmlWTY5YBybU/o
SbddzQDX1nLf0ZwF1Jiny9n6DMgde2WQxOXwUYp/ETsMvQ3M5DeykYvq+vJ/bG2ZyjpxgHuxW8Lr
kR2Tz2docyrOcvveqO44ekkbkkA0uGg4D8arjIL2B3xCQmrUVC+i991dC8gIemj594hlusRW/ZHz
tSaL22np3bWQ3gYWS8zcU63znq62hN6z8a5XoN+W3DUUk7bfRHvcKywvT015+SfGRxW1y5lu+kV7
wV3XNUbNVFUNVsfCVICranWv0gg61GL8tQ7Bso/+wl7VfZRs3V7lzhD//0hHem/0xyqnOFvdZ8P2
99L0iU3h7lKFhksfvEbyFD3P5ACGLV6K/Xv9W1tqPKoM4UIDNHxsh1Vsl+ltRgUhwH0l+GUGzZ7t
FUiKR7pMM+Viv3dNY/JETLr2AyQuKzrRWEpuJIMBpETm6yl6XllKpSt+akz2OIyuIFUmYzs1oZn7
MQJR+dRHHullFGJDkMSxuR3tkNkWVJdvm1jWckbv1Yqb6U5jmm+WyCCfTSnA+T/KsEQq86u3PxkO
0ZbOi/W3rtVhxlkx8eZ6/Im226//XtIpABDUuUm2yMZnGcs8VG8jCVQFCIXOfXkW+fhRnc5ATiJg
GIJBKRdS6eqY7za6saWpUrEG1ZwBwhd1Hu1qFsZ3Oq4xxEPAuVF8xxPUL6oHu2utEYsnD/kB+rva
db9Q7IEb+nmyYpHnoAnez2g+WFYLS7YIHeQNhjZtBn550hQ4jGbHhpioDz/lXTTf0OHg6POeMp6Y
bNqxOcNdq0JDNZi9KMULnEMq8vPRr3CiFpBIs1Dc0rxOCyFkYXWqFQF5GSlKE6Ea56sUiAbjBVg4
ggQ60QlkHxZShbLXVGynBYdK2nWxHyZSnDAhSAxd/Uok1xAhwrzkMVJur+OCfZ+lONdXn2xIuRIJ
30BOKdjljy3S+KmvHFJ5Kcce4q6pLA910rX4Ck/8V44kzqsW/DilN5SHri+XGFyXeIffp3ytwwPj
pFO7M3r+rJ/hl9jT0T3hsG49EmK7iHPGnHXOsifoDXgrUxLSk5WpB1Mwv+5iXIf7K5kmYqVaD8Cl
ys2fUvumaCrLAHkRmm91fvHqbSrquJ3pHKobJBO09BEg6GOC3cMIk00+W+LYSxpJXunG4LDwOSxc
yS0q1SxBS/iMoUW52gYJWeqOUSgSXCRjILDVF0gIeQpp4cJxim7a9QtY+sqUNrLVIPt8NZDcHosT
GAUcGTtGOpVa/LErNn2PgN7yUNvsGbH25FHzw03cYbjhas7Jll8oqn3ONT/65AiZGR0mXQrAP1/f
LMLl/y5LbhIgi5tsNi7GEJilaoYh7ngnbynnW+fSMLRL8xg/0eZaVX7cwnjfXjjt5Ckdh7ALBc2i
aPCQIqilUR5SwebxF943RfyZkhtAe2MX5ngz7/V/HDSDUs9PdpmFjxu3BccL+HcajVXR93nWmG3n
u9v4I+HndVkEYhJnDoJh0kif1uVTKUmBJXf7GiFxmZsp3NfrvvfnMr8G5atgj3lF1D9xhEcM2e4G
fNK/4BdA+o4wsBtm5HCyaz7OVPCirGkI5I51OAZ4TMef3AwWfhRzPQzPteOakzibL4ZaUrFEDXrU
fpkj/qmZiXc4w7fmNahhEfOR0UryFCSwSiLyiiKZnCSiU8XxDgLB5PosOrQtpOMgaaFHAlSty5oX
je9+zXpaAnSEVkT7xUUEEAW/ipiwd/Gt3ABx49TibFr6RiI0O0n7r7XNC8EyyXRqDFWE98zy4s5b
LrmCdyv7Q7KiEXo7a+Ko9tpNN2GJ1kW9LJ2xzo8refh4l4HKYUxCOJW2rXh13vaTrDLAhE+lYo5o
ijVAvfxpjVub6YEd4vkm2szpG7TOj9luDUbFVVOTJ7R4TFT/NQi+lvETriDyg7UoOA/XdWa7hsYI
rRp2iqjfSMMfDx+1RmBquRPIOL/mCUDKnUIACNJTHLafdOT8nk7DrEe3M248E5/B4hj41i6yr/cg
QOYFDIrq8ZpWQ2ky/ZJrv1B8dwEl3rHYVHaZ1OUT6jlxwkNsCcpDkNhY7tpRXTC6RxQNjGIfTZ/p
7uh584w5qVTa627XUsdSacNvWQwQcFR43VjK+Q6lDV5CN6vJaQaTkLj1LA9g9y+c089H/ddeAUQY
7/v7nyoIsI3is3GwaHxx9Aln65EXUZJu57kxI99U70L0Unbf3YA6+FZhfEuL5VXy+/iUTJMbzgKD
VlDI6YjK3S0RhNuLdzYFJoKBCqLkNKjI9rpSqDVw0ie/TMMmu3rmeTUogE7E4jiVdwKlCYc0GC9g
C+9G6S1WLVtgP8Bm04+/EhDX4JU9uFQ/O0c+llU6DE19/TMsAqMSKiGrKaN2yJdzQNMcp6yvT8jo
eU8XzcBlfm7VMF9Tn37UI6gdphToKhvyJcOxz7S+CDd+Q9aHwA7ZnpHSrJx/Nl1kngnPxjQ7ZzHo
TvdngQOXT/qFcnNZEQOBbsZuNxL3qQCKNqOrY1s3Cp0KJpJfSn7FbjVSSD/Z1odBptEHHsdHbyQs
uDY+WO8XdbzFymYYj8hLaUuJM8FyR6FndcASnJ6CE886GzeKBHyn/qbbinx2f2+AummyGQxyJf7S
eTM2Vrss/xoWc2b7e5VDALncaHQUC2Y1+46ZYEjbyL31UmXzQLv1F1WJ//ThNru9dDYWjvJqAVxV
9GhstaTc92bO8VYspS9GnqdyNCFk0vpWV5Kl3X5a+Tt/XmNpj2NIDJD55RuuzXLLk29r8siNO6ch
ioV8MfEXIXhVv63Qz6If2TRsJVvx4A4yJDzaAxOWxepOi53P7EjkFlPuzp/u1HJy/NZJ233ilTIt
H58nqNc3Tm3QaUicO6qsA5UdXYJ0ouDP6TU9Bzis9bTThaoImRgJsjjJyBxtsJIHYdnAguez1uIz
/No+Q8ah0AHtOcBO9EswmGa285UbpS8yA5j0Jj0qKunopOOU7L6bEvxHsofxRi3JpswT/gV0eXb5
Tdgm1+DQyHOgDoGdefPHd6lkVYWmAdP1gB4bV69m1J+JAEt+kejAclQwTbX0HlvxjO/9qGO13g4a
ffmxxL6Fx5qUyngPGDQ+DGrWcTwnBzTR1DtykSI2tSdWTmNMOj3gIinXIsl+7MJ/hQrLSKIf8Fss
+uycaO6KekwAR323pkIBUOikDkqaqM3DX0ErfoL3t8enuRpieZHoK9qZox+VXE5BhDd/VDY9+mga
5r0E+OQar1JX50v3IkAKigKcqvU5Zsd2cA+jbSbVVEuHkAs234ChX0UfRFgy0Y53Pgpdd/HfFZoN
LmuTTcZN7jZaet4HykQqJ0SukAoLs36RDVk+pyH0b9gjmv5p+bDNWZ+S7kTfmpyVQ+HtBMcEs580
apauM5/1IgCg79PbaT8LlJD2Pu/HLMO6Rjw/P2laj+edzigzkZ/hWwdh5ouX2ckDjt4TGwnvzFsG
dJu0DAM4lJzqzbz8VqhnhpWsS86JoyR1w/ZpfyqM63qRtRkc/S8LyhLBoIc0dwXb0h/43NbYyBvd
dN4fcmHbJLLu+Atz07ejaPxsDb242pjyGuWApNf1/IAok69nyzaBFsdUu87mRluehAVY9LvQBSdv
WcMk/H5VZPwXphhI4v6AJuLHDjWFVuPwOkZEfgxdXTzIryV1ufSsyHjkGjiMdpfTCfMmK4pV3z1n
avZaDUXlRvojkp86Set5n9eop2SipuB7NdkmliA5wnqbBAkPjWC3FbJzZQi3o4xdew8WUp+bEYRs
1TZZNFoXq/2RUd4IKD9jSU0xtGtPw4uWzp+bcUnLiGqESYjHmCB7cDDc3R1seprt+VVvnPI7ghkc
LdosRYbfWQFMkQA+tQhFke3s1VVh7ef5oGmGnTDmUxiHEs3s+hXvUa6y8cc+BdgRx898HoALemEB
RvmS5MOsLtAkNtJ2DUEzMdrGBlUNiFV9f+RENqQD24H2gJx/eEZFoLNFxejUecue3HGxtacWotCR
kXRGwJOjzL4fdrz8kgnsQ14OIC4nWawJuyTSeB9amEbQ84nDlHvHsRZSRsgjozmTgjiSklQDQ15N
0ovo9vmgF0FgjoWbVpXoFm73QLMobdFAD7mVFnkKjnwAsS4Vr9s1yHsdv5zcE92jZis6j9Je31g4
a0mbfCrw8ECFWtm6j/dXg/EY0Am7wq1K5MIWipYu4hUMh8fZORrKcLVf4Bpk1LQGpZd1mQ91kwNN
H1cyiNPdBvQK4GXAV4diTkxvH9euVIEnnWCKO1WsAagG6Yy44hXz6QALtytZwofsQTK5+sBSjvxM
kt/Zm1D16u6T7JDHY1OOmWh+Pw6jKrUowjn+rdzr/d4U82r99f3+515AQe4sGWrSL5OeX1ExJ90e
mnkzcyrXY83cyfZb8dN4f9hBcpFw0dObZoIw3xz5g6UZDLUKFgk/dQS5YXumJ6xIlZM0P7iG91PW
Uh0/IEnOttxAaQr5aPJy4odLhDZ5eBwfoLlMSZIcEaxEh8Y2+kkbPo7lPbzxbLGHOVHTVuRn5+/3
SNwKIhvnMZZL8Riy8wa8uyriwC8ubLkpTDaUBJJlKzFNAGM9DWEWz942v5w50Qk0A5IsRDXxV+TI
h6YX1ymO+rEu62BujpQze3jcsAtBR5ZM8EBfhV8bje4j6jJ6OTIb2CFB0RZ1SdD0/IIXZMo9PO3R
BrTK+NPG5Snk8Bbth8UHmT2JFNHYEkJPjpFV4/dSmyidTKQYgxCNfW4mfO4/yOrTR+7WRmAE5Qeb
xtzKFAaxrcmjkYn9dXDQ8NBzloT0I76niiXPDwZtIfHJAwsx7AkE+N9uLXqrtPEVQyTF5jolgSVv
hHArpdbdlxc03ezYW5PGcfxyCApCpo6qjgJtzX0NKz30f2KXh07wpubO2zXTz4jymfFDlaThhDvB
ufv/gsBFbLF7NhqJo62ciitbutpEnJHxtGKy1NG5BeJD+gfNmFr5QTnXDZ9MiTd0wmhSzodSt7q4
WsbtQ4if/TiCw7XiQ6Sr8kQglDA8/i64cXo6iK9MyhXP31nXOC5uHDihFvBQd1+3aX2MuGdv1NCJ
f1xNBUA5Bk20MjELSiy6XQ+yOj0DT8rIiNGM03cMmGa0jtHzhqplZJbcugRu5QipS4/Nh6HGiTf+
bJn19WFsccUpIwrC5xqB81MnqghV83MooF4LR7oJFJDYsN0yAXWNSUySUL5/fz9/Otx1bhGaPe9H
3jMKgkijIMk9SEwIVjVr23lQwVrxBbwsVv0zPc4HqsGXdNPoEE7Xig9c4JxbwxDBnQz04w+myNEE
asY5XSmobzIgwp8AoW5XpP2BSITnRWf5xtDX71wy7nGNDTh/LqLFoMHwUqI/d6YZM/pawrvirIk7
8uxfIcm58mqIePq4jFoKNZDiRtdRu5BTWrSm9hNRG/7iFOFYG6UVBuI6kMLru31qOgBiQOgpJVYz
Jc+FDXpNCsvZExoOsxL6RhIbKqVClXUBjpx/6WaaCk/cN8+5L6lCTwg5SwwH4URMrmlWAaAepS3I
L7WDvM3jUrQhHlhdC7nZZXRx/4oPuSzGru7tX9SitY7L2idzfVbk9KCc/xUpNw2f3sZ80UPxyuLY
DIAXyZ/bfOONeHntmzsUCNJKfQREb4y3Ep6HvfFLLlLhR+iwXq4DOuRDmO5qze/eK3kO1xsC9q4G
HHVhIYDJDgSYIlXDGAf2XtAeh8YJkcV5wEB9sVWzkOTksk8yzz7edYaIjd5qVqUQiEryUwIpjj9C
Miktb2V9GYAIZgtfzZ1GK69ullXAc5MEvaG7kR577s7+a3AmyJrCmWWQWcfgEAQN3drBlMbvLN0G
Hmbk0HE21NVRLbD5nl/ppjvRJ6b+pvY0qOk5WGkLWLm7t7qAUcos/BYel7m0IChS+9rBfiAjYWs/
TzC7NvcK/FL9AUt9zm047YedG8X+gOTEBZHMhgZAyUAxiHmlV4EG4hCcZ0gRK1gb+mjtYflyZt7+
RpEkpt78Ddoxg1SX7o1bBE5gVvAfKhvJDh8qUdzXaMrfOdTFFoob1uMJ9ku4eGWFAJccGDyxzF0D
A4EASaICfbeDpnQPqt33zozzZ4fpUeqcqU3NbdyYNaDFniLtz5K9Z0qcgCmddH8kqZIY/yFUTsm0
b1fiHDM+7VFd++u7rm+DkK8wHjdWNQbx8XPx0PFy5Mq3BCbTNg5DAi8ojCVzItirTEGnMcm2nEWq
+TkrJpmofLerdhHAEeOccmwSm8Y8gu2atUq10pwTX+5J1kyTqFDUywGdPZjiVouZ0aohL1TCH6/7
UVSuTCkdpV+XH7axfOrEJ8SlzJv4Km1R+HWbow7HGzkXPwAwq+i0UYlxbD34B0KUBKCzpGnP6atG
G9wzEeHaXyk9TX0reI8nCRR981wWQG/BozB5Xy1Cb+HZz12ERJG2CyTugpmhP8pJJD9JV/GUvAcq
TyGwZSFd+ZLpNKuupEvBXxnXt/4IhQzgX70OmAhOLnABPPUOwLsmcmi/SRgoRUjOUumMtC5yUHBX
hDm0XzVYqsaiZKBGBUkquJVoy3EOb3Iz51AbTKgYR3K/gTRC9Np1lLJ4vGFenlZ4OYnFGLmqB1EN
nyCXuet1xtnzLTHWxyHkLFx7BV9WetViwJi6352TPe9GnZ7UOL2KOTQ/KTeS1euYJDg85i6sSkjm
UE56yG7Nl2gY7wLjdOZrQOTR/lR+Blm79jeeol9RxPjpbDX0phS2Q+LxYVYHh4huQDc52tSQpGl3
d7pqnaKz7lUuDoDnokO7aqabIP9zOC4SZeMGZ34HM3qRzWqgosWiKzIDvE2pVvhGHD5fTiPdfegz
mvqT5Yay4vzAtkX5eTl5ZEv6C62Aunv0EGtwWxK0OZKp2zhFZXqfiHdVN+POo3jav90jkgusbZfd
EBTNvvHbWcljXKfCkFgOwWAp6MRid+9sKAk642/A7fCEV5iKI31t6QyXcSIuV3hJR2LQ107IcqUu
5FoB9omrEsTAtY4PwbwvJh1pNmKzEoM4F9xMAGhTpezJ44L/SwDYmcdrx4QWBzZoFXyFg2FtObYT
m//QmZnI70USd8GMg+tldsp7urC+eDO2oe1qnwyFUI1PNIYP8pG1iJpMGziBt6G4Zx+keKZxzyGJ
SVQ9WVmnYJAr2a2Fa/1YoT1QIX05EtA+h/aOf7YxiqmwqGUNLRVMbCu6xq/rjXDpOEozRdnQKJ5o
cQZ1ICUcY4qdKEYIVLaKPFE8SXVOYsgo/0nhzvpQL7zEDDhrKgFW2/bNXZbPULyXzUSHLAz+rlZv
7PmK92KzF9C8YLxMYf1hObdUIr3JgrJ2+JzDCO44ak4zEkbysLvQYswOnn/EyIWSoBvihdbu6Vem
M7sR2p+18Yd5aaW7AkNfP/jGrMErnFaJVwDx7RH3i5sv8yJo/90JKCCtKh5RtSPR87F3ctR7qGK6
cGCkTIK088srZiiar1RW6uxicymHTkSPdXeBFBYRA4jeiIYvP000mdZ8DVOvY+iYERy9gle6/COi
VC/imh9iyKojBugCRbtt96v41zSANlLxq3ROW0R9BmzoTqo9qDr8khHUiYv40h1rqL1dI1bxQ0Cx
WITYyXCqG7XR+FhogyibTHDB9xC+c4dCY7AOUFnjZk3ZLxZ7sS872vv71DjNCbL3yuJ7XouEVuiG
CdRBg02UNinX2fUyu0HkoUVkjkvjm3l/dCRAnZKxPfRWEBKML+G9xyg4omNPxkuT0oic9I4zM5Cu
rkIjHLjf5huomVuFVOmiZkBW2f1S9iV5bhqZkv3cnkcUZFsuynf4FD2VQ/5mbJ2dNmPYL838OvDM
xCNGz7xhlviqFQBxvo7xFsGxeCyWdl5L2YyNoZr++S8S8t76soaQkTBAkHM84Lo9BlH1QxsTi7c8
hOMAe8BSWdy3kGxcqThMb82SDF70Of2IvPvXNCx9+BeSsgKdb9etC2jBJPc5AeeWE5J13bkBpw04
SVnuItHc7A0kExDjwgWimxS10Uvxr2yhEHmpASG7n7AHKKqOGvVfi0BLURUwoyOEwAxuMrWixWdw
IRfOnxGbjcTjyx7Yc8OB88NlDNjSsKgLVml5DxiIc3uRmNUcaMUNfKR+zqNqAoBsh6KuJi4jUOE4
hUOhMHe8rado72LLPCrenGhYhRFgKylYiCrbzMz/oVfuMunrxaVBVdWB1tYs2jv11CuBvRYR9GWO
3vjIOXp1wj5j8bg5/J7cihssE+HZ9TR0oH7fQ2umfRWWtlcijpqaGFOLS9s9MNX2FDrEwha819k7
AFTHkuq04gx8wSt7vX79bTqFwMNxBeiSzEhmO9bZ867CQie4gBYc89+NkbjMuUPuAj3T/qqSJd5J
A5oEehTUtgOKp1VhD/k6JkbImI3epJ0tNjP6CNGTg4gdudDfrRGyeqt7QvJKO4LlFykUcJd3zcWZ
99usq2Nkw6JpYIPhTGm8AmTJHIlxuvAdfBcLRkiIS2YS1YhpGmLXIo0oQ6IiKTG201ah51zMpe5a
TCxHV3Ap57tAj/0+qS1CCGCwnAQCc2VgJy5hUIWCXKbad4KGagMiu5mnRXgD2hWBoae0Zp2NKdGg
mO7eFcqtgVISAWDGR3TJJnyv4uK6LplCuuLn0WaFlaou9yKSmO8MkNIRhcSvqIOoQOkm1k2mtPCH
KKgWotr3h6hR35YG6d1H0NRwaJhacE0nuTU2GwMYQLmy+CmGKjqxnnyZ9tngDZJDszMUFi6geZkY
EijFDZWWFeG/W5ZSrKlGOn9sn/wgoWlyNedPJKPlQFVL9z5OfQKEQZBDORZiaKXzSAdLpZcUaf4b
lvcBsXRMLjFA7tkA9Blzwqx9k1Ib8W+K9esiswt4s94e/jQaDN09aZX0ldgD+pTvGd7lxs2hp2x5
wCuuWqG3L97AcjyGTLp5IbIgbRY3HA4Uk0HyvXsuTWv7xHb/r7ZQSjusL0DGcMZ7sUjFUqbVMTql
sK+xBLyP8gMC5RParpupkqgeBcahq9SQ63kCN7dZqI4a5Ak0xHgOiMGPbDAGz297PseCnUFopICI
24bp6r0VeUdJJPLfY9LJ8KM2rgWjwckG8CTLOtgMpZzhTFQRRL2/E4Y+UocIBH09mN20y6DiIxuK
4n5gxfL8jF+kQv82+WhMRxucR2ntbvFPHOWhGtrXD9wDe6IS8kBqzwQgLS5ty/OMHpcll5zT+M7N
DcOZ7D7FRBzrrhtUXZhegM0h4q1SGFj8zoEHllZcwbroIsdWJzdr3V2MUnbhmiTlV+s1OKgbtLgl
lHQB7vcxBfiRINo0I5USy+801uxubIJ5Ne8RMGTOz2HfwgGrT2AsXiMVs4lEq4wGLfOriFZltBkx
bzVkONoDKDVaxpvs66BuoyDZ+6YYgmAxPKNVZYDlHlZvrJ+9DQMB6WSVNDeAvPr7ACKNR1RVvQQb
8FeTYzwWlPp0scDSqBTUvURbzTHOAyINDLNAAr0S7HsHTgcA1VZ2ZLNrvJbkNxtmzEa6tD+hDl0m
ofpKc/LZSkizoUtIJ/0VY6EoOqMp92u0CaeAFgjkwBRxu2xPZpHG3n+hIXvl4tLlpjEZYBuhkVWj
IDuYARPRI4WCjggIKR7xWHeQWDzAog3KM6Kj26QiJHt08F/pnxGznOeL+yaDCcZVVCw27BhdjK2D
YLPStGUIxu+SN6CEyY+cVyjPVHhwSv/Kw0TNNtHlrwokhiQIWyWi4ii/pLnDpwS2VN+Q1O/kZw61
eKYwRIHFvGi0ZOyphZ50qXwD6v3LrFcGtCBV2w55/7cdiqe00rB5MDuMih7s6adzm5wGwVop7oXq
JlxUBAFPqztlAhbCD+0QA0yA98Lzkih53im8/xaMeGJ5zeAeghOsA42YewWslWXoYJMLea0/mvFV
qmhIc7cqTfgU6JUD6Navpdke1Tkn2p1U9KBj45UfVGAX850Oh8DOWmQrM8y6R97RdLC0sseMJzRS
Qg6EiwH3uVOvSHaqKpimHJCRNfhaFyfAIQcGI/yKa+XDN2WnHskhqMv1REPmTCtMa4h4pruttW4V
XQjoDZQ1TLcRIN1CpQJMCw3ogCGs/HCK3jo8tF2IhVSJUeTLXlYD51c4o8YrMQRzBZ3UXwW5Xs+P
rZARJUCiZ9qMSUK6or0iPtzOAexHIm7KgkU8J0A0z+ZieFq/NipiBnLGXs0hou1D/Eyp6+We27rC
vEaZXNErRiE79KgjhHucfpbf9mR+lhCTVz7h5aGvyWuh+2Mf8WnlWZjrc7LciB4lDImAd8Z3TGQQ
lY28ejpnW7wsh1TWBl8b4tQPu+p7s6pQPIr2CnJ8xU5UfF8J5OX3mRlBhEHSuhgV4XCFeSIHu9oV
Cjx15kOX0fBbiVkPqVuSF7L/7w1cQNFTMkcq8NqUmnidGElzaPb2ASlJn8ug27F4mex/4fA5BCdJ
JayzDtxUzwppJXDAvezrZY5t/Mk3pcoFHfC6rHBroMSSHoFEW+LStR66kDN3rCSq34vRktNA1Ww6
QfXqLYquDPPpNjXASriSKPXcrZ2NLCiUMp6Ja9Gf9M8DT1FaotD8akquAiJzZ5415TUsRR1dPu7x
3pjN0clUzqDMoOMMjI7k5/DHcQ3qY/d2enzarhbQ0/8UVHYQia9mvjJLjDy8ioUvu9ZZPDulhBqw
6O4fyovn9fDXrIqp5+jY17kj8R8BheJn/snQYwD3FDJ5kdqOWILpY2WuYAI6RMbg4mWYYbDkMv0Z
Sjplksvn14UGpPhwID/OtcuqBh5m0+vCOa/urNVsTLAuyW9LjSmwVfuptgvm57XnIu7nnNXYTM7A
gTFzrjprrxqY+uFY3AZCOQMnlUKb+A8kbIuMbZxnex3j7RB2jJYOIV3ngxvgFo2pw0xU3eQd9gBQ
F0xF5MVmhTpKWB8It6jSymAZghH7DXikUigOHidHojvtfOgBrmLtxJvXDaNBMukzFntAYps/7yQb
5u/la9jaA0nCfgq9gBt7R4lASGr+pbAvAYM+u5XLD7hOHqRzt0ECXwJvmhK7JeTR3aWmN3qsi9c7
HFJW8wZpt7oM5GSgUQ7dHboiThitlDapfw7PXcL/eEuRP5hQbqK0QYszssRDgWQlYjMUs0Y+Al2y
GE+HQnoBFiyTIVMYhBZMa0QA2Ij+yj7BVE539YCsSARwG8frAQ0mBIxJDnnxfKCXmwQAqQm5IjDj
tDmruh2WKX1lCbol/w/PUlugcQMXoKGwv07wMRX+QkES1v5IyC5NtRmKI0rWIHPFqLL6fqArNRjn
AdiqauXKRBt7fbvVnp1wxvhsWEDjeJqd9ow82OaqcIep2oZ602OaJ2pUZoWS2v38m+FDZfvHYcvW
YzoalRpHKyHWVNzuHsd1HXbuHqzW7V48hvHlzmVheivKWZK4yVgAwJ9xWedc74YeCwBJ04H1TlfH
O0jUeun6Y/dq7/9KKV93HjMQFL+UwRgWv1Nz7eqimFIxVTK4LXqsR0nbfOkg408IZzdBUJ3muLKd
81tlJpX3uzWG0rmA/rVVqe/sB4Y65pyJIQ5q5jcwalyVqQS/oAv7pxAcBAVjxGVEHw0xP5UaOlbU
x+2zjhpA3NgJqlvmQwlNVWTrRyxRyPuMNcl1fn3p2487Vz5vmgD0bsOHxVy+8B5ebMUVvVQyiOqr
rJ3C3z2mHLrQuUKbq1JUeNE4QUw6FWRsDIJxaUa0RHsk4nRquOz3Umg1C9no5uor/Evl3RGkHUie
pomQcsNL+Kx2DcNN6aHDooxOer3lzdLqZL50vEeCJ0+FZBCH78L+2nc/rTIccTQ7HOJIXL+5A07s
dBC4kdIGSO1ayJxPwlx1pma7YHgDO4qeRPmvd/WvvD+X1ts8Z89A3wLyErSo5a6HSueb/trZD5gi
UQFWPlFuSJRD6X4GwRKyMc6nLkG1x8XjuGz9V1eXvrmZwhNvdJKWBAhLZzCvzbw9Spa/Y/DAvbod
U7Ejxa3cRjbOwvaNMzDUOed0mLO3WvWSYPUVHakbGyNzn8HR+A80yGclVdreqU1Tiie+imuMOGSg
EuiTjVdPQxkREq/FL0aIH/9h3Q9sgvrMnQlr20MGFRn9Ywz+ewHKSBJaE+sRGpkeb4WriJR+albm
8Oy8UNSPfeOH3yEBbi1O/fa86CepZhzyq3uCPtSvQ7gRW7rsHubEzRODEwa9zY4V2Mox7sWWM1Li
ZLS1fF2b6GmgMG2S+kEItBp6TQMw+YQVEtk7tYD01ip62L4UGzB5sCnCWHUpDyncySuDucYFd9Jj
JJ1wkKWKtiudbQaUPuvxRNqH06AmXsbp19VqUdYw/pzxlcI/qYUCU1WpwlKTMjgqgPeq8G3o4yfc
8SJbpTfoG3Q9TtbtgbhLBU5+NJsk2T+umHfZ7MN9eSaN8k18NTpHHOHwMZ8E+2UzD/ocRTq6/jCd
Qk1bHFEtwJ8x6hpRar+C0PiFDfkpvt3i6n2AVZTXuI5XaGqayA+2l1rHgWDZEL2RwkomlN9xyub4
gdYaJpCC8f+5VkK4SmJ+yNImqSXmIWpVzcnaWt6t5gqnVj3vhG6zUk7k4xkicDt/dODp+34uOgKP
87KsYWKy58q/j3MiiNXH2MbFjMB3APUIV7H1RK+TpnS+G7vsl2qhOoOlpu2YFGMmOMRGzSAi6qwx
/HrKrdNQJ1thJf7smw9KdmHPAe7Aa55Grlhb71WtiipYB4gvX2GWq8qlxi6ccrRzvKzyARKftFs7
/e5bjRDhEAwnehIGynH0s9oiiggtwjBPuo+CziWSMOmkGge1AAt8eNfubM31aE5eQUnhDXPTrdRp
NfEAjBy8otVrM8pDVEKPKXuM/Zo2r78OpHvMkOV4HDGWICS8xZAVVDgjwTqfrJKtiACXHThdi+jQ
XEiDofGAjUXWxec4iyJ25c4Hm7gUIjgG2O2AlhilWmR11IyVn0t3eNlgbXvGh6deAPRP1oUvWo8M
lSdFhbV3oUbjz/TBp5uxRWrPXsLMUEqzdWvbcg8UcjtnBbyq5ykjVQHgGYFekbagegr7QM392Uf1
4wk5dBKO0O+vymraNYBhWduEl37MYNFAT+17zgaUrZFN2z9rvOf3mUotAFHQkOhZXnzjbFFGBSei
rJbNgCLf6neSRd0iptJ71qcrIK0lPF8Efu5Vx26yWSlGuizo2pgSWl2awbEPZXXOapt4vW5c7hqP
63IF7jKxD5Cwa05fSvqtwLdZIOLMF1eA0YwUvSJVx7E95gp7SXcUymy279CzugdCCK7D+I2+DxKO
D2yV+5X5SfM5mmhbt8JEj31ycQNfAEcak2m3PM+GpMEQQL8MVH8p0htcnmnXg/c8pAEnjS7iIKmo
X/TGUveC2W3t6sJ7foMNn2lcAMDS71lkJdYF2bJkJoSrE2QrigLUS/q9MZkJ07cuTClIXZvWMFCC
8QID0lFZQLEAm9jvjkd/ylMjh78aonb7RU2CZyahJMPqPeKgsHxRWOmLw/JTg5iGFdklFuH/M4cP
CNPlYJHJx+YiFKRc3nLFpgwH+GG131/Z
`protect end_protected
|
entity tb_snum04 is
end tb_snum04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_snum04 is
signal r : boolean;
begin
cmp04_1: entity work.snum04
port map (r);
process
begin
wait for 1 ns;
assert r severity failure;
wait;
end process;
end behav;
|
-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2014, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : ram2ddr.vhd
-- MODULE NAME : RAM to DDR2 Interface Converter with internal XADC
-- instantiation
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : mihaita.nagy@digilent.ro
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2014-02-04 Mihaita Nagy Created
-- 1.1 2014-04-04 Mihaita Nagy Fixed double registering write bug
-------------------------------------------------------------------------------
-- DESCRIPTION : This module implements a simple Static RAM to DDR2 interface
-- converter designed to be used with Digilent Nexys4-DDR board
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity Ram2Ddr is
port (
-- Common
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
ram_a : in std_logic_vector(26 downto 0);
ram_dq_i : in std_logic_vector(15 downto 0);
ram_dq_o : out std_logic_vector(15 downto 0);
ram_cen : in std_logic;
ram_oen : in std_logic;
ram_wen : in std_logic;
ram_ub : in std_logic;
ram_lb : in std_logic;
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end Ram2Ddr;
architecture Behavioral of Ram2Ddr is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component ddr
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
sys_clk_i : in std_logic;
sys_rst : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
init_calib_complete : out std_logic);
end component;
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
-- FSM
type state_type is (stIdle, stPreset, stSendData, stSetCmdRd, stSetCmdWr,
stWaitCen);
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
-- ddr commands
constant CMD_WRITE : std_logic_vector(2 downto 0) := "000";
constant CMD_READ : std_logic_vector(2 downto 0) := "001";
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- state machine
signal cState, nState : state_type;
-- global signals
signal mem_ui_clk : std_logic;
signal mem_ui_rst : std_logic;
signal rst : std_logic;
signal rstn : std_logic;
signal sreg : std_logic_vector(1 downto 0);
-- ram internal signals
signal ram_a_int : std_logic_vector(26 downto 0);
signal ram_dq_i_int : std_logic_vector(15 downto 0);
signal ram_cen_int : std_logic;
signal ram_oen_int : std_logic;
signal ram_wen_int : std_logic;
signal ram_ub_int : std_logic;
signal ram_lb_int : std_logic;
-- ddr user interface signals
signal mem_addr : std_logic_vector(26 downto 0); -- address for current request
signal mem_cmd : std_logic_vector(2 downto 0); -- command for current request
signal mem_en : std_logic; -- active-high strobe for 'cmd' and 'addr'
signal mem_rdy : std_logic;
signal mem_wdf_rdy : std_logic; -- write data FIFO is ready to receive data (wdf_rdy = 1 & wdf_wren = 1)
signal mem_wdf_data : std_logic_vector(127 downto 0);
signal mem_wdf_end : std_logic; -- active-high last 'wdf_data'
signal mem_wdf_mask : std_logic_vector(15 downto 0);
signal mem_wdf_wren : std_logic;
signal mem_rd_data : std_logic_vector(127 downto 0);
signal mem_rd_data_end : std_logic; -- active-high last 'rd_data'
signal mem_rd_data_valid : std_logic; -- active-high 'rd_data' valid
signal calib_complete : std_logic; -- active-high calibration complete
------------------------------------------------------------------------
-- Signal attributes (debugging)
------------------------------------------------------------------------
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of cState : signal is "GRAY";
attribute ASYNC_REG : string;
attribute ASYNC_REG of sreg : signal is "TRUE";
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Registering the active-low reset for the MIG component
------------------------------------------------------------------------
RSTSYNC: process(clk_200MHz_i)
begin
if rising_edge(clk_200MHz_i) then
sreg <= sreg(0) & rst_i;
rstn <= not sreg(1);
end if;
end process RSTSYNC;
------------------------------------------------------------------------
-- DDR controller instance
------------------------------------------------------------------------
Inst_DDR: ddr
port map (
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Inputs
sys_clk_i => clk_200MHz_i,
sys_rst => rstn,
-- user interface signals
app_addr => mem_addr,
app_cmd => mem_cmd,
app_en => mem_en,
app_wdf_data => mem_wdf_data,
app_wdf_end => mem_wdf_end,
app_wdf_mask => mem_wdf_mask,
app_wdf_wren => mem_wdf_wren,
app_rd_data => mem_rd_data,
app_rd_data_end => mem_rd_data_end,
app_rd_data_valid => mem_rd_data_valid,
app_rdy => mem_rdy,
app_wdf_rdy => mem_wdf_rdy,
app_sr_req => '0',
app_sr_active => open,
app_ref_req => '0',
app_ref_ack => open,
app_zq_req => '0',
app_zq_ack => open,
ui_clk => mem_ui_clk,
ui_clk_sync_rst => mem_ui_rst,
device_temp_i => device_temp_i,
init_calib_complete => calib_complete);
------------------------------------------------------------------------
-- Registering all inputs of the state machine to 'mem_ui_clk' domain
------------------------------------------------------------------------
REG_IN: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
ram_a_int <= ram_a;
ram_dq_i_int <= ram_dq_i;
ram_cen_int <= ram_cen;
ram_oen_int <= ram_oen;
ram_wen_int <= ram_wen;
ram_ub_int <= ram_ub;
ram_lb_int <= ram_lb;
end if;
end process REG_IN;
------------------------------------------------------------------------
-- State Machine
------------------------------------------------------------------------
-- Register states
SYNC_PROCESS: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst = '1' then
cState <= stIdle;
else
cState <= nState;
end if;
end if;
end process SYNC_PROCESS;
-- Next state logic
NEXT_STATE_DECODE: process(cState, calib_complete, ram_cen_int,
mem_rdy, mem_wdf_rdy)
begin
nState <= cState;
case(cState) is
-- If calibration is done successfully and CEN is
-- deasserted then start a new transaction
when stIdle =>
if ram_cen_int = '0' and
calib_complete = '1' then
nState <= stPreset;
end if;
-- In this state we store the address and data to
-- be written or the address to read from. We need
-- this additional state to make sure that all input
-- transitions are fully settled and registered
when stPreset =>
if ram_wen_int = '0' then
nState <= stSendData;
elsif ram_oen_int = '0' then
nState <= stSetCmdRd;
end if;
-- In a write transaction the data it written first
-- giving higher priority to 'mem_wdf_rdy' frag over
-- 'mem_rdy'
when stSendData =>
if mem_wdf_rdy = '1' then
nState <= stSetCmdWr;
end if;
-- Sending the read command and wait for the 'mem_rdy'
-- frag to be asserted (in case it's not)
when stSetCmdRd =>
if mem_rdy = '1' then
nState <= stWaitCen;
end if;
-- Sending the write command after the data has been
-- written to the controller FIFO and wait ro the
-- 'mem_rdy' frag to be asserted (in case it's not)
when stSetCmdWr =>
if mem_rdy = '1' then
nState <= stWaitCen;
end if;
-- After sending all the control signals and data, we
-- wait for the external CEN to signal transaction
-- end
when stWaitCen =>
if ram_cen_int = '1' then
nState <= stIdle;
end if;
when others => nState <= stIdle;
end case;
end process;
------------------------------------------------------------------------
-- Generating the FIFO control and command signals according to the
-- current state of the FSM
------------------------------------------------------------------------
MEM_WR_CTL: process(cState)
begin
if cState = stSendData then
mem_wdf_wren <= '1';
mem_wdf_end <= '1';
else
mem_wdf_wren <= '0';
mem_wdf_end <= '0';
end if;
end process MEM_WR_CTL;
MEM_CTL: process(cState)
begin
if cState = stSetCmdRd then
mem_en <= '1';
mem_cmd <= CMD_READ;
elsif cState = stSetCmdWr then
mem_en <= '1';
mem_cmd <= CMD_WRITE;
else
mem_en <= '0';
mem_cmd <= (others => '0');
end if;
end process MEM_CTL;
------------------------------------------------------------------------
-- Decoding the least significant 3 bits of the address and creating
-- accordingly the 'mem_wdf_mask'
------------------------------------------------------------------------
WR_DATA_MSK: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stPreset then
case(ram_a_int(3 downto 1)) is
when "000" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111111111101";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111111111110";
else -- 16-bit
mem_wdf_mask <= "1111111111111100";
end if;
when "001" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111111110111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111111111011";
else -- 16-bit
mem_wdf_mask <= "1111111111110011";
end if;
when "010" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111111011111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111111101111";
else -- 16-bit
mem_wdf_mask <= "1111111111001111";
end if;
when "011" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111101111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111110111111";
else -- 16-bit
mem_wdf_mask <= "1111111100111111";
end if;
when "100" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111110111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111011111111";
else -- 16-bit
mem_wdf_mask <= "1111110011111111";
end if;
when "101" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111011111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111101111111111";
else -- 16-bit
mem_wdf_mask <= "1111001111111111";
end if;
when "110" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1101111111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1110111111111111";
else -- 16-bit
mem_wdf_mask <= "1100111111111111";
end if;
when "111" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "0111111111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1011111111111111";
else -- 16-bit
mem_wdf_mask <= "0011111111111111";
end if;
when others => null;
end case;
end if;
end if;
end process WR_DATA_MSK;
------------------------------------------------------------------------
-- Registering write data and read/write address
------------------------------------------------------------------------
WR_DATA_ADDR: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stPreset then
mem_wdf_data <= ram_dq_i_int & ram_dq_i_int & ram_dq_i_int &
ram_dq_i_int & ram_dq_i_int & ram_dq_i_int &
ram_dq_i_int & ram_dq_i_int;
end if;
end if;
end process WR_DATA_ADDR;
WR_ADDR: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stPreset then
mem_addr <= ram_a_int(26 downto 4) & "0000";
end if;
end if;
end process WR_ADDR;
------------------------------------------------------------------------
-- Mask and output the read data from the FIFO
------------------------------------------------------------------------
RD_DATA: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stWaitCen and mem_rd_data_valid = '1' and
mem_rd_data_end = '1' then
case(ram_a_int(3 downto 1)) is
when "000" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(15 downto 8) &
mem_rd_data(15 downto 8);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(7 downto 0) &
mem_rd_data(7 downto 0);
else -- 16-bit
ram_dq_o <= mem_rd_data(15 downto 0);
end if;
when "001" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(31 downto 24) &
mem_rd_data(31 downto 24);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(23 downto 16) &
mem_rd_data(23 downto 16);
else -- 16-bit
ram_dq_o <= mem_rd_data(31 downto 16);
end if;
when "010" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(47 downto 40) &
mem_rd_data(47 downto 40);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(39 downto 32) &
mem_rd_data(39 downto 32);
else -- 16-bit
ram_dq_o <= mem_rd_data(47 downto 32);
end if;
when "011" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(63 downto 56) &
mem_rd_data(63 downto 56);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(55 downto 48) &
mem_rd_data(55 downto 48);
else -- 16-bit
ram_dq_o <= mem_rd_data(63 downto 48);
end if;
when "100" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(79 downto 72) &
mem_rd_data(79 downto 72);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(71 downto 64) &
mem_rd_data(71 downto 64);
else -- 16-bit
ram_dq_o <= mem_rd_data(79 downto 64);
end if;
when "101" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(95 downto 88) &
mem_rd_data(95 downto 88);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(87 downto 80) &
mem_rd_data(87 downto 80);
else -- 16-bit
ram_dq_o <= mem_rd_data(95 downto 80);
end if;
when "110" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(111 downto 104) &
mem_rd_data(111 downto 104);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(103 downto 96) &
mem_rd_data(103 downto 96);
else -- 16-bit
ram_dq_o <= mem_rd_data(111 downto 96);
end if;
when "111" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(127 downto 120) &
mem_rd_data(127 downto 120);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(119 downto 112) &
mem_rd_data(119 downto 112);
else -- 16-bit
ram_dq_o <= mem_rd_data(127 downto 112);
end if;
when others => null;
end case;
end if;
end if;
end process RD_DATA;
end Behavioral;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
qXwUbNWAqYbdpqBgu5V2Irr0yIHokdWq4yIsYatvbtHKhU5sTXcicxiWkZwMlmh7JxJXXORLT+ZU
v/PLV06P9w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
INsIPl3meZGaPEpm/0hY6qn6pNkmquxWy2FiThgvPkXiH85UtEqY8o5v8IRoHwlNbiFMfARYDbEO
+OZA2Z89jPi7vSGZam1nQVpdb9tTe8gy3sT0W8L8+/zNcgLhbWP9KgDZMNF+3YJnaj0hueORxLD7
CetUAimRvUF+Ldr4nyU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gJNTE+b/peQ4Oto07xlVbEfbFZ6nMfBGBuiUK4g+q+PLYtJWQI7QotLPwqtbFK07bXzvTJuyp/V5
wl4PKEJefSdYOEbPh6MIoiuvoQGJTFadYzFpMqBoF16yqhXJkL2oVtmXvJfQIITgSFazvP3qKZh3
NjuPtF1edJvfzpI7PLpFpZGoayowx6z/jtYsnIk2GP0W7YdZ9cOlkiSH2S1km12oKXLOaR0rDUTJ
ebEra0Bgy/Z3Q2E/7BECOXrujkXocR8xNi5Eaeaa53/ccDlgYYbn9NCrztVKJ5qtFbzqTQTW0d9a
mJndrp56FTBESQa//wxKfj8ZblMcoVBhTmzhNQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
xGHFc5dhsERwTBJ6HzSxtgI4YwpmHAsH9SafoAvaDa+cI2KAeGL0jrTiG3tkhsE6iSwJrqEOYnBt
n+EBnh1QW0+XSDRvU22yYrXld4AFAowoDmmRvGl8seLeA88PptewzCsn0OcE/MP4++TlNv7LK5dv
mheDDGnWdYqkYHdJIIs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Jbuyhmw//VZkr7Ws9+6WrN6Lj7dPBf/FX+UDLxKbBrhbv56fo3Y5D7icn71R0xbIApuFFtR8Iwcm
uySbAa59erYexsrtv2JwyehWzp7rsT+wE9FVJrZ76BH99VmVzK8R26yYJmnQOxniTZ9Bpt/l1Hgp
bqR9KddxVv7YR/TVF4FIjFACcu1LMYgxNBjvUjYUdYT1kFzIT54fa5kEBMPS2KGJrfY9RdbMnuHO
JIGhONlUF43KljQ2n+XLyCeaL8y6a2Zgqg+6lrVG6Ztpt3ZM95CTfiRQvsefR4QauRmUQSbN7I6O
wmyxcB0504V7UGeVSRNaInvWNlHwpFrgxy052A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19488)
`protect data_block
ZOdI0iP37J9pIcofeEB28BfxN2U3/rji4ipjw5lr6o3x4jhbCjwb7Ztbz/CLVL8St7mYcvoL/dYq
5+gWUzsl7Ydljsakd2HM7+lvdUDYlMDu1ak7l4pPaH7afx0UDQEPoC7zbAM7mpb1xLfrpqGnpVW2
JbrdFDxT9mszhfrRlEm26YIfkwPke8Y1y7yypDB6JxxAn1+nYfiPM1gklBA/wAmNFZ/fUDPztbOx
fr+b3oAiKEicuQhOXDU2b2grmWbhknxewEgKnKv+W2/jdejqfVh7P4/yV3VnVWs4fWuMZRv91LRr
Fm3vspLbkewYDRcreiIAMYIyc7Rt6gqq5p5+awdEBeWb14JtRbIG5FGJRFY6yuZDzFP7Mt9HWu8v
GpOIzL522uTZg9CYRRXFlBitsgVKBZiJy0ni8tiLM51tYJMvrl9gigTn9+YckK1bLrNGcxIrwzjt
nHffYtRVHgweShPwnVv/aUkIiUM2O5lqvxwKvs7dzXxv2Q2adgle1XLlAH67+p1MgkWk+mbXVU6H
wJUheYWopF/lhgFE61ivB1qTJyd6j1lMaPiKTsAAtEuxaBfbCEXNH1T3wPlCYZxUtB+okycwL9oC
coCvP2Geu8Y0Z1mNKu7u0R8xw9OB1EJ6GRlt3Aj7C0Xguq6pyRnZrSTNGRaZDZe6PLh3Dx2Xdqa8
Um7mAdWU6wYY0qMQxPOmrYxh2n1XILRKUR+dNrHLwP0+8SUdSN0cMr5S5UuoX5Ob1ppAwFqm9KEk
6ifP2WRzfl0YqeUpeDOGXruOl2JKkdlldvfm2LgjUXgm/Ei22Bc2gPEmFoRTYyr0QKH9vH2DaJDW
Bxr27qjuywr6ffYod05Czc6HCqt2BmVJbhic5tbUV1TJs7vYHLBZI/LmngPRp090E12m2t8MpsaQ
iOfQQO5U4wLXFut3X12TKMAHeP7k2TBQwGDj8J+4qe5FuoExKXd+WGpIA5rWm83BPjZb6k4s5aUj
nH+x8zoZet6NMQcvzm3mHy7vvXnqbtFBC39UEXGqqO1XNNaeNZIgigmeCaA/C30Zp9v8TRgXqiWi
g9NM40arYrmkXiDwNOUx9Pk81z7g7JAGAtzIdlYeCt7a+vbbhkpWODL21g4pWMDJ8hepuU/Ji6CY
2VAtCQtkpi5p+tunmxw3aRdrqSNoPfi8B9Y3SgSgfvBGzOPonbaDIdGJJEuxcb29Hxu6f2FLVA+O
KpKRALtdUC/kLjpzkkJ1eAvNARPe0fccPhw9fweR+kIaAncKZuymXizBwJ+IVqoR+rE6v5PtloS8
Y+9zQQ6zStv/79cXQQ1H7dmZBpqdeyQj1Lyv2lRAcC+y8t5Tjv+rcg1JLydWS9coiEt3mLsLhuS7
mteHH+MtWou51Ez4DLMgXkanfxi2BQXV8dJrV2tNEwySHkKmER9y44AVhUqEQj40EMGUWxTxInDA
ESfN+BZgU+1qhi6yXqdSHiDd2J5mfapKajD4w28dQwZ1hEMfSWqRyPObgUHIzd85zk5cToJP2g8i
TOJHuiObOhXQWiBtYIUms9teUuGI1+mZIy74ikDrmh9KcMXZuV54+jEfJG/F63QPQPwPlbomNbTb
t/QEWX0gkdwe/ZHejgg9lO5KtVVeY2W71CPPS7pBYs55eQFlDv7Y8tsi9buPuoF01KN/4cyGFtzJ
FDWRo0prEZVw7QN1HyyoGO+OgCWSJ9+J6cgQ1pFodl9NB1TphCx7mWg2t8aVFfTkQnaFcfvcpusY
6Yn53kU9irRsop0uTzTea1wKd01tWzA52vKPnFE1SLb+Q5xwGLFAI+xej7gm2ooEwlb2a6mSYxlT
YxZtrtZwBN5i7j7UO7FYj7rNr1E8Jn6gSErhxJcgO2hPdsx0RsuSCvWGtefN/GSkrXQesBzAdu2Y
mhgFEEk8LmYSlwQj1rDpWCCr07lzqs3R0y13S64VG+aYH4l8gIyd7vL9LURq5kOyAo0Hxhp9uvdP
JihCbqqBK11Sr1kXE3cL7l2m7U7a11LRcNLMFJDrTzezn3/7INa8q36MwZ1eh0SHcyQaKutkRd50
h9UEA+lnVTIzi9VjSwe5J06ax+ANn55f9UtPIRGqQQOuRkrm95mU86dcNeoqKAOQ0VEcQUR2wwLv
xO28IqToexdE3JBJbOIE/Acrz+opvMl3gE3T1t1CeVw//jc1Wg22ZfVG3niStXvLtetMtZA1qgdK
Hk93Hk2AsTdMP4EJK8O5uqpGNGrYV2dD0YpmxSfDUcHapV0gXDkLdn02Veqq60L+VM8yAs+8ZgDB
AalwWM/OOsLPi1kNzjfoy1rgD9mbQIPMx79nfBn0ZYOldkgUm+4pc7ch9ASgS/UOoaQobUfGfTxh
DrqkbkoJY8DWgvSD3LgwlZ+dfTqLueqxJaGEf2j3CPrTWN53pjW5GmsjM7kmwd49yWJ3Y9gIDacW
854gKsux7xL1kQ1EvEbIpzynvVW8FwUSKaQIXv3QXQehbvBNe2+NFrG42fm6Bt1Jnn2EpTZPmmMJ
BAM8y7hqIqJAEJttbS+eO6WqJHTXs3Uj9EfGLVVQM3mk7osvQtCw0+6qgal2X/MGFRFc8Jebq6n0
L0aAFwCmGk1QX6Ohr2nM6o3xqF+a7E3y+WFlKuvrDsLQzHEJY3duKaR+E4vONhvRJfqUgvFZewMs
0cD0nWCm5Ka/yfI90gTofvZi4Fgk24utJcaOqVqBCPGcu9MaPidFKgKGFnyr6M6mqyKQuEXbY54g
ifbECttY050nG9H9z/k9mdEuEHLhrMQ0kLmY5SAR3JiFIms8dtKPIDChKlPIRgI5ynAyoa9HiAmA
IWmQTzK9dkUvKE7S3+mo5SoulQ3B+qkEfaitytlI13392Drr7F09ThJgADrcTyMsN8oF32+AXh70
rpc6mltRk269YM05X+jXsfTNb0bO6Mc5eAesoLYSwqm1CGCb/HY5RME2TlqNUZQZPHZI+7Jo1wwf
FZ2e/pehzqf16buKyw6zBCoDvSJX09g7wnzGn9aLKIuRKmRE+3TgvvHQMLK2WzYKKVthAW5A5pPe
rRZ7RqJ7eAKRNf27mgY3XnVA6D+tK8+N97w+zQKprfVjpTrZ3qwpfhHEuzv2o26vH7ExL9HxN2+L
cLxy5aArT6gdlf9cyhHLLUh8XicnuHHDW8BsKRtq5JhAg5zTf6KJRN0uhArS1djeg4MgOr+2G+8K
4gapi6CGS0I8j65GpZCo8ZW6Bcgc3i0BRKVprsXfScxkip29co0K96l/tGe6hc+SVuzX2pM2mabv
KiolZIb5BUaHKV66YIoDnQtgg/dJeCPkKt1F8a5FfkF37NKOfsYsxG49crqXmFnW7t+OFJarMj71
ZvwVNmILzHLaNJrT/JOOnsVBqxvOhqWB93VDTcDFqz3eooibgxeBW07NBVLwzjqNK6BdFzbaN2zn
mTTnx2iq3oLwKdblWBqJtUF3EbYDtodJ52Lq0x0g88JuSDa9TjhY9PRog+dv9KcjX14bMsKTwxLH
7kvjetk2XsiMJPW1z+Rn/7Qpn2fFsjh2SO6yiUj3lwxIlj91uK299l0yyu90Xud+qlvA5OqPm17c
wliUBU/xZso/v2DmL24cP+KGT1LjyylAkqnFx4LKM1ZGmlG7pPNW1MlXVmQ2Ix1Y5vIbQO/ck67/
1DkqUFNDzljtYy/UVtBSJptSsr/EQkcx40pNjmOO1AFtca8Y7rsc9a4ilBz2sqfQbcQvY1oEgLzw
xHnX+6HLkz9u9F01n8Pu8to8TTYoF88QkE2xrpE/s1nh7eeTcUydzoSz50VNK2Dp+sELeYyMLbPr
quzG/O3SBcG84HmftvcopYAiCkvKoH8gTwdWNbP+VeTr3gu/se5YPo4Eh64kGMwD4s2pHI3C7WjP
OHMe8FfgFBSP/00ItXE5PAgWP46iviqBvNLeXChWU+oTNyXnIuAAXEE17vYDCvusRbCk16RXP3To
v/LDgUlNiQiFZ3MzaFFoE0cwNy3GshCm8sNTGQaXOybw5lCJIsHhFRLvhh6yp4Ejy4+Xf4sODqC6
VybJlZkv7jT+sG+GgUyIG8hHGSpM997CqYi/pKtbrK6AfXU0tlL+fDDdxFjv88D2ymeVIN2JREmy
0m0kOdP2fYA7p20Nct6hi3VYi26+g3nAFgWOS9p/uCt28qYHtuMUqd4BH+WHeBDwzgGpjFslB1vy
d1JtXXHmiFz5fUv+vCXFPGNesDgbSOwXh032Pkv09zTgXwIL2pcF43Uc57ISMKf01sBAw7gRDGFp
yDH+0KdhHWURhzKBmgm94cifysCskBxhQtiQiFznh2Kn/Qr2hdHqIHVBFr0/oCL3WfLjhztQgpeH
/XBEFo71zvd1nbpq5mCaEJuR3napCAaaht1bmTRGt+QGlZysLO0js8V8N8Y8vFVsA1+muSmyhZ4U
NeOxfxrBZ4FGHv/neKktZyNX4qKBBjJJyCHGKU/tLmdB29Jk1Nn2JBmaI4+GNcM97t6EBaSDoFWi
O9Ww+w/13btpNXWBrFLJgPSdN7YDRhczAsFIhwTfUDmEdfSeFLf1XkbbRDgpHOdyLfAyTWSWs8bX
Mg+XifY7MTVYCw0IFNWj2w8CpW2VIFVKaAxwpHoCS1aUSMYN34zkkCUB6leskZ4s13wSex+BHur9
qfdwvHGk40WRwa6xStvNoLfcN2PMiv0z13UvsyFLv9PsdA4lrzfMVH3HRlIz1c9+6o01uPuGQJyb
/5jIMkJz2IbWV3WjW7HZDM0et+LpVmwRKvobZ6NTAyXOSAJQTOKqZwOo0En+FStcHJyqysjhoJhQ
XN4q7KLrCbrv+t2MmUIDHrlXbMi0EhI6tF+Yl+X5wxB7w1PnABLrOU6hqOgBVhYDVGjnSEd4vnhe
mg77HyXxiL8VfKFFmblCGsv6XNHfvbe2apWbaJLouWczLl/LeyrZF0TqvLjleHJCmCysLVgE9gQl
fv0yqg7nr3f5pA4bPyZIe/Cqb2LyWv4nems9/2B2BLZQMTj6ExmqOPnd/URjkNGQ1tl6UBYDvjU+
SmE+uYVPPmrw1wMN1B0VeAlAGLSlHq6A/kSumhbQ4Ozmbv6Jb5WPZfb900wbF3vMkGRVun+zjy22
NH+4MaE7E6kLEyu0Gz9X9F9EvMkjMeLoB1BrW9lgMcS2MaQC6ycK6bjuI3xZwAADZrC07Gfv/R4k
hD4C+jFX/I+l49sSOZ+I4Va7WvOoqBv/vFdon6jAfQZUWHTEZbIAc8CR1owkpMK0ruKEny+MGM7q
bA/EeItFHMnZ+8l1bWGHngzZH/X7BgmPhtDFU8OaZouYQzJ1gxLFkW9ylUBJmXZNS9X9PfTQx4RH
2DuWIoWf2XZdlOXgOeZolu8v741TXGSdjV3W20X2NLD7Es4on7oHPJ3WdwfpL+kvFqm2vjQwYeys
Gjz+o0A0uMDjCLnK3ubECYI1aaNcOKJRxML+0lD8nFaSHz5InhhkZ8AQesugPedEsDMkXJL1ODY3
04gEn1/p/j+zB6Oa49ti+5Z7IhXB2jAAcnJzDfiwSIwHPzOJkAvbAwgqKM4k0VIq/mhaWBmC+z8O
ZIzpotsf4G/GSlcSPG3nKrDJQpYaSH7WxZ6P/lj/eDFq8Kcbqv56PdGJWZmALsL9xXTTLH5rRN6V
kmaBHX7zGgUlr8iSqwaD+8uUL4Nl3QKj1EHmDoxpFtkzgoqqyRz5f9ttxWJ4Fh99q8DsbcXyUFzB
Apf567qAGFb5gFjKlOEWCLQAv4tWjONBwZROOHN3MEBYZi0zI+0NSpHGcIzzIKIz/FLBqG/qlMne
7upS1NnlCSBvoHFxzPxEYW0UJSn59C1EpC2Xcpo/ZDegNfmB4Q5Y1RtwJN1H3BZFtGcc+pBu0gaR
8ueMPiIIUMrbly1C8DFn2wGpwFGsIdgaCDPKAcHYQu+56gKAmNFXHntiMyzJ5ZMQPEKe81SEJbyP
pZBUKiJtcacOhGCRtEraA0b4dZpNv5avVlbJ71S8o/W5w0XrS59r6RS2H5C1jNQr+SyiLavq0nR+
L0Z8jvFzWbZeTpNWmtBKiQJ9C4y14hyPqpBzGYZXYPyDT9PF+P/6JLG+nWBmphjAeKYIskHdar9t
WFCHvpssSnGuNM3IKMWdpHij3uH7EBSO7k4PQFN5Sg1bg62JHbx64ByZZdl8mdeCVMDBH0BbcfJO
ZgJnRQGkY0AK11jtz2QAYUd572RYvLf79P7X6y3IWcKOELGKfoJgf2nzoZXve1zrbXnKZ5I57B1j
KuTBbm4ohJnTxKTBhJxBRrABE2XBmRrHrq4ZSVXlOiJ3jicxVR3IsIb0Qi9tLMZ0xZ/ox0ZTv65c
Os0VOgThk7tJ7SSYdkXCZUusgEezAv1HcaO8qXQgqYo5jrwVJrg3fFLOEKiB1WCddKthrwh7ucoj
CRgQ64q+jfpC4UlpEG4Y3iFHg0oiwVQuXfyOqrXOe3LYFcE0OjZu6bTUc79lvgVMmSaBduPOeY8W
ACKO9IG5MtEGNOXxVAEivJcLPs2FYO6NvohsA19nJFw42p0sWFyO/cX/ziW+iQanfx8pmE50j/Lj
HDX9D7GT+V0fXaV2OPECFtOK98gYHuTFjg8G6Vg6GYA/LcJoO8xTCpeH0hxALcKMC+sUfkKv47L7
I6MZs71b729VW16ietYBR2xr45jKWxmP90n3F7073OuxhK8XDEl25LMNdWljP99CP0T+8W+F2t9M
COpLJt/2vf/AFsHPD7+zpqmLnuKhJdaJt4Xv4irm558MLxmgVcYult4szCO6epTqi8xBO4lgViOJ
L1AQ34yGCDsdWqmlrHU5R52tgWjWR0VU6+M7DBLkr9detKgC0iUBPHrIQ2xE/jHlqjVJ1K1zpXNd
AnXJHPSA53dE98SmHldQA0XqC3gnDjYrdfP7m5CssIRDusCQ6fIzhnYIhdvCh5yvnRx56LUo5kqq
jGzTxfX/7lXKl6joSGrxYafMf82zWpGmkZBP7HMIaJOaiAbqEqtp8FA+gX+4ixw4RXkTKIyOgKqC
s6t+GorHun2o0zjflqUl+dkoBTpEaHGbgLWnGBNtsI6sPvgJNebKV1JLH5p2xNZboBO/vQ5eP+PT
/pPKE2ddDZ4xKOcJmd8l43ztFtAq/+z1OIRdxAvseuHcTtKqo8+S4MoC8A8JBNEA0nDFzQfTgz0G
430uXYaVmT3OHlBYclptDMuAFqx6ZxovFs6UEa4kHc0mLNhWZdhjmo8Aoo1Q6tVr5fJWOJYuTXSK
og8w/n91yf5U97nHbr4LRVe3tg0GV+UTPnMkGHzDiqY9RMdG+jy5koiCaY8jm+loir5BZQmyrBmW
65eDja2+p8o81LSAaKntGuHfNvxJ+nna7lpJrIJm5dCwKs9oQ58htKhUQ0WepBnaOQtZHl8V+wMk
t5NyunSHq6QZQyCwQ0LOyLlYvLhCpz87qjH6QKc+5APE8G8RJbVpX1IQ01MBn96f6s3SlKlRXjZR
kEUyX8p9mWKPqXhQj4ewGMHrlGr44ZFAZYvVr6Lz0lkK9c1d5HayuqPwhxFlIDus8oUh6xpPBj6s
1EgaS9FXkkLASMBsjLbWb+zODzGi1UI35pyKgxsQ3UnUfUWOkg8ui0hxlsWuYXKuEl938GklrUF0
V7wGhzbZPSQ+LduiPiUZjBv5HuyHzHx6WvwIWa44CntdL93hmPW3c65OMP/CRE53kzuFrjxzVSmc
xUq8+H1FYD4Lzwd7TzIqPxNRNYZ/WCsyXw00XGDVfAI6m/48XEYF4NeyH+Cc4szS4gilQbiSn2p8
/XS2J1BeltZwDzkVOCOSydzJuuy/HU8mG/wfTED1PbJo8klxkiA973QJ0/YJyAJLZen8BiQRgVWE
oZOM6nQlH5qRpBIDob4O40KaFnvvRMQlrwgrDmMAzsO9jQSW7lCjQ0AAVfzmKQYswGrugd2g7r8h
nnMEOroFe5e7AjJ5wRbAmalENw9dShGaHlMfuTZ2uX29Axr7U3TQjSo8gkaNnfSyPlXg0kU4UT5n
RhiE7yi2Eg0wjjWBe4gmaDIR6okrQPCGiToeHkQbBMBin89XWsyKa4lL5WT3vOqybyK2HxC6iUYD
Q6jGsUaHT4wWkxqQP6I6LdwgmvbwXXqSpJtb1uTAehRtFg8DkNifsn1PcyfP8g71PZBor5BPcvm7
VG6eF00tBsxZXlR8OcGdZia2NOUG5WLKA0s43u3B6TrLWeqLCYyH+je/y4wS94ej3tutFHKWFoux
VSXzgZNpzIvuDuYEAvcISLuM+Zd4cMAztnGYnSd+uRo026E4MgjlU6R4V+/R3UypOrzL8ZNgGoxC
16F4pQMhQ3duPwW1GqLqNhl8D/GVA1CtBbuVi0ypa7vkp0l2Gphai7KRkUbMXhiB8Wivy/yD+sFc
9xh/L6WInlTgGYJX5zYywiq3zEi9UzpxDfMos40iVDirLEuaQoOpePqp31hMdUjP0+z0TCfK7Urm
57MhQkhVqzUGETerpsEEa5BrJ5wBXzc85hNnfLkow4HljHEQgPDiG+IES8TTjf7P1l5rn9a985Zx
wBWwj3MvlQ62+0zqXuewp/5D8S5Dij1AdZ8Xt1lTvGeTOWmavqT48i13AcK7TUvH6L1jGau07pU9
yqFoz7D1MwYcSQbD3I/Wjqfe91HvMQ7Brkn/5FM/WIa5d+uat3WBf8fkIEwmJM3ENDekN+NEZ4ZY
QLzuxEgU3KkE/woVVA7siUEvnZHGBl8SJbJRoEyRiVFyecbcXeqX1B2X8ALSWJfDQg+p0pZSUczD
14hLfBmgqiVG7KrUeFm4O/FcLXBxSbxaFt7zesVQt5YSf3s7jWRhsMhmSuRsdOF6Rihe9+v0mFGb
yC9Um42IfHYWn57Q9T+nUTa6bIVg+PRnvukAKBQJNGQ2bWNJdfm2Q14PPg8KZjyjQaeLZmEw27vG
elXzxBY/uTKIV1N5H7B2vhyIQXikKCAErO+PlmGhKoGQTiIi/6c49q5c+GSjOe2uCOcUIhr57Iv4
0LO4ZUBobtD6gQlshJqtYL53YNZWnKWJKQUigaASj7xbFXm5hsoLLMm9dJHL4VjcNFxjwkGLV1Uj
CDWuM+vuDTi8ZdMCywHxmsX/eDEKthG7fEsqfIc7PRtYXILMw3LHRfx6B4I5jzhHOTX+6nc5yXrz
QtVmvcCxkW9PYg3IQTdJqKFOPOlRJAkDNTZqp3J/zwLpHvTLBI465TQwSuudQn9TpW1vJOZivfRc
EI7qtVcvVuangZczeqozQMk55FjovFRAwb0EG0f+GBZAqVRikwMrHn0my/sahmY2gF3dYC9aadPp
CDDb4DVCHkRc7gG8Vm3/R6O03bZoSK34U+RaZZSz+8yAG8gZq7ju47Kc4f+bGoe3Gg57z6jf5sWk
orfEilazEbr5JglorSuGC4JR5SVHvXgjXmuaEkQ/KcnH2IFS1XAX1Wqy1Zes18OA92gQLeFYTKQr
C+Nh9BjqF60bG/R0UGRYrfku9slEx4DtdaE7rDMeTKaYXL7HUD2Vsb+F50IDvTGSi/NHW+gP3f1A
Tntt7UG4hG3ZD8MeiquXQBPnrFdS+9cRMhrDaF341Pig5IM2pCbCHdByLn66Z5DuXyVrdmgJuTEF
PdMWNuVft7XZZd5rL50fsYFP5cymcutTtTQE1HjO89/otsz68b79N6Bo/fVI4LhS722PM41ziTqJ
j+kAnzXOof4Cm2ReYmZs5wI2dVRjNE4R9jwhoy8997sUpqIWgLDdgE4EOjK4tGOo1zEShO8jN/61
+PQcsRdn4pmrd9/CBiJA65t9iZk1CZ7wP/7yCFX3AZsUGuEpLYTuO4ihhcfBav59iYQ4bq9OTaA5
SUZEmlFvfeEiBAXMguraIWgZQC4Hgcz3hXWC6vxzNxy+Lygia+Zkg4/lWKENEDmw0mmnelBIPjcG
K1JkXaNkwM2+ZFsXy6nbhQrXqzPBGZIuyZQez1vjehRNvo6z2wg1x1k8ID544Ny0Pd6efVT06cVo
EDf89EuQV7K0cYianx5272OXQOiGwOFVsTLgxmiV/pQunpt2bkccDyH+mWo+kPWY+KeuAN7CbolU
scATD4td3C8sZMzVuelvzRiiCoDVD5M3glOiQmFkAB3ltseppJtvo5npKFKkiWItWboh9DMTjq0u
78HJp1uDpD486MfP9Iu7DHLNonjcE3eo6eU1xe2T5nprH+K85t+ZFSfTlRuZPFItLh/PmrO7zk6L
QK5VzkobTpC550XrT1GXQ51w0hTdXOblpXewLQKhbsP66lSlxFNfr102C0DD+SmMZY2pjs5adlCI
eG8hOTnnSa4ePwzMGQLmlVSi3n/H7QUYu2ZdP02JLCGY95ODI6GQFcsFNhN7ls0Qe+20T70+pjWl
c6V9/Hw9zHH47RAbjxvC/uqNmS24qlaUAHHgeo/FlHh+9Elri8ulMtHME/j8wugCm8y/nsSA+Osv
/zUx83XHyRzxoQA8U+xLKx7WPAdL6K7E9kndfFMPieKaCuqGi1pKVOwAAjd/8DeoNLtLpyJ8tO5Q
o9yhp4oBzo0o8f+Yfh0ME1moCvQfh+eAVwHirX6M0s2AAB1mKJ6ysWEPNuNae5HIbntrtQprc/Rr
cKRA/T9eT/5wsw03kxwCfN6NF8N0JrNfAt+YJE1oDgsniOQUKRCgxVTR/IChSz8Im36opU+6mPyF
ROgk83e6AlTSldEBpgpvRNkdM/pTwrcujr1hFmu9Kbv7gT3Cztynx9Q6Mm2Gh2nUgrLYBi4QNFY1
ZG1pAQxz2RBkEFZbQyBBSXSrmUmt04pkD68dr9Yblh0Xx9Px1yN0K5nQ+ot/XjFhgsNAuUAvL4F5
Rt/DagoRxUnaA8kvBsKsS7Al2Cr/+/H2bcDqW5OM8s7soFA20umhBHYgTPx8FQjJxTEnruTS0hIA
OVjyIC4hE+phkDW6eM3sYtfnTyBPZplKM6uCnMxSQy1bjF7I8I8Z0uydWQsGcmovcltxr9Kmkal4
ok79yKWvgyBOqmxPSYZslrWWqVQwWUEV1xNHCSuGZeUaZN1bnbzoqYU5+Gmi3PVSDQmvZ7se/S6C
pQ1moDWW/Jd2ucZJSaH/0+IR9o7U5hnlR03DmTdh7W3lXpgcQxEm9HP6tj6x31WhgA6qk4gepEQH
9MNHAdbfJ8O9WiBKHWkPD4QWA9VEYcSUpjlXVvB2n0CoB2Fg6rtWaZA0O5xDRl2edLOBeOT1PTW3
VtFcANlvNv1rKaXbMkVcCZOEBgt7mElBey/aHJj+Cf1jY79r166vJ2bltKppZO+MRKTtGYPabNXw
8K1jKOH2t955EjQn/Q2mIBUwW4zbI3fvgb8FdefF4zhk5LmyftMwYKC3e6QO42NzDDHHhpJAm4Yp
wmZpXCp/7cEIDTGc0s8CFVIkBihKIkix7NjwiSBdlrJqYOjSeCk7CMg9iBnTI3eaTXpk4zGzJ3xj
Q2z5G7+n7oZRauxksfbK7uD9XzSa1noiYCMDpex4A/GV9OgxSNiSIZiYejXVYyPVdcaNKm6bRtGs
DfFOM/v5FYr6GwjsmCuNFDzB9ble4pO6FHu5f7WaRKgTT50M419wqccbNQxgTVJ18MrOWDAtPEnU
zizTKTly9WCj03A1QU2chy4caSCdY4Dan4jruKnEBcG9an3z+8bVd0W92vpWrgVpwEzgiMKrZ9LV
bRz3hgSY7ducWWVVSp83NtnGmzUrknVo2zBk2ljyq5vduUHUi+vlIMJllc1AeWVjEuV4QoDRg1Sd
TDaLtmxeTNkRhflWmxRNzvknKbEYkTA78UZjzHGOe77VZq746wPsunGVeXwsUuDBupXJEO2/bb6L
lBvsHfl96lL/2ssXHpZG04FefSuMvBanmw3Nq+aHyxAnZE9Hid45tiSHkrnFgHz1YcljADC71HBF
bB9XvDfuMjknPWEB5A8MGT88XpXwCIrj4dYWoeaBJ7HNCirwoi6UBEihUMkaHf7xHLXn6oQcwPWR
KQO9QS0rfZ7LNvRWU+kLnHhah58DZmBiyQxVU+Er6XsSCspcKv+Of5p+zYkVi5ZxZ0CDi8B41/i0
9t7znMKYkYuP+XkYlIox2fc/7LudYWh1HT1GLKQHIMnbBaa/DllzNeL2FlXMa4BLVfp5nSddVtC7
gQnwLyjqtgqCa5gC333efhBWK/mD308DHTnrL9FeWQNjY9zu9nE5yzrKxX7KKsGIjts0iiW9MOL7
UF/1CZYyyGivDOJvs0TuYfzE5p8h7cLx6v1MLXNxfZNWKDAIyoGvkjJJP5bu1m9s48wS6X4IC0fE
o2OHyRifCCmuXL3rZ6qMDU7c3R+sq/bUS0obCbQqQ5ACvo4eEgnLV+8DhmYOGBs3t8sdoEMPPA5H
G06/GlYsTMWsdQTXMs9M+6mprdSLafqB1ljpYqi4I9lax3NCCpQC3VBPmmfhadn4dgW1ectldcUb
SMj+X5a9Jjejvd4WI7whQtCsBhl/1pRPRd6XhFFfot12PN0YI61ZcyYMvhkUAUkB8UJjdm3t04UI
Q6L43uCsc07a9NzLp5k9SdnLU1eChbaun3hlkvmLJdH6j3QRbig3icPL/UrsBMfXIBy4SIYSwk1M
3Gsyh8k5tqEyqIiCeGUifEnjh6GJ/TecFMU7f9XN3hjuGWOtvjEcuH0lCGX5qflStQmSv+gSZy1r
+zaAgBqKVNKPHI+NZVjqaFN3JwPXczXJB5LZDd7kyIELjMd7O91j17cdDcH26KX1mbu8UQPYhKZ5
nJGYx00MGTAi8kLGQogofKvqe9aCoIHF9hZlH9dwnC+4QwepTuERjGEnJAIMul+OT8WGZNXE/3vS
N4gZm5lC3WKlN20xOMzlGYXKlXgoIvfzn12NYE0sPR6Qyxd6fA0j+xBhhmwjS1GxYzqrTuFapicx
suu9jvhHhn6MNYit2B4p9ITIgUdsVdlzSYNjfQzb/aV68+frEMap3ro09ee/CzuqgQnl0XmE3JfG
h6lPdiVlUMFLIoIGBFJhCh3uMLiE1OIgJJWe79Ko8MPK2AqNhh1QMz9veFn6BIzjAEb33ge9Ha3z
wKKrgsvx1/yK6RlQ56nQUcGYfLNrHaoI/h6EyOy3o404WvJvsGMWN7kB2BOnvtCwxErwvMDqhZkO
HtJyZqlUhhiGrv/4JJ8sC4s73OCBqvAPNSYYGrwBN/T6n7FB0k9xU1BFq6rsRwjE4f3uSbIzeFiA
RV5iIYsLuBJRPDxFeOUlpEnVPK1F2hyj0gRCfk8XIrIv+xg7tSHY3+L47y1wY68vVSYPjNbBaLmN
bKrftWmKfOd8LzcEBF6x5UZp4NBgn4rkxuHCxPxFi8gWPWPhNPvN0kv4RuqwCM0G5IPqcbOh6EPR
jJcL7wZ1L+hZ1ewFkgD0Sq8JcYKNPM7oqaEu+ksFJi5lj6zyggc04pGiC7M2HqKMmMTaK0xYct8l
9j51jPJWBcYqwlz/1MU2BDtagClFz/kyfWkx0CRzV6D6I+Jpfrek1sa8VRqL/fNdavEfwlS/JpvC
ToGWBXEgJVvw+TKO0w3z6vO2w1Yi7grCOV/vjgQU1VrMyJGfjVsvVMO9VPJO6omjfq7tg0Yh9WHN
Gt294DFtRPhQVF3hmkpYb8r9ACTpbsTQ9yh3PYTjMIe84GcFNItCVU5+D+O4m6U4qHKse5yvyYML
nYh63MO4MQnAuNffrr+Z6sBOOXTL1pBa70y48XWSXxGAzImmrFCb68S5hR51wh4YqHS3C2veAtYQ
zqlTKcBVVZQ0JljYrnnsmgQBlLRiqNT00BMZTxYQyjKoeanfCOogKstRGShVPdF+we4+dd3gd73g
5nvDRTECRXFDKm1vi88YnHXqdw25zbwyjk0m0V3mbpEMEwiIV1PalDkb19Y+YHUR31K9/UsOx7ij
3Eh8pMNowZaRPhtXv13GYO5ZBJnlZmjUVCiXSsa/a65bG9i3Hvsw/4knTOeiqoxVLhS4008Wz2ul
j4mo68lfyzIsCtlPer5ktt5aiPOZEL1138tTGgPSV/M1GK7PFl2kWoyDpOYtiB0pGmGwJecqnvc8
7kdDPeF8mBQbe3arEM+j8zPR4mFp+IdlpDL2VZaVI0gNwny3zQjRJoKd4IYrKwK9tiyt7v5Pi1h7
OslZd6jhfnnbb2+5YLisYP3QLPMad6k2rr36mNc+hXaLp1NTdYXXKJBmujpzfueN7kJeJG92RzgA
BQGh/GemHF/dxf86KVdJMbj4zFn1+ZDnALLRzp2jg2oyoxgif5SLKF4eEI7qNOO+9TbGReUjjG96
8vDnL4wsWCKvz9p2LacSzQZ+/lBet2wM94jK8ceCdWmD0ELbvY/eU3MFyecVPbNprYS7anWM7QqI
H1G3QmTXb+xNtIcSPpvUisdDSfLTSpwxXxSOk1KPZqQtHXIusfAW0sRWUklURbOJ+zywP/h0oAJI
6D4Zg1q2asvJzkMVGXMKd33mXJSZmk5Q+2YU69TPoyYhqAiebDmJqfj791U89zaHJ4UfiuxFfWjx
ADjsSgS3FztSNpq0AakILVEglIng8VtDKNpFYb1R2QO39r2/uasuycRZHznbCB1AyzmYAel0EWKl
AOzqy4v8DLQ0MyDQYDPNBv9NPsymXNZkyfODrfprOEl9uuZdIaMBE6mO78L9VBU6AIdwU0GFD1oS
kq/3kUNpS97FKOnE5pDsz5h3QpywzRYwGBelUtZQeo7n1eS1NuzHKcjIh66Ps2SBHQa7WZtT3ngg
tXVI4ObH7xowh3BFU8ZY+LbHvfH8246xA8bNdQN15rIMRwZvnbXLKKAunF9YNYB53tjPXzhYMCpH
oZnmALAqU/VkMJLd3BsNTbszTNgsFobR44oNLTQRaNZ6NDkaJ8YvbdyYp14+vKv2neeollbMWjQa
3iYIwrVzEBESRHkdqgk6g+C74ZJJqjf2nmMcqwhRjyyGJxREiQ+krJfVBYGDkbTuCYQH8wu/AkmR
aJJjR5ZwKkkj1/Ol43aA8qh4wVqArqu72kAoHMiCE8y2Yvxp/kfz5nXTToDfTeA7pkRGyj81S97L
WDJ+mAmaFbC8/5dJwiUgeIpLbMRvpetQoelicvJRPgF9j3nTNWhaqI/JVVoPvhty2568j4ptv+ch
+KGZu6x4HShhnRPrKRKSuph7AXDkoQjVEE/GaiCBlucTCUyfySrMf9dTi+rEcWhot4OhKKvBuybK
qvmpBCG0uXnXvg0IPg1cxyWZWPWZ9xTBgKOYe97JBtCFFCO2uq2b2EAryG9eXxzRkQVNmMul2VSh
pPGpUWf3AwoefWpnrVofFdezR2wFY0ItdYxzSOPgXEC/er0Oz+9DikwFtE6sjmQK/e3t4lw5JIJA
icw/AFEnT1dVRSDDhMB5xSlTzhZ/0y69NYEPWJ1ucUA3APD/78tqEf44N6G7fcaSfb7vhvU2BfKM
2XqDMwewiefFPYld9wu7WDDLzoDCcRCFaDpbo296a0cDoTAbRJIqumrMAU/N8q0o4IuuRfI9NRTO
pAmjPMHH5A2sMZn1VfkR9fcroTtMBCZodf17robntScYst+eEezFt2oLFWvt/RGmXktF8g/+j/0e
qqeEPnUkgzq9gZVpY9PLC/RdAne9LxpXxza+sL3BbyBSNSuzPdodxfhov896WNlo/EYCGDddMfDr
w41x583iv0CFpxW+l1XuLHlqXLJhzvXnsrsFPQ66alGC79XKo3S+Oml+Hxl4gwrWaGJJ/lAJbFXa
YmYX3zGMcucWi9nMUqheZ1zCq6jE5Q66559+ZM+wlgIps7xtO+MCtz/Mv9aaXvkzyjezZqUz0Pou
FdyXhjjFzADhsUWTYBRO6cyX3ui/II7CtA21jYJAx3HniDgQeVj415Z0mA9Vip3xKT4cs2pt6Hwl
8NhG1ob4rrGdyyJuq3znjFScYDx9tqYn156Kka7G/yR99+7VpolDqfEzmyNz9fh0u25MwWXyEZ91
5gHYmWsCFZnJ9GKoXXmhPV+w6nGb3tBdjybta4SG3uI3gm9umNxV3cE3MM3ZF8KQH0y2auLnEWCY
wXM3n5S/ZMI3gV4Wcv0NPCMQo+9f1Dhazh1T5NxwcBTJ5BS2vFZw9sMO72TZMSJizfOHSCR5v4ra
Bwepv0lMdtZvG7YWdUWiYhIR2FmSnMP0BE/Locptinqnf/LMGiGv0frSnnD8KpReBVFvBc/Z11YL
YjZntdNhkrrKR004cIOiAW1H/eoN0ypLGaE6wDnMrIs5E9emuFzP0vkBfrfrZ8iSo2U7uJoAhTZ4
FT/bwDsyUj+2WxF8jfliczSAvw0KA7cPqc19+DXpkyJpHKQuSxIb0TF/Q9nH22i/Dk8jZRT3FdnA
ss0XHeX+I8SyVOYpjH4FeWaSdhz0pj5ICyb2H+g8KUqOohZq/XLG2P8GtU9ctoHET/+Z3AoE4VK6
2sgfTtKnnNV0PpjKt3LrhoVB7R9gFp4igZj1Jjt7/5gNnq3cjIU6Z7GJQGW6INAbBxFDiIZ05V0r
l8wxCeDr4QGhU96osl820FbDEZ9GJ9fcsMqUIlHA+fZpFZ2q2J6XsGQYKLIM2Zgi8+REF++YXVrw
3jkws3HW4wW3FEMXtZddrtSjbh5lOg2Kn1vIWiKWvVm09eSzqDUzxDHy2fcDgyvxA5hgbpMmR7FM
t66ELVZmUoBG7lgzqV10BN9pqj2TpghhBCqNmNhJhPTTx18RXm9VNQVw49iM4yqMYb6PbkVfFwxL
XOTYymQ0woqVheT6fgWy9mpvuXrPh7aXfeoBRC5o/AVS9mmbeHJoRThzVrWJ9q6HW3s/xhfdZ7/u
stsMnKrRK+KfmANE40pVNGMppr+YxxatTHj6VhsCy6/iQV/mxGAitcngqvPMgdASreskAHJIJEEJ
L5Ck2Ikw+3kswdXjz77DqCXO81Tjv5DKZN596CCW/FInU9ivZxmB4rL8Hdfhu7gjijvA2yBjCHRn
+xZuz51z28hyLlWKlmeDAmdGQGLOC4r7+Z1efxrgzAOuhQtmIGdUgB7IMi0F1twVaPHvoXtK74hV
vAFS2fk8CWm6M4rRC+HULQgc3TbYqJ7Oc1w2zhAyQxYHUyQDs9X+Zl9QCyY2aj0cQuXFFgDxCu1u
CMVVzbDcmDxWc13cGi5kHU3fTeevk4/1mQ2QFM1eTu/Ymp9wSH+X3lRsgoZrTkZ59bXzgD10XTwI
7YpLw8/VNynn/G9o/Q0DDSzlkn3dNEHh77H6h6UPhj7qJWK1XOZHw/dlfxr2jKG7Aw7FlPZIIlki
wtEmp98EHkwtbEhl3c7EAbhZ0BHVGt3LRS15OcyM5q0aToxBYEc/H9bA6vltNMKgWup7GFoyWzzS
PrQsed7SVdojLwSjm7fShsQtn6iRYr/HF721uPTyJVxr2rVQkkBPjxztsjIOJbrDjFXtA73As39/
SsajCPElnI3xi0vqyzMqRNox8YjTX5OFXKf4N5lXLeB8zBBM6tfafHAl9XoEomiNrqz7SRro1pm/
AN5irpgT9MagZ4GxJBIuMH6DjH5LFri5BfYiSSPgoonrhRtkjQ0lpuDwVg1ISdmidDHQs2fKaUg0
F84bjODLCLLTcOIa6yYbpKrYhGGAMNBR2uqV1cf8dorx9WXBK7dIfV7ZrSMs8u3L34MGDanAwCGE
Oa2Qofx3hBfjTxKI79vSt/yE3fcvOJjlsgBTect617eEi65JxFIT8vob6NpawJxzA1Ba1SbvKFdN
UtbEgbtqV+HFAR3lzzApMZ63feuScpmxArM/1a4CvSZdhqKdM7kOMzOymt02G4QkqtAvJTa7jfGo
8Gg7NdSAln8fEgc39C/oXTMO1V8yy7IJBUuTnFymU6Js976h7veI9V27QsM3vLJTA9nat6SjJrbX
AW6eGw3fqklYB8J+TO8anxWd8WRs6L9/EaRCYIdExXa+ggeHWCcwnrJd3ooAT7Qu6Y7Z8ZiTFwpQ
XWLFUpAudgN8BM8iQMxnaKig0zf0yzDTVtjUNMGews0OXXTlfpQfRF6IbQ2O759fi+wcAycyTL4p
sFoWnCUAjCrdPVCW5QFsYkkQB1IVxcTSN2YLQlI1jB6ebRW8T8uRoTBFM46e/UiofESlku5RXt3R
RuZKA2kNXCnwEEi9WsWlPnqUkTk/a1mr5HYzvQn5Z7wD1mjI3LJXzn3ZXggyJn0/7Z8N5+D2Wj5C
Etc0RLE1VCidAgbuCZXOPI7nmD876eL/tL2Mb9mgeuUGF6hhmopl3ldHGIaC02IvDr3C8qyWPA11
ntJORuBtzSyip1mRXxSX1oqW3ttVk1fxE73bXQRKyBYZZLYLvFbJ7QUKYcjKgiYj9houLyATyQUA
FTrUvtfyn90gumSw0gU6oKEnpuj5Pum5VGH+RrJYyCL0+Rr+0Wc0lv8bvsY4P9M5WnNuQO4QwMGM
SskrJbXpQQfSGEb8CiLpKxZnOcNPq/zx1uP767azQxnGhNQT1wCVPn2I1JgOs58RhU2+m31BE6n0
NjwE0WhUV42ovkDYmP5Y9+2sjZnKcWI1lwVFnxtOCkHW/lau9vYugOjvylRwYbEa5VMO6p+e2UPz
aYjpb0N7WH3L9kVdYwycoSpGsalq3he9pi2v/N0xWZeIbCh7kSuqlyfc2aBh5gdwe88e63y+LNNI
Q+cv4XtxApBYxEacJSeAdMkZxxpWipFPuZZrBqrFIiu+H2XpFzIXhdI2msL0a7Ya/299xdI7yV8m
lafqp9Kr4E5a2mEQvqf931l3hRpnTtDRhRkyHmVYNwCJmTqTPfijzEZddiHulzW3DkY0I45WYzh1
cOMg7CFPruB1xl3sFwCF3X0AC8ZtGM2+2keo1+bAFXy7Uv6Zs6Mg8Na5AKmB99z9re/n2y1yULwg
1CQCcfB0dixNs4sa4X+RoClWqSKjG3A2YfCd5oVnEigdeHh8snESMoU/gFdxA2NwVXjys6LasXAf
Z/I2n8kkkObF0bDpPyqk3BdKdgZ5cC3TtvWJJzGYLvCybE8nffUuxddFuXHiH20dufRso9N/UeQv
ImcxMGuZMmoJzWbre2g1tyRT2HyQcALC3KzNjN/kQVamUrIzLWnuyfvnk1UslfNjV5Oa6M0cg+Ul
hhar8m4jAlo6nFr91maBQyGR0IY1aqMIp2Gx5M4kqHoKPB+9LLGbF7MHf8y11QG+a82k76s+WyV6
DDxWXD0Y+y7QljEZd4ePpZpRUZdBUu/EAEdprLG6xIdRjub0j4w/JBb+I8ifAmuH0ShqX5XadNPm
b/8GQYy937ZMLL4h8gfSD0T9GV9cG82C0Mii6iZUm+yN5v19mgt3YoYA0vrH2ggIfTX/SVqsI7Ty
geHGCEkx1SLfsJDSGZlxm/vEKiCuQevsr86HnQhtojVDkh5jzVm2M98UnjSym4upA5ykcomvrOLP
vKODalzuAqaBHVSVWWNRbANtxvtKmW+e1L7tOY/N443Y2te2CJMbSDFGQNaICSV/5XovuKRbB8kg
eCT+d4NWMaHzqwDELBbga2TW974YieKMVaDuEtxEmUwZV5zkh+2KAVdWmDXINfyCkiLdq+VHRo36
7JnAEsa/A8cLhoOk7ybGqRHqLXv0cVQSn5MROmAn+GNRV192FoReEVqBeHgAvnF3BwICG/JafxM9
lvgI4eB4icenASQ213UMa1hq9+pFKXQaXUgmEj0c+xfXxMxiwY/z6Q+pcKVY4CS5dQuZidOzMoeo
/EMAJjBVTDm1tYyndt9QoyQxdFlxixRe2fibzBLeMrDdEjFbBmkpNRqxJ06eIXpx7y5/8ikrjQKk
pmIU8nTb7p/BrPf0dfOURlbxCTJDEtPrOFgtYer/VT78cZdyrtFpZJrBeOokMwcL+JYLKW294ENt
F+SxARXUAVMukKQgwpkIYpnVWDfLkkUOfB/an05veHeFQhLFv3IVfjTiUqERktn4+ECNzfqeJJXw
n+3OSYU5bSBRC1IdTg6miHAQo4Z4f2B41m9/nImK304bqiyZixgVHuQxl4rBNXBB/JNYmjoJIQoB
gAFTNSrq1JzqtjJbZV56DRMWxwKySe+bDVbC4lJ6SJjXiLgEI0GSW6w8M+hAGD5rWlsJIl1g2hz0
z2DsOnShdsdJINW9cUqWGCIkc0zVggFSBa/0UrRK3xcDvlFe0l03hoIFtd+KZx2EUb5URB5VwHi7
z7WlNUrprlD4LJ1ED23wVJaQ6VXGqze0QLKCkA1DNEfBgxFhuoIiXZJzk/2u7MhcjRlKO6uuO/44
8hfr7Oqt9zCgW2EUADjI7Ba+yXeNvqxY6Ao4rO8hBrV3z4draARgiXrmW5PKv7KCGRa1OKRw54Gw
uqBkh8vi2WdRv17uhVlnoVJdDH8Y4J+wb0UXfuFDyhx2UqSfc0ruVqjIl8PuicuGGW/44SWcrWtX
xE1sXyX3OMpIX2FrBQUCu6flh+cc60WPR9+vTFUGSwIDFyjPLQgGjnY++MMRoS6T3NS/EathTi7y
R2CYqquXR4TIyLJ7ziqz2AMNroyAzF8PUE9hObmzF0xUdMZiAnnAIn6lb90R5QC/eGQptEQs/qCJ
Zfs63s51JSmVg/ADR3E+jB4Lnv7Fsxd7+mRr3VyuASp8aGW6nROMxmtZ/SmHRoIpNP5TOEYuRTCm
hCjREBzknilmWOkMH2A1bvoEHA7GQLhQ1fBcY0MhRvcNPrJrwsMlzYAOCGUkP6/NaRf/t8wkfwHl
YHUDsXJVGmUTX5AQoTcNbUBh/MhO5nSnLTh93mzYGAQ8GD8v1x5KyKq/r5ZKXv7i9F2TcMKguSUv
CGss7zEMHJxAdgx6kKvQSwwwM99VOZDjNgqCt2KuesnE9yarhj8ZBd60M0v+9Scuo92XIxRU6QtX
aNt0GjQ0iVfmyHR8JbKjgg97AbusfS6ni8IsKaxfkpuC/tuagvACU/evu21Du0mDZ9L/JaX2e4Ml
IX+VA3Xa5bmd5Hd3xpJYsVRzeuGr99thqGy3nxcSmmWanxv5wirTuBvOIvaZ1kGJuZmgMkTU4glC
eFe2Z82q7I5HEeH5fQXJ7y1ksNsMqWPOkcfmiMBtPZp1OGMRPKcj76MIElqGtkuxWeXB1Hzl8uk3
49ObO0c/ggdHszqUhTKPDZ57HVyLG2y9/wa96OMwqmmWc+arffjUDSHlbPF2wTzj4YMEUWhLIPm/
5sNDwkD844om/S4ptW4pzcYbziCJaMYlZrSV8UJVj63eX43WTNoNDlw1rzGUtDRxZxftGaHoTnz9
4JbV4o+XQ7X2dnJps/5cCWED3uc1wa2ZpqO+D8ZyfAwh/lNHEhwJNgwDWkRoL0ke8QUu4VX+G01c
EDiXFW3jzpocsTbKWiNpkEQ/N5TihZBSFnL3kSVyWXBvVl0JqYv+0yUzjHct6yWYVTj3s8uHcC5B
TxBiMdXaj3SIMN4L75WUWl8RbIS1MOT68BeCFV47jyb9OevGA/y2l/1JLOQPx2b70FTntqfxExVv
Y9e3KuCWc5gYV0wPtruXKyblVTrb6N8nrg1y69Nyi3JHXEJsXfZearWax3mAlebgpGC7xspiIHUs
0c3S5rZf0zPHGsmE4Vh0sSss/afKep+eQwv/fI5pEWfYBv7x+tJFERGQsnmpkLf/h55ELbETr+7A
57LSy8LEyns5m6XeegaGwne6CLGUm9A95IKEEQNRVeTcO7TlA0HpiKnttyqBkTpqB+a2VZSuTR5+
sNHqf+UVVQSDEn/EDrToC3rA5NzUjn8JJuqp1/kMztO13ukT73fguQIUj11jMb8Gh8/3C8e1fxGs
IodSNyyQq+0ex7gUcyMQHgmgwQ9WTAFhketK/9DYZ9l5+EAI94xgGvY3AYF88l5AI9Wr+y6TzhHY
vbMZ3NhU71LHgl3WQMKefqLMc9wfFVWsMKYCsDV/+yUYBuLhcS3JPJjP0KEMW+wdPHPSStRipOqZ
hcT1jKRV1SM8bH/Sa6w/+3tOq/dwErKjEsRFntaM64TDNvydf1u4qHpuMXN17BEg5ZDCM53T+C8d
djZR4cgT46+dPcPsyGIC3kKTQsr6EGjVnRIrYVW38+ECnUoP6B9mwnCEtgqZOryVNIRP4rlwrOTP
Jd0+pIfxgqbnCG7UIB99iBuIOppnEKrqYj5wJlI6Shef2Uj2MK60XFkJus9Gfch7nOX3i8dZMGha
n70CM/htNZHriwrT5xxfGyci5Jr87upRRypqUMo7pARA9/53ZsTmttzAmV0Z7KBkyxcNPNLnOOAT
KZLm7XmqT7Bh41VPzQvAahNuyhjaj0kMWWWoMjzfUVwq+7Hz7o3bd2cRTFwryKE5NuMkYsDSwD/T
lVHtoRd3Lu0vN/NLktoLTHmrAF6WqD85IYO7bykQi5R1gvwuS8sNGensOJ00NrzwJWgJcKX/kxZt
ev4dFQzB6BzXppC/YAUiB6aAzVhPL9t23KCrer4loKJZyv+Qv4DF5z5JVCBVI/UoOQKjA41UZ8Q8
H7WZnOhY0iDMrZ1quP0Au5h+0JXz9BXjAxyD6IDGF+rOBo8x1ep1UfmjZDcivJ00iBkUvOAgcraa
e5xtGFq/+DTej6dq1tQI9AFFYUBL0Oh3BaZtnuJOUCq2uY29RKqCGGMq1JU3phGpsEJP38Zcn+Gg
XnEwD0SQup1vdL8SWAaOZ1NPWlyaQAbKeRwp0FtKne3NQ59HATniwotFrx31L1OEKdGUultcA3J7
l1se67mwDb1FdNbLR3LyWgWABXYgbLfjn0RPAhKFxW6TvLTudg6sY8/MZLlwfLzTRBYPftv5xX1U
xOHTwCdo6cQZvhpp481kmq8R9CaMEfMFBrZl7VidCZM8yEtsAW1deYenF5XDzYso/0IdQMeFYiRl
3yM3vkhthhEpq6agRoVs3ySN5MHKJb62TKGOV3b5135JHQcJ597+bxVpJFMkIVpy+qEUDZ2pc2iN
gAPBomntZIVFOQDuEDIGHDiXSQUKCrMGP2KyY6aTd9FM4aVINAnqQmQICEy6oIsj7/iBLXMfv5Jc
YvOIMnEdXZ1DF/gov+hE8HKuHEfi/IEFrX2j2NFHrIJOBsXQJk8uHB0STG7eVZ+9OpjQUfeDJDmc
7TuAcs6St4Vzynd+/ggNtAYf8A3IUHRSLFLwu+2DsDioRsb1gKf1hDwmiaO73uuhmTkseqs1AQvl
4ccuQnVAUGYur2Bly9TG342jNS0LZgxv0N+c3sUvnMUbzllAoCe4VcWj7203vJ3wM8r1I06uJhiJ
iYY+EjQDaDDVcIlFSgtOhvhtywfNXHyfNjRD42tPV69+B0StoBtivTIEkuD1kllcwrz9tvSlfO7u
CVuK5nV/qL1vKSvDL1L6vJ9CnKZwtWKl8hb/XBpDLtMaBVL+izdhsGBzJnLK8gtu8fHc48KyrP5Z
5+8s289bCOA210dBVEiz48sje66Prlwf1oxCD3WOr8DqMsqk/RJbHxVr/bGMUxw5n6uNMJN1U31t
+QhIfCV7pJBpjHbZQg2V092jeKsENGQPR3fE32vwTfvM1urHFmjR+iKtN1FXIxXEWIrAVCZeDj/4
DN5Ta5WvpOguJcVkyfbT6PALIeJoSS+ixBfz82o7ZvcAHnUq2clXr+wLytVToQ5XB1mFsmDk6+ni
uY/6HX1NVg9KaCaij+oQeaUVFHqKoDXjYcu5va0LgWyMnso9tFCcjcO+duqMJnKP4rlLO7r6fDy4
FyYpToEtal59IewWItYeKpicyodgZgYH8/INu6wW8dWBQ2oZAr+IfO3UwSxuovhIZonWjCtDg2gQ
IIOKkbOPiyIwo2/iluG0K5tr05R/wdCsObJz/SKiPvorUoIwVRtYjPQ/mCNCZ0xr/vUFBQ3m0arK
7Hzr7P0RObYMl1zpd7MuttYLQHrKnEwdxoXT1VLWKfsc6X57B6yG1g/wl3YMvD+DMFb0OxTGpn34
eYR7PbfW1hCNpCFYjahmQ+HyYNkPm23FrPMPY5g2BBpr6NLxJOAIb9NGOq2cBlCH0p1E6t4FOHQu
V9BQdmcaRYaMjk2s8BO6QA5W8NFMCrZBDPT0BL3UxR7RZ5JcYxyQeE+YwSeYvwjmiMYICC3GbmW5
OCVFs6oUHvXqpGqS+PomMjd6A9gDjzws9r65tv55UQa3ZFLBhUJH77YP4AwTohQfQSCiZnexYtG1
Az3IF8oHv3pYxRRmGnhVSjeNYNlEmXT+Tu5EIqslKza3d14S3rhBPF9k5GnUvDlzwsc7H/bH7+87
SNA0+sty35tFalhWo2jwKgFGegW/yQ8cVAP8eqn5yek0CI490so/Uyr5KX1D3USP7tEfI3OJsVyP
rlo5yxaq2DpA2+Iful0AnGWq9XzcexGUNFl6EpsOhiWqt4fdSjIdHlLuG0kid3HDEENjW4qO/WO8
ar5bastP0n5LwvpMG7k9KDLqedJpO0mencyrpX/vrE1BWXRKKOl/HqgxbnkqR7S8wY+0FgAdqmlR
BmFWAv8hEQj7DwvXj/6aN0FPa9todqul0igmaGz/zD9no/IhpYk/tEoEBLp/MHu3c8Bj+J3JOpqd
ztOSwSav34Q7yjh8wAKw4WMNqfARbKSXBq6nZgA7srpxb4wPLRrkWQ1YcX9GT1zmg4AfIJPuUozW
v1/lY8bo0NXjHI0i1kiqTPvRO2PhhNU5qcC25Xnww90VmLBIzSm/KaEkrEldiBtgaMClMdBpClv8
GTFg8xMk+GfL6lPQPF4i3dkSaaVTF9/Sswqx8X+5oiWh5wjtotAsIG/IDEMpN7q/rh65x+9aAneO
XjnmsxjC2X6LS77qCgFkIghk9c8QyObdM308aoBE48molDaajypVp4tQkOf0bU9Wy4xVNVul/6Ls
Lny1/myGqI9k8PG+t1twLgsbFfBFXXkDldpG1YiPQ1oxV44f1xwMrPX8qdkbPq9QHElnSpRdsF7k
GIXSzczqTSHDlhY2NpiCNgZcZMh5S+iIhEVBHRj6sUudkbpA29p8sVhglBKTFKyE0ulb4UnAivNW
SPgrjzQvYGVRrMgfFfq4/wFlO7MEBlQ6Kqs3nJ7usbWCLnxO2MrZThbjDN0hQZjmat/img2tUFD+
JgzM9+JWgp/GFs09DZUxKlv/5lLyWhSPwdBftSjmZjUad/USMj9pD7j1diZC9Mj8ABdV6cJ2ScDn
AacZC4f4ikQ74cbjF2F/+A7HPopL2IuUpivg3dgaP9rS6GEf5j8tBHeAwCCmqODFxStKdIur1bdN
7FNufbqr6c0GrNQYygGuF6+lRC1VY3wXn4kCbcviYBKDdcsNzhOx6xxIPhIMnOVKcEZVlnGFmSiv
0a2XwVyi9BzXTCYSXfhJZQa10QvhA31UqROzffr/LnaqgT8cCqf8ZKemXMTNtBj1lFzEMFIvLPih
UlIae00z1enfMvhuXE2aJjTZy3ZMXPQn46K9E9CK1iw9nP+GgQng4bmT5QTmsX/fRToQerpAGzpB
bJrCR/v9qKPjXa1s/zECJ3RuAA/Oe+BKBUVixuLEzVzHqHNveNQ9lfcm1bcRnLJX5MWt5vOBvS/j
eFit44556ZhhZgB0E88YE3upTaqrnRtg91LuHmaPumkhFyMBFUBSReebCNKv0IIcwqNKaVMlKO4u
nXBz4rxmiloAO9GyDrzNiCLAZXImQo+jwS76r/QAyDzGClBX7ttXnPjFFZ04VofQyxMgt8c13VNY
AURx0gBSIHy3kAf+QumcbZUjmthr4fwGFaHCdnlBQPhVPmHGaygyF7uBBT3LmDOagcYqBG+lSN4j
bq+D+UXZ93x8LYiKyWnnHR+rbjNxGTHlsqO7We/lYrZDPUSlzgwxY+XZu6Gx5h3sTpoFBxc1gnCc
DelspIu9+J1IOO4/CX11UTeT6F61jkEDCKMpaEHLILfG5F10dhiyKmBqPXUSKSlq7mnXvg9m2eK/
owWpjEl0KoGy34XW2aSyu8cVwYakgD0P8pxqfiEK9kzhRleVyVF+HhDUJY4T51GwmpERDzDYayA8
1sZa6VyW6mdCT9HBHcl+0OPn7DG/ook75wSmReX8JjokJGpId7/kS25aY6YKRXBCejhRXriCVBuf
x3s6rDYgmK6z9kqDqmKuibMqxUDPruZDkVBxYb3mR82HEkiQJf2RLRzylCcZQKNEwn7I
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
qXwUbNWAqYbdpqBgu5V2Irr0yIHokdWq4yIsYatvbtHKhU5sTXcicxiWkZwMlmh7JxJXXORLT+ZU
v/PLV06P9w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
INsIPl3meZGaPEpm/0hY6qn6pNkmquxWy2FiThgvPkXiH85UtEqY8o5v8IRoHwlNbiFMfARYDbEO
+OZA2Z89jPi7vSGZam1nQVpdb9tTe8gy3sT0W8L8+/zNcgLhbWP9KgDZMNF+3YJnaj0hueORxLD7
CetUAimRvUF+Ldr4nyU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gJNTE+b/peQ4Oto07xlVbEfbFZ6nMfBGBuiUK4g+q+PLYtJWQI7QotLPwqtbFK07bXzvTJuyp/V5
wl4PKEJefSdYOEbPh6MIoiuvoQGJTFadYzFpMqBoF16yqhXJkL2oVtmXvJfQIITgSFazvP3qKZh3
NjuPtF1edJvfzpI7PLpFpZGoayowx6z/jtYsnIk2GP0W7YdZ9cOlkiSH2S1km12oKXLOaR0rDUTJ
ebEra0Bgy/Z3Q2E/7BECOXrujkXocR8xNi5Eaeaa53/ccDlgYYbn9NCrztVKJ5qtFbzqTQTW0d9a
mJndrp56FTBESQa//wxKfj8ZblMcoVBhTmzhNQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
xGHFc5dhsERwTBJ6HzSxtgI4YwpmHAsH9SafoAvaDa+cI2KAeGL0jrTiG3tkhsE6iSwJrqEOYnBt
n+EBnh1QW0+XSDRvU22yYrXld4AFAowoDmmRvGl8seLeA88PptewzCsn0OcE/MP4++TlNv7LK5dv
mheDDGnWdYqkYHdJIIs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Jbuyhmw//VZkr7Ws9+6WrN6Lj7dPBf/FX+UDLxKbBrhbv56fo3Y5D7icn71R0xbIApuFFtR8Iwcm
uySbAa59erYexsrtv2JwyehWzp7rsT+wE9FVJrZ76BH99VmVzK8R26yYJmnQOxniTZ9Bpt/l1Hgp
bqR9KddxVv7YR/TVF4FIjFACcu1LMYgxNBjvUjYUdYT1kFzIT54fa5kEBMPS2KGJrfY9RdbMnuHO
JIGhONlUF43KljQ2n+XLyCeaL8y6a2Zgqg+6lrVG6Ztpt3ZM95CTfiRQvsefR4QauRmUQSbN7I6O
wmyxcB0504V7UGeVSRNaInvWNlHwpFrgxy052A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19488)
`protect data_block
ZOdI0iP37J9pIcofeEB28BfxN2U3/rji4ipjw5lr6o3x4jhbCjwb7Ztbz/CLVL8St7mYcvoL/dYq
5+gWUzsl7Ydljsakd2HM7+lvdUDYlMDu1ak7l4pPaH7afx0UDQEPoC7zbAM7mpb1xLfrpqGnpVW2
JbrdFDxT9mszhfrRlEm26YIfkwPke8Y1y7yypDB6JxxAn1+nYfiPM1gklBA/wAmNFZ/fUDPztbOx
fr+b3oAiKEicuQhOXDU2b2grmWbhknxewEgKnKv+W2/jdejqfVh7P4/yV3VnVWs4fWuMZRv91LRr
Fm3vspLbkewYDRcreiIAMYIyc7Rt6gqq5p5+awdEBeWb14JtRbIG5FGJRFY6yuZDzFP7Mt9HWu8v
GpOIzL522uTZg9CYRRXFlBitsgVKBZiJy0ni8tiLM51tYJMvrl9gigTn9+YckK1bLrNGcxIrwzjt
nHffYtRVHgweShPwnVv/aUkIiUM2O5lqvxwKvs7dzXxv2Q2adgle1XLlAH67+p1MgkWk+mbXVU6H
wJUheYWopF/lhgFE61ivB1qTJyd6j1lMaPiKTsAAtEuxaBfbCEXNH1T3wPlCYZxUtB+okycwL9oC
coCvP2Geu8Y0Z1mNKu7u0R8xw9OB1EJ6GRlt3Aj7C0Xguq6pyRnZrSTNGRaZDZe6PLh3Dx2Xdqa8
Um7mAdWU6wYY0qMQxPOmrYxh2n1XILRKUR+dNrHLwP0+8SUdSN0cMr5S5UuoX5Ob1ppAwFqm9KEk
6ifP2WRzfl0YqeUpeDOGXruOl2JKkdlldvfm2LgjUXgm/Ei22Bc2gPEmFoRTYyr0QKH9vH2DaJDW
Bxr27qjuywr6ffYod05Czc6HCqt2BmVJbhic5tbUV1TJs7vYHLBZI/LmngPRp090E12m2t8MpsaQ
iOfQQO5U4wLXFut3X12TKMAHeP7k2TBQwGDj8J+4qe5FuoExKXd+WGpIA5rWm83BPjZb6k4s5aUj
nH+x8zoZet6NMQcvzm3mHy7vvXnqbtFBC39UEXGqqO1XNNaeNZIgigmeCaA/C30Zp9v8TRgXqiWi
g9NM40arYrmkXiDwNOUx9Pk81z7g7JAGAtzIdlYeCt7a+vbbhkpWODL21g4pWMDJ8hepuU/Ji6CY
2VAtCQtkpi5p+tunmxw3aRdrqSNoPfi8B9Y3SgSgfvBGzOPonbaDIdGJJEuxcb29Hxu6f2FLVA+O
KpKRALtdUC/kLjpzkkJ1eAvNARPe0fccPhw9fweR+kIaAncKZuymXizBwJ+IVqoR+rE6v5PtloS8
Y+9zQQ6zStv/79cXQQ1H7dmZBpqdeyQj1Lyv2lRAcC+y8t5Tjv+rcg1JLydWS9coiEt3mLsLhuS7
mteHH+MtWou51Ez4DLMgXkanfxi2BQXV8dJrV2tNEwySHkKmER9y44AVhUqEQj40EMGUWxTxInDA
ESfN+BZgU+1qhi6yXqdSHiDd2J5mfapKajD4w28dQwZ1hEMfSWqRyPObgUHIzd85zk5cToJP2g8i
TOJHuiObOhXQWiBtYIUms9teUuGI1+mZIy74ikDrmh9KcMXZuV54+jEfJG/F63QPQPwPlbomNbTb
t/QEWX0gkdwe/ZHejgg9lO5KtVVeY2W71CPPS7pBYs55eQFlDv7Y8tsi9buPuoF01KN/4cyGFtzJ
FDWRo0prEZVw7QN1HyyoGO+OgCWSJ9+J6cgQ1pFodl9NB1TphCx7mWg2t8aVFfTkQnaFcfvcpusY
6Yn53kU9irRsop0uTzTea1wKd01tWzA52vKPnFE1SLb+Q5xwGLFAI+xej7gm2ooEwlb2a6mSYxlT
YxZtrtZwBN5i7j7UO7FYj7rNr1E8Jn6gSErhxJcgO2hPdsx0RsuSCvWGtefN/GSkrXQesBzAdu2Y
mhgFEEk8LmYSlwQj1rDpWCCr07lzqs3R0y13S64VG+aYH4l8gIyd7vL9LURq5kOyAo0Hxhp9uvdP
JihCbqqBK11Sr1kXE3cL7l2m7U7a11LRcNLMFJDrTzezn3/7INa8q36MwZ1eh0SHcyQaKutkRd50
h9UEA+lnVTIzi9VjSwe5J06ax+ANn55f9UtPIRGqQQOuRkrm95mU86dcNeoqKAOQ0VEcQUR2wwLv
xO28IqToexdE3JBJbOIE/Acrz+opvMl3gE3T1t1CeVw//jc1Wg22ZfVG3niStXvLtetMtZA1qgdK
Hk93Hk2AsTdMP4EJK8O5uqpGNGrYV2dD0YpmxSfDUcHapV0gXDkLdn02Veqq60L+VM8yAs+8ZgDB
AalwWM/OOsLPi1kNzjfoy1rgD9mbQIPMx79nfBn0ZYOldkgUm+4pc7ch9ASgS/UOoaQobUfGfTxh
DrqkbkoJY8DWgvSD3LgwlZ+dfTqLueqxJaGEf2j3CPrTWN53pjW5GmsjM7kmwd49yWJ3Y9gIDacW
854gKsux7xL1kQ1EvEbIpzynvVW8FwUSKaQIXv3QXQehbvBNe2+NFrG42fm6Bt1Jnn2EpTZPmmMJ
BAM8y7hqIqJAEJttbS+eO6WqJHTXs3Uj9EfGLVVQM3mk7osvQtCw0+6qgal2X/MGFRFc8Jebq6n0
L0aAFwCmGk1QX6Ohr2nM6o3xqF+a7E3y+WFlKuvrDsLQzHEJY3duKaR+E4vONhvRJfqUgvFZewMs
0cD0nWCm5Ka/yfI90gTofvZi4Fgk24utJcaOqVqBCPGcu9MaPidFKgKGFnyr6M6mqyKQuEXbY54g
ifbECttY050nG9H9z/k9mdEuEHLhrMQ0kLmY5SAR3JiFIms8dtKPIDChKlPIRgI5ynAyoa9HiAmA
IWmQTzK9dkUvKE7S3+mo5SoulQ3B+qkEfaitytlI13392Drr7F09ThJgADrcTyMsN8oF32+AXh70
rpc6mltRk269YM05X+jXsfTNb0bO6Mc5eAesoLYSwqm1CGCb/HY5RME2TlqNUZQZPHZI+7Jo1wwf
FZ2e/pehzqf16buKyw6zBCoDvSJX09g7wnzGn9aLKIuRKmRE+3TgvvHQMLK2WzYKKVthAW5A5pPe
rRZ7RqJ7eAKRNf27mgY3XnVA6D+tK8+N97w+zQKprfVjpTrZ3qwpfhHEuzv2o26vH7ExL9HxN2+L
cLxy5aArT6gdlf9cyhHLLUh8XicnuHHDW8BsKRtq5JhAg5zTf6KJRN0uhArS1djeg4MgOr+2G+8K
4gapi6CGS0I8j65GpZCo8ZW6Bcgc3i0BRKVprsXfScxkip29co0K96l/tGe6hc+SVuzX2pM2mabv
KiolZIb5BUaHKV66YIoDnQtgg/dJeCPkKt1F8a5FfkF37NKOfsYsxG49crqXmFnW7t+OFJarMj71
ZvwVNmILzHLaNJrT/JOOnsVBqxvOhqWB93VDTcDFqz3eooibgxeBW07NBVLwzjqNK6BdFzbaN2zn
mTTnx2iq3oLwKdblWBqJtUF3EbYDtodJ52Lq0x0g88JuSDa9TjhY9PRog+dv9KcjX14bMsKTwxLH
7kvjetk2XsiMJPW1z+Rn/7Qpn2fFsjh2SO6yiUj3lwxIlj91uK299l0yyu90Xud+qlvA5OqPm17c
wliUBU/xZso/v2DmL24cP+KGT1LjyylAkqnFx4LKM1ZGmlG7pPNW1MlXVmQ2Ix1Y5vIbQO/ck67/
1DkqUFNDzljtYy/UVtBSJptSsr/EQkcx40pNjmOO1AFtca8Y7rsc9a4ilBz2sqfQbcQvY1oEgLzw
xHnX+6HLkz9u9F01n8Pu8to8TTYoF88QkE2xrpE/s1nh7eeTcUydzoSz50VNK2Dp+sELeYyMLbPr
quzG/O3SBcG84HmftvcopYAiCkvKoH8gTwdWNbP+VeTr3gu/se5YPo4Eh64kGMwD4s2pHI3C7WjP
OHMe8FfgFBSP/00ItXE5PAgWP46iviqBvNLeXChWU+oTNyXnIuAAXEE17vYDCvusRbCk16RXP3To
v/LDgUlNiQiFZ3MzaFFoE0cwNy3GshCm8sNTGQaXOybw5lCJIsHhFRLvhh6yp4Ejy4+Xf4sODqC6
VybJlZkv7jT+sG+GgUyIG8hHGSpM997CqYi/pKtbrK6AfXU0tlL+fDDdxFjv88D2ymeVIN2JREmy
0m0kOdP2fYA7p20Nct6hi3VYi26+g3nAFgWOS9p/uCt28qYHtuMUqd4BH+WHeBDwzgGpjFslB1vy
d1JtXXHmiFz5fUv+vCXFPGNesDgbSOwXh032Pkv09zTgXwIL2pcF43Uc57ISMKf01sBAw7gRDGFp
yDH+0KdhHWURhzKBmgm94cifysCskBxhQtiQiFznh2Kn/Qr2hdHqIHVBFr0/oCL3WfLjhztQgpeH
/XBEFo71zvd1nbpq5mCaEJuR3napCAaaht1bmTRGt+QGlZysLO0js8V8N8Y8vFVsA1+muSmyhZ4U
NeOxfxrBZ4FGHv/neKktZyNX4qKBBjJJyCHGKU/tLmdB29Jk1Nn2JBmaI4+GNcM97t6EBaSDoFWi
O9Ww+w/13btpNXWBrFLJgPSdN7YDRhczAsFIhwTfUDmEdfSeFLf1XkbbRDgpHOdyLfAyTWSWs8bX
Mg+XifY7MTVYCw0IFNWj2w8CpW2VIFVKaAxwpHoCS1aUSMYN34zkkCUB6leskZ4s13wSex+BHur9
qfdwvHGk40WRwa6xStvNoLfcN2PMiv0z13UvsyFLv9PsdA4lrzfMVH3HRlIz1c9+6o01uPuGQJyb
/5jIMkJz2IbWV3WjW7HZDM0et+LpVmwRKvobZ6NTAyXOSAJQTOKqZwOo0En+FStcHJyqysjhoJhQ
XN4q7KLrCbrv+t2MmUIDHrlXbMi0EhI6tF+Yl+X5wxB7w1PnABLrOU6hqOgBVhYDVGjnSEd4vnhe
mg77HyXxiL8VfKFFmblCGsv6XNHfvbe2apWbaJLouWczLl/LeyrZF0TqvLjleHJCmCysLVgE9gQl
fv0yqg7nr3f5pA4bPyZIe/Cqb2LyWv4nems9/2B2BLZQMTj6ExmqOPnd/URjkNGQ1tl6UBYDvjU+
SmE+uYVPPmrw1wMN1B0VeAlAGLSlHq6A/kSumhbQ4Ozmbv6Jb5WPZfb900wbF3vMkGRVun+zjy22
NH+4MaE7E6kLEyu0Gz9X9F9EvMkjMeLoB1BrW9lgMcS2MaQC6ycK6bjuI3xZwAADZrC07Gfv/R4k
hD4C+jFX/I+l49sSOZ+I4Va7WvOoqBv/vFdon6jAfQZUWHTEZbIAc8CR1owkpMK0ruKEny+MGM7q
bA/EeItFHMnZ+8l1bWGHngzZH/X7BgmPhtDFU8OaZouYQzJ1gxLFkW9ylUBJmXZNS9X9PfTQx4RH
2DuWIoWf2XZdlOXgOeZolu8v741TXGSdjV3W20X2NLD7Es4on7oHPJ3WdwfpL+kvFqm2vjQwYeys
Gjz+o0A0uMDjCLnK3ubECYI1aaNcOKJRxML+0lD8nFaSHz5InhhkZ8AQesugPedEsDMkXJL1ODY3
04gEn1/p/j+zB6Oa49ti+5Z7IhXB2jAAcnJzDfiwSIwHPzOJkAvbAwgqKM4k0VIq/mhaWBmC+z8O
ZIzpotsf4G/GSlcSPG3nKrDJQpYaSH7WxZ6P/lj/eDFq8Kcbqv56PdGJWZmALsL9xXTTLH5rRN6V
kmaBHX7zGgUlr8iSqwaD+8uUL4Nl3QKj1EHmDoxpFtkzgoqqyRz5f9ttxWJ4Fh99q8DsbcXyUFzB
Apf567qAGFb5gFjKlOEWCLQAv4tWjONBwZROOHN3MEBYZi0zI+0NSpHGcIzzIKIz/FLBqG/qlMne
7upS1NnlCSBvoHFxzPxEYW0UJSn59C1EpC2Xcpo/ZDegNfmB4Q5Y1RtwJN1H3BZFtGcc+pBu0gaR
8ueMPiIIUMrbly1C8DFn2wGpwFGsIdgaCDPKAcHYQu+56gKAmNFXHntiMyzJ5ZMQPEKe81SEJbyP
pZBUKiJtcacOhGCRtEraA0b4dZpNv5avVlbJ71S8o/W5w0XrS59r6RS2H5C1jNQr+SyiLavq0nR+
L0Z8jvFzWbZeTpNWmtBKiQJ9C4y14hyPqpBzGYZXYPyDT9PF+P/6JLG+nWBmphjAeKYIskHdar9t
WFCHvpssSnGuNM3IKMWdpHij3uH7EBSO7k4PQFN5Sg1bg62JHbx64ByZZdl8mdeCVMDBH0BbcfJO
ZgJnRQGkY0AK11jtz2QAYUd572RYvLf79P7X6y3IWcKOELGKfoJgf2nzoZXve1zrbXnKZ5I57B1j
KuTBbm4ohJnTxKTBhJxBRrABE2XBmRrHrq4ZSVXlOiJ3jicxVR3IsIb0Qi9tLMZ0xZ/ox0ZTv65c
Os0VOgThk7tJ7SSYdkXCZUusgEezAv1HcaO8qXQgqYo5jrwVJrg3fFLOEKiB1WCddKthrwh7ucoj
CRgQ64q+jfpC4UlpEG4Y3iFHg0oiwVQuXfyOqrXOe3LYFcE0OjZu6bTUc79lvgVMmSaBduPOeY8W
ACKO9IG5MtEGNOXxVAEivJcLPs2FYO6NvohsA19nJFw42p0sWFyO/cX/ziW+iQanfx8pmE50j/Lj
HDX9D7GT+V0fXaV2OPECFtOK98gYHuTFjg8G6Vg6GYA/LcJoO8xTCpeH0hxALcKMC+sUfkKv47L7
I6MZs71b729VW16ietYBR2xr45jKWxmP90n3F7073OuxhK8XDEl25LMNdWljP99CP0T+8W+F2t9M
COpLJt/2vf/AFsHPD7+zpqmLnuKhJdaJt4Xv4irm558MLxmgVcYult4szCO6epTqi8xBO4lgViOJ
L1AQ34yGCDsdWqmlrHU5R52tgWjWR0VU6+M7DBLkr9detKgC0iUBPHrIQ2xE/jHlqjVJ1K1zpXNd
AnXJHPSA53dE98SmHldQA0XqC3gnDjYrdfP7m5CssIRDusCQ6fIzhnYIhdvCh5yvnRx56LUo5kqq
jGzTxfX/7lXKl6joSGrxYafMf82zWpGmkZBP7HMIaJOaiAbqEqtp8FA+gX+4ixw4RXkTKIyOgKqC
s6t+GorHun2o0zjflqUl+dkoBTpEaHGbgLWnGBNtsI6sPvgJNebKV1JLH5p2xNZboBO/vQ5eP+PT
/pPKE2ddDZ4xKOcJmd8l43ztFtAq/+z1OIRdxAvseuHcTtKqo8+S4MoC8A8JBNEA0nDFzQfTgz0G
430uXYaVmT3OHlBYclptDMuAFqx6ZxovFs6UEa4kHc0mLNhWZdhjmo8Aoo1Q6tVr5fJWOJYuTXSK
og8w/n91yf5U97nHbr4LRVe3tg0GV+UTPnMkGHzDiqY9RMdG+jy5koiCaY8jm+loir5BZQmyrBmW
65eDja2+p8o81LSAaKntGuHfNvxJ+nna7lpJrIJm5dCwKs9oQ58htKhUQ0WepBnaOQtZHl8V+wMk
t5NyunSHq6QZQyCwQ0LOyLlYvLhCpz87qjH6QKc+5APE8G8RJbVpX1IQ01MBn96f6s3SlKlRXjZR
kEUyX8p9mWKPqXhQj4ewGMHrlGr44ZFAZYvVr6Lz0lkK9c1d5HayuqPwhxFlIDus8oUh6xpPBj6s
1EgaS9FXkkLASMBsjLbWb+zODzGi1UI35pyKgxsQ3UnUfUWOkg8ui0hxlsWuYXKuEl938GklrUF0
V7wGhzbZPSQ+LduiPiUZjBv5HuyHzHx6WvwIWa44CntdL93hmPW3c65OMP/CRE53kzuFrjxzVSmc
xUq8+H1FYD4Lzwd7TzIqPxNRNYZ/WCsyXw00XGDVfAI6m/48XEYF4NeyH+Cc4szS4gilQbiSn2p8
/XS2J1BeltZwDzkVOCOSydzJuuy/HU8mG/wfTED1PbJo8klxkiA973QJ0/YJyAJLZen8BiQRgVWE
oZOM6nQlH5qRpBIDob4O40KaFnvvRMQlrwgrDmMAzsO9jQSW7lCjQ0AAVfzmKQYswGrugd2g7r8h
nnMEOroFe5e7AjJ5wRbAmalENw9dShGaHlMfuTZ2uX29Axr7U3TQjSo8gkaNnfSyPlXg0kU4UT5n
RhiE7yi2Eg0wjjWBe4gmaDIR6okrQPCGiToeHkQbBMBin89XWsyKa4lL5WT3vOqybyK2HxC6iUYD
Q6jGsUaHT4wWkxqQP6I6LdwgmvbwXXqSpJtb1uTAehRtFg8DkNifsn1PcyfP8g71PZBor5BPcvm7
VG6eF00tBsxZXlR8OcGdZia2NOUG5WLKA0s43u3B6TrLWeqLCYyH+je/y4wS94ej3tutFHKWFoux
VSXzgZNpzIvuDuYEAvcISLuM+Zd4cMAztnGYnSd+uRo026E4MgjlU6R4V+/R3UypOrzL8ZNgGoxC
16F4pQMhQ3duPwW1GqLqNhl8D/GVA1CtBbuVi0ypa7vkp0l2Gphai7KRkUbMXhiB8Wivy/yD+sFc
9xh/L6WInlTgGYJX5zYywiq3zEi9UzpxDfMos40iVDirLEuaQoOpePqp31hMdUjP0+z0TCfK7Urm
57MhQkhVqzUGETerpsEEa5BrJ5wBXzc85hNnfLkow4HljHEQgPDiG+IES8TTjf7P1l5rn9a985Zx
wBWwj3MvlQ62+0zqXuewp/5D8S5Dij1AdZ8Xt1lTvGeTOWmavqT48i13AcK7TUvH6L1jGau07pU9
yqFoz7D1MwYcSQbD3I/Wjqfe91HvMQ7Brkn/5FM/WIa5d+uat3WBf8fkIEwmJM3ENDekN+NEZ4ZY
QLzuxEgU3KkE/woVVA7siUEvnZHGBl8SJbJRoEyRiVFyecbcXeqX1B2X8ALSWJfDQg+p0pZSUczD
14hLfBmgqiVG7KrUeFm4O/FcLXBxSbxaFt7zesVQt5YSf3s7jWRhsMhmSuRsdOF6Rihe9+v0mFGb
yC9Um42IfHYWn57Q9T+nUTa6bIVg+PRnvukAKBQJNGQ2bWNJdfm2Q14PPg8KZjyjQaeLZmEw27vG
elXzxBY/uTKIV1N5H7B2vhyIQXikKCAErO+PlmGhKoGQTiIi/6c49q5c+GSjOe2uCOcUIhr57Iv4
0LO4ZUBobtD6gQlshJqtYL53YNZWnKWJKQUigaASj7xbFXm5hsoLLMm9dJHL4VjcNFxjwkGLV1Uj
CDWuM+vuDTi8ZdMCywHxmsX/eDEKthG7fEsqfIc7PRtYXILMw3LHRfx6B4I5jzhHOTX+6nc5yXrz
QtVmvcCxkW9PYg3IQTdJqKFOPOlRJAkDNTZqp3J/zwLpHvTLBI465TQwSuudQn9TpW1vJOZivfRc
EI7qtVcvVuangZczeqozQMk55FjovFRAwb0EG0f+GBZAqVRikwMrHn0my/sahmY2gF3dYC9aadPp
CDDb4DVCHkRc7gG8Vm3/R6O03bZoSK34U+RaZZSz+8yAG8gZq7ju47Kc4f+bGoe3Gg57z6jf5sWk
orfEilazEbr5JglorSuGC4JR5SVHvXgjXmuaEkQ/KcnH2IFS1XAX1Wqy1Zes18OA92gQLeFYTKQr
C+Nh9BjqF60bG/R0UGRYrfku9slEx4DtdaE7rDMeTKaYXL7HUD2Vsb+F50IDvTGSi/NHW+gP3f1A
Tntt7UG4hG3ZD8MeiquXQBPnrFdS+9cRMhrDaF341Pig5IM2pCbCHdByLn66Z5DuXyVrdmgJuTEF
PdMWNuVft7XZZd5rL50fsYFP5cymcutTtTQE1HjO89/otsz68b79N6Bo/fVI4LhS722PM41ziTqJ
j+kAnzXOof4Cm2ReYmZs5wI2dVRjNE4R9jwhoy8997sUpqIWgLDdgE4EOjK4tGOo1zEShO8jN/61
+PQcsRdn4pmrd9/CBiJA65t9iZk1CZ7wP/7yCFX3AZsUGuEpLYTuO4ihhcfBav59iYQ4bq9OTaA5
SUZEmlFvfeEiBAXMguraIWgZQC4Hgcz3hXWC6vxzNxy+Lygia+Zkg4/lWKENEDmw0mmnelBIPjcG
K1JkXaNkwM2+ZFsXy6nbhQrXqzPBGZIuyZQez1vjehRNvo6z2wg1x1k8ID544Ny0Pd6efVT06cVo
EDf89EuQV7K0cYianx5272OXQOiGwOFVsTLgxmiV/pQunpt2bkccDyH+mWo+kPWY+KeuAN7CbolU
scATD4td3C8sZMzVuelvzRiiCoDVD5M3glOiQmFkAB3ltseppJtvo5npKFKkiWItWboh9DMTjq0u
78HJp1uDpD486MfP9Iu7DHLNonjcE3eo6eU1xe2T5nprH+K85t+ZFSfTlRuZPFItLh/PmrO7zk6L
QK5VzkobTpC550XrT1GXQ51w0hTdXOblpXewLQKhbsP66lSlxFNfr102C0DD+SmMZY2pjs5adlCI
eG8hOTnnSa4ePwzMGQLmlVSi3n/H7QUYu2ZdP02JLCGY95ODI6GQFcsFNhN7ls0Qe+20T70+pjWl
c6V9/Hw9zHH47RAbjxvC/uqNmS24qlaUAHHgeo/FlHh+9Elri8ulMtHME/j8wugCm8y/nsSA+Osv
/zUx83XHyRzxoQA8U+xLKx7WPAdL6K7E9kndfFMPieKaCuqGi1pKVOwAAjd/8DeoNLtLpyJ8tO5Q
o9yhp4oBzo0o8f+Yfh0ME1moCvQfh+eAVwHirX6M0s2AAB1mKJ6ysWEPNuNae5HIbntrtQprc/Rr
cKRA/T9eT/5wsw03kxwCfN6NF8N0JrNfAt+YJE1oDgsniOQUKRCgxVTR/IChSz8Im36opU+6mPyF
ROgk83e6AlTSldEBpgpvRNkdM/pTwrcujr1hFmu9Kbv7gT3Cztynx9Q6Mm2Gh2nUgrLYBi4QNFY1
ZG1pAQxz2RBkEFZbQyBBSXSrmUmt04pkD68dr9Yblh0Xx9Px1yN0K5nQ+ot/XjFhgsNAuUAvL4F5
Rt/DagoRxUnaA8kvBsKsS7Al2Cr/+/H2bcDqW5OM8s7soFA20umhBHYgTPx8FQjJxTEnruTS0hIA
OVjyIC4hE+phkDW6eM3sYtfnTyBPZplKM6uCnMxSQy1bjF7I8I8Z0uydWQsGcmovcltxr9Kmkal4
ok79yKWvgyBOqmxPSYZslrWWqVQwWUEV1xNHCSuGZeUaZN1bnbzoqYU5+Gmi3PVSDQmvZ7se/S6C
pQ1moDWW/Jd2ucZJSaH/0+IR9o7U5hnlR03DmTdh7W3lXpgcQxEm9HP6tj6x31WhgA6qk4gepEQH
9MNHAdbfJ8O9WiBKHWkPD4QWA9VEYcSUpjlXVvB2n0CoB2Fg6rtWaZA0O5xDRl2edLOBeOT1PTW3
VtFcANlvNv1rKaXbMkVcCZOEBgt7mElBey/aHJj+Cf1jY79r166vJ2bltKppZO+MRKTtGYPabNXw
8K1jKOH2t955EjQn/Q2mIBUwW4zbI3fvgb8FdefF4zhk5LmyftMwYKC3e6QO42NzDDHHhpJAm4Yp
wmZpXCp/7cEIDTGc0s8CFVIkBihKIkix7NjwiSBdlrJqYOjSeCk7CMg9iBnTI3eaTXpk4zGzJ3xj
Q2z5G7+n7oZRauxksfbK7uD9XzSa1noiYCMDpex4A/GV9OgxSNiSIZiYejXVYyPVdcaNKm6bRtGs
DfFOM/v5FYr6GwjsmCuNFDzB9ble4pO6FHu5f7WaRKgTT50M419wqccbNQxgTVJ18MrOWDAtPEnU
zizTKTly9WCj03A1QU2chy4caSCdY4Dan4jruKnEBcG9an3z+8bVd0W92vpWrgVpwEzgiMKrZ9LV
bRz3hgSY7ducWWVVSp83NtnGmzUrknVo2zBk2ljyq5vduUHUi+vlIMJllc1AeWVjEuV4QoDRg1Sd
TDaLtmxeTNkRhflWmxRNzvknKbEYkTA78UZjzHGOe77VZq746wPsunGVeXwsUuDBupXJEO2/bb6L
lBvsHfl96lL/2ssXHpZG04FefSuMvBanmw3Nq+aHyxAnZE9Hid45tiSHkrnFgHz1YcljADC71HBF
bB9XvDfuMjknPWEB5A8MGT88XpXwCIrj4dYWoeaBJ7HNCirwoi6UBEihUMkaHf7xHLXn6oQcwPWR
KQO9QS0rfZ7LNvRWU+kLnHhah58DZmBiyQxVU+Er6XsSCspcKv+Of5p+zYkVi5ZxZ0CDi8B41/i0
9t7znMKYkYuP+XkYlIox2fc/7LudYWh1HT1GLKQHIMnbBaa/DllzNeL2FlXMa4BLVfp5nSddVtC7
gQnwLyjqtgqCa5gC333efhBWK/mD308DHTnrL9FeWQNjY9zu9nE5yzrKxX7KKsGIjts0iiW9MOL7
UF/1CZYyyGivDOJvs0TuYfzE5p8h7cLx6v1MLXNxfZNWKDAIyoGvkjJJP5bu1m9s48wS6X4IC0fE
o2OHyRifCCmuXL3rZ6qMDU7c3R+sq/bUS0obCbQqQ5ACvo4eEgnLV+8DhmYOGBs3t8sdoEMPPA5H
G06/GlYsTMWsdQTXMs9M+6mprdSLafqB1ljpYqi4I9lax3NCCpQC3VBPmmfhadn4dgW1ectldcUb
SMj+X5a9Jjejvd4WI7whQtCsBhl/1pRPRd6XhFFfot12PN0YI61ZcyYMvhkUAUkB8UJjdm3t04UI
Q6L43uCsc07a9NzLp5k9SdnLU1eChbaun3hlkvmLJdH6j3QRbig3icPL/UrsBMfXIBy4SIYSwk1M
3Gsyh8k5tqEyqIiCeGUifEnjh6GJ/TecFMU7f9XN3hjuGWOtvjEcuH0lCGX5qflStQmSv+gSZy1r
+zaAgBqKVNKPHI+NZVjqaFN3JwPXczXJB5LZDd7kyIELjMd7O91j17cdDcH26KX1mbu8UQPYhKZ5
nJGYx00MGTAi8kLGQogofKvqe9aCoIHF9hZlH9dwnC+4QwepTuERjGEnJAIMul+OT8WGZNXE/3vS
N4gZm5lC3WKlN20xOMzlGYXKlXgoIvfzn12NYE0sPR6Qyxd6fA0j+xBhhmwjS1GxYzqrTuFapicx
suu9jvhHhn6MNYit2B4p9ITIgUdsVdlzSYNjfQzb/aV68+frEMap3ro09ee/CzuqgQnl0XmE3JfG
h6lPdiVlUMFLIoIGBFJhCh3uMLiE1OIgJJWe79Ko8MPK2AqNhh1QMz9veFn6BIzjAEb33ge9Ha3z
wKKrgsvx1/yK6RlQ56nQUcGYfLNrHaoI/h6EyOy3o404WvJvsGMWN7kB2BOnvtCwxErwvMDqhZkO
HtJyZqlUhhiGrv/4JJ8sC4s73OCBqvAPNSYYGrwBN/T6n7FB0k9xU1BFq6rsRwjE4f3uSbIzeFiA
RV5iIYsLuBJRPDxFeOUlpEnVPK1F2hyj0gRCfk8XIrIv+xg7tSHY3+L47y1wY68vVSYPjNbBaLmN
bKrftWmKfOd8LzcEBF6x5UZp4NBgn4rkxuHCxPxFi8gWPWPhNPvN0kv4RuqwCM0G5IPqcbOh6EPR
jJcL7wZ1L+hZ1ewFkgD0Sq8JcYKNPM7oqaEu+ksFJi5lj6zyggc04pGiC7M2HqKMmMTaK0xYct8l
9j51jPJWBcYqwlz/1MU2BDtagClFz/kyfWkx0CRzV6D6I+Jpfrek1sa8VRqL/fNdavEfwlS/JpvC
ToGWBXEgJVvw+TKO0w3z6vO2w1Yi7grCOV/vjgQU1VrMyJGfjVsvVMO9VPJO6omjfq7tg0Yh9WHN
Gt294DFtRPhQVF3hmkpYb8r9ACTpbsTQ9yh3PYTjMIe84GcFNItCVU5+D+O4m6U4qHKse5yvyYML
nYh63MO4MQnAuNffrr+Z6sBOOXTL1pBa70y48XWSXxGAzImmrFCb68S5hR51wh4YqHS3C2veAtYQ
zqlTKcBVVZQ0JljYrnnsmgQBlLRiqNT00BMZTxYQyjKoeanfCOogKstRGShVPdF+we4+dd3gd73g
5nvDRTECRXFDKm1vi88YnHXqdw25zbwyjk0m0V3mbpEMEwiIV1PalDkb19Y+YHUR31K9/UsOx7ij
3Eh8pMNowZaRPhtXv13GYO5ZBJnlZmjUVCiXSsa/a65bG9i3Hvsw/4knTOeiqoxVLhS4008Wz2ul
j4mo68lfyzIsCtlPer5ktt5aiPOZEL1138tTGgPSV/M1GK7PFl2kWoyDpOYtiB0pGmGwJecqnvc8
7kdDPeF8mBQbe3arEM+j8zPR4mFp+IdlpDL2VZaVI0gNwny3zQjRJoKd4IYrKwK9tiyt7v5Pi1h7
OslZd6jhfnnbb2+5YLisYP3QLPMad6k2rr36mNc+hXaLp1NTdYXXKJBmujpzfueN7kJeJG92RzgA
BQGh/GemHF/dxf86KVdJMbj4zFn1+ZDnALLRzp2jg2oyoxgif5SLKF4eEI7qNOO+9TbGReUjjG96
8vDnL4wsWCKvz9p2LacSzQZ+/lBet2wM94jK8ceCdWmD0ELbvY/eU3MFyecVPbNprYS7anWM7QqI
H1G3QmTXb+xNtIcSPpvUisdDSfLTSpwxXxSOk1KPZqQtHXIusfAW0sRWUklURbOJ+zywP/h0oAJI
6D4Zg1q2asvJzkMVGXMKd33mXJSZmk5Q+2YU69TPoyYhqAiebDmJqfj791U89zaHJ4UfiuxFfWjx
ADjsSgS3FztSNpq0AakILVEglIng8VtDKNpFYb1R2QO39r2/uasuycRZHznbCB1AyzmYAel0EWKl
AOzqy4v8DLQ0MyDQYDPNBv9NPsymXNZkyfODrfprOEl9uuZdIaMBE6mO78L9VBU6AIdwU0GFD1oS
kq/3kUNpS97FKOnE5pDsz5h3QpywzRYwGBelUtZQeo7n1eS1NuzHKcjIh66Ps2SBHQa7WZtT3ngg
tXVI4ObH7xowh3BFU8ZY+LbHvfH8246xA8bNdQN15rIMRwZvnbXLKKAunF9YNYB53tjPXzhYMCpH
oZnmALAqU/VkMJLd3BsNTbszTNgsFobR44oNLTQRaNZ6NDkaJ8YvbdyYp14+vKv2neeollbMWjQa
3iYIwrVzEBESRHkdqgk6g+C74ZJJqjf2nmMcqwhRjyyGJxREiQ+krJfVBYGDkbTuCYQH8wu/AkmR
aJJjR5ZwKkkj1/Ol43aA8qh4wVqArqu72kAoHMiCE8y2Yvxp/kfz5nXTToDfTeA7pkRGyj81S97L
WDJ+mAmaFbC8/5dJwiUgeIpLbMRvpetQoelicvJRPgF9j3nTNWhaqI/JVVoPvhty2568j4ptv+ch
+KGZu6x4HShhnRPrKRKSuph7AXDkoQjVEE/GaiCBlucTCUyfySrMf9dTi+rEcWhot4OhKKvBuybK
qvmpBCG0uXnXvg0IPg1cxyWZWPWZ9xTBgKOYe97JBtCFFCO2uq2b2EAryG9eXxzRkQVNmMul2VSh
pPGpUWf3AwoefWpnrVofFdezR2wFY0ItdYxzSOPgXEC/er0Oz+9DikwFtE6sjmQK/e3t4lw5JIJA
icw/AFEnT1dVRSDDhMB5xSlTzhZ/0y69NYEPWJ1ucUA3APD/78tqEf44N6G7fcaSfb7vhvU2BfKM
2XqDMwewiefFPYld9wu7WDDLzoDCcRCFaDpbo296a0cDoTAbRJIqumrMAU/N8q0o4IuuRfI9NRTO
pAmjPMHH5A2sMZn1VfkR9fcroTtMBCZodf17robntScYst+eEezFt2oLFWvt/RGmXktF8g/+j/0e
qqeEPnUkgzq9gZVpY9PLC/RdAne9LxpXxza+sL3BbyBSNSuzPdodxfhov896WNlo/EYCGDddMfDr
w41x583iv0CFpxW+l1XuLHlqXLJhzvXnsrsFPQ66alGC79XKo3S+Oml+Hxl4gwrWaGJJ/lAJbFXa
YmYX3zGMcucWi9nMUqheZ1zCq6jE5Q66559+ZM+wlgIps7xtO+MCtz/Mv9aaXvkzyjezZqUz0Pou
FdyXhjjFzADhsUWTYBRO6cyX3ui/II7CtA21jYJAx3HniDgQeVj415Z0mA9Vip3xKT4cs2pt6Hwl
8NhG1ob4rrGdyyJuq3znjFScYDx9tqYn156Kka7G/yR99+7VpolDqfEzmyNz9fh0u25MwWXyEZ91
5gHYmWsCFZnJ9GKoXXmhPV+w6nGb3tBdjybta4SG3uI3gm9umNxV3cE3MM3ZF8KQH0y2auLnEWCY
wXM3n5S/ZMI3gV4Wcv0NPCMQo+9f1Dhazh1T5NxwcBTJ5BS2vFZw9sMO72TZMSJizfOHSCR5v4ra
Bwepv0lMdtZvG7YWdUWiYhIR2FmSnMP0BE/Locptinqnf/LMGiGv0frSnnD8KpReBVFvBc/Z11YL
YjZntdNhkrrKR004cIOiAW1H/eoN0ypLGaE6wDnMrIs5E9emuFzP0vkBfrfrZ8iSo2U7uJoAhTZ4
FT/bwDsyUj+2WxF8jfliczSAvw0KA7cPqc19+DXpkyJpHKQuSxIb0TF/Q9nH22i/Dk8jZRT3FdnA
ss0XHeX+I8SyVOYpjH4FeWaSdhz0pj5ICyb2H+g8KUqOohZq/XLG2P8GtU9ctoHET/+Z3AoE4VK6
2sgfTtKnnNV0PpjKt3LrhoVB7R9gFp4igZj1Jjt7/5gNnq3cjIU6Z7GJQGW6INAbBxFDiIZ05V0r
l8wxCeDr4QGhU96osl820FbDEZ9GJ9fcsMqUIlHA+fZpFZ2q2J6XsGQYKLIM2Zgi8+REF++YXVrw
3jkws3HW4wW3FEMXtZddrtSjbh5lOg2Kn1vIWiKWvVm09eSzqDUzxDHy2fcDgyvxA5hgbpMmR7FM
t66ELVZmUoBG7lgzqV10BN9pqj2TpghhBCqNmNhJhPTTx18RXm9VNQVw49iM4yqMYb6PbkVfFwxL
XOTYymQ0woqVheT6fgWy9mpvuXrPh7aXfeoBRC5o/AVS9mmbeHJoRThzVrWJ9q6HW3s/xhfdZ7/u
stsMnKrRK+KfmANE40pVNGMppr+YxxatTHj6VhsCy6/iQV/mxGAitcngqvPMgdASreskAHJIJEEJ
L5Ck2Ikw+3kswdXjz77DqCXO81Tjv5DKZN596CCW/FInU9ivZxmB4rL8Hdfhu7gjijvA2yBjCHRn
+xZuz51z28hyLlWKlmeDAmdGQGLOC4r7+Z1efxrgzAOuhQtmIGdUgB7IMi0F1twVaPHvoXtK74hV
vAFS2fk8CWm6M4rRC+HULQgc3TbYqJ7Oc1w2zhAyQxYHUyQDs9X+Zl9QCyY2aj0cQuXFFgDxCu1u
CMVVzbDcmDxWc13cGi5kHU3fTeevk4/1mQ2QFM1eTu/Ymp9wSH+X3lRsgoZrTkZ59bXzgD10XTwI
7YpLw8/VNynn/G9o/Q0DDSzlkn3dNEHh77H6h6UPhj7qJWK1XOZHw/dlfxr2jKG7Aw7FlPZIIlki
wtEmp98EHkwtbEhl3c7EAbhZ0BHVGt3LRS15OcyM5q0aToxBYEc/H9bA6vltNMKgWup7GFoyWzzS
PrQsed7SVdojLwSjm7fShsQtn6iRYr/HF721uPTyJVxr2rVQkkBPjxztsjIOJbrDjFXtA73As39/
SsajCPElnI3xi0vqyzMqRNox8YjTX5OFXKf4N5lXLeB8zBBM6tfafHAl9XoEomiNrqz7SRro1pm/
AN5irpgT9MagZ4GxJBIuMH6DjH5LFri5BfYiSSPgoonrhRtkjQ0lpuDwVg1ISdmidDHQs2fKaUg0
F84bjODLCLLTcOIa6yYbpKrYhGGAMNBR2uqV1cf8dorx9WXBK7dIfV7ZrSMs8u3L34MGDanAwCGE
Oa2Qofx3hBfjTxKI79vSt/yE3fcvOJjlsgBTect617eEi65JxFIT8vob6NpawJxzA1Ba1SbvKFdN
UtbEgbtqV+HFAR3lzzApMZ63feuScpmxArM/1a4CvSZdhqKdM7kOMzOymt02G4QkqtAvJTa7jfGo
8Gg7NdSAln8fEgc39C/oXTMO1V8yy7IJBUuTnFymU6Js976h7veI9V27QsM3vLJTA9nat6SjJrbX
AW6eGw3fqklYB8J+TO8anxWd8WRs6L9/EaRCYIdExXa+ggeHWCcwnrJd3ooAT7Qu6Y7Z8ZiTFwpQ
XWLFUpAudgN8BM8iQMxnaKig0zf0yzDTVtjUNMGews0OXXTlfpQfRF6IbQ2O759fi+wcAycyTL4p
sFoWnCUAjCrdPVCW5QFsYkkQB1IVxcTSN2YLQlI1jB6ebRW8T8uRoTBFM46e/UiofESlku5RXt3R
RuZKA2kNXCnwEEi9WsWlPnqUkTk/a1mr5HYzvQn5Z7wD1mjI3LJXzn3ZXggyJn0/7Z8N5+D2Wj5C
Etc0RLE1VCidAgbuCZXOPI7nmD876eL/tL2Mb9mgeuUGF6hhmopl3ldHGIaC02IvDr3C8qyWPA11
ntJORuBtzSyip1mRXxSX1oqW3ttVk1fxE73bXQRKyBYZZLYLvFbJ7QUKYcjKgiYj9houLyATyQUA
FTrUvtfyn90gumSw0gU6oKEnpuj5Pum5VGH+RrJYyCL0+Rr+0Wc0lv8bvsY4P9M5WnNuQO4QwMGM
SskrJbXpQQfSGEb8CiLpKxZnOcNPq/zx1uP767azQxnGhNQT1wCVPn2I1JgOs58RhU2+m31BE6n0
NjwE0WhUV42ovkDYmP5Y9+2sjZnKcWI1lwVFnxtOCkHW/lau9vYugOjvylRwYbEa5VMO6p+e2UPz
aYjpb0N7WH3L9kVdYwycoSpGsalq3he9pi2v/N0xWZeIbCh7kSuqlyfc2aBh5gdwe88e63y+LNNI
Q+cv4XtxApBYxEacJSeAdMkZxxpWipFPuZZrBqrFIiu+H2XpFzIXhdI2msL0a7Ya/299xdI7yV8m
lafqp9Kr4E5a2mEQvqf931l3hRpnTtDRhRkyHmVYNwCJmTqTPfijzEZddiHulzW3DkY0I45WYzh1
cOMg7CFPruB1xl3sFwCF3X0AC8ZtGM2+2keo1+bAFXy7Uv6Zs6Mg8Na5AKmB99z9re/n2y1yULwg
1CQCcfB0dixNs4sa4X+RoClWqSKjG3A2YfCd5oVnEigdeHh8snESMoU/gFdxA2NwVXjys6LasXAf
Z/I2n8kkkObF0bDpPyqk3BdKdgZ5cC3TtvWJJzGYLvCybE8nffUuxddFuXHiH20dufRso9N/UeQv
ImcxMGuZMmoJzWbre2g1tyRT2HyQcALC3KzNjN/kQVamUrIzLWnuyfvnk1UslfNjV5Oa6M0cg+Ul
hhar8m4jAlo6nFr91maBQyGR0IY1aqMIp2Gx5M4kqHoKPB+9LLGbF7MHf8y11QG+a82k76s+WyV6
DDxWXD0Y+y7QljEZd4ePpZpRUZdBUu/EAEdprLG6xIdRjub0j4w/JBb+I8ifAmuH0ShqX5XadNPm
b/8GQYy937ZMLL4h8gfSD0T9GV9cG82C0Mii6iZUm+yN5v19mgt3YoYA0vrH2ggIfTX/SVqsI7Ty
geHGCEkx1SLfsJDSGZlxm/vEKiCuQevsr86HnQhtojVDkh5jzVm2M98UnjSym4upA5ykcomvrOLP
vKODalzuAqaBHVSVWWNRbANtxvtKmW+e1L7tOY/N443Y2te2CJMbSDFGQNaICSV/5XovuKRbB8kg
eCT+d4NWMaHzqwDELBbga2TW974YieKMVaDuEtxEmUwZV5zkh+2KAVdWmDXINfyCkiLdq+VHRo36
7JnAEsa/A8cLhoOk7ybGqRHqLXv0cVQSn5MROmAn+GNRV192FoReEVqBeHgAvnF3BwICG/JafxM9
lvgI4eB4icenASQ213UMa1hq9+pFKXQaXUgmEj0c+xfXxMxiwY/z6Q+pcKVY4CS5dQuZidOzMoeo
/EMAJjBVTDm1tYyndt9QoyQxdFlxixRe2fibzBLeMrDdEjFbBmkpNRqxJ06eIXpx7y5/8ikrjQKk
pmIU8nTb7p/BrPf0dfOURlbxCTJDEtPrOFgtYer/VT78cZdyrtFpZJrBeOokMwcL+JYLKW294ENt
F+SxARXUAVMukKQgwpkIYpnVWDfLkkUOfB/an05veHeFQhLFv3IVfjTiUqERktn4+ECNzfqeJJXw
n+3OSYU5bSBRC1IdTg6miHAQo4Z4f2B41m9/nImK304bqiyZixgVHuQxl4rBNXBB/JNYmjoJIQoB
gAFTNSrq1JzqtjJbZV56DRMWxwKySe+bDVbC4lJ6SJjXiLgEI0GSW6w8M+hAGD5rWlsJIl1g2hz0
z2DsOnShdsdJINW9cUqWGCIkc0zVggFSBa/0UrRK3xcDvlFe0l03hoIFtd+KZx2EUb5URB5VwHi7
z7WlNUrprlD4LJ1ED23wVJaQ6VXGqze0QLKCkA1DNEfBgxFhuoIiXZJzk/2u7MhcjRlKO6uuO/44
8hfr7Oqt9zCgW2EUADjI7Ba+yXeNvqxY6Ao4rO8hBrV3z4draARgiXrmW5PKv7KCGRa1OKRw54Gw
uqBkh8vi2WdRv17uhVlnoVJdDH8Y4J+wb0UXfuFDyhx2UqSfc0ruVqjIl8PuicuGGW/44SWcrWtX
xE1sXyX3OMpIX2FrBQUCu6flh+cc60WPR9+vTFUGSwIDFyjPLQgGjnY++MMRoS6T3NS/EathTi7y
R2CYqquXR4TIyLJ7ziqz2AMNroyAzF8PUE9hObmzF0xUdMZiAnnAIn6lb90R5QC/eGQptEQs/qCJ
Zfs63s51JSmVg/ADR3E+jB4Lnv7Fsxd7+mRr3VyuASp8aGW6nROMxmtZ/SmHRoIpNP5TOEYuRTCm
hCjREBzknilmWOkMH2A1bvoEHA7GQLhQ1fBcY0MhRvcNPrJrwsMlzYAOCGUkP6/NaRf/t8wkfwHl
YHUDsXJVGmUTX5AQoTcNbUBh/MhO5nSnLTh93mzYGAQ8GD8v1x5KyKq/r5ZKXv7i9F2TcMKguSUv
CGss7zEMHJxAdgx6kKvQSwwwM99VOZDjNgqCt2KuesnE9yarhj8ZBd60M0v+9Scuo92XIxRU6QtX
aNt0GjQ0iVfmyHR8JbKjgg97AbusfS6ni8IsKaxfkpuC/tuagvACU/evu21Du0mDZ9L/JaX2e4Ml
IX+VA3Xa5bmd5Hd3xpJYsVRzeuGr99thqGy3nxcSmmWanxv5wirTuBvOIvaZ1kGJuZmgMkTU4glC
eFe2Z82q7I5HEeH5fQXJ7y1ksNsMqWPOkcfmiMBtPZp1OGMRPKcj76MIElqGtkuxWeXB1Hzl8uk3
49ObO0c/ggdHszqUhTKPDZ57HVyLG2y9/wa96OMwqmmWc+arffjUDSHlbPF2wTzj4YMEUWhLIPm/
5sNDwkD844om/S4ptW4pzcYbziCJaMYlZrSV8UJVj63eX43WTNoNDlw1rzGUtDRxZxftGaHoTnz9
4JbV4o+XQ7X2dnJps/5cCWED3uc1wa2ZpqO+D8ZyfAwh/lNHEhwJNgwDWkRoL0ke8QUu4VX+G01c
EDiXFW3jzpocsTbKWiNpkEQ/N5TihZBSFnL3kSVyWXBvVl0JqYv+0yUzjHct6yWYVTj3s8uHcC5B
TxBiMdXaj3SIMN4L75WUWl8RbIS1MOT68BeCFV47jyb9OevGA/y2l/1JLOQPx2b70FTntqfxExVv
Y9e3KuCWc5gYV0wPtruXKyblVTrb6N8nrg1y69Nyi3JHXEJsXfZearWax3mAlebgpGC7xspiIHUs
0c3S5rZf0zPHGsmE4Vh0sSss/afKep+eQwv/fI5pEWfYBv7x+tJFERGQsnmpkLf/h55ELbETr+7A
57LSy8LEyns5m6XeegaGwne6CLGUm9A95IKEEQNRVeTcO7TlA0HpiKnttyqBkTpqB+a2VZSuTR5+
sNHqf+UVVQSDEn/EDrToC3rA5NzUjn8JJuqp1/kMztO13ukT73fguQIUj11jMb8Gh8/3C8e1fxGs
IodSNyyQq+0ex7gUcyMQHgmgwQ9WTAFhketK/9DYZ9l5+EAI94xgGvY3AYF88l5AI9Wr+y6TzhHY
vbMZ3NhU71LHgl3WQMKefqLMc9wfFVWsMKYCsDV/+yUYBuLhcS3JPJjP0KEMW+wdPHPSStRipOqZ
hcT1jKRV1SM8bH/Sa6w/+3tOq/dwErKjEsRFntaM64TDNvydf1u4qHpuMXN17BEg5ZDCM53T+C8d
djZR4cgT46+dPcPsyGIC3kKTQsr6EGjVnRIrYVW38+ECnUoP6B9mwnCEtgqZOryVNIRP4rlwrOTP
Jd0+pIfxgqbnCG7UIB99iBuIOppnEKrqYj5wJlI6Shef2Uj2MK60XFkJus9Gfch7nOX3i8dZMGha
n70CM/htNZHriwrT5xxfGyci5Jr87upRRypqUMo7pARA9/53ZsTmttzAmV0Z7KBkyxcNPNLnOOAT
KZLm7XmqT7Bh41VPzQvAahNuyhjaj0kMWWWoMjzfUVwq+7Hz7o3bd2cRTFwryKE5NuMkYsDSwD/T
lVHtoRd3Lu0vN/NLktoLTHmrAF6WqD85IYO7bykQi5R1gvwuS8sNGensOJ00NrzwJWgJcKX/kxZt
ev4dFQzB6BzXppC/YAUiB6aAzVhPL9t23KCrer4loKJZyv+Qv4DF5z5JVCBVI/UoOQKjA41UZ8Q8
H7WZnOhY0iDMrZ1quP0Au5h+0JXz9BXjAxyD6IDGF+rOBo8x1ep1UfmjZDcivJ00iBkUvOAgcraa
e5xtGFq/+DTej6dq1tQI9AFFYUBL0Oh3BaZtnuJOUCq2uY29RKqCGGMq1JU3phGpsEJP38Zcn+Gg
XnEwD0SQup1vdL8SWAaOZ1NPWlyaQAbKeRwp0FtKne3NQ59HATniwotFrx31L1OEKdGUultcA3J7
l1se67mwDb1FdNbLR3LyWgWABXYgbLfjn0RPAhKFxW6TvLTudg6sY8/MZLlwfLzTRBYPftv5xX1U
xOHTwCdo6cQZvhpp481kmq8R9CaMEfMFBrZl7VidCZM8yEtsAW1deYenF5XDzYso/0IdQMeFYiRl
3yM3vkhthhEpq6agRoVs3ySN5MHKJb62TKGOV3b5135JHQcJ597+bxVpJFMkIVpy+qEUDZ2pc2iN
gAPBomntZIVFOQDuEDIGHDiXSQUKCrMGP2KyY6aTd9FM4aVINAnqQmQICEy6oIsj7/iBLXMfv5Jc
YvOIMnEdXZ1DF/gov+hE8HKuHEfi/IEFrX2j2NFHrIJOBsXQJk8uHB0STG7eVZ+9OpjQUfeDJDmc
7TuAcs6St4Vzynd+/ggNtAYf8A3IUHRSLFLwu+2DsDioRsb1gKf1hDwmiaO73uuhmTkseqs1AQvl
4ccuQnVAUGYur2Bly9TG342jNS0LZgxv0N+c3sUvnMUbzllAoCe4VcWj7203vJ3wM8r1I06uJhiJ
iYY+EjQDaDDVcIlFSgtOhvhtywfNXHyfNjRD42tPV69+B0StoBtivTIEkuD1kllcwrz9tvSlfO7u
CVuK5nV/qL1vKSvDL1L6vJ9CnKZwtWKl8hb/XBpDLtMaBVL+izdhsGBzJnLK8gtu8fHc48KyrP5Z
5+8s289bCOA210dBVEiz48sje66Prlwf1oxCD3WOr8DqMsqk/RJbHxVr/bGMUxw5n6uNMJN1U31t
+QhIfCV7pJBpjHbZQg2V092jeKsENGQPR3fE32vwTfvM1urHFmjR+iKtN1FXIxXEWIrAVCZeDj/4
DN5Ta5WvpOguJcVkyfbT6PALIeJoSS+ixBfz82o7ZvcAHnUq2clXr+wLytVToQ5XB1mFsmDk6+ni
uY/6HX1NVg9KaCaij+oQeaUVFHqKoDXjYcu5va0LgWyMnso9tFCcjcO+duqMJnKP4rlLO7r6fDy4
FyYpToEtal59IewWItYeKpicyodgZgYH8/INu6wW8dWBQ2oZAr+IfO3UwSxuovhIZonWjCtDg2gQ
IIOKkbOPiyIwo2/iluG0K5tr05R/wdCsObJz/SKiPvorUoIwVRtYjPQ/mCNCZ0xr/vUFBQ3m0arK
7Hzr7P0RObYMl1zpd7MuttYLQHrKnEwdxoXT1VLWKfsc6X57B6yG1g/wl3YMvD+DMFb0OxTGpn34
eYR7PbfW1hCNpCFYjahmQ+HyYNkPm23FrPMPY5g2BBpr6NLxJOAIb9NGOq2cBlCH0p1E6t4FOHQu
V9BQdmcaRYaMjk2s8BO6QA5W8NFMCrZBDPT0BL3UxR7RZ5JcYxyQeE+YwSeYvwjmiMYICC3GbmW5
OCVFs6oUHvXqpGqS+PomMjd6A9gDjzws9r65tv55UQa3ZFLBhUJH77YP4AwTohQfQSCiZnexYtG1
Az3IF8oHv3pYxRRmGnhVSjeNYNlEmXT+Tu5EIqslKza3d14S3rhBPF9k5GnUvDlzwsc7H/bH7+87
SNA0+sty35tFalhWo2jwKgFGegW/yQ8cVAP8eqn5yek0CI490so/Uyr5KX1D3USP7tEfI3OJsVyP
rlo5yxaq2DpA2+Iful0AnGWq9XzcexGUNFl6EpsOhiWqt4fdSjIdHlLuG0kid3HDEENjW4qO/WO8
ar5bastP0n5LwvpMG7k9KDLqedJpO0mencyrpX/vrE1BWXRKKOl/HqgxbnkqR7S8wY+0FgAdqmlR
BmFWAv8hEQj7DwvXj/6aN0FPa9todqul0igmaGz/zD9no/IhpYk/tEoEBLp/MHu3c8Bj+J3JOpqd
ztOSwSav34Q7yjh8wAKw4WMNqfARbKSXBq6nZgA7srpxb4wPLRrkWQ1YcX9GT1zmg4AfIJPuUozW
v1/lY8bo0NXjHI0i1kiqTPvRO2PhhNU5qcC25Xnww90VmLBIzSm/KaEkrEldiBtgaMClMdBpClv8
GTFg8xMk+GfL6lPQPF4i3dkSaaVTF9/Sswqx8X+5oiWh5wjtotAsIG/IDEMpN7q/rh65x+9aAneO
XjnmsxjC2X6LS77qCgFkIghk9c8QyObdM308aoBE48molDaajypVp4tQkOf0bU9Wy4xVNVul/6Ls
Lny1/myGqI9k8PG+t1twLgsbFfBFXXkDldpG1YiPQ1oxV44f1xwMrPX8qdkbPq9QHElnSpRdsF7k
GIXSzczqTSHDlhY2NpiCNgZcZMh5S+iIhEVBHRj6sUudkbpA29p8sVhglBKTFKyE0ulb4UnAivNW
SPgrjzQvYGVRrMgfFfq4/wFlO7MEBlQ6Kqs3nJ7usbWCLnxO2MrZThbjDN0hQZjmat/img2tUFD+
JgzM9+JWgp/GFs09DZUxKlv/5lLyWhSPwdBftSjmZjUad/USMj9pD7j1diZC9Mj8ABdV6cJ2ScDn
AacZC4f4ikQ74cbjF2F/+A7HPopL2IuUpivg3dgaP9rS6GEf5j8tBHeAwCCmqODFxStKdIur1bdN
7FNufbqr6c0GrNQYygGuF6+lRC1VY3wXn4kCbcviYBKDdcsNzhOx6xxIPhIMnOVKcEZVlnGFmSiv
0a2XwVyi9BzXTCYSXfhJZQa10QvhA31UqROzffr/LnaqgT8cCqf8ZKemXMTNtBj1lFzEMFIvLPih
UlIae00z1enfMvhuXE2aJjTZy3ZMXPQn46K9E9CK1iw9nP+GgQng4bmT5QTmsX/fRToQerpAGzpB
bJrCR/v9qKPjXa1s/zECJ3RuAA/Oe+BKBUVixuLEzVzHqHNveNQ9lfcm1bcRnLJX5MWt5vOBvS/j
eFit44556ZhhZgB0E88YE3upTaqrnRtg91LuHmaPumkhFyMBFUBSReebCNKv0IIcwqNKaVMlKO4u
nXBz4rxmiloAO9GyDrzNiCLAZXImQo+jwS76r/QAyDzGClBX7ttXnPjFFZ04VofQyxMgt8c13VNY
AURx0gBSIHy3kAf+QumcbZUjmthr4fwGFaHCdnlBQPhVPmHGaygyF7uBBT3LmDOagcYqBG+lSN4j
bq+D+UXZ93x8LYiKyWnnHR+rbjNxGTHlsqO7We/lYrZDPUSlzgwxY+XZu6Gx5h3sTpoFBxc1gnCc
DelspIu9+J1IOO4/CX11UTeT6F61jkEDCKMpaEHLILfG5F10dhiyKmBqPXUSKSlq7mnXvg9m2eK/
owWpjEl0KoGy34XW2aSyu8cVwYakgD0P8pxqfiEK9kzhRleVyVF+HhDUJY4T51GwmpERDzDYayA8
1sZa6VyW6mdCT9HBHcl+0OPn7DG/ook75wSmReX8JjokJGpId7/kS25aY6YKRXBCejhRXriCVBuf
x3s6rDYgmK6z9kqDqmKuibMqxUDPruZDkVBxYb3mR82HEkiQJf2RLRzylCcZQKNEwn7I
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
qXwUbNWAqYbdpqBgu5V2Irr0yIHokdWq4yIsYatvbtHKhU5sTXcicxiWkZwMlmh7JxJXXORLT+ZU
v/PLV06P9w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
INsIPl3meZGaPEpm/0hY6qn6pNkmquxWy2FiThgvPkXiH85UtEqY8o5v8IRoHwlNbiFMfARYDbEO
+OZA2Z89jPi7vSGZam1nQVpdb9tTe8gy3sT0W8L8+/zNcgLhbWP9KgDZMNF+3YJnaj0hueORxLD7
CetUAimRvUF+Ldr4nyU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gJNTE+b/peQ4Oto07xlVbEfbFZ6nMfBGBuiUK4g+q+PLYtJWQI7QotLPwqtbFK07bXzvTJuyp/V5
wl4PKEJefSdYOEbPh6MIoiuvoQGJTFadYzFpMqBoF16yqhXJkL2oVtmXvJfQIITgSFazvP3qKZh3
NjuPtF1edJvfzpI7PLpFpZGoayowx6z/jtYsnIk2GP0W7YdZ9cOlkiSH2S1km12oKXLOaR0rDUTJ
ebEra0Bgy/Z3Q2E/7BECOXrujkXocR8xNi5Eaeaa53/ccDlgYYbn9NCrztVKJ5qtFbzqTQTW0d9a
mJndrp56FTBESQa//wxKfj8ZblMcoVBhTmzhNQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
xGHFc5dhsERwTBJ6HzSxtgI4YwpmHAsH9SafoAvaDa+cI2KAeGL0jrTiG3tkhsE6iSwJrqEOYnBt
n+EBnh1QW0+XSDRvU22yYrXld4AFAowoDmmRvGl8seLeA88PptewzCsn0OcE/MP4++TlNv7LK5dv
mheDDGnWdYqkYHdJIIs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Jbuyhmw//VZkr7Ws9+6WrN6Lj7dPBf/FX+UDLxKbBrhbv56fo3Y5D7icn71R0xbIApuFFtR8Iwcm
uySbAa59erYexsrtv2JwyehWzp7rsT+wE9FVJrZ76BH99VmVzK8R26yYJmnQOxniTZ9Bpt/l1Hgp
bqR9KddxVv7YR/TVF4FIjFACcu1LMYgxNBjvUjYUdYT1kFzIT54fa5kEBMPS2KGJrfY9RdbMnuHO
JIGhONlUF43KljQ2n+XLyCeaL8y6a2Zgqg+6lrVG6Ztpt3ZM95CTfiRQvsefR4QauRmUQSbN7I6O
wmyxcB0504V7UGeVSRNaInvWNlHwpFrgxy052A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19488)
`protect data_block
ZOdI0iP37J9pIcofeEB28BfxN2U3/rji4ipjw5lr6o3x4jhbCjwb7Ztbz/CLVL8St7mYcvoL/dYq
5+gWUzsl7Ydljsakd2HM7+lvdUDYlMDu1ak7l4pPaH7afx0UDQEPoC7zbAM7mpb1xLfrpqGnpVW2
JbrdFDxT9mszhfrRlEm26YIfkwPke8Y1y7yypDB6JxxAn1+nYfiPM1gklBA/wAmNFZ/fUDPztbOx
fr+b3oAiKEicuQhOXDU2b2grmWbhknxewEgKnKv+W2/jdejqfVh7P4/yV3VnVWs4fWuMZRv91LRr
Fm3vspLbkewYDRcreiIAMYIyc7Rt6gqq5p5+awdEBeWb14JtRbIG5FGJRFY6yuZDzFP7Mt9HWu8v
GpOIzL522uTZg9CYRRXFlBitsgVKBZiJy0ni8tiLM51tYJMvrl9gigTn9+YckK1bLrNGcxIrwzjt
nHffYtRVHgweShPwnVv/aUkIiUM2O5lqvxwKvs7dzXxv2Q2adgle1XLlAH67+p1MgkWk+mbXVU6H
wJUheYWopF/lhgFE61ivB1qTJyd6j1lMaPiKTsAAtEuxaBfbCEXNH1T3wPlCYZxUtB+okycwL9oC
coCvP2Geu8Y0Z1mNKu7u0R8xw9OB1EJ6GRlt3Aj7C0Xguq6pyRnZrSTNGRaZDZe6PLh3Dx2Xdqa8
Um7mAdWU6wYY0qMQxPOmrYxh2n1XILRKUR+dNrHLwP0+8SUdSN0cMr5S5UuoX5Ob1ppAwFqm9KEk
6ifP2WRzfl0YqeUpeDOGXruOl2JKkdlldvfm2LgjUXgm/Ei22Bc2gPEmFoRTYyr0QKH9vH2DaJDW
Bxr27qjuywr6ffYod05Czc6HCqt2BmVJbhic5tbUV1TJs7vYHLBZI/LmngPRp090E12m2t8MpsaQ
iOfQQO5U4wLXFut3X12TKMAHeP7k2TBQwGDj8J+4qe5FuoExKXd+WGpIA5rWm83BPjZb6k4s5aUj
nH+x8zoZet6NMQcvzm3mHy7vvXnqbtFBC39UEXGqqO1XNNaeNZIgigmeCaA/C30Zp9v8TRgXqiWi
g9NM40arYrmkXiDwNOUx9Pk81z7g7JAGAtzIdlYeCt7a+vbbhkpWODL21g4pWMDJ8hepuU/Ji6CY
2VAtCQtkpi5p+tunmxw3aRdrqSNoPfi8B9Y3SgSgfvBGzOPonbaDIdGJJEuxcb29Hxu6f2FLVA+O
KpKRALtdUC/kLjpzkkJ1eAvNARPe0fccPhw9fweR+kIaAncKZuymXizBwJ+IVqoR+rE6v5PtloS8
Y+9zQQ6zStv/79cXQQ1H7dmZBpqdeyQj1Lyv2lRAcC+y8t5Tjv+rcg1JLydWS9coiEt3mLsLhuS7
mteHH+MtWou51Ez4DLMgXkanfxi2BQXV8dJrV2tNEwySHkKmER9y44AVhUqEQj40EMGUWxTxInDA
ESfN+BZgU+1qhi6yXqdSHiDd2J5mfapKajD4w28dQwZ1hEMfSWqRyPObgUHIzd85zk5cToJP2g8i
TOJHuiObOhXQWiBtYIUms9teUuGI1+mZIy74ikDrmh9KcMXZuV54+jEfJG/F63QPQPwPlbomNbTb
t/QEWX0gkdwe/ZHejgg9lO5KtVVeY2W71CPPS7pBYs55eQFlDv7Y8tsi9buPuoF01KN/4cyGFtzJ
FDWRo0prEZVw7QN1HyyoGO+OgCWSJ9+J6cgQ1pFodl9NB1TphCx7mWg2t8aVFfTkQnaFcfvcpusY
6Yn53kU9irRsop0uTzTea1wKd01tWzA52vKPnFE1SLb+Q5xwGLFAI+xej7gm2ooEwlb2a6mSYxlT
YxZtrtZwBN5i7j7UO7FYj7rNr1E8Jn6gSErhxJcgO2hPdsx0RsuSCvWGtefN/GSkrXQesBzAdu2Y
mhgFEEk8LmYSlwQj1rDpWCCr07lzqs3R0y13S64VG+aYH4l8gIyd7vL9LURq5kOyAo0Hxhp9uvdP
JihCbqqBK11Sr1kXE3cL7l2m7U7a11LRcNLMFJDrTzezn3/7INa8q36MwZ1eh0SHcyQaKutkRd50
h9UEA+lnVTIzi9VjSwe5J06ax+ANn55f9UtPIRGqQQOuRkrm95mU86dcNeoqKAOQ0VEcQUR2wwLv
xO28IqToexdE3JBJbOIE/Acrz+opvMl3gE3T1t1CeVw//jc1Wg22ZfVG3niStXvLtetMtZA1qgdK
Hk93Hk2AsTdMP4EJK8O5uqpGNGrYV2dD0YpmxSfDUcHapV0gXDkLdn02Veqq60L+VM8yAs+8ZgDB
AalwWM/OOsLPi1kNzjfoy1rgD9mbQIPMx79nfBn0ZYOldkgUm+4pc7ch9ASgS/UOoaQobUfGfTxh
DrqkbkoJY8DWgvSD3LgwlZ+dfTqLueqxJaGEf2j3CPrTWN53pjW5GmsjM7kmwd49yWJ3Y9gIDacW
854gKsux7xL1kQ1EvEbIpzynvVW8FwUSKaQIXv3QXQehbvBNe2+NFrG42fm6Bt1Jnn2EpTZPmmMJ
BAM8y7hqIqJAEJttbS+eO6WqJHTXs3Uj9EfGLVVQM3mk7osvQtCw0+6qgal2X/MGFRFc8Jebq6n0
L0aAFwCmGk1QX6Ohr2nM6o3xqF+a7E3y+WFlKuvrDsLQzHEJY3duKaR+E4vONhvRJfqUgvFZewMs
0cD0nWCm5Ka/yfI90gTofvZi4Fgk24utJcaOqVqBCPGcu9MaPidFKgKGFnyr6M6mqyKQuEXbY54g
ifbECttY050nG9H9z/k9mdEuEHLhrMQ0kLmY5SAR3JiFIms8dtKPIDChKlPIRgI5ynAyoa9HiAmA
IWmQTzK9dkUvKE7S3+mo5SoulQ3B+qkEfaitytlI13392Drr7F09ThJgADrcTyMsN8oF32+AXh70
rpc6mltRk269YM05X+jXsfTNb0bO6Mc5eAesoLYSwqm1CGCb/HY5RME2TlqNUZQZPHZI+7Jo1wwf
FZ2e/pehzqf16buKyw6zBCoDvSJX09g7wnzGn9aLKIuRKmRE+3TgvvHQMLK2WzYKKVthAW5A5pPe
rRZ7RqJ7eAKRNf27mgY3XnVA6D+tK8+N97w+zQKprfVjpTrZ3qwpfhHEuzv2o26vH7ExL9HxN2+L
cLxy5aArT6gdlf9cyhHLLUh8XicnuHHDW8BsKRtq5JhAg5zTf6KJRN0uhArS1djeg4MgOr+2G+8K
4gapi6CGS0I8j65GpZCo8ZW6Bcgc3i0BRKVprsXfScxkip29co0K96l/tGe6hc+SVuzX2pM2mabv
KiolZIb5BUaHKV66YIoDnQtgg/dJeCPkKt1F8a5FfkF37NKOfsYsxG49crqXmFnW7t+OFJarMj71
ZvwVNmILzHLaNJrT/JOOnsVBqxvOhqWB93VDTcDFqz3eooibgxeBW07NBVLwzjqNK6BdFzbaN2zn
mTTnx2iq3oLwKdblWBqJtUF3EbYDtodJ52Lq0x0g88JuSDa9TjhY9PRog+dv9KcjX14bMsKTwxLH
7kvjetk2XsiMJPW1z+Rn/7Qpn2fFsjh2SO6yiUj3lwxIlj91uK299l0yyu90Xud+qlvA5OqPm17c
wliUBU/xZso/v2DmL24cP+KGT1LjyylAkqnFx4LKM1ZGmlG7pPNW1MlXVmQ2Ix1Y5vIbQO/ck67/
1DkqUFNDzljtYy/UVtBSJptSsr/EQkcx40pNjmOO1AFtca8Y7rsc9a4ilBz2sqfQbcQvY1oEgLzw
xHnX+6HLkz9u9F01n8Pu8to8TTYoF88QkE2xrpE/s1nh7eeTcUydzoSz50VNK2Dp+sELeYyMLbPr
quzG/O3SBcG84HmftvcopYAiCkvKoH8gTwdWNbP+VeTr3gu/se5YPo4Eh64kGMwD4s2pHI3C7WjP
OHMe8FfgFBSP/00ItXE5PAgWP46iviqBvNLeXChWU+oTNyXnIuAAXEE17vYDCvusRbCk16RXP3To
v/LDgUlNiQiFZ3MzaFFoE0cwNy3GshCm8sNTGQaXOybw5lCJIsHhFRLvhh6yp4Ejy4+Xf4sODqC6
VybJlZkv7jT+sG+GgUyIG8hHGSpM997CqYi/pKtbrK6AfXU0tlL+fDDdxFjv88D2ymeVIN2JREmy
0m0kOdP2fYA7p20Nct6hi3VYi26+g3nAFgWOS9p/uCt28qYHtuMUqd4BH+WHeBDwzgGpjFslB1vy
d1JtXXHmiFz5fUv+vCXFPGNesDgbSOwXh032Pkv09zTgXwIL2pcF43Uc57ISMKf01sBAw7gRDGFp
yDH+0KdhHWURhzKBmgm94cifysCskBxhQtiQiFznh2Kn/Qr2hdHqIHVBFr0/oCL3WfLjhztQgpeH
/XBEFo71zvd1nbpq5mCaEJuR3napCAaaht1bmTRGt+QGlZysLO0js8V8N8Y8vFVsA1+muSmyhZ4U
NeOxfxrBZ4FGHv/neKktZyNX4qKBBjJJyCHGKU/tLmdB29Jk1Nn2JBmaI4+GNcM97t6EBaSDoFWi
O9Ww+w/13btpNXWBrFLJgPSdN7YDRhczAsFIhwTfUDmEdfSeFLf1XkbbRDgpHOdyLfAyTWSWs8bX
Mg+XifY7MTVYCw0IFNWj2w8CpW2VIFVKaAxwpHoCS1aUSMYN34zkkCUB6leskZ4s13wSex+BHur9
qfdwvHGk40WRwa6xStvNoLfcN2PMiv0z13UvsyFLv9PsdA4lrzfMVH3HRlIz1c9+6o01uPuGQJyb
/5jIMkJz2IbWV3WjW7HZDM0et+LpVmwRKvobZ6NTAyXOSAJQTOKqZwOo0En+FStcHJyqysjhoJhQ
XN4q7KLrCbrv+t2MmUIDHrlXbMi0EhI6tF+Yl+X5wxB7w1PnABLrOU6hqOgBVhYDVGjnSEd4vnhe
mg77HyXxiL8VfKFFmblCGsv6XNHfvbe2apWbaJLouWczLl/LeyrZF0TqvLjleHJCmCysLVgE9gQl
fv0yqg7nr3f5pA4bPyZIe/Cqb2LyWv4nems9/2B2BLZQMTj6ExmqOPnd/URjkNGQ1tl6UBYDvjU+
SmE+uYVPPmrw1wMN1B0VeAlAGLSlHq6A/kSumhbQ4Ozmbv6Jb5WPZfb900wbF3vMkGRVun+zjy22
NH+4MaE7E6kLEyu0Gz9X9F9EvMkjMeLoB1BrW9lgMcS2MaQC6ycK6bjuI3xZwAADZrC07Gfv/R4k
hD4C+jFX/I+l49sSOZ+I4Va7WvOoqBv/vFdon6jAfQZUWHTEZbIAc8CR1owkpMK0ruKEny+MGM7q
bA/EeItFHMnZ+8l1bWGHngzZH/X7BgmPhtDFU8OaZouYQzJ1gxLFkW9ylUBJmXZNS9X9PfTQx4RH
2DuWIoWf2XZdlOXgOeZolu8v741TXGSdjV3W20X2NLD7Es4on7oHPJ3WdwfpL+kvFqm2vjQwYeys
Gjz+o0A0uMDjCLnK3ubECYI1aaNcOKJRxML+0lD8nFaSHz5InhhkZ8AQesugPedEsDMkXJL1ODY3
04gEn1/p/j+zB6Oa49ti+5Z7IhXB2jAAcnJzDfiwSIwHPzOJkAvbAwgqKM4k0VIq/mhaWBmC+z8O
ZIzpotsf4G/GSlcSPG3nKrDJQpYaSH7WxZ6P/lj/eDFq8Kcbqv56PdGJWZmALsL9xXTTLH5rRN6V
kmaBHX7zGgUlr8iSqwaD+8uUL4Nl3QKj1EHmDoxpFtkzgoqqyRz5f9ttxWJ4Fh99q8DsbcXyUFzB
Apf567qAGFb5gFjKlOEWCLQAv4tWjONBwZROOHN3MEBYZi0zI+0NSpHGcIzzIKIz/FLBqG/qlMne
7upS1NnlCSBvoHFxzPxEYW0UJSn59C1EpC2Xcpo/ZDegNfmB4Q5Y1RtwJN1H3BZFtGcc+pBu0gaR
8ueMPiIIUMrbly1C8DFn2wGpwFGsIdgaCDPKAcHYQu+56gKAmNFXHntiMyzJ5ZMQPEKe81SEJbyP
pZBUKiJtcacOhGCRtEraA0b4dZpNv5avVlbJ71S8o/W5w0XrS59r6RS2H5C1jNQr+SyiLavq0nR+
L0Z8jvFzWbZeTpNWmtBKiQJ9C4y14hyPqpBzGYZXYPyDT9PF+P/6JLG+nWBmphjAeKYIskHdar9t
WFCHvpssSnGuNM3IKMWdpHij3uH7EBSO7k4PQFN5Sg1bg62JHbx64ByZZdl8mdeCVMDBH0BbcfJO
ZgJnRQGkY0AK11jtz2QAYUd572RYvLf79P7X6y3IWcKOELGKfoJgf2nzoZXve1zrbXnKZ5I57B1j
KuTBbm4ohJnTxKTBhJxBRrABE2XBmRrHrq4ZSVXlOiJ3jicxVR3IsIb0Qi9tLMZ0xZ/ox0ZTv65c
Os0VOgThk7tJ7SSYdkXCZUusgEezAv1HcaO8qXQgqYo5jrwVJrg3fFLOEKiB1WCddKthrwh7ucoj
CRgQ64q+jfpC4UlpEG4Y3iFHg0oiwVQuXfyOqrXOe3LYFcE0OjZu6bTUc79lvgVMmSaBduPOeY8W
ACKO9IG5MtEGNOXxVAEivJcLPs2FYO6NvohsA19nJFw42p0sWFyO/cX/ziW+iQanfx8pmE50j/Lj
HDX9D7GT+V0fXaV2OPECFtOK98gYHuTFjg8G6Vg6GYA/LcJoO8xTCpeH0hxALcKMC+sUfkKv47L7
I6MZs71b729VW16ietYBR2xr45jKWxmP90n3F7073OuxhK8XDEl25LMNdWljP99CP0T+8W+F2t9M
COpLJt/2vf/AFsHPD7+zpqmLnuKhJdaJt4Xv4irm558MLxmgVcYult4szCO6epTqi8xBO4lgViOJ
L1AQ34yGCDsdWqmlrHU5R52tgWjWR0VU6+M7DBLkr9detKgC0iUBPHrIQ2xE/jHlqjVJ1K1zpXNd
AnXJHPSA53dE98SmHldQA0XqC3gnDjYrdfP7m5CssIRDusCQ6fIzhnYIhdvCh5yvnRx56LUo5kqq
jGzTxfX/7lXKl6joSGrxYafMf82zWpGmkZBP7HMIaJOaiAbqEqtp8FA+gX+4ixw4RXkTKIyOgKqC
s6t+GorHun2o0zjflqUl+dkoBTpEaHGbgLWnGBNtsI6sPvgJNebKV1JLH5p2xNZboBO/vQ5eP+PT
/pPKE2ddDZ4xKOcJmd8l43ztFtAq/+z1OIRdxAvseuHcTtKqo8+S4MoC8A8JBNEA0nDFzQfTgz0G
430uXYaVmT3OHlBYclptDMuAFqx6ZxovFs6UEa4kHc0mLNhWZdhjmo8Aoo1Q6tVr5fJWOJYuTXSK
og8w/n91yf5U97nHbr4LRVe3tg0GV+UTPnMkGHzDiqY9RMdG+jy5koiCaY8jm+loir5BZQmyrBmW
65eDja2+p8o81LSAaKntGuHfNvxJ+nna7lpJrIJm5dCwKs9oQ58htKhUQ0WepBnaOQtZHl8V+wMk
t5NyunSHq6QZQyCwQ0LOyLlYvLhCpz87qjH6QKc+5APE8G8RJbVpX1IQ01MBn96f6s3SlKlRXjZR
kEUyX8p9mWKPqXhQj4ewGMHrlGr44ZFAZYvVr6Lz0lkK9c1d5HayuqPwhxFlIDus8oUh6xpPBj6s
1EgaS9FXkkLASMBsjLbWb+zODzGi1UI35pyKgxsQ3UnUfUWOkg8ui0hxlsWuYXKuEl938GklrUF0
V7wGhzbZPSQ+LduiPiUZjBv5HuyHzHx6WvwIWa44CntdL93hmPW3c65OMP/CRE53kzuFrjxzVSmc
xUq8+H1FYD4Lzwd7TzIqPxNRNYZ/WCsyXw00XGDVfAI6m/48XEYF4NeyH+Cc4szS4gilQbiSn2p8
/XS2J1BeltZwDzkVOCOSydzJuuy/HU8mG/wfTED1PbJo8klxkiA973QJ0/YJyAJLZen8BiQRgVWE
oZOM6nQlH5qRpBIDob4O40KaFnvvRMQlrwgrDmMAzsO9jQSW7lCjQ0AAVfzmKQYswGrugd2g7r8h
nnMEOroFe5e7AjJ5wRbAmalENw9dShGaHlMfuTZ2uX29Axr7U3TQjSo8gkaNnfSyPlXg0kU4UT5n
RhiE7yi2Eg0wjjWBe4gmaDIR6okrQPCGiToeHkQbBMBin89XWsyKa4lL5WT3vOqybyK2HxC6iUYD
Q6jGsUaHT4wWkxqQP6I6LdwgmvbwXXqSpJtb1uTAehRtFg8DkNifsn1PcyfP8g71PZBor5BPcvm7
VG6eF00tBsxZXlR8OcGdZia2NOUG5WLKA0s43u3B6TrLWeqLCYyH+je/y4wS94ej3tutFHKWFoux
VSXzgZNpzIvuDuYEAvcISLuM+Zd4cMAztnGYnSd+uRo026E4MgjlU6R4V+/R3UypOrzL8ZNgGoxC
16F4pQMhQ3duPwW1GqLqNhl8D/GVA1CtBbuVi0ypa7vkp0l2Gphai7KRkUbMXhiB8Wivy/yD+sFc
9xh/L6WInlTgGYJX5zYywiq3zEi9UzpxDfMos40iVDirLEuaQoOpePqp31hMdUjP0+z0TCfK7Urm
57MhQkhVqzUGETerpsEEa5BrJ5wBXzc85hNnfLkow4HljHEQgPDiG+IES8TTjf7P1l5rn9a985Zx
wBWwj3MvlQ62+0zqXuewp/5D8S5Dij1AdZ8Xt1lTvGeTOWmavqT48i13AcK7TUvH6L1jGau07pU9
yqFoz7D1MwYcSQbD3I/Wjqfe91HvMQ7Brkn/5FM/WIa5d+uat3WBf8fkIEwmJM3ENDekN+NEZ4ZY
QLzuxEgU3KkE/woVVA7siUEvnZHGBl8SJbJRoEyRiVFyecbcXeqX1B2X8ALSWJfDQg+p0pZSUczD
14hLfBmgqiVG7KrUeFm4O/FcLXBxSbxaFt7zesVQt5YSf3s7jWRhsMhmSuRsdOF6Rihe9+v0mFGb
yC9Um42IfHYWn57Q9T+nUTa6bIVg+PRnvukAKBQJNGQ2bWNJdfm2Q14PPg8KZjyjQaeLZmEw27vG
elXzxBY/uTKIV1N5H7B2vhyIQXikKCAErO+PlmGhKoGQTiIi/6c49q5c+GSjOe2uCOcUIhr57Iv4
0LO4ZUBobtD6gQlshJqtYL53YNZWnKWJKQUigaASj7xbFXm5hsoLLMm9dJHL4VjcNFxjwkGLV1Uj
CDWuM+vuDTi8ZdMCywHxmsX/eDEKthG7fEsqfIc7PRtYXILMw3LHRfx6B4I5jzhHOTX+6nc5yXrz
QtVmvcCxkW9PYg3IQTdJqKFOPOlRJAkDNTZqp3J/zwLpHvTLBI465TQwSuudQn9TpW1vJOZivfRc
EI7qtVcvVuangZczeqozQMk55FjovFRAwb0EG0f+GBZAqVRikwMrHn0my/sahmY2gF3dYC9aadPp
CDDb4DVCHkRc7gG8Vm3/R6O03bZoSK34U+RaZZSz+8yAG8gZq7ju47Kc4f+bGoe3Gg57z6jf5sWk
orfEilazEbr5JglorSuGC4JR5SVHvXgjXmuaEkQ/KcnH2IFS1XAX1Wqy1Zes18OA92gQLeFYTKQr
C+Nh9BjqF60bG/R0UGRYrfku9slEx4DtdaE7rDMeTKaYXL7HUD2Vsb+F50IDvTGSi/NHW+gP3f1A
Tntt7UG4hG3ZD8MeiquXQBPnrFdS+9cRMhrDaF341Pig5IM2pCbCHdByLn66Z5DuXyVrdmgJuTEF
PdMWNuVft7XZZd5rL50fsYFP5cymcutTtTQE1HjO89/otsz68b79N6Bo/fVI4LhS722PM41ziTqJ
j+kAnzXOof4Cm2ReYmZs5wI2dVRjNE4R9jwhoy8997sUpqIWgLDdgE4EOjK4tGOo1zEShO8jN/61
+PQcsRdn4pmrd9/CBiJA65t9iZk1CZ7wP/7yCFX3AZsUGuEpLYTuO4ihhcfBav59iYQ4bq9OTaA5
SUZEmlFvfeEiBAXMguraIWgZQC4Hgcz3hXWC6vxzNxy+Lygia+Zkg4/lWKENEDmw0mmnelBIPjcG
K1JkXaNkwM2+ZFsXy6nbhQrXqzPBGZIuyZQez1vjehRNvo6z2wg1x1k8ID544Ny0Pd6efVT06cVo
EDf89EuQV7K0cYianx5272OXQOiGwOFVsTLgxmiV/pQunpt2bkccDyH+mWo+kPWY+KeuAN7CbolU
scATD4td3C8sZMzVuelvzRiiCoDVD5M3glOiQmFkAB3ltseppJtvo5npKFKkiWItWboh9DMTjq0u
78HJp1uDpD486MfP9Iu7DHLNonjcE3eo6eU1xe2T5nprH+K85t+ZFSfTlRuZPFItLh/PmrO7zk6L
QK5VzkobTpC550XrT1GXQ51w0hTdXOblpXewLQKhbsP66lSlxFNfr102C0DD+SmMZY2pjs5adlCI
eG8hOTnnSa4ePwzMGQLmlVSi3n/H7QUYu2ZdP02JLCGY95ODI6GQFcsFNhN7ls0Qe+20T70+pjWl
c6V9/Hw9zHH47RAbjxvC/uqNmS24qlaUAHHgeo/FlHh+9Elri8ulMtHME/j8wugCm8y/nsSA+Osv
/zUx83XHyRzxoQA8U+xLKx7WPAdL6K7E9kndfFMPieKaCuqGi1pKVOwAAjd/8DeoNLtLpyJ8tO5Q
o9yhp4oBzo0o8f+Yfh0ME1moCvQfh+eAVwHirX6M0s2AAB1mKJ6ysWEPNuNae5HIbntrtQprc/Rr
cKRA/T9eT/5wsw03kxwCfN6NF8N0JrNfAt+YJE1oDgsniOQUKRCgxVTR/IChSz8Im36opU+6mPyF
ROgk83e6AlTSldEBpgpvRNkdM/pTwrcujr1hFmu9Kbv7gT3Cztynx9Q6Mm2Gh2nUgrLYBi4QNFY1
ZG1pAQxz2RBkEFZbQyBBSXSrmUmt04pkD68dr9Yblh0Xx9Px1yN0K5nQ+ot/XjFhgsNAuUAvL4F5
Rt/DagoRxUnaA8kvBsKsS7Al2Cr/+/H2bcDqW5OM8s7soFA20umhBHYgTPx8FQjJxTEnruTS0hIA
OVjyIC4hE+phkDW6eM3sYtfnTyBPZplKM6uCnMxSQy1bjF7I8I8Z0uydWQsGcmovcltxr9Kmkal4
ok79yKWvgyBOqmxPSYZslrWWqVQwWUEV1xNHCSuGZeUaZN1bnbzoqYU5+Gmi3PVSDQmvZ7se/S6C
pQ1moDWW/Jd2ucZJSaH/0+IR9o7U5hnlR03DmTdh7W3lXpgcQxEm9HP6tj6x31WhgA6qk4gepEQH
9MNHAdbfJ8O9WiBKHWkPD4QWA9VEYcSUpjlXVvB2n0CoB2Fg6rtWaZA0O5xDRl2edLOBeOT1PTW3
VtFcANlvNv1rKaXbMkVcCZOEBgt7mElBey/aHJj+Cf1jY79r166vJ2bltKppZO+MRKTtGYPabNXw
8K1jKOH2t955EjQn/Q2mIBUwW4zbI3fvgb8FdefF4zhk5LmyftMwYKC3e6QO42NzDDHHhpJAm4Yp
wmZpXCp/7cEIDTGc0s8CFVIkBihKIkix7NjwiSBdlrJqYOjSeCk7CMg9iBnTI3eaTXpk4zGzJ3xj
Q2z5G7+n7oZRauxksfbK7uD9XzSa1noiYCMDpex4A/GV9OgxSNiSIZiYejXVYyPVdcaNKm6bRtGs
DfFOM/v5FYr6GwjsmCuNFDzB9ble4pO6FHu5f7WaRKgTT50M419wqccbNQxgTVJ18MrOWDAtPEnU
zizTKTly9WCj03A1QU2chy4caSCdY4Dan4jruKnEBcG9an3z+8bVd0W92vpWrgVpwEzgiMKrZ9LV
bRz3hgSY7ducWWVVSp83NtnGmzUrknVo2zBk2ljyq5vduUHUi+vlIMJllc1AeWVjEuV4QoDRg1Sd
TDaLtmxeTNkRhflWmxRNzvknKbEYkTA78UZjzHGOe77VZq746wPsunGVeXwsUuDBupXJEO2/bb6L
lBvsHfl96lL/2ssXHpZG04FefSuMvBanmw3Nq+aHyxAnZE9Hid45tiSHkrnFgHz1YcljADC71HBF
bB9XvDfuMjknPWEB5A8MGT88XpXwCIrj4dYWoeaBJ7HNCirwoi6UBEihUMkaHf7xHLXn6oQcwPWR
KQO9QS0rfZ7LNvRWU+kLnHhah58DZmBiyQxVU+Er6XsSCspcKv+Of5p+zYkVi5ZxZ0CDi8B41/i0
9t7znMKYkYuP+XkYlIox2fc/7LudYWh1HT1GLKQHIMnbBaa/DllzNeL2FlXMa4BLVfp5nSddVtC7
gQnwLyjqtgqCa5gC333efhBWK/mD308DHTnrL9FeWQNjY9zu9nE5yzrKxX7KKsGIjts0iiW9MOL7
UF/1CZYyyGivDOJvs0TuYfzE5p8h7cLx6v1MLXNxfZNWKDAIyoGvkjJJP5bu1m9s48wS6X4IC0fE
o2OHyRifCCmuXL3rZ6qMDU7c3R+sq/bUS0obCbQqQ5ACvo4eEgnLV+8DhmYOGBs3t8sdoEMPPA5H
G06/GlYsTMWsdQTXMs9M+6mprdSLafqB1ljpYqi4I9lax3NCCpQC3VBPmmfhadn4dgW1ectldcUb
SMj+X5a9Jjejvd4WI7whQtCsBhl/1pRPRd6XhFFfot12PN0YI61ZcyYMvhkUAUkB8UJjdm3t04UI
Q6L43uCsc07a9NzLp5k9SdnLU1eChbaun3hlkvmLJdH6j3QRbig3icPL/UrsBMfXIBy4SIYSwk1M
3Gsyh8k5tqEyqIiCeGUifEnjh6GJ/TecFMU7f9XN3hjuGWOtvjEcuH0lCGX5qflStQmSv+gSZy1r
+zaAgBqKVNKPHI+NZVjqaFN3JwPXczXJB5LZDd7kyIELjMd7O91j17cdDcH26KX1mbu8UQPYhKZ5
nJGYx00MGTAi8kLGQogofKvqe9aCoIHF9hZlH9dwnC+4QwepTuERjGEnJAIMul+OT8WGZNXE/3vS
N4gZm5lC3WKlN20xOMzlGYXKlXgoIvfzn12NYE0sPR6Qyxd6fA0j+xBhhmwjS1GxYzqrTuFapicx
suu9jvhHhn6MNYit2B4p9ITIgUdsVdlzSYNjfQzb/aV68+frEMap3ro09ee/CzuqgQnl0XmE3JfG
h6lPdiVlUMFLIoIGBFJhCh3uMLiE1OIgJJWe79Ko8MPK2AqNhh1QMz9veFn6BIzjAEb33ge9Ha3z
wKKrgsvx1/yK6RlQ56nQUcGYfLNrHaoI/h6EyOy3o404WvJvsGMWN7kB2BOnvtCwxErwvMDqhZkO
HtJyZqlUhhiGrv/4JJ8sC4s73OCBqvAPNSYYGrwBN/T6n7FB0k9xU1BFq6rsRwjE4f3uSbIzeFiA
RV5iIYsLuBJRPDxFeOUlpEnVPK1F2hyj0gRCfk8XIrIv+xg7tSHY3+L47y1wY68vVSYPjNbBaLmN
bKrftWmKfOd8LzcEBF6x5UZp4NBgn4rkxuHCxPxFi8gWPWPhNPvN0kv4RuqwCM0G5IPqcbOh6EPR
jJcL7wZ1L+hZ1ewFkgD0Sq8JcYKNPM7oqaEu+ksFJi5lj6zyggc04pGiC7M2HqKMmMTaK0xYct8l
9j51jPJWBcYqwlz/1MU2BDtagClFz/kyfWkx0CRzV6D6I+Jpfrek1sa8VRqL/fNdavEfwlS/JpvC
ToGWBXEgJVvw+TKO0w3z6vO2w1Yi7grCOV/vjgQU1VrMyJGfjVsvVMO9VPJO6omjfq7tg0Yh9WHN
Gt294DFtRPhQVF3hmkpYb8r9ACTpbsTQ9yh3PYTjMIe84GcFNItCVU5+D+O4m6U4qHKse5yvyYML
nYh63MO4MQnAuNffrr+Z6sBOOXTL1pBa70y48XWSXxGAzImmrFCb68S5hR51wh4YqHS3C2veAtYQ
zqlTKcBVVZQ0JljYrnnsmgQBlLRiqNT00BMZTxYQyjKoeanfCOogKstRGShVPdF+we4+dd3gd73g
5nvDRTECRXFDKm1vi88YnHXqdw25zbwyjk0m0V3mbpEMEwiIV1PalDkb19Y+YHUR31K9/UsOx7ij
3Eh8pMNowZaRPhtXv13GYO5ZBJnlZmjUVCiXSsa/a65bG9i3Hvsw/4knTOeiqoxVLhS4008Wz2ul
j4mo68lfyzIsCtlPer5ktt5aiPOZEL1138tTGgPSV/M1GK7PFl2kWoyDpOYtiB0pGmGwJecqnvc8
7kdDPeF8mBQbe3arEM+j8zPR4mFp+IdlpDL2VZaVI0gNwny3zQjRJoKd4IYrKwK9tiyt7v5Pi1h7
OslZd6jhfnnbb2+5YLisYP3QLPMad6k2rr36mNc+hXaLp1NTdYXXKJBmujpzfueN7kJeJG92RzgA
BQGh/GemHF/dxf86KVdJMbj4zFn1+ZDnALLRzp2jg2oyoxgif5SLKF4eEI7qNOO+9TbGReUjjG96
8vDnL4wsWCKvz9p2LacSzQZ+/lBet2wM94jK8ceCdWmD0ELbvY/eU3MFyecVPbNprYS7anWM7QqI
H1G3QmTXb+xNtIcSPpvUisdDSfLTSpwxXxSOk1KPZqQtHXIusfAW0sRWUklURbOJ+zywP/h0oAJI
6D4Zg1q2asvJzkMVGXMKd33mXJSZmk5Q+2YU69TPoyYhqAiebDmJqfj791U89zaHJ4UfiuxFfWjx
ADjsSgS3FztSNpq0AakILVEglIng8VtDKNpFYb1R2QO39r2/uasuycRZHznbCB1AyzmYAel0EWKl
AOzqy4v8DLQ0MyDQYDPNBv9NPsymXNZkyfODrfprOEl9uuZdIaMBE6mO78L9VBU6AIdwU0GFD1oS
kq/3kUNpS97FKOnE5pDsz5h3QpywzRYwGBelUtZQeo7n1eS1NuzHKcjIh66Ps2SBHQa7WZtT3ngg
tXVI4ObH7xowh3BFU8ZY+LbHvfH8246xA8bNdQN15rIMRwZvnbXLKKAunF9YNYB53tjPXzhYMCpH
oZnmALAqU/VkMJLd3BsNTbszTNgsFobR44oNLTQRaNZ6NDkaJ8YvbdyYp14+vKv2neeollbMWjQa
3iYIwrVzEBESRHkdqgk6g+C74ZJJqjf2nmMcqwhRjyyGJxREiQ+krJfVBYGDkbTuCYQH8wu/AkmR
aJJjR5ZwKkkj1/Ol43aA8qh4wVqArqu72kAoHMiCE8y2Yvxp/kfz5nXTToDfTeA7pkRGyj81S97L
WDJ+mAmaFbC8/5dJwiUgeIpLbMRvpetQoelicvJRPgF9j3nTNWhaqI/JVVoPvhty2568j4ptv+ch
+KGZu6x4HShhnRPrKRKSuph7AXDkoQjVEE/GaiCBlucTCUyfySrMf9dTi+rEcWhot4OhKKvBuybK
qvmpBCG0uXnXvg0IPg1cxyWZWPWZ9xTBgKOYe97JBtCFFCO2uq2b2EAryG9eXxzRkQVNmMul2VSh
pPGpUWf3AwoefWpnrVofFdezR2wFY0ItdYxzSOPgXEC/er0Oz+9DikwFtE6sjmQK/e3t4lw5JIJA
icw/AFEnT1dVRSDDhMB5xSlTzhZ/0y69NYEPWJ1ucUA3APD/78tqEf44N6G7fcaSfb7vhvU2BfKM
2XqDMwewiefFPYld9wu7WDDLzoDCcRCFaDpbo296a0cDoTAbRJIqumrMAU/N8q0o4IuuRfI9NRTO
pAmjPMHH5A2sMZn1VfkR9fcroTtMBCZodf17robntScYst+eEezFt2oLFWvt/RGmXktF8g/+j/0e
qqeEPnUkgzq9gZVpY9PLC/RdAne9LxpXxza+sL3BbyBSNSuzPdodxfhov896WNlo/EYCGDddMfDr
w41x583iv0CFpxW+l1XuLHlqXLJhzvXnsrsFPQ66alGC79XKo3S+Oml+Hxl4gwrWaGJJ/lAJbFXa
YmYX3zGMcucWi9nMUqheZ1zCq6jE5Q66559+ZM+wlgIps7xtO+MCtz/Mv9aaXvkzyjezZqUz0Pou
FdyXhjjFzADhsUWTYBRO6cyX3ui/II7CtA21jYJAx3HniDgQeVj415Z0mA9Vip3xKT4cs2pt6Hwl
8NhG1ob4rrGdyyJuq3znjFScYDx9tqYn156Kka7G/yR99+7VpolDqfEzmyNz9fh0u25MwWXyEZ91
5gHYmWsCFZnJ9GKoXXmhPV+w6nGb3tBdjybta4SG3uI3gm9umNxV3cE3MM3ZF8KQH0y2auLnEWCY
wXM3n5S/ZMI3gV4Wcv0NPCMQo+9f1Dhazh1T5NxwcBTJ5BS2vFZw9sMO72TZMSJizfOHSCR5v4ra
Bwepv0lMdtZvG7YWdUWiYhIR2FmSnMP0BE/Locptinqnf/LMGiGv0frSnnD8KpReBVFvBc/Z11YL
YjZntdNhkrrKR004cIOiAW1H/eoN0ypLGaE6wDnMrIs5E9emuFzP0vkBfrfrZ8iSo2U7uJoAhTZ4
FT/bwDsyUj+2WxF8jfliczSAvw0KA7cPqc19+DXpkyJpHKQuSxIb0TF/Q9nH22i/Dk8jZRT3FdnA
ss0XHeX+I8SyVOYpjH4FeWaSdhz0pj5ICyb2H+g8KUqOohZq/XLG2P8GtU9ctoHET/+Z3AoE4VK6
2sgfTtKnnNV0PpjKt3LrhoVB7R9gFp4igZj1Jjt7/5gNnq3cjIU6Z7GJQGW6INAbBxFDiIZ05V0r
l8wxCeDr4QGhU96osl820FbDEZ9GJ9fcsMqUIlHA+fZpFZ2q2J6XsGQYKLIM2Zgi8+REF++YXVrw
3jkws3HW4wW3FEMXtZddrtSjbh5lOg2Kn1vIWiKWvVm09eSzqDUzxDHy2fcDgyvxA5hgbpMmR7FM
t66ELVZmUoBG7lgzqV10BN9pqj2TpghhBCqNmNhJhPTTx18RXm9VNQVw49iM4yqMYb6PbkVfFwxL
XOTYymQ0woqVheT6fgWy9mpvuXrPh7aXfeoBRC5o/AVS9mmbeHJoRThzVrWJ9q6HW3s/xhfdZ7/u
stsMnKrRK+KfmANE40pVNGMppr+YxxatTHj6VhsCy6/iQV/mxGAitcngqvPMgdASreskAHJIJEEJ
L5Ck2Ikw+3kswdXjz77DqCXO81Tjv5DKZN596CCW/FInU9ivZxmB4rL8Hdfhu7gjijvA2yBjCHRn
+xZuz51z28hyLlWKlmeDAmdGQGLOC4r7+Z1efxrgzAOuhQtmIGdUgB7IMi0F1twVaPHvoXtK74hV
vAFS2fk8CWm6M4rRC+HULQgc3TbYqJ7Oc1w2zhAyQxYHUyQDs9X+Zl9QCyY2aj0cQuXFFgDxCu1u
CMVVzbDcmDxWc13cGi5kHU3fTeevk4/1mQ2QFM1eTu/Ymp9wSH+X3lRsgoZrTkZ59bXzgD10XTwI
7YpLw8/VNynn/G9o/Q0DDSzlkn3dNEHh77H6h6UPhj7qJWK1XOZHw/dlfxr2jKG7Aw7FlPZIIlki
wtEmp98EHkwtbEhl3c7EAbhZ0BHVGt3LRS15OcyM5q0aToxBYEc/H9bA6vltNMKgWup7GFoyWzzS
PrQsed7SVdojLwSjm7fShsQtn6iRYr/HF721uPTyJVxr2rVQkkBPjxztsjIOJbrDjFXtA73As39/
SsajCPElnI3xi0vqyzMqRNox8YjTX5OFXKf4N5lXLeB8zBBM6tfafHAl9XoEomiNrqz7SRro1pm/
AN5irpgT9MagZ4GxJBIuMH6DjH5LFri5BfYiSSPgoonrhRtkjQ0lpuDwVg1ISdmidDHQs2fKaUg0
F84bjODLCLLTcOIa6yYbpKrYhGGAMNBR2uqV1cf8dorx9WXBK7dIfV7ZrSMs8u3L34MGDanAwCGE
Oa2Qofx3hBfjTxKI79vSt/yE3fcvOJjlsgBTect617eEi65JxFIT8vob6NpawJxzA1Ba1SbvKFdN
UtbEgbtqV+HFAR3lzzApMZ63feuScpmxArM/1a4CvSZdhqKdM7kOMzOymt02G4QkqtAvJTa7jfGo
8Gg7NdSAln8fEgc39C/oXTMO1V8yy7IJBUuTnFymU6Js976h7veI9V27QsM3vLJTA9nat6SjJrbX
AW6eGw3fqklYB8J+TO8anxWd8WRs6L9/EaRCYIdExXa+ggeHWCcwnrJd3ooAT7Qu6Y7Z8ZiTFwpQ
XWLFUpAudgN8BM8iQMxnaKig0zf0yzDTVtjUNMGews0OXXTlfpQfRF6IbQ2O759fi+wcAycyTL4p
sFoWnCUAjCrdPVCW5QFsYkkQB1IVxcTSN2YLQlI1jB6ebRW8T8uRoTBFM46e/UiofESlku5RXt3R
RuZKA2kNXCnwEEi9WsWlPnqUkTk/a1mr5HYzvQn5Z7wD1mjI3LJXzn3ZXggyJn0/7Z8N5+D2Wj5C
Etc0RLE1VCidAgbuCZXOPI7nmD876eL/tL2Mb9mgeuUGF6hhmopl3ldHGIaC02IvDr3C8qyWPA11
ntJORuBtzSyip1mRXxSX1oqW3ttVk1fxE73bXQRKyBYZZLYLvFbJ7QUKYcjKgiYj9houLyATyQUA
FTrUvtfyn90gumSw0gU6oKEnpuj5Pum5VGH+RrJYyCL0+Rr+0Wc0lv8bvsY4P9M5WnNuQO4QwMGM
SskrJbXpQQfSGEb8CiLpKxZnOcNPq/zx1uP767azQxnGhNQT1wCVPn2I1JgOs58RhU2+m31BE6n0
NjwE0WhUV42ovkDYmP5Y9+2sjZnKcWI1lwVFnxtOCkHW/lau9vYugOjvylRwYbEa5VMO6p+e2UPz
aYjpb0N7WH3L9kVdYwycoSpGsalq3he9pi2v/N0xWZeIbCh7kSuqlyfc2aBh5gdwe88e63y+LNNI
Q+cv4XtxApBYxEacJSeAdMkZxxpWipFPuZZrBqrFIiu+H2XpFzIXhdI2msL0a7Ya/299xdI7yV8m
lafqp9Kr4E5a2mEQvqf931l3hRpnTtDRhRkyHmVYNwCJmTqTPfijzEZddiHulzW3DkY0I45WYzh1
cOMg7CFPruB1xl3sFwCF3X0AC8ZtGM2+2keo1+bAFXy7Uv6Zs6Mg8Na5AKmB99z9re/n2y1yULwg
1CQCcfB0dixNs4sa4X+RoClWqSKjG3A2YfCd5oVnEigdeHh8snESMoU/gFdxA2NwVXjys6LasXAf
Z/I2n8kkkObF0bDpPyqk3BdKdgZ5cC3TtvWJJzGYLvCybE8nffUuxddFuXHiH20dufRso9N/UeQv
ImcxMGuZMmoJzWbre2g1tyRT2HyQcALC3KzNjN/kQVamUrIzLWnuyfvnk1UslfNjV5Oa6M0cg+Ul
hhar8m4jAlo6nFr91maBQyGR0IY1aqMIp2Gx5M4kqHoKPB+9LLGbF7MHf8y11QG+a82k76s+WyV6
DDxWXD0Y+y7QljEZd4ePpZpRUZdBUu/EAEdprLG6xIdRjub0j4w/JBb+I8ifAmuH0ShqX5XadNPm
b/8GQYy937ZMLL4h8gfSD0T9GV9cG82C0Mii6iZUm+yN5v19mgt3YoYA0vrH2ggIfTX/SVqsI7Ty
geHGCEkx1SLfsJDSGZlxm/vEKiCuQevsr86HnQhtojVDkh5jzVm2M98UnjSym4upA5ykcomvrOLP
vKODalzuAqaBHVSVWWNRbANtxvtKmW+e1L7tOY/N443Y2te2CJMbSDFGQNaICSV/5XovuKRbB8kg
eCT+d4NWMaHzqwDELBbga2TW974YieKMVaDuEtxEmUwZV5zkh+2KAVdWmDXINfyCkiLdq+VHRo36
7JnAEsa/A8cLhoOk7ybGqRHqLXv0cVQSn5MROmAn+GNRV192FoReEVqBeHgAvnF3BwICG/JafxM9
lvgI4eB4icenASQ213UMa1hq9+pFKXQaXUgmEj0c+xfXxMxiwY/z6Q+pcKVY4CS5dQuZidOzMoeo
/EMAJjBVTDm1tYyndt9QoyQxdFlxixRe2fibzBLeMrDdEjFbBmkpNRqxJ06eIXpx7y5/8ikrjQKk
pmIU8nTb7p/BrPf0dfOURlbxCTJDEtPrOFgtYer/VT78cZdyrtFpZJrBeOokMwcL+JYLKW294ENt
F+SxARXUAVMukKQgwpkIYpnVWDfLkkUOfB/an05veHeFQhLFv3IVfjTiUqERktn4+ECNzfqeJJXw
n+3OSYU5bSBRC1IdTg6miHAQo4Z4f2B41m9/nImK304bqiyZixgVHuQxl4rBNXBB/JNYmjoJIQoB
gAFTNSrq1JzqtjJbZV56DRMWxwKySe+bDVbC4lJ6SJjXiLgEI0GSW6w8M+hAGD5rWlsJIl1g2hz0
z2DsOnShdsdJINW9cUqWGCIkc0zVggFSBa/0UrRK3xcDvlFe0l03hoIFtd+KZx2EUb5URB5VwHi7
z7WlNUrprlD4LJ1ED23wVJaQ6VXGqze0QLKCkA1DNEfBgxFhuoIiXZJzk/2u7MhcjRlKO6uuO/44
8hfr7Oqt9zCgW2EUADjI7Ba+yXeNvqxY6Ao4rO8hBrV3z4draARgiXrmW5PKv7KCGRa1OKRw54Gw
uqBkh8vi2WdRv17uhVlnoVJdDH8Y4J+wb0UXfuFDyhx2UqSfc0ruVqjIl8PuicuGGW/44SWcrWtX
xE1sXyX3OMpIX2FrBQUCu6flh+cc60WPR9+vTFUGSwIDFyjPLQgGjnY++MMRoS6T3NS/EathTi7y
R2CYqquXR4TIyLJ7ziqz2AMNroyAzF8PUE9hObmzF0xUdMZiAnnAIn6lb90R5QC/eGQptEQs/qCJ
Zfs63s51JSmVg/ADR3E+jB4Lnv7Fsxd7+mRr3VyuASp8aGW6nROMxmtZ/SmHRoIpNP5TOEYuRTCm
hCjREBzknilmWOkMH2A1bvoEHA7GQLhQ1fBcY0MhRvcNPrJrwsMlzYAOCGUkP6/NaRf/t8wkfwHl
YHUDsXJVGmUTX5AQoTcNbUBh/MhO5nSnLTh93mzYGAQ8GD8v1x5KyKq/r5ZKXv7i9F2TcMKguSUv
CGss7zEMHJxAdgx6kKvQSwwwM99VOZDjNgqCt2KuesnE9yarhj8ZBd60M0v+9Scuo92XIxRU6QtX
aNt0GjQ0iVfmyHR8JbKjgg97AbusfS6ni8IsKaxfkpuC/tuagvACU/evu21Du0mDZ9L/JaX2e4Ml
IX+VA3Xa5bmd5Hd3xpJYsVRzeuGr99thqGy3nxcSmmWanxv5wirTuBvOIvaZ1kGJuZmgMkTU4glC
eFe2Z82q7I5HEeH5fQXJ7y1ksNsMqWPOkcfmiMBtPZp1OGMRPKcj76MIElqGtkuxWeXB1Hzl8uk3
49ObO0c/ggdHszqUhTKPDZ57HVyLG2y9/wa96OMwqmmWc+arffjUDSHlbPF2wTzj4YMEUWhLIPm/
5sNDwkD844om/S4ptW4pzcYbziCJaMYlZrSV8UJVj63eX43WTNoNDlw1rzGUtDRxZxftGaHoTnz9
4JbV4o+XQ7X2dnJps/5cCWED3uc1wa2ZpqO+D8ZyfAwh/lNHEhwJNgwDWkRoL0ke8QUu4VX+G01c
EDiXFW3jzpocsTbKWiNpkEQ/N5TihZBSFnL3kSVyWXBvVl0JqYv+0yUzjHct6yWYVTj3s8uHcC5B
TxBiMdXaj3SIMN4L75WUWl8RbIS1MOT68BeCFV47jyb9OevGA/y2l/1JLOQPx2b70FTntqfxExVv
Y9e3KuCWc5gYV0wPtruXKyblVTrb6N8nrg1y69Nyi3JHXEJsXfZearWax3mAlebgpGC7xspiIHUs
0c3S5rZf0zPHGsmE4Vh0sSss/afKep+eQwv/fI5pEWfYBv7x+tJFERGQsnmpkLf/h55ELbETr+7A
57LSy8LEyns5m6XeegaGwne6CLGUm9A95IKEEQNRVeTcO7TlA0HpiKnttyqBkTpqB+a2VZSuTR5+
sNHqf+UVVQSDEn/EDrToC3rA5NzUjn8JJuqp1/kMztO13ukT73fguQIUj11jMb8Gh8/3C8e1fxGs
IodSNyyQq+0ex7gUcyMQHgmgwQ9WTAFhketK/9DYZ9l5+EAI94xgGvY3AYF88l5AI9Wr+y6TzhHY
vbMZ3NhU71LHgl3WQMKefqLMc9wfFVWsMKYCsDV/+yUYBuLhcS3JPJjP0KEMW+wdPHPSStRipOqZ
hcT1jKRV1SM8bH/Sa6w/+3tOq/dwErKjEsRFntaM64TDNvydf1u4qHpuMXN17BEg5ZDCM53T+C8d
djZR4cgT46+dPcPsyGIC3kKTQsr6EGjVnRIrYVW38+ECnUoP6B9mwnCEtgqZOryVNIRP4rlwrOTP
Jd0+pIfxgqbnCG7UIB99iBuIOppnEKrqYj5wJlI6Shef2Uj2MK60XFkJus9Gfch7nOX3i8dZMGha
n70CM/htNZHriwrT5xxfGyci5Jr87upRRypqUMo7pARA9/53ZsTmttzAmV0Z7KBkyxcNPNLnOOAT
KZLm7XmqT7Bh41VPzQvAahNuyhjaj0kMWWWoMjzfUVwq+7Hz7o3bd2cRTFwryKE5NuMkYsDSwD/T
lVHtoRd3Lu0vN/NLktoLTHmrAF6WqD85IYO7bykQi5R1gvwuS8sNGensOJ00NrzwJWgJcKX/kxZt
ev4dFQzB6BzXppC/YAUiB6aAzVhPL9t23KCrer4loKJZyv+Qv4DF5z5JVCBVI/UoOQKjA41UZ8Q8
H7WZnOhY0iDMrZ1quP0Au5h+0JXz9BXjAxyD6IDGF+rOBo8x1ep1UfmjZDcivJ00iBkUvOAgcraa
e5xtGFq/+DTej6dq1tQI9AFFYUBL0Oh3BaZtnuJOUCq2uY29RKqCGGMq1JU3phGpsEJP38Zcn+Gg
XnEwD0SQup1vdL8SWAaOZ1NPWlyaQAbKeRwp0FtKne3NQ59HATniwotFrx31L1OEKdGUultcA3J7
l1se67mwDb1FdNbLR3LyWgWABXYgbLfjn0RPAhKFxW6TvLTudg6sY8/MZLlwfLzTRBYPftv5xX1U
xOHTwCdo6cQZvhpp481kmq8R9CaMEfMFBrZl7VidCZM8yEtsAW1deYenF5XDzYso/0IdQMeFYiRl
3yM3vkhthhEpq6agRoVs3ySN5MHKJb62TKGOV3b5135JHQcJ597+bxVpJFMkIVpy+qEUDZ2pc2iN
gAPBomntZIVFOQDuEDIGHDiXSQUKCrMGP2KyY6aTd9FM4aVINAnqQmQICEy6oIsj7/iBLXMfv5Jc
YvOIMnEdXZ1DF/gov+hE8HKuHEfi/IEFrX2j2NFHrIJOBsXQJk8uHB0STG7eVZ+9OpjQUfeDJDmc
7TuAcs6St4Vzynd+/ggNtAYf8A3IUHRSLFLwu+2DsDioRsb1gKf1hDwmiaO73uuhmTkseqs1AQvl
4ccuQnVAUGYur2Bly9TG342jNS0LZgxv0N+c3sUvnMUbzllAoCe4VcWj7203vJ3wM8r1I06uJhiJ
iYY+EjQDaDDVcIlFSgtOhvhtywfNXHyfNjRD42tPV69+B0StoBtivTIEkuD1kllcwrz9tvSlfO7u
CVuK5nV/qL1vKSvDL1L6vJ9CnKZwtWKl8hb/XBpDLtMaBVL+izdhsGBzJnLK8gtu8fHc48KyrP5Z
5+8s289bCOA210dBVEiz48sje66Prlwf1oxCD3WOr8DqMsqk/RJbHxVr/bGMUxw5n6uNMJN1U31t
+QhIfCV7pJBpjHbZQg2V092jeKsENGQPR3fE32vwTfvM1urHFmjR+iKtN1FXIxXEWIrAVCZeDj/4
DN5Ta5WvpOguJcVkyfbT6PALIeJoSS+ixBfz82o7ZvcAHnUq2clXr+wLytVToQ5XB1mFsmDk6+ni
uY/6HX1NVg9KaCaij+oQeaUVFHqKoDXjYcu5va0LgWyMnso9tFCcjcO+duqMJnKP4rlLO7r6fDy4
FyYpToEtal59IewWItYeKpicyodgZgYH8/INu6wW8dWBQ2oZAr+IfO3UwSxuovhIZonWjCtDg2gQ
IIOKkbOPiyIwo2/iluG0K5tr05R/wdCsObJz/SKiPvorUoIwVRtYjPQ/mCNCZ0xr/vUFBQ3m0arK
7Hzr7P0RObYMl1zpd7MuttYLQHrKnEwdxoXT1VLWKfsc6X57B6yG1g/wl3YMvD+DMFb0OxTGpn34
eYR7PbfW1hCNpCFYjahmQ+HyYNkPm23FrPMPY5g2BBpr6NLxJOAIb9NGOq2cBlCH0p1E6t4FOHQu
V9BQdmcaRYaMjk2s8BO6QA5W8NFMCrZBDPT0BL3UxR7RZ5JcYxyQeE+YwSeYvwjmiMYICC3GbmW5
OCVFs6oUHvXqpGqS+PomMjd6A9gDjzws9r65tv55UQa3ZFLBhUJH77YP4AwTohQfQSCiZnexYtG1
Az3IF8oHv3pYxRRmGnhVSjeNYNlEmXT+Tu5EIqslKza3d14S3rhBPF9k5GnUvDlzwsc7H/bH7+87
SNA0+sty35tFalhWo2jwKgFGegW/yQ8cVAP8eqn5yek0CI490so/Uyr5KX1D3USP7tEfI3OJsVyP
rlo5yxaq2DpA2+Iful0AnGWq9XzcexGUNFl6EpsOhiWqt4fdSjIdHlLuG0kid3HDEENjW4qO/WO8
ar5bastP0n5LwvpMG7k9KDLqedJpO0mencyrpX/vrE1BWXRKKOl/HqgxbnkqR7S8wY+0FgAdqmlR
BmFWAv8hEQj7DwvXj/6aN0FPa9todqul0igmaGz/zD9no/IhpYk/tEoEBLp/MHu3c8Bj+J3JOpqd
ztOSwSav34Q7yjh8wAKw4WMNqfARbKSXBq6nZgA7srpxb4wPLRrkWQ1YcX9GT1zmg4AfIJPuUozW
v1/lY8bo0NXjHI0i1kiqTPvRO2PhhNU5qcC25Xnww90VmLBIzSm/KaEkrEldiBtgaMClMdBpClv8
GTFg8xMk+GfL6lPQPF4i3dkSaaVTF9/Sswqx8X+5oiWh5wjtotAsIG/IDEMpN7q/rh65x+9aAneO
XjnmsxjC2X6LS77qCgFkIghk9c8QyObdM308aoBE48molDaajypVp4tQkOf0bU9Wy4xVNVul/6Ls
Lny1/myGqI9k8PG+t1twLgsbFfBFXXkDldpG1YiPQ1oxV44f1xwMrPX8qdkbPq9QHElnSpRdsF7k
GIXSzczqTSHDlhY2NpiCNgZcZMh5S+iIhEVBHRj6sUudkbpA29p8sVhglBKTFKyE0ulb4UnAivNW
SPgrjzQvYGVRrMgfFfq4/wFlO7MEBlQ6Kqs3nJ7usbWCLnxO2MrZThbjDN0hQZjmat/img2tUFD+
JgzM9+JWgp/GFs09DZUxKlv/5lLyWhSPwdBftSjmZjUad/USMj9pD7j1diZC9Mj8ABdV6cJ2ScDn
AacZC4f4ikQ74cbjF2F/+A7HPopL2IuUpivg3dgaP9rS6GEf5j8tBHeAwCCmqODFxStKdIur1bdN
7FNufbqr6c0GrNQYygGuF6+lRC1VY3wXn4kCbcviYBKDdcsNzhOx6xxIPhIMnOVKcEZVlnGFmSiv
0a2XwVyi9BzXTCYSXfhJZQa10QvhA31UqROzffr/LnaqgT8cCqf8ZKemXMTNtBj1lFzEMFIvLPih
UlIae00z1enfMvhuXE2aJjTZy3ZMXPQn46K9E9CK1iw9nP+GgQng4bmT5QTmsX/fRToQerpAGzpB
bJrCR/v9qKPjXa1s/zECJ3RuAA/Oe+BKBUVixuLEzVzHqHNveNQ9lfcm1bcRnLJX5MWt5vOBvS/j
eFit44556ZhhZgB0E88YE3upTaqrnRtg91LuHmaPumkhFyMBFUBSReebCNKv0IIcwqNKaVMlKO4u
nXBz4rxmiloAO9GyDrzNiCLAZXImQo+jwS76r/QAyDzGClBX7ttXnPjFFZ04VofQyxMgt8c13VNY
AURx0gBSIHy3kAf+QumcbZUjmthr4fwGFaHCdnlBQPhVPmHGaygyF7uBBT3LmDOagcYqBG+lSN4j
bq+D+UXZ93x8LYiKyWnnHR+rbjNxGTHlsqO7We/lYrZDPUSlzgwxY+XZu6Gx5h3sTpoFBxc1gnCc
DelspIu9+J1IOO4/CX11UTeT6F61jkEDCKMpaEHLILfG5F10dhiyKmBqPXUSKSlq7mnXvg9m2eK/
owWpjEl0KoGy34XW2aSyu8cVwYakgD0P8pxqfiEK9kzhRleVyVF+HhDUJY4T51GwmpERDzDYayA8
1sZa6VyW6mdCT9HBHcl+0OPn7DG/ook75wSmReX8JjokJGpId7/kS25aY6YKRXBCejhRXriCVBuf
x3s6rDYgmK6z9kqDqmKuibMqxUDPruZDkVBxYb3mR82HEkiQJf2RLRzylCcZQKNEwn7I
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
entity scrambler_tb is
end entity scrambler_tb;
architecture behaviour of scrambler_tb is
constant clk_period : time := 10 ns;
signal clk, reset : std_logic;
signal en, seed : std_logic;
signal d_in, d_out : std_logic;
begin
uut: entity work.scrambler
port map (
clk => clk,
reset => reset,
en => en,
seed => seed,
d_in => d_out,
d_out => d_out);
-- Clock process definitions
clk_process: process
begin
for i in 1 to 10 loop
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process begin
-- Reset period
reset <= '1';
wait for clk_period * 2;
reset <= '0';
wait for clk_period * 3.5;
wait;
end process;
end architecture behaviour;
|
library ieee;
use ieee.std_logic_1164.all;
entity scrambler_tb is
end entity scrambler_tb;
architecture behaviour of scrambler_tb is
constant clk_period : time := 10 ns;
signal clk, reset : std_logic;
signal en, seed : std_logic;
signal d_in, d_out : std_logic;
begin
uut: entity work.scrambler
port map (
clk => clk,
reset => reset,
en => en,
seed => seed,
d_in => d_out,
d_out => d_out);
-- Clock process definitions
clk_process: process
begin
for i in 1 to 10 loop
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process begin
-- Reset period
reset <= '1';
wait for clk_period * 2;
reset <= '0';
wait for clk_period * 3.5;
wait;
end process;
end architecture behaviour;
|
library ieee;
use ieee.std_logic_1164.all;
entity scrambler_tb is
end entity scrambler_tb;
architecture behaviour of scrambler_tb is
constant clk_period : time := 10 ns;
signal clk, reset : std_logic;
signal en, seed : std_logic;
signal d_in, d_out : std_logic;
begin
uut: entity work.scrambler
port map (
clk => clk,
reset => reset,
en => en,
seed => seed,
d_in => d_out,
d_out => d_out);
-- Clock process definitions
clk_process: process
begin
for i in 1 to 10 loop
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process begin
-- Reset period
reset <= '1';
wait for clk_period * 2;
reset <= '0';
wait for clk_period * 3.5;
wait;
end process;
end architecture behaviour;
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'value("1") = 1 report "TEST FAILED value 1" severity FAILURE;
report "TEST PASSED value 1" severity NOTE;
assert small'value("2") = 2 report "TEST FAILED value 2" severity FAILURE;
report "TEST PASSED value 2" severity NOTE;
assert small'value("3") = 3 report "TEST FAILED value 3" severity FAILURE;
report "TEST PASSED value 3" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'value("1") = 1 report "TEST FAILED value 1" severity FAILURE;
report "TEST PASSED value 1" severity NOTE;
assert small'value("2") = 2 report "TEST FAILED value 2" severity FAILURE;
report "TEST PASSED value 2" severity NOTE;
assert small'value("3") = 3 report "TEST FAILED value 3" severity FAILURE;
report "TEST PASSED value 3" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'value("1") = 1 report "TEST FAILED value 1" severity FAILURE;
report "TEST PASSED value 1" severity NOTE;
assert small'value("2") = 2 report "TEST FAILED value 2" severity FAILURE;
report "TEST PASSED value 2" severity NOTE;
assert small'value("3") = 3 report "TEST FAILED value 3" severity FAILURE;
report "TEST PASSED value 3" severity NOTE;
wait;
end process p;
end only;
|
architecture RTL of ENT is
begin
end RTL;
architecture rtl of ENT is
begin
end rtl;
architecture Rtl of ENT is
begin
end Rtl;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
package QueueP is
generic (
type QUEUE_TYPE;
function to_string(d : in QUEUE_TYPE) return string
);
-- simple queue interface
type t_simple_queue is protected
procedure push (data : in QUEUE_TYPE);
procedure pop (data : out QUEUE_TYPE);
impure function is_empty return boolean;
impure function is_full return boolean;
end protected t_simple_queue;
end package QueueP;
package body QueueP is
-- simple queue implementation
-- inspired by noasic article http://noasic.com/blog/a-simple-fifo-using-vhdl-protected-types/
type t_simple_queue is protected body
constant C_QUEUE_DEPTH : natural := 64;
type t_queue_array is array (0 to C_QUEUE_DEPTH-1) of QUEUE_TYPE;
variable v_queue : t_queue_array;
variable v_count : natural range 0 to t_queue_array'length := 0;
variable v_head : natural range 0 to t_queue_array'high := 0;
variable v_tail : natural range 0 to t_queue_array'high := 0;
-- write one entry into queue
procedure push (data : in QUEUE_TYPE) is
begin
assert not(is_full)
report "push into full queue -> discarded"
severity failure;
v_queue(v_head) := data;
v_head := (v_head + 1) mod t_queue_array'length;
v_count := v_count + 1;
end procedure push;
-- read one entry from queue
procedure pop (data : out QUEUE_TYPE) is
begin
assert not(is_empty)
report "pop from empty queue -> discarded"
severity failure;
data := v_queue(v_tail);
v_tail := (v_tail + 1) mod t_queue_array'length;
v_count := v_count - 1;
end procedure pop;
-- returns true if queue is empty, false otherwise
impure function is_empty return boolean is
begin
return v_count = 0;
end function is_empty;
-- returns true if queue is full, false otherwise
impure function is_full return boolean is
begin
return v_count = t_queue_array'length;
end function is_full;
end protected body t_simple_queue;
end package body QueueP;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:57 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_xbar_0_stub.vhdl
-- Design : zynq_design_1_xbar_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awid[23:0],m_axi_awaddr[63:0],m_axi_awlen[15:0],m_axi_awsize[5:0],m_axi_awburst[3:0],m_axi_awlock[1:0],m_axi_awcache[7:0],m_axi_awprot[5:0],m_axi_awregion[7:0],m_axi_awqos[7:0],m_axi_awvalid[1:0],m_axi_awready[1:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast[1:0],m_axi_wvalid[1:0],m_axi_wready[1:0],m_axi_bid[23:0],m_axi_bresp[3:0],m_axi_bvalid[1:0],m_axi_bready[1:0],m_axi_arid[23:0],m_axi_araddr[63:0],m_axi_arlen[15:0],m_axi_arsize[5:0],m_axi_arburst[3:0],m_axi_arlock[1:0],m_axi_arcache[7:0],m_axi_arprot[5:0],m_axi_arregion[7:0],m_axi_arqos[7:0],m_axi_arvalid[1:0],m_axi_arready[1:0],m_axi_rid[23:0],m_axi_rdata[63:0],m_axi_rresp[3:0],m_axi_rlast[1:0],m_axi_rvalid[1:0],m_axi_rready[1:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2";
begin
end;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: dsp_round - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dsp_round is
generic (
BITWIDTH_IN : integer := 32;
BITWIDTH_OUT : integer := 32
);
port (
sclr : in std_logic;
nd : in std_logic;
AB_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
CARRYIN_IN : in std_logic;
CLK_IN : in std_logic;
C_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
P_OUT : out std_logic_vector (BITWIDTH_OUT-1 downto 0);
rdy : out std_logic
);
end dsp_round;
architecture BEHAVIORAL of dsp_round is
constant LAT : integer := 2;
signal GND_ALUMODE : std_logic;
signal GND_BUS_3 : std_logic_vector (2 downto 0);
signal GND_BUS_18 : std_logic_vector (17 downto 0);
signal GND_BUS_30 : std_logic_vector (29 downto 0);
signal GND_BUS_48 : std_logic_vector (47 downto 0);
signal GND_OPMODE : std_logic;
signal VCC_OPMODE : std_logic;
signal ab_in_ext : std_logic_vector(47 downto 0);
signal c_in_ext : std_logic_vector(47 downto 0);
signal p_out_ext : std_logic_vector(47 downto 0);
signal delay_line : std_logic_vector(0 to LAT-1);
begin
GND_ALUMODE <= '0';
GND_BUS_3(2 downto 0) <= "000";
GND_BUS_18(17 downto 0) <= "000000000000000000";
GND_BUS_30(29 downto 0) <= "000000000000000000000000000000";
GND_BUS_48(47 downto 0) <=
"000000000000000000000000000000000000000000000000";
GND_OPMODE <= '0';
VCC_OPMODE <= '1';
ab_in_ext(47 downto BITWIDTH_IN) <= (others => AB_IN(BITWIDTH_IN-1));
ab_in_ext(BITWIDTH_IN-1 downto 0) <= AB_IN;
c_in_ext(47 downto BITWIDTH_IN) <= (others => C_IN(BITWIDTH_IN-1));
c_in_ext(BITWIDTH_IN-1 downto 0) <= C_IN;
DSP48E_INST : DSP48E
generic map( ACASCREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATTERN_DETECT => FALSE,
AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 1,
CARRYINSELREG => 0,
CREG => 1,
MASK => x"3FFFFFFFFFFF",
MREG => 1,
MULTCARRYINREG => 1,
OPMODEREG => 0,
PATTERN => x"000000000000",
PREG => 1,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
SEL_ROUNDING_MASK => "SEL_MASK",
USE_MULT => "NONE",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48")
port map (A(29 downto 0)=>ab_in_ext(47 downto 18),
ACIN(29 downto 0)=>GND_BUS_30(29 downto 0),
ALUMODE(3)=>GND_ALUMODE,
ALUMODE(2)=>GND_ALUMODE,
ALUMODE(1)=>GND_ALUMODE,
ALUMODE(0)=>GND_ALUMODE,
B(17 downto 0)=>ab_in_ext(17 downto 0),
BCIN(17 downto 0)=>GND_BUS_18(17 downto 0),
C(47 downto 0)=>c_in_ext(47 downto 0),
CARRYCASCIN=>GND_ALUMODE,
CARRYIN=>CARRYIN_IN,
CARRYINSEL(2 downto 0)=>GND_BUS_3(2 downto 0),
CEALUMODE=>VCC_OPMODE,
CEA1=>VCC_OPMODE,
CEA2=>VCC_OPMODE,
CEB1=>VCC_OPMODE,
CEB2=>VCC_OPMODE,
CEC=>VCC_OPMODE,
CECARRYIN=>VCC_OPMODE,
CECTRL=>VCC_OPMODE,
CEM=>VCC_OPMODE,
CEMULTCARRYIN=>VCC_OPMODE,
CEP=>VCC_OPMODE,
CLK=>CLK_IN,
MULTSIGNIN=>GND_ALUMODE,
OPMODE(6)=>GND_OPMODE,
OPMODE(5)=>VCC_OPMODE,
OPMODE(4)=>VCC_OPMODE,
OPMODE(3)=>GND_OPMODE,
OPMODE(2)=>GND_OPMODE,
OPMODE(1)=>VCC_OPMODE,
OPMODE(0)=>VCC_OPMODE,
PCIN(47 downto 0)=>GND_BUS_48(47 downto 0),
RSTA=>GND_ALUMODE,
RSTALLCARRYIN=>GND_ALUMODE,
RSTALUMODE=>GND_ALUMODE,
RSTB=>GND_ALUMODE,
RSTC=>GND_ALUMODE,
RSTCTRL=>GND_ALUMODE,
RSTM=>GND_ALUMODE,
RSTP=>GND_ALUMODE,
ACOUT=>open,
BCOUT=>open,
CARRYCASCOUT=>open,
CARRYOUT=>open,
MULTSIGNOUT=>open,
OVERFLOW=>open,
P(47 downto 0)=>p_out_ext(47 downto 0),
PATTERNBDETECT=>open,
PATTERNDETECT=>open,
PCOUT=>open,
UNDERFLOW=>open);
P_OUT <= p_out_ext(BITWIDTH_IN-1 downto BITWIDTH_IN-BITWIDTH_OUT);
delay_line_proc : process(CLK_IN)
begin
if rising_edge(CLK_IN) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= nd;
delay_line(1 to LAT-1) <= delay_line(0 to LAT-2);
end if;
end if;
end process delay_line_proc;
rdy <= delay_line(LAT-1);
end BEHAVIORAL;
|
----------------------------------------------------------------------------------
--THE FOLLOWING IS THE CODE FOR 16X 1 MEM , WHICH CAN BE USED AS OUTRAM, WHICH CAN BE
--WRITTEN AND READ ACCORDING TO THE CONDITION IN WriteEnable PIN
--
------------------------------------------------------------------------------------
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.all;
--library UNISIM;
--use UNISIM.VComponents.all;
--
--
--entity OUTPUT_ MEM is
-- port (CLK : in std_logic;
-- WE : in std_logic;
-- EN : in std_logic;
-- OUTADDR : in std_logic_vector(3 downto 0);
-- OUTPUT_DI : in std_logic;
-- OUTPUT_DO : out std_logic);
--end OUTPUT_ MEM;
--
--architecture syn of OUTPUT_ MEM is
-- type OUTRAM_type is array (15 downto 0) of std_logic;
-- signal OUTRAM: OUTRAM_type;
--begin
--
-- process (CLK)
-- begin
-- if CLK'event and CLK = '1' then
-- if EN = '1' then
-- if WE = '1' then
-- OUTRAM(conv_integer(OUTADDR)) <= OUTPUT_DI;
-- end if;
-- OUTPUT_DO <= OUTRAM(conv_integer(OUTADDR)) ;
-- end if;
-- end if;
-- end process;
--
--end syn;
-------------------------------------------------------------
-------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------
entity OUTPUT_MEM is
port (CLK : in std_logic;
--CLR : in std_logic;
--WE : in std_logic;
--EN : in std_logic;
--OUTPUT_DI : in std_logic_vector(1 downto 0);
OUTPUT_DO : out std_logic);
end OUTPUT_MEM;
----------------------------------------------------
architecture outp_memarch of OUTPUT_MEM is
type OUTRAM_type is array (0 TO 15) of std_logic;
signal OUTADDR: std_logic_vector (3 downto 0);
signal OUTRAM: OUTRAM_type:= ('1',
'0',
'1',
'1',
'0',
'1',
'1',
'1',
'1',
'1',
'1',
'0',
'0',
'1',
'0',
'0');
----------------------------------------------------
component MOD16DOWN is
port(CLK:in std_logic;
--CLR :in std_logic;
Q_DOWN : out std_logic_vector(3 downto 0));
end component;
----------------------------------------------------
begin
counter1: MOD16DOWN port map (CLK,OUTADDR);----GIVE CLR IN SENSITIVITY LIST IF IT IS USED IN THE CIRCUIT
process (CLK)
begin
if CLK'event and CLK = '1' then
--if EN = '1' then
--- if WE = '1' then
-- OUTRAM(conv_integer(OUTADDR)) <= OUTPUT_DI;----(uncomment if used as OUTRAM)
--end if;
OUTPUT_DO <= OUTRAM(conv_integer(OUTADDR-1)) ;
--- end if;
end if;
end process;
end outp_memarch;
----------------------------------------------------
----------------------------------------------------
----------------------------------------------------
|
-------------------------------------------------------------------------------
-- ilmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_00_b;
use lmb_bram_if_cntlr_v3_00_b.all;
entity ilmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of ilmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v3_00_b";
end ilmb_cntlr_wrapper;
architecture STRUCTURE of ilmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
ilmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00007fff",
C_FAMILY => "spartan6",
C_MASK => X"80000000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PFRvViteb/axbSedtxZdW6uFxEgxk5HDXr52ZztCJxWCKdDmlOAHnc3JEW8CIFtzmjKOAOcvAPod
vtt04j05Vg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
YifkGv+JrzBIs/UUQvyB0aR8cJDay2lbjuAiS5PNdfcYrIMzhVbOG63ypMDOSCXjoNDh2LVGbHl3
ta/Q4WaIkhoGICqznMByToK8Qga8ZejWW77ntM2mnBUthJuws+YtgkUtEsIeNEMQMJ90DRm209bw
ea6opZ8Y3fuPQ0Trs1s=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
aguPFZ5LICOCYhEOysUisuw62lqz444/ZwFbsY3EB6+W4EImuoyayyhHbBUWgH73pGXi1zH6cewr
UMEBWh2iyImQzFkNLq15CWJ5QKrOG+vqQ9+7s7OhYai/OXygzdGNqfBbWflfKnFsYABsglk0q1cg
nvZF2n1Fv5jbuOGonGuTwaSeD93Up1SYYyNP+gr2L/zBScWpe07CQaHmBcnw1l7Yb4/3pUKs6jyP
o3n9MnVjJLqZcqpe0oM625sHf8uLhZ3ts8a2KuEmIf/n9YHvxmQOlHsUh3M0ASAhsY/IUhioTaVt
3psEsqATN8vqn09+5Ka5PbPz4pgSFzUYxoGmsw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
crqbnapJrzsKzLNb+AtGmQFmHNUJXrsIeevTjReFKq5qDhvhFDl7Hn29zbiGy/FzXhop55wp2Vpe
hc9T5+Xp8tfpDfH+MaIUngm3kTXG7Tyn0ROLEqkxxG6ZnPFxQxd6OTmcje1mTSc8iXYMXq4Xlu4Q
T+dmUhClJm120LFfIow=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
l0V0VHPXtBRxv+IxB2NS5WXP/pkBGK5eRz5mHgBmFAd50lxLN3/8MLKb7uOd3jzpJrWuPsMCEyNN
cGgnfvx+5gYyOFoj05pI/N4xPg9R3cN+yoYh6BXn/02NA8fwnXxVkOb9BWSfJRTudHD9rHY7NEMD
PWLboIFjDW9sRg3xS+CJhpeomY0T5D0r5wTSzPbYgAg/oCQCVvZ1F0B0BdOstQFjgJzlXN+y0jAp
nA5Ym2Tm/kDS1e/vGtXGMdT4wohimviPpQMWQivqVKADDS5qfrGiTWDi8oTqcngYxT/gi9MXpa2X
/WmdHyWT0iwKbTL+j7n1ZfYJZkNhd5gRrloxYA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 31072)
`protect data_block
hvgeB4DrwL0gZn2gxtaMqkp1oMtHkDpeGQVeFLRN315HgnUQeLxIUKoggK5HoRUANRdYjoNNhh4g
ohzRlV0hahMKDeYCg8azoApOp4p5ddzpGtdmSeMWycHUekdciWQR6+m0xo5EdT6RDXFkLoyXzGQi
BaQk/q0Baa5jJT4HktWQ36buMb/mtajxTm54IFd+tfx6oE+Fi8Iv1hDWiDxTdLGhqmawuCYvlE6o
Lo8XVkD/DCcitjhIriYvkWlahnMCatrn/urMuz4XmYboyJKlvn/onpnOmhsVF13y47x76JLbY/xq
ZfU4JX9KOaWLub/w5MQR01W5vEZRt9syglrSkhwjG8MB7ZZmxoTUcfMu/ncg++Q7HcmAmFUxAw8a
f0VrIXAh5RU+47zUZzrDWn3WkqozTwvn5MTBnkxx0w4R09LOXpH08usKO4c4syW4srB8epZDsAlY
NFXm9dPP75L5wwjEZjgOELMBDl5cgtIYuT4CpMNOx15RvStdOw0vRy7vBySxEH5Y6XkfpNZ9R6w1
9R7SP8VH6aAKZRagpKvxzpxCkqKi/tb5AEydcu7FaGa/xPLS5iq+6/h5YrGmRzbQRv+zxGu0KBks
vezy6Q6dtyOFcccZVdCSXILO0Eu/f/f6e5IoyJL/OxMf2Wl6JqwaMhGLvU89E1+nP++uXXHFX5ho
23kJfOdg85r013ZlKIlg5Gl5ufI6Dq8xSp9XSnRVOy06zgcnpPw1TKO4Jt9CHMWuCkDwYnWYLANO
LaWTDB8Aq8EQSt6Wf8rbrmsKBszFGUCk5jVOoqqspAQlF6x87O/yEdM4EgPKzGpltqocI2JwNU2/
XzkdU8gxMdXDLpwmB9GpHHzKDf6wIDPEFbuej81wDd4VEx6I2Q7MURnDlPutLBzHmPLcauyVY++p
ayXhAdzx1LxbbsdTu/Ty3gLcxo6ZAZe6RnAC4K/dENeTvE7LErJhSigafh9rUo/zIAjQbAZhM+KB
KxsaffDquh94U2RFWT17GrdrHc8LSDDFPZJKIYlceKgBqnr3+8x0MlCzLDJRPDYZDRFOGNGrAxTA
/jwvU3lRp31qLbrEgI1C6RJKUklx8802BEu31mHoxAjt5vvjEYGW/SDjkj65MEbz33FQbnMULE47
ghFf9i1WNhF0UFNpkDncRBUnCnA+J1t4i2U5xzkeICAjMLdvQ01QCBX75K6jAqrdV9Jpdr6vxlhU
jZlp0kU0hYiRRmG17AXtXTQx6ImuUf/NxAXw04KY3kWlCpzrI7H5GPlDCwANrV/TmNlGeWxcFgoL
j/H24AoqIOy8ICpluwRl6Z/mDyqQkfhnfuVEDPzRqnyJLXoTlvOkJDvhcH8gkXzxZnXvZkfbXllT
bjFB7FYi9nRyxaaV+alS/clhYdHkx+RGVWicjDb0R3vWci+wO5bteB7rPhVQ8zOSiykqhRWbHXPl
5yk0jN19Ci+acHTAqbaK8LCssqmJazIHE13CW0YMUjFtw9ubKVJyggbgTvAJlmQLEHWt4z4CA01Z
908winrsyQQ20oKj/tI69RomlTdFUYAmtFwRIcyWNX3qM7KCtR6mHNPUi1ktPO6WTJji3fFRMB5o
iBQHZt+SYsxFCfXqVHnsZH9bhZCCvJuT6uARcDdXP7aTxqc23rBc0Y08QNxls+T3hJQiabClUxd5
Lv8lYETpaypgAR7RwpMseVugztBlUEJDnXN+zSyFbc57UtOUfM6vRS39aWSjmTNxbcxR9E45gsPF
IRrTMvnPzMIiRWX7iOdrv06mEnYU+E6KnH5IUV5veUIjC+lCq0vQKqAifGgzuqVWSr93tyh4uOuR
rUp3U5c2ZgENEMmYpth79NCY6XCTlyN5B8O1rXRMcens2f1JnPab8XJS9NQ1kYlg/1FdY4iIs2Ej
usiAEmcfdx8TFvKwt39uWag/eZ2sAabWNbQ25P1DraeStUS4CIwNI4BiYZPZwLh8L1AqL4fLW98s
nKlVTNM//U/vxFlX9Ig0DrMtxJzkG9d3a82xAFjCh0Gyg78IkAZSclRJx+E98D5jTfb/lqFepwuc
5yS2deyIXlvYhG/tiNDTvuFv4RJBvtycKZ7OXIOtUnztf05AJNo1Okb48LR9QyGPTIA4cZcs9yYE
5xdMyy7v+ErHHIoAOND5RO9RLmqUSSyYv5GS3zL8gT6GZKM9d2tXSH1SBNYGyhzmQZ3KrO4kWY4J
O2XjM9MFt1PpiWifut6dXRlMgCtX31fSZwW8S566wnFank7QoH2OpEq38Rkud4ItIY8NCEbpT4sN
KWjSIVMMp7HxuzkJ6IIA/3BcdmPTDIGbU0OAgA2Jfw0Hea093jyPSWRbMLPzX7rCAHPLiyjo7M8p
DG91n5q/mqkJjIOSYgokNRAiEd8YaFm5G9dHeUpBsLvrT2V9x7gDZ8dVce2xuDX73mnspvyuwIcw
8WP8mrqOmZ6jcQ7wB8lfWnEbgWxH8sk/6AsKrEOHykuDUsSdGBrik4BuIvPUSx0r3RyB8y6+Lnct
c5F9NR/OMeYmyUKog/asEhhfZk0uAN3OX+lNtMeQQ+Zxz6ARYSPJV2dvTLl08SvO3f+vSJaBId+7
VUB75Ed8pi6oFXt972rBJCbeY01cDgRgkYyxy6AJvVAVRF5G/iiAe2/aPcEUkH9sNkNW+3N7Aabx
YKPkngWwAlKqsWIhqqAil7nWln9fXBHppubyumwZcgW9Uwp4WFzAMV/4BCWtBWHNLxdKco27FqEB
MprukEoTY9nK71of0zj4Z4HeljIq81myefeTPMGl2Kvqpk0cg1UbO1F+hdc6kbapE/lHm+J1smdU
iKo1DtDL4RfzJdiclhYEonJ5H6b2dLevEJ7vAzj7QHW2Y2h2s4HFiokHewUlZXqLNM/Up7rTK9MF
tjKRkpZMKCYPLqD1jVLq4zxS3EZVvEMK5eMRqpQL3XjJqJf1QFQ06MRFlAqtItGkdzztVsEOF62H
OUl13hrq66hfJtS3oP32dFMjEwuGpNAYl37TN144DujOIXeKJhfngbFYk4sOpsCFuJR1WYuywGhY
jhwh7wIVY6gFxcpicKg5DQ7NBpKVI21KBeQcpoYLM37yARx31+ywgamlSPNGZRZ8kdQdgrR1yH/8
+u+gTFo7Nk4/To3Jp9CNyQXDa22+PLbrkbHx/L/+IerJmp4S95NS0mxVJrkNyyNwzx1l+ZXW4kcZ
evGfvM5YUkqIAjn0SZ0Xn8ITEpTca56hHcWJRoqLMpCM9++o2VoIRDRCl/B2Yev22Tl49JE7R9PV
pFgVumOSotWgSJlomHWP9yAmYMYgtnepTwKH7WKWcOxNpCHA0R6Mb9nZsi9/mHRzTlSoSqmD1CWi
7WfRG0t54G/uSsl+uwZVLQvxhQKAKACyNTw0dQlIQckHBX6wNCuMnOKIrlcoIKnJCPB0XnTs6cpl
QN1eCZLRswB+DTpNuuTMEkLkDfe8I8QtT8fUZuzQQhW4dHdHVy/JN4OGp5x/OwwYX71ZeF5+GCEa
MYxXCeGfmh680xUNlBcloSWsZK5scPGv8IRtPxcxEJESNUlVa/iuN75F5Yyv7pFpf21xGWzuuio2
SPboEUdehQKqFkacD63ctdjvdhF6moSJmFf1njSaae1lbLlcMuStAcVnQVdSr5f/ipKhfbUd7jQz
RHanGAmra7Cv1ZJ2Q3F3SKPIQbll9ID+CDRPKD9ImyT0QHskrQ9Ac44p/jPDbO6EU2uw3gMS09rL
lhkkZFhWQfl59ZwH5b+KwIB/L08QbUaE4Aa5AumWiIffotpp/4n+Ysu29wZ+NXWwV1jMb6SjuFl3
YRKzTmwTimHNU2/n8ZF7HJlfVg3qP8CfU4TggTJaoyBh7pnGXxd7rwUCCh8k5b8n+fXUR/mZ9tq8
G9OM00xWTwYaFs1/ex+L4I1HqsWbWHJML3j7Xc5D33EjY5hB/QrkeOzCmtELBO9ajrAtzUrBEeSV
uRAaJrtvY5ntGG9KRDyFXTQ1CSBTJcsY3LE9PzZ2zF3uP+II2HugpR5ljNjJH5hkLkxLcyDX1h8Y
ZU55R/ofiaC4qwarq0EsURYQviUM1uo2WD7uCTNW1h4kSI64nARZQ6o62FtDldPHs9ZrqI1XRiQ8
BG50CHX3TpqDMYKz43RVZpLhCxMFlyCq9s3ssN1itiQaS1bra5O55RCDpnFMlV7y7hR7yW3vL/4e
UwSFPUgDV/nTfmFp/avN+1uzXaxbppu3xrDnE+WIk866L5H1A+p/wlh7nfjHA+MZI1SHHu+6T88F
PHakA2brEcRmWU+FnXMAbk1QEq5nJ4fshte8RjM69aI5qr7sMwvh8rFC/virSpzzCvrPxurMtFr9
rSXdyAOZiW5TGvu47LLDVJ6WOyDp3gWNvRSKO1YgHSP7JwBSA2Rhhi1i5LfJgNcpf0AOwgO9oOTC
Y4X7COR1dZOuKbw6QYv8CgeydkwWqc1+nadFSWK55/NWKWweadb4uA46Et/LsdCl/yGphn92BOXe
+gUNh9ZncRKbPWfBPN1W2spnXf4gmbTSHiSqTxcalZjBip/jHgYLL7+jwyTkPYPp6Uk8rXDVSulC
clo3g0UqV4g5KL0zSMXW+Ovp02D+PnjTL15rRF5np5jM+f500ZewwX9klFcGj6ar/K9Flww35ma2
yReDpUas+xF/wNGT/iPC34vDihn8J5uNXRcBeKLA9Zf4OZHA7RJ8kZ1jk072mnErbsNy//9Zq1yH
DjnJruJHh85Ugx5UvbP5vmyNEONU9Epz4MkpOWnnICBK5Ogl3P+emFSPoJM2V10IvEWNVvH4m8L/
iX1P++n8GnXNJgMvuZf2Owlj2LA/pMscCcWY9+WKMwk26Tz0CPgFbFBXoMNKlMTuLH1SraOq6CoO
LEG/n4iWDE/PDaIkf1pVxeVyfgzQBa8bud/XOOosHdrFQtqFwgHSn6bZvArmdUi/4jNGPwjDn+yk
2f+VYYHG7sGZff3XNNBpg5z33wc62UMvzaV56xvaaKyycVT7L0jsHWHMsa4/5uDal2h0e/GMQoea
BjfnlC0hPk6dg4ryKTUcv8LrmDGZO0jUfmQVHhaj/NsX5RLVe5HaV76bRZpXNFmjCQRY3hJEo5dD
/YijTYNEoM79g9iFH43JEiAbtizi86MYLGcYpEMRGuu8ih6xCrSqOPs5YHPLNr7sLWSwTTeYwLNB
37MPEEAvjNyYniDJnPA2md1K7Ru63Ut2ayu1u6Pj7xpPdlF06C8wnvddZDtO8tCaZzMqxFwz1bg5
u4PamuP2U3XRTm7qoG5BfB52Z09sueAesmq3+qzYCEbpqgLTRHVakJxpxLruCfXnRWxlGP64CJAQ
yzrQ6fDrPo1fAIvwoPbCiguXpL1Mj1+H2y8RVgzir/hOH9bkTTuqV7LuvHiy7wW96z0B949jPrMV
TwuREGEHCC7vb+pR96pGopEVgxzs8o2clLpU3SPCpVI+C4mLxEz0ICMxkdXQmdujHmsA7NX41y9O
4aUR9W3uIMONXV1sIMuQ1MJtRMIlhlLUhaeTfFkMDNc0KHusPa2VNqGGtg3RVBFDXu1c+QxMDP+U
+QcF4uIA9zGYbxpohL3QGOXzkUylAuXvnXyL+mzoyxyBwi2blb47bfGc7Dr7Lu8q0fffVAoi1Bi+
mm1jHM+8l+n1V1eXQ/5TjwifBfGYU+ybF/GaZBIXMp8GwNA0yh5N4ipBfu+z0rr0dGt/L+bw99N/
is7+ehZBsntU4upJ6tp2/tiWrC1xCd+1LaluexLz44D86FFjWreA6iYQkyL0OrcwOUH5hJGQqdGy
L56dpygE0J4E3VoB0M4Vo1xSqi7Po9aF7Cqf5Olakbbkt3gbhMcWsXY814s+C53d7UBd7oPTa+tO
suAXotCMjjKqjxdKs5B4atV4puaaxW+Xt320BzLL3bLnS/yA0cRBYGjowjyJmULzeZrzU51zoEik
VNjSlPjg2U19stiIKDUAE/oT2NlGd+T85drPgbUqX4EmDTZi1DpdsY0RorSaB3rBvRE3vGLtPPy7
95Ry4KMTCWx2UMVpMyRHM6qP3RWXCAV/LuxBwSn3nnmMwy2H9/GWuhDY8b89NYcoXqvcKERgtPdR
gkQZW9lXovryQdx7Bs7TGqWUMLaxZ8vAOoiAnTwQrBX2/al08VOhoUUvPjL2gmvkJr9pBFseEsJf
r8enJBRU2356PZwU8Xa6RN6YM40H2VTx9Ni5fV9k0VTL+/8t7mbxHtTCcipaDeDykDrladnh0NWs
4s4gjOlmYeV2BmcTFcEhCjGaijs9BLTQK6hR1a/Sui1pmxpiBAEQinZTs0hSNspkEqK8E4pn2TPQ
4GFT0iMp2RmF4y8FHPT+bnDR2F2JhR1l4UccpeNn3T0VJ8cJy5//W8BttQYzZYvcUg//gQRgsaMr
j84g9quDMEANRdkH1IKKIDOlOgosmdwOwjSnlXPTGuX9hg2hIkiZnTcdxzdPs75NVCUjDdeZo4uG
kfQTm1Lz/W7zXnTuI4NGs1eJef3n9ZwMt0zCLtn8dfAMVvFROcAKtSajpIOgeujehcmrgoh8xiPP
kirTpSdZyGGwSjZNFgfiC3h3O1/XPQ7QLd/t0zC3N1dgkZvTteui1szupYTjICtT/WEZnVaMqtmg
y8ztRKImh5UJodAg1NK9j5XEKcGgLXTkYmi68bOjjZZWNodVzXaT/eNO/iiSb48tTdvvrUfyVMlc
n2B5VcfxIRLuz9J5fHJR6qBJM9ePOAQt0602wQKzBTEdMzicQpzvdiiOw1vSJK+bPVWlH6F8x8FP
55ZFKdQPSVnS4Bw7lCva26T0D4tgfsYcDgAipGS4AZGOqHheEpcRn76o8ywpzowwsZ0GPrfUQino
q0LZ6PoyOUR885VaSnAwpes0w61x/gP2EHDX1o27ax9Valb6SWi6DPTjC+rRVBpjV7nyQqSww1ey
e6wp/advj95jjwOmkk7AzStGVmh+Toz2+Z8cU/giTMmeWTasP+245kS9Ux27ZqbCgH6L/PyFXQa+
SJnKB/x/NPTFToEc1DQkSmWIxUUxX4z1SS7wGAIRcVofZVE0cHwdASQg/r5TAFRzoZuaKpPqsX33
L2kZLVa4tItcK7NwW7ht0K3tVuVh4rICCHu86m3Sl2V0KSqOTAAMMLDDcJ8S8EyXLyXVIPe918ES
OCvwqWUEfW/l3LEAqGO6g5iZog8z8wjIRU0L6mYfO6dwQxtFpxfnmXeekcb+5FzhHpbdKjNcJkZM
qbxxr1qiWln2QbJHx6xz8ZsGwt8dcKIqq68MN388lv4Nm5j4oI/H51e7LnOe8bMlishvwbMajGAo
idS+/G7W2erekAW248mRJDNlWiFyNdGWVaHjZr30xFRY3oblXy2Fmdh5ae46XiPqYp8HjCoYkMVe
P+CSJ1ARju93ABJJeHNLfomyMG4mWc01Y4nkde0DKe7SD5TES6YqWZkKVINUN1qRkxRnsm49r4gu
OUtU04xMEgvrS+sgEBwJxblENsvSH2BPJ9jsuJ61Io6ekltHqQVOvLC+reBWhYRpo+cl8r/A87tj
9iXr4hz5dsxfYrDNEj3aOOtP//LsJS9qQdJZOzJ4OrbenpLYYMWt+RNLSHnfC+LZ7JbyEULrngSW
U81BeC1P0Lsth+MNLSctW4afkT5RE3Qh/GckfErAnTwENCdejynfKceC62BuBQ1WzXQgZHaUsPkU
f4ynNqCCcRziaA+Jg5LKZbt4lJGY3QrjioJiJRPE0T73m/J1atVcYxgNncB9hXd/FK3TXlTgzR1K
bMtQGHQcxnpCU0siwxVud2XyIyj0qRAxqeKcmuwvxaqMaCSnScnSn/Zwo4Yo3IwkawFhXOwyHVT8
6dxr/c9sZOEaBYrEHeLxpHkI3/y+TXsxoHKUM3BGAykYYi4/ln53jmeH6axuyAQ2NBY5h1pHTLov
mFTfbC8J8XODzqPUuXVs55LEqYrEZdwuk3oUMtDrXEwHHdKkONm3tuTxOjOXWDTeb1x6oYb3LQmi
5j2a0d0OHItefgvuzmEA9dYfSbu/qr8ul2Ep7KRZIlaKmKwJeAVhGPqLGfFOX1/2L5WWUERgm6Rs
Vli9Xi4hS7N9908rZcce4P9bOleZJylJ3NKdfcXDR9RrvwXziDZo7AhuGKCgAVrYpqq0lXRjiYDK
xjObUnbyx3XJ3HrIx1RkwM0Hro0JrentkuaWfJYLt/Xggv/7e6DyfyqNHw/AiDiGkHj73QCww/gH
lcwjwWYm0bqSG6pcm18l/7o6UBr9BGooqjGhxllVn0k/VY75qnFRsA8s1f0w3beBd6LLgFQiZcVJ
R6gNW026nHX882HU0tP/M7OrWmmRkBPSNdUvMoE8PdKbMat38Kna02vjNTUFyYJZq5RYyeWfsnCK
EqvjXge83wYnKfow5y06KPayOx3/b1wMSAx9YO2Y07bTWyG/I3WxmOfFIvAyBi2FOna+PoT3q3FG
a1gdNkVNYh6K44mVVyPlF4LqvrfjUo+al+6U+DvqHIjTBX/QX058dwTLUBkYi3SxR1vC0rdhL/Fo
foR+HGhsjsG92HbIkmCYDHQYqIsWFOv8QCVEoEWClBB2OHOpcC5RNDje7+ruZG3vIYracEUO8Mec
TvSmhS3e9gvjZPPP6poyUs9Px71vFUeF4KaJz6w/LOEUAkr4zFWP1kTj8NtaqqXQd71LanIUPEAb
zs7ulxseEU5dWebpAiymNsvhNKRp+C3ZvC3n109bHDNKi7WjVMqOAZ28XVOf0eS1w1GCIP9Ux+VA
jXCjqIi/lJBLOj1N+N5F6PtqyRIVxhY54vGlxUxe1Du3FsUaCQRfAXok4ltBW+siQUcQvY2E6ZZG
PeqPdQ/5ZzvosWjXdIbe6RVs2pY4gQZRFdIwYxPBBSHa9WRKXugRTuVq2+eDfWiLTzXrXyoDT5Ed
vGNLPPtx6DhBpDMPWPXpTqgoasyiTBbwWSo0bAWOPW2uFQ/TStxVgDqdEbGUMqoICIc9DvQzhnTY
pg3uuyD5Fvc76L5Z5INXbAL68yUcddv9Y6VF2pjsOR8JNF0hg6y76t9AvbVXoS4SVc7yTy6bkL1b
8bOv2N5Q9aWyxtsJUW/+izMs28niWzAUX5r/Oqj41SRQr5DCZUiAjbaSxUImzF0ZYMCbTYyyfmAZ
YSXHZ4FWCH4L/1EpZJ11ZavM7/mtuZCdEbwKLLeSTONUOUlgQcM7j+2QehOF0c9m98WLWNzio9Im
0UGB/5NZmVCg/zBb/3jU0JU8IvoSWQQCM3+7oWeaqqaBq2xSwCymxCaQUSjAi0F5zoct1gSxnKBX
Y/7SkqVxMNamQkNEgM13SBxEyxulujKjjACRQt4DiXdryWA90BoiWCCExNX30yvQD8oMtyaMwQ9N
m8IKhIjViPiF/HkbP7XAnmdkWJlDAq6Xkh4ExkHGyaEiT3zOHZZhnRaZl3p7x8n1BSETN4BHseI8
HQa9qzdEjhWkWYk4FkGKY4xoBv4QCnViwlBFTQ31oNRja078fYjs5+m9iIPZ7FDfYmr9BuWAHMbD
LOJf2AjTxnq2HQuYgYbeqww1krCH7Alh7UX56OL5pEUpnXxRJxPqd4p0qJG53uwhKSpUO6uCcaB8
2kzxieMs1ZKpYg0R+ca4V5DWZ5GjdSyKuGnGQJ9+ko59ghmzM5B4Ltn+86dmaP0AbyhWN+/SNPJS
EiiqZ/seVoXxJJbWInGGNmPvNru0H1iz5Tgf+WZ+Niw+adBDrs0fIpeRgbJTG13+Vorg1KqkORUF
xJLm2xe98AUu5tOAKrLind4a3WpfyPhI6idouZUUz5uAd1D9W5wOvxxWl8mjRo39Wiqec+uj6VSH
3zsb7rEakp1kzUF13U/wYtlCzXeeF0oJ3hHqiEa1lcg38fBn7Qexi4ftl9llLJp0QvE8XsvVG1Vq
FjDcQTb/ksScR3b/d2Eh97ldRWQSAKnPK2ZUljsiOf+B3a6yzN+nmFYDczD4IHthrfIHUEwrklmT
tqwEVqV54YRskSEMdBZYsfGY46gyWuhmvjoM3VYi7VRt7pTqcV1U9jcBXtsa9zZCNowBcofBibs6
Y9hAqV7RPxv+S/s9tFMY5SibE4ESGfFAuPkjUXsM2ag2kO+FsCkclGymRZic1IMCdxYa9v5xj30u
CamKVScY76UDhhZK5H/E9qSOf/YMbRNV6rcAxSOQM1Ll0fqFLZIuRCJXyNmNg9pp0Pv7Blw/lanD
IORsZwFB2ZCD8cMfN7Py4mCItLoJVcheX0Bmq50EOdHcZzEwYRAC/dMQ9FlqLmjiLjTLgWQZHz7J
nH7WBK3lTVxEGg90ugoF5cvBwXOof7jG+kBgA+R78cIhRBvqxGFOgOlL1aRp8FbX56NZXMsN/qme
V136tTjIKXU+gS81xGFT7VI6y2cAE2BHJdZhFeeQUDirEj8Voyq2GY5mA42SrmiTUNis8htH5gTG
AdC6MkO2qrqSEZUlbplrAhQl+jDt4/uZ7t2VwkVqoHLF1nE/XjqdCrZWHBHKeInk8ELvxdhEC8VX
GY1u0H30/VYfjTE8ubIHg7yEQlT9n2sfDVv5K/ZD/qcxKyFwOhiNBOccJSm7yyrz2bgz03oI5Sz6
1+LEpXmfi/L7Ec+Ig3Q5/qHytPoaopSpiPPGWZmjHW4QVdhGXiT9ouJmUOPbcd7DTKa5FuyY0Geg
IPR1JV35Wv6zvitxXDi1I0AfMMMvvYzL4p75Sycv3XXGwHAWUkFvZ2sD9eFOkXI8j1Ozm4jblFU2
bLuAh4Gtg1OclvLwJLN6ZJ8k5BF2urarkWkGOxFAFEsmYHxb2ZymE4EeYEOPZMACgKv5wu8Dpnrp
kqcfJTHQQmH+9oAFbYmJGS8Cb2TsTvXIQW+1eawcp5cSVBUdyqILn9ahKfHm1SmVeUEXzYPzoeas
mx5d6qcWdifa3+/+wY7BuecQOqVDLWIkotRKj+65h4GCNyUc7rochxI+Ik6A0+DhrPQqdaAiOzrZ
vulA5Y06cM/uy9dwK73Mz1ffdmuHhmUhtVX1EHTjd0J1VOO9/zpFFqq3jk/JW8gdK0LJxHZFE46u
gLaaAUzyGANNb/RJJ8PuTgMuX+ZWt9rcstJyt8OB/idW8FxcyTn79wrxyb+ZQ2SrxtA0fqfqan0j
IUgR/ZV5xKHhN2GV0ElTnF+vPIHKj+FpwbrVeAN8fSiXsng+ssw3OpzbvEJIhn/dDrG8IQm4bc8W
Epj+CNlOrdGaGtAJGfJYwVdwyeo9ot9QpS3fL7TJVe11cLCjTkjBG6rO45osTlkczsSq9oQZagjm
r7JBLE1TTffMjKrTHYzYIUuTNH9ySFjkZmATHdSwH+V4yWbC5hBzuw524o5oq6fhMtbGu0CEsCsm
928juYqKulubgHMHLamyyiloB/FjSbC/29eNjHUI4n+5tP0GizItyKyt7CuI/0di0Vpe6s1UVLgI
qDHLj6QPeIf1ivTtwzLo23aZS760J689KJBOt2rPtLVCEzgrEQG5iFiRFlTCRi+ZJkZF+44uPGkf
qWM7lrKIAFmF8CmfLkQ/hyKcx/3cdqM2k6wnWhuYKHqIodkXnrtdEcVQVxLqajygK65jPC9cBYyT
THd8L08/HayNbQnFjbj5Pt1ff43bfqeXJTpx/INMEgNnUYd51fmt89jN1wI7XmBzDgW09Vc/HElm
c0tRU06GTDp5mMwbcS0L8btHeRs6oCDJvxekNgKKi4tbBIk9U5ioC2TXU3oOEN1VUiecqybp+gH6
pQC9JOuRnfyPShSMORltvjiI6AegL42yApyqaK0bKWY+kLBQNUxQJllO14TYIaLzTjO7JrHeSOQ/
c4tlqbeudd1kI69IZJYlw1ia3MZmHxpu0VVLMZeq7d1fxQ9+OIgDV66rEPetNSwz0GTUbML5QBT6
jpvDJWdu10Q8UKPa7FMVlYdAfQdiPhUpqCphzCJtX8sK2arcueJsAB2asEUK8P2k/s2TzL8xqfyy
EUD/iSELrjO/pgmpWhQDeVKKDv5I22fBjWH4JsL0rSFbxH6ws5OurpVo42w5jfnfPiIeCbVpsYcw
isDpgOr3nQjXct04ibcVe+HXQ/inauvqZhoYyUo+l4arzLzf/pllPQRsJ+QeIwgCgWEOafY2atZ1
crf+KKtI5aVMj9TBTF9ecKaA3FTOvnpuQkr2+w+pBXfdBoWUYhn+613wtNTlCHs1n4dpV78qOyC6
0J77dL1SE9wOFwIdP5k6Eia8LXJGBqX29AmBqJWauylfT4n+jKk30lGpIMlN0IICNms4qU/OcsuR
zwpPqRguxNcIy4o72wKSBU5c8D9TTAMUot9UctynSE+aUmtMg3iEcYl74k24R8LutDRRxin8TjY2
mLX8RvwpYa98GZyjGTnUEVaev2HIin6qBLbIlFdobR3+vkvOCJLdyf2r+zoYjluCz6PG8DicRVnv
j91BJ5l+4rtiYL49s+PjnBZV6d1BVO7fmlS2MG7WiuDj6f8Bt7XJ3HiOA+0SY7fY3ugwQ4dF1cwQ
j7DLmpmx1zjp2cFl0u5rslu4bRzYBZBQbVxmH24oya0HfoE3+uFYO4shQTixpsYTwaKXPgyYhIWB
+GZN/YLBPW0RdDjAiQTLQce+XTVnQlX8HUmRbJBmDErMlmBzCJQ8k7AGJj7gExFhzTPQbtDeNJgd
RtQw0SrPSweZUVKrHZGSRCkslug1Kx711qv0bOKmyXcJFRUHRrm6JE3RlBrEJLZ+8ZEnOScdcgBI
RcoWr2imkkPQql/OR7OCQ3WxhsiERp81R0a08Ea2DqeBnQqUTx+6cjzQ7/OvGclfL84K072rpwxE
WsVuXWjAfDldOh0eamCGPwQ08GAqNb+DlgEGuI0idgG7mws6NhMYM8ElUj2EVlrlaSOs8TxHcvei
z1sfVkXBshKgGuf2dPEGGKGHhwFETHJZSJ8yVBh7Ur4Nb8ye0CnVFBfmA3tOaJyWTbBqvsKlLGmz
pqUl/H46FhYemUaMUgKuqrvyRVIQK+2IJlQEzqEDuaflDnnWgfQL8+1/N7bDMaysWAbJYFXHzdht
yP5Bi8Eb5fDQ6MbvoSzC8015snAXifd4iPsEv52TviWIQiliK4ziH6kRNyrRVfYagadmpsztQvhG
GCLbpJoSxwoEaTRNORlCmtVqyFmCiVrdb5pfOzY7Jp9vONDBfkoCj5oLUfZzgctqqLIjxuMMFyLv
fvovKhWvUqJkZBQWZOyOhCQ0UAzCT+9H8XqOAF6K8ul3SnaSQ5YAP0k5MyzBmEM86WYmE46kxRpM
C3lmQoo860rL68VZRnP7rbY2Hy7ChYVvAMdZnovfa27ghaasubg1myCfkr4wddoLJSMDo1gLHDXj
trd8s4j6D2KcX7CGU9rX85ulgZjajRSINU0qP9gJbfEWpSO0a0ZI7gzgRUdw6xj4RpyZnpJs4toB
WDxYAtwgUxZ6yQaU4ifSN9S2NjtVr+hZht/6YN1/INRYKT/J/Esg3HradPmftsHyr7O/Mej+feSr
u/4I7Z/MMQBAexXtxrYmo6WI/VC469Vln27RCIJLVbchcAz+M9FRzlSjkosybepzu4nJEycoctsM
X1aqpTnpAU3a3NuF4jTexcXV2ZaIqqdRyCTMsUJpdfUgT7fabK0hyFjJZCsx3DyfADqoUKTAZzAL
qBriqipLBmVA2rl3lQ8J8sOUDCXuTiJrb4pmgIIZNo3DOvcg5l73VEnIdcU5cMCCXw1/auc0JlGt
hhUJPgvFeeIsVg4uMf2dNmpaRzcFOfwJEYk3hf0P9V2HsST6pfKCK79/mhGsirNdWZlOTbZjelSe
xUdFlBY4ePloMyaB2Qf05j2Pd21fWxwO7TxDQRxqVCoz1C4cx5VmUAjlf2voFn25GNeUTVju6czF
3c/dopJG2VkR+QISiNNg615C3Lkzz32Th3toaY0Z0XFqxohPyXL+yu1yCVNabQe9X3QOyKU+tbyP
K7IJUsbEOv7G40vm4nDbEM9N9IsoSVuMNcDfZJlf/m9Bq8DekYW1c4VJGcEq0+xg00VWyBNP1jUR
LHUlqILkX/3PmG/RMRWri/VnKJz3AJxZ3/RkP9diiIZN8saFMu/eAlC6ayZDeOdiB1ffTEDwUD3o
Nnd9sAGP8cu+XUpgs7TKHH+6s+dQ/qo2erqZAkBsNXVIe4uwn6E2ggPuXpU5zfKGXuciWX30ID8B
WthdVqeLh9FmqC88GxdfZaF3577LdjpXZkpyDXwNcnFmLnQbVhUFeXtfAbVKP+j+wlIJ0opPDZi1
fP1aiqoJuJ0WIJL6bS4IT2eXAKjNb2rHsye6zKMLosn+VMDNDR2r/B4XIuGtyaK1kRtd9eZD6ZVM
tgyx2sGQoGUURY6qX5J+b+6zR6ry07XxDZ6Mf1NkdOCTi0AduTAcXA9/kLRvNtbvqBptzSXcWAax
0mHxeoQx5EpFQelqg0yVufhTy2C8k2dKnpDmoXyU/Dd/HbHo2+eXDQK2DfTKwdYxtVVL/faij24q
LxIxSuXFa9kOFmZPMRh5lwu9UBdc8Othv+dOq31VaQZArqB+gXS6fh96jzTYkHxq7N0gMriVVZ+3
ZYKZnKpaXDboSzQkR72l5JSVI3/0aHPlwnT06dU261tTkrwqj6l0/Uq/6/RTqjW4dp4OzgcYur0i
rMiwpLbrM7hM9Q2C1pCAtl9UvWbTUjFK4KM2xzPMflxw0UN52Bb4LcM6gBcNod70HO+6PWE2BPLl
YEL7l39NWQVlKgBDB9IqR0pfVwlWFpp/BfmESotxA91U8PP1N8/X/CnqEVV4pNR6OiC9Z/ddwpBn
ZMnKzkb3FgM07hTZME3JsoaFQY1q5E7GLv/2zAM21sWEP/VYKK0onL8BGzCURhMavwFS28LYBVSJ
K3Z/mGSLEp2nBAwPrkGh35Ts2njQEMEUTG2cn6JMROpgNYMQpkhb4vsw55viVaY57I3Ow4xSBr4h
zJ2hr6HxiZr5HdKJiyEFL3TPiDPFfgUCze9egeVbB6UEt7SXHupk0VMeuchwJ5iYY02SJcTZqk7c
+I2DhUjnJPpPZ7CO5HBhgyEXkqN2ntS7E0DExWDiYIT1lBw8n8jSvrmLtPgYGwj39HTG/X4lCezo
O5x49s7v0+rzsECi+1B/QXBA5l7Btwf0Kllf13atJw/kMoZzBT5bI5t1/Ionf/CL0s7z23FJ/9vG
BUOmf2n55EiiopJVinHK3GNW9RMRaK2tWB3IyRjy0K+qscTcGOg098TCWaVYShiGkWpL25D+wUe+
YkiJhy5onKROOKgM/2Ir1HA20SXoRYrLJPSgNKznBJM598OsynL6kqDqU5kM3onIXmieJIRZHktK
44xkV6h2cUz56yKKOShXsICrEakNlEWi48oHFVDgVX3a7uT0fywXDdsQdbLWfSOtNXg2utJO443L
DRFNbp2m/Iiy7nerhJZLIRogGKwea5f/NzU6pAx+gRj2wDad+KJGgcFeKS3FMLGqemOsnDCuDlZN
oC7qPHDxTSqwWNAGZup3NUNO6r9ZQVf49BlwLeh1EDcuyytsD9K5coGAPfaAJ/sMkO1chCcIBMAk
R9TzcdxHNo5e6JIGA7vrWuMLF0vUjjqJk6/NuWLOXdVFVts/knTWv0zIVtfIx79v+21z8K3BTubf
aVpfbEXCRzQzp6mEEowSfPYKab9Hihk+gGdVYZcioZYjGQfQCkiADdI0dl0t3GQxtZSEG8Pm5Sn1
QAxKbtoHo0wFaGMPk/vCzqYtZdjPkAISWgKUZJd37odwvr3ahnZKU7IwG5QncksWn1tcmrN1lgec
miQEKZuoPYewptwYEhh3IyDJ4WzEZdx8wy+tdUJrFw0iEqy/jzHvuH6d56mmDFA9lC7d549Vxnuy
2lCC6lm7KsCEYP4krhCMxovTTykTw2KlDVEe5AqYtIBu4dy4zgnW5s/VLDvaF9/zmw/rmjHWH2E4
1PY01CIhInrMR9usp4qPJkncvVyLmqewgCFR3qdhepO7wXPXbdfjJtWvs78aKSl1JnKslIu4Cq7N
/7WbZZCERhXfaB8CpL1bv3K+ANCNWHVy+n0c/pOtCrVWAflcKCf8I37q5wCAFtOY8KY67OGgpkFf
K+9PtDJ6nUps49TWEEdO8szQif5eKLPDoFHQo4JzlmmmxronX//2qBIM+xYiTvkRbloD0b6SyjDU
/re0Q7P2lJop6TBeHYokaS8jWBgnBzLW6iBorDQkYLo1JHSof9Pfih7wzbjOTvMjpYJN1lA7ADyH
ahH1OftPW76bbH3k52glL03EGTY4H8edNgJJGf1QWpnO6iXVZBSpU8PiQJiyyioE1HrzXIP2C9Fl
0vRVFQ8OnQe4mc1BVLY4EGESlL+zJLcEwQlqWSWMdGrO8e4/T6bbMoPlBqSiA66ZqslN8vBgWYta
so4EmXZ/8fM5oya9FwQ2G4bWbcaaemuO98U3iz7W1MgUf9GPeMwCAMW4jEWO/2EgSkUDRJMhxMB8
/ZXsNLsJf53J5flphlPEp3K719oCFYzhq8kKvk1j9hxbM87HxHKyY6oAEr94Qlfpo11vTcpPKSX0
putzKF8KfqqFbpenu1smUKaznA5pLf8rgSJhNaFFiIves/ea/+NX8lprky1M4cZtFY57ojv7OUNB
u2o62JO4+BzPavnwcOfO/02E46g8naBGOggDa87OVdh4VNn2KxaOqgvZS1ZMesa2qvcFTQoDZPJv
s100yKyyMYQP78+Cxx+v/gRqCuEzFDvyfnuGd4gefFbdbzIIhXKiYo9FRbcvab0GUjl5Rd8YFRJ1
ClGBixOEqrL7NdD7LmOqpy30RiV8E6eA8faYbIIkoQEhWufiCuBTKN8aNDkGsqwXt7wSWQCCGAZ8
8/YyTtp0eMvZtBLpU/wg/8S3ZbB2BMFYe9MFOMOzxmVnLFSlxYXRNvreqQ4i16oQEGswojkCJxVG
f2ETSFaL/E66Eo6awvGA/ucHtrDsLaeDzA/Ke6Uqh2HrMdSmIBrFegeGak7zZjpd761klFeH87dB
TwnEMVf8rXT8fQw+6I4Hpjl+J1kgkzHRJqxSnnKcojUFj3HIGgLHRL3vS9aDAWynfrvD4JocI7r8
CmxNj4Yu63D0PrI4IhVaVRwuPnVL8oJxTHk8WtKnAM/2aKH4t2qui6hO0OzpGKP8tYRia/Wb4+UL
DBAfDYangOgWXTGYhSsFlh9ATd5Yx9iK55ka49VCUhme6o6T8Pnm4PsxW+4hl7b75bGSXPB9K3Bk
65gYCf06u3lEK5M0bujP4RMowz4Rqpwe8oxHbNDNI2l1Te01HXvRphFzroVqJWsHQ2TSxnLHama4
KKo3p8jfDIthw35nOmaK86ci2R9qHIgAAuhEzRJ7KQHOsf3FapQzN2R6WKUp1Afj1cJaoQ+z973+
PySrEKFUwtUrmSwmpCECQsQ2y22ab2AlzDzDYClQUiuCOv4Q0o5rLETt9KEH7k5UgUeB/auzJgDn
aQR++kRbK70V0BIsv4k44NrsYBWDpvXTsTP1EL+xgASQfXn/nkMI9ZvLMk/tqr1JNZhfurFG/YWD
DrWHyv4amrs0gqrJdn2fneInb7WjbhIKdSC1gwLLL4I9iLZcbeB944SR8TZ75Rr9oiE91j88+x0c
Kf6QIgcd6y5L7eCLdwWhDa9Y/goHI98c789OYwN2LkjhmiDCY9K7tn9wBuVGk+HdAqYyv3HHDX5I
yUY5X8UwH133FEUfeaZsc02GFW8JWkaycPsQzbcI0nqbsjgzMHgGOnrP61EJt2Gyfc5tzE/y7N2s
tLVLzEphgdvPALrSxtQKu6xG97bmONdcS93T4MpiCjYo1gGeduXp2d9QXJZOT9r0Zjtd/qsMKXRi
66ZORcccVSp9RDw8pfAFNnCeb0k+HfeVqLkrKe7wDtZZHSOmhtVp3X7M+ydVvpdUK+7aYVwGuvo+
M+GbJhrZNoRZKBlf6qGu/7hjxsqKT8c6yd1ANMITyocpYmwPy3MeUMcM+PDi/KwSfxB3uWSib8Wr
RaQMjzxjipZgLmGbC750DUIbSzEno9sI9t74OoktQFKS0iEhpJikGEvxwv+oagmpnstXj6Sj4dcS
abGyP3Qt+6aTJaQOTf6Eu36uNjREwSn4tLzr+ecn8ezDZ58r6iYrh8Gr6/Vl1OBgEKl4pz7yTeMl
bGeq8c8//2foFdSed3PE5/JZua7L6rhTy326/PsTsriZgK/ypHM142Cg0Un9e+gksIiIbhrsXuxd
whgCNBUGQsLQf8snZ6uP3hG6zcn3h5B+1ikjtwdBxYp8akEbGTH9MrSVFFSiHW9TduvHrZ6UJw42
JOsuPPZjNtxvRTatLcis1uu78qjAjyd75qYffqz2+RUejwpYtThctghenH9j0ejYx/0MwFSjn6dL
J6ftuCc9UV8VnUSoF4ItX2yecKPf4RMQSCL49LkMQ0IAlWhuOBBNQTZc+cFiRpT7HwdL9v2UgBwP
6MAeGZVXrVv1fPwqTkl7nST+EDAY4No3GH0HzsHp4JIiGw1gGg05wNZplikYmKdiJjNTLJ5E3FTo
kq3X4NZLFmGeJi2szG0KHBgR97Rcupd9mmFeCnXNBeuH09NuT577Q1FWCWxXEmjZTU/a1Ane8Bvl
jUTrZfzHFZgH3MCOag1hUbHMxAo5jabNG7IgWEwfsglA0azsJKaABbs8ZFpQpzShE9EYFcvaYiRL
7tLASMrp+9KCk8im1K0/7TZq16rO5lHn7Jphz0dFT9dryYQxvU8buugewrs/i1QbP76DtyZtmb6m
36m8PrP9mdiMyYEuBmhhi7pudsAUTAGU48fc4ZYg4BsixiPezBvNYpjHm2KuGnvcfXmK0+e/+vFw
Zl10GfLohmJ1xtb5ILrnXFJsVu2Ui13+pcMvYKZdduwQAvHxwLlXGiM5jy+LEny3b8neFf6EyQiN
/laO0U9Nu5/S7hnDE2cOx0cJloZ+tmnVvYI9ZoPhnmeJ8dyxyXX7Flg9lgi4ccZb5SJY6JsIAhj3
TkilLaWn8K+fN3mCIeOHEUuLmUzTQaBOfbimRQw/WItrA8UepMgz4YsAOUFuZDnAEwxSIsd97TSB
3wOXwwSyOCi8R8I4Cl6UYcJnv4Aon2w6aNmFV8kQKcYFLSNpIDuendK6ocllkQ+2IGE3OqtNooMA
Q7luZTR68XlvcUJFw+lCqN/OcvKn8j/wZp3uETXa2Om2MhGJwNiultCCKEzLOKj9TAYKgz/jOv0o
XQXq+wX8/awEYWomoty0hzir9iLZvnXtBHPbZJ+NXXstksdoADD37gxF287PXuPCBnmSEC3AY/oF
alofOlZyYXrrCa/OagOd1mpdZ/uNCVx2xY+yNqXCwHRTaNB3NK1oueZmYtXFlLOlG50rB1GwczAT
wiNoSKCLPGAgvySuByPew5X4L4w1UfJIUQ7baPmy98X8YIdi1NFnFp0U56wyRxXcCi9ebzfnJLKB
0/v3ICsgoTebDacaI0+AK3BjFeo5fRZMgb9o3CnRMhKC1z5Df1jg+t2mTINglxaWmJrfONAWxw4Y
OXHcMeH83AinXJbZYSfBnGSX6eaqZGfZmICR872x0q4UyzDIccj3RY1JpAMKYbkF/pjo5ih4HFNU
RycXDBgXJx+gqCTOJg3OS9Lm0aCrg9Ye+A22oHCk6sNhS/KN0OlAdGSD5nJnFgCvrIGyzRHoACQn
5wSX6uWLswtyjR9nlWaxuWrattPt8cm+Tz/vgE3gEsxtHBBrLr7rhzEA/Nh2hnEwmZJlXil/7FxQ
PucYkzMViq7inu+XKSneS+hZYwUXPdgSjYWr4/NDTHCLN2vs/AgeCSwAWj4xrZJJJ9KLdCYIf7DU
faOOSqqBPhDlUSjJcPmO7d3hunuCqoXyzFNqj6sdM0x+uR2pVA1Rc2Fpn9QQKLGp7XJHePnbbg+Y
dGOLjW2EbFTWdvB1YexwfZ8EQGMUyGd1wkc1g+yts3dM6o7sMSBDZVLjuiqdRL3fNFouCDyuyy79
NAvcyja1tO25++fRsLAYgTv6WyOW+Z7j0TEsZ74WdWvRKJgoIH+yNJPpc9nS1f6o0yMJLd8gU8Yz
EeFF6KyIPD7wLwCLhIGuQFG1UlgyN25bic6W0DRe89evwwGtVf39YYSrdUJ9xTQwJ6JjpdDeGX29
BEkc6IjwKqvafSkF2SOPbWs65zwqV1mlektk7qq9V9ul8R8hkv02pyGPv1KScAxfJR2LfMJivy7/
I6BgivE+ls/h7IPPnLDZ8O8MN/PTji7zvpW+Zdpchwq9wfIHQbAJnLjxzOHeRc5otOAQGHvVM3C/
37Poc75XDNZZ3Bda++bJSkVPKGAS0XM3MiovuIudBAcy19vuoa2pI0R+s3G+pUeefX2AKi3Qn759
S6IGjju3/axYYZbo2ufkYnWMc8eRHEd8euqPkta5HbrNYFYhKP5BUT8oA4WVNLIf/M11elvRFMkr
ko1GBoFO1OURP655PH35nuCYgAxzf9iUvr/vcd/a/ntpMcmPjMN3XTkzjWclhgymSTYKgM/2Ne2w
0xg/yBUw92r7BVXIjB47IWyJ0TfC/RNf6A5cNlhhvu1EL+DiOGKkpc+pKiSqgIuHV9ZQjxBaydgS
GAVfPG9QEL/jMpwq5xyGlORQyqyBji/dzxwPZ/WqHRB8rERkRumv1ocJTypf6H7wIFlcigRY5XqO
oV13342G7fawfqTc8vC4kOl7gr/F3o1l/yUV7UluDgSUyklfs6kKxTKfhTD1zGcQwHPSD1lswG71
4ux9w1uY3ufcv9Y+06uEgQe7+BjKd8Jr4C2M1MbQwQnlRT9fhqyDD5V0WXA52AsYe34UKYL+GKD8
Zf81ftjDKVgMKrA/N1vIv27OwovzL2ZVBSTt1zCcFQl/T/5tgxj1peq71YuugNIpE/DKrqG8kct1
cCDm7aGy5Xh3t+CDw2qq7Eru95ohbDNtOovL2WsVHr5n1dSppBw4pig2Lnb8JaP8a0PZlr9dkFwZ
bwQHAa3OiaYI2ZZBJBzyteClvcpHnJIwZ4WTNrHHxItRIa1/1a8Nfpv9DewEMLpIGl/IlW7lnZMC
gZfs8abpXUKX2NmabaDHJiH3AK4JW0KQPOVzeJAJJ8Gi0XYkyaY5hir9nTJv/szcipTB4F5FdDi8
KnmMacYxkrAU9/Hc2vfkAnJcNjdAgcF7OlinGausbZSVWv0T29q8BneGy5iek4tNoAjuDHsrZDKQ
9ULUtpq8ryusrtjbvVmZeVKpn9HH7l56f6le9rWOPiXCNnr5M/I6aUJ7Y2ZNBVRmsb54hObZYzGP
meWF+5lIeNJ4OvCRAz5Dh1OanURRaVaWGyoYDfFcSonsYLOqEB8GEmxlRsfCJ1lMlmK+usuWoPDa
KgoCQ7omncyn2poQRjgBpdR+M+yE5Yy/7B6IK/6AHs3rTz+j0l6pILGGzMl6c7y2GjDnxypvyTMg
TfvduiQGfIB9zDvAUg6UtaKa9JsNRrQxTbrjXBGVp+njADJM6r5nf9WNN5gca0nOWAQw7JSu8iFc
HaXNDPSqGqtsxjCvD9meIavyZzDOqwTOl0crYpc+F8dqyTUC1tw82X+QftYyqCSHin8YCXNzy5rv
H278isCdHhivdKs/z8jTNFpvkAjdN5iyojB6j/rUJxK75sjefbcLyH4Yb/yS0taqBKhJmaMSxf4d
q31pKpuiYIrt4ehubgnwmBVmzjb6/+OcSgRmekmePmzXsR+pqyb4cFFRNuYcZ7lwzpAtyelj0Cxr
X+CDOipd3uute2pbEyRPHpJJBaplydCQCmGWGsrhTARJI7HIIfRmQcBBt+A7nxVcWFIzsqpXxZg2
PyugeKrXuVIj0YU85tTQUy3CH/bRxM3OfMtcVgppy8sFVkdj9XQNQbJ4UwsSsi/Hxej5oFoSe+CJ
839eEIu4tHRZy5KmdSdgzGx0A8greY+kis4koc2OOo8Rg6aKso1rzv5guJb1okjQg9/o952RIKm0
Vkxzg5GNsrUTOj/noAYUfSkeF1XA/hYE3xsPd/9rvt4fetaSFMMvZiEaPoWzGcl+rni/fjSICnIx
EBTL9x2Tlx7V03WI8TbeJv3tFC7R+cV6C8YOAMlBLozfBc2M0Cz0CzKibRKYsqIsYYtNhi4jQZ3j
2k3Ey/u/7NkknVFOxM4XTISiNUvo+qRmADCpYJeO7QgKGeu/qygLUWYhE9JsDCJJxaTCpD17IBHk
xG669F7N6GWBLR1EhPQ01ZVrhX09YkzcDnn4nZPOitxnYxkd0LYkrvCQWo7noV0WK1/k/DS+Pwxl
Scu9VdJLEPIazsDfzRZQUembdo1DE18Ft8UaTZiE9mUoKX0WntMx7YCEnB1uyGHNkkUHiwbnpUVL
ra6PBkaPHUiD54DayXi50E/I6I1ESlY92hNR66eePK/4tiDtamgWSMZmxYCiiNETVkqUoLscZc+f
iPZeZOLrWnjxTXqqVhh3YPvRjoffMozfqFVePi7Y6aHuvi/iGNRyIkfi6vYq9AW+p84Ojn+P8wRV
68+3adFQpJBQkYrKf0qijvnEHOLz2mIHpm1eBJidHhIbKcg5iWS3ro7X9P1v6mKNc8jANuaL8nEc
aeW5NSUm+eSc4VDfqH8itstLQhvhKuAhyhO3O0qBJcJq16ao1G9cWkgqtEeL2ge8aIz40KMyfzJx
fAD/LJTGv68njrWXx4YcR79G60XHh+F7R6KFXniXRkK7SrcMnRzI6/JuAiGHJYBOrpTmHyaqRNOz
zup+LfBTcpXqilbscEcX3eU8u20b2Ss5zJ8pzAmQfDOQbD2QYd9ihICDKw1sILAVhps9RXXRu2cS
aZK1uoDGBGKsZXyRsFBO6HcvSPBMzBP86WGcCyGYFPiw40KDJtcysOeqBAqrOLp2CJ5M0PhSbwww
ukbk2tE3HlM4oby+3ZDDR06WDlCBukV+gco49W6kUk5uabiLuDOsiTHu5PvAGI9RkxkzV75ofhhq
/CcRwid+wlSy79w5IlD0n+0wXGXJrsdZQK8+z8MJIyhR2G+0hBGIbWdZ2akO1Y5fdKBe8CMFWmwi
FaHjr3nCSr8HQciVWeq+QEkffP6SvyMG231A/LhoUvTCLT/FeFrNrTJT2S15Oe77fTdHap91iZlW
KpJu7Z+KcjM4IPB9xkwKM74HumGbMCYo9BV7ulJxOo4DPDz3IRbPVqPqVtsxZtKmt9rQaoyQIMAw
1J1Y5muqi7eBSsRnV+SKbMjylleEleC6jRS9ldZ/QZx93e9QP8GSDPq4HL37kCvEtsdi5tc7lmtj
rrKS1JjawT6dbynNElUaNYOFq14m4bs48eSuoyXOwf1VqcVOJr+bEQ62dIGHQJoUNhio6mNINRHL
7ST+u3pProm4uM4lxIWpTiIsVbzGXsxfM+pvb6HvcdWjVFNeEY0KT0x87EVYkb1VzS8x3rQLLFeq
KVwRel5qttWJfCGWX6V7DpNPZk5+rqw5jdHrv13FTp2StIPXHUNiNbu+AP3ZRYwwBL0CrM/H5mFE
VDY9DbqNlz1IkIGm2seft/jHz4sIWsdtGLuhgecNpGkhd/0OqXPiaIrgq2ksAE+AF8xX5aPQTf/l
QdNPrQnxOnFY2kNFSFcemkJxp0qel8HgsZTPYq3RWDcmEA0OUSm78Bqeg8+ELYXDrXxykcZais85
Du6ZbKIkImQ35sTdwRAH1dZeDKkVHnxQNEsgI7lOA6NJ03WwUlhTn5aVPlNOoIF6Oo5keCcrRaXa
41r7BwfModx+HxaZptovrvJSfUJv4+fVXXwMs5As4lR5UMoQicNxiDbXt/r+Jk9R5//fi4QrEjPH
bbHcUCZx5Suq2Q2NoQskuYbdmGNh1+kHW2+BcEToNwmlJqd1LHqS5m2vt0Oz0uDwWz4OifQSJM1/
rheYWOGalYgj+wrnPCB24GbS4BvTRHPXqgXrwnu5dhMPqueHBzoONMnDEQcOLMdodoDvpTevK/sm
NgrD555DwOfpc2c9UXa6ojBhj5qDN2uhBJNrnyJpR8m4tfxhQnEIFJKFnt6TWViDfJ4QRL4pYcJg
yow/ZYv/yqwfiTSwHI++xr2QyKWY71T31UEcbFQNtArrlvJ0v2jiE78hFz3KC5Ycsv98Y3nLvOqO
Bq+kol7BMHmAcD4ol7ZAZaFg+hHf8FjxEHnbzDkKhZCMWB9lpT4bq//77paRTkO/T+3MjA7cCoQJ
JXjkjhDowTPfH2HR77u2A6qGsJRFtTkQExWCIXeqZYI5QxWI8CFSV0KL34y01qR8a4SJXUsJE6Ot
kyPHFD45anaCz/0vVmdiNFr95MwW665m+p3fVPD4jyqHlKXAplQUpJZP3Se8V7/kl7IOHq7ubsQK
zP9hXiyVjtr79uzXZi2eVp/ESO/NDC03GpC5sCgatDGwUjoZspbyqt4aNN8BVvg04pGyKCaSH+SG
wV7OANDIhZE61j1rBh+5wdzKcTazgHCCldweHuA+ObuzOfeL7jywprG8AkNnP2//XkdpKyvi4+qd
iwc0/i5DAwU+X0HtzwBTs3q9wkNklDaXZEy8TKQyWGuhky55ScInbpQ/Z+KjIaUo2lHOk7XQzlnM
wprr/QTg4HhjrWng8bE5Hsnjbyh3phb2ZKuDygjtwl2aDmSO9xdCPNJNv/psuTmwPJ4+/tAadsLH
qWXWEu1Ov4l54PZl53vRzI0Y7Vz8sogW2yC3dO97vsxIUWbgBtl+aVkc4rEp1Ar+6Fb6IYtwlxar
T+riIGI6626haZ6wUS+aMp4jYIGsBORRFY/lcY9C7A4Ynib2pbGfwoKHESQP55s7ZCOcO4666DfV
OjSYtzW8cEx96w3uA7jhxw/5BdS2k7M19U0BNDMKvIW1J+ZC1HFH67je9L6n2//8GTJVbWf2T7Xq
qVsx/QAEFlsPv1tA1ZwEAzTiqn0wTuRBd+/FUt+rvhtJH+R75yI4GNxtLmIcVPuD0QFHkwqaeYRq
a/txNbJpUuwW/FhrwyXlHo4KPKgfBY778ZuzrGGt6bvniWE7K1+Nz/M64JlP0hBFJW5nf6S7rNvb
cttqtadfj2N14dZdFU4A4KdnZAdxiii6yzw6ZdIfQNco3bCu5HTdcNEAKDDIKocNpfdEWhAYSGY4
bIOirnBujcGk+LHZgufndK6r7KI6O3YI4o3MSIQh/zMhBjrrjMVUKW3vVr029709N3csk1elAzXo
+f7BzCSaAbN7DTdRb37YLOYX2T9xi5XP5pyo3W1LeDO7FLj9G1Lyt+cjJP+Uv+yl0hzrgCcZIT8J
QUR+IOlHQoXK3qYxlf2CBE8EYjHFu2PESHmYqRXwdpvSraS8G4hmRuEy68iM6AJualRH7Iw7vDa8
YNvOPiol4IMfOYbl097o0qUApj4cjCsWKI+b46Fxqdb4tz+1c/ch8BH7c/TNQiJl+An9MQUZ/On7
uDE2qIcwEVvSdxWuda/w7ecky+eChRQliN3PWg4WGiKLUhjlRyKAvdNBqcX6jAXx3ctLn/oLTmiC
ENl3IPIEByt7Ly5CL5crf9ZyCVUPHBk1nlXznlX/20CyOO4cPzw//uazoB5pzko9A47EKU6I4NDX
ONVy+r1WTUnUjBZLCBMyojJAGVzhAQBkRxgJIFWNvUjb1l4UoBsjArQU+M8LISBj0tzDjAl8gstO
5dKKo2aDePvyl22MSXHdOHfMjIcVcF2kKgALP0w77rD5qFlHEiYE2SZop2tKM6BnxLn8jj/WoiO8
aJ3BDqQjVms1fCO1QVL7G6SzCv/4sGxJbuTuVJFXACMsba7h27heTXkPQIZGuNGZ9hKcEr4fVC0+
o8YtnYbOnsaCTrkezBNJowYC0C/81PjwyNsxi6AaOhfVB2GSTfjoKDNuwdRmnyfmomxZizam7sgu
eBXJkI4EchaeeA1VCm8MjSIyuXpBjU1n9fn3p9n2GzYOEJYT+5oFaZ7rxq1h37lnDI80+QSx84D/
rszeSNKcAOrriIzY8IdIY62EVEYAZlyHdVN3/cWaLNv3efmj5vMXOnKvXbKVa46KaV35/uBFnLtJ
PWZMsJiq1eD9CdQkGxJeXIsqWL/RnDk7iSXaSLuPsmck6otpTtt/D/dqrM7BHWn6s/RvZR9dStxS
PiX8NYD8SNJNEM4wiuZlF2oWGY8wf+pLbTs5dRc9vu/crfCa+lrs05FV96pVnKiqohZGPk9kFoSc
SFWUk0wxpE8oSYgd5QaViFQkCgCBtPy8wqzVPDbPmkraNKq3URX63ork00RWYuxC1oNdoelHhRBQ
Et+F9gDmegd0qOd2E7znK7MTzrgHulhIA2+QZPzbq6kdWK1ltSRXsrr/EDHKHb1u8E+/Im9KyfkZ
3N87wscuN1h0NrGNIT/XWdC4yiIXnIfDOJRh1H0WcieCLUt7qJlutt+Ayu0YkIxe0Ak6TjtxAe5v
8GuL2xYWEy4RXBLmnc4yPo8FLevdEAEPxduI5l9T7fDUiZwdMCeGRY9Qi76eZw8ufQn0ZiDZ0Umg
IY/zTF327TsZPK7ksnzqEx51jD/bvZACOjLQDLJa0Oo7J1EfWt4EpZ5lfqjnfvZAJMmfSlOm2l6l
rQ3Y+RttXDHaOkMGfPv8grFL1yMZWpbth83r0U9c31ReH4rQZWlEbY1+68fWTSDl9JX/xECTyZ6a
hBADp9HUfWz5RqErKf+0V+9daG6GDWym9asW/HCuRPDxzXfuu8GF1PM8ZRSOPgdWwS1qXZgHaYq+
qi/YlzM7zsMkVEbmMHEXD38IgCpUSJtOAl6e/CUzNOKeE2PqapREZfo8Pa68OzyBX7e/K9MJ4DLk
201/6EDG2zTo2/Fr3aHRDQRXEVsOl8BfoztXJBbmJZ6AXUPgibqge48d6+mOqoGHvpiUcj8NmP1/
neS6A2gOPTGb/bMqXsOucclKkcEql/Mu/l3DZhQR5gZHzxqagZOTRYZGv3hZQUExg+ag0W3JQKiF
4IEX8gUvnZRWMjONd2KL+wJXoCGy2aGtq8rVJaQVIwXW3Aox5vmAh2afXHjdFpJ/6/yQKybXiqmX
DoOOquE680sGpZ8jehmLKCIR9ZOPjWkyeIUQzguR9udGlN2ZFVyhJ10afrbk/5L5NlbfG82oLHhH
MYDpK3MiyTgxOqr0FSM1rTPQg7yCOE9897LD1NCyUk4Qk934+K9jXqYcWEFJKBrJoFXhf/JECHi9
T8sjcK/+jl85B8/GoA1SvbpKhu919pJd+XAV37c1bn9u99Gjv7dgPr41SBI/13gBSe692CbWfCjF
iZsFnZiRJkReMndBQSjeYQ65PzeqkX24Rr63GdwVRxeVtd1nK9dvKkV9fp5DiBXtwjUN1hjufB1U
U3ue1t+f3yy7QIiJigynPhG4Cf8qNP7gjnX4lnoLfMyXgJB/fgDDnHdIWXrPIEIrHO3ayG1pfIqB
FrtF6cnETKpuIEVQQH6Q0CqN5awsdZsqs0KKvzGWK9xP0wKvm5xl1Ih4FcguYq4j2O3/qf28fGrX
gYYux3o52kXfbugSEC+qHrTdau5QxMf/4fDnryIFRVXRU0OadVemZ9EJ586IOgruly78g37bfpWO
Q8gYhSVIi+zJeKZsbnvaYNbsHkml82u89pclNbRgT5msYLDxR3AWfA+wZ6cUEvKWLX38YeOtitVN
Z/mte0aY4vBjywzhuPTFbAbf9M3R1csGrOiLG0kI3HOrHsws4BvaENXckLuf5eI/saYkrIVxsKnS
pagpjhi0L82xnXZ/C95DnI35p43osYPbLhQeXy3eARDcZnPw0ad1XLeC+YcHk8SlxuJJsjkiMEw2
0iZ/bZ7qfikhthY/dELz5FC03+glqDe9CimaKkHADCBVXnfigzxeuA2fBc85Bd40zZ11xq7ixFp4
b1XizG8Xaj4jjfTuoamGGqp0Gdn/i8ydbgbQ8C/itzZHOfXhonzDB79EJqZZcB5gfcw5TcLzFak+
6lIhDhNGaY3HGf8Q/yzM76M31e/dl2fiIeSUlsZR+RifEjvnpb165wU8AsvOXJ3ElAJrlJl9Z/az
4hbhq1QwrC+tbOo1yr3eEShRvuj/j4eeJhsx+nv71omrJPNid2CnpkTu1464zUkPPOqBMejbPLsm
HR0cbGhVP56P2x80Y/G+xREOoKNc/xv9vfuJWeTwNYcjvuqZ7KisH0zKdun97/T3ZeDHMQfr7di2
ExQXgxyC8NL9Q79zrJ3kd7v4Psz87FPt/it/ROQBRpFuUyOTB/hW2t7XzwIfGulyQ5lklTUDxMh+
oBKIPSAp+TA14/uPDhbRMoBCytSq3ITAMuaEDIzC7UH2uztzT8WE2JwRvGcnPW7d9HldxvwW8G11
xMit6DmBACl/MVqsDcGFmA5lMVvRL4UYR8S3WM4EpmZlTpNXHMfEX3ynepCAdDX6URGjNxZ10xRa
40n3dhPZe2sIjCKdp6v3al98clTk50r+n5KTuIrkl9gp6yiLN3gOYAGxrW50tChMaUL0sak/8GXI
iU1zS71/eWc2VyDs3cY3JUIQUNUiVR/CKDTMINACJTbFS28EhPqu9l6ma3Lm49f6aINAtlGcoYFC
JMV3Qxzb+tbI4NAgS1buBMZtTUJ6JiMBp75YdSV25iXGuz6kQK4ncV+F4wZTVgalRWLb5igAxGyT
hyzFXfbjj5W7zK0sjKRIbwYk5dHYtnw4N/TPP/iO5sTChLUJ5YFdNG6RS5QxzvzxZnEB6T1y+3/T
BGQHgRCq521RCJPAPgOTI/sFGKwJ7e8vt58EZ+PcytE/Q1YI2W4XOcrf8wjN9w2LU06y74hq1lOR
YcxeEaC47JNiroaiA2y6bD50U5NS2IhmiM+a0t3Sz+SIZ7mXMtgrwnLOzWJbm5uWHkb+Jdfh19BE
Zla9XdnqV2s9vooPcCrR7w+79ENjrs4LN80/kp+PgQPOV96WM9A/8NhwTykFAkdlyrkpzQVKwnN6
Id5ju3fVZxGKeZQhThb2f7++7H+7YHeqRKTWVkA0+kKUZqOlMK3qYIeaAkv1D+JQ/LUvwruSD6Kf
ll2NDtnHyFlFRLGOVF5gKtICWYJ1dhxIL/636ve9GGSTVsFTT9ZYJdOd1l876H4fEqY/lp9XxVp6
tjeJPxCq1Gd7IVFBny/ggl/kcBlVyF8yrgQb/0H0I1bDtNwXWtH5f7yA0l0dX2SgTSbREE9UC6RI
6N3zPnoq4tIh3OUUIl6R266OfhvpvHUwU4iaDneyDfIpcjt2TRmW0++neyv7X+zka1ahRABrh7wF
jEfdPlyrT/ndrGmNfRn+0PYJh8aknYuspl1hhYNqWzcwlPISKEW6U3QkDpWzkgY1Pvp01KgQBXNp
eCvMrmsNS/a22OYfeuCjjTGEYZJ3WfQtwtLQcMOFtSfu/kV2Yz2+07DdIUC0fDTAQdsz68z3aF93
28N6K18KOl8y9Qghxya3JS3oiS8f5yCzyXse+eGSPE+DRNQO1Ex1rf2/F4UK/8jjNIAo/C9yBW2d
ewUBA8e+r2VXfvV6aUxDnp14vY9P4puQNQZ6+slnreKU+1Di2e0NXDwcl2HGw0D8LhSttuO0TFMo
v8gDW7723hhV/Oah5NyL3aeb5loTEdGJjfZht/FVRCbf2ZMSJVT8zvacpv/0SacdvT5SmRwu63F5
Ax7BASz9izF52DII4jKg8CDGx4zB+C9AbSdySw3rDV2+QS/pMTMCNPN4EKlVPXbsKwPmeKa+lEyK
hjf5TtB+QvgyIlxMRO5eEJ8fRkWFjnw3jRPPcnFXS4rUiMQbecJtRGSq10VbZf7DsqIcHA40iZvX
JeL8eNjgedVnyiLUsHIeuegzTIf+i3lAeRzL3WLBwHaVtgNJ5Tv2d7Dw85efNXM0LPlOKVuuiDlJ
UNaKqxBPWFP8mXZqLBXY68H+lnovWWf4vye2CJAtEeR9iVEwjNTNGc8TawrMc/lU+OCabMpH9BVx
W8wEQMZGVZeYGPVeTKMH5lej255/Dy0fnghL0gZxBjeXXizgozYSVwkq1nUYCvUHfvJtAPLBtw48
25K63ejpXs3CH/e3A+F1zumMI9fAy0oZ0MX/rdfGIldl3h2qjpMQ9QMWvzkm4ZXHEtsg3Pq5XtEz
RhQ9cZsvbw6sb21zQ60s5wI4NJZqDDIopU87yiFUbYCLJbD6u4tNk8PBRDiEGDAfzfUwnP/NHaxD
x3ua1h9J1t2jREexKRRTB55ifCial9v7nXMAGJ72jWkaqFJGBPjC6UJWRKjud2dvPg9M+VbjTEo/
3cU0ka3JWxUyTLUgbO5GqONirVZD/xRHO907cBAexJJqg3yzc21rJlE29IjEjf/5caiAoLWg6O7h
gShMpKMXTbOlHX/7WJL+Ydliy+S/25HpnYlIAnGKuh9Tz9MMWPrK4BkXVW3xqwWgvmv5ar7n7pnv
cc2Pc0wBfJRlou5Rv8XjASvDHYj9w3m0aLE67EnoyAyXd6hbDQ480Za0rQwvxshu/u1VRSMIMrTo
y8xxFDfmBu4bHAIgXJW6qJaC+9rYXG29/qnOsyRD1mmY12YD8+Z0U6VAs7mc0WMM2jdiiUKe2j0H
Gu0XomajkafislZoQ5wHX6fDq1zgBoMJ2nLqY+aBcxsNa8hB6pj7jx6k7V9/GonJDu5Bfzlo3ynI
Q581pdSDkgXenIUIp/kbrL/6lbA8pzxwHcirFIuCfIA8/mf+cyMs6Nxcht3/rtNa+u3ezXhEdYLR
6t/7UUwwlZgs+jDvg/Il3E6BP1sYsQ8t6K45VUJ4NihXw4jdmvobZNAg99iPU2LYpuOgZeqGKdBN
R1w6oEpeS+oOeqn2LB0byjoHkBNBmtU1S31LMzwYmy2sztBdweTZDC+rp4W6/8SgKkYv3vFjUg/U
40AZoeCIGmGAFPoyg+6UeUfm0AAKFa3zycUVKuO02X+aqHnQ4EaD/1Mm2NR00cd8LrZE7B4y/fgk
2+2zjQwmnbeMMf/m7HL+KqYhB57ewFivx+Ww/T7qpdOTi/3M0MCzp8l5X41ch9UUtf7qQN7NFiQb
UgoCDD9FnWNgH7/PxaWxm66FO1B2a9C7wTccY8Y/GoyNMbSyugFrWoMtjn13jWXh6OVMDOfay0wF
WAgajYHwWUAT9Lem3oyI/6fFJXd7rSvzdEgqP06OzxJ1e1HCXkE5HC782yfkgywvHB7xpyXKYByO
9vACDjX/1DZ31RSX4sbfWWMabPuA5bhhpN8jrYppIQEqk5VuJQLix807G1E3jV2nymDKEBAw69j0
jE5ro107z4aqjo3tMgAYPiQvvUk92uNL6PmnatKgcmPc1kz8KHBWgyV9ospJ0HZnUo4+3OABa83R
EKL/dHM+z8VcqWENdxicnJoO5XcNejncfkfBsPZgJdKw2Ci+36ZayY/M/TIvGSBbYe8c14HW36wJ
pay/dTzTKj1zOOSYzIF+qz9N5NCAcp+eIuV+mkgCyrq6oFJ+6YK+VnZF4hIpiIwsVhi/x/1ooAP6
99zF9yDJvGsRjFK+ERHuWqpVWFK+Af2Qt0P+pr/VpXvnWqvZDF9WVlhLtuNKQtsAT5lcfJq9eO0b
HENsCq3lE4e8Z+i3NLwBqxB/0OfyNhdlbXP0yn70vVh/e4VrHe8v156mNZNi29T+2ArEyYH9o1Mb
IXa4LYVWZZR8mkCYpb3THDRFiSxzMtc+y3oxfqMzoz1zqF50ZNbKmQlMjcdwlC9sWmd/kF87IMbk
SVNpVTORaPirvj2E6h0uqyshDAVIRT4jqj0+s5GPqJLzbBmfSe9o5CfgRHfrXf8KGG0QqTRKY8FN
2HiTJ8EpBO+CtfdPvKDBmY1s6OYbnyLavcq7O682PQWhZja04a/IKn3mxt2DFXMnjE6xJOqtpmaX
0Sl3sc8COnMjIkuIsrMTMmFy5T/lE3oCE4avVRcTrdkKBnK+hOsRPlqOvBVb9O0qEqr32O/SRLNk
9+mxrZ5b8KA/TbtuLtVPVytfU1/GxAnMtjneEfcxg5f2QGZcHYnjYgLFE1C4pVl0hv5JO/mtd7uQ
uzowCp0ohTfH5iNd66vrChyCymFU0PHWTxyyElGLExvQylRxK6K9aA69kFONQpvMBnHT/vLBkcme
m5Zqqhq9e4DjVdGP8XRez7pd+4vtHSFY28g/Gz4cy9nHmu49Ai4yMeyfiayIlo+3FkHgeKMdNjZg
fcqtJJfaesS0DfG0lOYziV5I5vfaDIMKvoZAO97TbcBoKPyjfQU6CaN4/GslewOHbAz4R7jK75q+
r9kjxKaujOzWE6mScdqW8Nljw9OchXrT/XGF7IONp0By55qJfBfmmY/SVi6zxAU3eWxO8zkqjiXE
v0mca3fMSv/3NHkBBuz1DC5uKWWcWUtEWs3rmvmVmo2BO3wk5KyiJ0CY+sXpIPJNWrJ3xJudFDSn
TMYyN/A/7wOfRHVFOsty+TtKC6uxTrfJ0kkNXjUiBBbX7iixRfUphj/40MSnme4E9tr8jHavoTgb
RYnN7gw/D4fbYCCxe2wAREP4slUYfWirJQuJIi2qfaO+roLePQRfGHYZ/yEjw/fXdOCTbOaYHF39
16J6uCwpmRNpWofskaFQExftFPWNWXnQ3itX4y8VDsTqXxpGpZ6PnIzBahL/NVcw7lD4HRza0MMP
sD5UNgFtMBJ+tgYgHRHJ14XFt+gtUoM9owJTgp3tOEDcXhSssjiZ+3HMXqw8EdA5TmnEEwiurKjQ
NjDHgPR+gb2fK5fa30tTch/F+DMrHHblzvzXRPRuHZEpPp8zQKni+g5h37AuWPoNKbCuKCp3KPLg
HifO7/0C4akZk1xj0BKcBBGnTkNxf82V3sZ4FiASeeeZ0Mg91N3kQAMk8SGR5lvB+jVBjnfw/fck
X5sLxrbu5d2jkGuVwICzSwYFT82rQopfDjkwoBRifDrC3PN7QTs6OaT7mOMelcXGz90PRqa8XYKF
ESbXkxG4RZhOGq69N9ww2Jh1HxtCz/C3Pox1bYL84Rh21nQWL/M4AdqPa3TjPy1ByNeKOpblHIIa
kRfhif+m/XCogtYr/HbQobo6AV+D8gUoFPRYCWi7e0TE8cy96sCRD1CW7zs1um5+WCfvQvahMOtc
fD1dYsv21LTNNVvv3ukKu00rUU91ZZhh1l3kM28ytkOOA+mn5MKY9d6lHnxeFQym1xPKpeGJlbZ7
lylllP7JygRK3g/ct7C3WvjdrkeNeHTXhePY11psaWQc+SEZ026F+r3sDa23bTHSURZyfkDNy7Pu
2i47LUSSBTgq65a+JVVOwbxOriLcX0XF5KMFVKWvDfJSqrtcccPskyfG4OJSb6dswrJvgXzBQ6sc
YipV2Zs6YUsaPVMhQalV+dadQOa4nH88webLDLyT/gr9O3JwEifho9t40BQQ0RJtqJBXixTY38AY
WUYcXj4wIFUrk7UlAHMS/I1Hq6coiuNfMe46V28800njtV2tFFOXVmWs+qljAWH+DOfx/JmRtt93
zdNDtyrqUr1md/mvCUuO03HpdigqT5BBYp0T8ezpAGKZf/68fxD668FgiCFkXiFdliKuay84tQ3M
XV/HPtBbNA6laGbNccSXgbLeg8MMJBYmJq5tFLh1DGtBqBFhuHW4VEONCGUIzxHhmoWpz46QTHDR
bzMpouV/79M0YLLENoP7EePHS3darLbR+eiR2L4BXcgA8r+g6OAhltk91CgxMGx77ht6TAFouGKi
V5e4mtVgRHbx31qdBuHqoAwaX7zB79F6O4I1es4dARtaLZGvg8RslJohQd2/T16F4Q+vGLw+NNv8
ZXxfynHRvqzeaYOe/eNmR3Vrc3KTN7tYhzaNrUu0l+1G1uMCtlB0sftPwvjxOMcM6WMno//Btvnm
Kqr2IiN4RjHws5rOgFe4s9nY+qc90cqhPB0roRIvxW/YlzooSsmNGrbFzpmJEd2C8zLxI3gvKjVp
wcr58Ko44zgBNKMp6792J1hQBBUlwl0QtV8su5moW125o1laE4uElw9Yw/VOwMBWKnzV9q6HrPlt
l1rM27VMy2Hh/mGskaDkHj9nf/ATz2qal+wfHMxuNue2W9+9KeRsq/D5+9+NrMOLE/Ak2BeTGZge
td2tzAIGw6S8dwYG2ZymzprdrVFyPYjPoxMYhDuNjXhsd7JXrRdBFVvFAGgFHE3USRxsCJO6is3W
fOSf+CD7hYrjEwTaijTYqvJgBSQ8mLaorYf8nWuSCoi1wuwNlS+SQEprCza4rhxhyjlaiXiiH03e
BidYlto52mLmm4N/EaCSDueSqBna3hjs8pV6yeFa83R8IVEx/JSPl/nXCBJuMQiq74JBSaWtXhcf
yjMDqtCkFX69zCuotSqKpv8Ld4/iTFzfis1P3GqJzupYngkiLTGAqgLSnnFKLltmtIQUlj2sS9If
v6Mq/Xdgygif1oB/wPgcyILN4L8HJjcy5s6M5a2I4AThxVpJZdorgvMqigWA3vVYyWLEhku+s4xy
+rNUzyiAyfMbFbhg+/9eolXfdASrxCk07kb6FkUvdtxgWxDNUNzRh6RSC2uk5Dpq3bm82qZOheT0
1tkhHO/nGHbNgE+khxsahShb2a9TQWpGKzSzfr66FqZMFAuRVRmBz/A1AeMDHaprBOAyaw5N3iQB
MTLP66pzElBY5+6hRsNerljBsXmdrHJQ7Lu695Ubk89RKDoLc59Skq425pSOOQDU6RtnP7EZx82C
W4R3GITkLELBsCCihAb2PT4qXAkX4n40RX/dOJnAKzcukO4jMCPTAe1Jv1bsYizd8SFSJsM6M7cM
pSp+kco9TOdEfKg7CDYhV+znT+U9VdQreQ4n7mYGjxePGl3I4HrwWAR6UvVuerTlet/Yd5qzGdi1
sqIZJQsapQIYbv0hHtAWzg1YpomTOC+joTf8nwwgHwe/tKSR6xbbVxchTFWeXBcOQrWJMlxD+Sw4
dpv8xg1R24tszNrt+nT9C1E/XXWKYeAbYcbM680A4aPo/N68OCwLV/ZDBZnBaNm1WG9BowvJ7g4J
85UhZYfWtwcncMl8vHYNF5dp51VpZ1TWmJu01wfP/p9e/1DrvWW2KsDL+xsTRPadtHESp3Z3OmBp
3MX8Gdqb+VyKko5iFnNuohWsBbH9JoP1v4i3rkETMsYK38IIZuGs+PPc7ldRJmuuUIBbHfiBxOhj
5fSOE/scKvAVlaiq5K55jILKfmJJdLp+QngdJLGwFIGTaNvY/7b1pXgV6bdmWTAtOrgkWbct+L6G
3vxNLxx/JOuS6YiekeHKkU6RXZY8iv/bWK9aZiM1yuuwSSE5rW52937tq5zsMc7WxUohP7tOvZnm
eEH1Vk7ncx3OldN++55rtRxtcyBOpr/B07nwNOB/+SA92J6Q6eY4F9PXCXq/2Dv0HQ09MWpWHzaH
UkeqZUFTXD6J/Da698VUNHV4e6yva5Dd83WzVoASBF8A1+ShkqrKLgZDV5M+eei/xMY/neONB2m0
zDObSNyUWh7zBUEmuN5KyxwKc/6mJY0sCGPopWkCuiCIUWKp/o9aIILHOzTa7Lz7bB44+h+QFhK3
AHD2mBfb0as3MbdYK2XJ8HT+0dk+GRR2Ezfh3/hWvUb/v2vm1hbTlE4BMy1WXj/Km/uw5b5PJPmR
bbDAVaG3Ozu0eEuqrYRcoUgGKJcnVpCnrS3dkItvIIad/Kc3ckQGKHXGXMnIqZjKbQbAV6idkmpx
Ke7xgp6tVeMNZbRX8FfnaN26Qqrbnu3QHhWgAqxHbfsbZYOxv7trxpNkkc9QTPNIT/SXtPlkw8KM
g+leguSAeO9PiHMUNPq1hOsly4u4LXMvyaC/y7QpY091Ga2JtBfivhOGXoJf0/ymhasCB8PJkNpF
XfK6uBqocxPIi9q1P++zy+v44ppAVOC3WBXRSG7Nv/0i1M0e9DGrMTN0xqS77P1Q2KxyIYPNztnB
Mk/hlk7B8pPRFBCsIZi4XPhOM9WhIubZx2X0lVUFfwmTUiAG+2xSkfLvhSe9L7a2JRrXBG+afdUO
ZyZRwVwoCZsXRNH9885fxPM/Vk0e2sPG52DTdpr/toYge2T0w4lSbPjM0azMPF3u9pjlhijUO/HJ
YAXfAWExcUPYVFINx3VoblMyW8KdB0OG9Ln4gO4wi9uDJYjWflT1oqqKDIUQUGTa07drPCLcw2ma
OOQFUHeAj4DdkDWRMTRnXemw+/uPIzC0g8+jb79htiuJFOMfTmzdsWF2lq7AsKJV8A1AbGMPQ2mu
P+thAoA8wRxo6V3MwJ+A2bDR90prbYC8hgJFCFX1JG0I4s1M4T4zTgNjJMpJ4pIlXuJisfInq8Nu
WlVxhZ1597dN2I/YUMv09W94ow5xJxf57dX8fC4znMYtqKydKYD1wtn3jOmYUVvP1WdDNtxCCjvF
pXuek7kge+mwkCIb37t+JrNdCqCTEf7kplic7i9lMtFRTsxP88oPaoQ94WKiQtqUx8vuhgRqD7nR
B9nEED4Y9Cf2Z9ENfjQiNmOH0E4366LQKm+QqzLcmBZL8dlQNIaKktMfjaxqoutobWcoa+xsCziX
ouHtfixmYDq6b0y1wint6kIJHxPn6P+mIkSdveQp4eDVQgr8oy5Da/UQOaJhR1TIyb/kCnHD5FK/
dkAQ8PtZOBUAxzPsnUsK3+XyKRNcQMXT3EOk0Ckm9qJIinjK6vpaqRYokF4xCghoxEGMCU2PetuK
tTGNVLQ0fil/URrmmkxKoezaBQ60kDK6XJ4vWHWtkfU4S4k/gB/2Yi/VE3VSOrE8H1xBF0+NtVi0
zqF3oDnUFFfvMNJP6YNjRlI5GeSkdZ+2iQJfwAPUF/9eHFh1xMoVo2xAiHVITdthYtgUtrLlvBDL
ugTOj4cIwnbXhv+MzC0kKkLmCrS1oRxL5u5sx0xSJLNWbF3iPe/YLZckkoBJtT65g6JyK5Mxvf/X
GT3/Th/gTW32OAtzZuHB4BeMDJjD8EMOh9J/itv5Lhxj7arwWxYhWKbWJkJkSu1q/pWMJg4YjCDe
Fv5zoCqw7rrWgb6MYO4XvVUOGe/BuPs4prX77HuwZsigBvU5czfZXxworkUqrbVtw59uStw7dXIC
+nOttoft1BRRdHmOoBSjd9p0hlRwIeU9PSyVkCVQrdEDvR8V82/0AJ+HLM94cZeKQUEsLKRVJBpT
5h9pPaZi1/LdZKjCgbWNwEJZc6r9jmm+BNXDRRSW+SesduqJOWo1H558YGJIRioGaymRGDBQ/3d1
9S9d2JKXHmFG//0XxCJSirDBCmTEfRyJZDY+rPUvX9nkK2vrxCf5IP9WCSqEpUNIDim7QWwFpTD6
HYcRA7E7BlW6+6zemVxgPAL3MF5uzFQxtpaqVSWCejE5oJtr2uN/Al5L4pS30j3h+SYN6iDEQQPA
bsuJC73vRFq0k4skrDSb3YzkuPZig+Y3ysOTal8dJn+wVqcyaUvbIqKhv0fSuIZQTXzQHprlyceH
bjhCVei9JzeXTMR7UdJuEfCWlUe7O7V63OL98iPGPHMwKD5KxvW3of6O69TeSnWY0lpgHjImfhb+
Et5YQp2RgP5ktRtdvstnfCHUkksPKR9VL8or7J/yxmIB5H5tq91ifBQHvjtyTD3WoJXrY5Eg5iSS
IuBikKuNtEaNw2Jx716SSdA86Vshd7NMb4RpXPe/Ergd+f7W5mFA/ko05S+qPN6hPbYF7sWivWm1
PgMvCjNKEhOMxfk0Xpt3lEcFcYzZM0qPNYGsgjfRxAykoz2jbv9JlDvMJcbsgHj23OQkA3qJcrLK
cBzJ/8yFkcU30bplW4GHQisjtEnMyZH8sxlyfVlB8SnA00ChJ0E5OIpq5+Wv2Z3SCw1L2kc2SX5l
otJj9g2WoEGVX4r3sAUT6LdcMUSR8YaB+GT5AUAGyncNzD+EFJQjvMo6HvXAa7UmSkHkTOFmPzfD
QdeiJNFBuTCH6UiKOQd7uxaDKwWwGnj0E1VxuRye+gWjjqNp5Kxb87qySCEwBJBKkN3REnKEfsso
oHAoRg6POe03lyYpyvxfIiiKjHdWIcGqqk9zZpfDyMdOJxr/1d7kZ4578pQ0dxibYmaSDSRTehXQ
7ndHzhyVUNejSAr4ya9ljXou34bQWWwHosNS38gPcFW651UTqr8CrDTZyc+hAyIhJwQU0k1qcQeo
IUCR098RTWTmKfcjavVyWNgw06E2TxuztiilgDagTJYFXAWaOvgr4yWsjOMG688kdXBUgZCsDz+S
kW/WIqTBHigCof/5BAFxLA9uL9QcTkjBH3Yqfyvp7elNtsNxn+Czs3xLAR/7YsGy24QH9G0yCgSp
twfj0cNYBoT7MZkJK7BIHJQ3dJ5i6e5Dsj5957YFnRohLh1i8M+aNBIdCzrM1iadYh4ODofBMr/s
v1bulQExGmzfUFiT8+jsJqZdGeIvjfEXBTBBvMMCTnZfQCiPpk99tC/UcA9UVOOrwpk1FndRP16+
g+FWWgWsJKby2me0ArPL+gHlxnmoxGbJEry6MaTdmv72GqX41lQ9tlW8hhpJHuB06bQEVejcw83H
6VWgOQb/WO1DDwEJMlT3Lky1Y6mfc/TEjqwM4k1D3J13rU7rsR/s53NJ+gwN464Agq/bwH6TU4fl
Gi2HXfzrbf4vxw31L2bWzBFPdIiK1v6+L8upBKRMkLDWR1x5DgVtGouvTD3nBOfbmNhgvKBzwiZO
BK3KRSgWGeR3XBEohsFbTVvxoM+EqoWNglDLDZyxpRy9OHGh2CptocSL0XH21wdw7xaKd8F2z5Ac
Tg370uhbSz474RBclSTExQPFEQcif6wbcepjRCqhq/EaEssWcbPffPwh2v3A4J60M0ApvGwzMwX4
1cJEFYmJHgDYxSYmItf6lgpn4OfY/M37UJOQmhTp0j4X4Q03jOpnqIenxOek02JkFLjPtGUWMBJ+
N38VLanZRt2d9b5cOMVQfajQpnbh9bIK8a200vQ/yC+jNyNcshdQW1X3qGqqmCqSr+zTmzZbl4rd
kAmFxAsm181VxvBm1vd3KtRCz+fd27tCq9h41SPJZV09DoBdybQ83vPM5sliN/Aj8oQM2bdFiOOo
KXXzCJpJlW5TGfG4Dxrh1xyhlDh8mGwluaHhE9slWCQ7ayEgjRGeqWTT0c9RSjAlxFNKc18DcFjs
a4bvyhlJ+Q2KhPWbcON42iqzFEfW4CC8NrCuCIkuvLhdF8eXtcHlnbrHBywdPIJ4QD9N8FbWQnhJ
gazao0jDWtTv+Hc5ub8Z1fAfUpGPlXPW92zOf9ddKs4vX0dRK8fWxz0D95/82qp7MbDqkvuhO7Yo
dPQWs+QHDr/bUgJSmoZR2Bs+kRFLgidsq2S8DldaRbUcxPk86k4kZmcwyTTM8Z5UdHCwO8ivUVM7
lvZ+OTXZFdYPQ4CtRMZxt9Jjapi8gH5dHWC5lb704+QNN6RXFzNCMcPcIHLeGoYaJeKIAJpFquU0
KoFOeYd79Me7obeFsU5BdtzpC+JR5M9wmeeKpt/pG6FuG7qIQfyFDSoJpDptqEUS7+OY+dxLo/Ah
frH7SiUPBFAt+p3kHGapWL9hr/JcLrhbMXHYRsF/HqsjtFg/sXaa8w6I63+GWw1SZcDRUxCAP3mC
NqEg/F6r8TP4jQ1Oto3AxSTqBBILRfeIBUFrXbgdYRR5/8aUUA/YYGW1CDkqKi5nqmARTu5r2Gak
kEUOmF+wDQ1mexGv3uWyuGSStto5BLO69RYaO+8m1J+sa5MCDCiQKbjufNpUTbYlzN03WHeFVXLy
AE3YbrNJOGjgbVWY/kpri7kedlmQb4crWSwDZBePS6IyQCI7opf2HLFMnmi4mrqwYeZjkpPQ2JkF
VBbKF4ZGhxegrEM4+PctredlrnUdTVMZrIDiTi0EP/AlX2jiFwEEaUkNJQJv1f6Ph2/A65vcALxG
dAJ7HSxXV1QdCqFGMuLCF39qEOZ0dLdYVI47uc9jMESvOwjUt3rxL/OK6U2wiq6O4rkqxzvnGDul
PEnwVi6sAvx0KjC6vBP2W2YN9GavCUAUVQoFGwxde52ys1Rrnielm1cJpu8JPrDPxcA9kiMeTPqy
gYbey4d9nPJkZey1DBnkrdYTdDELkyMWNZ+I/U6NnOgBxPZ/ZMseFrF1SlbBHQAEJNOMjZFhw+ig
9Od7zd8ZiptdGoZyS/6mWmnL+N7xlTRm4mgFa4u1tEr5Yu2oErXRG378Dnp9wZXq456u7IaQMU6N
f389+4s1QHFyDvfuXHlJVcucOjVhRngdAX1T2Wd2mEQQX4p8CKy5YBrJKcP4FD/2qXoINjHt17OG
Vj1sz8uMS/0aZATjxDLH3BFNy4drJIegZyF1ZB3MuI6MzsqqUpN8k/vk5Armpg6woYvrPeiN4ekz
F9J1+3ZtntP01xk3ZZBFkA3pGfF0iwk+lvPu9ysnPEdHPIkzPrT8YgPF8b4FlC2/fnOzcbAMD4St
Y1xCyEZr5w2QRN4wP5KPeyUw3NWozGW3diGjaE4dKZ/y1LZ2ux28GcEIQyyt24hBM23qINeJYwQf
3mQcz7OYM0sPPRhi0aQ4EEZcsu0IPF25lQcx1ClkR2/w1+GHWixcHYwVTOzKFkwNdzPGzooNygpe
Uh5OZT426KjElgGpkRwhlUfjDQtuNPkhSq2KcsajTLmtyAIhDjWMMQCU+8Cpzc7b1jt0qetQtFJN
59U9XiPGulwcu017h4TcmDAcQHg9h2svWZ3DwnfTiqACMtxTN64t0lfJsKdzyZd6vcCo4ZOQDySV
38H+s8ZLs7KnveKQxK8yhXlDBSvaAFNys8C7DeWZv/DKEhXS3725cAjgAvzgzZejAzkJ2AGA1AUU
6XDD8JYamkFyzpSF+R6ChQOLjavu3Qm83VBUvN31zW53JLRYOzri+faFy6994jwuYoVc2bIbCtp1
WwzQLpCOWZtGYZ/XlqACvEigIWPyPqlX3YtvVyyy5ng7sakbFuyEYEFe7JRP85n6+rcAB2OFv+Ct
9ck3udEJZUIJsC8EbCAb21bkIBRuTkBkLqR32X4wNlOPPZJmmE9Ly9TSuOlAoLAC11V4pkupab6O
Mf9hExadpXh1PaGB2iEMsoAbNXVOhfdb5t3N05i+5wdSlHiEyr6P77Bu49cwI0lP/zbazoKCETXV
XGQpdIuBQR7N8l8WZoP4P64styLpJc1J4w5sjrH4pSAwVVph6rvHXB34PMWDDLXZ7wd0CQFeD1KC
Dvp83t3G5Aq9ZN2lqy8J/bxbjuB8+MUbXK5y5BuJMujUwHuEhj1cJWBV0+kHB6E53LTTFOJAGrlR
+Nhsbj5SQUFoHrWcmEUvsp1YjNuBC/ZJidoKead2rLzLVi+dPUyU7axJmDHW23Wbt5J6zGkHIoMl
thTuqZMM6qNE4KWVm259pZSz41iXZmGu0HldWwgvpZVcx+8g3MqwbIiGBeWMapvBOGBl2s7BU6fj
DnvFaNdGSIZ7l5IAM+L1G4P8XKZ2MT8GP/DVQEK3KmIvKwRrvjELyI/uvf2ZT3KzXMyL1E3l1eoa
OR6ZjRVpafg1U985zJw3aWtOEYggEk/QhH5eKcZRJlW0LrJeeLsyF1ffCjQ27A3dI9V2Yn0iP7/N
0/Cfsey+KUDpXU83wxg6PIAswhqgz5Vj+GiTkBp1MaCiaX25cq/gk9l7Trs5NiFfWorBPRmaF3/L
su3AoyDllw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PFRvViteb/axbSedtxZdW6uFxEgxk5HDXr52ZztCJxWCKdDmlOAHnc3JEW8CIFtzmjKOAOcvAPod
vtt04j05Vg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
YifkGv+JrzBIs/UUQvyB0aR8cJDay2lbjuAiS5PNdfcYrIMzhVbOG63ypMDOSCXjoNDh2LVGbHl3
ta/Q4WaIkhoGICqznMByToK8Qga8ZejWW77ntM2mnBUthJuws+YtgkUtEsIeNEMQMJ90DRm209bw
ea6opZ8Y3fuPQ0Trs1s=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
aguPFZ5LICOCYhEOysUisuw62lqz444/ZwFbsY3EB6+W4EImuoyayyhHbBUWgH73pGXi1zH6cewr
UMEBWh2iyImQzFkNLq15CWJ5QKrOG+vqQ9+7s7OhYai/OXygzdGNqfBbWflfKnFsYABsglk0q1cg
nvZF2n1Fv5jbuOGonGuTwaSeD93Up1SYYyNP+gr2L/zBScWpe07CQaHmBcnw1l7Yb4/3pUKs6jyP
o3n9MnVjJLqZcqpe0oM625sHf8uLhZ3ts8a2KuEmIf/n9YHvxmQOlHsUh3M0ASAhsY/IUhioTaVt
3psEsqATN8vqn09+5Ka5PbPz4pgSFzUYxoGmsw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
crqbnapJrzsKzLNb+AtGmQFmHNUJXrsIeevTjReFKq5qDhvhFDl7Hn29zbiGy/FzXhop55wp2Vpe
hc9T5+Xp8tfpDfH+MaIUngm3kTXG7Tyn0ROLEqkxxG6ZnPFxQxd6OTmcje1mTSc8iXYMXq4Xlu4Q
T+dmUhClJm120LFfIow=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
l0V0VHPXtBRxv+IxB2NS5WXP/pkBGK5eRz5mHgBmFAd50lxLN3/8MLKb7uOd3jzpJrWuPsMCEyNN
cGgnfvx+5gYyOFoj05pI/N4xPg9R3cN+yoYh6BXn/02NA8fwnXxVkOb9BWSfJRTudHD9rHY7NEMD
PWLboIFjDW9sRg3xS+CJhpeomY0T5D0r5wTSzPbYgAg/oCQCVvZ1F0B0BdOstQFjgJzlXN+y0jAp
nA5Ym2Tm/kDS1e/vGtXGMdT4wohimviPpQMWQivqVKADDS5qfrGiTWDi8oTqcngYxT/gi9MXpa2X
/WmdHyWT0iwKbTL+j7n1ZfYJZkNhd5gRrloxYA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 31072)
`protect data_block
hvgeB4DrwL0gZn2gxtaMqkp1oMtHkDpeGQVeFLRN315HgnUQeLxIUKoggK5HoRUANRdYjoNNhh4g
ohzRlV0hahMKDeYCg8azoApOp4p5ddzpGtdmSeMWycHUekdciWQR6+m0xo5EdT6RDXFkLoyXzGQi
BaQk/q0Baa5jJT4HktWQ36buMb/mtajxTm54IFd+tfx6oE+Fi8Iv1hDWiDxTdLGhqmawuCYvlE6o
Lo8XVkD/DCcitjhIriYvkWlahnMCatrn/urMuz4XmYboyJKlvn/onpnOmhsVF13y47x76JLbY/xq
ZfU4JX9KOaWLub/w5MQR01W5vEZRt9syglrSkhwjG8MB7ZZmxoTUcfMu/ncg++Q7HcmAmFUxAw8a
f0VrIXAh5RU+47zUZzrDWn3WkqozTwvn5MTBnkxx0w4R09LOXpH08usKO4c4syW4srB8epZDsAlY
NFXm9dPP75L5wwjEZjgOELMBDl5cgtIYuT4CpMNOx15RvStdOw0vRy7vBySxEH5Y6XkfpNZ9R6w1
9R7SP8VH6aAKZRagpKvxzpxCkqKi/tb5AEydcu7FaGa/xPLS5iq+6/h5YrGmRzbQRv+zxGu0KBks
vezy6Q6dtyOFcccZVdCSXILO0Eu/f/f6e5IoyJL/OxMf2Wl6JqwaMhGLvU89E1+nP++uXXHFX5ho
23kJfOdg85r013ZlKIlg5Gl5ufI6Dq8xSp9XSnRVOy06zgcnpPw1TKO4Jt9CHMWuCkDwYnWYLANO
LaWTDB8Aq8EQSt6Wf8rbrmsKBszFGUCk5jVOoqqspAQlF6x87O/yEdM4EgPKzGpltqocI2JwNU2/
XzkdU8gxMdXDLpwmB9GpHHzKDf6wIDPEFbuej81wDd4VEx6I2Q7MURnDlPutLBzHmPLcauyVY++p
ayXhAdzx1LxbbsdTu/Ty3gLcxo6ZAZe6RnAC4K/dENeTvE7LErJhSigafh9rUo/zIAjQbAZhM+KB
KxsaffDquh94U2RFWT17GrdrHc8LSDDFPZJKIYlceKgBqnr3+8x0MlCzLDJRPDYZDRFOGNGrAxTA
/jwvU3lRp31qLbrEgI1C6RJKUklx8802BEu31mHoxAjt5vvjEYGW/SDjkj65MEbz33FQbnMULE47
ghFf9i1WNhF0UFNpkDncRBUnCnA+J1t4i2U5xzkeICAjMLdvQ01QCBX75K6jAqrdV9Jpdr6vxlhU
jZlp0kU0hYiRRmG17AXtXTQx6ImuUf/NxAXw04KY3kWlCpzrI7H5GPlDCwANrV/TmNlGeWxcFgoL
j/H24AoqIOy8ICpluwRl6Z/mDyqQkfhnfuVEDPzRqnyJLXoTlvOkJDvhcH8gkXzxZnXvZkfbXllT
bjFB7FYi9nRyxaaV+alS/clhYdHkx+RGVWicjDb0R3vWci+wO5bteB7rPhVQ8zOSiykqhRWbHXPl
5yk0jN19Ci+acHTAqbaK8LCssqmJazIHE13CW0YMUjFtw9ubKVJyggbgTvAJlmQLEHWt4z4CA01Z
908winrsyQQ20oKj/tI69RomlTdFUYAmtFwRIcyWNX3qM7KCtR6mHNPUi1ktPO6WTJji3fFRMB5o
iBQHZt+SYsxFCfXqVHnsZH9bhZCCvJuT6uARcDdXP7aTxqc23rBc0Y08QNxls+T3hJQiabClUxd5
Lv8lYETpaypgAR7RwpMseVugztBlUEJDnXN+zSyFbc57UtOUfM6vRS39aWSjmTNxbcxR9E45gsPF
IRrTMvnPzMIiRWX7iOdrv06mEnYU+E6KnH5IUV5veUIjC+lCq0vQKqAifGgzuqVWSr93tyh4uOuR
rUp3U5c2ZgENEMmYpth79NCY6XCTlyN5B8O1rXRMcens2f1JnPab8XJS9NQ1kYlg/1FdY4iIs2Ej
usiAEmcfdx8TFvKwt39uWag/eZ2sAabWNbQ25P1DraeStUS4CIwNI4BiYZPZwLh8L1AqL4fLW98s
nKlVTNM//U/vxFlX9Ig0DrMtxJzkG9d3a82xAFjCh0Gyg78IkAZSclRJx+E98D5jTfb/lqFepwuc
5yS2deyIXlvYhG/tiNDTvuFv4RJBvtycKZ7OXIOtUnztf05AJNo1Okb48LR9QyGPTIA4cZcs9yYE
5xdMyy7v+ErHHIoAOND5RO9RLmqUSSyYv5GS3zL8gT6GZKM9d2tXSH1SBNYGyhzmQZ3KrO4kWY4J
O2XjM9MFt1PpiWifut6dXRlMgCtX31fSZwW8S566wnFank7QoH2OpEq38Rkud4ItIY8NCEbpT4sN
KWjSIVMMp7HxuzkJ6IIA/3BcdmPTDIGbU0OAgA2Jfw0Hea093jyPSWRbMLPzX7rCAHPLiyjo7M8p
DG91n5q/mqkJjIOSYgokNRAiEd8YaFm5G9dHeUpBsLvrT2V9x7gDZ8dVce2xuDX73mnspvyuwIcw
8WP8mrqOmZ6jcQ7wB8lfWnEbgWxH8sk/6AsKrEOHykuDUsSdGBrik4BuIvPUSx0r3RyB8y6+Lnct
c5F9NR/OMeYmyUKog/asEhhfZk0uAN3OX+lNtMeQQ+Zxz6ARYSPJV2dvTLl08SvO3f+vSJaBId+7
VUB75Ed8pi6oFXt972rBJCbeY01cDgRgkYyxy6AJvVAVRF5G/iiAe2/aPcEUkH9sNkNW+3N7Aabx
YKPkngWwAlKqsWIhqqAil7nWln9fXBHppubyumwZcgW9Uwp4WFzAMV/4BCWtBWHNLxdKco27FqEB
MprukEoTY9nK71of0zj4Z4HeljIq81myefeTPMGl2Kvqpk0cg1UbO1F+hdc6kbapE/lHm+J1smdU
iKo1DtDL4RfzJdiclhYEonJ5H6b2dLevEJ7vAzj7QHW2Y2h2s4HFiokHewUlZXqLNM/Up7rTK9MF
tjKRkpZMKCYPLqD1jVLq4zxS3EZVvEMK5eMRqpQL3XjJqJf1QFQ06MRFlAqtItGkdzztVsEOF62H
OUl13hrq66hfJtS3oP32dFMjEwuGpNAYl37TN144DujOIXeKJhfngbFYk4sOpsCFuJR1WYuywGhY
jhwh7wIVY6gFxcpicKg5DQ7NBpKVI21KBeQcpoYLM37yARx31+ywgamlSPNGZRZ8kdQdgrR1yH/8
+u+gTFo7Nk4/To3Jp9CNyQXDa22+PLbrkbHx/L/+IerJmp4S95NS0mxVJrkNyyNwzx1l+ZXW4kcZ
evGfvM5YUkqIAjn0SZ0Xn8ITEpTca56hHcWJRoqLMpCM9++o2VoIRDRCl/B2Yev22Tl49JE7R9PV
pFgVumOSotWgSJlomHWP9yAmYMYgtnepTwKH7WKWcOxNpCHA0R6Mb9nZsi9/mHRzTlSoSqmD1CWi
7WfRG0t54G/uSsl+uwZVLQvxhQKAKACyNTw0dQlIQckHBX6wNCuMnOKIrlcoIKnJCPB0XnTs6cpl
QN1eCZLRswB+DTpNuuTMEkLkDfe8I8QtT8fUZuzQQhW4dHdHVy/JN4OGp5x/OwwYX71ZeF5+GCEa
MYxXCeGfmh680xUNlBcloSWsZK5scPGv8IRtPxcxEJESNUlVa/iuN75F5Yyv7pFpf21xGWzuuio2
SPboEUdehQKqFkacD63ctdjvdhF6moSJmFf1njSaae1lbLlcMuStAcVnQVdSr5f/ipKhfbUd7jQz
RHanGAmra7Cv1ZJ2Q3F3SKPIQbll9ID+CDRPKD9ImyT0QHskrQ9Ac44p/jPDbO6EU2uw3gMS09rL
lhkkZFhWQfl59ZwH5b+KwIB/L08QbUaE4Aa5AumWiIffotpp/4n+Ysu29wZ+NXWwV1jMb6SjuFl3
YRKzTmwTimHNU2/n8ZF7HJlfVg3qP8CfU4TggTJaoyBh7pnGXxd7rwUCCh8k5b8n+fXUR/mZ9tq8
G9OM00xWTwYaFs1/ex+L4I1HqsWbWHJML3j7Xc5D33EjY5hB/QrkeOzCmtELBO9ajrAtzUrBEeSV
uRAaJrtvY5ntGG9KRDyFXTQ1CSBTJcsY3LE9PzZ2zF3uP+II2HugpR5ljNjJH5hkLkxLcyDX1h8Y
ZU55R/ofiaC4qwarq0EsURYQviUM1uo2WD7uCTNW1h4kSI64nARZQ6o62FtDldPHs9ZrqI1XRiQ8
BG50CHX3TpqDMYKz43RVZpLhCxMFlyCq9s3ssN1itiQaS1bra5O55RCDpnFMlV7y7hR7yW3vL/4e
UwSFPUgDV/nTfmFp/avN+1uzXaxbppu3xrDnE+WIk866L5H1A+p/wlh7nfjHA+MZI1SHHu+6T88F
PHakA2brEcRmWU+FnXMAbk1QEq5nJ4fshte8RjM69aI5qr7sMwvh8rFC/virSpzzCvrPxurMtFr9
rSXdyAOZiW5TGvu47LLDVJ6WOyDp3gWNvRSKO1YgHSP7JwBSA2Rhhi1i5LfJgNcpf0AOwgO9oOTC
Y4X7COR1dZOuKbw6QYv8CgeydkwWqc1+nadFSWK55/NWKWweadb4uA46Et/LsdCl/yGphn92BOXe
+gUNh9ZncRKbPWfBPN1W2spnXf4gmbTSHiSqTxcalZjBip/jHgYLL7+jwyTkPYPp6Uk8rXDVSulC
clo3g0UqV4g5KL0zSMXW+Ovp02D+PnjTL15rRF5np5jM+f500ZewwX9klFcGj6ar/K9Flww35ma2
yReDpUas+xF/wNGT/iPC34vDihn8J5uNXRcBeKLA9Zf4OZHA7RJ8kZ1jk072mnErbsNy//9Zq1yH
DjnJruJHh85Ugx5UvbP5vmyNEONU9Epz4MkpOWnnICBK5Ogl3P+emFSPoJM2V10IvEWNVvH4m8L/
iX1P++n8GnXNJgMvuZf2Owlj2LA/pMscCcWY9+WKMwk26Tz0CPgFbFBXoMNKlMTuLH1SraOq6CoO
LEG/n4iWDE/PDaIkf1pVxeVyfgzQBa8bud/XOOosHdrFQtqFwgHSn6bZvArmdUi/4jNGPwjDn+yk
2f+VYYHG7sGZff3XNNBpg5z33wc62UMvzaV56xvaaKyycVT7L0jsHWHMsa4/5uDal2h0e/GMQoea
BjfnlC0hPk6dg4ryKTUcv8LrmDGZO0jUfmQVHhaj/NsX5RLVe5HaV76bRZpXNFmjCQRY3hJEo5dD
/YijTYNEoM79g9iFH43JEiAbtizi86MYLGcYpEMRGuu8ih6xCrSqOPs5YHPLNr7sLWSwTTeYwLNB
37MPEEAvjNyYniDJnPA2md1K7Ru63Ut2ayu1u6Pj7xpPdlF06C8wnvddZDtO8tCaZzMqxFwz1bg5
u4PamuP2U3XRTm7qoG5BfB52Z09sueAesmq3+qzYCEbpqgLTRHVakJxpxLruCfXnRWxlGP64CJAQ
yzrQ6fDrPo1fAIvwoPbCiguXpL1Mj1+H2y8RVgzir/hOH9bkTTuqV7LuvHiy7wW96z0B949jPrMV
TwuREGEHCC7vb+pR96pGopEVgxzs8o2clLpU3SPCpVI+C4mLxEz0ICMxkdXQmdujHmsA7NX41y9O
4aUR9W3uIMONXV1sIMuQ1MJtRMIlhlLUhaeTfFkMDNc0KHusPa2VNqGGtg3RVBFDXu1c+QxMDP+U
+QcF4uIA9zGYbxpohL3QGOXzkUylAuXvnXyL+mzoyxyBwi2blb47bfGc7Dr7Lu8q0fffVAoi1Bi+
mm1jHM+8l+n1V1eXQ/5TjwifBfGYU+ybF/GaZBIXMp8GwNA0yh5N4ipBfu+z0rr0dGt/L+bw99N/
is7+ehZBsntU4upJ6tp2/tiWrC1xCd+1LaluexLz44D86FFjWreA6iYQkyL0OrcwOUH5hJGQqdGy
L56dpygE0J4E3VoB0M4Vo1xSqi7Po9aF7Cqf5Olakbbkt3gbhMcWsXY814s+C53d7UBd7oPTa+tO
suAXotCMjjKqjxdKs5B4atV4puaaxW+Xt320BzLL3bLnS/yA0cRBYGjowjyJmULzeZrzU51zoEik
VNjSlPjg2U19stiIKDUAE/oT2NlGd+T85drPgbUqX4EmDTZi1DpdsY0RorSaB3rBvRE3vGLtPPy7
95Ry4KMTCWx2UMVpMyRHM6qP3RWXCAV/LuxBwSn3nnmMwy2H9/GWuhDY8b89NYcoXqvcKERgtPdR
gkQZW9lXovryQdx7Bs7TGqWUMLaxZ8vAOoiAnTwQrBX2/al08VOhoUUvPjL2gmvkJr9pBFseEsJf
r8enJBRU2356PZwU8Xa6RN6YM40H2VTx9Ni5fV9k0VTL+/8t7mbxHtTCcipaDeDykDrladnh0NWs
4s4gjOlmYeV2BmcTFcEhCjGaijs9BLTQK6hR1a/Sui1pmxpiBAEQinZTs0hSNspkEqK8E4pn2TPQ
4GFT0iMp2RmF4y8FHPT+bnDR2F2JhR1l4UccpeNn3T0VJ8cJy5//W8BttQYzZYvcUg//gQRgsaMr
j84g9quDMEANRdkH1IKKIDOlOgosmdwOwjSnlXPTGuX9hg2hIkiZnTcdxzdPs75NVCUjDdeZo4uG
kfQTm1Lz/W7zXnTuI4NGs1eJef3n9ZwMt0zCLtn8dfAMVvFROcAKtSajpIOgeujehcmrgoh8xiPP
kirTpSdZyGGwSjZNFgfiC3h3O1/XPQ7QLd/t0zC3N1dgkZvTteui1szupYTjICtT/WEZnVaMqtmg
y8ztRKImh5UJodAg1NK9j5XEKcGgLXTkYmi68bOjjZZWNodVzXaT/eNO/iiSb48tTdvvrUfyVMlc
n2B5VcfxIRLuz9J5fHJR6qBJM9ePOAQt0602wQKzBTEdMzicQpzvdiiOw1vSJK+bPVWlH6F8x8FP
55ZFKdQPSVnS4Bw7lCva26T0D4tgfsYcDgAipGS4AZGOqHheEpcRn76o8ywpzowwsZ0GPrfUQino
q0LZ6PoyOUR885VaSnAwpes0w61x/gP2EHDX1o27ax9Valb6SWi6DPTjC+rRVBpjV7nyQqSww1ey
e6wp/advj95jjwOmkk7AzStGVmh+Toz2+Z8cU/giTMmeWTasP+245kS9Ux27ZqbCgH6L/PyFXQa+
SJnKB/x/NPTFToEc1DQkSmWIxUUxX4z1SS7wGAIRcVofZVE0cHwdASQg/r5TAFRzoZuaKpPqsX33
L2kZLVa4tItcK7NwW7ht0K3tVuVh4rICCHu86m3Sl2V0KSqOTAAMMLDDcJ8S8EyXLyXVIPe918ES
OCvwqWUEfW/l3LEAqGO6g5iZog8z8wjIRU0L6mYfO6dwQxtFpxfnmXeekcb+5FzhHpbdKjNcJkZM
qbxxr1qiWln2QbJHx6xz8ZsGwt8dcKIqq68MN388lv4Nm5j4oI/H51e7LnOe8bMlishvwbMajGAo
idS+/G7W2erekAW248mRJDNlWiFyNdGWVaHjZr30xFRY3oblXy2Fmdh5ae46XiPqYp8HjCoYkMVe
P+CSJ1ARju93ABJJeHNLfomyMG4mWc01Y4nkde0DKe7SD5TES6YqWZkKVINUN1qRkxRnsm49r4gu
OUtU04xMEgvrS+sgEBwJxblENsvSH2BPJ9jsuJ61Io6ekltHqQVOvLC+reBWhYRpo+cl8r/A87tj
9iXr4hz5dsxfYrDNEj3aOOtP//LsJS9qQdJZOzJ4OrbenpLYYMWt+RNLSHnfC+LZ7JbyEULrngSW
U81BeC1P0Lsth+MNLSctW4afkT5RE3Qh/GckfErAnTwENCdejynfKceC62BuBQ1WzXQgZHaUsPkU
f4ynNqCCcRziaA+Jg5LKZbt4lJGY3QrjioJiJRPE0T73m/J1atVcYxgNncB9hXd/FK3TXlTgzR1K
bMtQGHQcxnpCU0siwxVud2XyIyj0qRAxqeKcmuwvxaqMaCSnScnSn/Zwo4Yo3IwkawFhXOwyHVT8
6dxr/c9sZOEaBYrEHeLxpHkI3/y+TXsxoHKUM3BGAykYYi4/ln53jmeH6axuyAQ2NBY5h1pHTLov
mFTfbC8J8XODzqPUuXVs55LEqYrEZdwuk3oUMtDrXEwHHdKkONm3tuTxOjOXWDTeb1x6oYb3LQmi
5j2a0d0OHItefgvuzmEA9dYfSbu/qr8ul2Ep7KRZIlaKmKwJeAVhGPqLGfFOX1/2L5WWUERgm6Rs
Vli9Xi4hS7N9908rZcce4P9bOleZJylJ3NKdfcXDR9RrvwXziDZo7AhuGKCgAVrYpqq0lXRjiYDK
xjObUnbyx3XJ3HrIx1RkwM0Hro0JrentkuaWfJYLt/Xggv/7e6DyfyqNHw/AiDiGkHj73QCww/gH
lcwjwWYm0bqSG6pcm18l/7o6UBr9BGooqjGhxllVn0k/VY75qnFRsA8s1f0w3beBd6LLgFQiZcVJ
R6gNW026nHX882HU0tP/M7OrWmmRkBPSNdUvMoE8PdKbMat38Kna02vjNTUFyYJZq5RYyeWfsnCK
EqvjXge83wYnKfow5y06KPayOx3/b1wMSAx9YO2Y07bTWyG/I3WxmOfFIvAyBi2FOna+PoT3q3FG
a1gdNkVNYh6K44mVVyPlF4LqvrfjUo+al+6U+DvqHIjTBX/QX058dwTLUBkYi3SxR1vC0rdhL/Fo
foR+HGhsjsG92HbIkmCYDHQYqIsWFOv8QCVEoEWClBB2OHOpcC5RNDje7+ruZG3vIYracEUO8Mec
TvSmhS3e9gvjZPPP6poyUs9Px71vFUeF4KaJz6w/LOEUAkr4zFWP1kTj8NtaqqXQd71LanIUPEAb
zs7ulxseEU5dWebpAiymNsvhNKRp+C3ZvC3n109bHDNKi7WjVMqOAZ28XVOf0eS1w1GCIP9Ux+VA
jXCjqIi/lJBLOj1N+N5F6PtqyRIVxhY54vGlxUxe1Du3FsUaCQRfAXok4ltBW+siQUcQvY2E6ZZG
PeqPdQ/5ZzvosWjXdIbe6RVs2pY4gQZRFdIwYxPBBSHa9WRKXugRTuVq2+eDfWiLTzXrXyoDT5Ed
vGNLPPtx6DhBpDMPWPXpTqgoasyiTBbwWSo0bAWOPW2uFQ/TStxVgDqdEbGUMqoICIc9DvQzhnTY
pg3uuyD5Fvc76L5Z5INXbAL68yUcddv9Y6VF2pjsOR8JNF0hg6y76t9AvbVXoS4SVc7yTy6bkL1b
8bOv2N5Q9aWyxtsJUW/+izMs28niWzAUX5r/Oqj41SRQr5DCZUiAjbaSxUImzF0ZYMCbTYyyfmAZ
YSXHZ4FWCH4L/1EpZJ11ZavM7/mtuZCdEbwKLLeSTONUOUlgQcM7j+2QehOF0c9m98WLWNzio9Im
0UGB/5NZmVCg/zBb/3jU0JU8IvoSWQQCM3+7oWeaqqaBq2xSwCymxCaQUSjAi0F5zoct1gSxnKBX
Y/7SkqVxMNamQkNEgM13SBxEyxulujKjjACRQt4DiXdryWA90BoiWCCExNX30yvQD8oMtyaMwQ9N
m8IKhIjViPiF/HkbP7XAnmdkWJlDAq6Xkh4ExkHGyaEiT3zOHZZhnRaZl3p7x8n1BSETN4BHseI8
HQa9qzdEjhWkWYk4FkGKY4xoBv4QCnViwlBFTQ31oNRja078fYjs5+m9iIPZ7FDfYmr9BuWAHMbD
LOJf2AjTxnq2HQuYgYbeqww1krCH7Alh7UX56OL5pEUpnXxRJxPqd4p0qJG53uwhKSpUO6uCcaB8
2kzxieMs1ZKpYg0R+ca4V5DWZ5GjdSyKuGnGQJ9+ko59ghmzM5B4Ltn+86dmaP0AbyhWN+/SNPJS
EiiqZ/seVoXxJJbWInGGNmPvNru0H1iz5Tgf+WZ+Niw+adBDrs0fIpeRgbJTG13+Vorg1KqkORUF
xJLm2xe98AUu5tOAKrLind4a3WpfyPhI6idouZUUz5uAd1D9W5wOvxxWl8mjRo39Wiqec+uj6VSH
3zsb7rEakp1kzUF13U/wYtlCzXeeF0oJ3hHqiEa1lcg38fBn7Qexi4ftl9llLJp0QvE8XsvVG1Vq
FjDcQTb/ksScR3b/d2Eh97ldRWQSAKnPK2ZUljsiOf+B3a6yzN+nmFYDczD4IHthrfIHUEwrklmT
tqwEVqV54YRskSEMdBZYsfGY46gyWuhmvjoM3VYi7VRt7pTqcV1U9jcBXtsa9zZCNowBcofBibs6
Y9hAqV7RPxv+S/s9tFMY5SibE4ESGfFAuPkjUXsM2ag2kO+FsCkclGymRZic1IMCdxYa9v5xj30u
CamKVScY76UDhhZK5H/E9qSOf/YMbRNV6rcAxSOQM1Ll0fqFLZIuRCJXyNmNg9pp0Pv7Blw/lanD
IORsZwFB2ZCD8cMfN7Py4mCItLoJVcheX0Bmq50EOdHcZzEwYRAC/dMQ9FlqLmjiLjTLgWQZHz7J
nH7WBK3lTVxEGg90ugoF5cvBwXOof7jG+kBgA+R78cIhRBvqxGFOgOlL1aRp8FbX56NZXMsN/qme
V136tTjIKXU+gS81xGFT7VI6y2cAE2BHJdZhFeeQUDirEj8Voyq2GY5mA42SrmiTUNis8htH5gTG
AdC6MkO2qrqSEZUlbplrAhQl+jDt4/uZ7t2VwkVqoHLF1nE/XjqdCrZWHBHKeInk8ELvxdhEC8VX
GY1u0H30/VYfjTE8ubIHg7yEQlT9n2sfDVv5K/ZD/qcxKyFwOhiNBOccJSm7yyrz2bgz03oI5Sz6
1+LEpXmfi/L7Ec+Ig3Q5/qHytPoaopSpiPPGWZmjHW4QVdhGXiT9ouJmUOPbcd7DTKa5FuyY0Geg
IPR1JV35Wv6zvitxXDi1I0AfMMMvvYzL4p75Sycv3XXGwHAWUkFvZ2sD9eFOkXI8j1Ozm4jblFU2
bLuAh4Gtg1OclvLwJLN6ZJ8k5BF2urarkWkGOxFAFEsmYHxb2ZymE4EeYEOPZMACgKv5wu8Dpnrp
kqcfJTHQQmH+9oAFbYmJGS8Cb2TsTvXIQW+1eawcp5cSVBUdyqILn9ahKfHm1SmVeUEXzYPzoeas
mx5d6qcWdifa3+/+wY7BuecQOqVDLWIkotRKj+65h4GCNyUc7rochxI+Ik6A0+DhrPQqdaAiOzrZ
vulA5Y06cM/uy9dwK73Mz1ffdmuHhmUhtVX1EHTjd0J1VOO9/zpFFqq3jk/JW8gdK0LJxHZFE46u
gLaaAUzyGANNb/RJJ8PuTgMuX+ZWt9rcstJyt8OB/idW8FxcyTn79wrxyb+ZQ2SrxtA0fqfqan0j
IUgR/ZV5xKHhN2GV0ElTnF+vPIHKj+FpwbrVeAN8fSiXsng+ssw3OpzbvEJIhn/dDrG8IQm4bc8W
Epj+CNlOrdGaGtAJGfJYwVdwyeo9ot9QpS3fL7TJVe11cLCjTkjBG6rO45osTlkczsSq9oQZagjm
r7JBLE1TTffMjKrTHYzYIUuTNH9ySFjkZmATHdSwH+V4yWbC5hBzuw524o5oq6fhMtbGu0CEsCsm
928juYqKulubgHMHLamyyiloB/FjSbC/29eNjHUI4n+5tP0GizItyKyt7CuI/0di0Vpe6s1UVLgI
qDHLj6QPeIf1ivTtwzLo23aZS760J689KJBOt2rPtLVCEzgrEQG5iFiRFlTCRi+ZJkZF+44uPGkf
qWM7lrKIAFmF8CmfLkQ/hyKcx/3cdqM2k6wnWhuYKHqIodkXnrtdEcVQVxLqajygK65jPC9cBYyT
THd8L08/HayNbQnFjbj5Pt1ff43bfqeXJTpx/INMEgNnUYd51fmt89jN1wI7XmBzDgW09Vc/HElm
c0tRU06GTDp5mMwbcS0L8btHeRs6oCDJvxekNgKKi4tbBIk9U5ioC2TXU3oOEN1VUiecqybp+gH6
pQC9JOuRnfyPShSMORltvjiI6AegL42yApyqaK0bKWY+kLBQNUxQJllO14TYIaLzTjO7JrHeSOQ/
c4tlqbeudd1kI69IZJYlw1ia3MZmHxpu0VVLMZeq7d1fxQ9+OIgDV66rEPetNSwz0GTUbML5QBT6
jpvDJWdu10Q8UKPa7FMVlYdAfQdiPhUpqCphzCJtX8sK2arcueJsAB2asEUK8P2k/s2TzL8xqfyy
EUD/iSELrjO/pgmpWhQDeVKKDv5I22fBjWH4JsL0rSFbxH6ws5OurpVo42w5jfnfPiIeCbVpsYcw
isDpgOr3nQjXct04ibcVe+HXQ/inauvqZhoYyUo+l4arzLzf/pllPQRsJ+QeIwgCgWEOafY2atZ1
crf+KKtI5aVMj9TBTF9ecKaA3FTOvnpuQkr2+w+pBXfdBoWUYhn+613wtNTlCHs1n4dpV78qOyC6
0J77dL1SE9wOFwIdP5k6Eia8LXJGBqX29AmBqJWauylfT4n+jKk30lGpIMlN0IICNms4qU/OcsuR
zwpPqRguxNcIy4o72wKSBU5c8D9TTAMUot9UctynSE+aUmtMg3iEcYl74k24R8LutDRRxin8TjY2
mLX8RvwpYa98GZyjGTnUEVaev2HIin6qBLbIlFdobR3+vkvOCJLdyf2r+zoYjluCz6PG8DicRVnv
j91BJ5l+4rtiYL49s+PjnBZV6d1BVO7fmlS2MG7WiuDj6f8Bt7XJ3HiOA+0SY7fY3ugwQ4dF1cwQ
j7DLmpmx1zjp2cFl0u5rslu4bRzYBZBQbVxmH24oya0HfoE3+uFYO4shQTixpsYTwaKXPgyYhIWB
+GZN/YLBPW0RdDjAiQTLQce+XTVnQlX8HUmRbJBmDErMlmBzCJQ8k7AGJj7gExFhzTPQbtDeNJgd
RtQw0SrPSweZUVKrHZGSRCkslug1Kx711qv0bOKmyXcJFRUHRrm6JE3RlBrEJLZ+8ZEnOScdcgBI
RcoWr2imkkPQql/OR7OCQ3WxhsiERp81R0a08Ea2DqeBnQqUTx+6cjzQ7/OvGclfL84K072rpwxE
WsVuXWjAfDldOh0eamCGPwQ08GAqNb+DlgEGuI0idgG7mws6NhMYM8ElUj2EVlrlaSOs8TxHcvei
z1sfVkXBshKgGuf2dPEGGKGHhwFETHJZSJ8yVBh7Ur4Nb8ye0CnVFBfmA3tOaJyWTbBqvsKlLGmz
pqUl/H46FhYemUaMUgKuqrvyRVIQK+2IJlQEzqEDuaflDnnWgfQL8+1/N7bDMaysWAbJYFXHzdht
yP5Bi8Eb5fDQ6MbvoSzC8015snAXifd4iPsEv52TviWIQiliK4ziH6kRNyrRVfYagadmpsztQvhG
GCLbpJoSxwoEaTRNORlCmtVqyFmCiVrdb5pfOzY7Jp9vONDBfkoCj5oLUfZzgctqqLIjxuMMFyLv
fvovKhWvUqJkZBQWZOyOhCQ0UAzCT+9H8XqOAF6K8ul3SnaSQ5YAP0k5MyzBmEM86WYmE46kxRpM
C3lmQoo860rL68VZRnP7rbY2Hy7ChYVvAMdZnovfa27ghaasubg1myCfkr4wddoLJSMDo1gLHDXj
trd8s4j6D2KcX7CGU9rX85ulgZjajRSINU0qP9gJbfEWpSO0a0ZI7gzgRUdw6xj4RpyZnpJs4toB
WDxYAtwgUxZ6yQaU4ifSN9S2NjtVr+hZht/6YN1/INRYKT/J/Esg3HradPmftsHyr7O/Mej+feSr
u/4I7Z/MMQBAexXtxrYmo6WI/VC469Vln27RCIJLVbchcAz+M9FRzlSjkosybepzu4nJEycoctsM
X1aqpTnpAU3a3NuF4jTexcXV2ZaIqqdRyCTMsUJpdfUgT7fabK0hyFjJZCsx3DyfADqoUKTAZzAL
qBriqipLBmVA2rl3lQ8J8sOUDCXuTiJrb4pmgIIZNo3DOvcg5l73VEnIdcU5cMCCXw1/auc0JlGt
hhUJPgvFeeIsVg4uMf2dNmpaRzcFOfwJEYk3hf0P9V2HsST6pfKCK79/mhGsirNdWZlOTbZjelSe
xUdFlBY4ePloMyaB2Qf05j2Pd21fWxwO7TxDQRxqVCoz1C4cx5VmUAjlf2voFn25GNeUTVju6czF
3c/dopJG2VkR+QISiNNg615C3Lkzz32Th3toaY0Z0XFqxohPyXL+yu1yCVNabQe9X3QOyKU+tbyP
K7IJUsbEOv7G40vm4nDbEM9N9IsoSVuMNcDfZJlf/m9Bq8DekYW1c4VJGcEq0+xg00VWyBNP1jUR
LHUlqILkX/3PmG/RMRWri/VnKJz3AJxZ3/RkP9diiIZN8saFMu/eAlC6ayZDeOdiB1ffTEDwUD3o
Nnd9sAGP8cu+XUpgs7TKHH+6s+dQ/qo2erqZAkBsNXVIe4uwn6E2ggPuXpU5zfKGXuciWX30ID8B
WthdVqeLh9FmqC88GxdfZaF3577LdjpXZkpyDXwNcnFmLnQbVhUFeXtfAbVKP+j+wlIJ0opPDZi1
fP1aiqoJuJ0WIJL6bS4IT2eXAKjNb2rHsye6zKMLosn+VMDNDR2r/B4XIuGtyaK1kRtd9eZD6ZVM
tgyx2sGQoGUURY6qX5J+b+6zR6ry07XxDZ6Mf1NkdOCTi0AduTAcXA9/kLRvNtbvqBptzSXcWAax
0mHxeoQx5EpFQelqg0yVufhTy2C8k2dKnpDmoXyU/Dd/HbHo2+eXDQK2DfTKwdYxtVVL/faij24q
LxIxSuXFa9kOFmZPMRh5lwu9UBdc8Othv+dOq31VaQZArqB+gXS6fh96jzTYkHxq7N0gMriVVZ+3
ZYKZnKpaXDboSzQkR72l5JSVI3/0aHPlwnT06dU261tTkrwqj6l0/Uq/6/RTqjW4dp4OzgcYur0i
rMiwpLbrM7hM9Q2C1pCAtl9UvWbTUjFK4KM2xzPMflxw0UN52Bb4LcM6gBcNod70HO+6PWE2BPLl
YEL7l39NWQVlKgBDB9IqR0pfVwlWFpp/BfmESotxA91U8PP1N8/X/CnqEVV4pNR6OiC9Z/ddwpBn
ZMnKzkb3FgM07hTZME3JsoaFQY1q5E7GLv/2zAM21sWEP/VYKK0onL8BGzCURhMavwFS28LYBVSJ
K3Z/mGSLEp2nBAwPrkGh35Ts2njQEMEUTG2cn6JMROpgNYMQpkhb4vsw55viVaY57I3Ow4xSBr4h
zJ2hr6HxiZr5HdKJiyEFL3TPiDPFfgUCze9egeVbB6UEt7SXHupk0VMeuchwJ5iYY02SJcTZqk7c
+I2DhUjnJPpPZ7CO5HBhgyEXkqN2ntS7E0DExWDiYIT1lBw8n8jSvrmLtPgYGwj39HTG/X4lCezo
O5x49s7v0+rzsECi+1B/QXBA5l7Btwf0Kllf13atJw/kMoZzBT5bI5t1/Ionf/CL0s7z23FJ/9vG
BUOmf2n55EiiopJVinHK3GNW9RMRaK2tWB3IyRjy0K+qscTcGOg098TCWaVYShiGkWpL25D+wUe+
YkiJhy5onKROOKgM/2Ir1HA20SXoRYrLJPSgNKznBJM598OsynL6kqDqU5kM3onIXmieJIRZHktK
44xkV6h2cUz56yKKOShXsICrEakNlEWi48oHFVDgVX3a7uT0fywXDdsQdbLWfSOtNXg2utJO443L
DRFNbp2m/Iiy7nerhJZLIRogGKwea5f/NzU6pAx+gRj2wDad+KJGgcFeKS3FMLGqemOsnDCuDlZN
oC7qPHDxTSqwWNAGZup3NUNO6r9ZQVf49BlwLeh1EDcuyytsD9K5coGAPfaAJ/sMkO1chCcIBMAk
R9TzcdxHNo5e6JIGA7vrWuMLF0vUjjqJk6/NuWLOXdVFVts/knTWv0zIVtfIx79v+21z8K3BTubf
aVpfbEXCRzQzp6mEEowSfPYKab9Hihk+gGdVYZcioZYjGQfQCkiADdI0dl0t3GQxtZSEG8Pm5Sn1
QAxKbtoHo0wFaGMPk/vCzqYtZdjPkAISWgKUZJd37odwvr3ahnZKU7IwG5QncksWn1tcmrN1lgec
miQEKZuoPYewptwYEhh3IyDJ4WzEZdx8wy+tdUJrFw0iEqy/jzHvuH6d56mmDFA9lC7d549Vxnuy
2lCC6lm7KsCEYP4krhCMxovTTykTw2KlDVEe5AqYtIBu4dy4zgnW5s/VLDvaF9/zmw/rmjHWH2E4
1PY01CIhInrMR9usp4qPJkncvVyLmqewgCFR3qdhepO7wXPXbdfjJtWvs78aKSl1JnKslIu4Cq7N
/7WbZZCERhXfaB8CpL1bv3K+ANCNWHVy+n0c/pOtCrVWAflcKCf8I37q5wCAFtOY8KY67OGgpkFf
K+9PtDJ6nUps49TWEEdO8szQif5eKLPDoFHQo4JzlmmmxronX//2qBIM+xYiTvkRbloD0b6SyjDU
/re0Q7P2lJop6TBeHYokaS8jWBgnBzLW6iBorDQkYLo1JHSof9Pfih7wzbjOTvMjpYJN1lA7ADyH
ahH1OftPW76bbH3k52glL03EGTY4H8edNgJJGf1QWpnO6iXVZBSpU8PiQJiyyioE1HrzXIP2C9Fl
0vRVFQ8OnQe4mc1BVLY4EGESlL+zJLcEwQlqWSWMdGrO8e4/T6bbMoPlBqSiA66ZqslN8vBgWYta
so4EmXZ/8fM5oya9FwQ2G4bWbcaaemuO98U3iz7W1MgUf9GPeMwCAMW4jEWO/2EgSkUDRJMhxMB8
/ZXsNLsJf53J5flphlPEp3K719oCFYzhq8kKvk1j9hxbM87HxHKyY6oAEr94Qlfpo11vTcpPKSX0
putzKF8KfqqFbpenu1smUKaznA5pLf8rgSJhNaFFiIves/ea/+NX8lprky1M4cZtFY57ojv7OUNB
u2o62JO4+BzPavnwcOfO/02E46g8naBGOggDa87OVdh4VNn2KxaOqgvZS1ZMesa2qvcFTQoDZPJv
s100yKyyMYQP78+Cxx+v/gRqCuEzFDvyfnuGd4gefFbdbzIIhXKiYo9FRbcvab0GUjl5Rd8YFRJ1
ClGBixOEqrL7NdD7LmOqpy30RiV8E6eA8faYbIIkoQEhWufiCuBTKN8aNDkGsqwXt7wSWQCCGAZ8
8/YyTtp0eMvZtBLpU/wg/8S3ZbB2BMFYe9MFOMOzxmVnLFSlxYXRNvreqQ4i16oQEGswojkCJxVG
f2ETSFaL/E66Eo6awvGA/ucHtrDsLaeDzA/Ke6Uqh2HrMdSmIBrFegeGak7zZjpd761klFeH87dB
TwnEMVf8rXT8fQw+6I4Hpjl+J1kgkzHRJqxSnnKcojUFj3HIGgLHRL3vS9aDAWynfrvD4JocI7r8
CmxNj4Yu63D0PrI4IhVaVRwuPnVL8oJxTHk8WtKnAM/2aKH4t2qui6hO0OzpGKP8tYRia/Wb4+UL
DBAfDYangOgWXTGYhSsFlh9ATd5Yx9iK55ka49VCUhme6o6T8Pnm4PsxW+4hl7b75bGSXPB9K3Bk
65gYCf06u3lEK5M0bujP4RMowz4Rqpwe8oxHbNDNI2l1Te01HXvRphFzroVqJWsHQ2TSxnLHama4
KKo3p8jfDIthw35nOmaK86ci2R9qHIgAAuhEzRJ7KQHOsf3FapQzN2R6WKUp1Afj1cJaoQ+z973+
PySrEKFUwtUrmSwmpCECQsQ2y22ab2AlzDzDYClQUiuCOv4Q0o5rLETt9KEH7k5UgUeB/auzJgDn
aQR++kRbK70V0BIsv4k44NrsYBWDpvXTsTP1EL+xgASQfXn/nkMI9ZvLMk/tqr1JNZhfurFG/YWD
DrWHyv4amrs0gqrJdn2fneInb7WjbhIKdSC1gwLLL4I9iLZcbeB944SR8TZ75Rr9oiE91j88+x0c
Kf6QIgcd6y5L7eCLdwWhDa9Y/goHI98c789OYwN2LkjhmiDCY9K7tn9wBuVGk+HdAqYyv3HHDX5I
yUY5X8UwH133FEUfeaZsc02GFW8JWkaycPsQzbcI0nqbsjgzMHgGOnrP61EJt2Gyfc5tzE/y7N2s
tLVLzEphgdvPALrSxtQKu6xG97bmONdcS93T4MpiCjYo1gGeduXp2d9QXJZOT9r0Zjtd/qsMKXRi
66ZORcccVSp9RDw8pfAFNnCeb0k+HfeVqLkrKe7wDtZZHSOmhtVp3X7M+ydVvpdUK+7aYVwGuvo+
M+GbJhrZNoRZKBlf6qGu/7hjxsqKT8c6yd1ANMITyocpYmwPy3MeUMcM+PDi/KwSfxB3uWSib8Wr
RaQMjzxjipZgLmGbC750DUIbSzEno9sI9t74OoktQFKS0iEhpJikGEvxwv+oagmpnstXj6Sj4dcS
abGyP3Qt+6aTJaQOTf6Eu36uNjREwSn4tLzr+ecn8ezDZ58r6iYrh8Gr6/Vl1OBgEKl4pz7yTeMl
bGeq8c8//2foFdSed3PE5/JZua7L6rhTy326/PsTsriZgK/ypHM142Cg0Un9e+gksIiIbhrsXuxd
whgCNBUGQsLQf8snZ6uP3hG6zcn3h5B+1ikjtwdBxYp8akEbGTH9MrSVFFSiHW9TduvHrZ6UJw42
JOsuPPZjNtxvRTatLcis1uu78qjAjyd75qYffqz2+RUejwpYtThctghenH9j0ejYx/0MwFSjn6dL
J6ftuCc9UV8VnUSoF4ItX2yecKPf4RMQSCL49LkMQ0IAlWhuOBBNQTZc+cFiRpT7HwdL9v2UgBwP
6MAeGZVXrVv1fPwqTkl7nST+EDAY4No3GH0HzsHp4JIiGw1gGg05wNZplikYmKdiJjNTLJ5E3FTo
kq3X4NZLFmGeJi2szG0KHBgR97Rcupd9mmFeCnXNBeuH09NuT577Q1FWCWxXEmjZTU/a1Ane8Bvl
jUTrZfzHFZgH3MCOag1hUbHMxAo5jabNG7IgWEwfsglA0azsJKaABbs8ZFpQpzShE9EYFcvaYiRL
7tLASMrp+9KCk8im1K0/7TZq16rO5lHn7Jphz0dFT9dryYQxvU8buugewrs/i1QbP76DtyZtmb6m
36m8PrP9mdiMyYEuBmhhi7pudsAUTAGU48fc4ZYg4BsixiPezBvNYpjHm2KuGnvcfXmK0+e/+vFw
Zl10GfLohmJ1xtb5ILrnXFJsVu2Ui13+pcMvYKZdduwQAvHxwLlXGiM5jy+LEny3b8neFf6EyQiN
/laO0U9Nu5/S7hnDE2cOx0cJloZ+tmnVvYI9ZoPhnmeJ8dyxyXX7Flg9lgi4ccZb5SJY6JsIAhj3
TkilLaWn8K+fN3mCIeOHEUuLmUzTQaBOfbimRQw/WItrA8UepMgz4YsAOUFuZDnAEwxSIsd97TSB
3wOXwwSyOCi8R8I4Cl6UYcJnv4Aon2w6aNmFV8kQKcYFLSNpIDuendK6ocllkQ+2IGE3OqtNooMA
Q7luZTR68XlvcUJFw+lCqN/OcvKn8j/wZp3uETXa2Om2MhGJwNiultCCKEzLOKj9TAYKgz/jOv0o
XQXq+wX8/awEYWomoty0hzir9iLZvnXtBHPbZJ+NXXstksdoADD37gxF287PXuPCBnmSEC3AY/oF
alofOlZyYXrrCa/OagOd1mpdZ/uNCVx2xY+yNqXCwHRTaNB3NK1oueZmYtXFlLOlG50rB1GwczAT
wiNoSKCLPGAgvySuByPew5X4L4w1UfJIUQ7baPmy98X8YIdi1NFnFp0U56wyRxXcCi9ebzfnJLKB
0/v3ICsgoTebDacaI0+AK3BjFeo5fRZMgb9o3CnRMhKC1z5Df1jg+t2mTINglxaWmJrfONAWxw4Y
OXHcMeH83AinXJbZYSfBnGSX6eaqZGfZmICR872x0q4UyzDIccj3RY1JpAMKYbkF/pjo5ih4HFNU
RycXDBgXJx+gqCTOJg3OS9Lm0aCrg9Ye+A22oHCk6sNhS/KN0OlAdGSD5nJnFgCvrIGyzRHoACQn
5wSX6uWLswtyjR9nlWaxuWrattPt8cm+Tz/vgE3gEsxtHBBrLr7rhzEA/Nh2hnEwmZJlXil/7FxQ
PucYkzMViq7inu+XKSneS+hZYwUXPdgSjYWr4/NDTHCLN2vs/AgeCSwAWj4xrZJJJ9KLdCYIf7DU
faOOSqqBPhDlUSjJcPmO7d3hunuCqoXyzFNqj6sdM0x+uR2pVA1Rc2Fpn9QQKLGp7XJHePnbbg+Y
dGOLjW2EbFTWdvB1YexwfZ8EQGMUyGd1wkc1g+yts3dM6o7sMSBDZVLjuiqdRL3fNFouCDyuyy79
NAvcyja1tO25++fRsLAYgTv6WyOW+Z7j0TEsZ74WdWvRKJgoIH+yNJPpc9nS1f6o0yMJLd8gU8Yz
EeFF6KyIPD7wLwCLhIGuQFG1UlgyN25bic6W0DRe89evwwGtVf39YYSrdUJ9xTQwJ6JjpdDeGX29
BEkc6IjwKqvafSkF2SOPbWs65zwqV1mlektk7qq9V9ul8R8hkv02pyGPv1KScAxfJR2LfMJivy7/
I6BgivE+ls/h7IPPnLDZ8O8MN/PTji7zvpW+Zdpchwq9wfIHQbAJnLjxzOHeRc5otOAQGHvVM3C/
37Poc75XDNZZ3Bda++bJSkVPKGAS0XM3MiovuIudBAcy19vuoa2pI0R+s3G+pUeefX2AKi3Qn759
S6IGjju3/axYYZbo2ufkYnWMc8eRHEd8euqPkta5HbrNYFYhKP5BUT8oA4WVNLIf/M11elvRFMkr
ko1GBoFO1OURP655PH35nuCYgAxzf9iUvr/vcd/a/ntpMcmPjMN3XTkzjWclhgymSTYKgM/2Ne2w
0xg/yBUw92r7BVXIjB47IWyJ0TfC/RNf6A5cNlhhvu1EL+DiOGKkpc+pKiSqgIuHV9ZQjxBaydgS
GAVfPG9QEL/jMpwq5xyGlORQyqyBji/dzxwPZ/WqHRB8rERkRumv1ocJTypf6H7wIFlcigRY5XqO
oV13342G7fawfqTc8vC4kOl7gr/F3o1l/yUV7UluDgSUyklfs6kKxTKfhTD1zGcQwHPSD1lswG71
4ux9w1uY3ufcv9Y+06uEgQe7+BjKd8Jr4C2M1MbQwQnlRT9fhqyDD5V0WXA52AsYe34UKYL+GKD8
Zf81ftjDKVgMKrA/N1vIv27OwovzL2ZVBSTt1zCcFQl/T/5tgxj1peq71YuugNIpE/DKrqG8kct1
cCDm7aGy5Xh3t+CDw2qq7Eru95ohbDNtOovL2WsVHr5n1dSppBw4pig2Lnb8JaP8a0PZlr9dkFwZ
bwQHAa3OiaYI2ZZBJBzyteClvcpHnJIwZ4WTNrHHxItRIa1/1a8Nfpv9DewEMLpIGl/IlW7lnZMC
gZfs8abpXUKX2NmabaDHJiH3AK4JW0KQPOVzeJAJJ8Gi0XYkyaY5hir9nTJv/szcipTB4F5FdDi8
KnmMacYxkrAU9/Hc2vfkAnJcNjdAgcF7OlinGausbZSVWv0T29q8BneGy5iek4tNoAjuDHsrZDKQ
9ULUtpq8ryusrtjbvVmZeVKpn9HH7l56f6le9rWOPiXCNnr5M/I6aUJ7Y2ZNBVRmsb54hObZYzGP
meWF+5lIeNJ4OvCRAz5Dh1OanURRaVaWGyoYDfFcSonsYLOqEB8GEmxlRsfCJ1lMlmK+usuWoPDa
KgoCQ7omncyn2poQRjgBpdR+M+yE5Yy/7B6IK/6AHs3rTz+j0l6pILGGzMl6c7y2GjDnxypvyTMg
TfvduiQGfIB9zDvAUg6UtaKa9JsNRrQxTbrjXBGVp+njADJM6r5nf9WNN5gca0nOWAQw7JSu8iFc
HaXNDPSqGqtsxjCvD9meIavyZzDOqwTOl0crYpc+F8dqyTUC1tw82X+QftYyqCSHin8YCXNzy5rv
H278isCdHhivdKs/z8jTNFpvkAjdN5iyojB6j/rUJxK75sjefbcLyH4Yb/yS0taqBKhJmaMSxf4d
q31pKpuiYIrt4ehubgnwmBVmzjb6/+OcSgRmekmePmzXsR+pqyb4cFFRNuYcZ7lwzpAtyelj0Cxr
X+CDOipd3uute2pbEyRPHpJJBaplydCQCmGWGsrhTARJI7HIIfRmQcBBt+A7nxVcWFIzsqpXxZg2
PyugeKrXuVIj0YU85tTQUy3CH/bRxM3OfMtcVgppy8sFVkdj9XQNQbJ4UwsSsi/Hxej5oFoSe+CJ
839eEIu4tHRZy5KmdSdgzGx0A8greY+kis4koc2OOo8Rg6aKso1rzv5guJb1okjQg9/o952RIKm0
Vkxzg5GNsrUTOj/noAYUfSkeF1XA/hYE3xsPd/9rvt4fetaSFMMvZiEaPoWzGcl+rni/fjSICnIx
EBTL9x2Tlx7V03WI8TbeJv3tFC7R+cV6C8YOAMlBLozfBc2M0Cz0CzKibRKYsqIsYYtNhi4jQZ3j
2k3Ey/u/7NkknVFOxM4XTISiNUvo+qRmADCpYJeO7QgKGeu/qygLUWYhE9JsDCJJxaTCpD17IBHk
xG669F7N6GWBLR1EhPQ01ZVrhX09YkzcDnn4nZPOitxnYxkd0LYkrvCQWo7noV0WK1/k/DS+Pwxl
Scu9VdJLEPIazsDfzRZQUembdo1DE18Ft8UaTZiE9mUoKX0WntMx7YCEnB1uyGHNkkUHiwbnpUVL
ra6PBkaPHUiD54DayXi50E/I6I1ESlY92hNR66eePK/4tiDtamgWSMZmxYCiiNETVkqUoLscZc+f
iPZeZOLrWnjxTXqqVhh3YPvRjoffMozfqFVePi7Y6aHuvi/iGNRyIkfi6vYq9AW+p84Ojn+P8wRV
68+3adFQpJBQkYrKf0qijvnEHOLz2mIHpm1eBJidHhIbKcg5iWS3ro7X9P1v6mKNc8jANuaL8nEc
aeW5NSUm+eSc4VDfqH8itstLQhvhKuAhyhO3O0qBJcJq16ao1G9cWkgqtEeL2ge8aIz40KMyfzJx
fAD/LJTGv68njrWXx4YcR79G60XHh+F7R6KFXniXRkK7SrcMnRzI6/JuAiGHJYBOrpTmHyaqRNOz
zup+LfBTcpXqilbscEcX3eU8u20b2Ss5zJ8pzAmQfDOQbD2QYd9ihICDKw1sILAVhps9RXXRu2cS
aZK1uoDGBGKsZXyRsFBO6HcvSPBMzBP86WGcCyGYFPiw40KDJtcysOeqBAqrOLp2CJ5M0PhSbwww
ukbk2tE3HlM4oby+3ZDDR06WDlCBukV+gco49W6kUk5uabiLuDOsiTHu5PvAGI9RkxkzV75ofhhq
/CcRwid+wlSy79w5IlD0n+0wXGXJrsdZQK8+z8MJIyhR2G+0hBGIbWdZ2akO1Y5fdKBe8CMFWmwi
FaHjr3nCSr8HQciVWeq+QEkffP6SvyMG231A/LhoUvTCLT/FeFrNrTJT2S15Oe77fTdHap91iZlW
KpJu7Z+KcjM4IPB9xkwKM74HumGbMCYo9BV7ulJxOo4DPDz3IRbPVqPqVtsxZtKmt9rQaoyQIMAw
1J1Y5muqi7eBSsRnV+SKbMjylleEleC6jRS9ldZ/QZx93e9QP8GSDPq4HL37kCvEtsdi5tc7lmtj
rrKS1JjawT6dbynNElUaNYOFq14m4bs48eSuoyXOwf1VqcVOJr+bEQ62dIGHQJoUNhio6mNINRHL
7ST+u3pProm4uM4lxIWpTiIsVbzGXsxfM+pvb6HvcdWjVFNeEY0KT0x87EVYkb1VzS8x3rQLLFeq
KVwRel5qttWJfCGWX6V7DpNPZk5+rqw5jdHrv13FTp2StIPXHUNiNbu+AP3ZRYwwBL0CrM/H5mFE
VDY9DbqNlz1IkIGm2seft/jHz4sIWsdtGLuhgecNpGkhd/0OqXPiaIrgq2ksAE+AF8xX5aPQTf/l
QdNPrQnxOnFY2kNFSFcemkJxp0qel8HgsZTPYq3RWDcmEA0OUSm78Bqeg8+ELYXDrXxykcZais85
Du6ZbKIkImQ35sTdwRAH1dZeDKkVHnxQNEsgI7lOA6NJ03WwUlhTn5aVPlNOoIF6Oo5keCcrRaXa
41r7BwfModx+HxaZptovrvJSfUJv4+fVXXwMs5As4lR5UMoQicNxiDbXt/r+Jk9R5//fi4QrEjPH
bbHcUCZx5Suq2Q2NoQskuYbdmGNh1+kHW2+BcEToNwmlJqd1LHqS5m2vt0Oz0uDwWz4OifQSJM1/
rheYWOGalYgj+wrnPCB24GbS4BvTRHPXqgXrwnu5dhMPqueHBzoONMnDEQcOLMdodoDvpTevK/sm
NgrD555DwOfpc2c9UXa6ojBhj5qDN2uhBJNrnyJpR8m4tfxhQnEIFJKFnt6TWViDfJ4QRL4pYcJg
yow/ZYv/yqwfiTSwHI++xr2QyKWY71T31UEcbFQNtArrlvJ0v2jiE78hFz3KC5Ycsv98Y3nLvOqO
Bq+kol7BMHmAcD4ol7ZAZaFg+hHf8FjxEHnbzDkKhZCMWB9lpT4bq//77paRTkO/T+3MjA7cCoQJ
JXjkjhDowTPfH2HR77u2A6qGsJRFtTkQExWCIXeqZYI5QxWI8CFSV0KL34y01qR8a4SJXUsJE6Ot
kyPHFD45anaCz/0vVmdiNFr95MwW665m+p3fVPD4jyqHlKXAplQUpJZP3Se8V7/kl7IOHq7ubsQK
zP9hXiyVjtr79uzXZi2eVp/ESO/NDC03GpC5sCgatDGwUjoZspbyqt4aNN8BVvg04pGyKCaSH+SG
wV7OANDIhZE61j1rBh+5wdzKcTazgHCCldweHuA+ObuzOfeL7jywprG8AkNnP2//XkdpKyvi4+qd
iwc0/i5DAwU+X0HtzwBTs3q9wkNklDaXZEy8TKQyWGuhky55ScInbpQ/Z+KjIaUo2lHOk7XQzlnM
wprr/QTg4HhjrWng8bE5Hsnjbyh3phb2ZKuDygjtwl2aDmSO9xdCPNJNv/psuTmwPJ4+/tAadsLH
qWXWEu1Ov4l54PZl53vRzI0Y7Vz8sogW2yC3dO97vsxIUWbgBtl+aVkc4rEp1Ar+6Fb6IYtwlxar
T+riIGI6626haZ6wUS+aMp4jYIGsBORRFY/lcY9C7A4Ynib2pbGfwoKHESQP55s7ZCOcO4666DfV
OjSYtzW8cEx96w3uA7jhxw/5BdS2k7M19U0BNDMKvIW1J+ZC1HFH67je9L6n2//8GTJVbWf2T7Xq
qVsx/QAEFlsPv1tA1ZwEAzTiqn0wTuRBd+/FUt+rvhtJH+R75yI4GNxtLmIcVPuD0QFHkwqaeYRq
a/txNbJpUuwW/FhrwyXlHo4KPKgfBY778ZuzrGGt6bvniWE7K1+Nz/M64JlP0hBFJW5nf6S7rNvb
cttqtadfj2N14dZdFU4A4KdnZAdxiii6yzw6ZdIfQNco3bCu5HTdcNEAKDDIKocNpfdEWhAYSGY4
bIOirnBujcGk+LHZgufndK6r7KI6O3YI4o3MSIQh/zMhBjrrjMVUKW3vVr029709N3csk1elAzXo
+f7BzCSaAbN7DTdRb37YLOYX2T9xi5XP5pyo3W1LeDO7FLj9G1Lyt+cjJP+Uv+yl0hzrgCcZIT8J
QUR+IOlHQoXK3qYxlf2CBE8EYjHFu2PESHmYqRXwdpvSraS8G4hmRuEy68iM6AJualRH7Iw7vDa8
YNvOPiol4IMfOYbl097o0qUApj4cjCsWKI+b46Fxqdb4tz+1c/ch8BH7c/TNQiJl+An9MQUZ/On7
uDE2qIcwEVvSdxWuda/w7ecky+eChRQliN3PWg4WGiKLUhjlRyKAvdNBqcX6jAXx3ctLn/oLTmiC
ENl3IPIEByt7Ly5CL5crf9ZyCVUPHBk1nlXznlX/20CyOO4cPzw//uazoB5pzko9A47EKU6I4NDX
ONVy+r1WTUnUjBZLCBMyojJAGVzhAQBkRxgJIFWNvUjb1l4UoBsjArQU+M8LISBj0tzDjAl8gstO
5dKKo2aDePvyl22MSXHdOHfMjIcVcF2kKgALP0w77rD5qFlHEiYE2SZop2tKM6BnxLn8jj/WoiO8
aJ3BDqQjVms1fCO1QVL7G6SzCv/4sGxJbuTuVJFXACMsba7h27heTXkPQIZGuNGZ9hKcEr4fVC0+
o8YtnYbOnsaCTrkezBNJowYC0C/81PjwyNsxi6AaOhfVB2GSTfjoKDNuwdRmnyfmomxZizam7sgu
eBXJkI4EchaeeA1VCm8MjSIyuXpBjU1n9fn3p9n2GzYOEJYT+5oFaZ7rxq1h37lnDI80+QSx84D/
rszeSNKcAOrriIzY8IdIY62EVEYAZlyHdVN3/cWaLNv3efmj5vMXOnKvXbKVa46KaV35/uBFnLtJ
PWZMsJiq1eD9CdQkGxJeXIsqWL/RnDk7iSXaSLuPsmck6otpTtt/D/dqrM7BHWn6s/RvZR9dStxS
PiX8NYD8SNJNEM4wiuZlF2oWGY8wf+pLbTs5dRc9vu/crfCa+lrs05FV96pVnKiqohZGPk9kFoSc
SFWUk0wxpE8oSYgd5QaViFQkCgCBtPy8wqzVPDbPmkraNKq3URX63ork00RWYuxC1oNdoelHhRBQ
Et+F9gDmegd0qOd2E7znK7MTzrgHulhIA2+QZPzbq6kdWK1ltSRXsrr/EDHKHb1u8E+/Im9KyfkZ
3N87wscuN1h0NrGNIT/XWdC4yiIXnIfDOJRh1H0WcieCLUt7qJlutt+Ayu0YkIxe0Ak6TjtxAe5v
8GuL2xYWEy4RXBLmnc4yPo8FLevdEAEPxduI5l9T7fDUiZwdMCeGRY9Qi76eZw8ufQn0ZiDZ0Umg
IY/zTF327TsZPK7ksnzqEx51jD/bvZACOjLQDLJa0Oo7J1EfWt4EpZ5lfqjnfvZAJMmfSlOm2l6l
rQ3Y+RttXDHaOkMGfPv8grFL1yMZWpbth83r0U9c31ReH4rQZWlEbY1+68fWTSDl9JX/xECTyZ6a
hBADp9HUfWz5RqErKf+0V+9daG6GDWym9asW/HCuRPDxzXfuu8GF1PM8ZRSOPgdWwS1qXZgHaYq+
qi/YlzM7zsMkVEbmMHEXD38IgCpUSJtOAl6e/CUzNOKeE2PqapREZfo8Pa68OzyBX7e/K9MJ4DLk
201/6EDG2zTo2/Fr3aHRDQRXEVsOl8BfoztXJBbmJZ6AXUPgibqge48d6+mOqoGHvpiUcj8NmP1/
neS6A2gOPTGb/bMqXsOucclKkcEql/Mu/l3DZhQR5gZHzxqagZOTRYZGv3hZQUExg+ag0W3JQKiF
4IEX8gUvnZRWMjONd2KL+wJXoCGy2aGtq8rVJaQVIwXW3Aox5vmAh2afXHjdFpJ/6/yQKybXiqmX
DoOOquE680sGpZ8jehmLKCIR9ZOPjWkyeIUQzguR9udGlN2ZFVyhJ10afrbk/5L5NlbfG82oLHhH
MYDpK3MiyTgxOqr0FSM1rTPQg7yCOE9897LD1NCyUk4Qk934+K9jXqYcWEFJKBrJoFXhf/JECHi9
T8sjcK/+jl85B8/GoA1SvbpKhu919pJd+XAV37c1bn9u99Gjv7dgPr41SBI/13gBSe692CbWfCjF
iZsFnZiRJkReMndBQSjeYQ65PzeqkX24Rr63GdwVRxeVtd1nK9dvKkV9fp5DiBXtwjUN1hjufB1U
U3ue1t+f3yy7QIiJigynPhG4Cf8qNP7gjnX4lnoLfMyXgJB/fgDDnHdIWXrPIEIrHO3ayG1pfIqB
FrtF6cnETKpuIEVQQH6Q0CqN5awsdZsqs0KKvzGWK9xP0wKvm5xl1Ih4FcguYq4j2O3/qf28fGrX
gYYux3o52kXfbugSEC+qHrTdau5QxMf/4fDnryIFRVXRU0OadVemZ9EJ586IOgruly78g37bfpWO
Q8gYhSVIi+zJeKZsbnvaYNbsHkml82u89pclNbRgT5msYLDxR3AWfA+wZ6cUEvKWLX38YeOtitVN
Z/mte0aY4vBjywzhuPTFbAbf9M3R1csGrOiLG0kI3HOrHsws4BvaENXckLuf5eI/saYkrIVxsKnS
pagpjhi0L82xnXZ/C95DnI35p43osYPbLhQeXy3eARDcZnPw0ad1XLeC+YcHk8SlxuJJsjkiMEw2
0iZ/bZ7qfikhthY/dELz5FC03+glqDe9CimaKkHADCBVXnfigzxeuA2fBc85Bd40zZ11xq7ixFp4
b1XizG8Xaj4jjfTuoamGGqp0Gdn/i8ydbgbQ8C/itzZHOfXhonzDB79EJqZZcB5gfcw5TcLzFak+
6lIhDhNGaY3HGf8Q/yzM76M31e/dl2fiIeSUlsZR+RifEjvnpb165wU8AsvOXJ3ElAJrlJl9Z/az
4hbhq1QwrC+tbOo1yr3eEShRvuj/j4eeJhsx+nv71omrJPNid2CnpkTu1464zUkPPOqBMejbPLsm
HR0cbGhVP56P2x80Y/G+xREOoKNc/xv9vfuJWeTwNYcjvuqZ7KisH0zKdun97/T3ZeDHMQfr7di2
ExQXgxyC8NL9Q79zrJ3kd7v4Psz87FPt/it/ROQBRpFuUyOTB/hW2t7XzwIfGulyQ5lklTUDxMh+
oBKIPSAp+TA14/uPDhbRMoBCytSq3ITAMuaEDIzC7UH2uztzT8WE2JwRvGcnPW7d9HldxvwW8G11
xMit6DmBACl/MVqsDcGFmA5lMVvRL4UYR8S3WM4EpmZlTpNXHMfEX3ynepCAdDX6URGjNxZ10xRa
40n3dhPZe2sIjCKdp6v3al98clTk50r+n5KTuIrkl9gp6yiLN3gOYAGxrW50tChMaUL0sak/8GXI
iU1zS71/eWc2VyDs3cY3JUIQUNUiVR/CKDTMINACJTbFS28EhPqu9l6ma3Lm49f6aINAtlGcoYFC
JMV3Qxzb+tbI4NAgS1buBMZtTUJ6JiMBp75YdSV25iXGuz6kQK4ncV+F4wZTVgalRWLb5igAxGyT
hyzFXfbjj5W7zK0sjKRIbwYk5dHYtnw4N/TPP/iO5sTChLUJ5YFdNG6RS5QxzvzxZnEB6T1y+3/T
BGQHgRCq521RCJPAPgOTI/sFGKwJ7e8vt58EZ+PcytE/Q1YI2W4XOcrf8wjN9w2LU06y74hq1lOR
YcxeEaC47JNiroaiA2y6bD50U5NS2IhmiM+a0t3Sz+SIZ7mXMtgrwnLOzWJbm5uWHkb+Jdfh19BE
Zla9XdnqV2s9vooPcCrR7w+79ENjrs4LN80/kp+PgQPOV96WM9A/8NhwTykFAkdlyrkpzQVKwnN6
Id5ju3fVZxGKeZQhThb2f7++7H+7YHeqRKTWVkA0+kKUZqOlMK3qYIeaAkv1D+JQ/LUvwruSD6Kf
ll2NDtnHyFlFRLGOVF5gKtICWYJ1dhxIL/636ve9GGSTVsFTT9ZYJdOd1l876H4fEqY/lp9XxVp6
tjeJPxCq1Gd7IVFBny/ggl/kcBlVyF8yrgQb/0H0I1bDtNwXWtH5f7yA0l0dX2SgTSbREE9UC6RI
6N3zPnoq4tIh3OUUIl6R266OfhvpvHUwU4iaDneyDfIpcjt2TRmW0++neyv7X+zka1ahRABrh7wF
jEfdPlyrT/ndrGmNfRn+0PYJh8aknYuspl1hhYNqWzcwlPISKEW6U3QkDpWzkgY1Pvp01KgQBXNp
eCvMrmsNS/a22OYfeuCjjTGEYZJ3WfQtwtLQcMOFtSfu/kV2Yz2+07DdIUC0fDTAQdsz68z3aF93
28N6K18KOl8y9Qghxya3JS3oiS8f5yCzyXse+eGSPE+DRNQO1Ex1rf2/F4UK/8jjNIAo/C9yBW2d
ewUBA8e+r2VXfvV6aUxDnp14vY9P4puQNQZ6+slnreKU+1Di2e0NXDwcl2HGw0D8LhSttuO0TFMo
v8gDW7723hhV/Oah5NyL3aeb5loTEdGJjfZht/FVRCbf2ZMSJVT8zvacpv/0SacdvT5SmRwu63F5
Ax7BASz9izF52DII4jKg8CDGx4zB+C9AbSdySw3rDV2+QS/pMTMCNPN4EKlVPXbsKwPmeKa+lEyK
hjf5TtB+QvgyIlxMRO5eEJ8fRkWFjnw3jRPPcnFXS4rUiMQbecJtRGSq10VbZf7DsqIcHA40iZvX
JeL8eNjgedVnyiLUsHIeuegzTIf+i3lAeRzL3WLBwHaVtgNJ5Tv2d7Dw85efNXM0LPlOKVuuiDlJ
UNaKqxBPWFP8mXZqLBXY68H+lnovWWf4vye2CJAtEeR9iVEwjNTNGc8TawrMc/lU+OCabMpH9BVx
W8wEQMZGVZeYGPVeTKMH5lej255/Dy0fnghL0gZxBjeXXizgozYSVwkq1nUYCvUHfvJtAPLBtw48
25K63ejpXs3CH/e3A+F1zumMI9fAy0oZ0MX/rdfGIldl3h2qjpMQ9QMWvzkm4ZXHEtsg3Pq5XtEz
RhQ9cZsvbw6sb21zQ60s5wI4NJZqDDIopU87yiFUbYCLJbD6u4tNk8PBRDiEGDAfzfUwnP/NHaxD
x3ua1h9J1t2jREexKRRTB55ifCial9v7nXMAGJ72jWkaqFJGBPjC6UJWRKjud2dvPg9M+VbjTEo/
3cU0ka3JWxUyTLUgbO5GqONirVZD/xRHO907cBAexJJqg3yzc21rJlE29IjEjf/5caiAoLWg6O7h
gShMpKMXTbOlHX/7WJL+Ydliy+S/25HpnYlIAnGKuh9Tz9MMWPrK4BkXVW3xqwWgvmv5ar7n7pnv
cc2Pc0wBfJRlou5Rv8XjASvDHYj9w3m0aLE67EnoyAyXd6hbDQ480Za0rQwvxshu/u1VRSMIMrTo
y8xxFDfmBu4bHAIgXJW6qJaC+9rYXG29/qnOsyRD1mmY12YD8+Z0U6VAs7mc0WMM2jdiiUKe2j0H
Gu0XomajkafislZoQ5wHX6fDq1zgBoMJ2nLqY+aBcxsNa8hB6pj7jx6k7V9/GonJDu5Bfzlo3ynI
Q581pdSDkgXenIUIp/kbrL/6lbA8pzxwHcirFIuCfIA8/mf+cyMs6Nxcht3/rtNa+u3ezXhEdYLR
6t/7UUwwlZgs+jDvg/Il3E6BP1sYsQ8t6K45VUJ4NihXw4jdmvobZNAg99iPU2LYpuOgZeqGKdBN
R1w6oEpeS+oOeqn2LB0byjoHkBNBmtU1S31LMzwYmy2sztBdweTZDC+rp4W6/8SgKkYv3vFjUg/U
40AZoeCIGmGAFPoyg+6UeUfm0AAKFa3zycUVKuO02X+aqHnQ4EaD/1Mm2NR00cd8LrZE7B4y/fgk
2+2zjQwmnbeMMf/m7HL+KqYhB57ewFivx+Ww/T7qpdOTi/3M0MCzp8l5X41ch9UUtf7qQN7NFiQb
UgoCDD9FnWNgH7/PxaWxm66FO1B2a9C7wTccY8Y/GoyNMbSyugFrWoMtjn13jWXh6OVMDOfay0wF
WAgajYHwWUAT9Lem3oyI/6fFJXd7rSvzdEgqP06OzxJ1e1HCXkE5HC782yfkgywvHB7xpyXKYByO
9vACDjX/1DZ31RSX4sbfWWMabPuA5bhhpN8jrYppIQEqk5VuJQLix807G1E3jV2nymDKEBAw69j0
jE5ro107z4aqjo3tMgAYPiQvvUk92uNL6PmnatKgcmPc1kz8KHBWgyV9ospJ0HZnUo4+3OABa83R
EKL/dHM+z8VcqWENdxicnJoO5XcNejncfkfBsPZgJdKw2Ci+36ZayY/M/TIvGSBbYe8c14HW36wJ
pay/dTzTKj1zOOSYzIF+qz9N5NCAcp+eIuV+mkgCyrq6oFJ+6YK+VnZF4hIpiIwsVhi/x/1ooAP6
99zF9yDJvGsRjFK+ERHuWqpVWFK+Af2Qt0P+pr/VpXvnWqvZDF9WVlhLtuNKQtsAT5lcfJq9eO0b
HENsCq3lE4e8Z+i3NLwBqxB/0OfyNhdlbXP0yn70vVh/e4VrHe8v156mNZNi29T+2ArEyYH9o1Mb
IXa4LYVWZZR8mkCYpb3THDRFiSxzMtc+y3oxfqMzoz1zqF50ZNbKmQlMjcdwlC9sWmd/kF87IMbk
SVNpVTORaPirvj2E6h0uqyshDAVIRT4jqj0+s5GPqJLzbBmfSe9o5CfgRHfrXf8KGG0QqTRKY8FN
2HiTJ8EpBO+CtfdPvKDBmY1s6OYbnyLavcq7O682PQWhZja04a/IKn3mxt2DFXMnjE6xJOqtpmaX
0Sl3sc8COnMjIkuIsrMTMmFy5T/lE3oCE4avVRcTrdkKBnK+hOsRPlqOvBVb9O0qEqr32O/SRLNk
9+mxrZ5b8KA/TbtuLtVPVytfU1/GxAnMtjneEfcxg5f2QGZcHYnjYgLFE1C4pVl0hv5JO/mtd7uQ
uzowCp0ohTfH5iNd66vrChyCymFU0PHWTxyyElGLExvQylRxK6K9aA69kFONQpvMBnHT/vLBkcme
m5Zqqhq9e4DjVdGP8XRez7pd+4vtHSFY28g/Gz4cy9nHmu49Ai4yMeyfiayIlo+3FkHgeKMdNjZg
fcqtJJfaesS0DfG0lOYziV5I5vfaDIMKvoZAO97TbcBoKPyjfQU6CaN4/GslewOHbAz4R7jK75q+
r9kjxKaujOzWE6mScdqW8Nljw9OchXrT/XGF7IONp0By55qJfBfmmY/SVi6zxAU3eWxO8zkqjiXE
v0mca3fMSv/3NHkBBuz1DC5uKWWcWUtEWs3rmvmVmo2BO3wk5KyiJ0CY+sXpIPJNWrJ3xJudFDSn
TMYyN/A/7wOfRHVFOsty+TtKC6uxTrfJ0kkNXjUiBBbX7iixRfUphj/40MSnme4E9tr8jHavoTgb
RYnN7gw/D4fbYCCxe2wAREP4slUYfWirJQuJIi2qfaO+roLePQRfGHYZ/yEjw/fXdOCTbOaYHF39
16J6uCwpmRNpWofskaFQExftFPWNWXnQ3itX4y8VDsTqXxpGpZ6PnIzBahL/NVcw7lD4HRza0MMP
sD5UNgFtMBJ+tgYgHRHJ14XFt+gtUoM9owJTgp3tOEDcXhSssjiZ+3HMXqw8EdA5TmnEEwiurKjQ
NjDHgPR+gb2fK5fa30tTch/F+DMrHHblzvzXRPRuHZEpPp8zQKni+g5h37AuWPoNKbCuKCp3KPLg
HifO7/0C4akZk1xj0BKcBBGnTkNxf82V3sZ4FiASeeeZ0Mg91N3kQAMk8SGR5lvB+jVBjnfw/fck
X5sLxrbu5d2jkGuVwICzSwYFT82rQopfDjkwoBRifDrC3PN7QTs6OaT7mOMelcXGz90PRqa8XYKF
ESbXkxG4RZhOGq69N9ww2Jh1HxtCz/C3Pox1bYL84Rh21nQWL/M4AdqPa3TjPy1ByNeKOpblHIIa
kRfhif+m/XCogtYr/HbQobo6AV+D8gUoFPRYCWi7e0TE8cy96sCRD1CW7zs1um5+WCfvQvahMOtc
fD1dYsv21LTNNVvv3ukKu00rUU91ZZhh1l3kM28ytkOOA+mn5MKY9d6lHnxeFQym1xPKpeGJlbZ7
lylllP7JygRK3g/ct7C3WvjdrkeNeHTXhePY11psaWQc+SEZ026F+r3sDa23bTHSURZyfkDNy7Pu
2i47LUSSBTgq65a+JVVOwbxOriLcX0XF5KMFVKWvDfJSqrtcccPskyfG4OJSb6dswrJvgXzBQ6sc
YipV2Zs6YUsaPVMhQalV+dadQOa4nH88webLDLyT/gr9O3JwEifho9t40BQQ0RJtqJBXixTY38AY
WUYcXj4wIFUrk7UlAHMS/I1Hq6coiuNfMe46V28800njtV2tFFOXVmWs+qljAWH+DOfx/JmRtt93
zdNDtyrqUr1md/mvCUuO03HpdigqT5BBYp0T8ezpAGKZf/68fxD668FgiCFkXiFdliKuay84tQ3M
XV/HPtBbNA6laGbNccSXgbLeg8MMJBYmJq5tFLh1DGtBqBFhuHW4VEONCGUIzxHhmoWpz46QTHDR
bzMpouV/79M0YLLENoP7EePHS3darLbR+eiR2L4BXcgA8r+g6OAhltk91CgxMGx77ht6TAFouGKi
V5e4mtVgRHbx31qdBuHqoAwaX7zB79F6O4I1es4dARtaLZGvg8RslJohQd2/T16F4Q+vGLw+NNv8
ZXxfynHRvqzeaYOe/eNmR3Vrc3KTN7tYhzaNrUu0l+1G1uMCtlB0sftPwvjxOMcM6WMno//Btvnm
Kqr2IiN4RjHws5rOgFe4s9nY+qc90cqhPB0roRIvxW/YlzooSsmNGrbFzpmJEd2C8zLxI3gvKjVp
wcr58Ko44zgBNKMp6792J1hQBBUlwl0QtV8su5moW125o1laE4uElw9Yw/VOwMBWKnzV9q6HrPlt
l1rM27VMy2Hh/mGskaDkHj9nf/ATz2qal+wfHMxuNue2W9+9KeRsq/D5+9+NrMOLE/Ak2BeTGZge
td2tzAIGw6S8dwYG2ZymzprdrVFyPYjPoxMYhDuNjXhsd7JXrRdBFVvFAGgFHE3USRxsCJO6is3W
fOSf+CD7hYrjEwTaijTYqvJgBSQ8mLaorYf8nWuSCoi1wuwNlS+SQEprCza4rhxhyjlaiXiiH03e
BidYlto52mLmm4N/EaCSDueSqBna3hjs8pV6yeFa83R8IVEx/JSPl/nXCBJuMQiq74JBSaWtXhcf
yjMDqtCkFX69zCuotSqKpv8Ld4/iTFzfis1P3GqJzupYngkiLTGAqgLSnnFKLltmtIQUlj2sS9If
v6Mq/Xdgygif1oB/wPgcyILN4L8HJjcy5s6M5a2I4AThxVpJZdorgvMqigWA3vVYyWLEhku+s4xy
+rNUzyiAyfMbFbhg+/9eolXfdASrxCk07kb6FkUvdtxgWxDNUNzRh6RSC2uk5Dpq3bm82qZOheT0
1tkhHO/nGHbNgE+khxsahShb2a9TQWpGKzSzfr66FqZMFAuRVRmBz/A1AeMDHaprBOAyaw5N3iQB
MTLP66pzElBY5+6hRsNerljBsXmdrHJQ7Lu695Ubk89RKDoLc59Skq425pSOOQDU6RtnP7EZx82C
W4R3GITkLELBsCCihAb2PT4qXAkX4n40RX/dOJnAKzcukO4jMCPTAe1Jv1bsYizd8SFSJsM6M7cM
pSp+kco9TOdEfKg7CDYhV+znT+U9VdQreQ4n7mYGjxePGl3I4HrwWAR6UvVuerTlet/Yd5qzGdi1
sqIZJQsapQIYbv0hHtAWzg1YpomTOC+joTf8nwwgHwe/tKSR6xbbVxchTFWeXBcOQrWJMlxD+Sw4
dpv8xg1R24tszNrt+nT9C1E/XXWKYeAbYcbM680A4aPo/N68OCwLV/ZDBZnBaNm1WG9BowvJ7g4J
85UhZYfWtwcncMl8vHYNF5dp51VpZ1TWmJu01wfP/p9e/1DrvWW2KsDL+xsTRPadtHESp3Z3OmBp
3MX8Gdqb+VyKko5iFnNuohWsBbH9JoP1v4i3rkETMsYK38IIZuGs+PPc7ldRJmuuUIBbHfiBxOhj
5fSOE/scKvAVlaiq5K55jILKfmJJdLp+QngdJLGwFIGTaNvY/7b1pXgV6bdmWTAtOrgkWbct+L6G
3vxNLxx/JOuS6YiekeHKkU6RXZY8iv/bWK9aZiM1yuuwSSE5rW52937tq5zsMc7WxUohP7tOvZnm
eEH1Vk7ncx3OldN++55rtRxtcyBOpr/B07nwNOB/+SA92J6Q6eY4F9PXCXq/2Dv0HQ09MWpWHzaH
UkeqZUFTXD6J/Da698VUNHV4e6yva5Dd83WzVoASBF8A1+ShkqrKLgZDV5M+eei/xMY/neONB2m0
zDObSNyUWh7zBUEmuN5KyxwKc/6mJY0sCGPopWkCuiCIUWKp/o9aIILHOzTa7Lz7bB44+h+QFhK3
AHD2mBfb0as3MbdYK2XJ8HT+0dk+GRR2Ezfh3/hWvUb/v2vm1hbTlE4BMy1WXj/Km/uw5b5PJPmR
bbDAVaG3Ozu0eEuqrYRcoUgGKJcnVpCnrS3dkItvIIad/Kc3ckQGKHXGXMnIqZjKbQbAV6idkmpx
Ke7xgp6tVeMNZbRX8FfnaN26Qqrbnu3QHhWgAqxHbfsbZYOxv7trxpNkkc9QTPNIT/SXtPlkw8KM
g+leguSAeO9PiHMUNPq1hOsly4u4LXMvyaC/y7QpY091Ga2JtBfivhOGXoJf0/ymhasCB8PJkNpF
XfK6uBqocxPIi9q1P++zy+v44ppAVOC3WBXRSG7Nv/0i1M0e9DGrMTN0xqS77P1Q2KxyIYPNztnB
Mk/hlk7B8pPRFBCsIZi4XPhOM9WhIubZx2X0lVUFfwmTUiAG+2xSkfLvhSe9L7a2JRrXBG+afdUO
ZyZRwVwoCZsXRNH9885fxPM/Vk0e2sPG52DTdpr/toYge2T0w4lSbPjM0azMPF3u9pjlhijUO/HJ
YAXfAWExcUPYVFINx3VoblMyW8KdB0OG9Ln4gO4wi9uDJYjWflT1oqqKDIUQUGTa07drPCLcw2ma
OOQFUHeAj4DdkDWRMTRnXemw+/uPIzC0g8+jb79htiuJFOMfTmzdsWF2lq7AsKJV8A1AbGMPQ2mu
P+thAoA8wRxo6V3MwJ+A2bDR90prbYC8hgJFCFX1JG0I4s1M4T4zTgNjJMpJ4pIlXuJisfInq8Nu
WlVxhZ1597dN2I/YUMv09W94ow5xJxf57dX8fC4znMYtqKydKYD1wtn3jOmYUVvP1WdDNtxCCjvF
pXuek7kge+mwkCIb37t+JrNdCqCTEf7kplic7i9lMtFRTsxP88oPaoQ94WKiQtqUx8vuhgRqD7nR
B9nEED4Y9Cf2Z9ENfjQiNmOH0E4366LQKm+QqzLcmBZL8dlQNIaKktMfjaxqoutobWcoa+xsCziX
ouHtfixmYDq6b0y1wint6kIJHxPn6P+mIkSdveQp4eDVQgr8oy5Da/UQOaJhR1TIyb/kCnHD5FK/
dkAQ8PtZOBUAxzPsnUsK3+XyKRNcQMXT3EOk0Ckm9qJIinjK6vpaqRYokF4xCghoxEGMCU2PetuK
tTGNVLQ0fil/URrmmkxKoezaBQ60kDK6XJ4vWHWtkfU4S4k/gB/2Yi/VE3VSOrE8H1xBF0+NtVi0
zqF3oDnUFFfvMNJP6YNjRlI5GeSkdZ+2iQJfwAPUF/9eHFh1xMoVo2xAiHVITdthYtgUtrLlvBDL
ugTOj4cIwnbXhv+MzC0kKkLmCrS1oRxL5u5sx0xSJLNWbF3iPe/YLZckkoBJtT65g6JyK5Mxvf/X
GT3/Th/gTW32OAtzZuHB4BeMDJjD8EMOh9J/itv5Lhxj7arwWxYhWKbWJkJkSu1q/pWMJg4YjCDe
Fv5zoCqw7rrWgb6MYO4XvVUOGe/BuPs4prX77HuwZsigBvU5czfZXxworkUqrbVtw59uStw7dXIC
+nOttoft1BRRdHmOoBSjd9p0hlRwIeU9PSyVkCVQrdEDvR8V82/0AJ+HLM94cZeKQUEsLKRVJBpT
5h9pPaZi1/LdZKjCgbWNwEJZc6r9jmm+BNXDRRSW+SesduqJOWo1H558YGJIRioGaymRGDBQ/3d1
9S9d2JKXHmFG//0XxCJSirDBCmTEfRyJZDY+rPUvX9nkK2vrxCf5IP9WCSqEpUNIDim7QWwFpTD6
HYcRA7E7BlW6+6zemVxgPAL3MF5uzFQxtpaqVSWCejE5oJtr2uN/Al5L4pS30j3h+SYN6iDEQQPA
bsuJC73vRFq0k4skrDSb3YzkuPZig+Y3ysOTal8dJn+wVqcyaUvbIqKhv0fSuIZQTXzQHprlyceH
bjhCVei9JzeXTMR7UdJuEfCWlUe7O7V63OL98iPGPHMwKD5KxvW3of6O69TeSnWY0lpgHjImfhb+
Et5YQp2RgP5ktRtdvstnfCHUkksPKR9VL8or7J/yxmIB5H5tq91ifBQHvjtyTD3WoJXrY5Eg5iSS
IuBikKuNtEaNw2Jx716SSdA86Vshd7NMb4RpXPe/Ergd+f7W5mFA/ko05S+qPN6hPbYF7sWivWm1
PgMvCjNKEhOMxfk0Xpt3lEcFcYzZM0qPNYGsgjfRxAykoz2jbv9JlDvMJcbsgHj23OQkA3qJcrLK
cBzJ/8yFkcU30bplW4GHQisjtEnMyZH8sxlyfVlB8SnA00ChJ0E5OIpq5+Wv2Z3SCw1L2kc2SX5l
otJj9g2WoEGVX4r3sAUT6LdcMUSR8YaB+GT5AUAGyncNzD+EFJQjvMo6HvXAa7UmSkHkTOFmPzfD
QdeiJNFBuTCH6UiKOQd7uxaDKwWwGnj0E1VxuRye+gWjjqNp5Kxb87qySCEwBJBKkN3REnKEfsso
oHAoRg6POe03lyYpyvxfIiiKjHdWIcGqqk9zZpfDyMdOJxr/1d7kZ4578pQ0dxibYmaSDSRTehXQ
7ndHzhyVUNejSAr4ya9ljXou34bQWWwHosNS38gPcFW651UTqr8CrDTZyc+hAyIhJwQU0k1qcQeo
IUCR098RTWTmKfcjavVyWNgw06E2TxuztiilgDagTJYFXAWaOvgr4yWsjOMG688kdXBUgZCsDz+S
kW/WIqTBHigCof/5BAFxLA9uL9QcTkjBH3Yqfyvp7elNtsNxn+Czs3xLAR/7YsGy24QH9G0yCgSp
twfj0cNYBoT7MZkJK7BIHJQ3dJ5i6e5Dsj5957YFnRohLh1i8M+aNBIdCzrM1iadYh4ODofBMr/s
v1bulQExGmzfUFiT8+jsJqZdGeIvjfEXBTBBvMMCTnZfQCiPpk99tC/UcA9UVOOrwpk1FndRP16+
g+FWWgWsJKby2me0ArPL+gHlxnmoxGbJEry6MaTdmv72GqX41lQ9tlW8hhpJHuB06bQEVejcw83H
6VWgOQb/WO1DDwEJMlT3Lky1Y6mfc/TEjqwM4k1D3J13rU7rsR/s53NJ+gwN464Agq/bwH6TU4fl
Gi2HXfzrbf4vxw31L2bWzBFPdIiK1v6+L8upBKRMkLDWR1x5DgVtGouvTD3nBOfbmNhgvKBzwiZO
BK3KRSgWGeR3XBEohsFbTVvxoM+EqoWNglDLDZyxpRy9OHGh2CptocSL0XH21wdw7xaKd8F2z5Ac
Tg370uhbSz474RBclSTExQPFEQcif6wbcepjRCqhq/EaEssWcbPffPwh2v3A4J60M0ApvGwzMwX4
1cJEFYmJHgDYxSYmItf6lgpn4OfY/M37UJOQmhTp0j4X4Q03jOpnqIenxOek02JkFLjPtGUWMBJ+
N38VLanZRt2d9b5cOMVQfajQpnbh9bIK8a200vQ/yC+jNyNcshdQW1X3qGqqmCqSr+zTmzZbl4rd
kAmFxAsm181VxvBm1vd3KtRCz+fd27tCq9h41SPJZV09DoBdybQ83vPM5sliN/Aj8oQM2bdFiOOo
KXXzCJpJlW5TGfG4Dxrh1xyhlDh8mGwluaHhE9slWCQ7ayEgjRGeqWTT0c9RSjAlxFNKc18DcFjs
a4bvyhlJ+Q2KhPWbcON42iqzFEfW4CC8NrCuCIkuvLhdF8eXtcHlnbrHBywdPIJ4QD9N8FbWQnhJ
gazao0jDWtTv+Hc5ub8Z1fAfUpGPlXPW92zOf9ddKs4vX0dRK8fWxz0D95/82qp7MbDqkvuhO7Yo
dPQWs+QHDr/bUgJSmoZR2Bs+kRFLgidsq2S8DldaRbUcxPk86k4kZmcwyTTM8Z5UdHCwO8ivUVM7
lvZ+OTXZFdYPQ4CtRMZxt9Jjapi8gH5dHWC5lb704+QNN6RXFzNCMcPcIHLeGoYaJeKIAJpFquU0
KoFOeYd79Me7obeFsU5BdtzpC+JR5M9wmeeKpt/pG6FuG7qIQfyFDSoJpDptqEUS7+OY+dxLo/Ah
frH7SiUPBFAt+p3kHGapWL9hr/JcLrhbMXHYRsF/HqsjtFg/sXaa8w6I63+GWw1SZcDRUxCAP3mC
NqEg/F6r8TP4jQ1Oto3AxSTqBBILRfeIBUFrXbgdYRR5/8aUUA/YYGW1CDkqKi5nqmARTu5r2Gak
kEUOmF+wDQ1mexGv3uWyuGSStto5BLO69RYaO+8m1J+sa5MCDCiQKbjufNpUTbYlzN03WHeFVXLy
AE3YbrNJOGjgbVWY/kpri7kedlmQb4crWSwDZBePS6IyQCI7opf2HLFMnmi4mrqwYeZjkpPQ2JkF
VBbKF4ZGhxegrEM4+PctredlrnUdTVMZrIDiTi0EP/AlX2jiFwEEaUkNJQJv1f6Ph2/A65vcALxG
dAJ7HSxXV1QdCqFGMuLCF39qEOZ0dLdYVI47uc9jMESvOwjUt3rxL/OK6U2wiq6O4rkqxzvnGDul
PEnwVi6sAvx0KjC6vBP2W2YN9GavCUAUVQoFGwxde52ys1Rrnielm1cJpu8JPrDPxcA9kiMeTPqy
gYbey4d9nPJkZey1DBnkrdYTdDELkyMWNZ+I/U6NnOgBxPZ/ZMseFrF1SlbBHQAEJNOMjZFhw+ig
9Od7zd8ZiptdGoZyS/6mWmnL+N7xlTRm4mgFa4u1tEr5Yu2oErXRG378Dnp9wZXq456u7IaQMU6N
f389+4s1QHFyDvfuXHlJVcucOjVhRngdAX1T2Wd2mEQQX4p8CKy5YBrJKcP4FD/2qXoINjHt17OG
Vj1sz8uMS/0aZATjxDLH3BFNy4drJIegZyF1ZB3MuI6MzsqqUpN8k/vk5Armpg6woYvrPeiN4ekz
F9J1+3ZtntP01xk3ZZBFkA3pGfF0iwk+lvPu9ysnPEdHPIkzPrT8YgPF8b4FlC2/fnOzcbAMD4St
Y1xCyEZr5w2QRN4wP5KPeyUw3NWozGW3diGjaE4dKZ/y1LZ2ux28GcEIQyyt24hBM23qINeJYwQf
3mQcz7OYM0sPPRhi0aQ4EEZcsu0IPF25lQcx1ClkR2/w1+GHWixcHYwVTOzKFkwNdzPGzooNygpe
Uh5OZT426KjElgGpkRwhlUfjDQtuNPkhSq2KcsajTLmtyAIhDjWMMQCU+8Cpzc7b1jt0qetQtFJN
59U9XiPGulwcu017h4TcmDAcQHg9h2svWZ3DwnfTiqACMtxTN64t0lfJsKdzyZd6vcCo4ZOQDySV
38H+s8ZLs7KnveKQxK8yhXlDBSvaAFNys8C7DeWZv/DKEhXS3725cAjgAvzgzZejAzkJ2AGA1AUU
6XDD8JYamkFyzpSF+R6ChQOLjavu3Qm83VBUvN31zW53JLRYOzri+faFy6994jwuYoVc2bIbCtp1
WwzQLpCOWZtGYZ/XlqACvEigIWPyPqlX3YtvVyyy5ng7sakbFuyEYEFe7JRP85n6+rcAB2OFv+Ct
9ck3udEJZUIJsC8EbCAb21bkIBRuTkBkLqR32X4wNlOPPZJmmE9Ly9TSuOlAoLAC11V4pkupab6O
Mf9hExadpXh1PaGB2iEMsoAbNXVOhfdb5t3N05i+5wdSlHiEyr6P77Bu49cwI0lP/zbazoKCETXV
XGQpdIuBQR7N8l8WZoP4P64styLpJc1J4w5sjrH4pSAwVVph6rvHXB34PMWDDLXZ7wd0CQFeD1KC
Dvp83t3G5Aq9ZN2lqy8J/bxbjuB8+MUbXK5y5BuJMujUwHuEhj1cJWBV0+kHB6E53LTTFOJAGrlR
+Nhsbj5SQUFoHrWcmEUvsp1YjNuBC/ZJidoKead2rLzLVi+dPUyU7axJmDHW23Wbt5J6zGkHIoMl
thTuqZMM6qNE4KWVm259pZSz41iXZmGu0HldWwgvpZVcx+8g3MqwbIiGBeWMapvBOGBl2s7BU6fj
DnvFaNdGSIZ7l5IAM+L1G4P8XKZ2MT8GP/DVQEK3KmIvKwRrvjELyI/uvf2ZT3KzXMyL1E3l1eoa
OR6ZjRVpafg1U985zJw3aWtOEYggEk/QhH5eKcZRJlW0LrJeeLsyF1ffCjQ27A3dI9V2Yn0iP7/N
0/Cfsey+KUDpXU83wxg6PIAswhqgz5Vj+GiTkBp1MaCiaX25cq/gk9l7Trs5NiFfWorBPRmaF3/L
su3AoyDllw==
`protect end_protected
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Floating-point package (Generic package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary floating point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.fixed_float_types.all;
package float_generic_pkg is
generic (
-- Defaults for sizing routines, when you do a "to_float" this will be
-- the default size. Example float32 would be 8 and 23 (8 downto -23)
float_exponent_width : NATURAL := 8;
float_fraction_width : NATURAL := 23;
-- Rounding algorithm, "round_nearest" is default, other valid values
-- are "round_zero" (truncation), "round_inf" (round up), and
-- "round_neginf" (round down)
float_round_style : round_type := round_nearest;
-- Denormal numbers (very small numbers near zero) true or false
float_denormalize : BOOLEAN := true;
-- Turns on NAN processing (invalid numbers and overflow) true of false
float_check_error : BOOLEAN := true;
-- Guard bits are added to the bottom of every operation for rounding.
-- any natural number (including 0) are valid.
float_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
no_warning : BOOLEAN := false;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (<>) );
-- Author David Bishop (dbishop@vhdl.org)
constant CopyRightNotice : STRING :=
"Copyright IEEE P1076 WG. Licensed Apache 2.0";
use fixed_pkg.all;
-- Note that this is "INTEGER range <>", thus if you use a literal, then the
-- default range will be (INTEGER'low to INTEGER'low + X)
type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type
alias U_float is UNRESOLVED_float;
subtype float is (resolved) UNRESOLVED_float;
-----------------------------------------------------------------------------
-- Use the float type to define your own floating point numbers.
-- There must be a negative index or the packages will error out.
-- Minimum supported is "subtype float7 is float (3 downto -3);"
-- "subtype float16 is float (6 downto -9);" is probably the smallest
-- practical one to use.
-----------------------------------------------------------------------------
-- IEEE 754 single precision
subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23);
alias U_float32 is UNRESOLVED_float32;
subtype float32 is float (8 downto -23);
-----------------------------------------------------------------------------
-- IEEE-754 single precision floating point. This is a "float"
-- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and
-- the fraction is 23 bits wide. This format can hold roughly 7 decimal
-- digits. Infinity is 2**127 = 1.7E38 in this number system.
-- The bit representation is as follows:
-- 1 09876543 21098765432109876543210
-- 8 76543210 12345678901234567890123
-- 0 00000000 00000000000000000000000
-- 8 7 0 -1 -23
-- +/- exp. fraction
-----------------------------------------------------------------------------
-- IEEE 754 double precision
subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52);
alias U_float64 is UNRESOLVED_float64;
subtype float64 is float (11 downto -52);
-----------------------------------------------------------------------------
-- IEEE-754 double precision floating point. This is a "double float"
-- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and
-- the fraction is 52 bits wide. This format can hold roughly 15 decimal
-- digits. Infinity is 2**2047 in this number system.
-- The bit representation is as follows:
-- 3 21098765432 1098765432109876543210987654321098765432109876543210
-- 1 09876543210 1234567890123456789012345678901234567890123456789012
-- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
-- 11 10 0 -1 -52
-- +/- exponent fraction
-----------------------------------------------------------------------------
-- IEEE 854 & C extended precision
subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112);
alias U_float128 is UNRESOLVED_float128;
subtype float128 is float (15 downto -112);
-----------------------------------------------------------------------------
-- The 128 bit floating point number is "long double" in C (on
-- some systems this is a 70 bit floating point number) and FLOAT*32
-- in Fortran. The exponent is 15 bits wide and the fraction is 112
-- bits wide. This number can handle approximately 33 decimal digits.
-- Infinity is 2**32,767 in this number system.
-----------------------------------------------------------------------------
-- purpose: Checks for a valid floating point number
type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)
quiet_nan, -- Quiet NaN (C FP_NAN)
neg_inf, -- Negative infinity (C FP_INFINITE)
neg_normal, -- negative normalized nonzero
neg_denormal, -- negative denormalized (FP_SUBNORMAL)
neg_zero, -- -0 (C FP_ZERO)
pos_zero, -- +0 (C FP_ZERO)
pos_denormal, -- Positive denormalized (FP_SUBNORMAL)
pos_normal, -- positive normalized nonzero
pos_inf, -- positive infinity
isx); -- at least one input is unknown
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers.
constant fphdlsynth_or_real : BOOLEAN; -- deferred constant
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate;
-- Arithmetic functions, these operators do not require parameters.
function "abs" (arg : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Basic parameter list
-- round_style - Selects the rounding algorithm to use
-- guard - extra bits added to the end if the operation to add precision
-- check_error - When "false" turns off NAN and overflow checks
-- denormalize - When "false" turns off denormal number processing
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- reciprocal
function reciprocal (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Square root (all 754 based implementations need this)
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN;
-----------------------------------------------------------------------------
-- compare functions
-- =, /=, >=, <=, <, >, maximum, minimum
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ne ( -- not equal /=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
-- Need to overload the default versions of these
function "=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<" (l, r : UNRESOLVED_float) return BOOLEAN;
function "?=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?/=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?>" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?>=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?<" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?<=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_float) return BOOLEAN;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- conversion functions
-- Converts one floating point number into another.
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function resize (
arg : UNRESOLVED_float; -- Floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128;
-- Converts an fp into an SLV (needed for synthesis)
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
-- Converts an fp into an std_ulogic_vector (sulv)
function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
-- Integer to float
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNRESOLVED_UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : UNRESOLVED_SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNRESOLVED_UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : UNRESOLVED_SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- sulv to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- float to real
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL;
-- float to integer
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL;
-- Maps metalogical values
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float;
function Is_X (arg : UNRESOLVED_float) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These two procedures were copied out of the body because they proved
-- very useful for vendor specific algorithm development
-- Break_number converts a floating point number into it's parts
-- Exponent is biased by -1
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_UNSIGNED;
expon : out UNRESOLVED_SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_ufixed; -- a number between 1.0 and 2.0
expon : out UNRESOLVED_SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
-- Normalize takes a fraction and and exponent and converts them into
-- a floating point number. Does the shifting and the rounding.
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
function normalize (
fract : UNRESOLVED_UNSIGNED; -- unsigned
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
-- overloaded compare functions
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
-- minimum and maximum overloads
function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_float) return UNRESOLVED_float;
function "and" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "or" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nand" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xnor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "and" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "or" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nand" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xnor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
-- Reduction operators, same as numeric_std functions
function "and" (l : UNRESOLVED_float) return STD_ULOGIC;
function "nand" (l : UNRESOLVED_float) return STD_ULOGIC;
function "or" (l : UNRESOLVED_float) return STD_ULOGIC;
function "nor" (l : UNRESOLVED_float) return STD_ULOGIC;
function "xor" (l : UNRESOLVED_float) return STD_ULOGIC;
function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC;
-- Note: "sla", "sra", "sll", "slr", "rol" and "ror" not implemented.
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : UNRESOLVED_SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- returns the unbiased exponent of x
function Logb (x : UNRESOLVED_float) return INTEGER;
function Logb (x : UNRESOLVED_float) return UNRESOLVED_SIGNED;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
-- Returns TRUE if X is unordered with Y.
function Unordered (x, y : UNRESOLVED_float) return BOOLEAN;
function Finite (x : UNRESOLVED_float) return BOOLEAN;
function Isnan (x : UNRESOLVED_float) return BOOLEAN;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- writes S:EEEE:FFFFFFFF
procedure WRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Reads SEEEEFFFFFFFF, "." and ":" are ignored
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_float];
alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
alias BINARY_READ is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_float];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Octal read with padding, no separators used
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_float, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_float];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
-- Hex write with padding, no separators
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Hex read with padding, no separators used
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_float, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_float];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
-- returns "S:EEEE:FFFFFFFF"
function to_string (value : UNRESOLVED_float) return STRING;
alias TO_BSTRING is TO_STRING [UNRESOLVED_float return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_float return STRING];
-- Returns a HEX string, with padding
function to_hstring (value : UNRESOLVED_float) return STRING;
alias TO_HEX_STRING is to_hstring [UNRESOLVED_float return STRING];
-- Returns and octal string, with padding
function to_ostring (value : UNRESOLVED_float) return STRING;
alias TO_OCTAL_STRING is to_ostring [UNRESOLVED_float return STRING];
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
end package float_generic_pkg;
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Floating-point package (Generic package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary floating point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.fixed_float_types.all;
package float_generic_pkg is
generic (
-- Defaults for sizing routines, when you do a "to_float" this will be
-- the default size. Example float32 would be 8 and 23 (8 downto -23)
float_exponent_width : NATURAL := 8;
float_fraction_width : NATURAL := 23;
-- Rounding algorithm, "round_nearest" is default, other valid values
-- are "round_zero" (truncation), "round_inf" (round up), and
-- "round_neginf" (round down)
float_round_style : round_type := round_nearest;
-- Denormal numbers (very small numbers near zero) true or false
float_denormalize : BOOLEAN := true;
-- Turns on NAN processing (invalid numbers and overflow) true of false
float_check_error : BOOLEAN := true;
-- Guard bits are added to the bottom of every operation for rounding.
-- any natural number (including 0) are valid.
float_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
no_warning : BOOLEAN := false;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (<>) );
-- Author David Bishop (dbishop@vhdl.org)
constant CopyRightNotice : STRING :=
"Copyright IEEE P1076 WG. Licensed Apache 2.0";
use fixed_pkg.all;
-- Note that this is "INTEGER range <>", thus if you use a literal, then the
-- default range will be (INTEGER'low to INTEGER'low + X)
type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type
alias U_float is UNRESOLVED_float;
subtype float is (resolved) UNRESOLVED_float;
-----------------------------------------------------------------------------
-- Use the float type to define your own floating point numbers.
-- There must be a negative index or the packages will error out.
-- Minimum supported is "subtype float7 is float (3 downto -3);"
-- "subtype float16 is float (6 downto -9);" is probably the smallest
-- practical one to use.
-----------------------------------------------------------------------------
-- IEEE 754 single precision
subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23);
alias U_float32 is UNRESOLVED_float32;
subtype float32 is float (8 downto -23);
-----------------------------------------------------------------------------
-- IEEE-754 single precision floating point. This is a "float"
-- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and
-- the fraction is 23 bits wide. This format can hold roughly 7 decimal
-- digits. Infinity is 2**127 = 1.7E38 in this number system.
-- The bit representation is as follows:
-- 1 09876543 21098765432109876543210
-- 8 76543210 12345678901234567890123
-- 0 00000000 00000000000000000000000
-- 8 7 0 -1 -23
-- +/- exp. fraction
-----------------------------------------------------------------------------
-- IEEE 754 double precision
subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52);
alias U_float64 is UNRESOLVED_float64;
subtype float64 is float (11 downto -52);
-----------------------------------------------------------------------------
-- IEEE-754 double precision floating point. This is a "double float"
-- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and
-- the fraction is 52 bits wide. This format can hold roughly 15 decimal
-- digits. Infinity is 2**2047 in this number system.
-- The bit representation is as follows:
-- 3 21098765432 1098765432109876543210987654321098765432109876543210
-- 1 09876543210 1234567890123456789012345678901234567890123456789012
-- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
-- 11 10 0 -1 -52
-- +/- exponent fraction
-----------------------------------------------------------------------------
-- IEEE 854 & C extended precision
subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112);
alias U_float128 is UNRESOLVED_float128;
subtype float128 is float (15 downto -112);
-----------------------------------------------------------------------------
-- The 128 bit floating point number is "long double" in C (on
-- some systems this is a 70 bit floating point number) and FLOAT*32
-- in Fortran. The exponent is 15 bits wide and the fraction is 112
-- bits wide. This number can handle approximately 33 decimal digits.
-- Infinity is 2**32,767 in this number system.
-----------------------------------------------------------------------------
-- purpose: Checks for a valid floating point number
type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)
quiet_nan, -- Quiet NaN (C FP_NAN)
neg_inf, -- Negative infinity (C FP_INFINITE)
neg_normal, -- negative normalized nonzero
neg_denormal, -- negative denormalized (FP_SUBNORMAL)
neg_zero, -- -0 (C FP_ZERO)
pos_zero, -- +0 (C FP_ZERO)
pos_denormal, -- Positive denormalized (FP_SUBNORMAL)
pos_normal, -- positive normalized nonzero
pos_inf, -- positive infinity
isx); -- at least one input is unknown
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers.
constant fphdlsynth_or_real : BOOLEAN; -- deferred constant
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate;
-- Arithmetic functions, these operators do not require parameters.
function "abs" (arg : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Basic parameter list
-- round_style - Selects the rounding algorithm to use
-- guard - extra bits added to the end if the operation to add precision
-- check_error - When "false" turns off NAN and overflow checks
-- denormalize - When "false" turns off denormal number processing
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- reciprocal
function reciprocal (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Square root (all 754 based implementations need this)
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN;
-----------------------------------------------------------------------------
-- compare functions
-- =, /=, >=, <=, <, >, maximum, minimum
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ne ( -- not equal /=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
-- Need to overload the default versions of these
function "=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<" (l, r : UNRESOLVED_float) return BOOLEAN;
function "?=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?/=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?>" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?>=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?<" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?<=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_float) return BOOLEAN;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- conversion functions
-- Converts one floating point number into another.
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function resize (
arg : UNRESOLVED_float; -- Floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128;
-- Converts an fp into an SLV (needed for synthesis)
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
-- Converts an fp into an std_ulogic_vector (sulv)
function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
-- Integer to float
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNRESOLVED_UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : UNRESOLVED_SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNRESOLVED_UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : UNRESOLVED_SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- sulv to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- float to real
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL;
-- float to integer
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL;
-- Maps metalogical values
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float;
function Is_X (arg : UNRESOLVED_float) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These two procedures were copied out of the body because they proved
-- very useful for vendor specific algorithm development
-- Break_number converts a floating point number into it's parts
-- Exponent is biased by -1
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_UNSIGNED;
expon : out UNRESOLVED_SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_ufixed; -- a number between 1.0 and 2.0
expon : out UNRESOLVED_SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
-- Normalize takes a fraction and and exponent and converts them into
-- a floating point number. Does the shifting and the rounding.
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
function normalize (
fract : UNRESOLVED_UNSIGNED; -- unsigned
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
-- overloaded compare functions
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
-- minimum and maximum overloads
function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_float) return UNRESOLVED_float;
function "and" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "or" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nand" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xnor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "and" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "or" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nand" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xnor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
-- Reduction operators, same as numeric_std functions
function "and" (l : UNRESOLVED_float) return STD_ULOGIC;
function "nand" (l : UNRESOLVED_float) return STD_ULOGIC;
function "or" (l : UNRESOLVED_float) return STD_ULOGIC;
function "nor" (l : UNRESOLVED_float) return STD_ULOGIC;
function "xor" (l : UNRESOLVED_float) return STD_ULOGIC;
function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC;
-- Note: "sla", "sra", "sll", "slr", "rol" and "ror" not implemented.
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : UNRESOLVED_SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- returns the unbiased exponent of x
function Logb (x : UNRESOLVED_float) return INTEGER;
function Logb (x : UNRESOLVED_float) return UNRESOLVED_SIGNED;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
-- Returns TRUE if X is unordered with Y.
function Unordered (x, y : UNRESOLVED_float) return BOOLEAN;
function Finite (x : UNRESOLVED_float) return BOOLEAN;
function Isnan (x : UNRESOLVED_float) return BOOLEAN;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- writes S:EEEE:FFFFFFFF
procedure WRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Reads SEEEEFFFFFFFF, "." and ":" are ignored
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_float];
alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
alias BINARY_READ is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_float];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Octal read with padding, no separators used
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_float, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_float];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
-- Hex write with padding, no separators
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Hex read with padding, no separators used
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_float, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_float];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
-- returns "S:EEEE:FFFFFFFF"
function to_string (value : UNRESOLVED_float) return STRING;
alias TO_BSTRING is TO_STRING [UNRESOLVED_float return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_float return STRING];
-- Returns a HEX string, with padding
function to_hstring (value : UNRESOLVED_float) return STRING;
alias TO_HEX_STRING is to_hstring [UNRESOLVED_float return STRING];
-- Returns and octal string, with padding
function to_ostring (value : UNRESOLVED_float) return STRING;
alias TO_OCTAL_STRING is to_ostring [UNRESOLVED_float return STRING];
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
end package float_generic_pkg;
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_control_mul
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for multracting control units
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_control_mul is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_control_mul;
architecture Behavioral of hwt_control_mul is
----------------------------------------------------------------
-- mulcomponent declarations
----------------------------------------------------------------
component mul is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave1 : in signed(31 downto 0);
wave2 : in signed(31 downto 0);
output : out signed(31 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_addrESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMaddr_mul : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMData_mul : std_logic_vector(0 to 31); -- mul to local ram
signal i_RAMData_mul : std_logic_vector(0 to 31); -- local ram to mul
signal o_RAMWE_mul : std_logic;
signal o_RAMaddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMaddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMaddr_max : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal mul_ce : std_logic; -- mul clock enable (like a start/stop signal)
signal refresh_state : integer;
signal process_state : integer;
signal input1 : std_logic_vector(31 downto 0);
signal input2 : std_logic_vector(31 downto 0);
signal input1_addr : std_logic_vector(31 downto 0);
signal input2_addr : std_logic_vector(31 downto 0);
signal mul_data : signed(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant mul_START : std_logic_vector(31 downto 0) := x"0000000F";
constant mul_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_mul <= std_logic_vector(mul_data);
--mul_wave <= signed(i_RAMData_mul);
o_RAMaddr_reconos(0 to C_LOCAL_RAM_addrESS_WIDTH-1) <= o_RAMaddr_reconos_2((32-C_LOCAL_RAM_addrESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMaddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
mul_INST : mul
port map(
clk => clk,
rst => rst,
ce => mul_ce,
wave1 => signed(input1),
wave2 => signed(input2),
output => mul_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMaddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMaddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_mul = '1') then
local_ram(to_integer(unsigned(o_RAMaddr_mul))) := o_RAMData_mul;
else -- else needed, because mul is consuming samples
i_RAMData_mul <= local_ram(to_integer(unsigned(o_RAMaddr_mul)));
end if;
end if;
end process;
mul_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
mul_ce <= '0';
o_RAMWE_mul<= '0';
o_RAMaddr_mul <= (others => '0');
refresh_state <= 0;
process_state <= 0;
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
input2_addr <= snd_comp_header.opt_arg_addr;
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = mul_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = mul_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when 0 =>
memif_read_word(i_memif, o_memif, snd_comp_header.source_addr , input1, done);
if done then
refresh_state <= 1;
end if;
when 1 =>
memif_read_word(i_memif, o_memif, input2_addr , input2, done);
if done then
refresh_state <= 0;
state <= STATE_PROCESS;
end if;
when others =>
refresh_state <= 0;
end case;
-- memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
-- if done then
-- refresh_state <= 0;
-- state <= STATE_PROCESS;
-- end if;
-- when others =>
-- refresh_state <= 0;
-- end case;
when STATE_PROCESS =>
--if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
mul_ce <= '1';
process_state <= 1;
when 1 =>
o_RAMData_mul <= std_logic_vector(mul_data);
o_RAMWE_mul <= '1';
mul_ce <= '0';
process_state <= 2;
when 2 =>
o_RAMWE_mul <= '0';
-- o_RAMaddr_mul <= std_logic_vector(unsigned(o_RAMaddr_mul) + 1);
-- sample_count <= sample_count + 1;
process_state <= 3;
when 3 =>
--o_RAMaddr_mul <= (others => '0');
state <= STATE_WRITE_MEM;
when others =>
process_state <= 0;
end case;
-- else
-- -- Samples have been generated
-- o_RAMaddr_mul <= (others => '0');
-- sample_count <= to_unsigned(0, 16);
-- state <= STATE_WRITE_MEM;
-- end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_addr std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
|
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
-- Violations below
type state_machine
is (idle, write, read, done);
type state_machine
is (idle, write, read, done);
begin
end architecture RTL;
|
architecture rtl of fifo is
alias designator is name;
alias designator is name;
alias designator is name;
begin
end architecture rtl;
|
architecture rtl of fifo is
-- Type attributes
signal a : something'Ascending;
signal a : something'Base;
signal a : something'High;
signal a : something'Image(x);
signal a : something'Left;
signal a : something'LeftOf(x);
signal a : something'Low;
signal a : something'Pos(x);
signal a : something'Pred(x);
signal a : something'Right;
signal a : something'RightOf(x);
signal a : something'Succ(x);
signal a : something'Val(x);
signal a : something'Value(x);
-- Array attributes
signal a : something'Ascending(n);
signal a : something'High(n);
signal a : something'Left(n);
signal a : something'Length(n);
signal a : something'Low(n);
signal a : something'Range(n);
signal a : something'Reverse_Range(n);
signal a : something'Right(n);
-- Signal attributes
signal a : something'Active;
signal a : something'Delayed(t);
signal a : something'Driving;
signal a : something'Driving_value;
signal a : something'Event;
signal a : something'Last_Event;
signal a : something'Last_Active;
signal a : something'Last_Value;
signal a : something'Quiet(t);
signal a : something'Stable(t);
signal a : something'Transaction;
-- Other attributes
signal a : something'Instance_Name;
signal a : something'Path_Name;
signal a : something'Simple_name;
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package maxfinder_pkg is
function log2ceil(x: natural) return natural;
component maxfinder_base
generic (
N_WINDOW_LENGTH : natural;
N_OUTPUTS : natural;
N_SAMPLE_BITS : natural;
SYNC_STAGE1: boolean := FALSE;
SYNC_STAGE2: boolean := TRUE;
SYNC_STAGE3: boolean := TRUE
);
port (
clk : in std_logic;
samples : in std_logic_vector( N_WINDOW_LENGTH * N_SAMPLE_BITS - 1 downto 0 );
threshold : in std_logic_vector( N_SAMPLE_BITS - 1 downto 0 );
max_found : out std_logic_vector( N_OUTPUTS - 1 downto 0 );
max_pos : out std_logic_vector( N_OUTPUTS * log2ceil( N_WINDOW_LENGTH / N_OUTPUTS )- 1 downto 0 );
max_adiff0 : out std_logic_vector( N_OUTPUTS * N_SAMPLE_BITS - 1 downto 0 );
max_adiff1 : out std_logic_vector( N_OUTPUTS * N_SAMPLE_BITS - 1 downto 0 );
max_sample0 : out std_logic_vector( N_OUTPUTS * N_SAMPLE_BITS - 1 downto 0 );
max_sample1 : out std_logic_vector( N_OUTPUTS * N_SAMPLE_BITS - 1 downto 0 )
);
end component;
end maxfinder_pkg;
package body maxfinder_pkg is
function log2ceil(x: natural) return natural is
begin
return natural(ceil(log2(real(x))));
end log2ceil;
end maxfinder_pkg;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
JJbTY/FLcWvFG4qgAoNcpDhRwWPWVIcrdtaenypUXGLd3oTJ/JQb2qOK7MhEJn9BIXYTqB7VuZqx
e6DtbJOKOA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
pkuc65r8e4R3tDFvu6DzbbJcV9tkzKLyPKKlNc65L0768LzwNnpo2u6urWESUnoi9BL1+672QFhe
09HpyRE2HkjzJd1z1kaLv9hyhnpCA9GwqIBhjYdIURpu0ubdQR1UBOHtZ3qQJhtopEW8hfZl7dvJ
Y8ZIhtD89bkLtifYcuo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Vbv7nZIA7BpS+vnUBhHjIBriv57jxA12oW/i+XeuxCefIWgUPjKwfT/jgTuk9x4kTDnFYG9VQgJA
VtZoz66/xCsdqRQDoQ10qRAoO8/bmYjo5EFj8HLZCaMHwnNycGiRqLzuqEpP8hc9/7GtNoYDio5m
nM3lZ9W+cruj/J1hSpa+RJrLzeP1aeCTCLwmO89oKq/O1BYM3VLdeOalavdHsU0pUGcgu8HzWLCR
SdQ9pWkfAsp7Xnb3DEfWbn7cbKq4vrloHtXtRL3H02ehrsta1zMWUmHUfZWHR/zYfH1511de3x2t
jWYmYjqwAzRhX1yazPjaksvtLLF8y0HVNSvv/g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Gx+MOr4EV4k2yU99PxwAq2OTo44OHCHTACh+KbLxozta18EIEYOm2aizcy8q9vNvTL12Dt3xoIow
fSgPeMSp5cpLLLfL4wj50qgEh96d0vuP1gicF7owPtTTDzmmaoQOyIUrRcu5H83SV1PGRzx91OCM
ebTdB4aNsgvW+Ha+ijM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IV8iYcOvJgxHLoDBVMEKBuLzvur6e0kUMX78pvdR3suIc2NXa6qopmoQxw6EhQbDzn3Lgr28RHS6
F/4sOaM/udVMaESTiiOo53fb3tcfucg98na/aTs2wJoWzFwFCoosNKzKFDj9ZOBKeNEgjO7cH+bc
LpDBEu93gBfteu7+ib7BYwxshNw/zEolst1iEv30DWKOWjb1H3GpyWziNH46Nx9GuNunynQSnnn6
uoCJkSbXvPCb7SInOjxdbTOZq9cv/tUV7UxkNwOaGFWd3K0bY02rIBsR/FjAO5OWU43QRyYq1MTe
A68N51229WUZVQiKp+fbj67HDpUnk4geJwAKzA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6224)
`protect data_block
oiwKMgI4JUZws9tNOvrRyukMIt7a4KLtDF3AjGAKRBdCG8QZ7+wbINzG3t2VzRz3qBSBX3Zi8H7e
HNodVfqPx/Dbt9+ri3bBCCG0uw2CSRChQRrl92MULyOnl4l7oArJsW+loEfgIK6Uvxyx/4kJiniP
nwFMgJPaWEZhVWDIstPOEdSACIOpWAHqh/B+/G6epDjVAWUpDvfuJXF0a4lqSDSAd8Tz3c3RpfJf
LQQtZo5tnAEcPzzg3rV5qtYcIgCj1xe2Cs3ipNRubJUv84B+nIXVon6vyKRqnA5KWvjBqaYZi3cB
lso5Z/cljAuiel8a8CEUaS1a5hEFQdKvb9PwJILDuDsEvolDr+SGe2hsy5xkD5XKZQao0KtMhc0e
C/tCWpjUmxV2oso7Tp+MWOFFsW9Bpgguj+NJTZ5H9gax5LAKJpBNWu3L06XSXqv8TGSzyYOiYq6y
LBoeIM+lKTvuz1iZscUIqIeMuZoAKe5lja3iKv97eDq0cs27CJWbKGjMXmkmLW6hvVw37aU+J47z
WiuXkiTqsSBHiS7AeeaBntsxjbA3DmwOSnoYAcJQ/6rOdtBoTNXyIHmTVS5ktg2q47bVS9qz1+ei
JZ+EiGs5ruq6rjyoMBMd8RAcVUmrZP3qZqP19jeKMNO8FtfEC3NInIwDkCxxF0cwx+dlQqrDC4KE
15b3kt2pO25rAIvbnC7wC+1gN8fjbmS9ClpmkymB9AV9qcrsiOEZtzs9RrJ4AmTv1Nri0VNjt8bu
T9iL2nkuXoeTiLcIM779Woq3lvhnR5wlT7JmlbuodWxw+LGHemM0SsNg5QZBBUKCeq+1AWLJS5Kn
27QQ0JiiwiorRcHTebIciFqgF4o2WRC8IqWn3LVE1CDQ0ZsBbmBgLY+moKzmZYZrIo2Q/+uwwlVD
8NsaCRoANFjYL00nE/YsGD5Cv2HYOG/xpevPoQVVDmvUwqZ/LnW3oPqcvbUhouwST8jnRLlhcJQS
AP0L1ZTu9XH7T4OoVfVUSP3rZi3rU/aq0ibky7y9gtDVzonFUXW0ZCMWo6xgxGa26db0YT3iYsri
vQ3MiLc7or2W6Jduf3dJZMx4OEvHf2kqKkN7c5wDQ7OsMllI3pJ6QTrx+w/n4V4uIUQk3KnjtnZi
1wwzyv+RA0ffuBJ+kpE40wSsZ6khPaRuxRSn2fwLQtYCEb91/JJF7lvGPT1k9v2z+du02ZljgYXq
Uhcw9UiD5QJiCGqGprZfh4Y/XX4c2sbuX+NqQL575uztdB++zXgXYB+ep72GXSALzQcki2Wa8dzf
7IJRcVFJlFd/ulariBr52YLFNO+gvTemuHE9gfNBWm2VH4x0wFbzClKRVWgBUcP40ZFDIDH2Sm2T
Wf6cYrGRr3iDWyd8clz4TtcCzMFgD6UsbN6gT6eZP3FrbKgSfq/Xzoyoa7BQEcA8yHvlifJN0In7
pzu2SQL0IKkDrec13uaOv9D8d4L35z3bXw27sBMjfkriC193cITv7CsDMDYgYnVjwEj8LLHI8d6i
6y1vKexvQPupqQyo/NKGiwEsQj9Mj8jidm+bEhAm4ZXcXKwHpesT2igPmu9O/GMtzZZ+PdgYyjyQ
1ADfp15o0qQ7EqJkB+yRaqbmgrK+n/OjpKn3+nGSUFpCtK6ad7GdsewVA2s3pY/ROY8EGcA46azB
F3DUnpBXeRaB2/gyTPsV6gj95v/BwhJPvRUQBsuRbZVteV+xXoun+jbyx9DRO5sa5kLXegTgBAuf
sUUXrdbqzD/tuJBI8DtC9opEQXcBUjXqjpRA6AcSZN8+2R6TkL9n6vI5iVfvUboDL52sZKa+AuM6
K62bE0TTy+Ik5XldyjYBWZmUn+bA0NrKomcYQGbBUfckbLPGqAvCeTxmI5e34vwNBvMLLrXjjidT
YTIcMiC+uP/NYwshflq1tp70nhCtFNLt2fb8I850BW+rVHfrfxTmVdW76Z7hDvmuhQWAbypOpsU1
H17dwNDkGjQeH71lBB9yaWE420NFzXfwQaFIyOZGj2F9QQksoTeEV1aT6/C/c/2wmwsevYk3Rkio
9I0zRZjhsWcGkkNiOLKE7tLYKfqQlddyF6zGyPZ5L4cEwtipMvvoUpgS2NcbIsyv3jX7doE4eQ/e
tmYfqR0gpNH6mDCOiNxOi5881eFNC1UkgcqscNr97iwA7B2KRddKojBWUyFGWDlO4k0grzA+9Aal
WvlAFuGhMM4+SDv9gc0Vqo6kCzEElgcgYd6wV9BdO4JV+qyaQtiVWidKpy2dAty0dYHEDUHcgHE+
/cIkzw6QJThSh/paGWXKq9fxEq+xQbp06GGmtTxrmt0T5YYRfF3juQERPyQzqUY5WhDivmlUmghL
7VI0ShjTNx5x5tcgQo1oSwp6qSfgOWHQPAxTMYjRvH32xM+hzkogfQvMxOsRWQjONyiQJDvEV5CW
IzgzAQwPN9K78gfJr6CtCh4ZQFk3PSO+f+cPVLv6NrAItrG8kIc6cADsgCnzJofwznmIjR/rFulp
kWuJD39rZQF/or1LiyIJtRjkxDYMn0fiF7LZfRR8qBgodDrJLOvTGzlYH+hIVWwOozP5YtDiwHa+
+zKVbjsv9uy1mhMk+WII0WDWPlCeuG1i90qg0CTDlgwyEOQ/Z0FUmiv6fdgSODXjwv3OhyI7i0WO
ZYS6thEI70q5AMjLHspaq+EhUS3oB1j7vZ0m0H8dQskx4kvuRzo1ziMeYOjsCJiZYXHw9kI2Ykyh
ZKru9dN8bx8Vkxt7k7aDKJBuOqLXCJWZlRt52vcY3cj/3S15krnCXkPouoiLN+dBQNouEpO/PACJ
NIx4mzCyKVKxE/9/B2i0nIbbQzveNbRgPr/6JUrPXf5eoGfpVVvARQd0vEDzKxX+n39jzr6OQ5ec
Z3aH7pM+LVbF9qoxZJJwdK3BaHHrm3KKnDkpA2XAzEDz1qhO/L9DmFVjFKOQptpdrJRhB/YEcvAI
4SIcyZzr/oV2uSCPOyVMmPJZ0rNNOOA9W+SVzvIENzdwwPMT4fPIl7H/2Be1fRQc5LWrwwewRG5m
FVFIWo30WSS7p0wG6rlja9Vq1Nq5dPMdlT/QN0rm915wvisiutkLRc2nbAHLEGPIRUMnij6h3JaX
G15W5YVQeK8Lcm6//+3W9qlHrS7Q4/rOsrgw9rXowGGB+xV95Gan2TdE9Pgocktz0kqh8OnD79mP
aQZb8Um8sQWiRPdFYu7yETNQX6bbcIrGnTeJlQGeP+3U9x0Q5JlrPdzIk9hShRLMwCkHgYEf8tG/
8aWnIhKhHg48GGfzd6bUKQEsR/dadIAGnPc96N2gVyhqQ5/mB9xXbS/E/iHZzUrT65hoQ1fy4a1U
0RgBzbTTs9ViVWnTOgGZg/jzL+o/rLmMRrZzEg1w8XqvBzTNTt0ZC14H+Fk3hjyOGChappZYaEP6
c+4+9lQgx/4dgKekYDfkSBYH4InDUNExhdtOsRzto935MXoEgN+LzFjfQLk+8tQrNbW6OjrwZ/7R
7Dk2eYeU11jV1q5qPAD8gDkvzcjQUs3h7h9oLLrXWnQwDN8iElOviATzU1FLQqyXa+PJCTOrYXJG
nX+9mqKhYIOc/kSNUDnSR+0u+bNWUAPqOTdb4DjUh9lutrnqmrJEcG1ezyUlmkM11rSAaM4/3e32
MN5F1JlxSNk2fsRfaN23qHAihdD9OEAO0D/LRjMvJI7U9Wop/0BpPlwxeF9llT5Zb4jdtH1DL7Zt
Yj4+kCAaXrMWObBuPyLyuxFGFulNwWIP+31BRjFE5FzTK+9ijDAU4myXGaTza6tFVHD/6EGPE32M
379H5c8LliRRdfWUCmyWEVvp+OgbV8t3R9UnHDiYf8WBqwmiqZdoiVBpdKX1JpwUYOPzPjdEmZkY
y08QlfPcctPjiQba8vfRO+vN45xeGgY2uOLn5o+IVEqAbD62Ug+KZBzcOSN0gW2Qwt53vMuORw8H
fw3T1859JRvU2Iw1ivWYZFLz/Qbu/QrAFfCSKs7QfVaB8FqQa53NXBjrOHwkZ3E55bYFshCuvBR+
d046DTblGOcB8tqE949J6EIf4Z0K3sDWx+JhE7FBFv0S438OZEJZ+b06PL2/fh7z7JVieB99UxYh
oLdp7VcsqmQ/QdxfJWXxOvr6LZ3MozRvXDYvNiMeRvFof779JbM5ORVTseCPwrjzYNVJoT3d/NIH
JpaqQMTRbzYXBp7M53Ho4q3kMjdoHVaoqZfCAuRhn7cvfZVcQcv+Amqd2uPX87CH/jdZ+CGLhGNc
J6lGweBrbyqC8WhQEhOqy62GJVczg63n+lxMq/Y6WmbsPGS4+atceZpfwa81ZqcwMlFiQBGKSIqi
L31zaTP6Y/c2tkSvsKTD2JQXQ0X5Ih9gIpr+QsX1e0tzbILwFS9x47lRnNAbpt2YezqUaKx2jaLS
Q66DZJr3a/6SIKLowN7/neQRaTj5Pf9uiOwKE5i3yTcwZSHo2QrQA0lq/HN6PboBt0IY5iQUIXf3
5h3HAwJkgbKJ+S6rWnFJHp0WwXpicTMKVKT6m1waxoyr3fBrPm9OD0fX2Fh/DUt3ByA8jW/bHwui
Ed4cU21bCDZqG287eWyKUChYK2kQsOk/zuRUe3gAHt7tbHSAiGrZpwAdUA4Yeo4NueyZUo2TlmVP
jIBPWWlsFKocycZ+VAUvNGJt4+CdRSFJ9MaF2sokSCMTjbWmeXK7XHW2x75TpvF3Aq+hHnHkUZly
rsSDEHclpxynT9ycOTO24WVDNn5X4U/FWS9nz2ZSuR2r7IWylpXzV6uoBVjaCs4Dcz7f6gYIYyCG
f2s2dDyHtcl+5QrdkmPpemaLhKgQ9IkAofSW7jrj0bWuEweHT4iv66amLGz97W5GcZsorqYDy4Sw
9aAR1iRoolBfcA2jE22I/P6emCFHteA0eXPC10w5SysX6ZSAIuOXfJAZR8PMs0qkN5I3HZsjYZ6e
UUaHFN/8NHZxx5vC3DLCfnYFmOzp9E9HviGrpUrKsBomXHnIlp0q801N9w77IZHq1qMjWwC/JJvU
e0NhkQcriSFW07Ab2fWk4DV0v0EF+1kfRQGUuAY93LC8ZtsTC9NUYDgx8uVDj0+gGE5xeFXzKj2A
8+BtDx+6d0I56Npf6+F6hTA5U7+aCqaWXNFlMrHJ3rn0zKu+YsL8vNt4osY8QS1NvIe5snnFUr1Z
Jr4whcM1Zd4jnDFqppek3m6QFEGygIZX+hoeQ9X0N/rbUzfzlf2xNp/H9MIeK+yWhWz9v5lti4UB
rWnB0X8LX7YZlLNyVPS9YDAVs7iuPHO4F9TbUX5djjclepCluoLWO1fuVKGk4frQLe2JZOy9i9/C
BUroWtxv8MA65BStZp3AVIV0W/e29sEV5DFcdpo0oN+QiK6Gj7TX0tbkvpaHed+F8/AurkNJXtj6
R21qukJtZ4nJZVL6/7kbLK7LKrwSCf0KuVHUwCFEBIB51jKm/oOUcvP2gHYyxkhCup0AeDmF1ht/
seDjEO3xFBmMLvpTnNBNsIF+miLAmd2EXByk05bN47hIazzOB0sDds1EHfNGVY8rUA6aywt5agW7
/obBe+thpjAArIc/eu88WDA15Qe38HFIzuubmE/fxIpB4fjvRDJDVRPyLdOYXG8r7IdEaQA8/rhs
bvUI9jwIH2Anft5NBj11A0ScnPwVLepLj0n06mHt+sM62qtjiR46QJc3beJjUnQsjmAYI2O1LWYx
Vv6WXX8LrkECx321pbWJ48StwFQ3TtC8Hu5uoEqilcg3k6Gdd4+rc8V5HjfdA+2teFgxJSw3+z8H
JBZPeIByQHOJ/x5uhrfkeOi/owC18gQThWT+aljLBg/HmkwZa5GnAFEXDGq6VWwlpe6HWCu8/HVb
GXO60w5NdDmBm27QelOk4pBRRgGLZsgUQBJq62RSM8nw8qhJ+cWWRab2+tSp03h5Rp3/hYFVbaBP
awTL7wSHR9gWfTt/PiWI61C7Q87xeSbmLx/FsKR5WNXoa0xpgDYGWof/LcSLqm5J2NuhULc+AXOe
osMlxGQ7KBR8BMu/BME42yhInU0T5WcgyXGNvzX+QdHYOlFdDQbjftVNJnOFbqO3MOHer41C9oh/
mlIlFoWVw+K5m8vIE1zhudqqi5rNjX0DPyYFd0jGfpiuZGOQ/O497HKjk24f6vLuvPTZzyY3Kb5J
vk5l/Pn8B50DNNumwVj4JQQ2vuQXwAHmJGpEGNxhHdZae4DClnFgK3RQ0ScjlBDU5Djhetg6HC4+
TrsGiB06Cd5GqQsYbIJh7CSKVqAtR/A641FNNWWL2/MnJubDv3ufBQPhaA6Dp4WBWU0wThuRecNq
1BOuDKLemZIpy8RvXf5GQQO9wOIE0kkQLjwg0xqtKCuwcjFHCcK5H0KYOUpe+wJQtTqh37nvInKm
jO0EfVCjA51MnI+AecqnTRp83GEaTDejO2OAPXUgIROhDGyHjP+Tbx91sDbDM114oaShRkMc3jSN
sc6OYw99xfV4ojUedeo8FLp7DzaVaMg5mKS9rOkNz1FzS6d2zcjmgzLiDHMjHSr7DPfBqRYGZszn
rd1U439Ivg7+CjCjbIms58VLUK4cC3lxO9VMVe+dngx/zREIGUAqS40/qygTC84pPB/pIvQsQ+jl
3HqY1QFGnE8B9dSWpe6OgBBsgb+jZIaTNJVEPgveKtZxuUPWl4aem/zIySkKAOT9/sqDwbWa8oel
3pssHjFYCJgtuPsdv67v9CbTJNFU4OywC8TnNyx3SEHT1yRNMX5RkyDxoj46hEH4tflDbR1+0Qjx
ofwgIbv/2EbgUHgAoCB0cTNH4P6yxAvU53MzzAaTJBx0PSJFZYSTfdoE26z+lWXy7lQ3gRmDPcna
eJziXoPBnTRpPamWsU9ttGLIQAsJ/3j/+MmnL/tyrRbhzI5VccPKTgPvFMPZj/A2+xcfx2sODZyX
c1uL4n0QOp86pqY0s+loQiLuIeu9YU8yOtACIqcAfMshs6O60v3bKfzKvFHHGWMe4C3RvHZNMKk4
ijq0qMvOXWqO4dwvZLWV2DuQtn7OmQuMSdAeYjubXnO9pOistU4WyO3Lz7zZlW4A4utkUTUMoCwu
wmxhc2DW3/GuU+ctnhzKvy/3skFJhxF9XACcXbXffyT4peA36awvYX1hA0CJlLEQC5ytWF21MWLm
iLR3r2V2w5o8uPxgyyA/NFyabqriqPDptFAvt+bjX3/wKamASk9KaEB0oTZIAWlKivBsOTCQhmqh
vEx46z6b87c1k99OyeZ1UHc//0L1xjPYVggJqVgaSDhaKLyS0tInkLjdqsiubt+o1mqsUXdRhusa
Q7oYFRVEGmt6HugIwYuS3+jX66mEwX5CZom9ZCYVfzon2mXaaNSlK1AqP7mA3kaZhnxQk0F+P+Fk
CRJiYgKT/g1ig3YnBhkKYW454tTKzYrzzmfN3hUTyljRL45YfbMwHxJZ7ZtlfSDSzzashDN3LoT2
8nWDy98GX3LhBsvA2WUo0kD4oplB1zxvwx7J3hF+6GtE6CPsCq19lroE4FqCy2zEk/MVDTDp1Yca
08B8l6JkNpis/cXYINLPeCVNCGOT71veIaNdebTZ9En6syBSh+J2olLPLvSRWEm9+a4L0rI0Kd3s
8WIK6oD7WEOag4hMTI36Yz5COL/I5AKCI3Lx7qTw6UYfjcBTlsx/YoXwGbD6gXm121XuLT5OeIBv
YaBQgc8WeIvmsGC4sHQr6XdkLaSDOn8HgYLmQQ+2NkM2g1DqvDGJTk1TuSAMGtBGYy5K4FUOUBbO
9HCdaOuL6buzlhrkl0gA1GbGRowCIImfbvOPoZ+OEXGFOjZ3flNJ7Fk4TsrMqwAK/VU7nsMbkUpo
8i4w5YjQcC9n+MHF3PodVvha0PAEOdbR1CR2Kq4BwAFPQr0FC38SZ3DrXqFffh4nRv9VvcNTnutq
TM0YKaBN8nbtewJ/x2hdX9se7v8aaJ0S8ZBtGzvetfuJjl5QtaeoVh5811u+aRF9cVMiKpO4oNUL
XGkvlGUy4nCEU4XQvf5VXe1W+vQFNNEWRC5QmzGpA7VHpnDvTkZZCtf/uHx5EBL6OB5xWJLjt1VH
/pefHlGCn5Z5yPqyQ4yOE7DLC5TpiOAAh3UEhIc506jAeP6WJqknXt1B8x9Alc9BR3hVqOKXHN+C
ilhClDWo8i4GS6hJWOH18EL492By6b6diFHWyfgD6X+iykaUaBFlZoyP0A4INCoqQ60JDM0T3LtL
mUoCd3Ar2dAZ1DFB889x4YmPLP1g1YyjrkV7wj5065lKasetZ06ta2O1OFc+YTYbfTCT6GdN8QKp
H51QOLWVX9mImZ0=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
JJbTY/FLcWvFG4qgAoNcpDhRwWPWVIcrdtaenypUXGLd3oTJ/JQb2qOK7MhEJn9BIXYTqB7VuZqx
e6DtbJOKOA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
pkuc65r8e4R3tDFvu6DzbbJcV9tkzKLyPKKlNc65L0768LzwNnpo2u6urWESUnoi9BL1+672QFhe
09HpyRE2HkjzJd1z1kaLv9hyhnpCA9GwqIBhjYdIURpu0ubdQR1UBOHtZ3qQJhtopEW8hfZl7dvJ
Y8ZIhtD89bkLtifYcuo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Vbv7nZIA7BpS+vnUBhHjIBriv57jxA12oW/i+XeuxCefIWgUPjKwfT/jgTuk9x4kTDnFYG9VQgJA
VtZoz66/xCsdqRQDoQ10qRAoO8/bmYjo5EFj8HLZCaMHwnNycGiRqLzuqEpP8hc9/7GtNoYDio5m
nM3lZ9W+cruj/J1hSpa+RJrLzeP1aeCTCLwmO89oKq/O1BYM3VLdeOalavdHsU0pUGcgu8HzWLCR
SdQ9pWkfAsp7Xnb3DEfWbn7cbKq4vrloHtXtRL3H02ehrsta1zMWUmHUfZWHR/zYfH1511de3x2t
jWYmYjqwAzRhX1yazPjaksvtLLF8y0HVNSvv/g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Gx+MOr4EV4k2yU99PxwAq2OTo44OHCHTACh+KbLxozta18EIEYOm2aizcy8q9vNvTL12Dt3xoIow
fSgPeMSp5cpLLLfL4wj50qgEh96d0vuP1gicF7owPtTTDzmmaoQOyIUrRcu5H83SV1PGRzx91OCM
ebTdB4aNsgvW+Ha+ijM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IV8iYcOvJgxHLoDBVMEKBuLzvur6e0kUMX78pvdR3suIc2NXa6qopmoQxw6EhQbDzn3Lgr28RHS6
F/4sOaM/udVMaESTiiOo53fb3tcfucg98na/aTs2wJoWzFwFCoosNKzKFDj9ZOBKeNEgjO7cH+bc
LpDBEu93gBfteu7+ib7BYwxshNw/zEolst1iEv30DWKOWjb1H3GpyWziNH46Nx9GuNunynQSnnn6
uoCJkSbXvPCb7SInOjxdbTOZq9cv/tUV7UxkNwOaGFWd3K0bY02rIBsR/FjAO5OWU43QRyYq1MTe
A68N51229WUZVQiKp+fbj67HDpUnk4geJwAKzA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6224)
`protect data_block
oiwKMgI4JUZws9tNOvrRyukMIt7a4KLtDF3AjGAKRBdCG8QZ7+wbINzG3t2VzRz3qBSBX3Zi8H7e
HNodVfqPx/Dbt9+ri3bBCCG0uw2CSRChQRrl92MULyOnl4l7oArJsW+loEfgIK6Uvxyx/4kJiniP
nwFMgJPaWEZhVWDIstPOEdSACIOpWAHqh/B+/G6epDjVAWUpDvfuJXF0a4lqSDSAd8Tz3c3RpfJf
LQQtZo5tnAEcPzzg3rV5qtYcIgCj1xe2Cs3ipNRubJUv84B+nIXVon6vyKRqnA5KWvjBqaYZi3cB
lso5Z/cljAuiel8a8CEUaS1a5hEFQdKvb9PwJILDuDsEvolDr+SGe2hsy5xkD5XKZQao0KtMhc0e
C/tCWpjUmxV2oso7Tp+MWOFFsW9Bpgguj+NJTZ5H9gax5LAKJpBNWu3L06XSXqv8TGSzyYOiYq6y
LBoeIM+lKTvuz1iZscUIqIeMuZoAKe5lja3iKv97eDq0cs27CJWbKGjMXmkmLW6hvVw37aU+J47z
WiuXkiTqsSBHiS7AeeaBntsxjbA3DmwOSnoYAcJQ/6rOdtBoTNXyIHmTVS5ktg2q47bVS9qz1+ei
JZ+EiGs5ruq6rjyoMBMd8RAcVUmrZP3qZqP19jeKMNO8FtfEC3NInIwDkCxxF0cwx+dlQqrDC4KE
15b3kt2pO25rAIvbnC7wC+1gN8fjbmS9ClpmkymB9AV9qcrsiOEZtzs9RrJ4AmTv1Nri0VNjt8bu
T9iL2nkuXoeTiLcIM779Woq3lvhnR5wlT7JmlbuodWxw+LGHemM0SsNg5QZBBUKCeq+1AWLJS5Kn
27QQ0JiiwiorRcHTebIciFqgF4o2WRC8IqWn3LVE1CDQ0ZsBbmBgLY+moKzmZYZrIo2Q/+uwwlVD
8NsaCRoANFjYL00nE/YsGD5Cv2HYOG/xpevPoQVVDmvUwqZ/LnW3oPqcvbUhouwST8jnRLlhcJQS
AP0L1ZTu9XH7T4OoVfVUSP3rZi3rU/aq0ibky7y9gtDVzonFUXW0ZCMWo6xgxGa26db0YT3iYsri
vQ3MiLc7or2W6Jduf3dJZMx4OEvHf2kqKkN7c5wDQ7OsMllI3pJ6QTrx+w/n4V4uIUQk3KnjtnZi
1wwzyv+RA0ffuBJ+kpE40wSsZ6khPaRuxRSn2fwLQtYCEb91/JJF7lvGPT1k9v2z+du02ZljgYXq
Uhcw9UiD5QJiCGqGprZfh4Y/XX4c2sbuX+NqQL575uztdB++zXgXYB+ep72GXSALzQcki2Wa8dzf
7IJRcVFJlFd/ulariBr52YLFNO+gvTemuHE9gfNBWm2VH4x0wFbzClKRVWgBUcP40ZFDIDH2Sm2T
Wf6cYrGRr3iDWyd8clz4TtcCzMFgD6UsbN6gT6eZP3FrbKgSfq/Xzoyoa7BQEcA8yHvlifJN0In7
pzu2SQL0IKkDrec13uaOv9D8d4L35z3bXw27sBMjfkriC193cITv7CsDMDYgYnVjwEj8LLHI8d6i
6y1vKexvQPupqQyo/NKGiwEsQj9Mj8jidm+bEhAm4ZXcXKwHpesT2igPmu9O/GMtzZZ+PdgYyjyQ
1ADfp15o0qQ7EqJkB+yRaqbmgrK+n/OjpKn3+nGSUFpCtK6ad7GdsewVA2s3pY/ROY8EGcA46azB
F3DUnpBXeRaB2/gyTPsV6gj95v/BwhJPvRUQBsuRbZVteV+xXoun+jbyx9DRO5sa5kLXegTgBAuf
sUUXrdbqzD/tuJBI8DtC9opEQXcBUjXqjpRA6AcSZN8+2R6TkL9n6vI5iVfvUboDL52sZKa+AuM6
K62bE0TTy+Ik5XldyjYBWZmUn+bA0NrKomcYQGbBUfckbLPGqAvCeTxmI5e34vwNBvMLLrXjjidT
YTIcMiC+uP/NYwshflq1tp70nhCtFNLt2fb8I850BW+rVHfrfxTmVdW76Z7hDvmuhQWAbypOpsU1
H17dwNDkGjQeH71lBB9yaWE420NFzXfwQaFIyOZGj2F9QQksoTeEV1aT6/C/c/2wmwsevYk3Rkio
9I0zRZjhsWcGkkNiOLKE7tLYKfqQlddyF6zGyPZ5L4cEwtipMvvoUpgS2NcbIsyv3jX7doE4eQ/e
tmYfqR0gpNH6mDCOiNxOi5881eFNC1UkgcqscNr97iwA7B2KRddKojBWUyFGWDlO4k0grzA+9Aal
WvlAFuGhMM4+SDv9gc0Vqo6kCzEElgcgYd6wV9BdO4JV+qyaQtiVWidKpy2dAty0dYHEDUHcgHE+
/cIkzw6QJThSh/paGWXKq9fxEq+xQbp06GGmtTxrmt0T5YYRfF3juQERPyQzqUY5WhDivmlUmghL
7VI0ShjTNx5x5tcgQo1oSwp6qSfgOWHQPAxTMYjRvH32xM+hzkogfQvMxOsRWQjONyiQJDvEV5CW
IzgzAQwPN9K78gfJr6CtCh4ZQFk3PSO+f+cPVLv6NrAItrG8kIc6cADsgCnzJofwznmIjR/rFulp
kWuJD39rZQF/or1LiyIJtRjkxDYMn0fiF7LZfRR8qBgodDrJLOvTGzlYH+hIVWwOozP5YtDiwHa+
+zKVbjsv9uy1mhMk+WII0WDWPlCeuG1i90qg0CTDlgwyEOQ/Z0FUmiv6fdgSODXjwv3OhyI7i0WO
ZYS6thEI70q5AMjLHspaq+EhUS3oB1j7vZ0m0H8dQskx4kvuRzo1ziMeYOjsCJiZYXHw9kI2Ykyh
ZKru9dN8bx8Vkxt7k7aDKJBuOqLXCJWZlRt52vcY3cj/3S15krnCXkPouoiLN+dBQNouEpO/PACJ
NIx4mzCyKVKxE/9/B2i0nIbbQzveNbRgPr/6JUrPXf5eoGfpVVvARQd0vEDzKxX+n39jzr6OQ5ec
Z3aH7pM+LVbF9qoxZJJwdK3BaHHrm3KKnDkpA2XAzEDz1qhO/L9DmFVjFKOQptpdrJRhB/YEcvAI
4SIcyZzr/oV2uSCPOyVMmPJZ0rNNOOA9W+SVzvIENzdwwPMT4fPIl7H/2Be1fRQc5LWrwwewRG5m
FVFIWo30WSS7p0wG6rlja9Vq1Nq5dPMdlT/QN0rm915wvisiutkLRc2nbAHLEGPIRUMnij6h3JaX
G15W5YVQeK8Lcm6//+3W9qlHrS7Q4/rOsrgw9rXowGGB+xV95Gan2TdE9Pgocktz0kqh8OnD79mP
aQZb8Um8sQWiRPdFYu7yETNQX6bbcIrGnTeJlQGeP+3U9x0Q5JlrPdzIk9hShRLMwCkHgYEf8tG/
8aWnIhKhHg48GGfzd6bUKQEsR/dadIAGnPc96N2gVyhqQ5/mB9xXbS/E/iHZzUrT65hoQ1fy4a1U
0RgBzbTTs9ViVWnTOgGZg/jzL+o/rLmMRrZzEg1w8XqvBzTNTt0ZC14H+Fk3hjyOGChappZYaEP6
c+4+9lQgx/4dgKekYDfkSBYH4InDUNExhdtOsRzto935MXoEgN+LzFjfQLk+8tQrNbW6OjrwZ/7R
7Dk2eYeU11jV1q5qPAD8gDkvzcjQUs3h7h9oLLrXWnQwDN8iElOviATzU1FLQqyXa+PJCTOrYXJG
nX+9mqKhYIOc/kSNUDnSR+0u+bNWUAPqOTdb4DjUh9lutrnqmrJEcG1ezyUlmkM11rSAaM4/3e32
MN5F1JlxSNk2fsRfaN23qHAihdD9OEAO0D/LRjMvJI7U9Wop/0BpPlwxeF9llT5Zb4jdtH1DL7Zt
Yj4+kCAaXrMWObBuPyLyuxFGFulNwWIP+31BRjFE5FzTK+9ijDAU4myXGaTza6tFVHD/6EGPE32M
379H5c8LliRRdfWUCmyWEVvp+OgbV8t3R9UnHDiYf8WBqwmiqZdoiVBpdKX1JpwUYOPzPjdEmZkY
y08QlfPcctPjiQba8vfRO+vN45xeGgY2uOLn5o+IVEqAbD62Ug+KZBzcOSN0gW2Qwt53vMuORw8H
fw3T1859JRvU2Iw1ivWYZFLz/Qbu/QrAFfCSKs7QfVaB8FqQa53NXBjrOHwkZ3E55bYFshCuvBR+
d046DTblGOcB8tqE949J6EIf4Z0K3sDWx+JhE7FBFv0S438OZEJZ+b06PL2/fh7z7JVieB99UxYh
oLdp7VcsqmQ/QdxfJWXxOvr6LZ3MozRvXDYvNiMeRvFof779JbM5ORVTseCPwrjzYNVJoT3d/NIH
JpaqQMTRbzYXBp7M53Ho4q3kMjdoHVaoqZfCAuRhn7cvfZVcQcv+Amqd2uPX87CH/jdZ+CGLhGNc
J6lGweBrbyqC8WhQEhOqy62GJVczg63n+lxMq/Y6WmbsPGS4+atceZpfwa81ZqcwMlFiQBGKSIqi
L31zaTP6Y/c2tkSvsKTD2JQXQ0X5Ih9gIpr+QsX1e0tzbILwFS9x47lRnNAbpt2YezqUaKx2jaLS
Q66DZJr3a/6SIKLowN7/neQRaTj5Pf9uiOwKE5i3yTcwZSHo2QrQA0lq/HN6PboBt0IY5iQUIXf3
5h3HAwJkgbKJ+S6rWnFJHp0WwXpicTMKVKT6m1waxoyr3fBrPm9OD0fX2Fh/DUt3ByA8jW/bHwui
Ed4cU21bCDZqG287eWyKUChYK2kQsOk/zuRUe3gAHt7tbHSAiGrZpwAdUA4Yeo4NueyZUo2TlmVP
jIBPWWlsFKocycZ+VAUvNGJt4+CdRSFJ9MaF2sokSCMTjbWmeXK7XHW2x75TpvF3Aq+hHnHkUZly
rsSDEHclpxynT9ycOTO24WVDNn5X4U/FWS9nz2ZSuR2r7IWylpXzV6uoBVjaCs4Dcz7f6gYIYyCG
f2s2dDyHtcl+5QrdkmPpemaLhKgQ9IkAofSW7jrj0bWuEweHT4iv66amLGz97W5GcZsorqYDy4Sw
9aAR1iRoolBfcA2jE22I/P6emCFHteA0eXPC10w5SysX6ZSAIuOXfJAZR8PMs0qkN5I3HZsjYZ6e
UUaHFN/8NHZxx5vC3DLCfnYFmOzp9E9HviGrpUrKsBomXHnIlp0q801N9w77IZHq1qMjWwC/JJvU
e0NhkQcriSFW07Ab2fWk4DV0v0EF+1kfRQGUuAY93LC8ZtsTC9NUYDgx8uVDj0+gGE5xeFXzKj2A
8+BtDx+6d0I56Npf6+F6hTA5U7+aCqaWXNFlMrHJ3rn0zKu+YsL8vNt4osY8QS1NvIe5snnFUr1Z
Jr4whcM1Zd4jnDFqppek3m6QFEGygIZX+hoeQ9X0N/rbUzfzlf2xNp/H9MIeK+yWhWz9v5lti4UB
rWnB0X8LX7YZlLNyVPS9YDAVs7iuPHO4F9TbUX5djjclepCluoLWO1fuVKGk4frQLe2JZOy9i9/C
BUroWtxv8MA65BStZp3AVIV0W/e29sEV5DFcdpo0oN+QiK6Gj7TX0tbkvpaHed+F8/AurkNJXtj6
R21qukJtZ4nJZVL6/7kbLK7LKrwSCf0KuVHUwCFEBIB51jKm/oOUcvP2gHYyxkhCup0AeDmF1ht/
seDjEO3xFBmMLvpTnNBNsIF+miLAmd2EXByk05bN47hIazzOB0sDds1EHfNGVY8rUA6aywt5agW7
/obBe+thpjAArIc/eu88WDA15Qe38HFIzuubmE/fxIpB4fjvRDJDVRPyLdOYXG8r7IdEaQA8/rhs
bvUI9jwIH2Anft5NBj11A0ScnPwVLepLj0n06mHt+sM62qtjiR46QJc3beJjUnQsjmAYI2O1LWYx
Vv6WXX8LrkECx321pbWJ48StwFQ3TtC8Hu5uoEqilcg3k6Gdd4+rc8V5HjfdA+2teFgxJSw3+z8H
JBZPeIByQHOJ/x5uhrfkeOi/owC18gQThWT+aljLBg/HmkwZa5GnAFEXDGq6VWwlpe6HWCu8/HVb
GXO60w5NdDmBm27QelOk4pBRRgGLZsgUQBJq62RSM8nw8qhJ+cWWRab2+tSp03h5Rp3/hYFVbaBP
awTL7wSHR9gWfTt/PiWI61C7Q87xeSbmLx/FsKR5WNXoa0xpgDYGWof/LcSLqm5J2NuhULc+AXOe
osMlxGQ7KBR8BMu/BME42yhInU0T5WcgyXGNvzX+QdHYOlFdDQbjftVNJnOFbqO3MOHer41C9oh/
mlIlFoWVw+K5m8vIE1zhudqqi5rNjX0DPyYFd0jGfpiuZGOQ/O497HKjk24f6vLuvPTZzyY3Kb5J
vk5l/Pn8B50DNNumwVj4JQQ2vuQXwAHmJGpEGNxhHdZae4DClnFgK3RQ0ScjlBDU5Djhetg6HC4+
TrsGiB06Cd5GqQsYbIJh7CSKVqAtR/A641FNNWWL2/MnJubDv3ufBQPhaA6Dp4WBWU0wThuRecNq
1BOuDKLemZIpy8RvXf5GQQO9wOIE0kkQLjwg0xqtKCuwcjFHCcK5H0KYOUpe+wJQtTqh37nvInKm
jO0EfVCjA51MnI+AecqnTRp83GEaTDejO2OAPXUgIROhDGyHjP+Tbx91sDbDM114oaShRkMc3jSN
sc6OYw99xfV4ojUedeo8FLp7DzaVaMg5mKS9rOkNz1FzS6d2zcjmgzLiDHMjHSr7DPfBqRYGZszn
rd1U439Ivg7+CjCjbIms58VLUK4cC3lxO9VMVe+dngx/zREIGUAqS40/qygTC84pPB/pIvQsQ+jl
3HqY1QFGnE8B9dSWpe6OgBBsgb+jZIaTNJVEPgveKtZxuUPWl4aem/zIySkKAOT9/sqDwbWa8oel
3pssHjFYCJgtuPsdv67v9CbTJNFU4OywC8TnNyx3SEHT1yRNMX5RkyDxoj46hEH4tflDbR1+0Qjx
ofwgIbv/2EbgUHgAoCB0cTNH4P6yxAvU53MzzAaTJBx0PSJFZYSTfdoE26z+lWXy7lQ3gRmDPcna
eJziXoPBnTRpPamWsU9ttGLIQAsJ/3j/+MmnL/tyrRbhzI5VccPKTgPvFMPZj/A2+xcfx2sODZyX
c1uL4n0QOp86pqY0s+loQiLuIeu9YU8yOtACIqcAfMshs6O60v3bKfzKvFHHGWMe4C3RvHZNMKk4
ijq0qMvOXWqO4dwvZLWV2DuQtn7OmQuMSdAeYjubXnO9pOistU4WyO3Lz7zZlW4A4utkUTUMoCwu
wmxhc2DW3/GuU+ctnhzKvy/3skFJhxF9XACcXbXffyT4peA36awvYX1hA0CJlLEQC5ytWF21MWLm
iLR3r2V2w5o8uPxgyyA/NFyabqriqPDptFAvt+bjX3/wKamASk9KaEB0oTZIAWlKivBsOTCQhmqh
vEx46z6b87c1k99OyeZ1UHc//0L1xjPYVggJqVgaSDhaKLyS0tInkLjdqsiubt+o1mqsUXdRhusa
Q7oYFRVEGmt6HugIwYuS3+jX66mEwX5CZom9ZCYVfzon2mXaaNSlK1AqP7mA3kaZhnxQk0F+P+Fk
CRJiYgKT/g1ig3YnBhkKYW454tTKzYrzzmfN3hUTyljRL45YfbMwHxJZ7ZtlfSDSzzashDN3LoT2
8nWDy98GX3LhBsvA2WUo0kD4oplB1zxvwx7J3hF+6GtE6CPsCq19lroE4FqCy2zEk/MVDTDp1Yca
08B8l6JkNpis/cXYINLPeCVNCGOT71veIaNdebTZ9En6syBSh+J2olLPLvSRWEm9+a4L0rI0Kd3s
8WIK6oD7WEOag4hMTI36Yz5COL/I5AKCI3Lx7qTw6UYfjcBTlsx/YoXwGbD6gXm121XuLT5OeIBv
YaBQgc8WeIvmsGC4sHQr6XdkLaSDOn8HgYLmQQ+2NkM2g1DqvDGJTk1TuSAMGtBGYy5K4FUOUBbO
9HCdaOuL6buzlhrkl0gA1GbGRowCIImfbvOPoZ+OEXGFOjZ3flNJ7Fk4TsrMqwAK/VU7nsMbkUpo
8i4w5YjQcC9n+MHF3PodVvha0PAEOdbR1CR2Kq4BwAFPQr0FC38SZ3DrXqFffh4nRv9VvcNTnutq
TM0YKaBN8nbtewJ/x2hdX9se7v8aaJ0S8ZBtGzvetfuJjl5QtaeoVh5811u+aRF9cVMiKpO4oNUL
XGkvlGUy4nCEU4XQvf5VXe1W+vQFNNEWRC5QmzGpA7VHpnDvTkZZCtf/uHx5EBL6OB5xWJLjt1VH
/pefHlGCn5Z5yPqyQ4yOE7DLC5TpiOAAh3UEhIc506jAeP6WJqknXt1B8x9Alc9BR3hVqOKXHN+C
ilhClDWo8i4GS6hJWOH18EL492By6b6diFHWyfgD6X+iykaUaBFlZoyP0A4INCoqQ60JDM0T3LtL
mUoCd3Ar2dAZ1DFB889x4YmPLP1g1YyjrkV7wj5065lKasetZ06ta2O1OFc+YTYbfTCT6GdN8QKp
H51QOLWVX9mImZ0=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
JJbTY/FLcWvFG4qgAoNcpDhRwWPWVIcrdtaenypUXGLd3oTJ/JQb2qOK7MhEJn9BIXYTqB7VuZqx
e6DtbJOKOA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
pkuc65r8e4R3tDFvu6DzbbJcV9tkzKLyPKKlNc65L0768LzwNnpo2u6urWESUnoi9BL1+672QFhe
09HpyRE2HkjzJd1z1kaLv9hyhnpCA9GwqIBhjYdIURpu0ubdQR1UBOHtZ3qQJhtopEW8hfZl7dvJ
Y8ZIhtD89bkLtifYcuo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Vbv7nZIA7BpS+vnUBhHjIBriv57jxA12oW/i+XeuxCefIWgUPjKwfT/jgTuk9x4kTDnFYG9VQgJA
VtZoz66/xCsdqRQDoQ10qRAoO8/bmYjo5EFj8HLZCaMHwnNycGiRqLzuqEpP8hc9/7GtNoYDio5m
nM3lZ9W+cruj/J1hSpa+RJrLzeP1aeCTCLwmO89oKq/O1BYM3VLdeOalavdHsU0pUGcgu8HzWLCR
SdQ9pWkfAsp7Xnb3DEfWbn7cbKq4vrloHtXtRL3H02ehrsta1zMWUmHUfZWHR/zYfH1511de3x2t
jWYmYjqwAzRhX1yazPjaksvtLLF8y0HVNSvv/g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Gx+MOr4EV4k2yU99PxwAq2OTo44OHCHTACh+KbLxozta18EIEYOm2aizcy8q9vNvTL12Dt3xoIow
fSgPeMSp5cpLLLfL4wj50qgEh96d0vuP1gicF7owPtTTDzmmaoQOyIUrRcu5H83SV1PGRzx91OCM
ebTdB4aNsgvW+Ha+ijM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IV8iYcOvJgxHLoDBVMEKBuLzvur6e0kUMX78pvdR3suIc2NXa6qopmoQxw6EhQbDzn3Lgr28RHS6
F/4sOaM/udVMaESTiiOo53fb3tcfucg98na/aTs2wJoWzFwFCoosNKzKFDj9ZOBKeNEgjO7cH+bc
LpDBEu93gBfteu7+ib7BYwxshNw/zEolst1iEv30DWKOWjb1H3GpyWziNH46Nx9GuNunynQSnnn6
uoCJkSbXvPCb7SInOjxdbTOZq9cv/tUV7UxkNwOaGFWd3K0bY02rIBsR/FjAO5OWU43QRyYq1MTe
A68N51229WUZVQiKp+fbj67HDpUnk4geJwAKzA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6224)
`protect data_block
oiwKMgI4JUZws9tNOvrRyukMIt7a4KLtDF3AjGAKRBdCG8QZ7+wbINzG3t2VzRz3qBSBX3Zi8H7e
HNodVfqPx/Dbt9+ri3bBCCG0uw2CSRChQRrl92MULyOnl4l7oArJsW+loEfgIK6Uvxyx/4kJiniP
nwFMgJPaWEZhVWDIstPOEdSACIOpWAHqh/B+/G6epDjVAWUpDvfuJXF0a4lqSDSAd8Tz3c3RpfJf
LQQtZo5tnAEcPzzg3rV5qtYcIgCj1xe2Cs3ipNRubJUv84B+nIXVon6vyKRqnA5KWvjBqaYZi3cB
lso5Z/cljAuiel8a8CEUaS1a5hEFQdKvb9PwJILDuDsEvolDr+SGe2hsy5xkD5XKZQao0KtMhc0e
C/tCWpjUmxV2oso7Tp+MWOFFsW9Bpgguj+NJTZ5H9gax5LAKJpBNWu3L06XSXqv8TGSzyYOiYq6y
LBoeIM+lKTvuz1iZscUIqIeMuZoAKe5lja3iKv97eDq0cs27CJWbKGjMXmkmLW6hvVw37aU+J47z
WiuXkiTqsSBHiS7AeeaBntsxjbA3DmwOSnoYAcJQ/6rOdtBoTNXyIHmTVS5ktg2q47bVS9qz1+ei
JZ+EiGs5ruq6rjyoMBMd8RAcVUmrZP3qZqP19jeKMNO8FtfEC3NInIwDkCxxF0cwx+dlQqrDC4KE
15b3kt2pO25rAIvbnC7wC+1gN8fjbmS9ClpmkymB9AV9qcrsiOEZtzs9RrJ4AmTv1Nri0VNjt8bu
T9iL2nkuXoeTiLcIM779Woq3lvhnR5wlT7JmlbuodWxw+LGHemM0SsNg5QZBBUKCeq+1AWLJS5Kn
27QQ0JiiwiorRcHTebIciFqgF4o2WRC8IqWn3LVE1CDQ0ZsBbmBgLY+moKzmZYZrIo2Q/+uwwlVD
8NsaCRoANFjYL00nE/YsGD5Cv2HYOG/xpevPoQVVDmvUwqZ/LnW3oPqcvbUhouwST8jnRLlhcJQS
AP0L1ZTu9XH7T4OoVfVUSP3rZi3rU/aq0ibky7y9gtDVzonFUXW0ZCMWo6xgxGa26db0YT3iYsri
vQ3MiLc7or2W6Jduf3dJZMx4OEvHf2kqKkN7c5wDQ7OsMllI3pJ6QTrx+w/n4V4uIUQk3KnjtnZi
1wwzyv+RA0ffuBJ+kpE40wSsZ6khPaRuxRSn2fwLQtYCEb91/JJF7lvGPT1k9v2z+du02ZljgYXq
Uhcw9UiD5QJiCGqGprZfh4Y/XX4c2sbuX+NqQL575uztdB++zXgXYB+ep72GXSALzQcki2Wa8dzf
7IJRcVFJlFd/ulariBr52YLFNO+gvTemuHE9gfNBWm2VH4x0wFbzClKRVWgBUcP40ZFDIDH2Sm2T
Wf6cYrGRr3iDWyd8clz4TtcCzMFgD6UsbN6gT6eZP3FrbKgSfq/Xzoyoa7BQEcA8yHvlifJN0In7
pzu2SQL0IKkDrec13uaOv9D8d4L35z3bXw27sBMjfkriC193cITv7CsDMDYgYnVjwEj8LLHI8d6i
6y1vKexvQPupqQyo/NKGiwEsQj9Mj8jidm+bEhAm4ZXcXKwHpesT2igPmu9O/GMtzZZ+PdgYyjyQ
1ADfp15o0qQ7EqJkB+yRaqbmgrK+n/OjpKn3+nGSUFpCtK6ad7GdsewVA2s3pY/ROY8EGcA46azB
F3DUnpBXeRaB2/gyTPsV6gj95v/BwhJPvRUQBsuRbZVteV+xXoun+jbyx9DRO5sa5kLXegTgBAuf
sUUXrdbqzD/tuJBI8DtC9opEQXcBUjXqjpRA6AcSZN8+2R6TkL9n6vI5iVfvUboDL52sZKa+AuM6
K62bE0TTy+Ik5XldyjYBWZmUn+bA0NrKomcYQGbBUfckbLPGqAvCeTxmI5e34vwNBvMLLrXjjidT
YTIcMiC+uP/NYwshflq1tp70nhCtFNLt2fb8I850BW+rVHfrfxTmVdW76Z7hDvmuhQWAbypOpsU1
H17dwNDkGjQeH71lBB9yaWE420NFzXfwQaFIyOZGj2F9QQksoTeEV1aT6/C/c/2wmwsevYk3Rkio
9I0zRZjhsWcGkkNiOLKE7tLYKfqQlddyF6zGyPZ5L4cEwtipMvvoUpgS2NcbIsyv3jX7doE4eQ/e
tmYfqR0gpNH6mDCOiNxOi5881eFNC1UkgcqscNr97iwA7B2KRddKojBWUyFGWDlO4k0grzA+9Aal
WvlAFuGhMM4+SDv9gc0Vqo6kCzEElgcgYd6wV9BdO4JV+qyaQtiVWidKpy2dAty0dYHEDUHcgHE+
/cIkzw6QJThSh/paGWXKq9fxEq+xQbp06GGmtTxrmt0T5YYRfF3juQERPyQzqUY5WhDivmlUmghL
7VI0ShjTNx5x5tcgQo1oSwp6qSfgOWHQPAxTMYjRvH32xM+hzkogfQvMxOsRWQjONyiQJDvEV5CW
IzgzAQwPN9K78gfJr6CtCh4ZQFk3PSO+f+cPVLv6NrAItrG8kIc6cADsgCnzJofwznmIjR/rFulp
kWuJD39rZQF/or1LiyIJtRjkxDYMn0fiF7LZfRR8qBgodDrJLOvTGzlYH+hIVWwOozP5YtDiwHa+
+zKVbjsv9uy1mhMk+WII0WDWPlCeuG1i90qg0CTDlgwyEOQ/Z0FUmiv6fdgSODXjwv3OhyI7i0WO
ZYS6thEI70q5AMjLHspaq+EhUS3oB1j7vZ0m0H8dQskx4kvuRzo1ziMeYOjsCJiZYXHw9kI2Ykyh
ZKru9dN8bx8Vkxt7k7aDKJBuOqLXCJWZlRt52vcY3cj/3S15krnCXkPouoiLN+dBQNouEpO/PACJ
NIx4mzCyKVKxE/9/B2i0nIbbQzveNbRgPr/6JUrPXf5eoGfpVVvARQd0vEDzKxX+n39jzr6OQ5ec
Z3aH7pM+LVbF9qoxZJJwdK3BaHHrm3KKnDkpA2XAzEDz1qhO/L9DmFVjFKOQptpdrJRhB/YEcvAI
4SIcyZzr/oV2uSCPOyVMmPJZ0rNNOOA9W+SVzvIENzdwwPMT4fPIl7H/2Be1fRQc5LWrwwewRG5m
FVFIWo30WSS7p0wG6rlja9Vq1Nq5dPMdlT/QN0rm915wvisiutkLRc2nbAHLEGPIRUMnij6h3JaX
G15W5YVQeK8Lcm6//+3W9qlHrS7Q4/rOsrgw9rXowGGB+xV95Gan2TdE9Pgocktz0kqh8OnD79mP
aQZb8Um8sQWiRPdFYu7yETNQX6bbcIrGnTeJlQGeP+3U9x0Q5JlrPdzIk9hShRLMwCkHgYEf8tG/
8aWnIhKhHg48GGfzd6bUKQEsR/dadIAGnPc96N2gVyhqQ5/mB9xXbS/E/iHZzUrT65hoQ1fy4a1U
0RgBzbTTs9ViVWnTOgGZg/jzL+o/rLmMRrZzEg1w8XqvBzTNTt0ZC14H+Fk3hjyOGChappZYaEP6
c+4+9lQgx/4dgKekYDfkSBYH4InDUNExhdtOsRzto935MXoEgN+LzFjfQLk+8tQrNbW6OjrwZ/7R
7Dk2eYeU11jV1q5qPAD8gDkvzcjQUs3h7h9oLLrXWnQwDN8iElOviATzU1FLQqyXa+PJCTOrYXJG
nX+9mqKhYIOc/kSNUDnSR+0u+bNWUAPqOTdb4DjUh9lutrnqmrJEcG1ezyUlmkM11rSAaM4/3e32
MN5F1JlxSNk2fsRfaN23qHAihdD9OEAO0D/LRjMvJI7U9Wop/0BpPlwxeF9llT5Zb4jdtH1DL7Zt
Yj4+kCAaXrMWObBuPyLyuxFGFulNwWIP+31BRjFE5FzTK+9ijDAU4myXGaTza6tFVHD/6EGPE32M
379H5c8LliRRdfWUCmyWEVvp+OgbV8t3R9UnHDiYf8WBqwmiqZdoiVBpdKX1JpwUYOPzPjdEmZkY
y08QlfPcctPjiQba8vfRO+vN45xeGgY2uOLn5o+IVEqAbD62Ug+KZBzcOSN0gW2Qwt53vMuORw8H
fw3T1859JRvU2Iw1ivWYZFLz/Qbu/QrAFfCSKs7QfVaB8FqQa53NXBjrOHwkZ3E55bYFshCuvBR+
d046DTblGOcB8tqE949J6EIf4Z0K3sDWx+JhE7FBFv0S438OZEJZ+b06PL2/fh7z7JVieB99UxYh
oLdp7VcsqmQ/QdxfJWXxOvr6LZ3MozRvXDYvNiMeRvFof779JbM5ORVTseCPwrjzYNVJoT3d/NIH
JpaqQMTRbzYXBp7M53Ho4q3kMjdoHVaoqZfCAuRhn7cvfZVcQcv+Amqd2uPX87CH/jdZ+CGLhGNc
J6lGweBrbyqC8WhQEhOqy62GJVczg63n+lxMq/Y6WmbsPGS4+atceZpfwa81ZqcwMlFiQBGKSIqi
L31zaTP6Y/c2tkSvsKTD2JQXQ0X5Ih9gIpr+QsX1e0tzbILwFS9x47lRnNAbpt2YezqUaKx2jaLS
Q66DZJr3a/6SIKLowN7/neQRaTj5Pf9uiOwKE5i3yTcwZSHo2QrQA0lq/HN6PboBt0IY5iQUIXf3
5h3HAwJkgbKJ+S6rWnFJHp0WwXpicTMKVKT6m1waxoyr3fBrPm9OD0fX2Fh/DUt3ByA8jW/bHwui
Ed4cU21bCDZqG287eWyKUChYK2kQsOk/zuRUe3gAHt7tbHSAiGrZpwAdUA4Yeo4NueyZUo2TlmVP
jIBPWWlsFKocycZ+VAUvNGJt4+CdRSFJ9MaF2sokSCMTjbWmeXK7XHW2x75TpvF3Aq+hHnHkUZly
rsSDEHclpxynT9ycOTO24WVDNn5X4U/FWS9nz2ZSuR2r7IWylpXzV6uoBVjaCs4Dcz7f6gYIYyCG
f2s2dDyHtcl+5QrdkmPpemaLhKgQ9IkAofSW7jrj0bWuEweHT4iv66amLGz97W5GcZsorqYDy4Sw
9aAR1iRoolBfcA2jE22I/P6emCFHteA0eXPC10w5SysX6ZSAIuOXfJAZR8PMs0qkN5I3HZsjYZ6e
UUaHFN/8NHZxx5vC3DLCfnYFmOzp9E9HviGrpUrKsBomXHnIlp0q801N9w77IZHq1qMjWwC/JJvU
e0NhkQcriSFW07Ab2fWk4DV0v0EF+1kfRQGUuAY93LC8ZtsTC9NUYDgx8uVDj0+gGE5xeFXzKj2A
8+BtDx+6d0I56Npf6+F6hTA5U7+aCqaWXNFlMrHJ3rn0zKu+YsL8vNt4osY8QS1NvIe5snnFUr1Z
Jr4whcM1Zd4jnDFqppek3m6QFEGygIZX+hoeQ9X0N/rbUzfzlf2xNp/H9MIeK+yWhWz9v5lti4UB
rWnB0X8LX7YZlLNyVPS9YDAVs7iuPHO4F9TbUX5djjclepCluoLWO1fuVKGk4frQLe2JZOy9i9/C
BUroWtxv8MA65BStZp3AVIV0W/e29sEV5DFcdpo0oN+QiK6Gj7TX0tbkvpaHed+F8/AurkNJXtj6
R21qukJtZ4nJZVL6/7kbLK7LKrwSCf0KuVHUwCFEBIB51jKm/oOUcvP2gHYyxkhCup0AeDmF1ht/
seDjEO3xFBmMLvpTnNBNsIF+miLAmd2EXByk05bN47hIazzOB0sDds1EHfNGVY8rUA6aywt5agW7
/obBe+thpjAArIc/eu88WDA15Qe38HFIzuubmE/fxIpB4fjvRDJDVRPyLdOYXG8r7IdEaQA8/rhs
bvUI9jwIH2Anft5NBj11A0ScnPwVLepLj0n06mHt+sM62qtjiR46QJc3beJjUnQsjmAYI2O1LWYx
Vv6WXX8LrkECx321pbWJ48StwFQ3TtC8Hu5uoEqilcg3k6Gdd4+rc8V5HjfdA+2teFgxJSw3+z8H
JBZPeIByQHOJ/x5uhrfkeOi/owC18gQThWT+aljLBg/HmkwZa5GnAFEXDGq6VWwlpe6HWCu8/HVb
GXO60w5NdDmBm27QelOk4pBRRgGLZsgUQBJq62RSM8nw8qhJ+cWWRab2+tSp03h5Rp3/hYFVbaBP
awTL7wSHR9gWfTt/PiWI61C7Q87xeSbmLx/FsKR5WNXoa0xpgDYGWof/LcSLqm5J2NuhULc+AXOe
osMlxGQ7KBR8BMu/BME42yhInU0T5WcgyXGNvzX+QdHYOlFdDQbjftVNJnOFbqO3MOHer41C9oh/
mlIlFoWVw+K5m8vIE1zhudqqi5rNjX0DPyYFd0jGfpiuZGOQ/O497HKjk24f6vLuvPTZzyY3Kb5J
vk5l/Pn8B50DNNumwVj4JQQ2vuQXwAHmJGpEGNxhHdZae4DClnFgK3RQ0ScjlBDU5Djhetg6HC4+
TrsGiB06Cd5GqQsYbIJh7CSKVqAtR/A641FNNWWL2/MnJubDv3ufBQPhaA6Dp4WBWU0wThuRecNq
1BOuDKLemZIpy8RvXf5GQQO9wOIE0kkQLjwg0xqtKCuwcjFHCcK5H0KYOUpe+wJQtTqh37nvInKm
jO0EfVCjA51MnI+AecqnTRp83GEaTDejO2OAPXUgIROhDGyHjP+Tbx91sDbDM114oaShRkMc3jSN
sc6OYw99xfV4ojUedeo8FLp7DzaVaMg5mKS9rOkNz1FzS6d2zcjmgzLiDHMjHSr7DPfBqRYGZszn
rd1U439Ivg7+CjCjbIms58VLUK4cC3lxO9VMVe+dngx/zREIGUAqS40/qygTC84pPB/pIvQsQ+jl
3HqY1QFGnE8B9dSWpe6OgBBsgb+jZIaTNJVEPgveKtZxuUPWl4aem/zIySkKAOT9/sqDwbWa8oel
3pssHjFYCJgtuPsdv67v9CbTJNFU4OywC8TnNyx3SEHT1yRNMX5RkyDxoj46hEH4tflDbR1+0Qjx
ofwgIbv/2EbgUHgAoCB0cTNH4P6yxAvU53MzzAaTJBx0PSJFZYSTfdoE26z+lWXy7lQ3gRmDPcna
eJziXoPBnTRpPamWsU9ttGLIQAsJ/3j/+MmnL/tyrRbhzI5VccPKTgPvFMPZj/A2+xcfx2sODZyX
c1uL4n0QOp86pqY0s+loQiLuIeu9YU8yOtACIqcAfMshs6O60v3bKfzKvFHHGWMe4C3RvHZNMKk4
ijq0qMvOXWqO4dwvZLWV2DuQtn7OmQuMSdAeYjubXnO9pOistU4WyO3Lz7zZlW4A4utkUTUMoCwu
wmxhc2DW3/GuU+ctnhzKvy/3skFJhxF9XACcXbXffyT4peA36awvYX1hA0CJlLEQC5ytWF21MWLm
iLR3r2V2w5o8uPxgyyA/NFyabqriqPDptFAvt+bjX3/wKamASk9KaEB0oTZIAWlKivBsOTCQhmqh
vEx46z6b87c1k99OyeZ1UHc//0L1xjPYVggJqVgaSDhaKLyS0tInkLjdqsiubt+o1mqsUXdRhusa
Q7oYFRVEGmt6HugIwYuS3+jX66mEwX5CZom9ZCYVfzon2mXaaNSlK1AqP7mA3kaZhnxQk0F+P+Fk
CRJiYgKT/g1ig3YnBhkKYW454tTKzYrzzmfN3hUTyljRL45YfbMwHxJZ7ZtlfSDSzzashDN3LoT2
8nWDy98GX3LhBsvA2WUo0kD4oplB1zxvwx7J3hF+6GtE6CPsCq19lroE4FqCy2zEk/MVDTDp1Yca
08B8l6JkNpis/cXYINLPeCVNCGOT71veIaNdebTZ9En6syBSh+J2olLPLvSRWEm9+a4L0rI0Kd3s
8WIK6oD7WEOag4hMTI36Yz5COL/I5AKCI3Lx7qTw6UYfjcBTlsx/YoXwGbD6gXm121XuLT5OeIBv
YaBQgc8WeIvmsGC4sHQr6XdkLaSDOn8HgYLmQQ+2NkM2g1DqvDGJTk1TuSAMGtBGYy5K4FUOUBbO
9HCdaOuL6buzlhrkl0gA1GbGRowCIImfbvOPoZ+OEXGFOjZ3flNJ7Fk4TsrMqwAK/VU7nsMbkUpo
8i4w5YjQcC9n+MHF3PodVvha0PAEOdbR1CR2Kq4BwAFPQr0FC38SZ3DrXqFffh4nRv9VvcNTnutq
TM0YKaBN8nbtewJ/x2hdX9se7v8aaJ0S8ZBtGzvetfuJjl5QtaeoVh5811u+aRF9cVMiKpO4oNUL
XGkvlGUy4nCEU4XQvf5VXe1W+vQFNNEWRC5QmzGpA7VHpnDvTkZZCtf/uHx5EBL6OB5xWJLjt1VH
/pefHlGCn5Z5yPqyQ4yOE7DLC5TpiOAAh3UEhIc506jAeP6WJqknXt1B8x9Alc9BR3hVqOKXHN+C
ilhClDWo8i4GS6hJWOH18EL492By6b6diFHWyfgD6X+iykaUaBFlZoyP0A4INCoqQ60JDM0T3LtL
mUoCd3Ar2dAZ1DFB889x4YmPLP1g1YyjrkV7wj5065lKasetZ06ta2O1OFc+YTYbfTCT6GdN8QKp
H51QOLWVX9mImZ0=
`protect end_protected
|
entity access1 is
end entity;
architecture test of access1 is
type list;
type list_ptr is access list;
type list is record
link : list_ptr;
value : integer;
end record;
procedure list_add(l : inout list_ptr; v : integer) is
variable n : list_ptr;
begin
n := new list;
n.link := l;
n.value := v;
l := n;
end procedure;
begin
end architecture;
|
entity access1 is
end entity;
architecture test of access1 is
type list;
type list_ptr is access list;
type list is record
link : list_ptr;
value : integer;
end record;
procedure list_add(l : inout list_ptr; v : integer) is
variable n : list_ptr;
begin
n := new list;
n.link := l;
n.value := v;
l := n;
end procedure;
begin
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grpci2_phy_net is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0
);
port(
pciclk : in std_logic;
--pcii : in pci_in_type;
pcii_rst : in std_ulogic;
pcii_gnt : in std_ulogic;
pcii_idsel : in std_ulogic;
pcii_ad : in std_logic_vector(31 downto 0);
pcii_cbe : in std_logic_vector(3 downto 0);
pcii_frame : in std_ulogic;
pcii_irdy : in std_ulogic;
pcii_trdy : in std_ulogic;
pcii_devsel : in std_ulogic;
pcii_stop : in std_ulogic;
pcii_lock : in std_ulogic;
pcii_perr : in std_ulogic;
pcii_serr : in std_ulogic;
pcii_par : in std_ulogic;
pcii_host : in std_ulogic;
pcii_pci66 : in std_ulogic;
pcii_pme_status : in std_ulogic;
pcii_int : in std_logic_vector(3 downto 0);
--phyi : in grpci2_phy_in_type;
phyi_pcirstout : in std_logic;
phyi_pciasyncrst : in std_logic;
phyi_pcisoftrst : in std_logic_vector(2 downto 0);
phyi_pciinten : in std_logic_vector(3 downto 0);
phyi_m_request : in std_logic;
phyi_m_mabort : in std_logic;
phyi_pr_m_fstate : in std_logic_vector(1 downto 0); --pci_master_fifo_state_type;
--phyi_pr_m_cfifo : in pci_core_fifo_vector_type;
phyi_pr_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_0_last : in std_logic;
phyi_pr_m_cfifo_0_stlast : in std_logic;
phyi_pr_m_cfifo_0_hold : in std_logic;
phyi_pr_m_cfifo_0_valid : in std_logic;
phyi_pr_m_cfifo_0_err : in std_logic;
phyi_pr_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_1_last : in std_logic;
phyi_pr_m_cfifo_1_stlast : in std_logic;
phyi_pr_m_cfifo_1_hold : in std_logic;
phyi_pr_m_cfifo_1_valid : in std_logic;
phyi_pr_m_cfifo_1_err : in std_logic;
phyi_pr_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_2_last : in std_logic;
phyi_pr_m_cfifo_2_stlast : in std_logic;
phyi_pr_m_cfifo_2_hold : in std_logic;
phyi_pr_m_cfifo_2_valid : in std_logic;
phyi_pr_m_cfifo_2_err : in std_logic;
--phyi_pv_m_cfifo : in pci_core_fifo_vector_type;
phyi_pv_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_0_last : in std_logic;
phyi_pv_m_cfifo_0_stlast : in std_logic;
phyi_pv_m_cfifo_0_hold : in std_logic;
phyi_pv_m_cfifo_0_valid : in std_logic;
phyi_pv_m_cfifo_0_err : in std_logic;
phyi_pv_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_1_last : in std_logic;
phyi_pv_m_cfifo_1_stlast : in std_logic;
phyi_pv_m_cfifo_1_hold : in std_logic;
phyi_pv_m_cfifo_1_valid : in std_logic;
phyi_pv_m_cfifo_1_err : in std_logic;
phyi_pv_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_2_last : in std_logic;
phyi_pv_m_cfifo_2_stlast : in std_logic;
phyi_pv_m_cfifo_2_hold : in std_logic;
phyi_pv_m_cfifo_2_valid : in std_logic;
phyi_pv_m_cfifo_2_err : in std_logic;
phyi_pr_m_addr : in std_logic_vector(31 downto 0);
phyi_pr_m_cbe_data : in std_logic_vector(3 downto 0);
phyi_pr_m_cbe_cmd : in std_logic_vector(3 downto 0);
phyi_pr_m_first : in std_logic_vector(1 downto 0);
phyi_pv_m_term : in std_logic_vector(1 downto 0);
phyi_pr_m_ltimer : in std_logic_vector(7 downto 0);
phyi_pr_m_burst : in std_logic;
phyi_pr_m_abort : in std_logic_vector(0 downto 0);
phyi_pr_m_perren : in std_logic_vector(0 downto 0);
phyi_pr_m_done_fifo : in std_logic;
phyi_t_abort : in std_logic;
phyi_t_ready : in std_logic;
phyi_t_retry : in std_logic;
phyi_pr_t_state : in std_logic_vector(2 downto 0); --pci_target_state_type;
phyi_pv_t_state : in std_logic_vector(2 downto 0); --pci_target_state_type;
phyi_pr_t_fstate : in std_logic_vector(1 downto 0); --pci_target_fifo_state_type;
--phyi_pr_t_cfifo : in pci_core_fifo_vector_type;
phyi_pr_t_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_0_last : in std_logic;
phyi_pr_t_cfifo_0_stlast : in std_logic;
phyi_pr_t_cfifo_0_hold : in std_logic;
phyi_pr_t_cfifo_0_valid : in std_logic;
phyi_pr_t_cfifo_0_err : in std_logic;
phyi_pr_t_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_1_last : in std_logic;
phyi_pr_t_cfifo_1_stlast : in std_logic;
phyi_pr_t_cfifo_1_hold : in std_logic;
phyi_pr_t_cfifo_1_valid : in std_logic;
phyi_pr_t_cfifo_1_err : in std_logic;
phyi_pr_t_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_2_last : in std_logic;
phyi_pr_t_cfifo_2_stlast : in std_logic;
phyi_pr_t_cfifo_2_hold : in std_logic;
phyi_pr_t_cfifo_2_valid : in std_logic;
phyi_pr_t_cfifo_2_err : in std_logic;
phyi_pv_t_diswithout : in std_logic;
phyi_pr_t_stoped : in std_logic;
phyi_pr_t_lcount : in std_logic_vector(2 downto 0);
phyi_pr_t_first_word : in std_logic;
phyi_pr_t_cur_acc_0_read : in std_logic;
phyi_pv_t_hold_write : in std_logic;
phyi_pv_t_hold_reset : in std_logic;
phyi_pr_conf_comm_perren : in std_logic;
phyi_pr_conf_comm_serren : in std_logic;
--pcio : out pci_out_type;
pcio_aden : out std_ulogic;
pcio_vaden : out std_logic_vector(31 downto 0);
pcio_cbeen : out std_logic_vector(3 downto 0);
pcio_frameen : out std_ulogic;
pcio_irdyen : out std_ulogic;
pcio_trdyen : out std_ulogic;
pcio_devselen : out std_ulogic;
pcio_stopen : out std_ulogic;
pcio_ctrlen : out std_ulogic;
pcio_perren : out std_ulogic;
pcio_paren : out std_ulogic;
pcio_reqen : out std_ulogic;
pcio_locken : out std_ulogic;
pcio_serren : out std_ulogic;
pcio_inten : out std_ulogic;
pcio_vinten : out std_logic_vector(3 downto 0);
pcio_req : out std_ulogic;
pcio_ad : out std_logic_vector(31 downto 0);
pcio_cbe : out std_logic_vector(3 downto 0);
pcio_frame : out std_ulogic;
pcio_irdy : out std_ulogic;
pcio_trdy : out std_ulogic;
pcio_devsel : out std_ulogic;
pcio_stop : out std_ulogic;
pcio_perr : out std_ulogic;
pcio_serr : out std_ulogic;
pcio_par : out std_ulogic;
pcio_lock : out std_ulogic;
pcio_power_state : out std_logic_vector(1 downto 0);
pcio_pme_enable : out std_ulogic;
pcio_pme_clear : out std_ulogic;
pcio_int : out std_ulogic;
pcio_rst : out std_ulogic;
--phyo : out grpci2_phy_out_type
--phyo_pciv : out pci_in_type;
phyo_pciv_rst : out std_ulogic;
phyo_pciv_gnt : out std_ulogic;
phyo_pciv_idsel : out std_ulogic;
phyo_pciv_ad : out std_logic_vector(31 downto 0);
phyo_pciv_cbe : out std_logic_vector(3 downto 0);
phyo_pciv_frame : out std_ulogic;
phyo_pciv_irdy : out std_ulogic;
phyo_pciv_trdy : out std_ulogic;
phyo_pciv_devsel : out std_ulogic;
phyo_pciv_stop : out std_ulogic;
phyo_pciv_lock : out std_ulogic;
phyo_pciv_perr : out std_ulogic;
phyo_pciv_serr : out std_ulogic;
phyo_pciv_par : out std_ulogic;
phyo_pciv_host : out std_ulogic;
phyo_pciv_pci66 : out std_ulogic;
phyo_pciv_pme_status : out std_ulogic;
phyo_pciv_int : out std_logic_vector(3 downto 0);
phyo_pr_m_state : out std_logic_vector(2 downto 0); --pci_master_state_type;
phyo_pr_m_last : out std_logic_vector(1 downto 0);
phyo_pr_m_hold : out std_logic_vector(1 downto 0);
phyo_pr_m_term : out std_logic_vector(1 downto 0);
phyo_pr_t_hold : out std_logic_vector(0 downto 0);
phyo_pr_t_stop : out std_logic;
phyo_pr_t_abort : out std_logic;
phyo_pr_t_diswithout : out std_logic;
phyo_pr_t_addr_perr : out std_logic;
phyo_pcirsto : out std_logic_vector(0 downto 0);
--phyo_pr_po : out pci_reg_out_type;
phyo_pr_po_ad : out std_logic_vector(31 downto 0);
phyo_pr_po_aden : out std_logic_vector(31 downto 0);
phyo_pr_po_cbe : out std_logic_vector(3 downto 0);
phyo_pr_po_cbeen : out std_logic_vector(3 downto 0);
phyo_pr_po_frame : out std_logic;
phyo_pr_po_frameen : out std_logic;
phyo_pr_po_irdy : out std_logic;
phyo_pr_po_irdyen : out std_logic;
phyo_pr_po_trdy : out std_logic;
phyo_pr_po_trdyen : out std_logic;
phyo_pr_po_stop : out std_logic;
phyo_pr_po_stopen : out std_logic;
phyo_pr_po_devsel : out std_logic;
phyo_pr_po_devselen : out std_logic;
phyo_pr_po_par : out std_logic;
phyo_pr_po_paren : out std_logic;
phyo_pr_po_perr : out std_logic;
phyo_pr_po_perren : out std_logic;
phyo_pr_po_lock : out std_logic;
phyo_pr_po_locken : out std_logic;
phyo_pr_po_req : out std_logic;
phyo_pr_po_reqen : out std_logic;
phyo_pr_po_serren : out std_logic;
phyo_pr_po_inten : out std_logic;
phyo_pr_po_vinten : out std_logic_vector(3 downto 0);
--phyo_pio : out pci_in_type;
phyo_pio_rst : out std_ulogic;
phyo_pio_gnt : out std_ulogic;
phyo_pio_idsel : out std_ulogic;
phyo_pio_ad : out std_logic_vector(31 downto 0);
phyo_pio_cbe : out std_logic_vector(3 downto 0);
phyo_pio_frame : out std_ulogic;
phyo_pio_irdy : out std_ulogic;
phyo_pio_trdy : out std_ulogic;
phyo_pio_devsel : out std_ulogic;
phyo_pio_stop : out std_ulogic;
phyo_pio_lock : out std_ulogic;
phyo_pio_perr : out std_ulogic;
phyo_pio_serr : out std_ulogic;
phyo_pio_par : out std_ulogic;
phyo_pio_host : out std_ulogic;
phyo_pio_pci66 : out std_ulogic;
phyo_pio_pme_status : out std_ulogic;
phyo_pio_int : out std_logic_vector(3 downto 0);
--phyo_poo : out pci_reg_out_type;
phyo_poo_ad : out std_logic_vector(31 downto 0);
phyo_poo_aden : out std_logic_vector(31 downto 0);
phyo_poo_cbe : out std_logic_vector(3 downto 0);
phyo_poo_cbeen : out std_logic_vector(3 downto 0);
phyo_poo_frame : out std_logic;
phyo_poo_frameen : out std_logic;
phyo_poo_irdy : out std_logic;
phyo_poo_irdyen : out std_logic;
phyo_poo_trdy : out std_logic;
phyo_poo_trdyen : out std_logic;
phyo_poo_stop : out std_logic;
phyo_poo_stopen : out std_logic;
phyo_poo_devsel : out std_logic;
phyo_poo_devselen : out std_logic;
phyo_poo_par : out std_logic;
phyo_poo_paren : out std_logic;
phyo_poo_perr : out std_logic;
phyo_poo_perren : out std_logic;
phyo_poo_lock : out std_logic;
phyo_poo_locken : out std_logic;
phyo_poo_req : out std_logic;
phyo_poo_reqen : out std_logic;
phyo_poo_serren : out std_logic;
phyo_poo_inten : out std_logic;
phyo_poo_vinten : out std_logic_vector(3 downto 0)
);
end grpci2_phy_net;
architecture struct of grpci2_phy_net is
component grpci2_phy_rtax_bypass is
-- generic(
-- tech : integer := axcel;
-- oepol : integer := 1;
-- bypass : integer range 0 to 1 := 1;
-- netlist : integer := 1
-- scantest: integer := 0
-- );
port(
pciclk : in std_logic;
--pcii : in pci_in_type;
pcii_rst : in std_ulogic;
pcii_gnt : in std_ulogic;
pcii_idsel : in std_ulogic;
pcii_ad : in std_logic_vector(31 downto 0);
pcii_cbe : in std_logic_vector(3 downto 0);
pcii_frame : in std_ulogic;
pcii_irdy : in std_ulogic;
pcii_trdy : in std_ulogic;
pcii_devsel : in std_ulogic;
pcii_stop : in std_ulogic;
pcii_lock : in std_ulogic;
pcii_perr : in std_ulogic;
pcii_serr : in std_ulogic;
pcii_par : in std_ulogic;
pcii_host : in std_ulogic;
pcii_pci66 : in std_ulogic;
pcii_pme_status : in std_ulogic;
pcii_int : in std_logic_vector(3 downto 0);
--phyi : in grpci2_phy_in_type;
phyi_pcirstout : in std_logic;
phyi_pciasyncrst : in std_logic;
phyi_pcisoftrst : in std_logic_vector(2 downto 0);
phyi_pciinten : in std_logic_vector(3 downto 0);
phyi_m_request : in std_logic;
phyi_m_mabort : in std_logic;
phyi_pr_m_fstate : in std_logic_vector(1 downto 0); --pci_master_fifo_state_type;
--phyi_pr_m_cfifo : in pci_core_fifo_vector_type;
phyi_pr_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_0_last : in std_logic;
phyi_pr_m_cfifo_0_stlast : in std_logic;
phyi_pr_m_cfifo_0_hold : in std_logic;
phyi_pr_m_cfifo_0_valid : in std_logic;
phyi_pr_m_cfifo_0_err : in std_logic;
phyi_pr_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_1_last : in std_logic;
phyi_pr_m_cfifo_1_stlast : in std_logic;
phyi_pr_m_cfifo_1_hold : in std_logic;
phyi_pr_m_cfifo_1_valid : in std_logic;
phyi_pr_m_cfifo_1_err : in std_logic;
phyi_pr_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_2_last : in std_logic;
phyi_pr_m_cfifo_2_stlast : in std_logic;
phyi_pr_m_cfifo_2_hold : in std_logic;
phyi_pr_m_cfifo_2_valid : in std_logic;
phyi_pr_m_cfifo_2_err : in std_logic;
--phyi_pv_m_cfifo : in pci_core_fifo_vector_type;
phyi_pv_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_0_last : in std_logic;
phyi_pv_m_cfifo_0_stlast : in std_logic;
phyi_pv_m_cfifo_0_hold : in std_logic;
phyi_pv_m_cfifo_0_valid : in std_logic;
phyi_pv_m_cfifo_0_err : in std_logic;
phyi_pv_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_1_last : in std_logic;
phyi_pv_m_cfifo_1_stlast : in std_logic;
phyi_pv_m_cfifo_1_hold : in std_logic;
phyi_pv_m_cfifo_1_valid : in std_logic;
phyi_pv_m_cfifo_1_err : in std_logic;
phyi_pv_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_2_last : in std_logic;
phyi_pv_m_cfifo_2_stlast : in std_logic;
phyi_pv_m_cfifo_2_hold : in std_logic;
phyi_pv_m_cfifo_2_valid : in std_logic;
phyi_pv_m_cfifo_2_err : in std_logic;
phyi_pr_m_addr : in std_logic_vector(31 downto 0);
phyi_pr_m_cbe_data : in std_logic_vector(3 downto 0);
phyi_pr_m_cbe_cmd : in std_logic_vector(3 downto 0);
phyi_pr_m_first : in std_logic_vector(1 downto 0);
phyi_pv_m_term : in std_logic_vector(1 downto 0);
phyi_pr_m_ltimer : in std_logic_vector(7 downto 0);
phyi_pr_m_burst : in std_logic;
phyi_pr_m_abort : in std_logic_vector(0 downto 0);
phyi_pr_m_perren : in std_logic_vector(0 downto 0);
phyi_pr_m_done_fifo : in std_logic;
phyi_t_abort : in std_logic;
phyi_t_ready : in std_logic;
phyi_t_retry : in std_logic;
phyi_pr_t_state : in std_logic_vector(2 downto 0); --pci_target_state_type;
phyi_pv_t_state : in std_logic_vector(2 downto 0); --pci_target_state_type;
phyi_pr_t_fstate : in std_logic_vector(1 downto 0); --pci_target_fifo_state_type;
--phyi_pr_t_cfifo : in pci_core_fifo_vector_type;
phyi_pr_t_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_0_last : in std_logic;
phyi_pr_t_cfifo_0_stlast : in std_logic;
phyi_pr_t_cfifo_0_hold : in std_logic;
phyi_pr_t_cfifo_0_valid : in std_logic;
phyi_pr_t_cfifo_0_err : in std_logic;
phyi_pr_t_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_1_last : in std_logic;
phyi_pr_t_cfifo_1_stlast : in std_logic;
phyi_pr_t_cfifo_1_hold : in std_logic;
phyi_pr_t_cfifo_1_valid : in std_logic;
phyi_pr_t_cfifo_1_err : in std_logic;
phyi_pr_t_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_2_last : in std_logic;
phyi_pr_t_cfifo_2_stlast : in std_logic;
phyi_pr_t_cfifo_2_hold : in std_logic;
phyi_pr_t_cfifo_2_valid : in std_logic;
phyi_pr_t_cfifo_2_err : in std_logic;
phyi_pv_t_diswithout : in std_logic;
phyi_pr_t_stoped : in std_logic;
phyi_pr_t_lcount : in std_logic_vector(2 downto 0);
phyi_pr_t_first_word : in std_logic;
phyi_pr_t_cur_acc_0_read : in std_logic;
phyi_pv_t_hold_write : in std_logic;
phyi_pv_t_hold_reset : in std_logic;
phyi_pr_conf_comm_perren : in std_logic;
phyi_pr_conf_comm_serren : in std_logic;
--pcio : out pci_out_type;
pcio_aden : out std_ulogic;
pcio_vaden : out std_logic_vector(31 downto 0);
pcio_cbeen : out std_logic_vector(3 downto 0);
pcio_frameen : out std_ulogic;
pcio_irdyen : out std_ulogic;
pcio_trdyen : out std_ulogic;
pcio_devselen : out std_ulogic;
pcio_stopen : out std_ulogic;
pcio_ctrlen : out std_ulogic;
pcio_perren : out std_ulogic;
pcio_paren : out std_ulogic;
pcio_reqen : out std_ulogic;
pcio_locken : out std_ulogic;
pcio_serren : out std_ulogic;
pcio_inten : out std_ulogic;
pcio_vinten : out std_logic_vector(3 downto 0);
pcio_req : out std_ulogic;
pcio_ad : out std_logic_vector(31 downto 0);
pcio_cbe : out std_logic_vector(3 downto 0);
pcio_frame : out std_ulogic;
pcio_irdy : out std_ulogic;
pcio_trdy : out std_ulogic;
pcio_devsel : out std_ulogic;
pcio_stop : out std_ulogic;
pcio_perr : out std_ulogic;
pcio_serr : out std_ulogic;
pcio_par : out std_ulogic;
pcio_lock : out std_ulogic;
pcio_power_state : out std_logic_vector(1 downto 0);
pcio_pme_enable : out std_ulogic;
pcio_pme_clear : out std_ulogic;
pcio_int : out std_ulogic;
pcio_rst : out std_ulogic;
--phyo : out grpci2_phy_out_type
--phyo_pciv : out pci_in_type;
phyo_pciv_rst : out std_ulogic;
phyo_pciv_gnt : out std_ulogic;
phyo_pciv_idsel : out std_ulogic;
phyo_pciv_ad : out std_logic_vector(31 downto 0);
phyo_pciv_cbe : out std_logic_vector(3 downto 0);
phyo_pciv_frame : out std_ulogic;
phyo_pciv_irdy : out std_ulogic;
phyo_pciv_trdy : out std_ulogic;
phyo_pciv_devsel : out std_ulogic;
phyo_pciv_stop : out std_ulogic;
phyo_pciv_lock : out std_ulogic;
phyo_pciv_perr : out std_ulogic;
phyo_pciv_serr : out std_ulogic;
phyo_pciv_par : out std_ulogic;
phyo_pciv_host : out std_ulogic;
phyo_pciv_pci66 : out std_ulogic;
phyo_pciv_pme_status : out std_ulogic;
phyo_pciv_int : out std_logic_vector(3 downto 0);
phyo_pr_m_state : out std_logic_vector(2 downto 0); --pci_master_state_type;
phyo_pr_m_last : out std_logic_vector(1 downto 0);
phyo_pr_m_hold : out std_logic_vector(1 downto 0);
phyo_pr_m_term : out std_logic_vector(1 downto 0);
phyo_pr_t_hold : out std_logic_vector(0 downto 0);
phyo_pr_t_stop : out std_logic;
phyo_pr_t_abort : out std_logic;
phyo_pr_t_diswithout : out std_logic;
phyo_pr_t_addr_perr : out std_logic;
phyo_pcirsto : out std_logic_vector(0 downto 0);
--phyo_pr_po : out pci_reg_out_type;
phyo_pr_po_ad : out std_logic_vector(31 downto 0);
phyo_pr_po_aden : out std_logic_vector(31 downto 0);
phyo_pr_po_cbe : out std_logic_vector(3 downto 0);
phyo_pr_po_cbeen : out std_logic_vector(3 downto 0);
phyo_pr_po_frame : out std_logic;
phyo_pr_po_frameen : out std_logic;
phyo_pr_po_irdy : out std_logic;
phyo_pr_po_irdyen : out std_logic;
phyo_pr_po_trdy : out std_logic;
phyo_pr_po_trdyen : out std_logic;
phyo_pr_po_stop : out std_logic;
phyo_pr_po_stopen : out std_logic;
phyo_pr_po_devsel : out std_logic;
phyo_pr_po_devselen : out std_logic;
phyo_pr_po_par : out std_logic;
phyo_pr_po_paren : out std_logic;
phyo_pr_po_perr : out std_logic;
phyo_pr_po_perren : out std_logic;
phyo_pr_po_lock : out std_logic;
phyo_pr_po_locken : out std_logic;
phyo_pr_po_req : out std_logic;
phyo_pr_po_reqen : out std_logic;
phyo_pr_po_serren : out std_logic;
phyo_pr_po_inten : out std_logic;
phyo_pr_po_vinten : out std_logic_vector(3 downto 0);
--phyo_pio : out pci_in_type;
phyo_pio_rst : out std_ulogic;
phyo_pio_gnt : out std_ulogic;
phyo_pio_idsel : out std_ulogic;
phyo_pio_ad : out std_logic_vector(31 downto 0);
phyo_pio_cbe : out std_logic_vector(3 downto 0);
phyo_pio_frame : out std_ulogic;
phyo_pio_irdy : out std_ulogic;
phyo_pio_trdy : out std_ulogic;
phyo_pio_devsel : out std_ulogic;
phyo_pio_stop : out std_ulogic;
phyo_pio_lock : out std_ulogic;
phyo_pio_perr : out std_ulogic;
phyo_pio_serr : out std_ulogic;
phyo_pio_par : out std_ulogic;
phyo_pio_host : out std_ulogic;
phyo_pio_pci66 : out std_ulogic;
phyo_pio_pme_status : out std_ulogic;
phyo_pio_int : out std_logic_vector(3 downto 0);
--phyo_poo : out pci_reg_out_type;
phyo_poo_ad : out std_logic_vector(31 downto 0);
phyo_poo_aden : out std_logic_vector(31 downto 0);
phyo_poo_cbe : out std_logic_vector(3 downto 0);
phyo_poo_cbeen : out std_logic_vector(3 downto 0);
phyo_poo_frame : out std_logic;
phyo_poo_frameen : out std_logic;
phyo_poo_irdy : out std_logic;
phyo_poo_irdyen : out std_logic;
phyo_poo_trdy : out std_logic;
phyo_poo_trdyen : out std_logic;
phyo_poo_stop : out std_logic;
phyo_poo_stopen : out std_logic;
phyo_poo_devsel : out std_logic;
phyo_poo_devselen : out std_logic;
phyo_poo_par : out std_logic;
phyo_poo_paren : out std_logic;
phyo_poo_perr : out std_logic;
phyo_poo_perren : out std_logic;
phyo_poo_lock : out std_logic;
phyo_poo_locken : out std_logic;
phyo_poo_req : out std_logic;
phyo_poo_reqen : out std_logic;
phyo_poo_serren : out std_logic;
phyo_poo_inten : out std_logic;
phyo_poo_vinten : out std_logic_vector(3 downto 0)
);
end component;
begin
ax : if ((tech = axcel) or (tech = axdsp)) and (bypass = 1) generate
phy_bypass_rtax : grpci2_phy_rtax_bypass
port map(
pciclk => pciclk,
--pcii : in pci_in_type,
pcii_rst => pcii_rst,
pcii_gnt => pcii_gnt,
pcii_idsel => pcii_idsel,
pcii_ad => pcii_ad,
pcii_cbe => pcii_cbe,
pcii_frame => pcii_frame,
pcii_irdy => pcii_irdy,
pcii_trdy => pcii_trdy,
pcii_devsel => pcii_devsel,
pcii_stop => pcii_stop,
pcii_lock => pcii_lock,
pcii_perr => pcii_perr,
pcii_serr => pcii_serr,
pcii_par => pcii_par,
pcii_host => pcii_host,
pcii_pci66 => pcii_pci66,
pcii_pme_status => pcii_pme_status,
pcii_int => pcii_int,
--phyi : in grpci2_phy_in_type,
phyi_pcirstout => phyi_pcirstout,
phyi_pciasyncrst => phyi_pciasyncrst,
phyi_pcisoftrst => phyi_pcisoftrst,
phyi_pciinten => phyi_pciinten,
phyi_m_request => phyi_m_request,
phyi_m_mabort => phyi_m_mabort,
phyi_pr_m_fstate => phyi_pr_m_fstate,
phyi_pr_m_cfifo_0_data => phyi_pr_m_cfifo_0_data,
phyi_pr_m_cfifo_0_last => phyi_pr_m_cfifo_0_last,
phyi_pr_m_cfifo_0_stlast => phyi_pr_m_cfifo_0_stlast,
phyi_pr_m_cfifo_0_hold => phyi_pr_m_cfifo_0_hold,
phyi_pr_m_cfifo_0_valid => phyi_pr_m_cfifo_0_valid,
phyi_pr_m_cfifo_0_err => phyi_pr_m_cfifo_0_err,
phyi_pr_m_cfifo_1_data => phyi_pr_m_cfifo_1_data,
phyi_pr_m_cfifo_1_last => phyi_pr_m_cfifo_1_last,
phyi_pr_m_cfifo_1_stlast => phyi_pr_m_cfifo_1_stlast,
phyi_pr_m_cfifo_1_hold => phyi_pr_m_cfifo_1_hold,
phyi_pr_m_cfifo_1_valid => phyi_pr_m_cfifo_1_valid,
phyi_pr_m_cfifo_1_err => phyi_pr_m_cfifo_1_err,
phyi_pr_m_cfifo_2_data => phyi_pr_m_cfifo_2_data,
phyi_pr_m_cfifo_2_last => phyi_pr_m_cfifo_2_last,
phyi_pr_m_cfifo_2_stlast => phyi_pr_m_cfifo_2_stlast,
phyi_pr_m_cfifo_2_hold => phyi_pr_m_cfifo_2_hold,
phyi_pr_m_cfifo_2_valid => phyi_pr_m_cfifo_2_valid,
phyi_pr_m_cfifo_2_err => phyi_pr_m_cfifo_2_err,
phyi_pv_m_cfifo_0_data => phyi_pv_m_cfifo_0_data,
phyi_pv_m_cfifo_0_last => phyi_pv_m_cfifo_0_last,
phyi_pv_m_cfifo_0_stlast => phyi_pv_m_cfifo_0_stlast,
phyi_pv_m_cfifo_0_hold => phyi_pv_m_cfifo_0_hold,
phyi_pv_m_cfifo_0_valid => phyi_pv_m_cfifo_0_valid,
phyi_pv_m_cfifo_0_err => phyi_pv_m_cfifo_0_err,
phyi_pv_m_cfifo_1_data => phyi_pv_m_cfifo_1_data,
phyi_pv_m_cfifo_1_last => phyi_pv_m_cfifo_1_last,
phyi_pv_m_cfifo_1_stlast => phyi_pv_m_cfifo_1_stlast,
phyi_pv_m_cfifo_1_hold => phyi_pv_m_cfifo_1_hold,
phyi_pv_m_cfifo_1_valid => phyi_pv_m_cfifo_1_valid,
phyi_pv_m_cfifo_1_err => phyi_pv_m_cfifo_1_err,
phyi_pv_m_cfifo_2_data => phyi_pv_m_cfifo_2_data,
phyi_pv_m_cfifo_2_last => phyi_pv_m_cfifo_2_last,
phyi_pv_m_cfifo_2_stlast => phyi_pv_m_cfifo_2_stlast,
phyi_pv_m_cfifo_2_hold => phyi_pv_m_cfifo_2_hold,
phyi_pv_m_cfifo_2_valid => phyi_pv_m_cfifo_2_valid,
phyi_pv_m_cfifo_2_err => phyi_pv_m_cfifo_2_err,
phyi_pr_m_addr => phyi_pr_m_addr,
phyi_pr_m_cbe_data => phyi_pr_m_cbe_data,
phyi_pr_m_cbe_cmd => phyi_pr_m_cbe_cmd,
phyi_pr_m_first => phyi_pr_m_first,
phyi_pv_m_term => phyi_pv_m_term,
phyi_pr_m_ltimer => phyi_pr_m_ltimer,
phyi_pr_m_burst => phyi_pr_m_burst,
phyi_pr_m_abort => phyi_pr_m_abort,
phyi_pr_m_perren => phyi_pr_m_perren,
phyi_pr_m_done_fifo => phyi_pr_m_done_fifo,
phyi_t_abort => phyi_t_abort,
phyi_t_ready => phyi_t_ready,
phyi_t_retry => phyi_t_retry,
phyi_pr_t_state => phyi_pr_t_state,
phyi_pv_t_state => phyi_pv_t_state,
phyi_pr_t_fstate => phyi_pr_t_fstate,
phyi_pr_t_cfifo_0_data => phyi_pr_t_cfifo_0_data,
phyi_pr_t_cfifo_0_last => phyi_pr_t_cfifo_0_last,
phyi_pr_t_cfifo_0_stlast => phyi_pr_t_cfifo_0_stlast,
phyi_pr_t_cfifo_0_hold => phyi_pr_t_cfifo_0_hold,
phyi_pr_t_cfifo_0_valid => phyi_pr_t_cfifo_0_valid,
phyi_pr_t_cfifo_0_err => phyi_pr_t_cfifo_0_err,
phyi_pr_t_cfifo_1_data => phyi_pr_t_cfifo_1_data,
phyi_pr_t_cfifo_1_last => phyi_pr_t_cfifo_1_last,
phyi_pr_t_cfifo_1_stlast => phyi_pr_t_cfifo_1_stlast,
phyi_pr_t_cfifo_1_hold => phyi_pr_t_cfifo_1_hold,
phyi_pr_t_cfifo_1_valid => phyi_pr_t_cfifo_1_valid,
phyi_pr_t_cfifo_1_err => phyi_pr_t_cfifo_1_err,
phyi_pr_t_cfifo_2_data => phyi_pr_t_cfifo_2_data,
phyi_pr_t_cfifo_2_last => phyi_pr_t_cfifo_2_last,
phyi_pr_t_cfifo_2_stlast => phyi_pr_t_cfifo_2_stlast,
phyi_pr_t_cfifo_2_hold => phyi_pr_t_cfifo_2_hold,
phyi_pr_t_cfifo_2_valid => phyi_pr_t_cfifo_2_valid,
phyi_pr_t_cfifo_2_err => phyi_pr_t_cfifo_2_err,
phyi_pv_t_diswithout => phyi_pv_t_diswithout,
phyi_pr_t_stoped => phyi_pr_t_stoped,
phyi_pr_t_lcount => phyi_pr_t_lcount,
phyi_pr_t_first_word => phyi_pr_t_first_word,
phyi_pr_t_cur_acc_0_read => phyi_pr_t_cur_acc_0_read,
phyi_pv_t_hold_write => phyi_pv_t_hold_write,
phyi_pv_t_hold_reset => phyi_pv_t_hold_reset,
phyi_pr_conf_comm_perren => phyi_pr_conf_comm_perren,
phyi_pr_conf_comm_serren => phyi_pr_conf_comm_serren,
--pcio : out pci_out_type,
pcio_aden => pcio_aden,
pcio_vaden => pcio_vaden,
pcio_cbeen => pcio_cbeen,
pcio_frameen => pcio_frameen,
pcio_irdyen => pcio_irdyen,
pcio_trdyen => pcio_trdyen,
pcio_devselen => pcio_devselen,
pcio_stopen => pcio_stopen,
pcio_ctrlen => pcio_ctrlen,
pcio_perren => pcio_perren,
pcio_paren => pcio_paren,
pcio_reqen => pcio_reqen,
pcio_locken => pcio_locken,
pcio_serren => pcio_serren,
pcio_inten => pcio_inten,
pcio_vinten => pcio_vinten,
pcio_req => pcio_req,
pcio_ad => pcio_ad,
pcio_cbe => pcio_cbe,
pcio_frame => pcio_frame,
pcio_irdy => pcio_irdy,
pcio_trdy => pcio_trdy,
pcio_devsel => pcio_devsel,
pcio_stop => pcio_stop,
pcio_perr => pcio_perr,
pcio_serr => pcio_serr,
pcio_par => pcio_par,
pcio_lock => pcio_lock,
pcio_power_state => pcio_power_state,
pcio_pme_enable => pcio_pme_enable,
pcio_pme_clear => pcio_pme_clear,
pcio_int => pcio_int,
pcio_rst => pcio_rst,
--phyo : out grpci2_phy_out_type
phyo_pciv_rst => phyo_pciv_rst,
phyo_pciv_gnt => phyo_pciv_gnt,
phyo_pciv_idsel => phyo_pciv_idsel,
phyo_pciv_ad => phyo_pciv_ad,
phyo_pciv_cbe => phyo_pciv_cbe,
phyo_pciv_frame => phyo_pciv_frame,
phyo_pciv_irdy => phyo_pciv_irdy,
phyo_pciv_trdy => phyo_pciv_trdy,
phyo_pciv_devsel => phyo_pciv_devsel,
phyo_pciv_stop => phyo_pciv_stop,
phyo_pciv_lock => phyo_pciv_lock,
phyo_pciv_perr => phyo_pciv_perr,
phyo_pciv_serr => phyo_pciv_serr,
phyo_pciv_par => phyo_pciv_par,
phyo_pciv_host => phyo_pciv_host,
phyo_pciv_pci66 => phyo_pciv_pci66,
phyo_pciv_pme_status => phyo_pciv_pme_status,
phyo_pciv_int => phyo_pciv_int,
phyo_pr_m_state => phyo_pr_m_state,
phyo_pr_m_last => phyo_pr_m_last,
phyo_pr_m_hold => phyo_pr_m_hold,
phyo_pr_m_term => phyo_pr_m_term,
phyo_pr_t_hold => phyo_pr_t_hold,
phyo_pr_t_stop => phyo_pr_t_stop,
phyo_pr_t_abort => phyo_pr_t_abort,
phyo_pr_t_diswithout => phyo_pr_t_diswithout,
phyo_pr_t_addr_perr => phyo_pr_t_addr_perr,
phyo_pcirsto => phyo_pcirsto,
phyo_pr_po_ad => phyo_pr_po_ad,
phyo_pr_po_aden => phyo_pr_po_aden,
phyo_pr_po_cbe => phyo_pr_po_cbe,
phyo_pr_po_cbeen => phyo_pr_po_cbeen,
phyo_pr_po_frame => phyo_pr_po_frame,
phyo_pr_po_frameen => phyo_pr_po_frameen,
phyo_pr_po_irdy => phyo_pr_po_irdy,
phyo_pr_po_irdyen => phyo_pr_po_irdyen,
phyo_pr_po_trdy => phyo_pr_po_trdy,
phyo_pr_po_trdyen => phyo_pr_po_trdyen,
phyo_pr_po_stop => phyo_pr_po_stop,
phyo_pr_po_stopen => phyo_pr_po_stopen,
phyo_pr_po_devsel => phyo_pr_po_devsel,
phyo_pr_po_devselen => phyo_pr_po_devselen,
phyo_pr_po_par => phyo_pr_po_par,
phyo_pr_po_paren => phyo_pr_po_paren,
phyo_pr_po_perr => phyo_pr_po_perr,
phyo_pr_po_perren => phyo_pr_po_perren,
phyo_pr_po_lock => phyo_pr_po_lock,
phyo_pr_po_locken => phyo_pr_po_locken,
phyo_pr_po_req => phyo_pr_po_req,
phyo_pr_po_reqen => phyo_pr_po_reqen,
phyo_pr_po_serren => phyo_pr_po_serren,
phyo_pr_po_inten => phyo_pr_po_inten,
phyo_pr_po_vinten => phyo_pr_po_vinten,
phyo_pio_rst => phyo_pio_rst,
phyo_pio_gnt => phyo_pio_gnt,
phyo_pio_idsel => phyo_pio_idsel,
phyo_pio_ad => phyo_pio_ad,
phyo_pio_cbe => phyo_pio_cbe,
phyo_pio_frame => phyo_pio_frame,
phyo_pio_irdy => phyo_pio_irdy,
phyo_pio_trdy => phyo_pio_trdy,
phyo_pio_devsel => phyo_pio_devsel,
phyo_pio_stop => phyo_pio_stop,
phyo_pio_lock => phyo_pio_lock,
phyo_pio_perr => phyo_pio_perr,
phyo_pio_serr => phyo_pio_serr,
phyo_pio_par => phyo_pio_par,
phyo_pio_host => phyo_pio_host,
phyo_pio_pci66 => phyo_pio_pci66,
phyo_pio_pme_status => phyo_pio_pme_status,
phyo_pio_int => phyo_pio_int,
phyo_poo_ad => phyo_poo_ad,
phyo_poo_aden => phyo_poo_aden,
phyo_poo_cbe => phyo_poo_cbe,
phyo_poo_cbeen => phyo_poo_cbeen,
phyo_poo_frame => phyo_poo_frame,
phyo_poo_frameen => phyo_poo_frameen,
phyo_poo_irdy => phyo_poo_irdy,
phyo_poo_irdyen => phyo_poo_irdyen,
phyo_poo_trdy => phyo_poo_trdy,
phyo_poo_trdyen => phyo_poo_trdyen,
phyo_poo_stop => phyo_poo_stop,
phyo_poo_stopen => phyo_poo_stopen,
phyo_poo_devsel => phyo_poo_devsel,
phyo_poo_devselen => phyo_poo_devselen,
phyo_poo_par => phyo_poo_par,
phyo_poo_paren => phyo_poo_paren,
phyo_poo_perr => phyo_poo_perr,
phyo_poo_perren => phyo_poo_perren,
phyo_poo_lock => phyo_poo_lock,
phyo_poo_locken => phyo_poo_locken,
phyo_poo_req => phyo_poo_req,
phyo_poo_reqen => phyo_poo_reqen,
phyo_poo_serren => phyo_poo_serren,
phyo_poo_inten => phyo_poo_inten,
phyo_poo_vinten => phyo_poo_vinten
);
end generate;
-- pragma translate_off
nonet : if not (((tech = axcel) or (tech = axdsp)) and
(bypass = 1))
generate
err : process
begin
assert False report "ERROR : No pci_arb netlist available for this configuration!"
severity Failure;
wait;
end process;
end generate;
-- pragma translate_on
end struct;
|
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/6/30 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Compares a the look ahead buffer to a candidate and returns the number of bytes before the first
--* non-matching pair. The counting starts at the least significant end of the look ahead and the candidate
--*
--***************************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VComponents.all;
entity comparator is
port (
-- ClkxCI : in std_logic;
-- RstxRI : in std_logic;
-- EnxSI : in std_logic;
LookAheadxDI : in std_logic_vector(16*8-1 downto 0);
LookAheadLenxDI : in integer range 0 to 16; -- how many bytes of LookAheadxDI are valid
CandidatexDI : in std_logic_vector(16*8-1 downto 0);
CandidateLenxDI : in integer range 0 to 16; -- how many bytes of CandidatexDI are valid
MatchLenxDO : out integer range 0 to 16); -- length of the match in bytes
end comparator;
architecture Behavioral of comparator is
signal MatchVectorxS : std_logic_vector(15 downto 0); -- match signals for the individual bytes
signal RawMatchLenxD : integer range 0 to 16; -- number of matching bytes (before further processing)
signal MaxLengthxD : integer range 0 to 16; -- smaller of the two input signal length;
begin
-- implement 16 byte wide comparators
genByteComps : for i in 0 to 15 generate
MatchVectorxS(i) <= '1' when CandidatexDI((i+1)*8-1 downto i*8) = LookAheadxDI((i+1)*8-1 downto i*8) else '0';
end generate genByteComps;
-- count the number of leading bytes to determine the match length
process (MatchVectorxS)
variable cnt : integer range 0 to 16 := 0;
begin -- process
cnt := 0;
cntLoop : for i in 0 to 15 loop
if MatchVectorxS(i) = '1' then
cnt := cnt + 1;
else
exit cntLoop;
end if;
end loop; -- i
RawMatchLenxD <= cnt;
end process;
-- the match length can not be longer than the shorter of the two data inputs
MaxLengthxD <= CandidateLenxDI when CandidateLenxDI < LookAheadLenxDI else LookAheadLenxDI;
-- make sure the match length is not bigger than the max length
MatchLenxDO <= RawMatchLenxD when RawMatchLenxD <= MaxLengthxD else MaxLengthxD;
end Behavioral;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: divisor10.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY divisor10 IS
PORT
(
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END divisor10;
ARCHITECTURE SYN OF divisor10 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(29 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 2500000,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 30
)
PORT MAP (
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "2500000"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "30"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "2500000"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL divisor10_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
--
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end slib_edge_detect;
architecture rtl of slib_edge_detect is
signal iDd : std_logic; -- D register
begin
-- Store D
ED_D: process (RST, CLK)
begin
if (RST = '1') then
iDd <= '0';
elsif (CLK'event and CLK='1') then
iDd <= D;
end if;
end process;
-- Output ports
RE <= '1' when iDd = '0' and D = '1' else '0';
FE <= '1' when iDd = '1' and D = '0' else '0';
end rtl;
|
-- $Id: ibdr_rk11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_rk11 - syn
-- Description: ibus dev(rem): RK11-A/B
--
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 46 248 16 137 s 7.2
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-05-24 219 1.0.9 add CE_MSEC input; inc sector counter every msec
-- BUGFIX: sector counter now counts 000,...,013.
-- 2009-05-21 217 1.0.8 cancel pending interrupt requests when IE=0
-- 2009-05-16 216 1.0.7 BUGFIX: correct interrupt on IE 0->1 logic
-- BUGFIX: re-work the seek complete handling
-- 2008-08-22 161 1.0.6 use iblib
-- 2008-05-30 151 1.0.5 BUGFIX: do control reset locally now, add CRDONE
-- 2008-03-30 131 1.0.4 issue interrupt when IDE bit set with GO=0
-- 2008-02-23 118 1.0.3 remove redundant condition in rkda access code
-- fix bug in control reset logic (we's missing)
-- 2008-01-20 113 1.0.2 Fix busy handling when control reset done
-- 2008-01-20 112 1.0.1 Fix scp handling; use BRESET
-- 2008-01-06 111 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_rk11 is -- ibus dev(rem): RK11
-- fixed address: 177400
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_rk11;
architecture syn of ibdr_rk11 is
constant ibaddr_rk11 : slv16 := slv(to_unsigned(8#177400#,16));
constant ibaddr_rkds : slv3 := "000"; -- rkds address offset
constant ibaddr_rker : slv3 := "001"; -- rker address offset
constant ibaddr_rkcs : slv3 := "010"; -- rkcs address offset
constant ibaddr_rkwc : slv3 := "011"; -- rkwc address offset
constant ibaddr_rkba : slv3 := "100"; -- rkba address offset
constant ibaddr_rkda : slv3 := "101"; -- rkda address offset
constant ibaddr_rkmr : slv3 := "110"; -- rkmr address offset
constant ibaddr_rkdb : slv3 := "111"; -- rkdb address offset
subtype rkds_ibf_id is integer range 15 downto 13;
constant rkds_ibf_adry : integer := 6;
constant rkds_ibf_scsa : integer := 4;
subtype rkds_ibf_sc is integer range 3 downto 0;
subtype rker_ibf_he is integer range 15 downto 5;
constant rker_ibf_cse : integer := 1;
constant rker_ibf_wce : integer := 0;
constant rkcs_ibf_err : integer := 15;
constant rkcs_ibf_he : integer := 14;
constant rkcs_ibf_scp : integer := 13;
constant rkcs_ibf_maint : integer := 12;
constant rkcs_ibf_rdy : integer := 7;
constant rkcs_ibf_ide : integer := 6;
subtype rkcs_ibf_mex is integer range 5 downto 4;
subtype rkcs_ibf_func is integer range 3 downto 1;
constant rkcs_ibf_go : integer := 0;
subtype rkda_ibf_drsel is integer range 15 downto 13;
subtype rkmr_ibf_rid is integer range 15 downto 13; -- rem id
constant rkmr_ibf_crdone: integer := 11; -- contr. reset done
constant rkmr_ibf_sbclr : integer := 10; -- clear sbusy's
constant rkmr_ibf_creset: integer := 9; -- control reset
constant rkmr_ibf_fdone : integer := 8; -- func done
subtype rkmr_ibf_sdone is integer range 7 downto 0; -- seek done
type state_type is (
s_idle,
s_init
);
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
state : state_type; -- state
id : slv3; -- rkds: drive id of search done
sc : slv4; -- rkds: sector counter
cse : slbit; -- rker: check sum error
wce : slbit; -- rker: write check error
he : slbit; -- rkcs: hard error
scp : slbit; -- rkcs: seek complete
maint : slbit; -- rkcs: maintenance mode
rdy : slbit; -- rkcs: control ready
ide : slbit; -- rkcs: interrupt on done enable
drsel : slv3; -- rkda: currently selected drive
fireq : slbit; -- func done interrupt request flag
sireq : slv8; -- seek done interrupt request flags
sbusy : slv8; -- seek busy flags
rid : slv3; -- drive id for rem ds reads
icnt : slv3; -- init state counter
creset : slbit; -- control reset flag
crdone : slbit; -- control reset done since last fdone
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
s_init, -- state
(others=>'0'), -- id
(others=>'0'), -- sc
'0','0', -- cse, wce
'0','0','0', -- he, scp, maint
'1', -- rdy (SET TO 1)
'0', -- ide
(others=>'0'), -- drsel
'0', -- fireq
(others=>'0'), -- sireq
(others=>'0'), -- sbusy
(others=>'0'), -- rid
(others=>'0'), -- icnt
'0','1' -- creset, crdone
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal MEM_1_WE : slbit := '0';
signal MEM_0_WE : slbit := '0';
signal MEM_ADDR : slv4 := (others=>'0');
signal MEM_DIN : slv16 := (others=>'0');
signal MEM_DOUT : slv16 := (others=>'0');
begin
MEM_1 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_1_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte1),
DO => MEM_DOUT(ibf_byte1));
MEM_0 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_0_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte0),
DO => MEM_DOUT(ibf_byte0));
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET='1' or R_REGS.creset='1' then
R_REGS <= regs_init;
if R_REGS.creset = '1' then
R_REGS.sbusy <= N_REGS.sbusy;
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable icrip : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibrem : slbit := '0';
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ibwrem : slbit := '0';
variable ilam : slbit := '0';
variable iscval : slbit := '0';
variable iscid : slv3 := (others=>'0');
variable iei_req : slbit := '0';
variable imem_we0 : slbit := '0';
variable imem_we1 : slbit := '0';
variable imem_addr : slv4 := (others=>'0');
variable imem_din : slv16 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
icrip := '0';
idout := (others=>'0');
ibrem := IB_MREQ.racc or r.maint;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ibwrem := IB_MREQ.we and ibrem;
ilam := '0';
iscval := '0';
iscid := (others=>'0');
iei_req := '0';
imem_we0 := '0';
imem_we1 := '0';
imem_addr := '0' & IB_MREQ.addr(3 downto 1);
imem_din := IB_MREQ.din;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval = '1' and
IB_MREQ.addr(12 downto 4)=ibaddr_rk11(12 downto 4) then
n.ibsel := '1';
end if;
-- internal state machine (for control reset)
case r.state is
when s_idle =>
null;
when s_init =>
ibhold := r.ibsel; -- hold ibus when controller busy
icrip := '1';
n.icnt := slv(unsigned(r.icnt) + 1);
if unsigned(r.icnt) = 7 then
n.state := s_idle;
end if;
when others => null;
end case;
-- ibus transactions
if r.ibsel='1' and ibhold='0' then -- selected and not holding
idout := MEM_DOUT;
imem_we0 := ibw0;
imem_we1 := ibw1;
case IB_MREQ.addr(3 downto 1) is
when ibaddr_rkds => -- RKDS -- drive status register ----
if ibrem = '0' then
imem_addr := '1' & r.drsel; -- loc read ds data: drsel as addr.
else
imem_addr := '1' & r.rid; -- rem read ds data: rid as addr.
end if;
idout(rkds_ibf_id) := r.id;
if ibrem = '0' then -- loc ? simulate drive sector monitor
if r.sc = MEM_DOUT(rkds_ibf_sc) then
idout(rkds_ibf_scsa) := '1';
else
idout(rkds_ibf_scsa) := '0';
end if;
idout(rkds_ibf_sc) := r.sc;
end if;
if r.sbusy(to_integer(unsigned(imem_addr(2 downto 0))))='1' then
idout(rkds_ibf_adry) := '0'; -- clear drive access rdy
end if;
if ibwrem = '1' then -- rem write ? than update ds data
imem_addr := '1' & IB_MREQ.din(rkds_ibf_id); -- use id field as addr
else -- loc write ?
imem_we0 := '0'; -- suppress we, is read-only
imem_we1 := '0';
end if;
when ibaddr_rker => -- RKER -- error register ------------
idout(4 downto 2) := (others=>'0'); -- unassigned bits
idout(rker_ibf_cse) := r.cse; -- use state bits (cleared at go !)
idout(rker_ibf_wce) := r.wce;
if ibwrem = '1' then -- rem write ?
if unsigned(IB_MREQ.din(rker_ibf_he)) /= 0 then -- hard errors set ?
n.he := '1';
else
n.he := '0';
end if;
n.cse := IB_MREQ.din(rker_ibf_cse); -- mirror cse bit
n.wce := IB_MREQ.din(rker_ibf_wce); -- mirror wce bit
else -- loc write ?
imem_we0 := '0'; -- suppress we, is read-only
imem_we1 := '0';
end if;
when ibaddr_rkcs => -- RKCS -- control status register ---
idout(rkcs_ibf_err) := r.he or r.cse or r.wce;
idout(rkcs_ibf_he) := r.he;
idout(rkcs_ibf_scp) := r.scp;
idout(rkcs_ibf_rdy) := r.rdy;
idout(rkcs_ibf_go) := not r.rdy;
if ibw1 = '1' then
n.maint := IB_MREQ.din(rkcs_ibf_maint); -- mirror maint bit
end if;
if ibw0 = '1' then
n.ide := IB_MREQ.din(rkcs_ibf_ide); -- mirror ide bit
if n.ide = '0' then -- if IE 0 or set to 0
n.fireq := '0'; -- cancel all pending
n.sireq := (others=>'0'); -- interrupt requests
end if;
if IB_MREQ.din(rkcs_ibf_go) = '1' then -- GO=1 ?
if r.rdy = '1' then -- ready and GO ?
n.scp := '0'; -- go clears scp !
n.rdy := '0'; -- mark busy
n.cse := '0'; -- clear soft errors
n.wce := '0';
n.fireq := '0'; -- cancel pend. int
if unsigned(IB_MREQ.din(rkcs_ibf_func))=0 then -- control reset?
n.creset := '1'; -- handle locally
else
ilam := '1'; -- issue lam
end if;
if unsigned(IB_MREQ.din(rkcs_ibf_func))=4 or -- if seek
unsigned(IB_MREQ.din(rkcs_ibf_func))=6 then -- or drive reset
n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- set busy
end if;
end if;
else -- GO=0
if r.ide = '0' and -- if ide now 0
IB_MREQ.din(rkcs_ibf_ide)='1' and -- and is set to 1
r.rdy='1' then -- and controller ready
n.fireq := '1'; -- issue interrupt
end if;
end if;
end if;
when ibaddr_rkda => -- RKDA -- disk address register -----
if ibrem = '0' then -- loc access ?
if r.rdy = '0' then -- controller busy ?
imem_we0 := '0'; -- suppress write
imem_we1 := '0';
end if;
end if;
if imem_we1 = '1' then
n.drsel := IB_MREQ.din(rkda_ibf_drsel); -- mirror drsel bits
end if;
when ibaddr_rkmr => -- RKMR -- maintenance register ------
idout := (others=>'0');
idout(rkmr_ibf_rid) := r.rid;
idout(rkmr_ibf_crdone) := r.crdone;
idout(rkmr_ibf_sdone) := r.sbusy;
if ibwrem = '1' then -- rem write ?
n.rid := IB_MREQ.din(rkmr_ibf_rid);
if r.ide='1' and IB_MREQ.din(rkmr_ibf_sbclr)='0' then
n.sireq := r.sireq or (IB_MREQ.din(rkmr_ibf_sdone) and r.sbusy);
end if;
n.sbusy := r.sbusy and not IB_MREQ.din(rkmr_ibf_sdone);
if IB_MREQ.din(rkmr_ibf_fdone) = '1' then -- func completed
n.rdy := '1';
n.crdone := '0';
if r.ide = '1' then
n.fireq := '1';
end if;
end if;
if IB_MREQ.din(rkmr_ibf_creset) = '1' then -- control reset
n.creset := '1';
end if;
end if;
when others => -- all other regs
null;
end case;
end if;
iscval := '1';
if r.sireq(7) = '1' then iscid := "111";
elsif r.sireq(6) = '1' then iscid := "110";
elsif r.sireq(5) = '1' then iscid := "101";
elsif r.sireq(4) = '1' then iscid := "100";
elsif r.sireq(3) = '1' then iscid := "011";
elsif r.sireq(2) = '1' then iscid := "010";
elsif r.sireq(1) = '1' then iscid := "001";
elsif r.sireq(0) = '1' then iscid := "000";
else
iscval := '0';
end if;
if r.ide = '1' then
if r.fireq='1' or iscval='1' then
iei_req := '1';
end if;
end if;
if EI_ACK = '1' then -- interrupt executed
if r.fireq = '1' then
n.scp := '0'; -- clear scp flag, is command end
n.fireq := '0';
elsif iscval = '1' then -- was a seek done
n.scp := '1'; -- signal seek complete interrupt
n.id := iscid; -- load id
n.sireq(to_integer(unsigned(iscid))) := '0'; -- reset sireq bit
end if;
end if;
if icrip = '1' then -- control reset in progress ?
imem_addr := '0' & r.icnt; -- use icnt as addr
imem_din := (others=>'0'); -- force data to zero
imem_we0 := '1'; -- enable writes
imem_we1 := '1';
end if;
if CE_MSEC = '1' then -- advance sector counter every msec
if unsigned(r.sc) = 8#13# then -- sector counter (count to 8#13#)
n.sc := (others=>'0');
else
n.sc := slv(unsigned(r.sc) + 1);
end if;
end if;
N_REGS <= n;
MEM_0_WE <= imem_we0;
MEM_1_WE <= imem_we1;
MEM_ADDR <= imem_addr;
MEM_DIN <= imem_din;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
RB_LAM <= ilam;
EI_REQ <= iei_req;
end process proc_next;
end syn;
|
-- $Id: ibdr_rk11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_rk11 - syn
-- Description: ibus dev(rem): RK11-A/B
--
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 46 248 16 137 s 7.2
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-05-24 219 1.0.9 add CE_MSEC input; inc sector counter every msec
-- BUGFIX: sector counter now counts 000,...,013.
-- 2009-05-21 217 1.0.8 cancel pending interrupt requests when IE=0
-- 2009-05-16 216 1.0.7 BUGFIX: correct interrupt on IE 0->1 logic
-- BUGFIX: re-work the seek complete handling
-- 2008-08-22 161 1.0.6 use iblib
-- 2008-05-30 151 1.0.5 BUGFIX: do control reset locally now, add CRDONE
-- 2008-03-30 131 1.0.4 issue interrupt when IDE bit set with GO=0
-- 2008-02-23 118 1.0.3 remove redundant condition in rkda access code
-- fix bug in control reset logic (we's missing)
-- 2008-01-20 113 1.0.2 Fix busy handling when control reset done
-- 2008-01-20 112 1.0.1 Fix scp handling; use BRESET
-- 2008-01-06 111 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_rk11 is -- ibus dev(rem): RK11
-- fixed address: 177400
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_rk11;
architecture syn of ibdr_rk11 is
constant ibaddr_rk11 : slv16 := slv(to_unsigned(8#177400#,16));
constant ibaddr_rkds : slv3 := "000"; -- rkds address offset
constant ibaddr_rker : slv3 := "001"; -- rker address offset
constant ibaddr_rkcs : slv3 := "010"; -- rkcs address offset
constant ibaddr_rkwc : slv3 := "011"; -- rkwc address offset
constant ibaddr_rkba : slv3 := "100"; -- rkba address offset
constant ibaddr_rkda : slv3 := "101"; -- rkda address offset
constant ibaddr_rkmr : slv3 := "110"; -- rkmr address offset
constant ibaddr_rkdb : slv3 := "111"; -- rkdb address offset
subtype rkds_ibf_id is integer range 15 downto 13;
constant rkds_ibf_adry : integer := 6;
constant rkds_ibf_scsa : integer := 4;
subtype rkds_ibf_sc is integer range 3 downto 0;
subtype rker_ibf_he is integer range 15 downto 5;
constant rker_ibf_cse : integer := 1;
constant rker_ibf_wce : integer := 0;
constant rkcs_ibf_err : integer := 15;
constant rkcs_ibf_he : integer := 14;
constant rkcs_ibf_scp : integer := 13;
constant rkcs_ibf_maint : integer := 12;
constant rkcs_ibf_rdy : integer := 7;
constant rkcs_ibf_ide : integer := 6;
subtype rkcs_ibf_mex is integer range 5 downto 4;
subtype rkcs_ibf_func is integer range 3 downto 1;
constant rkcs_ibf_go : integer := 0;
subtype rkda_ibf_drsel is integer range 15 downto 13;
subtype rkmr_ibf_rid is integer range 15 downto 13; -- rem id
constant rkmr_ibf_crdone: integer := 11; -- contr. reset done
constant rkmr_ibf_sbclr : integer := 10; -- clear sbusy's
constant rkmr_ibf_creset: integer := 9; -- control reset
constant rkmr_ibf_fdone : integer := 8; -- func done
subtype rkmr_ibf_sdone is integer range 7 downto 0; -- seek done
type state_type is (
s_idle,
s_init
);
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
state : state_type; -- state
id : slv3; -- rkds: drive id of search done
sc : slv4; -- rkds: sector counter
cse : slbit; -- rker: check sum error
wce : slbit; -- rker: write check error
he : slbit; -- rkcs: hard error
scp : slbit; -- rkcs: seek complete
maint : slbit; -- rkcs: maintenance mode
rdy : slbit; -- rkcs: control ready
ide : slbit; -- rkcs: interrupt on done enable
drsel : slv3; -- rkda: currently selected drive
fireq : slbit; -- func done interrupt request flag
sireq : slv8; -- seek done interrupt request flags
sbusy : slv8; -- seek busy flags
rid : slv3; -- drive id for rem ds reads
icnt : slv3; -- init state counter
creset : slbit; -- control reset flag
crdone : slbit; -- control reset done since last fdone
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
s_init, -- state
(others=>'0'), -- id
(others=>'0'), -- sc
'0','0', -- cse, wce
'0','0','0', -- he, scp, maint
'1', -- rdy (SET TO 1)
'0', -- ide
(others=>'0'), -- drsel
'0', -- fireq
(others=>'0'), -- sireq
(others=>'0'), -- sbusy
(others=>'0'), -- rid
(others=>'0'), -- icnt
'0','1' -- creset, crdone
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal MEM_1_WE : slbit := '0';
signal MEM_0_WE : slbit := '0';
signal MEM_ADDR : slv4 := (others=>'0');
signal MEM_DIN : slv16 := (others=>'0');
signal MEM_DOUT : slv16 := (others=>'0');
begin
MEM_1 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_1_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte1),
DO => MEM_DOUT(ibf_byte1));
MEM_0 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_0_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte0),
DO => MEM_DOUT(ibf_byte0));
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET='1' or R_REGS.creset='1' then
R_REGS <= regs_init;
if R_REGS.creset = '1' then
R_REGS.sbusy <= N_REGS.sbusy;
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable icrip : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibrem : slbit := '0';
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ibwrem : slbit := '0';
variable ilam : slbit := '0';
variable iscval : slbit := '0';
variable iscid : slv3 := (others=>'0');
variable iei_req : slbit := '0';
variable imem_we0 : slbit := '0';
variable imem_we1 : slbit := '0';
variable imem_addr : slv4 := (others=>'0');
variable imem_din : slv16 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
icrip := '0';
idout := (others=>'0');
ibrem := IB_MREQ.racc or r.maint;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ibwrem := IB_MREQ.we and ibrem;
ilam := '0';
iscval := '0';
iscid := (others=>'0');
iei_req := '0';
imem_we0 := '0';
imem_we1 := '0';
imem_addr := '0' & IB_MREQ.addr(3 downto 1);
imem_din := IB_MREQ.din;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval = '1' and
IB_MREQ.addr(12 downto 4)=ibaddr_rk11(12 downto 4) then
n.ibsel := '1';
end if;
-- internal state machine (for control reset)
case r.state is
when s_idle =>
null;
when s_init =>
ibhold := r.ibsel; -- hold ibus when controller busy
icrip := '1';
n.icnt := slv(unsigned(r.icnt) + 1);
if unsigned(r.icnt) = 7 then
n.state := s_idle;
end if;
when others => null;
end case;
-- ibus transactions
if r.ibsel='1' and ibhold='0' then -- selected and not holding
idout := MEM_DOUT;
imem_we0 := ibw0;
imem_we1 := ibw1;
case IB_MREQ.addr(3 downto 1) is
when ibaddr_rkds => -- RKDS -- drive status register ----
if ibrem = '0' then
imem_addr := '1' & r.drsel; -- loc read ds data: drsel as addr.
else
imem_addr := '1' & r.rid; -- rem read ds data: rid as addr.
end if;
idout(rkds_ibf_id) := r.id;
if ibrem = '0' then -- loc ? simulate drive sector monitor
if r.sc = MEM_DOUT(rkds_ibf_sc) then
idout(rkds_ibf_scsa) := '1';
else
idout(rkds_ibf_scsa) := '0';
end if;
idout(rkds_ibf_sc) := r.sc;
end if;
if r.sbusy(to_integer(unsigned(imem_addr(2 downto 0))))='1' then
idout(rkds_ibf_adry) := '0'; -- clear drive access rdy
end if;
if ibwrem = '1' then -- rem write ? than update ds data
imem_addr := '1' & IB_MREQ.din(rkds_ibf_id); -- use id field as addr
else -- loc write ?
imem_we0 := '0'; -- suppress we, is read-only
imem_we1 := '0';
end if;
when ibaddr_rker => -- RKER -- error register ------------
idout(4 downto 2) := (others=>'0'); -- unassigned bits
idout(rker_ibf_cse) := r.cse; -- use state bits (cleared at go !)
idout(rker_ibf_wce) := r.wce;
if ibwrem = '1' then -- rem write ?
if unsigned(IB_MREQ.din(rker_ibf_he)) /= 0 then -- hard errors set ?
n.he := '1';
else
n.he := '0';
end if;
n.cse := IB_MREQ.din(rker_ibf_cse); -- mirror cse bit
n.wce := IB_MREQ.din(rker_ibf_wce); -- mirror wce bit
else -- loc write ?
imem_we0 := '0'; -- suppress we, is read-only
imem_we1 := '0';
end if;
when ibaddr_rkcs => -- RKCS -- control status register ---
idout(rkcs_ibf_err) := r.he or r.cse or r.wce;
idout(rkcs_ibf_he) := r.he;
idout(rkcs_ibf_scp) := r.scp;
idout(rkcs_ibf_rdy) := r.rdy;
idout(rkcs_ibf_go) := not r.rdy;
if ibw1 = '1' then
n.maint := IB_MREQ.din(rkcs_ibf_maint); -- mirror maint bit
end if;
if ibw0 = '1' then
n.ide := IB_MREQ.din(rkcs_ibf_ide); -- mirror ide bit
if n.ide = '0' then -- if IE 0 or set to 0
n.fireq := '0'; -- cancel all pending
n.sireq := (others=>'0'); -- interrupt requests
end if;
if IB_MREQ.din(rkcs_ibf_go) = '1' then -- GO=1 ?
if r.rdy = '1' then -- ready and GO ?
n.scp := '0'; -- go clears scp !
n.rdy := '0'; -- mark busy
n.cse := '0'; -- clear soft errors
n.wce := '0';
n.fireq := '0'; -- cancel pend. int
if unsigned(IB_MREQ.din(rkcs_ibf_func))=0 then -- control reset?
n.creset := '1'; -- handle locally
else
ilam := '1'; -- issue lam
end if;
if unsigned(IB_MREQ.din(rkcs_ibf_func))=4 or -- if seek
unsigned(IB_MREQ.din(rkcs_ibf_func))=6 then -- or drive reset
n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- set busy
end if;
end if;
else -- GO=0
if r.ide = '0' and -- if ide now 0
IB_MREQ.din(rkcs_ibf_ide)='1' and -- and is set to 1
r.rdy='1' then -- and controller ready
n.fireq := '1'; -- issue interrupt
end if;
end if;
end if;
when ibaddr_rkda => -- RKDA -- disk address register -----
if ibrem = '0' then -- loc access ?
if r.rdy = '0' then -- controller busy ?
imem_we0 := '0'; -- suppress write
imem_we1 := '0';
end if;
end if;
if imem_we1 = '1' then
n.drsel := IB_MREQ.din(rkda_ibf_drsel); -- mirror drsel bits
end if;
when ibaddr_rkmr => -- RKMR -- maintenance register ------
idout := (others=>'0');
idout(rkmr_ibf_rid) := r.rid;
idout(rkmr_ibf_crdone) := r.crdone;
idout(rkmr_ibf_sdone) := r.sbusy;
if ibwrem = '1' then -- rem write ?
n.rid := IB_MREQ.din(rkmr_ibf_rid);
if r.ide='1' and IB_MREQ.din(rkmr_ibf_sbclr)='0' then
n.sireq := r.sireq or (IB_MREQ.din(rkmr_ibf_sdone) and r.sbusy);
end if;
n.sbusy := r.sbusy and not IB_MREQ.din(rkmr_ibf_sdone);
if IB_MREQ.din(rkmr_ibf_fdone) = '1' then -- func completed
n.rdy := '1';
n.crdone := '0';
if r.ide = '1' then
n.fireq := '1';
end if;
end if;
if IB_MREQ.din(rkmr_ibf_creset) = '1' then -- control reset
n.creset := '1';
end if;
end if;
when others => -- all other regs
null;
end case;
end if;
iscval := '1';
if r.sireq(7) = '1' then iscid := "111";
elsif r.sireq(6) = '1' then iscid := "110";
elsif r.sireq(5) = '1' then iscid := "101";
elsif r.sireq(4) = '1' then iscid := "100";
elsif r.sireq(3) = '1' then iscid := "011";
elsif r.sireq(2) = '1' then iscid := "010";
elsif r.sireq(1) = '1' then iscid := "001";
elsif r.sireq(0) = '1' then iscid := "000";
else
iscval := '0';
end if;
if r.ide = '1' then
if r.fireq='1' or iscval='1' then
iei_req := '1';
end if;
end if;
if EI_ACK = '1' then -- interrupt executed
if r.fireq = '1' then
n.scp := '0'; -- clear scp flag, is command end
n.fireq := '0';
elsif iscval = '1' then -- was a seek done
n.scp := '1'; -- signal seek complete interrupt
n.id := iscid; -- load id
n.sireq(to_integer(unsigned(iscid))) := '0'; -- reset sireq bit
end if;
end if;
if icrip = '1' then -- control reset in progress ?
imem_addr := '0' & r.icnt; -- use icnt as addr
imem_din := (others=>'0'); -- force data to zero
imem_we0 := '1'; -- enable writes
imem_we1 := '1';
end if;
if CE_MSEC = '1' then -- advance sector counter every msec
if unsigned(r.sc) = 8#13# then -- sector counter (count to 8#13#)
n.sc := (others=>'0');
else
n.sc := slv(unsigned(r.sc) + 1);
end if;
end if;
N_REGS <= n;
MEM_0_WE <= imem_we0;
MEM_1_WE <= imem_we1;
MEM_ADDR <= imem_addr;
MEM_DIN <= imem_din;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
RB_LAM <= ilam;
EI_REQ <= iei_req;
end process proc_next;
end syn;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.